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!arch/stm32wl5: use common STM32 Kconfig symbols

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BREAKING CHANGE: STM32WL5 Kconfig symbols were renamed from CONFIG_STM32WL5_* to CONFIG_STM32_*.
Out-of-tree code must update defconfigs and Kconfig references to the new CONFIG_STM32_* names.

Signed-off-by: raiden00pl <raiden00@railab.me>
This commit is contained in:
raiden00pl 2026-05-28 14:28:43 +02:00 • committed by Xiang Xiao
parent 2379454ca8
commit fa8d14eb9b
30 changed files with 427 additions and 779 deletions
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1
arch/arm/Kconfig
View file

@ -664,6 +664,7 @@ config ARCH_CHIP_STM32WB
config ARCH_CHIP_STM32WL5
bool "STMicro STM32 WL5"
select ARCH_CHIP_STM32
select ARCH_CORTEXM4
select ARCH_HAVE_MPU
select ARCH_HAVE_FETCHADD

6
arch/arm/include/stm32wl5/chip.h
View file

@ -33,14 +33,14 @@
* Pre-processor Prototypes
****************************************************************************/
#if defined(CONFIG_STM32WL5_STM32WL5XXX)
#if defined(CONFIG_STM32_STM32WL5XXX)
# define STM32_SRAM1_SIZE (32*1024) /* 32kB SRAM1 on AHB bus Matrix */
# define STM32_SRAM2_SIZE (32*1024) /* 32kB SRAM2 on AHB bus Matrix */
#else
# error "Unsupported STM32L5 chip"
#endif
#if defined(CONFIG_STM32WL5_STM32WL5XXX_CPU1)
#if defined(CONFIG_STM32_STM32WL5XXX_CPU1)
# define STM32_NATIM 1 /* One advanced timer TIM1 */
# define STM32_NGTIM32 1 /* 32-bit general timer TIM2 with DMA */
# define STM32_NGTIM16 2 /* 16-bit general timers TIM16 and 17 with DMA */
@ -56,7 +56,7 @@
# define STM32_NDAC 1 /* DAC1 */
# define STM32_NCRC 1 /* CRC1 */
# define STM32_NCOMP 1 /* COMP1 */
#endif /* CONFIG_STM32WL5_STM32WL5XXX */
#endif /* CONFIG_STM32_STM32WL5XXX */
/* NVIC priority levels *****************************************************/

2
arch/arm/include/stm32wl5/irq.h
View file

@ -69,7 +69,7 @@
* Included Files
****************************************************************************/
#if defined(CONFIG_STM32WL5_STM32WL5XXX_CPU1)
#if defined(CONFIG_STM32_STM32WL5XXX_CPU1)
# include <arch/stm32wl5/stm32wl5xxx_cpu1_irq.h>
#else
# error "Unsupported STM32 L5 chip"

2
arch/arm/src/stm32wl5/CMakeLists.txt
View file

@ -42,7 +42,7 @@ set(SRCS
stm32wl5_timerisr.c
stm32wl5_spi.c)
if(CONFIG_STM32WL5_IPCC)
if(CONFIG_STM32_IPCC)
list(APPEND SRCS stm32wl5_ipcc.c)
endif()

394
arch/arm/src/stm32wl5/Kconfig
View file

@ -7,6 +7,12 @@ if ARCH_CHIP_STM32WL5
comment "STM32WL5 Configuration Options"
config STM32_WL5_PERIPHERALS
bool
default ARCH_CHIP_STM32WL5
select STM32_HAVE_SYSCFG
select STM32_HAVE_IPCC
choice
prompt "STM32 WL5 Chip Selection"
default ARCH_CHIP_STM32WL55JC_CPU1
@ -14,396 +20,34 @@ choice
config ARCH_CHIP_STM32WL55JC_CPU1
bool "STM32WL55JC (cpu1)"
select STM32WL5_STM32WL5XXX_CPU1
select STM32WL5_STM32WL5XXX
select STM32WL5_FLASH_CONFIG_C
select STM32_STM32WL5XXX_CPU1
select STM32_STM32WL5XXX
select STM32_FLASH_CONFIG_C
---help---
STM32 WL5 Cortex M4 (cpu1), 256kiB FLASH, 64kiB SRAM
config ARCH_CHIP_STM32WL55JC_CPU2
bool "STM32WL55JC (cpu2)"
select STM32WL5_STM32WL5XXX_CPU2
select STM32WL5_STM32WL5XXX
select STM32WL5_FLASH_CONFIG_C
select STM32_STM32WL5XXX_CPU2
select STM32_STM32WL5XXX
select STM32_FLASH_CONFIG_C
---help---
STM32 WL5 Cortex M0 (cpu2), 256kiB FLASH, 64kiB SRAM
endchoice # STM32 WL5 Chip Selection
# Chip product lines
config STM32WL5_STM32WL5XXX
config STM32_STM32WL5XXX
bool
config STM32WL5_STM32WL5XXX_CPU1
config STM32_STM32WL5XXX_CPU1
bool
default y
select STM32WL5_HAVE_USART1
select STM32WL5_HAVE_USART2
select STM32WL5_HAVE_LPUART1
select STM32WL5_HAVE_SPI1
select STM32WL5_HAVE_SPI2S2
comment "STM32WL5 Peripherals"
menu "STM32WL5 Peripheral Support"
choice
prompt "Override Flash Size Designator"
depends on ARCH_CHIP_STM32WL5
default STM32WL5_FLASH_OVERRIDE_DEFAULT
---help---
STM32WL5 series parts numbering (sans the package type) ends with a letter
that designates the FLASH size.
Designator Size in KiB
8 64
B 128
C 256
E 512
G 1024
I 2048
This configuration option defaults to using the configuration based on that designator
or the default smaller size if there is no last character designator is present in the
STM32 Chip Selection.
Examples:
If the STM32WL55JC is chosen, the Flash configuration would be 'C', if a variant of
the part with a 1024 KiB Flash is released in the future one could simply select
the 'G' designator here.
If an STM32WL5xxx Series parts is chosen the default Flash configuration will be set
herein and can be changed.
config STM32WL5_FLASH_OVERRIDE_DEFAULT
bool "Default"
config STM32WL5_FLASH_OVERRIDE_8
bool "8 64 KB"
config STM32WL5_FLASH_OVERRIDE_B
bool "B 128 KB"
config STM32WL5_FLASH_OVERRIDE_C
bool "C 256 KB"
config STM32WL5_FLASH_OVERRIDE_E
bool "E 512 KB"
config STM32WL5_FLASH_OVERRIDE_G
bool "G 1024 KB"
endchoice # "Override Flash Size Designator"
# Flash configurations
config STM32WL5_FLASH_CONFIG_8
bool
default n
config STM32WL5_FLASH_CONFIG_B
bool
default n
config STM32WL5_FLASH_CONFIG_C
bool
default n
config STM32WL5_FLASH_CONFIG_E
bool
default n
config STM32WL5_FLASH_CONFIG_G
bool
default n
# These "hidden" settings determine whether a peripheral option is available
# for the selected MCU
config STM32WL5_HAVE_USART1
bool
default n
config STM32WL5_HAVE_USART2
bool
default n
config STM32WL5_HAVE_LPUART1
bool
default n
config STM32WL5_HAVE_SPI1
bool
default n
config STM32WL5_HAVE_SPI2S2
bool
default n
# These "hidden" settings are the OR of individual peripheral selections
# indicating that the general capability is required.
config STM32WL5_USART
bool
default n
config STM32WL5_SPI
bool
default n
config STM32WL5_SPI_DMA
bool
default n
# These are the peripheral selections proper
comment "APB1 Peripherals"
config STM32WL5_USART2
bool "USART2"
default n
depends on STM32WL5_HAVE_USART2
select ARCH_HAVE_SERIAL_TERMIOS
select STM32WL5_USART
config STM32WL5_LPUART1
bool "LPUART1"
default n
depends on STM32WL5_HAVE_LPUART1
select ARCH_HAVE_SERIAL_TERMIOS
select STM32WL5_USART
config STM32WL5_SPI2S2
bool "SPI2S2"
default n
depends on STM32WL5_HAVE_SPI2S2
select STM32WL5_SPI
comment "APB2 Peripherals"
config STM32WL5_SYSCFG
bool "SYSCFG"
default y
config STM32WL5_USART1
bool "USART1"
default n
depends on STM32WL5_HAVE_USART1
select ARCH_HAVE_SERIAL_TERMIOS
select STM32WL5_USART
config STM32WL5_SPI1
bool "SPI1"
default n
depends on STM32WL5_HAVE_SPI1
select STM32WL5_SPI
comment "AHB3 Peripherals"
config STM32WL5_IPCC
bool "IPCC"
select IPCC
default n
---help---
IPCC - Inter Processor Communication Controller. A very simple
character device stream driver to exchange data between
CM0 and CM4.
endmenu # STM32WL5 Peripheral Support
config STM32WL5_SERIALDRIVER
bool
menu "[LP]U[S]ART Configuration"
depends on STM32WL5_USART
choice
prompt "USART1 Driver Configuration"
default STM32WL5_USART1_SERIALDRIVER
depends on STM32WL5_USART1
config STM32WL5_USART1_SERIALDRIVER
bool "Standard serial driver"
select USART1_SERIALDRIVER
select STM32WL5_SERIALDRIVER
endchoice # USART1 Driver Configuration
choice
prompt "USART2 Driver Configuration"
default STM32WL5_USART2_SERIALDRIVER
depends on STM32WL5_USART2
config STM32WL5_USART2_SERIALDRIVER
bool "Standard serial driver"
select USART2_SERIALDRIVER
select STM32WL5_SERIALDRIVER
endchoice # USART2 Driver Configuration
choice
prompt "LPUART1 Driver Configuration"
default STM32WL5_LPUART1_SERIALDRIVER
depends on STM32WL5_LPUART1
config STM32WL5_LPUART1_SERIALDRIVER
bool "Standard serial driver"
select LPUART1_SERIALDRIVER
select STM32WL5_SERIALDRIVER
endchoice # LPUART1 Driver Configuration
endmenu # [LP]U[S]ART Configuration
menu "SPI Configuration"
depends on STM32WL5_SPI
config STM32WL5_SPI_INTERRUPTS
bool "Interrupt driver SPI"
default n
---help---
Select to enable interrupt driven SPI support. Non-interrupt-driven,
poll-waiting is recommended if the interrupt rate would be to high in
the interrupt driven case.
config STM32WL5_SPI1_DMA
bool "SPI1 DMA"
default n
depends on STM32WL5_SPI1 && !STM32WL5_SPI_INTERRUPT
select STM32WL5_SPI_DMA
---help---
Use DMA to improve SPI1 transfer performance. Cannot be used with STM32WL5_SPI_INTERRUPT.
config STM32WL5_SPI1_DMA_BUFFER
int "SPI1 DMA buffer size"
default 0
depends on STM32WL5_SPI1_DMA
---help---
Add a properly aligned DMA buffer for RX and TX DMA for SPI1.
config STM32WL5_SPI_DMATHRESHOLD
int "SPI DMA threshold"
default 4
depends on STM32WL5_SPI_DMA
---help---
When SPI DMA is enabled, small DMA transfers will still be performed
by polling logic. But we need a threshold value to determine what
is small.
config STM32WL5_SPI2S2_DMA
bool "SPI2S2 DMA"
default n
depends on STM32WL5_SPI2 && !STM32WL5_SPI_INTERRUPT
select STM32WL5_SPI_DMA
---help---
Use DMA to improve SPI2S2 transfer performance. Cannot be used with STM32WL5_SPI_INTERRUPT.
config STM32WL5_SPI2S2_DMA_BUFFER
int "SPI2S2 DMA buffer size"
default 0
depends on STM32WL5_SPI2S2_DMA
---help---
Add a properly aligned DMA buffer for RX and TX DMA for SPI2S2.
endmenu # SPI Configuration
menu "IPCC Configuration"
depends on STM32WL5_IPCC
config STM32WL5_IPCC_CHAN1_RX_SIZE
int "Channel 1 RX size"
default 256
---help---
Size of the receive buffer. Another CPU will write to this
buffer and currently running CPU will read from it.
config STM32WL5_IPCC_CHAN1_TX_SIZE
int "Channel 1 TX size"
default 256
---help---
Size of the send buffer. Another CPU will read from this
buffer and currently running CPU will write to it.
config STM32WL5_IPCC_CHAN2
bool "Enable channel 2"
default n
if STM32WL5_IPCC_CHAN2
config STM32WL5_IPCC_CHAN2_RX_SIZE
int "Channel 2 RX size"
default 256
config STM32WL5_IPCC_CHAN2_TX_SIZE
int "Channel 2 TX size"
default 256
config STM32WL5_IPCC_CHAN3
bool "Enable channel 3"
default n
if STM32WL5_IPCC_CHAN3
config STM32WL5_IPCC_CHAN3_RX_SIZE
int "Channel 3 RX size"
default 256
config STM32WL5_IPCC_CHAN3_TX_SIZE
int "Channel 3 TX size"
default 256
config STM32WL5_IPCC_CHAN4
bool "Enable channel 4"
default n
if STM32WL5_IPCC_CHAN4
config STM32WL5_IPCC_CHAN4_RX_SIZE
int "Channel 4 RX size"
default 256
config STM32WL5_IPCC_CHAN4_TX_SIZE
int "Channel 4 TX size"
default 256
config STM32WL5_IPCC_CHAN5
bool "Enable channel 5"
default n
if STM32WL5_IPCC_CHAN5
config STM32WL5_IPCC_CHAN5_RX_SIZE
int "Channel 5 RX size"
default 256
config STM32WL5_IPCC_CHAN5_TX_SIZE
int "Channel 5 TX size"
default 256
config STM32WL5_IPCC_CHAN6
bool "Enable channel 6"
default n
if STM32WL5_IPCC_CHAN6
config STM32WL5_IPCC_CHAN6_RX_SIZE
int "Channel 6 RX size"
default 256
config STM32WL5_IPCC_CHAN6_TX_SIZE
int "Channel 6 TX size"
default 256
endif # STM32WL5_IPCC_CHAN2
endif # STM32WL5_IPCC_CHAN3
endif # STM32WL5_IPCC_CHAN4
endif # STM32WL5_IPCC_CHAN5
endif # STM32WL5_IPCC_CHAN6
endmenu # IPCC Configuration
select STM32_HAVE_USART1
select STM32_HAVE_USART2
select STM32_HAVE_LPUART1
select STM32_HAVE_SPI1
select STM32_HAVE_SPI2S2
endif # ARCH_CHIP_STM32WL5

2
arch/arm/src/stm32wl5/Make.defs
View file

@ -36,6 +36,6 @@ CHIP_CSRCS += stm32wl5_lse.c stm32wl5_lsi.c stm32wl5_idle.c
CHIP_CSRCS += stm32wl5_pwr.c stm32wl5_tim.c stm32wl5_flash.c stm32wl5_timerisr.c
CHIP_CSRCS += stm32wl5_spi.c
CSRCS-$(CONFIG_STM32WL5_IPCC) = stm32wl5_ipcc.c
CSRCS-$(CONFIG_STM32_IPCC) = stm32wl5_ipcc.c
CHIP_CSRCS += $(CSRCS-y)

68
arch/arm/src/stm32wl5/hardware/stm32wl5_flash.h
View file

@ -35,7 +35,7 @@
/* Flash size is known from the chip selection:
*
* When CONFIG_STM32WL5_FLASH_OVERRIDE_DEFAULT is set the
* When CONFIG_STM32_FLASH_OVERRIDE_DEFAULT is set the
* CONFIG_STM32WL5_FLASH_CONFIG_x selects the default FLASH size based
* on the chip part number. This value can be overridden with
* CONFIG_STM32WL5_FLASH_OVERRIDE_x. For example:
@ -47,57 +47,57 @@
* STM32WL5xxx has only single bank flash and page size 2KiB
*/
#if !defined(CONFIG_STM32WL5_FLASH_OVERRIDE_DEFAULT) && \
!defined(CONFIG_STM32WL5_FLASH_OVERRIDE_8) && \
!defined(CONFIG_STM32WL5_FLASH_OVERRIDE_B) && \
!defined(CONFIG_STM32WL5_FLASH_OVERRIDE_C) && \
!defined(CONFIG_STM32WL5_FLASH_OVERRIDE_E) && \
!defined(CONFIG_STM32WL5_FLASH_OVERRIDE_G) && \
!defined(CONFIG_STM32WL5_FLASH_CONFIG_8) && \
!defined(CONFIG_STM32WL5_FLASH_CONFIG_B) && \
!defined(CONFIG_STM32WL5_FLASH_CONFIG_C) && \
!defined(CONFIG_STM32WL5_FLASH_CONFIG_E) && \
!defined(CONFIG_STM32WL5_FLASH_CONFIG_G)
# define CONFIG_STM32WL5_FLASH_OVERRIDE_E
#if !defined(CONFIG_STM32_FLASH_OVERRIDE_DEFAULT) && \
!defined(CONFIG_STM32_FLASH_OVERRIDE_8) && \
!defined(CONFIG_STM32_FLASH_OVERRIDE_B) && \
!defined(CONFIG_STM32_FLASH_OVERRIDE_C) && \
!defined(CONFIG_STM32_FLASH_OVERRIDE_E) && \
!defined(CONFIG_STM32_FLASH_OVERRIDE_G) && \
!defined(CONFIG_STM32_FLASH_CONFIG_8) && \
!defined(CONFIG_STM32_FLASH_CONFIG_B) && \
!defined(CONFIG_STM32_FLASH_CONFIG_C) && \
!defined(CONFIG_STM32_FLASH_CONFIG_E) && \
!defined(CONFIG_STM32_FLASH_CONFIG_G)
# define CONFIG_STM32_FLASH_OVERRIDE_E
# warning "Flash size not defined defaulting to 512KiB (E)"
#endif
/* Override of the Flash has been chosen */
#if !defined(CONFIG_STM32WL5_FLASH_OVERRIDE_DEFAULT)
# undef CONFIG_STM32WL5_FLASH_CONFIG_8
# undef CONFIG_STM32WL5_FLASH_CONFIG_B
# undef CONFIG_STM32WL5_FLASH_CONFIG_C
# undef CONFIG_STM32WL5_FLASH_CONFIG_E
# undef CONFIG_STM32WL5_FLASH_CONFIG_G
# if defined(CONFIG_STM32WL5_FLASH_OVERRIDE_8)
# define CONFIG_STM32WL5_FLASH_CONFIG_8
# elif defined(CONFIG_STM32WL5_FLASH_OVERRIDE_B)
# define CONFIG_STM32WL5_FLASH_CONFIG_B
# elif defined(CONFIG_STM32WL5_FLASH_OVERRIDE_C)
# define CONFIG_STM32WL5_FLASH_CONFIG_C
# elif defined(CONFIG_STM32WL5_FLASH_OVERRIDE_E)
# define CONFIG_STM32WL5_FLASH_CONFIG_E
# elif defined(CONFIG_STM32WL5_FLASH_OVERRIDE_G)
# define CONFIG_STM32WL5_FLASH_CONFIG_G
#if !defined(CONFIG_STM32_FLASH_OVERRIDE_DEFAULT)
# undef CONFIG_STM32_FLASH_CONFIG_8
# undef CONFIG_STM32_FLASH_CONFIG_B
# undef CONFIG_STM32_FLASH_CONFIG_C
# undef CONFIG_STM32_FLASH_CONFIG_E
# undef CONFIG_STM32_FLASH_CONFIG_G
# if defined(CONFIG_STM32_FLASH_OVERRIDE_8)
# define CONFIG_STM32_FLASH_CONFIG_8
# elif defined(CONFIG_STM32_FLASH_OVERRIDE_B)
# define CONFIG_STM32_FLASH_CONFIG_B
# elif defined(CONFIG_STM32_FLASH_OVERRIDE_C)
# define CONFIG_STM32_FLASH_CONFIG_C
# elif defined(CONFIG_STM32_FLASH_OVERRIDE_E)
# define CONFIG_STM32_FLASH_CONFIG_E
# elif defined(CONFIG_STM32_FLASH_OVERRIDE_G)
# define CONFIG_STM32_FLASH_CONFIG_G
# endif
#endif
/* Define the valid configuration */
#if defined(CONFIG_STM32WL5_FLASH_CONFIG_8) /* 64 kB */
#if defined(CONFIG_STM32_FLASH_CONFIG_8) /* 64 kB */
# define STM32_FLASH_NPAGES 32
# define STM32_FLASH_PAGESIZE 2048
#elif defined(CONFIG_STM32WL5_FLASH_CONFIG_B) /* 128 kB */
#elif defined(CONFIG_STM32_FLASH_CONFIG_B) /* 128 kB */
# define STM32_FLASH_NPAGES 64
# define STM32_FLASH_PAGESIZE 2048
#elif defined(CONFIG_STM32WL5_FLASH_CONFIG_C) /* 256 kB */
#elif defined(CONFIG_STM32_FLASH_CONFIG_C) /* 256 kB */
# define STM32_FLASH_NPAGES 128
# define STM32_FLASH_PAGESIZE 2048
#elif defined(CONFIG_STM32WL5_FLASH_CONFIG_E) /* 512 kB */
#elif defined(CONFIG_STM32_FLASH_CONFIG_E) /* 512 kB */
# define STM32_FLASH_NPAGES 256
# define STM32_FLASH_PAGESIZE 2048
#elif defined(CONFIG_STM32WL5_FLASH_CONFIG_G) /* 1 MB */
#elif defined(CONFIG_STM32_FLASH_CONFIG_G) /* 1 MB */
# define STM32_FLASH_NPAGES 512
# define STM32_FLASH_PAGESIZE 2048
#else

2
arch/arm/src/stm32wl5/hardware/stm32wl5_spi.h
View file

@ -74,7 +74,7 @@
/* Maximum allowed speed as per specifications for all SPIs */
#if defined(CONFIG_STM32WL5_STM32F4XXX)
#if defined(CONFIG_STM32_STM32F4XXX)
# define STM32_SPI_CLK_MAX 37500000UL
#else
# define STM32_SPI_CLK_MAX 18000000UL

6
arch/arm/src/stm32wl5/stm32wl5_allocateheap.c
View file

@ -83,11 +83,11 @@
* that we have been asked to add to the heap.
*/
#if CONFIG_MM_REGIONS < defined(CONFIG_STM32WL5_SRAM2_HEAP) + 1
#if CONFIG_MM_REGIONS < defined(CONFIG_STM32_SRAM2_HEAP) + 1
# error "You need more memory manager regions to support selected heap components"
#endif
#if CONFIG_MM_REGIONS > defined(CONFIG_STM32WL5_SRAM2_HEAP) + 1
#if CONFIG_MM_REGIONS > defined(CONFIG_STM32_SRAM2_HEAP) + 1
# warning "CONFIG_MM_REGIONS large enough but I do not know what some of the region(s) are"
#endif
@ -264,7 +264,7 @@ void up_allocate_kheap(void **heap_start, size_t *heap_size)
#if CONFIG_MM_REGIONS > 1
void arm_addregion(void)
{
#ifdef CONFIG_STM32WL5_SRAM2_HEAP
#ifdef CONFIG_STM32_SRAM2_HEAP
#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP)

2
arch/arm/src/stm32wl5/stm32wl5_exti.h
View file

@ -141,7 +141,7 @@ int stm32_exti_wakeup(bool risingedge, bool fallingedge, bool event,
*
****************************************************************************/
#ifdef CONFIG_STM32WL5_COMP
#ifdef CONFIG_STM32_COMP
int stm32_exti_comp(int cmp, bool risingedge, bool fallingedge,
bool event, xcpt_t func, void *arg);
#endif

2
arch/arm/src/stm32wl5/stm32wl5_flash.c
View file

@ -50,7 +50,7 @@
#include "stm32wl5_flash.h"
#include "arm_internal.h"
#if !defined(CONFIG_STM32WL5_FLASH_OVERRIDE_DEFAULT)
#if !defined(CONFIG_STM32_FLASH_OVERRIDE_DEFAULT)
# warning "Flash Configuration has been overridden - make sure it is correct"
#endif

2
arch/arm/src/stm32wl5/stm32wl5_gpio.h
View file

@ -39,7 +39,7 @@
#include "chip.h"
#if defined(CONFIG_STM32WL5_STM32WL5XXX)
#if defined(CONFIG_STM32_STM32WL5XXX)
# include "hardware/stm32wl5_gpio.h"
#else
# error "Unsupported STM32WL5 chip"

2
arch/arm/src/stm32wl5/stm32wl5_idle.c
View file

@ -88,7 +88,7 @@ void up_idle(void)
/* Sleep until an interrupt occurs to save power. */
#if !(defined(CONFIG_DEBUG_SYMBOLS) && defined(CONFIG_STM32WL5_DISABLE_IDLE_SLEEP_DURING_DEBUG))
#if !(defined(CONFIG_DEBUG_SYMBOLS) && defined(CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG))
BEGIN_IDLE();
asm("WFI");
END_IDLE();

34
arch/arm/src/stm32wl5/stm32wl5_ipcc.h
View file

@ -41,17 +41,17 @@
/* channel 1 configuration **************************************************/
#define IPCC_CHAN1_RX_SIZE (CONFIG_STM32WL5_IPCC_CHAN1_RX_SIZE)
#define IPCC_CHAN1_TX_SIZE (CONFIG_STM32WL5_IPCC_CHAN1_TX_SIZE)
#define IPCC_CHAN1_RX_SIZE (CONFIG_STM32_IPCC_CHAN1_RX_SIZE)
#define IPCC_CHAN1_TX_SIZE (CONFIG_STM32_IPCC_CHAN1_TX_SIZE)
#define IPCC_CHAN1_START (IPCC_START)
#define IPCC_CHAN1_SIZE (IPCC_CHAN1_RX_SIZE + IPCC_CHAN1_TX_SIZE)
#define IPCC_CHAN1 (1)
/* channel 2 configuration **************************************************/
#if defined(CONFIG_STM32WL5_IPCC_CHAN2)
# define IPCC_CHAN2_RX_SIZE (CONFIG_STM32WL5_IPCC_CHAN2_RX_SIZE)
# define IPCC_CHAN2_TX_SIZE (CONFIG_STM32WL5_IPCC_CHAN2_TX_SIZE)
#if defined(CONFIG_STM32_IPCC_CHAN2)
# define IPCC_CHAN2_RX_SIZE (CONFIG_STM32_IPCC_CHAN2_RX_SIZE)
# define IPCC_CHAN2_TX_SIZE (CONFIG_STM32_IPCC_CHAN2_TX_SIZE)
# define IPCC_CHAN2_START (IPCC_CHAN1_START + IPCC_CHAN1_SIZE)
# define IPCC_CHAN2_SIZE (IPCC_CHAN2_RX_SIZE + IPCC_CHAN2_TX_SIZE)
# define IPCC_CHAN2 (1)
@ -62,9 +62,9 @@
/* channel 3 configuration **************************************************/
#if defined(CONFIG_STM32WL5_IPCC_CHAN3)
# define IPCC_CHAN3_RX_SIZE (CONFIG_STM32WL5_IPCC_CHAN3_RX_SIZE)
# define IPCC_CHAN3_TX_SIZE (CONFIG_STM32WL5_IPCC_CHAN3_TX_SIZE)
#if defined(CONFIG_STM32_IPCC_CHAN3)
# define IPCC_CHAN3_RX_SIZE (CONFIG_STM32_IPCC_CHAN3_RX_SIZE)
# define IPCC_CHAN3_TX_SIZE (CONFIG_STM32_IPCC_CHAN3_TX_SIZE)
# define IPCC_CHAN3_START (IPCC_CHAN2_START + IPCC_CHAN2_SIZE)
# define IPCC_CHAN3_SIZE (IPCC_CHAN3_RX_SIZE + IPCC_CHAN3_TX_SIZE)
# define IPCC_CHAN3 (1)
@ -75,9 +75,9 @@
/* channel 4 configuration **************************************************/
#if defined(CONFIG_STM32WL5_IPCC_CHAN4)
# define IPCC_CHAN4_RX_SIZE (CONFIG_STM32WL5_IPCC_CHAN4_RX_SIZE)
# define IPCC_CHAN4_TX_SIZE (CONFIG_STM32WL5_IPCC_CHAN4_TX_SIZE)
#if defined(CONFIG_STM32_IPCC_CHAN4)
# define IPCC_CHAN4_RX_SIZE (CONFIG_STM32_IPCC_CHAN4_RX_SIZE)
# define IPCC_CHAN4_TX_SIZE (CONFIG_STM32_IPCC_CHAN4_TX_SIZE)
# define IPCC_CHAN4_START (IPCC_CHAN3_START + IPCC_CHAN3_SIZE)
# define IPCC_CHAN4_SIZE (IPCC_CHAN4_RX_SIZE + IPCC_CHAN4_TX_SIZE)
# define IPCC_CHAN4 (1)
@ -88,9 +88,9 @@
/* channel 5 configuration **************************************************/
#if defined(CONFIG_STM32WL5_IPCC_CHAN5)
# define IPCC_CHAN5_RX_SIZE (CONFIG_STM32WL5_IPCC_CHAN5_RX_SIZE)
# define IPCC_CHAN5_TX_SIZE (CONFIG_STM32WL5_IPCC_CHAN5_TX_SIZE)
#if defined(CONFIG_STM32_IPCC_CHAN5)
# define IPCC_CHAN5_RX_SIZE (CONFIG_STM32_IPCC_CHAN5_RX_SIZE)
# define IPCC_CHAN5_TX_SIZE (CONFIG_STM32_IPCC_CHAN5_TX_SIZE)
# define IPCC_CHAN5_START (IPCC_CHAN4_START + IPCC_CHAN4_SIZE)
# define IPCC_CHAN5_SIZE (IPCC_CHAN5_RX_SIZE + IPCC_CHAN5_TX_SIZE)
# define IPCC_CHAN5 (1)
@ -101,9 +101,9 @@
/* channel 6 configuration **************************************************/
#if defined(CONFIG_STM32WL5_IPCC_CHAN6)
# define IPCC_CHAN6_RX_SIZE (CONFIG_STM32WL5_IPCC_CHAN6_RX_SIZE)
# define IPCC_CHAN6_TX_SIZE (CONFIG_STM32WL5_IPCC_CHAN6_TX_SIZE)
#if defined(CONFIG_STM32_IPCC_CHAN6)
# define IPCC_CHAN6_RX_SIZE (CONFIG_STM32_IPCC_CHAN6_RX_SIZE)
# define IPCC_CHAN6_TX_SIZE (CONFIG_STM32_IPCC_CHAN6_TX_SIZE)
# define IPCC_CHAN6_START (IPCC_CHAN5_START + IPCC_CHAN5_SIZE)
# define IPCC_CHAN6_SIZE (IPCC_CHAN6_RX_SIZE + IPCC_CHAN6_TX_SIZE)
# define IPCC_CHAN6 (1)

20
arch/arm/src/stm32wl5/stm32wl5_lse.c
View file

@ -43,9 +43,9 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1,
#define LSERDY_TIMEOUT (500 * CONFIG_BOARD_LOOPSPERMSEC)
#ifdef CONFIG_STM32WL5_RTC_LSECLOCK_START_DRV_CAPABILITY
# if CONFIG_STM32WL5_RTC_LSECLOCK_START_DRV_CAPABILITY < 0 || \
CONFIG_STM32WL5_RTC_LSECLOCK_START_DRV_CAPABILITY > 3
#ifdef CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY
# if CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY < 0 || \
CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY > 3
# error "Invalid LSE drive capability setting"
# endif
#endif
@ -54,7 +54,7 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1,
* Private Data
****************************************************************************/
#ifdef CONFIG_STM32WL5_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY
#ifdef CONFIG_STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY
static const uint32_t drives[4] =
{
RCC_BDCR_LSEDRV_LOW,
@ -81,7 +81,7 @@ void stm32_rcc_enablelse(void)
int writable;
uint32_t regval;
volatile int32_t timeout;
#ifdef CONFIG_STM32WL5_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY
#ifdef CONFIG_STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY
volatile int32_t drive = 0;
#endif
@ -109,19 +109,19 @@ void stm32_rcc_enablelse(void)
regval |= RCC_BDCR_LSEON;
#ifdef CONFIG_STM32WL5_RTC_LSECLOCK_START_DRV_CAPABILITY
#ifdef CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY
/* Set start-up drive capability for LSE oscillator. LSE must be OFF
* to change drive strength.
*/
regval &= ~(RCC_BDCR_LSEDRV_MASK | RCC_BDCR_LSEON);
regval |= CONFIG_STM32WL5_RTC_LSECLOCK_START_DRV_CAPABILITY <<
regval |= CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY <<
RCC_BDCR_LSEDRV_SHIFT;
putreg32(regval, STM32_RCC_BDCR);
regval |= RCC_BDCR_LSEON;
#endif
#ifdef CONFIG_STM32WL5_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY
#ifdef CONFIG_STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY
do
{
regval &= ~(RCC_BDCR_LSEDRV_MASK | RCC_BDCR_LSEON);
@ -149,7 +149,7 @@ void stm32_rcc_enablelse(void)
}
}
#ifdef CONFIG_STM32WL5_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY
#ifdef CONFIG_STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY
if (timeout != 0)
{
break;
@ -178,7 +178,7 @@ void stm32_rcc_enablelse(void)
}
}
#ifdef CONFIG_STM32WL5_RTC_LSECLOCK_LOWER_RUN_DRV_CAPABILITY
#ifdef CONFIG_STM32_RTC_LSECLOCK_LOWER_RUN_DRV_CAPABILITY
/* Set running drive capability for LSE oscillator. */

74
arch/arm/src/stm32wl5/stm32wl5_rcc.c
View file

@ -74,7 +74,7 @@
*
****************************************************************************/
#if defined(CONFIG_STM32WL5_PWR) && defined(CONFIG_STM32WL5_RTC)
#if defined(CONFIG_STM32_PWR) && defined(CONFIG_STM32_RTC)
static inline void stm32_rcc_resetbkp(void)
{
bool init_stat;
@ -139,7 +139,7 @@ static inline void stm32_rcc_resetbkp(void)
* and enable peripheral clocking for all peripherals enabled in the NuttX
* configuration file.
*
* If CONFIG_ARCH_BOARD_STM32WL5_CUSTOM_CLOCKCONFIG is defined, then
* If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then
* clocking will be enabled by an externally provided, board-specific
* function called stm32_board_clockconfig().
*
@ -162,7 +162,7 @@ void stm32_clockconfig(void)
rcc_resetbkp();
#endif
#if defined(CONFIG_ARCH_BOARD_STM32WL5_CUSTOM_CLOCKCONFIG)
#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG)
/* Invoke Board Custom Clock Configuration */
@ -201,19 +201,19 @@ static void stm32_rcc_enableahb1(void)
regval = getreg32(STM32_RCC_AHB1ENR);
#ifdef CONFIG_STM32WL5_DMA1
#ifdef CONFIG_STM32_DMA1
/* DMA 1 clock enable */
regval |= RCC_AHB1ENR_DMA1EN;
#endif
#ifdef CONFIG_STM32WL5_DMA2
#ifdef CONFIG_STM32_DMA2
/* DMA 2 clock enable */
regval |= RCC_AHB1ENR_DMA2EN;
#endif
#ifdef CONFIG_STM32WL5_CRC
#ifdef CONFIG_STM32_CRC
/* CRC clock enable */
regval |= RCC_AHB1ENR_CRCEN;
@ -277,13 +277,13 @@ static inline void stm32_rcc_enableahb3(void)
regval = getreg32(STM32_RCC_AHB3ENR);
#ifdef CONFIG_STM32WL5_AES
#ifdef CONFIG_STM32_AES
/* Cryptographic modules clock enable */
regval |= RCC_AHB2ENR_AESEN;
#endif
#ifdef CONFIG_STM32WL5_RNG
#ifdef CONFIG_STM32_RNG
/* Random number generator clock enable */
regval |= RCC_AHB2ENR_RNGEN;
@ -295,7 +295,7 @@ static inline void stm32_rcc_enableahb3(void)
regval |= RCC_AHB3ENR_FLASHEN;
#endif
#ifdef CONFIG_STM32WL5_IPCC
#ifdef CONFIG_STM32_IPCC
/* IPCC interface clock enable */
regval |= RCC_AHB3ENR_IPCCEN;
@ -322,49 +322,49 @@ static inline void stm32_rcc_enableapb1(void)
regval = getreg32(STM32_RCC_APB1ENR1);
#ifdef CONFIG_STM32WL5_TIM2
#ifdef CONFIG_STM32_TIM2
/* TIM2 clock enable */
regval |= RCC_APB1ENR1_TIM2EN;
#endif
#ifdef CONFIG_STM32WL5_SPI2
#ifdef CONFIG_STM32_SPI2
/* SPI2 clock enable */
regval |= RCC_APB1ENR1_SPI2EN;
#endif
#ifdef CONFIG_STM32WL5_USART2
#ifdef CONFIG_STM32_USART2
/* USART 2 clock enable */
regval |= RCC_APB1ENR1_USART2EN;
#endif
#ifdef CONFIG_STM32WL5_I2C1
#ifdef CONFIG_STM32_I2C1
/* I2C1 clock enable */
regval |= RCC_APB1ENR1_I2C1EN;
#endif
#ifdef CONFIG_STM32WL5_I2C2
#ifdef CONFIG_STM32_I2C2
/* I2C2 clock enable */
regval |= RCC_APB1ENR1_I2C2EN;
#endif
#ifdef CONFIG_STM32WL5_I2C3
#ifdef CONFIG_STM32_I2C3
/* I2C3 clock enable */
regval |= RCC_APB1ENR1_I2C3EN;
#endif
#if defined (CONFIG_STM32WL5_DAC1)
#if defined (CONFIG_STM32_DAC1)
/* DAC interface clock enable */
regval |= RCC_APB1ENR1_DAC1EN;
#endif
#ifdef CONFIG_STM32WL5_LPTIM1
#ifdef CONFIG_STM32_LPTIM1
/* Low power timer 1 clock enable */
regval |= RCC_APB1ENR1_LPTIM1EN;
@ -376,19 +376,19 @@ static inline void stm32_rcc_enableapb1(void)
regval = getreg32(STM32_RCC_APB1ENR2);
#ifdef CONFIG_STM32WL5_LPUART1
#ifdef CONFIG_STM32_LPUART1
/* Low power uart clock enable */
regval |= RCC_APB1ENR2_LPUART1EN;
#endif
#ifdef CONFIG_STM32WL5_LPTIM2
#ifdef CONFIG_STM32_LPTIM2
/* Low power timer 2 clock enable */
regval |= RCC_APB1ENR2_LPTIM2EN;
#endif
#ifdef CONFIG_STM32WL5_LPTIM3
#ifdef CONFIG_STM32_LPTIM3
/* Low power timer 3 clock enable */
regval |= RCC_APB1ENR2_LPTIM3EN;
@ -415,37 +415,37 @@ static inline void stm32_rcc_enableapb2(void)
regval = getreg32(STM32_RCC_APB2ENR);
#if defined(CONFIG_STM32WL5_ADC1)
#if defined(CONFIG_STM32_ADC1)
/* ADC clock enable */
regval |= RCC_AHB2ENR_ADC1EN;
#endif
#ifdef CONFIG_STM32WL5_TIM1
#ifdef CONFIG_STM32_TIM1
/* TIM1 clock enable */
regval |= RCC_APB2ENR_TIM1EN;
#endif
#ifdef CONFIG_STM32WL5_SPI1
#ifdef CONFIG_STM32_SPI1
/* SPI1 clock enable */
regval |= RCC_APB2ENR_SPI1EN;
#endif
#ifdef CONFIG_STM32WL5_USART1
#ifdef CONFIG_STM32_USART1
/* USART1 clock enable */
regval |= RCC_APB2ENR_USART1EN;
#endif
#ifdef CONFIG_STM32WL5_TIM16
#ifdef CONFIG_STM32_TIM16
/* TIM16 clock enable */
regval |= RCC_APB2ENR_TIM16EN;
#endif
#ifdef CONFIG_STM32WL5_TIM17
#ifdef CONFIG_STM32_TIM17
/* TIM16 clock enable */
regval |= RCC_APB2ENR_TIM17EN;
@ -474,17 +474,17 @@ static inline void stm32_rcc_enableccip(void)
regval = getreg32(STM32_RCC_CCIPR);
#if defined(STM32_I2C_USE_HSI16)
#ifdef CONFIG_STM32WL5_I2C1
#ifdef CONFIG_STM32_I2C1
/* Select HSI16 as I2C1 clock source. */
regval |= RCC_CCIPR_I2C1SEL_HSI;
#endif
#ifdef CONFIG_STM32WL5_I2C2
#ifdef CONFIG_STM32_I2C2
/* Select HSI16 as I2C2 clock source. */
regval |= RCC_CCIPR_I2C2SEL_HSI;
#endif
#ifdef CONFIG_STM32WL5_I2C3
#ifdef CONFIG_STM32_I2C3
/* Select HSI16 as I2C3 clock source. */
regval |= RCC_CCIPR_I2C3SEL_HSI;
@ -500,13 +500,13 @@ static inline void stm32_rcc_enableccip(void)
regval |= STM32_CLK48_SEL;
#endif
#if defined(CONFIG_STM32WL5_ADC1)
#if defined(CONFIG_STM32_ADC1)
/* Select SYSCLK as ADC clock source */
regval |= RCC_CCIPR_ADCSEL_SYSCLK;
#endif
#ifdef CONFIG_STM32WL5_DFSDM1
#ifdef CONFIG_STM32_DFSDM1
/* Select SYSCLK as DFSDM clock source */
/* RM0394 Rev 3, p. 525 is confused about DFSDM clock source.
@ -523,7 +523,7 @@ static inline void stm32_rcc_enableccip(void)
/* I2C4 alone has their clock selection in CCIPR2 register. */
#if defined(STM32_I2C_USE_HSI16)
#ifdef CONFIG_STM32WL5_I2C4
#ifdef CONFIG_STM32_I2C4
regval = getreg32(STM32_RCC_CCIPR2);
/* Select HSI16 as I2C4 clock source. */
@ -548,7 +548,7 @@ static inline void stm32_rcc_enableccip(void)
* stm32_clockconfig()
* reset the currently enabled peripheral clocks.
*
* If CONFIG_ARCH_BOARD_STM32WL5_CUSTOM_CLOCKCONFIG is defined, then
* If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then
* clocking will be enabled by an externally provided, board-specific
* function called stm32_board_clockconfig().
*
@ -563,7 +563,7 @@ static inline void stm32_rcc_enableccip(void)
#ifdef CONFIG_PM
void stm32_clockenable(void)
{
#if defined(CONFIG_ARCH_BOARD_STM32WL5_CUSTOM_CLOCKCONFIG)
#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG)
/* Invoke Board Custom Clock Configuration */
@ -605,7 +605,7 @@ void stm32_rcc_enableperipherals(void)
* power clocking modes!
****************************************************************************/
#ifndef CONFIG_ARCH_BOARD_STM32WL5_CUSTOM_CLOCKCONFIG
#ifndef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG
void stm32_stdclockconfig(void)
{
uint32_t regval;
@ -759,7 +759,7 @@ void stm32_stdclockconfig(void)
regval |= STM32_RCC_CFGR_PPRE1;
putreg32(regval, STM32_RCC_CFGR);
#ifdef CONFIG_STM32WL5_RTC_HSECLOCK
#ifdef CONFIG_STM32_RTC_HSECLOCK
/* Set the RTC clock divisor */
regval = getreg32(STM32_RCC_CFGR);
@ -849,7 +849,7 @@ void stm32_stdclockconfig(void)
{
}
#if defined(CONFIG_STM32WL5_IWDG) || defined(CONFIG_STM32WL5_RTC_LSICLOCK)
#if defined(CONFIG_STM32_IWDG) || defined(CONFIG_STM32_RTC_LSICLOCK)
/* Low speed internal clock source LSI */
stm32_rcc_enablelsi();

8
arch/arm/src/stm32wl5/stm32wl5_rcc.h
View file

@ -96,7 +96,7 @@ static inline void stm32_mcoconfig(uint32_t source)
* and enable peripheral clocking for all periperipherals enabled in the
* NuttX configuration file.
*
* If CONFIG_ARCH_BOARD_STM32WL5_CUSTOM_CLOCKCONFIG is defined, then
* If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then
* clocking will be enabled by an externally provided, board-specific
* function called stm32_board_clockconfig().
*
@ -119,7 +119,7 @@ void stm32_clockconfig(void);
*
****************************************************************************/
#ifdef CONFIG_ARCH_BOARD_STM32WL5_CUSTOM_CLOCKCONFIG
#ifdef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG
void stm32_board_clockconfig(void);
#endif
@ -134,7 +134,7 @@ void stm32_board_clockconfig(void);
*
****************************************************************************/
#ifndef CONFIG_ARCH_BOARD_STM32WL5_CUSTOM_CLOCKCONFIG
#ifndef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG
void stm32_stdclockconfig(void);
#endif
@ -151,7 +151,7 @@ void stm32_stdclockconfig(void);
* stm32_clockconfig(): It does not reset any devices, and it does not
* reset the currently enabled peripheral clocks.
*
* If CONFIG_ARCH_BOARD_STM32WL5_CUSTOM_CLOCKCONFIG is defined, then
* If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then
* clocking will be enabled by an externally provided, board-specific
* function called stm32_board_clockconfig().
*

68
arch/arm/src/stm32wl5/stm32wl5_serial.c
View file

@ -82,8 +82,8 @@
*/
# if defined(CONFIG_USART2_RXDMA)
# if !defined(CONFIG_STM32WL5_DMA1) && !defined(CONFIG_STM32WL5_DMAMUX)
# error STM32WL5 USART2/3 receive DMA requires CONFIG_STM32WL5_DMA1
# if !defined(CONFIG_STM32_DMA1) && !defined(CONFIG_STM32_DMAMUX)
# error STM32WL5 USART2/3 receive DMA requires CONFIG_STM32_DMA1
# endif
# endif
@ -98,7 +98,7 @@
/* UART2-5 have no alternate channels without DMAMUX */
# ifndef CONFIG_STM32WL5_HAVE_DMAMUX
# ifndef CONFIG_STM32_HAVE_DMAMUX
# define DMAMAP_USART2_RX DMACHAN_USART2_RX
# endif
@ -116,11 +116,11 @@
* can be individually invalidated.
*/
# if !defined(CONFIG_STM32WL5_SERIAL_RXDMA_BUFFER_SIZE) || \
CONFIG_STM32WL5_SERIAL_RXDMA_BUFFER_SIZE == 0
# if !defined(CONFIG_STM32_SERIAL_RXDMA_BUFFER_SIZE) || \
CONFIG_STM32_SERIAL_RXDMA_BUFFER_SIZE == 0
# define RXDMA_BUFFER_SIZE 32
# else
# define RXDMA_BUFFER_SIZE ((CONFIG_STM32WL5_SERIAL_RXDMA_BUFFER_SIZE + 31) & ~31)
# define RXDMA_BUFFER_SIZE ((CONFIG_STM32_SERIAL_RXDMA_BUFFER_SIZE + 31) & ~31)
# endif
/* DMA priority */
@ -152,8 +152,8 @@
/* Power management definitions */
#if defined(CONFIG_PM) && !defined(CONFIG_STM32WL5_PM_SERIAL_ACTIVITY)
# define CONFIG_STM32WL5_PM_SERIAL_ACTIVITY 10
#if defined(CONFIG_PM) && !defined(CONFIG_STM32_PM_SERIAL_ACTIVITY)
# define CONFIG_STM32_PM_SERIAL_ACTIVITY 10
#endif
#if defined(CONFIG_PM)
# define PM_IDLE_DOMAIN 0 /* Revisit */
@ -170,7 +170,7 @@
* See stm32wl5serial_restoreusartint where the masking is done.
*/
#ifdef CONFIG_STM32WL5_SERIALBRK_BSDCOMPAT
#ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT
# define USART_CR1_IE_BREAK_INPROGRESS_SHFTS 15
# define USART_CR1_IE_BREAK_INPROGRESS (1 << USART_CR1_IE_BREAK_INPROGRESS_SHFTS)
#endif
@ -366,7 +366,7 @@ static const struct uart_ops_s g_uart_dma_ops =
/* I/O buffers */
#ifdef CONFIG_STM32WL5_LPUART1_SERIALDRIVER
#ifdef CONFIG_STM32_LPUART1_SERIALDRIVER
static char g_lpuart1rxbuffer[CONFIG_LPUART1_RXBUFSIZE];
static char g_lpuart1txbuffer[CONFIG_LPUART1_TXBUFSIZE];
# ifdef CONFIG_LPUART1_RXDMA
@ -374,7 +374,7 @@ static char g_lpuart1rxfifo[RXDMA_BUFFER_SIZE];
# endif
#endif
#ifdef CONFIG_STM32WL5_USART1_SERIALDRIVER
#ifdef CONFIG_STM32_USART1_SERIALDRIVER
static char g_usart1rxbuffer[CONFIG_USART1_RXBUFSIZE];
static char g_usart1txbuffer[CONFIG_USART1_TXBUFSIZE];
# ifdef CONFIG_USART1_RXDMA
@ -382,7 +382,7 @@ static char g_usart1rxfifo[RXDMA_BUFFER_SIZE];
# endif
#endif
#ifdef CONFIG_STM32WL5_USART2_SERIALDRIVER
#ifdef CONFIG_STM32_USART2_SERIALDRIVER
static char g_usart2rxbuffer[CONFIG_USART2_RXBUFSIZE];
static char g_usart2txbuffer[CONFIG_USART2_TXBUFSIZE];
# ifdef CONFIG_USART2_RXDMA
@ -392,7 +392,7 @@ static char g_usart2rxfifo[RXDMA_BUFFER_SIZE];
/* This describes the state of the STM32 USART1 ports. */
#ifdef CONFIG_STM32WL5_LPUART1_SERIALDRIVER
#ifdef CONFIG_STM32_LPUART1_SERIALDRIVER
static struct stm32_serial_s g_lpuart1priv =
{
.dev =
@ -452,7 +452,7 @@ static struct stm32_serial_s g_lpuart1priv =
};
#endif
#ifdef CONFIG_STM32WL5_USART1_SERIALDRIVER
#ifdef CONFIG_STM32_USART1_SERIALDRIVER
static struct stm32_serial_s g_usart1priv =
{
.dev =
@ -514,7 +514,7 @@ static struct stm32_serial_s g_usart1priv =
/* This describes the state of the STM32 USART2 port. */
#ifdef CONFIG_STM32WL5_USART2_SERIALDRIVER
#ifdef CONFIG_STM32_USART2_SERIALDRIVER
static struct stm32_serial_s g_usart2priv =
{
.dev =
@ -579,13 +579,13 @@ static struct stm32_serial_s g_usart2priv =
static struct stm32_serial_s * const
g_uart_devs[STM32_NLPUART + STM32_NUSART] =
{
#ifdef CONFIG_STM32WL5_LPUART1_SERIALDRIVER
#ifdef CONFIG_STM32_LPUART1_SERIALDRIVER
[0] = &g_lpuart1priv,
#endif
#ifdef CONFIG_STM32WL5_USART1_SERIALDRIVER
#ifdef CONFIG_STM32_USART1_SERIALDRIVER
[1] = &g_usart1priv,
#endif
#ifdef CONFIG_STM32WL5_USART2_SERIALDRIVER
#ifdef CONFIG_STM32_USART2_SERIALDRIVER
[2] = &g_usart2priv,
#endif
};
@ -892,7 +892,7 @@ static void stm32wl5serial_setformat(struct uart_dev_s *dev)
regval = stm32wl5serial_getreg(priv, STM32_USART_CR3_OFFSET);
regval &= ~(USART_CR3_CTSE | USART_CR3_RTSE);
#if defined(CONFIG_SERIAL_IFLOWCONTROL) && !defined(CONFIG_STM32WL5_FLOWCONTROL_BROKEN)
#if defined(CONFIG_SERIAL_IFLOWCONTROL) && !defined(CONFIG_STM32_FLOWCONTROL_BROKEN)
if (priv->iflow && (priv->rts_gpio != 0))
{
regval |= USART_CR3_RTSE;
@ -1096,19 +1096,19 @@ static void stm32wl5serial_setapbclock(struct uart_dev_s *dev, bool on)
{
default:
return;
#ifdef CONFIG_STM32WL5_LPUART1_SERIALDRIVER
#ifdef CONFIG_STM32_LPUART1_SERIALDRIVER
case STM32_LPUART1_BASE:
rcc_en = RCC_APB1ENR2_LPUART1EN;
regaddr = STM32_RCC_APB1ENR2;
break;
#endif
#ifdef CONFIG_STM32WL5_USART1_SERIALDRIVER
#ifdef CONFIG_STM32_USART1_SERIALDRIVER
case STM32_USART1_BASE:
rcc_en = RCC_APB2ENR_USART1EN;
regaddr = STM32_RCC_APB2ENR;
break;
#endif
#ifdef CONFIG_STM32WL5_USART2_SERIALDRIVER
#ifdef CONFIG_STM32_USART2_SERIALDRIVER
case STM32_USART2_BASE:
rcc_en = RCC_APB1ENR1_USART2EN;
regaddr = STM32_RCC_APB1ENR1;
@ -1177,7 +1177,7 @@ static int stm32wl5serial_setup(struct uart_dev_s *dev)
{
uint32_t config = priv->rts_gpio;
#ifdef CONFIG_STM32WL5_FLOWCONTROL_BROKEN
#ifdef CONFIG_STM32_FLOWCONTROL_BROKEN
/* Instead of letting hw manage this pin, we will bitbang */
config = (config & ~GPIO_MODE_MASK) | GPIO_OUTPUT;
@ -1529,8 +1529,8 @@ static int stm32wl5serial_interrupt(int irq, void *context,
/* Report serial activity to the power management logic */
#if defined(CONFIG_PM) && CONFIG_STM32WL5_PM_SERIAL_ACTIVITY > 0
pm_activity(PM_IDLE_DOMAIN, CONFIG_STM32WL5_PM_SERIAL_ACTIVITY);
#if defined(CONFIG_PM) && CONFIG_STM32_PM_SERIAL_ACTIVITY > 0
pm_activity(PM_IDLE_DOMAIN, CONFIG_STM32_PM_SERIAL_ACTIVITY);
#endif
/* Loop until there are no characters to be transferred or,
@ -1674,7 +1674,7 @@ static int stm32wl5serial_ioctl(struct file *filep, int cmd,
break;
#endif
#ifdef CONFIG_STM32WL5_USART_SINGLEWIRE
#ifdef CONFIG_STM32_USART_SINGLEWIRE
case TIOCSSINGLEWIRE:
{
uint32_t cr1;
@ -1752,7 +1752,7 @@ static int stm32wl5serial_ioctl(struct file *filep, int cmd,
break;
#endif
#ifdef CONFIG_STM32WL5_USART_INVERT
#ifdef CONFIG_STM32_USART_INVERT
case TIOCSINVERT:
{
uint32_t cr1;
@ -1803,7 +1803,7 @@ static int stm32wl5serial_ioctl(struct file *filep, int cmd,
break;
#endif
#ifdef CONFIG_STM32WL5_USART_SWAP
#ifdef CONFIG_STM32_USART_SWAP
case TIOCSSWAP:
{
uint32_t cr1;
@ -1940,8 +1940,8 @@ static int stm32wl5serial_ioctl(struct file *filep, int cmd,
break;
#endif /* CONFIG_SERIAL_TERMIOS */
#ifdef CONFIG_STM32WL5_USART_BREAKS
# ifdef CONFIG_STM32WL5_SERIALBRK_BSDCOMPAT
#ifdef CONFIG_STM32_USART_BREAKS
# ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT
case TIOCSBRK: /* BSD compatibility: Turn break on, unconditionally */
{
irqstate_t flags;
@ -2169,7 +2169,7 @@ static bool stm32wl5serial_rxflowcontrol(struct uart_dev_s *dev,
(struct stm32_serial_s *)dev->priv;
#if defined(CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS) && \
defined(CONFIG_STM32WL5_FLOWCONTROL_BROKEN)
defined(CONFIG_STM32_FLOWCONTROL_BROKEN)
if (priv->iflow && (priv->rts_gpio != 0))
{
/* Assert/de-assert nRTS set it high resume/stop sending */
@ -2521,7 +2521,7 @@ static void stm32wl5serial_txint(struct uart_dev_s *dev, bool enable)
}
# endif
# ifdef CONFIG_STM32WL5_SERIALBRK_BSDCOMPAT
# ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT
if (priv->ie & USART_CR1_IE_BREAK_INPROGRESS)
{
leave_critical_section(flags);
@ -2862,7 +2862,7 @@ void arm_serialinit(void)
#if CONSOLE_UART > 0
(void)uart_register("/dev/console", &g_uart_devs[CONSOLE_UART - 1]->dev);
#ifndef CONFIG_STM32WL5_SERIAL_DISABLE_REORDERING
#ifndef CONFIG_STM32_SERIAL_DISABLE_REORDERING
/* If not disabled, register the console UART to ttyS0 and exclude
* it from initializing it further down
*/
@ -2891,7 +2891,7 @@ void arm_serialinit(void)
continue;
}
#ifndef CONFIG_STM32WL5_SERIAL_DISABLE_REORDERING
#ifndef CONFIG_STM32_SERIAL_DISABLE_REORDERING
/* Don't create a device for the console - we did that above */
if (g_uart_devs[i]->dev.isconsole)

100
arch/arm/src/stm32wl5/stm32wl5_spi.c
View file

@ -69,12 +69,12 @@
#include "chip.h"
#include "stm32.h"
#include "stm32wl5_gpio.h"
#ifdef CONFIG_STM32WL5_SPI_DMA
#ifdef CONFIG_STM32_SPI_DMA
#include "stm32wl5_dma.h"
#endif
#include "stm32wl5_spi.h"
#if defined(CONFIG_STM32WL5_SPI1) || defined(CONFIG_STM32WL5_SPI2S2)
#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2S2)
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
@ -83,34 +83,34 @@
/* SPI interrupts */
#ifdef CONFIG_STM32WL5_SPI_INTERRUPTS
#ifdef CONFIG_STM32_SPI_INTERRUPTS
# error "Interrupt driven SPI not yet supported"
#endif
#ifdef CONFIG_STM32WL5_SPI_DMA
#ifdef CONFIG_STM32_SPI_DMA
# error "DMA driven SPI not yet supported"
#endif
/* Can't have both interrupt driven SPI and SPI DMA */
#if defined(CONFIG_STM32WL5_SPI_INTERRUPTS) && defined(CONFIG_STM32WL5_SPI_DMA)
#if defined(CONFIG_STM32_SPI_INTERRUPTS) && defined(CONFIG_STM32_SPI_DMA)
# error "Cannot enable both interrupt mode and DMA mode for SPI"
#endif
/* SPI DMA priority */
#ifdef CONFIG_STM32WL5_SPI_DMA
#ifdef CONFIG_STM32_SPI_DMA
# if defined(CONFIG_SPI_DMAPRIO)
# define SPI_DMA_PRIO CONFIG_SPI_DMAPRIO
# elif defined(CONFIG_STM32WL5_STM32WL5XXX_CPU1
# elif defined(CONFIG_STM32_STM32WL5XXX_CPU1
#warning "Verify, read doc and Implement"
# define SPI_DMA_PRIO DMA_CCR_PRIMED
# else
# error "Unknown STM32WL5 DMA"
# endif
# if defined(CONFIG_STM32WL5_STM32WL5XXX_CPU1)
# if defined(CONFIG_STM32_STM32WL5XXX_CPU1)
# if (SPI_DMA_PRIO & ~DMA_CCR_PL_MASK) != 0
# error "Illegal value for CONFIG_SPI_DMAPRIO"
# endif
@ -120,7 +120,7 @@
/* DMA channel configuration */
#if defined(CONFIG_STM32WL5_STM32WL5XXX_CPU1)
#if defined(CONFIG_STM32_STM32WL5XXX_CPU1)
# define SPI_RXDMA16_CONFIG (SPI_DMA_PRIO|DMA_CCR_MSIZE_16BITS|DMA_CCR_PSIZE_16BITS|DMA_CCR_MINC )
# define SPI_RXDMA8_CONFIG (SPI_DMA_PRIO|DMA_CCR_MSIZE_8BITS |DMA_CCR_PSIZE_8BITS |DMA_CCR_MINC )
# define SPI_RXDMA16NULL_CONFIG (SPI_DMA_PRIO|DMA_CCR_MSIZE_8BITS |DMA_CCR_PSIZE_16BITS )
@ -137,15 +137,15 @@
# define SPIDMA_SIZE(b) (((b) + SPIDMA_BUFFER_MASK) & ~SPIDMA_BUFFER_MASK)
# define SPIDMA_BUF_ALIGN aligned_data(4)
# if defined(CONFIG_STM32WL5_SPI1_DMA_BUFFER) && \
CONFIG_STM32WL5_SPI1_DMA_BUFFER > 0
# define SPI1_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32WL5_SPI1_DMA_BUFFER)
# if defined(CONFIG_STM32_SPI1_DMA_BUFFER) && \
CONFIG_STM32_SPI1_DMA_BUFFER > 0
# define SPI1_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32_SPI1_DMA_BUFFER)
# define SPI1_DMABUFSIZE_ALGN SPIDMA_BUF_ALIGN
# endif
# if defined(CONFIG_STM32WL5_SPI2S2_DMA_BUFFER) && \
CONFIG_STM32WL5_SPI2S2_DMA_BUFFER > 0
# define SPI2S2_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32WL5_SPI2S2_DMA_BUFFER)
# if defined(CONFIG_STM32_SPI2S2_DMA_BUFFER) && \
CONFIG_STM32_SPI2S2_DMA_BUFFER > 0
# define SPI2S2_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32_SPI2S2_DMA_BUFFER)
# define SPI2S2_DMABUFSIZE_ALGN SPIDMA_BUF_ALIGN
# endif
@ -160,10 +160,10 @@ struct stm32_spidev_s
struct spi_dev_s spidev; /* Externally visible part of the SPI interface */
uint32_t spibase; /* SPIn base address */
uint32_t spiclock; /* Clocking for the SPI module */
#ifdef CONFIG_STM32WL5_SPI_INTERRUPTS
#ifdef CONFIG_STM32_SPI_INTERRUPTS
uint8_t spiirq; /* SPI IRQ number */
#endif
#ifdef CONFIG_STM32WL5_SPI_DMA
#ifdef CONFIG_STM32_SPI_DMA
volatile uint8_t rxresult; /* Result of the RX DMA */
volatile uint8_t txresult; /* Result of the RX DMA */
#ifdef CONFIG_SPI_TRIGGER
@ -216,7 +216,7 @@ static inline void spi_writeword(struct stm32_spidev_s *priv,
/* DMA support */
#ifdef CONFIG_STM32WL5_SPI_DMA
#ifdef CONFIG_STM32_SPI_DMA
static int spi_dmarxwait(struct stm32_spidev_s *priv);
static int spi_dmatxwait(struct stm32_spidev_s *priv);
static inline void spi_dmarxwakeup(struct stm32_spidev_s *priv);
@ -273,7 +273,7 @@ static void spi_bus_initialize(struct stm32_spidev_s *priv);
* Private Data
****************************************************************************/
#ifdef CONFIG_STM32WL5_SPI1
#ifdef CONFIG_STM32_SPI1
static const struct spi_ops_s g_sp1iops =
{
.lock = spi_lock,
@ -318,11 +318,11 @@ static struct stm32_spidev_s g_spi1dev =
},
.spibase = STM32_SPI1_BASE,
.spiclock = STM32_PCLK2_FREQUENCY,
#ifdef CONFIG_STM32WL5_SPI_INTERRUPTS
#ifdef CONFIG_STM32_SPI_INTERRUPTS
.spiirq = STM32_IRQ_SPI1,
#endif
#ifdef CONFIG_STM32WL5_SPI_DMA
# ifdef CONFIG_STM32WL5_SPI1_DMA
#ifdef CONFIG_STM32_SPI_DMA
# ifdef CONFIG_STM32_SPI1_DMA
.rxch = DMACHAN_SPI1_RX,
.txch = DMACHAN_SPI1_TX,
#if defined(SPI1_DMABUFSIZE_ADJUSTED)
@ -341,7 +341,7 @@ static struct stm32_spidev_s g_spi1dev =
};
#endif
#ifdef CONFIG_STM32WL5_SPI2S2
#ifdef CONFIG_STM32_SPI2S2
static const struct spi_ops_s g_sp2iops =
{
.lock = spi_lock,
@ -388,11 +388,11 @@ static struct stm32_spidev_s g_spi2s2dev =
},
.spibase = STM32_SPI2S2_BASE,
.spiclock = STM32_PCLK1_FREQUENCY,
#ifdef CONFIG_STM32WL5_SPI_INTERRUPTS
#ifdef CONFIG_STM32_SPI_INTERRUPTS
.spiirq = STM32_IRQ_SPI2S2,
#endif
#ifdef CONFIG_STM32WL5_SPI_DMA
# ifdef CONFIG_STM32WL5_SPI2S2_DMA
#ifdef CONFIG_STM32_SPI_DMA
# ifdef CONFIG_STM32_SPI2S2_DMA
.rxch = DMACHAN_SPI2S2_RX,
.txch = DMACHAN_SPI2S2_TX,
#if defined(SPI2S2_DMABUFSIZE_ADJUSTED)
@ -592,7 +592,7 @@ static inline void spi_writeword(struct stm32_spidev_s *priv,
*
****************************************************************************/
#ifdef CONFIG_STM32WL5_SPI_DMA
#ifdef CONFIG_STM32_SPI_DMA
static int spi_dmarxwait(struct stm32_spidev_s *priv)
{
int ret;
@ -625,7 +625,7 @@ static int spi_dmarxwait(struct stm32_spidev_s *priv)
*
****************************************************************************/
#ifdef CONFIG_STM32WL5_SPI_DMA
#ifdef CONFIG_STM32_SPI_DMA
static int spi_dmatxwait(struct stm32_spidev_s *priv)
{
int ret;
@ -658,7 +658,7 @@ static int spi_dmatxwait(struct stm32_spidev_s *priv)
*
****************************************************************************/
#ifdef CONFIG_STM32WL5_SPI_DMA
#ifdef CONFIG_STM32_SPI_DMA
static inline void spi_dmarxwakeup(struct stm32_spidev_s *priv)
{
nxsem_post(&priv->rxsem);
@ -673,7 +673,7 @@ static inline void spi_dmarxwakeup(struct stm32_spidev_s *priv)
*
****************************************************************************/
#ifdef CONFIG_STM32WL5_SPI_DMA
#ifdef CONFIG_STM32_SPI_DMA
static inline void spi_dmatxwakeup(struct stm32_spidev_s *priv)
{
nxsem_post(&priv->txsem);
@ -688,7 +688,7 @@ static inline void spi_dmatxwakeup(struct stm32_spidev_s *priv)
*
****************************************************************************/
#ifdef CONFIG_STM32WL5_SPI_DMA
#ifdef CONFIG_STM32_SPI_DMA
static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg)
{
struct stm32_spidev_s *priv = (struct stm32_spidev_s *)arg;
@ -708,7 +708,7 @@ static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg)
*
****************************************************************************/
#ifdef CONFIG_STM32WL5_SPI_DMA
#ifdef CONFIG_STM32_SPI_DMA
static void spi_dmatxcallback(DMA_HANDLE handle, uint8_t isr, void *arg)
{
struct stm32_spidev_s *priv = (struct stm32_spidev_s *)arg;
@ -728,7 +728,7 @@ static void spi_dmatxcallback(DMA_HANDLE handle, uint8_t isr, void *arg)
*
****************************************************************************/
#ifdef CONFIG_STM32WL5_SPI_DMA
#ifdef CONFIG_STM32_SPI_DMA
static void spi_dmarxsetup(struct stm32_spidev_s *priv,
void *rxbuffer,
void *rxdummy, size_t nwords)
@ -779,7 +779,7 @@ static void spi_dmarxsetup(struct stm32_spidev_s *priv,
*
****************************************************************************/
#ifdef CONFIG_STM32WL5_SPI_DMA
#ifdef CONFIG_STM32_SPI_DMA
static void spi_dmatxsetup(struct stm32_spidev_s *priv,
const void *txbuffer,
const void *txdummy, size_t nwords)
@ -830,7 +830,7 @@ static void spi_dmatxsetup(struct stm32_spidev_s *priv,
*
****************************************************************************/
#ifdef CONFIG_STM32WL5_SPI_DMA
#ifdef CONFIG_STM32_SPI_DMA
static inline void spi_dmarxstart(struct stm32_spidev_s *priv)
{
priv->rxresult = 0;
@ -846,7 +846,7 @@ static inline void spi_dmarxstart(struct stm32_spidev_s *priv)
*
****************************************************************************/
#ifdef CONFIG_STM32WL5_SPI_DMA
#ifdef CONFIG_STM32_SPI_DMA
static inline void spi_dmatxstart(struct stm32_spidev_s *priv)
{
priv->txresult = 0;
@ -1348,9 +1348,9 @@ static uint32_t spi_send(struct spi_dev_s *dev, uint32_t wd)
*
****************************************************************************/
#if !defined(CONFIG_STM32WL5_SPI_DMA) || defined(CONFIG_STM32WL5_DMACAPABLE) || \
defined(CONFIG_STM32WL5_SPI_DMATHRESHOLD)
#if !defined(CONFIG_STM32WL5_SPI_DMA)
#if !defined(CONFIG_STM32_SPI_DMA) || defined(CONFIG_STM32_DMACAPABLE) || \
defined(CONFIG_STM32_SPI_DMATHRESHOLD)
#if !defined(CONFIG_STM32_SPI_DMA)
static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer,
void *rxbuffer, size_t nwords)
#else
@ -1433,7 +1433,7 @@ static void spi_exchange_nodma(struct spi_dev_s *dev,
}
}
}
#endif /* !CONFIG_STM32WL5_SPI_DMA || CONFIG_STM32WL5_DMACAPABLE || CONFIG_STM32WL5_SPI_DMATHRESHOLD */
#endif /* !CONFIG_STM32_SPI_DMA || CONFIG_STM32_DMACAPABLE || CONFIG_STM32_SPI_DMATHRESHOLD */
/****************************************************************************
* Name: spi_exchange (with DMA capability)
@ -1456,7 +1456,7 @@ static void spi_exchange_nodma(struct spi_dev_s *dev,
*
****************************************************************************/
#ifdef CONFIG_STM32WL5_SPI_DMA
#ifdef CONFIG_STM32_SPI_DMA
static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer,
void *rxbuffer, size_t nwords)
{
@ -1470,12 +1470,12 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer,
size_t nbytes = (priv->nbits > 8) ? nwords << 1 : nwords;
#ifdef CONFIG_STM32WL5_SPI_DMATHRESHOLD
#ifdef CONFIG_STM32_SPI_DMATHRESHOLD
/* If this is a small SPI transfer, then let spi_exchange_nodma() do the
* work.
*/
if (nbytes <= CONFIG_STM32WL5_SPI_DMATHRESHOLD)
if (nbytes <= CONFIG_STM32_SPI_DMATHRESHOLD)
{
spi_exchange_nodma(dev, txbuffer, rxbuffer, nwords);
return;
@ -1493,7 +1493,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer,
return;
}
#ifdef CONFIG_STM32WL5_DMACAPABLE
#ifdef CONFIG_STM32_DMACAPABLE
if ((txbuffer != NULL && priv->txbuf == NULL &&
!stm32_dmacapable((uintptr_t)txbuffer, nwords, priv->txccr)) ||
(rxbuffer != NULL && priv->rxbuf == NULL &&
@ -1580,7 +1580,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer,
#endif
}
}
#endif /* CONFIG_STM32WL5_SPI_DMA */
#endif /* CONFIG_STM32_SPI_DMA */
/****************************************************************************
* Name: spi_trigger
@ -1601,7 +1601,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer,
#ifdef CONFIG_SPI_TRIGGER
static int spi_trigger(struct spi_dev_s *dev)
{
#ifdef CONFIG_STM32WL5_SPI_DMA
#ifdef CONFIG_STM32_SPI_DMA
struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev;
if (!priv->trigarmed)
@ -1733,7 +1733,7 @@ static void spi_bus_initialize(struct stm32_spidev_s *priv)
spi_putreg(priv, STM32_SPI_CRCPR_OFFSET, 7);
#ifdef CONFIG_STM32WL5_SPI_DMA
#ifdef CONFIG_STM32_SPI_DMA
if (priv->rxch && priv->txch)
{
/* Get DMA channels. NOTE: stm32_dmachannel() will always assign
@ -1788,7 +1788,7 @@ struct spi_dev_s *stm32_spibus_initialize(int bus)
irqstate_t flags = enter_critical_section();
#ifdef CONFIG_STM32WL5_SPI1
#ifdef CONFIG_STM32_SPI1
if (bus == 1)
{
/* Select SPI1 */
@ -1813,7 +1813,7 @@ struct spi_dev_s *stm32_spibus_initialize(int bus)
}
else
#endif
#ifdef CONFIG_STM32WL5_SPI2S2
#ifdef CONFIG_STM32_SPI2S2
if (bus == 2)
{
/* Select SPI2S2 */
@ -1846,4 +1846,4 @@ struct spi_dev_s *stm32_spibus_initialize(int bus)
return (struct spi_dev_s *)priv;
}
#endif /* CONFIG_STM32WL5_SPI1 || CONFIG_STM32WL5_SPI2S2 */
#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2S2 */

8
arch/arm/src/stm32wl5/stm32wl5_spi.h
View file

@ -107,14 +107,14 @@ struct spi_dev_s *stm32_spibus_initialize(int bus);
*
****************************************************************************/
#ifdef CONFIG_STM32WL5_SPI1
#ifdef CONFIG_STM32_SPI1
void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid,
bool selected);
uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid);
int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd);
#endif
#ifdef CONFIG_STM32WL5_SPI2S2
#ifdef CONFIG_STM32_SPI2S2
void stm32_spi2s2select(struct spi_dev_s *dev, uint32_t devid,
bool selected);
uint8_t stm32_spi2s2status(struct spi_dev_s *dev, uint32_t devid);
@ -142,12 +142,12 @@ int stm32_spi2s2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd);
****************************************************************************/
#ifdef CONFIG_SPI_CALLBACK
#ifdef CONFIG_STM32WL5_SPI1
#ifdef CONFIG_STM32_SPI1
int stm32_spi1register(struct spi_dev_s *dev, spi_mediachange_t callback,
void *arg);
#endif
#ifdef CONFIG_STM32WL5_SPI2S2
#ifdef CONFIG_STM32_SPI2S2
int stm32_spi2s2register(struct spi_dev_s *dev,
spi_mediachange_t callback,
void *arg);

2
arch/arm/src/stm32wl5/stm32wl5_start.c
View file

@ -133,7 +133,7 @@ void __start(void)
"r"(CONFIG_IDLETHREAD_STACKSIZE - 64) :);
#endif
#ifdef CONFIG_STM32WL5_SRAM2_INIT
#ifdef CONFIG_STM32_SRAM2_INIT
/* The SRAM2 region is parity checked, but upon power up, it will be in
* a random state and probably invalid with respect to parity, potentially
* generating faults if accessed. If elected, we will write zeros to the

246
arch/arm/src/stm32wl5/stm32wl5_tim.c
View file

@ -74,118 +74,118 @@
* In any of these cases, the timer will not be used by this timer module.
*/
#if defined(CONFIG_STM32WL5_TIM1_PWM) || defined (CONFIG_STM32WL5_TIM1_ADC) || \
defined(CONFIG_STM32WL5_TIM1_DAC) || defined(CONFIG_STM32WL5_TIM1_QE)
# undef CONFIG_STM32WL5_TIM1
#if defined(CONFIG_STM32_TIM1_PWM) || defined (CONFIG_STM32_TIM1_ADC) || \
defined(CONFIG_STM32_TIM1_DAC) || defined(CONFIG_STM32_TIM1_QE)
# undef CONFIG_STM32_TIM1
#endif
#if defined(CONFIG_STM32WL5_TIM2_PWM) || defined (CONFIG_STM32WL5_TIM2_ADC) || \
defined(CONFIG_STM32WL5_TIM2_DAC) || defined(CONFIG_STM32WL5_TIM2_QE)
# undef CONFIG_STM32WL5_TIM2
#if defined(CONFIG_STM32_TIM2_PWM) || defined (CONFIG_STM32_TIM2_ADC) || \
defined(CONFIG_STM32_TIM2_DAC) || defined(CONFIG_STM32_TIM2_QE)
# undef CONFIG_STM32_TIM2
#endif
#if defined(CONFIG_STM32WL5_TIM3_PWM) || defined (CONFIG_STM32WL5_TIM3_ADC) || \
defined(CONFIG_STM32WL5_TIM3_DAC) || defined(CONFIG_STM32WL5_TIM3_QE)
# undef CONFIG_STM32WL5_TIM3
#if defined(CONFIG_STM32_TIM3_PWM) || defined (CONFIG_STM32_TIM3_ADC) || \
defined(CONFIG_STM32_TIM3_DAC) || defined(CONFIG_STM32_TIM3_QE)
# undef CONFIG_STM32_TIM3
#endif
#if defined(CONFIG_STM32WL5_TIM4_PWM) || defined (CONFIG_STM32WL5_TIM4_ADC) || \
defined(CONFIG_STM32WL5_TIM4_DAC) || defined(CONFIG_STM32WL5_TIM4_QE)
# undef CONFIG_STM32WL5_TIM4
#if defined(CONFIG_STM32_TIM4_PWM) || defined (CONFIG_STM32_TIM4_ADC) || \
defined(CONFIG_STM32_TIM4_DAC) || defined(CONFIG_STM32_TIM4_QE)
# undef CONFIG_STM32_TIM4
#endif
#if defined(CONFIG_STM32WL5_TIM5_PWM) || defined (CONFIG_STM32WL5_TIM5_ADC) || \
defined(CONFIG_STM32WL5_TIM5_DAC) || defined(CONFIG_STM32WL5_TIM5_QE)
# undef CONFIG_STM32WL5_TIM5
#if defined(CONFIG_STM32_TIM5_PWM) || defined (CONFIG_STM32_TIM5_ADC) || \
defined(CONFIG_STM32_TIM5_DAC) || defined(CONFIG_STM32_TIM5_QE)
# undef CONFIG_STM32_TIM5
#endif
#if defined(CONFIG_STM32WL5_TIM6_PWM) || defined (CONFIG_STM32WL5_TIM6_ADC) || \
defined(CONFIG_STM32WL5_TIM6_DAC) || defined(CONFIG_STM32WL5_TIM6_QE)
# undef CONFIG_STM32WL5_TIM6
#if defined(CONFIG_STM32WL5_TIM6_PWM) || defined (CONFIG_STM32_TIM6_ADC) || \
defined(CONFIG_STM32_TIM6_DAC) || defined(CONFIG_STM32WL5_TIM6_QE)
# undef CONFIG_STM32_TIM6
#endif
#if defined(CONFIG_STM32WL5_TIM7_PWM) || defined (CONFIG_STM32WL5_TIM7_ADC) || \
defined(CONFIG_STM32WL5_TIM7_DAC) || defined(CONFIG_STM32WL5_TIM7_QE)
# undef CONFIG_STM32WL5_TIM7
defined(CONFIG_STM32_TIM7_DAC) || defined(CONFIG_STM32WL5_TIM7_QE)
# undef CONFIG_STM32_TIM7
#endif
#if defined(CONFIG_STM32WL5_TIM8_PWM) || defined (CONFIG_STM32WL5_TIM8_ADC) || \
defined(CONFIG_STM32WL5_TIM8_DAC) || defined(CONFIG_STM32WL5_TIM8_QE)
# undef CONFIG_STM32WL5_TIM8
#if defined(CONFIG_STM32_TIM8_PWM) || defined (CONFIG_STM32_TIM8_ADC) || \
defined(CONFIG_STM32_TIM8_DAC) || defined(CONFIG_STM32_TIM8_QE)
# undef CONFIG_STM32_TIM8
#endif
#if defined(CONFIG_STM32WL5_TIM15_PWM) || defined (CONFIG_STM32WL5_TIM15_ADC) || \
#if defined(CONFIG_STM32_TIM15_PWM) || defined (CONFIG_STM32_TIM15_ADC) || \
defined(CONFIG_STM32WL5_TIM15_DAC) || defined(CONFIG_STM32WL5_TIM15_QE)
# undef CONFIG_STM32WL5_TIM15
# undef CONFIG_STM32_TIM15
#endif
#if defined(CONFIG_STM32WL5_TIM16_PWM) || defined (CONFIG_STM32WL5_TIM16_ADC) || \
#if defined(CONFIG_STM32_TIM16_PWM) || defined (CONFIG_STM32WL5_TIM16_ADC) || \
defined(CONFIG_STM32WL5_TIM16_DAC) || defined(CONFIG_STM32WL5_TIM16_QE)
# undef CONFIG_STM32WL5_TIM16
# undef CONFIG_STM32_TIM16
#endif
#if defined(CONFIG_STM32WL5_TIM17_PWM) || defined (CONFIG_STM32WL5_TIM17_ADC) || \
#if defined(CONFIG_STM32_TIM17_PWM) || defined (CONFIG_STM32WL5_TIM17_ADC) || \
defined(CONFIG_STM32WL5_TIM17_DAC) || defined(CONFIG_STM32WL5_TIM17_QE)
# undef CONFIG_STM32WL5_TIM17
# undef CONFIG_STM32_TIM17
#endif
#if defined(CONFIG_STM32WL5_TIM1)
#if defined(CONFIG_STM32_TIM1)
# if defined(GPIO_TIM1_CH1OUT) ||defined(GPIO_TIM1_CH2OUT)||\
defined(GPIO_TIM1_CH3OUT) ||defined(GPIO_TIM1_CH4OUT)
# define HAVE_TIM1_GPIOCONFIG 1
#endif
#endif
#if defined(CONFIG_STM32WL5_TIM2)
#if defined(CONFIG_STM32_TIM2)
# if defined(GPIO_TIM2_CH1OUT) ||defined(GPIO_TIM2_CH2OUT)||\
defined(GPIO_TIM2_CH3OUT) ||defined(GPIO_TIM2_CH4OUT)
# define HAVE_TIM2_GPIOCONFIG 1
#endif
#endif
#if defined(CONFIG_STM32WL5_TIM3)
#if defined(CONFIG_STM32_TIM3)
# if defined(GPIO_TIM3_CH1OUT) ||defined(GPIO_TIM3_CH2OUT)||\
defined(GPIO_TIM3_CH3OUT) ||defined(GPIO_TIM3_CH4OUT)
# define HAVE_TIM3_GPIOCONFIG 1
#endif
#endif
#if defined(CONFIG_STM32WL5_TIM4)
#if defined(CONFIG_STM32_TIM4)
# if defined(GPIO_TIM4_CH1OUT) ||defined(GPIO_TIM4_CH2OUT)||\
defined(GPIO_TIM4_CH3OUT) ||defined(GPIO_TIM4_CH4OUT)
# define HAVE_TIM4_GPIOCONFIG 1
#endif
#endif
#if defined(CONFIG_STM32WL5_TIM5)
#if defined(CONFIG_STM32_TIM5)
# if defined(GPIO_TIM5_CH1OUT) ||defined(GPIO_TIM5_CH2OUT)||\
defined(GPIO_TIM5_CH3OUT) ||defined(GPIO_TIM5_CH4OUT)
# define HAVE_TIM5_GPIOCONFIG 1
#endif
#endif
#if defined(CONFIG_STM32WL5_TIM8)
#if defined(CONFIG_STM32_TIM8)
# if defined(GPIO_TIM8_CH1OUT) ||defined(GPIO_TIM8_CH2OUT)||\
defined(GPIO_TIM8_CH3OUT) ||defined(GPIO_TIM8_CH4OUT)
# define HAVE_TIM8_GPIOCONFIG 1
#endif
#endif
#if defined(CONFIG_STM32WL5_TIM15)
#if defined(CONFIG_STM32_TIM15)
# if defined(GPIO_TIM15_CH1OUT) ||defined(GPIO_TIM15_CH2OUT)||\
defined(GPIO_TIM15_CH3OUT) ||defined(GPIO_TIM15_CH4OUT)
# define HAVE_TIM15_GPIOCONFIG 1
#endif
#endif
#if defined(CONFIG_STM32WL5_TIM16)
#if defined(CONFIG_STM32_TIM16)
# if defined(GPIO_TIM16_CH1OUT) ||defined(GPIO_TIM16_CH2OUT)||\
defined(GPIO_TIM16_CH3OUT) ||defined(GPIO_TIM16_CH4OUT)
# define HAVE_TIM16_GPIOCONFIG 1
#endif
#endif
#if defined(CONFIG_STM32WL5_TIM17)
#if defined(CONFIG_STM32_TIM17)
# if defined(GPIO_TIM17_CH1OUT) ||defined(GPIO_TIM17_CH2OUT)||\
defined(GPIO_TIM17_CH3OUT) ||defined(GPIO_TIM17_CH4OUT)
# define HAVE_TIM17_GPIOCONFIG 1
@ -196,12 +196,12 @@
* intended for some other purpose.
*/
#if defined(CONFIG_STM32WL5_TIM1) || defined(CONFIG_STM32WL5_TIM2) || \
defined(CONFIG_STM32WL5_TIM3) || defined(CONFIG_STM32WL5_TIM4) || \
defined(CONFIG_STM32WL5_TIM5) || defined(CONFIG_STM32WL5_TIM6) || \
defined(CONFIG_STM32WL5_TIM7) || defined(CONFIG_STM32WL5_TIM8) || \
defined(CONFIG_STM32WL5_TIM15) || defined(CONFIG_STM32WL5_TIM16) || \
defined(CONFIG_STM32WL5_TIM17)
#if defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM2) || \
defined(CONFIG_STM32_TIM3) || defined(CONFIG_STM32_TIM4) || \
defined(CONFIG_STM32_TIM5) || defined(CONFIG_STM32_TIM6) || \
defined(CONFIG_STM32_TIM7) || defined(CONFIG_STM32_TIM8) || \
defined(CONFIG_STM32_TIM15) || defined(CONFIG_STM32_TIM16) || \
defined(CONFIG_STM32_TIM17)
/****************************************************************************
* Private Types
@ -302,7 +302,7 @@ static const struct stm32_tim_ops_s stm32_tim_ops =
.checkint = stm32_tim_checkint,
};
#ifdef CONFIG_STM32WL5_TIM1
#ifdef CONFIG_STM32_TIM1
struct stm32_tim_priv_s stm32_tim1_priv =
{
.ops = &stm32_tim_ops,
@ -310,7 +310,7 @@ struct stm32_tim_priv_s stm32_tim1_priv =
.base = STM32_TIM1_BASE,
};
#endif
#ifdef CONFIG_STM32WL5_TIM2
#ifdef CONFIG_STM32_TIM2
struct stm32_tim_priv_s stm32_tim2_priv =
{
.ops = &stm32_tim_ops,
@ -319,7 +319,7 @@ struct stm32_tim_priv_s stm32_tim2_priv =
};
#endif
#ifdef CONFIG_STM32WL5_TIM3
#ifdef CONFIG_STM32_TIM3
struct stm32_tim_priv_s stm32_tim3_priv =
{
.ops = &stm32_tim_ops,
@ -328,7 +328,7 @@ struct stm32_tim_priv_s stm32_tim3_priv =
};
#endif
#ifdef CONFIG_STM32WL5_TIM4
#ifdef CONFIG_STM32_TIM4
struct stm32_tim_priv_s stm32_tim4_priv =
{
.ops = &stm32_tim_ops,
@ -337,7 +337,7 @@ struct stm32_tim_priv_s stm32_tim4_priv =
};
#endif
#ifdef CONFIG_STM32WL5_TIM5
#ifdef CONFIG_STM32_TIM5
struct stm32_tim_priv_s stm32_tim5_priv =
{
.ops = &stm32_tim_ops,
@ -346,7 +346,7 @@ struct stm32_tim_priv_s stm32_tim5_priv =
};
#endif
#ifdef CONFIG_STM32WL5_TIM6
#ifdef CONFIG_STM32_TIM6
struct stm32_tim_priv_s stm32_tim6_priv =
{
.ops = &stm32_tim_ops,
@ -355,7 +355,7 @@ struct stm32_tim_priv_s stm32_tim6_priv =
};
#endif
#ifdef CONFIG_STM32WL5_TIM7
#ifdef CONFIG_STM32_TIM7
struct stm32_tim_priv_s stm32_tim7_priv =
{
.ops = &stm32_tim_ops,
@ -364,7 +364,7 @@ struct stm32_tim_priv_s stm32_tim7_priv =
};
#endif
#ifdef CONFIG_STM32WL5_TIM8
#ifdef CONFIG_STM32_TIM8
struct stm32_tim_priv_s stm32_tim8_priv =
{
.ops = &stm32_tim_ops,
@ -373,7 +373,7 @@ struct stm32_tim_priv_s stm32_tim8_priv =
};
#endif
#ifdef CONFIG_STM32WL5_TIM15
#ifdef CONFIG_STM32_TIM15
struct stm32_tim_priv_s stm32_tim15_priv =
{
.ops = &stm32_tim_ops,
@ -382,7 +382,7 @@ struct stm32_tim_priv_s stm32_tim15_priv =
};
#endif
#ifdef CONFIG_STM32WL5_TIM16
#ifdef CONFIG_STM32_TIM16
struct stm32_tim_priv_s stm32_tim16_priv =
{
.ops = &stm32_tim_ops,
@ -391,7 +391,7 @@ struct stm32_tim_priv_s stm32_tim16_priv =
};
#endif
#ifdef CONFIG_STM32WL5_TIM17
#ifdef CONFIG_STM32_TIM17
struct stm32_tim_priv_s stm32_tim17_priv =
{
.ops = &stm32_tim_ops,
@ -656,66 +656,66 @@ static int stm32_tim_setclock(struct stm32_tim_dev_s *dev,
switch (((struct stm32_tim_priv_s *)dev)->base)
{
#ifdef CONFIG_STM32WL5_TIM1
#ifdef CONFIG_STM32_TIM1
case STM32_TIM1_BASE:
freqin = BOARD_TIM1_FREQUENCY;
break;
#endif
#ifdef CONFIG_STM32WL5_TIM2
#ifdef CONFIG_STM32_TIM2
case STM32_TIM2_BASE:
freqin = BOARD_TIM2_FREQUENCY;
break;
#endif
#ifdef CONFIG_STM32WL5_TIM3
#ifdef CONFIG_STM32_TIM3
case STM32_TIM3_BASE:
freqin = BOARD_TIM3_FREQUENCY;
break;
#endif
#ifdef CONFIG_STM32WL5_TIM4
#ifdef CONFIG_STM32_TIM4
case STM32_TIM4_BASE:
freqin = BOARD_TIM4_FREQUENCY;
break;
#endif
#ifdef CONFIG_STM32WL5_TIM5
#ifdef CONFIG_STM32_TIM5
case STM32_TIM5_BASE:
freqin = BOARD_TIM5_FREQUENCY;
break;
#endif
#ifdef CONFIG_STM32WL5_TIM6
#ifdef CONFIG_STM32_TIM6
case STM32_TIM6_BASE:
freqin = BOARD_TIM6_FREQUENCY;
break;
#endif
#ifdef CONFIG_STM32WL5_TIM7
#ifdef CONFIG_STM32_TIM7
case STM32_TIM7_BASE:
freqin = BOARD_TIM7_FREQUENCY;
break;
#endif
#ifdef CONFIG_STM32WL5_TIM8
#ifdef CONFIG_STM32_TIM8
case STM32_TIM8_BASE:
freqin = BOARD_TIM8_FREQUENCY;
break;
#endif
#ifdef CONFIG_STM32WL5_TIM15
#ifdef CONFIG_STM32_TIM15
case STM32_TIM15_BASE:
freqin = BOARD_TIM15_FREQUENCY;
break;
#endif
#ifdef CONFIG_STM32WL5_TIM16
#ifdef CONFIG_STM32_TIM16
case STM32_TIM16_BASE:
freqin = BOARD_TIM16_FREQUENCY;
break;
#endif
#ifdef CONFIG_STM32WL5_TIM17
#ifdef CONFIG_STM32_TIM17
case STM32_TIM17_BASE:
freqin = BOARD_TIM17_FREQUENCY;
break;
@ -771,64 +771,64 @@ static uint32_t stm32_tim_getclock(struct stm32_tim_dev_s *dev)
switch (((struct stm32_tim_priv_s *)dev)->base)
{
#ifdef CONFIG_STM32WL5_TIM1
#ifdef CONFIG_STM32_TIM1
case STM32_TIM1_BASE:
freqin = BOARD_TIM1_FREQUENCY;
break;
#endif
#ifdef CONFIG_STM32WL5_TIM2
#ifdef CONFIG_STM32_TIM2
case STM32_TIM2_BASE:
freqin = BOARD_TIM2_FREQUENCY;
break;
#endif
#ifdef CONFIG_STM32WL5_TIM3
#ifdef CONFIG_STM32_TIM3
case STM32_TIM3_BASE:
freqin = BOARD_TIM3_FREQUENCY;
break;
#endif
#ifdef CONFIG_STM32WL5_TIM4
#ifdef CONFIG_STM32_TIM4
case STM32_TIM4_BASE:
freqin = BOARD_TIM4_FREQUENCY;
break;
#endif
#ifdef CONFIG_STM32WL5_TIM5
#ifdef CONFIG_STM32_TIM5
case STM32_TIM5_BASE:
freqin = BOARD_TIM5_FREQUENCY;
break;
#endif
#ifdef CONFIG_STM32WL5_TIM6
#ifdef CONFIG_STM32_TIM6
case STM32_TIM6_BASE:
freqin = BOARD_TIM6_FREQUENCY;
break;
#endif
#ifdef CONFIG_STM32WL5_TIM7
#ifdef CONFIG_STM32_TIM7
case STM32_TIM7_BASE:
freqin = BOARD_TIM7_FREQUENCY;
break;
#endif
#ifdef CONFIG_STM32WL5_TIM8
#ifdef CONFIG_STM32_TIM8
case STM32_TIM8_BASE:
freqin = BOARD_TIM8_FREQUENCY;
break;
#endif
#ifdef CONFIG_STM32WL5_TIM15
#ifdef CONFIG_STM32_TIM15
case STM32_TIM15_BASE:
freqin = BOARD_TIM15_FREQUENCY;
break;
#endif
#ifdef CONFIG_STM32WL5_TIM16
#ifdef CONFIG_STM32_TIM16
case STM32_TIM16_BASE:
freqin = BOARD_TIM16_FREQUENCY;
break;
#endif
#ifdef CONFIG_STM32WL5_TIM17
#ifdef CONFIG_STM32_TIM17
case STM32_TIM17_BASE:
freqin = BOARD_TIM17_FREQUENCY;
break;
@ -877,13 +877,13 @@ static uint32_t stm32_tim_getcounter(struct stm32_tim_dev_s *dev)
* reset it it result when not TIM2 or TIM5.
*/
#if defined(CONFIG_STM32WL5_TIM2) || defined(CONFIG_STM32WL5_TIM5)
#if defined(CONFIG_STM32_TIM2) || defined(CONFIG_STM32_TIM5)
switch (((struct stm32_tim_priv_s *)dev)->base)
{
#ifdef CONFIG_STM32WL5_TIM2
#ifdef CONFIG_STM32_TIM2
case STM32_TIM2_BASE:
#endif
#ifdef CONFIG_STM32WL5_TIM5
#ifdef CONFIG_STM32_TIM5
case STM32_TIM5_BASE:
#endif
return counter;
@ -989,7 +989,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev,
switch (((struct stm32_tim_priv_s *)dev)->base)
{
#ifdef CONFIG_STM32WL5_TIM1
#ifdef CONFIG_STM32_TIM1
case STM32_TIM1_BASE:
switch (channel)
{
@ -1022,7 +1022,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev,
}
break;
#endif
#ifdef CONFIG_STM32WL5_TIM2
#ifdef CONFIG_STM32_TIM2
case STM32_TIM2_BASE:
switch (channel)
{
@ -1055,7 +1055,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev,
}
break;
#endif
#ifdef CONFIG_STM32WL5_TIM3
#ifdef CONFIG_STM32_TIM3
case STM32_TIM3_BASE:
switch (channel)
{
@ -1088,7 +1088,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev,
}
break;
#endif
#ifdef CONFIG_STM32WL5_TIM4
#ifdef CONFIG_STM32_TIM4
case STM32_TIM4_BASE:
switch (channel)
{
@ -1120,7 +1120,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev,
}
break;
#endif
#ifdef CONFIG_STM32WL5_TIM5
#ifdef CONFIG_STM32_TIM5
case STM32_TIM5_BASE:
switch (channel)
{
@ -1153,7 +1153,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev,
}
break;
#endif
#ifdef CONFIG_STM32WL5_TIM8
#ifdef CONFIG_STM32_TIM8
case STM32_TIM8_BASE:
switch (channel)
{
@ -1186,7 +1186,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev,
}
break;
#endif
#ifdef CONFIG_STM32WL5_TIM15
#ifdef CONFIG_STM32_TIM15
case STM32_TIM15_BASE:
switch (channel)
{
@ -1219,7 +1219,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev,
}
break;
#endif
#ifdef CONFIG_STM32WL5_TIM16
#ifdef CONFIG_STM32_TIM16
case STM32_TIM16_BASE:
switch (channel)
{
@ -1252,7 +1252,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev,
}
break;
#endif
#ifdef CONFIG_STM32WL5_TIM17
#ifdef CONFIG_STM32_TIM17
case STM32_TIM17_BASE:
switch (channel)
{
@ -1368,65 +1368,65 @@ static int stm32_tim_setisr(struct stm32_tim_dev_s *dev,
switch (((struct stm32_tim_priv_s *)dev)->base)
{
#ifdef CONFIG_STM32WL5_TIM1
#ifdef CONFIG_STM32_TIM1
case STM32_TIM1_BASE:
vectorno = STM32_IRQ_TIM1UP;
break;
#endif
#ifdef CONFIG_STM32WL5_TIM2
#ifdef CONFIG_STM32_TIM2
case STM32_TIM2_BASE:
vectorno = STM32_IRQ_TIM2;
break;
#endif
#ifdef CONFIG_STM32WL5_TIM3
#ifdef CONFIG_STM32_TIM3
case STM32_TIM3_BASE:
vectorno = STM32_IRQ_TIM3;
break;
#endif
#ifdef CONFIG_STM32WL5_TIM4
#ifdef CONFIG_STM32_TIM4
case STM32_TIM4_BASE:
vectorno = STM32_IRQ_TIM4;
break;
#endif
#ifdef CONFIG_STM32WL5_TIM5
#ifdef CONFIG_STM32_TIM5
case STM32_TIM5_BASE:
vectorno = STM32_IRQ_TIM5;
break;
#endif
#ifdef CONFIG_STM32WL5_TIM6
#ifdef CONFIG_STM32_TIM6
case STM32_TIM6_BASE:
vectorno = STM32_IRQ_TIM6;
break;
#endif
#ifdef CONFIG_STM32WL5_TIM7
#ifdef CONFIG_STM32_TIM7
case STM32_TIM7_BASE:
vectorno = STM32_IRQ_TIM7;
break;
#endif
#ifdef CONFIG_STM32WL5_TIM8
#ifdef CONFIG_STM32_TIM8
case STM32_TIM8_BASE:
vectorno = STM32_IRQ_TIM8UP;
break;
#endif
#ifdef CONFIG_STM32WL5_TIM15
#ifdef CONFIG_STM32_TIM15
case STM32_TIM15_BASE:
vectorno = STM32_IRQ_TIM15;
break;
#endif
#ifdef CONFIG_STM32WL5_TIM16
#ifdef CONFIG_STM32_TIM16
case STM32_TIM16_BASE:
vectorno = STM32_IRQ_TIM16;
break;
#endif
#ifdef CONFIG_STM32WL5_TIM17
#ifdef CONFIG_STM32_TIM17
case STM32_TIM17_BASE:
vectorno = STM32_IRQ_TIM17;
break;
@ -1511,76 +1511,76 @@ struct stm32_tim_dev_s *stm32_tim_init(int timer)
switch (timer)
{
#ifdef CONFIG_STM32WL5_TIM1
#ifdef CONFIG_STM32_TIM1
case 1:
dev = (struct stm32_tim_dev_s *)&stm32_tim1_priv;
modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM1EN);
break;
#endif
#ifdef CONFIG_STM32WL5_TIM2
#ifdef CONFIG_STM32_TIM2
case 2:
dev = (struct stm32_tim_dev_s *)&stm32_tim2_priv;
modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM2EN);
break;
#endif
#ifdef CONFIG_STM32WL5_TIM3
#ifdef CONFIG_STM32_TIM3
case 3:
dev = (struct stm32_tim_dev_s *)&stm32_tim3_priv;
modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM3EN);
break;
#endif
#ifdef CONFIG_STM32WL5_TIM4
#ifdef CONFIG_STM32_TIM4
case 4:
dev = (struct stm32_tim_dev_s *)&stm32_tim4_priv;
modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM4EN);
break;
#endif
#ifdef CONFIG_STM32WL5_TIM5
#ifdef CONFIG_STM32_TIM5
case 5:
dev = (struct stm32_tim_dev_s *)&stm32_tim5_priv;
modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM5EN);
break;
#endif
#ifdef CONFIG_STM32WL5_TIM6
#ifdef CONFIG_STM32_TIM6
case 6:
dev = (struct stm32_tim_dev_s *)&stm32_tim6_priv;
modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM6EN);
break;
#endif
#ifdef CONFIG_STM32WL5_TIM7
#ifdef CONFIG_STM32_TIM7
case 7:
dev = (struct stm32_tim_dev_s *)&stm32_tim7_priv;
modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM7EN);
break;
#endif
#ifdef CONFIG_STM32WL5_TIM8
#ifdef CONFIG_STM32_TIM8
case 8:
dev = (struct stm32_tim_dev_s *)&stm32_tim8_priv;
modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM8EN);
break;
#endif
#ifdef CONFIG_STM32WL5_TIM15
#ifdef CONFIG_STM32_TIM15
case 15:
dev = (struct stm32_tim_dev_s *)&stm32_tim15_priv;
modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM15EN);
break;
#endif
#ifdef CONFIG_STM32WL5_TIM16
#ifdef CONFIG_STM32_TIM16
case 16:
dev = (struct stm32_tim_dev_s *)&stm32_tim16_priv;
modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM16EN);
break;
#endif
#ifdef CONFIG_STM32WL5_TIM17
#ifdef CONFIG_STM32_TIM17
case 17:
dev = (struct stm32_tim_dev_s *)&stm32_tim17_priv;
modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM17EN);
@ -1618,66 +1618,66 @@ int stm32_tim_deinit(struct stm32_tim_dev_s *dev)
switch (((struct stm32_tim_priv_s *)dev)->base)
{
#ifdef CONFIG_STM32WL5_TIM1
#ifdef CONFIG_STM32_TIM1
case STM32_TIM1_BASE:
modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM1EN, 0);
break;
#endif
#ifdef CONFIG_STM32WL5_TIM2
#ifdef CONFIG_STM32_TIM2
case STM32_TIM2_BASE:
modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM2EN, 0);
break;
#endif
#ifdef CONFIG_STM32WL5_TIM3
#ifdef CONFIG_STM32_TIM3
case STM32_TIM3_BASE:
modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM3EN, 0);
break;
#endif
#ifdef CONFIG_STM32WL5_TIM4
#ifdef CONFIG_STM32_TIM4
case STM32_TIM4_BASE:
modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM4EN, 0);
break;
#endif
#ifdef CONFIG_STM32WL5_TIM5
#ifdef CONFIG_STM32_TIM5
case STM32_TIM5_BASE:
modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM5EN, 0);
break;
#endif
#ifdef CONFIG_STM32WL5_TIM6
#ifdef CONFIG_STM32_TIM6
case STM32_TIM6_BASE:
modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM6EN, 0);
break;
#endif
#ifdef CONFIG_STM32WL5_TIM7
#ifdef CONFIG_STM32_TIM7
case STM32_TIM7_BASE:
modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM7EN, 0);
break;
#endif
#ifdef CONFIG_STM32WL5_TIM8
#ifdef CONFIG_STM32_TIM8
case STM32_TIM8_BASE:
modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM8EN, 0);
break;
#endif
#ifdef CONFIG_STM32WL5_TIM15
#ifdef CONFIG_STM32_TIM15
case STM32_TIM15_BASE:
modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM15EN, 0);
break;
#endif
#ifdef CONFIG_STM32WL5_TIM16
#ifdef CONFIG_STM32_TIM16
case STM32_TIM16_BASE:
modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM16EN, 0);
break;
#endif
#ifdef CONFIG_STM32WL5_TIM17
#ifdef CONFIG_STM32_TIM17
case STM32_TIM17_BASE:
modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM17EN, 0);
break;
@ -1694,4 +1694,4 @@ int stm32_tim_deinit(struct stm32_tim_dev_s *dev)
return OK;
}
#endif /* defined(CONFIG_STM32WL5_TIM1 || ... || TIM17) */
#endif /* defined(CONFIG_STM32_TIM1 || ... || TIM17) */

56
arch/arm/src/stm32wl5/stm32wl5_tim_lowerhalf.c
View file

@ -41,12 +41,12 @@
#include "stm32wl5_tim.h"
#if defined(CONFIG_TIMER) && \
(defined(CONFIG_STM32WL5_TIM1) || defined(CONFIG_STM32WL5_TIM2) || \
defined(CONFIG_STM32WL5_TIM3) || defined(CONFIG_STM32WL5_TIM4) || \
defined(CONFIG_STM32WL5_TIM5) || defined(CONFIG_STM32WL5_TIM6) || \
defined(CONFIG_STM32WL5_TIM7) || defined(CONFIG_STM32WL5_TIM8) || \
defined(CONFIG_STM32WL5_TIM15) || defined(CONFIG_STM32WL5_TIM16) || \
defined(CONFIG_STM32WL5_TIM17))
(defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM2) || \
defined(CONFIG_STM32_TIM3) || defined(CONFIG_STM32_TIM4) || \
defined(CONFIG_STM32_TIM5) || defined(CONFIG_STM32_TIM6) || \
defined(CONFIG_STM32_TIM7) || defined(CONFIG_STM32_TIM8) || \
defined(CONFIG_STM32_TIM15) || defined(CONFIG_STM32_TIM16) || \
defined(CONFIG_STM32_TIM17))
/****************************************************************************
* Pre-processor Definitions
@ -118,7 +118,7 @@ static const struct timer_ops_s g_timer_ops =
.ioctl = NULL,
};
#ifdef CONFIG_STM32WL5_TIM1
#ifdef CONFIG_STM32_TIM1
static struct stm32_lowerhalf_s g_tim1_lowerhalf =
{
.ops = &g_timer_ops,
@ -126,7 +126,7 @@ static struct stm32_lowerhalf_s g_tim1_lowerhalf =
};
#endif
#ifdef CONFIG_STM32WL5_TIM2
#ifdef CONFIG_STM32_TIM2
static struct stm32_lowerhalf_s g_tim2_lowerhalf =
{
.ops = &g_timer_ops,
@ -134,7 +134,7 @@ static struct stm32_lowerhalf_s g_tim2_lowerhalf =
};
#endif
#ifdef CONFIG_STM32WL5_TIM3
#ifdef CONFIG_STM32_TIM3
static struct stm32_lowerhalf_s g_tim3_lowerhalf =
{
.ops = &g_timer_ops,
@ -142,7 +142,7 @@ static struct stm32_lowerhalf_s g_tim3_lowerhalf =
};
#endif
#ifdef CONFIG_STM32WL5_TIM4
#ifdef CONFIG_STM32_TIM4
static struct stm32_lowerhalf_s g_tim4_lowerhalf =
{
.ops = &g_timer_ops,
@ -150,7 +150,7 @@ static struct stm32_lowerhalf_s g_tim4_lowerhalf =
};
#endif
#ifdef CONFIG_STM32WL5_TIM5
#ifdef CONFIG_STM32_TIM5
static struct stm32_lowerhalf_s g_tim5_lowerhalf =
{
.ops = &g_timer_ops,
@ -158,7 +158,7 @@ static struct stm32_lowerhalf_s g_tim5_lowerhalf =
};
#endif
#ifdef CONFIG_STM32WL5_TIM6
#ifdef CONFIG_STM32_TIM6
static struct stm32_lowerhalf_s g_tim6_lowerhalf =
{
.ops = &g_timer_ops,
@ -166,7 +166,7 @@ static struct stm32_lowerhalf_s g_tim6_lowerhalf =
};
#endif
#ifdef CONFIG_STM32WL5_TIM7
#ifdef CONFIG_STM32_TIM7
static struct stm32_lowerhalf_s g_tim7_lowerhalf =
{
.ops = &g_timer_ops,
@ -174,7 +174,7 @@ static struct stm32_lowerhalf_s g_tim7_lowerhalf =
};
#endif
#ifdef CONFIG_STM32WL5_TIM8
#ifdef CONFIG_STM32_TIM8
static struct stm32_lowerhalf_s g_tim8_lowerhalf =
{
.ops = &g_timer_ops,
@ -182,7 +182,7 @@ static struct stm32_lowerhalf_s g_tim8_lowerhalf =
};
#endif
#ifdef CONFIG_STM32WL5_TIM15
#ifdef CONFIG_STM32_TIM15
static struct stm32_lowerhalf_s g_tim15_lowerhalf =
{
.ops = &g_timer_ops,
@ -190,7 +190,7 @@ static struct stm32_lowerhalf_s g_tim15_lowerhalf =
};
#endif
#ifdef CONFIG_STM32WL5_TIM16
#ifdef CONFIG_STM32_TIM16
static struct stm32_lowerhalf_s g_tim16_lowerhalf =
{
.ops = &g_timer_ops,
@ -198,7 +198,7 @@ static struct stm32_lowerhalf_s g_tim16_lowerhalf =
};
#endif
#ifdef CONFIG_STM32WL5_TIM17
#ifdef CONFIG_STM32_TIM17
static struct stm32_lowerhalf_s g_tim17_lowerhalf =
{
.ops = &g_timer_ops,
@ -503,66 +503,66 @@ int stm32_timer_initialize(const char *devpath, int timer)
switch (timer)
{
#ifdef CONFIG_STM32WL5_TIM1
#ifdef CONFIG_STM32_TIM1
case 1:
lower = &g_tim1_lowerhalf;
break;
#endif
#ifdef CONFIG_STM32WL5_TIM2
#ifdef CONFIG_STM32_TIM2
case 2:
lower = &g_tim2_lowerhalf;
break;
#endif
#ifdef CONFIG_STM32WL5_TIM3
#ifdef CONFIG_STM32_TIM3
case 3:
lower = &g_tim3_lowerhalf;
break;
#endif
#ifdef CONFIG_STM32WL5_TIM4
#ifdef CONFIG_STM32_TIM4
case 4:
lower = &g_tim4_lowerhalf;
break;
#endif
#ifdef CONFIG_STM32WL5_TIM5
#ifdef CONFIG_STM32_TIM5
case 5:
lower = &g_tim5_lowerhalf;
break;
#endif
#ifdef CONFIG_STM32WL5_TIM6
#ifdef CONFIG_STM32_TIM6
case 6:
lower = &g_tim6_lowerhalf;
break;
#endif
#ifdef CONFIG_STM32WL5_TIM7
#ifdef CONFIG_STM32_TIM7
case 7:
lower = &g_tim7_lowerhalf;
break;
#endif
#ifdef CONFIG_STM32WL5_TIM8
#ifdef CONFIG_STM32_TIM8
case 8:
lower = &g_tim8_lowerhalf;
break;
#endif
#ifdef CONFIG_STM32WL5_TIM15
#ifdef CONFIG_STM32_TIM15
case 15:
lower = &g_tim15_lowerhalf;
break;
#endif
#ifdef CONFIG_STM32WL5_TIM16
#ifdef CONFIG_STM32_TIM16
case 16:
lower = &g_tim16_lowerhalf;
break;
#endif
#ifdef CONFIG_STM32WL5_TIM17
#ifdef CONFIG_STM32_TIM17
case 17:
lower = &g_tim17_lowerhalf;
break;

54
arch/arm/src/stm32wl5/stm32wl5_uart.h
View file

@ -42,42 +42,42 @@
* device.
*/
#if !defined(CONFIG_STM32WL5_HAVE_USART2)
# undef CONFIG_STM32WL5_USART2
#if !defined(CONFIG_STM32_HAVE_USART2)
# undef CONFIG_STM32_USART2
#endif
#if !defined(CONFIG_STM32WL5_HAVE_USART1)
# undef CONFIG_STM32WL5_USART1
#if !defined(CONFIG_STM32_HAVE_USART1)
# undef CONFIG_STM32_USART1
#endif
#if !defined(CONFIG_STM32WL5_HAVE_LPUART1)
# undef CONFIG_STM32WL5_LPUART1
#if !defined(CONFIG_STM32_HAVE_LPUART1)
# undef CONFIG_STM32_LPUART1
#endif
/* Sanity checks */
#if !defined(CONFIG_STM32WL5_LPUART1)
# undef CONFIG_STM32WL5_LPUART1_SERIALDRIVER
# undef CONFIG_STM32WL5_LPUART1_1WIREDRIVER
#if !defined(CONFIG_STM32_LPUART1)
# undef CONFIG_STM32_LPUART1_SERIALDRIVER
# undef CONFIG_STM32_LPUART1_1WIREDRIVER
#endif
#if !defined(CONFIG_STM32WL5_USART1)
# undef CONFIG_STM32WL5_USART1_SERIALDRIVER
# undef CONFIG_STM32WL5_USART1_1WIREDRIVER
#if !defined(CONFIG_STM32_USART1)
# undef CONFIG_STM32_USART1_SERIALDRIVER
# undef CONFIG_STM32_USART1_1WIREDRIVER
#endif
#if !defined(CONFIG_STM32WL5_USART2)
# undef CONFIG_STM32WL5_USART2_SERIALDRIVER
# undef CONFIG_STM32WL5_USART2_1WIREDRIVER
#if !defined(CONFIG_STM32_USART2)
# undef CONFIG_STM32_USART2_SERIALDRIVER
# undef CONFIG_STM32_USART2_1WIREDRIVER
#endif
/* Is there a USART enabled? */
#if defined(CONFIG_STM32WL5_LPUART1) || \
defined(CONFIG_STM32WL5_USART1) || \
defined(CONFIG_STM32WL5_USART2)
#if defined(CONFIG_STM32_LPUART1) || \
defined(CONFIG_STM32_USART1) || \
defined(CONFIG_STM32_USART2)
# define HAVE_UART 1
#endif
/* Is there a serial console? */
#if defined(CONFIG_LPUART1_SERIAL_CONSOLE) && defined(CONFIG_STM32WL5_LPUART1_SERIALDRIVER)
#if defined(CONFIG_LPUART1_SERIAL_CONSOLE) && defined(CONFIG_STM32_LPUART1_SERIALDRIVER)
# undef CONFIG_USART1_SERIAL_CONSOLE
# undef CONFIG_USART2_SERIAL_CONSOLE
# undef CONFIG_USART3_SERIAL_CONSOLE
@ -85,7 +85,7 @@
# undef CONFIG_UART5_SERIAL_CONSOLE
# define CONSOLE_UART 1
# define HAVE_CONSOLE 1
#elif defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_STM32WL5_USART1_SERIALDRIVER)
#elif defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART1_SERIALDRIVER)
# undef CONFIG_LPUART1_SERIAL_CONSOLE
# undef CONFIG_USART2_SERIAL_CONSOLE
# undef CONFIG_USART3_SERIAL_CONSOLE
@ -93,7 +93,7 @@
# undef CONFIG_UART5_SERIAL_CONSOLE
# define CONSOLE_UART 2
# define HAVE_CONSOLE 1
#elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(CONFIG_STM32WL5_USART2_SERIALDRIVER)
#elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART2_SERIALDRIVER)
# undef CONFIG_USART1_SERIAL_CONSOLE
# undef CONFIG_USART3_SERIAL_CONSOLE
# undef CONFIG_UART4_SERIAL_CONSOLE
@ -121,15 +121,15 @@
/* Disable the DMA configuration on all unused USARTs */
#ifndef CONFIG_STM32WL5_LPUART1_SERIALDRIVER
#ifndef CONFIG_STM32_LPUART1_SERIALDRIVER
# undef CONFIG_LPUART1_RXDMA
#endif
#ifndef CONFIG_STM32WL5_USART1_SERIALDRIVER
#ifndef CONFIG_STM32_USART1_SERIALDRIVER
# undef CONFIG_USART1_RXDMA
#endif
#ifndef CONFIG_STM32WL5_USART2_SERIALDRIVER
#ifndef CONFIG_STM32_USART2_SERIALDRIVER
# undef CONFIG_USART2_RXDMA
#endif
@ -156,11 +156,11 @@
/* Is DMA used on all (enabled) USARTs */
#define SERIAL_HAVE_ONLY_DMA 1
#if defined(CONFIG_STM32WL5_LPUART1_SERIALDRIVER) && !defined(CONFIG_LPUART1_RXDMA)
#if defined(CONFIG_STM32_LPUART1_SERIALDRIVER) && !defined(CONFIG_LPUART1_RXDMA)
# undef SERIAL_HAVE_ONLY_DMA
#elif defined(CONFIG_STM32WL5_USART1_SERIALDRIVER) && !defined(CONFIG_USART1_RXDMA)
#elif defined(CONFIG_STM32_USART1_SERIALDRIVER) && !defined(CONFIG_USART1_RXDMA)
# undef SERIAL_HAVE_ONLY_DMA
#elif defined(CONFIG_STM32WL5_USART2_SERIALDRIVER) && !defined(CONFIG_USART2_RXDMA)
#elif defined(CONFIG_STM32_USART2_SERIALDRIVER) && !defined(CONFIG_USART2_RXDMA)
# undef SERIAL_HAVE_ONLY_DMA
#endif

12
boards/arm/stm32wl5/nucleo-wl55jc/Kconfig
View file

@ -24,7 +24,7 @@ config ARCH_BOARD_ENABLE_CPU2
menuconfig ARCH_BOARD_IPCC
bool "Enabled IPCC"
select IPCC
select STM32WL5_IPCC
select STM32_IPCC
default n
---help---
Enables IPCC (inter processor communication controller)
@ -52,7 +52,7 @@ config ARCH_BOARD_IPCC_CHAN1_TXBUF
config ARCH_BOARD_IPCC_CHAN2
bool "Enable channel 2"
default n
select STM32WL5_IPCC_CHAN2
select STM32_IPCC_CHAN2
if ARCH_BOARD_IPCC_CHAN2
@ -69,7 +69,7 @@ config ARCH_BOARD_IPCC_CHAN2_TXBUF
config ARCH_BOARD_IPCC_CHAN3
bool "Enable channel 3"
default n
select STM32WL5_IPCC_CHAN3
select STM32_IPCC_CHAN3
if ARCH_BOARD_IPCC_CHAN3
@ -86,7 +86,7 @@ config ARCH_BOARD_IPCC_CHAN3_TXBUF
config ARCH_BOARD_IPCC_CHAN4
bool "Enable channel 4"
default n
select STM32WL5_IPCC_CHAN4
select STM32_IPCC_CHAN4
if ARCH_BOARD_IPCC_CHAN4
@ -103,7 +103,7 @@ config ARCH_BOARD_IPCC_CHAN4_TXBUF
config ARCH_BOARD_IPCC_CHAN5
bool "Enable channel 5"
default n
select STM32WL5_IPCC_CHAN5
select STM32_IPCC_CHAN5
if ARCH_BOARD_IPCC_CHAN5
@ -120,7 +120,7 @@ config ARCH_BOARD_IPCC_CHAN5_TXBUF
config ARCH_BOARD_IPCC_CHAN6
bool "Enable channel 6"
default n
select STM32WL5_IPCC_CHAN6
select STM32_IPCC_CHAN6
if ARCH_BOARD_IPCC_CHAN6

3
boards/arm/stm32wl5/nucleo-wl55jc/configs/demo/defconfig
View file

@ -28,6 +28,7 @@ CONFIG_ARCH_BOARD_NUCLEO_WL55JC=y
CONFIG_ARCH_BOARD_NUCLEO_WL55JC_DEMO_LED_IRQ=y
CONFIG_ARCH_BUTTONS=y
CONFIG_ARCH_CHIP="stm32wl5"
CONFIG_ARCH_CHIP_STM32=y
CONFIG_ARCH_CHIP_STM32WL55JC_CPU1=y
CONFIG_ARCH_CHIP_STM32WL5=y
CONFIG_ARCH_IRQBUTTONS=y
@ -48,7 +49,7 @@ CONFIG_NSH_BUILTIN_APPS=y
CONFIG_RAM_SIZE=32768
CONFIG_RAM_START=0x20000000
CONFIG_RAW_BINARY=y
CONFIG_STM32WL5_LPUART1=y
CONFIG_STM32_LPUART1=y
CONFIG_SYSTEM_CFGDATA=y
CONFIG_SYSTEM_NSH=y
CONFIG_USERLED=y

9
boards/arm/stm32wl5/nucleo-wl55jc/configs/fb/defconfig
View file

@ -12,6 +12,7 @@ CONFIG_ARCH_BOARD_COMMON=y
CONFIG_ARCH_BOARD_NUCLEO_WL55JC=y
CONFIG_ARCH_BUTTONS=y
CONFIG_ARCH_CHIP="stm32wl5"
CONFIG_ARCH_CHIP_STM32=y
CONFIG_ARCH_CHIP_STM32WL55JC_CPU1=y
CONFIG_ARCH_CHIP_STM32WL5=y
CONFIG_BOARD_LOOPSPERMSEC=0
@ -33,9 +34,9 @@ CONFIG_RAM_START=0x20000000
CONFIG_RAW_BINARY=y
CONFIG_SPI=y
CONFIG_SPI_DRIVER=y
CONFIG_STM32WL5_LPUART1=y
CONFIG_STM32WL5_SPI1=y
CONFIG_STM32WL5_SPI2S2=y
CONFIG_STM32WL5_USART1=y
CONFIG_STM32_LPUART1=y
CONFIG_STM32_SPI1=y
CONFIG_STM32_SPI2S2=y
CONFIG_STM32_USART1=y
CONFIG_SYSTEM_NSH=y
CONFIG_VIDEO_FB=y

3
boards/arm/stm32wl5/nucleo-wl55jc/configs/nsh/defconfig
View file

@ -11,6 +11,7 @@ CONFIG_ARCH_BOARD="nucleo-wl55jc"
CONFIG_ARCH_BOARD_NUCLEO_WL55JC=y
CONFIG_ARCH_BUTTONS=y
CONFIG_ARCH_CHIP="stm32wl5"
CONFIG_ARCH_CHIP_STM32=y
CONFIG_ARCH_CHIP_STM32WL55JC_CPU1=y
CONFIG_ARCH_CHIP_STM32WL5=y
CONFIG_BOARD_LOOPSPERMSEC=0
@ -20,5 +21,5 @@ CONFIG_LPUART1_SERIAL_CONSOLE=y
CONFIG_RAM_SIZE=32768
CONFIG_RAM_START=0x20000000
CONFIG_RAW_BINARY=y
CONFIG_STM32WL5_LPUART1=y
CONFIG_STM32_LPUART1=y
CONFIG_SYSTEM_NSH=y

2
boards/arm/stm32wl5/nucleo-wl55jc/src/stm32_boot.c
View file

@ -108,7 +108,7 @@ void board_late_initialize(void)
{
int ret;
#if defined(CONFIG_STM32WL5_SPI1) || defined(CONFIG_STM32WL5_SPI2S2)
#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2S2)
stm32_spidev_initialize();
#endif

16
boards/arm/stm32wl5/nucleo-wl55jc/src/stm32_spi.c
View file

@ -40,7 +40,7 @@
#include "stm32.h"
#include "nucleo-wl55jc.h"
#if defined(CONFIG_STM32WL5_SPI1) || defined(CONFIG_STM32WL5_SPI2S2)
#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2S2)
/****************************************************************************
* Public Data
@ -48,10 +48,10 @@
/* Global driver instances */
#ifdef CONFIG_STM32WL5_SPI1
#ifdef CONFIG_STM32_SPI1
struct spi_dev_s *g_spi1;
#endif
#ifdef CONFIG_STM32WL5_SPI2S2
#ifdef CONFIG_STM32_SPI2S2
struct spi_dev_s *g_spi2;
#endif
@ -70,7 +70,7 @@ struct spi_dev_s *g_spi2;
void weak_function stm32_spidev_initialize(void)
{
#ifdef CONFIG_STM32WL5_SPI1
#ifdef CONFIG_STM32_SPI1
/* Configure SPI-based devices */
g_spi1 = stm32_spibus_initialize(1);
@ -90,7 +90,7 @@ void weak_function stm32_spidev_initialize(void)
#endif
#ifdef CONFIG_STM32WL5_SPI2S2
#ifdef CONFIG_STM32_SPI2S2
/* Configure SPI-based devices */
g_spi2 = stm32_spibus_initialize(2);
@ -123,7 +123,7 @@ void weak_function stm32_spidev_initialize(void)
*
****************************************************************************/
#ifdef CONFIG_STM32WL5_SPI1
#ifdef CONFIG_STM32_SPI1
void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid,
bool selected)
{
@ -178,7 +178,7 @@ int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd)
#endif
#ifdef CONFIG_STM32WL5_SPI2S2
#ifdef CONFIG_STM32_SPI2S2
void stm32_spi2s2select(struct spi_dev_s *dev, uint32_t devid,
bool selected)
{
@ -198,4 +198,4 @@ int stm32_spi2s2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd)
#endif
#endif /* CONFIG_STM32WL5_SPI1 || CONFIG_STM32WL5_SPI2S2 */
#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2S2 */