diff --git a/arch/arm/src/common/stm32/Kconfig b/arch/arm/src/common/stm32/Kconfig index 37c61bcc2c9..92853f2cf52 100644 --- a/arch/arm/src/common/stm32/Kconfig +++ b/arch/arm/src/common/stm32/Kconfig @@ -14,6 +14,72 @@ config STM32_1WIREDRIVER config STM32_HCIUART bool +config STM32_COMMON_LEGACY + bool + default y if ARCH_CHIP_STM32F1 + default y if ARCH_CHIP_STM32F2 + default y if ARCH_CHIP_STM32F3 + default y if ARCH_CHIP_STM32F4 + default y if ARCH_CHIP_STM32G4 + default y if ARCH_CHIP_STM32L1 + +config STM32_COMMON_F0_L0_G0_C0 + bool + default y if ARCH_CHIP_STM32F0 + default y if ARCH_CHIP_STM32L0 + default y if ARCH_CHIP_STM32G0 + default y if ARCH_CHIP_STM32C0 + +config STM32_COMMON_F7_H7 + bool + default y if ARCH_CHIP_STM32F7 + default y if ARCH_CHIP_STM32H7 + +config STM32_COMMON_H7_H5 + bool + default y if ARCH_CHIP_STM32H7 + default y if ARCH_CHIP_STM32H5 + +config STM32_COMMON_F7_H7_H5 + bool + default y if STM32_COMMON_F7_H7 + default y if ARCH_CHIP_STM32H5 + +config STM32_COMMON_L4_L5_U5 + bool + default y if ARCH_CHIP_STM32L4 + default y if ARCH_CHIP_STM32L5 + default y if ARCH_CHIP_STM32U5 + +config STM32_COMMON_L5_U5 + bool + default y if ARCH_CHIP_STM32L5 + default y if ARCH_CHIP_STM32U5 + +config STM32_COMMON_L4_H5_L5_U5 + bool + default y if STM32_COMMON_L4_L5_U5 + default y if ARCH_CHIP_STM32H5 + +config STM32_COMMON_FULL_FEATURED + bool + default y if STM32_COMMON_LEGACY + default y if STM32_COMMON_F0_L0_G0_C0 + default y if STM32_COMMON_F7_H7_H5 + default y if STM32_COMMON_L4_L5_U5 + +config STM32_COMMON_SRAM2_OPTIONS + bool + default y if ARCH_CHIP_STM32L4 + default y if ARCH_CHIP_STM32H5 + default y if ARCH_CHIP_STM32L5 + default y if ARCH_CHIP_STM32U5 && STM32_SRAM2 + +config STM32_COMMON_USART_UNCONFIG_ON_CLOSE + bool + default y if ARCH_CHIP_STM32H5 + default y if ARCH_CHIP_STM32N6 + choice prompt "JTAG Configuration" default STM32_JTAG_DISABLE @@ -579,6 +645,190 @@ config STM32_LPUART1_1WIREDRIVER endchoice # LPUART1 Driver Configuration +choice + prompt "USART4 Driver Configuration" + depends on STM32_USART4 + default STM32_USART4_SERIALDRIVER + +config STM32_USART4_SERIALDRIVER + bool "Standard serial driver" + select USART4_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + select STM32_SERIALDRIVER + +config STM32_USART4_1WIREDRIVER + bool "1-Wire driver" + select STM32_1WIREDRIVER + +endchoice # USART4 Driver Configuration + +choice + prompt "USART5 Driver Configuration" + depends on STM32_USART5 + default STM32_USART5_SERIALDRIVER + +config STM32_USART5_SERIALDRIVER + bool "Standard serial driver" + select USART5_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + select STM32_SERIALDRIVER + +config STM32_USART5_1WIREDRIVER + bool "1-Wire driver" + select STM32_1WIREDRIVER + +endchoice # USART5 Driver Configuration + +choice + prompt "USART7 Driver Configuration" + depends on STM32_USART7 + default STM32_USART7_SERIALDRIVER + +config STM32_USART7_SERIALDRIVER + bool "Standard serial driver" + select USART7_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + select STM32_SERIALDRIVER + +config STM32_USART7_1WIREDRIVER + bool "1-Wire driver" + select STM32_1WIREDRIVER + +endchoice # USART7 Driver Configuration + +choice + prompt "USART8 Driver Configuration" + depends on STM32_USART8 + default STM32_USART8_SERIALDRIVER + +config STM32_USART8_SERIALDRIVER + bool "Standard serial driver" + select USART8_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + select STM32_SERIALDRIVER + +config STM32_USART8_1WIREDRIVER + bool "1-Wire driver" + select STM32_1WIREDRIVER + +endchoice # USART8 Driver Configuration + +choice + prompt "UART7 Driver Configuration" + depends on STM32_COMMON_LEGACY && STM32_UART7 + default STM32_UART7_SERIALDRIVER + +config STM32_UART7_SERIALDRIVER + bool "Standard serial driver" + select UART7_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + select STM32_SERIALDRIVER + +config STM32_UART7_1WIREDRIVER + bool "1-Wire driver" + select STM32_1WIREDRIVER + +config STM32_UART7_HCIUART + bool "Bluetooth HCI-UART" + select STM32_HCIUART + depends on WIRELESS_BLUETOOTH + +endchoice # UART7 Driver Configuration + +if STM32_UART7_HCIUART + +config STM32_HCIUART7_RXBUFSIZE + int "HCI UART7 Rx buffer size" + default 80 + ---help--- + Characters are buffered as they are received. This specifies + the size of the receive buffer. Ideally this should be at least + the size of the largest frame that can be received + +config STM32_HCIUART7_TXBUFSIZE + int "HCI UART7 Transmit buffer size" + default 80 + ---help--- + Characters are buffered before being sent. This specifies + the size of the transmit buffer. Ideally this should be at least + the size of the largest frame that can be sent + +config STM32_HCIUART7_BAUD + int "HCI UART7 initial BAUD rate" + default 115200 + ---help--- + The configured initial BAUD of the HCIR USART used during bringup. + In most cases this initial rate can be increased by the upper half + HCI UART driver using vendor-specifi HCI UART commands. + +config STM32_HCIUART7_RXDMA + bool "HCI UART7 Rx DMA" + default n + depends on STM32_DMA2 + select STM32_HCIUART_RXDMA + ---help--- + In high data rate usage, Rx DMA may eliminate Rx overrun errors + +endif # STM32_UART7_HCIUART + +choice + prompt "UART8 Driver Configuration" + depends on STM32_COMMON_LEGACY && STM32_UART8 + default STM32_UART8_SERIALDRIVER + +config STM32_UART8_SERIALDRIVER + bool "Standard serial driver" + select UART8_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + select STM32_SERIALDRIVER + +config STM32_UART8_1WIREDRIVER + bool "1-Wire driver" + select STM32_1WIREDRIVER + +config STM32_UART8_HCIUART + bool "Bluetooth HCI-UART" + select STM32_HCIUART + depends on WIRELESS_BLUETOOTH + +endchoice # UART8 Driver Configuration + +if STM32_UART8_HCIUART + +config STM32_HCIUART8_RXBUFSIZE + int "HCI UART8 Rx buffer size" + default 80 + ---help--- + Characters are buffered as they are received. This specifies + the size of the receive buffer. Ideally this should be at least + the size of the largest frame that can be received + +config STM32_HCIUART8_TXBUFSIZE + int "HCI UART8 Transmit buffer size" + default 80 + ---help--- + Characters are buffered before being sent. This specifies + the size of the transmit buffer. Ideally this should be at least + the size of the largest frame that can be sent + +config STM32_HCIUART8_BAUD + int "HCI UART8 initial BAUD rate" + default 115200 + ---help--- + The configured initial BAUD of the HCIR USART used during bringup. + In most cases this initial rate can be increased by the upper half + HCI UART driver using vendor-specifi HCI UART commands. + +config STM32_HCIUART8_RXDMA + bool "HCI UART8 Rx DMA" + default n + depends on STM32_DMA2 + select STM32_HCIUART_RXDMA + ---help--- + In high data rate usage, Rx DMA may eliminate Rx overrun errors + +endif # STM32_UART8_HCIUART + choice prompt "RTC clock source" depends on STM32_RTC @@ -700,9 +950,10 @@ config STM32_FDCAN_SOCKET endchoice # FDCAN character driver or SocketCAN support +if STM32_FDCAN1 + choice prompt "FDCAN1 frame format" - depends on STM32_FDCAN1 default STM32_FDCAN1_ISO11898_1 config STM32_FDCAN1_ISO11898_1 @@ -713,13 +964,12 @@ config STM32_FDCAN1_ISO11898_1 config STM32_FDCAN1_NONISO_FORMAT bool "Non ISO" ---help--- - Enable Non ISO, Bosch CAN FD Specification V1.0 + Enable Non ISO, Bosch CAN FD Specification V1.0 endchoice # FDCAN1 frame format choice prompt "FDCAN1 mode" - depends on STM32_FDCAN1 default STM32_FDCAN1_CLASSIC config STM32_FDCAN1_CLASSIC @@ -737,13 +987,16 @@ config STM32_FDCAN1_FD_BRS bool "CAN FD with fast bit rate switching" depends on CAN_FD || NET_CAN_CANFD ---help--- - Enable CAN FD mode with fast bit rate switching mode. + Enable CAN FD mode with fast bit rate switching mode. endchoice # FDCAN1 mode +endif # STM32_FDCAN1 + +if STM32_FDCAN2 + choice prompt "FDCAN2 frame format" - depends on STM32_FDCAN2 default STM32_FDCAN2_ISO11898_1 config STM32_FDCAN2_ISO11898_1 @@ -754,13 +1007,12 @@ config STM32_FDCAN2_ISO11898_1 config STM32_FDCAN2_NONISO_FORMAT bool "Non ISO" ---help--- - Enable Non ISO, Bosch CAN FD Specification V1.0 + Enable Non ISO, Bosch CAN FD Specification V1.0 endchoice # FDCAN2 frame format choice prompt "FDCAN2 mode" - depends on STM32_FDCAN2 default STM32_FDCAN2_CLASSIC config STM32_FDCAN2_CLASSIC @@ -782,6 +1034,8 @@ config STM32_FDCAN2_FD_BRS endchoice # FDCAN2 mode +endif # STM32_FDCAN2 + choice prompt "Layer 1 color format" depends on STM32_LTDC @@ -1304,4 +1558,8018 @@ config STM32_LPTIM2_CLK_HSI bool "Clock LPTIM2 from HSI" endchoice + +config STM32_TIM_PWM_COMMON + bool + default y if STM32_COMMON_FULL_FEATURED + +config STM32_TIM_PWM_NO_F0_COMMON + bool + default y if STM32_COMMON_LEGACY || STM32_COMMON_F7_H7 || STM32_COMMON_L4_H5_L5_U5 + +config STM32_TIM_PWM_ADVANCED_COMMON + bool + default y if STM32_COMMON_LEGACY || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5 + +config STM32_TIM_PWM_SINGLECHAN_COMMON + bool + default y if STM32_COMMON_LEGACY || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5 + +config STM32_TIM_PWM_INTERNAL_COMMON + bool + default y if STM32_COMMON_LEGACY || STM32_COMMON_F7_H7_H5 + +config STM32_TIM_PWM_STM32PWM_COMMON + bool + default y if STM32_COMMON_LEGACY || STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5 || ARCH_CHIP_STM32U5 + +config STM32_TIM_PWM_CHMODE_EXTENDED_COMMON + bool + default y if (STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2) || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5 + +config STM32_TIM_PWM_CHMODE_LEGACY_COMMON + bool + default y if STM32_COMMON_LEGACY && !STM32_HAVE_IP_TIMERS_V2 + +config STM32_TIM_PWM_CHMODE_LIMITED_COMMON + bool + default y if STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_L5_U5 + +config STM32_TIM_PWM_CHMODE_TIM16_17_EXTENDED_COMMON + bool + default y if STM32_COMMON_LEGACY || ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5 + +config STM32_ADC_TIMTRIG_TRGO2_COMMON + bool + default y if STM32_COMMON_LEGACY || STM32_COMMON_F0_L0_G0_C0 || ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32H5 + +config STM32_ADC_TIMTRIG_TRGO_COMMON + bool + default y if ARCH_CHIP_STM32H7 || STM32_COMMON_L5_U5 + +config STM32_TIM_PWM_NOUT_REQUIRES_OUT_COMMON + bool + default y if STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_L4_L5_U5 + +config STM32_PWM_MULTICHAN_L5_TIMERS + bool + default y if STM32_TIM1_PWM || STM32_TIM2_PWM || STM32_TIM3_PWM + default y if STM32_TIM4_PWM || STM32_TIM5_PWM || STM32_TIM8_PWM + default y if STM32_TIM15_PWM || STM32_TIM16_PWM || STM32_TIM17_PWM + +config STM32_PWM_MULTICHAN_CAPABLE + bool + default y if STM32_COMMON_LEGACY && STM32_TIM && STM32_PWM + default y if (STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_F7_H7) && STM32_PWM + default y if (ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5 || ARCH_CHIP_STM32U5) && STM32_PWM + default y if ARCH_CHIP_STM32L5 && STM32_PWM_MULTICHAN_L5_TIMERS + +config STM32_SPI_CORE_DMA_CAPABLE + bool + default y if STM32_COMMON_LEGACY || STM32_COMMON_F0_L0_G0_C0 + default y if STM32_COMMON_F7_H7_H5 + default y if ARCH_CHIP_STM32WL5 + default y if STM32_COMMON_L4_L5_U5 && STM32_SPI + default y if ARCH_CHIP_STM32WB && (STM32_SPI1 || STM32_SPI2) && STM32_DMA + +config STM32_SPI_DMA_FAMILY_WL5 + bool + default y if STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7 + default y if STM32_COMMON_H7_H5 || ARCH_CHIP_STM32WL5 + +config STM32_SPI_DMA_FAMILY + bool + default y if STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7 + default y if STM32_COMMON_H7_H5 + +config STM32_RTC_MAGIC_CAPABLE + bool + default y if STM32_COMMON_LEGACY && STM32_RTC && !STM32_HAVE_RTC_COUNTER + default y if (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4) && STM32_RTC + default y if (STM32_COMMON_L5_U5 || ARCH_CHIP_STM32WB) && STM32_RTC + +config STM32_ADC1_TIMER_FREQ_CAPABLE + bool + default y if STM32_COMMON_LEGACY && STM32_TIM && STM32_HAVE_ADC1_TIMER + default y if (STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_F7_H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_HAVE_ADC1_TIMER + +config STM32_ADC1_TIMTRIG_CAPABLE + bool + default y if STM32_COMMON_LEGACY && STM32_TIM && STM32_HAVE_ADC1_TIMER + default y if (STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_F7_H7) && STM32_HAVE_ADC1_TIMER + default y if (ARCH_CHIP_STM32H5 || STM32_COMMON_L5_U5) && STM32_HAVE_ADC1_TIMER + +config STM32_ADC2_TIMER_FREQ_CAPABLE + bool + default y if STM32_COMMON_LEGACY && STM32_TIM && STM32_HAVE_ADC2_TIMER + default y if (STM32_COMMON_F7_H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_HAVE_ADC2_TIMER + +config STM32_ADC2_TIMTRIG_CAPABLE + bool + default y if STM32_COMMON_LEGACY && STM32_TIM && STM32_HAVE_ADC2_TIMER + default y if (STM32_COMMON_F7_H7_H5) && STM32_HAVE_ADC2_TIMER + default y if STM32_COMMON_L5_U5 && STM32_HAVE_ADC2_TIMER + +config STM32_ADC3_TIMER_CAPABLE + bool + default y if STM32_COMMON_LEGACY && STM32_TIM && STM32_HAVE_ADC3_TIMER + default y if (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4) && STM32_HAVE_ADC3_TIMER + default y if STM32_COMMON_L5_U5 && STM32_HAVE_ADC3_TIMER + +config STM32_QENCODER_TIMS_1_4 + bool + default y if STM32_TIM1 || STM32_TIM2 || STM32_TIM3 || STM32_TIM4 + +config STM32_QENCODER_TIMS_1_8 + bool + default y if STM32_QENCODER_TIMS_1_4 + default y if STM32_TIM5 || STM32_TIM8 + +config STM32_QENCODER_MAIN_COMMON + bool + default y if STM32_COMMON_LEGACY || STM32_COMMON_F7_H7 + default y if STM32_COMMON_L4_L5_U5 + +config STM32_QENCODER_MAIN + bool + default y if STM32_QENCODER_MAIN_COMMON && SENSORS_QENCODER && STM32_QENCODER_TIMS_1_8 + +config STM32_QENCODER_STM32 + bool + default y if STM32_COMMON_LEGACY && SENSORS_QENCODER && STM32_QENCODER_TIMS_1_8 + +config STM32_QENCODER_F0 + bool + default y if STM32_COMMON_F0_L0_G0_C0 && SENSORS_QENCODER && STM32_QENCODER_TIMS_1_4 + +config STM32_QENCODER_16BIT_CAPABLE + bool + default y if STM32_QENCODER_STM32 || STM32_QENCODER_F0 + +config STM32_LPTIM1_CH1OUT_CAPABLE + bool + default y if ARCH_CHIP_STM32L4 && STM32_LPTIM1_PWM && STM32_PWM_MULTICHAN && STM32_LPTIM1_CHANNEL1 + default y if ARCH_CHIP_STM32L4 && STM32_LPTIM1_PWM && !STM32_PWM_MULTICHAN && STM32_LPTIM1_CHANNEL = 1 + +config STM32_LPTIM1_CH1NOUT_CAPABLE + bool + default y if STM32_LPTIM1_CH1OUT_CAPABLE && STM32_LPTIM1_CH1OUT + default y if ARCH_CHIP_STM32L4 && STM32_LPTIM1_PWM && !STM32_PWM_MULTICHAN && STM32_LPTIM1_CHANNEL = 1 + +config STM32_LPTIM2_CH1OUT_CAPABLE + bool + default y if ARCH_CHIP_STM32L4 && STM32_LPTIM2_PWM && STM32_PWM_MULTICHAN && STM32_LPTIM2_CHANNEL1 + default y if ARCH_CHIP_STM32L4 && STM32_LPTIM2_PWM && !STM32_PWM_MULTICHAN && STM32_LPTIM2_CHANNEL = 1 + +config STM32_LPTIM2_CH1NOUT_CAPABLE + bool + default y if STM32_LPTIM2_CH1OUT_CAPABLE && STM32_LPTIM2_CH1OUT + default y if ARCH_CHIP_STM32L4 && STM32_LPTIM2_PWM && !STM32_PWM_MULTICHAN && STM32_LPTIM2_CHANNEL = 1 + +config STM32_ADC1_DFSDM_L4_CHIP + bool + default y if STM32_STM32L496XX || STM32_STM32L4XR + +config STM32_ADC1_DFSDM_L5_CHIP + bool + default y if STM32_STM32L596XX || STM32_STM32L5XR + +config STM32_ADC1_DFSDM_U5_CHIP + bool + default y if STM32_STM32U596XX || STM32_STM32U5XR + +config STM32_ADC1_OUTPUT_DFSDM_CAPABLE + bool + default y if ARCH_CHIP_STM32L4 && STM32_ADC && STM32_ADC1 && STM32_DFSDM1 && STM32_ADC1_DFSDM_L4_CHIP + default y if ARCH_CHIP_STM32L5 && STM32_ADC && STM32_ADC1 && STM32_DFSDM1 && STM32_ADC1_DFSDM_L5_CHIP + default y if ARCH_CHIP_STM32U5 && STM32_ADC && STM32_ADC1 && STM32_DFSDM1 && STM32_ADC1_DFSDM_U5_CHIP + +config STM32_ADC2_OUTPUT_DFSDM_CAPABLE + bool + default y if ARCH_CHIP_STM32L4 && STM32_ADC && STM32_ADC2 && STM32_DFSDM1 && STM32_STM32L496XX + default y if ARCH_CHIP_STM32L5 && STM32_ADC && STM32_ADC2 && STM32_DFSDM1 && STM32_STM32L596XX + default y if ARCH_CHIP_STM32U5 && STM32_ADC && STM32_ADC2 && STM32_DFSDM1 && STM32_STM32U596XX + +config STM32_ADC3_OUTPUT_DFSDM_CAPABLE + bool + default y if ARCH_CHIP_STM32L4 && STM32_ADC && STM32_ADC3 && STM32_DFSDM1 && STM32_STM32L496XX + default y if ARCH_CHIP_STM32L5 && STM32_ADC && STM32_ADC3 && STM32_DFSDM1 && STM32_STM32L596XX + default y if ARCH_CHIP_STM32U5 && STM32_ADC && STM32_ADC3 && STM32_DFSDM1 && STM32_STM32U596XX + +config STM32_FLASH_CONFIG_4 + bool + +config STM32_FLASH_CONFIG_6 + bool + +config STM32_FLASH_CONFIG_8 + bool + +config STM32_FLASH_CONFIG_B + bool + +config STM32_FLASH_CONFIG_C + bool + +config STM32_FLASH_CONFIG_D + bool + +config STM32_FLASH_CONFIG_E + bool + +config STM32_FLASH_CONFIG_F + bool + +config STM32_FLASH_CONFIG_G + bool + +config STM32_FLASH_CONFIG_I + bool + +config STM32_ENERGYLITE + bool + select STM32_HAVE_TIM6 if STM32_COMMON_LEGACY + select STM32_HAVE_TIM7 if STM32_COMMON_LEGACY + +config STM32_VALUELINE + bool + select STM32_HAVE_USART3 if STM32_COMMON_LEGACY + select STM32_HAVE_UART4 if STM32_COMMON_LEGACY + select STM32_HAVE_UART5 if STM32_COMMON_LEGACY + select STM32_HAVE_TIM1 if STM32_COMMON_LEGACY + select STM32_HAVE_TIM5 if STM32_COMMON_LEGACY + select STM32_HAVE_TIM6 if STM32_COMMON_LEGACY + select STM32_HAVE_TIM7 if STM32_COMMON_LEGACY + select STM32_HAVE_TIM12 if STM32_COMMON_LEGACY + select STM32_HAVE_TIM13 if STM32_COMMON_LEGACY + select STM32_HAVE_TIM14 if STM32_COMMON_LEGACY + select STM32_HAVE_TIM15 if STM32_COMMON_LEGACY + select STM32_HAVE_TIM16 if STM32_COMMON_LEGACY + select STM32_HAVE_TIM17 if STM32_COMMON_LEGACY + select STM32_HAVE_SPI2 if STM32_COMMON_LEGACY && STM32_HIGHDENSITY + select STM32_HAVE_SPI3 if STM32_COMMON_LEGACY && STM32_HIGHDENSITY + select STM32_HAVE_USART5 if STM32_COMMON_F0_L0_G0_C0 + select STM32_HAVE_SPI2 if STM32_COMMON_F0_L0_G0_C0 + +config STM32_DFU + bool "DFU bootloader" + depends on (STM32_COMMON_LEGACY || STM32_COMMON_F0_L0_G0_C0) && !STM32_VALUELINE + ---help--- + Configure and position code for use with the STMicro DFU bootloader. Do + not select this option if you will load code using JTAG/SWM. + +# These hidden settings determine whether a peripheral option is available +# for the selected MCU. Family Kconfigs select these from chip data. + +config STM32_HAVE_AES + bool + +config STM32_HAVE_CRYP + bool + +config STM32_HAVE_CCM + bool + +config STM32_HAVE_DMAMUX + bool + +config STM32_HAVE_USBDEV + bool + +config STM32_HAVE_USBFS + bool + +config STM32_HAVE_OTGFS + bool + +config STM32_HAVE_FMC + bool + +config STM32_HAVE_FSMC + bool + +config STM32_HAVE_SYSCFG + bool + +config STM32_HAVE_FDCAN1 + bool + +config STM32_HAVE_FDCAN2 + bool + +config STM32_HAVE_FDCAN3 + bool + +config STM32_HAVE_LTDC + bool + +config STM32_HAVE_USART2 + bool + +config STM32_HAVE_USART3 + bool + +config STM32_HAVE_UART4 + bool + +config STM32_HAVE_UART5 + bool + +config STM32_HAVE_USART6 + bool + +config STM32_HAVE_UART7 + bool + +config STM32_HAVE_UART8 + bool + +config STM32_HAVE_TIM1 + bool + +config STM32_HAVE_TIM2 + bool + +config STM32_HAVE_TIM3 + bool + +config STM32_HAVE_TIM4 + bool + +config STM32_HAVE_TIM5 + bool + +config STM32_HAVE_TIM6 + bool + +config STM32_HAVE_TIM7 + bool + +config STM32_HAVE_TIM8 + bool + +config STM32_HAVE_TIM9 + bool + +config STM32_HAVE_TIM10 + bool + +config STM32_HAVE_TIM11 + bool + +config STM32_HAVE_TIM12 + bool + +config STM32_HAVE_TIM13 + bool + +config STM32_HAVE_TIM14 + bool + +config STM32_HAVE_TIM15 + bool + +config STM32_HAVE_TIM16 + bool + +config STM32_HAVE_TIM17 + bool + +config STM32_HAVE_TSC + bool + +config STM32_HAVE_ADC2 + bool + +config STM32_HAVE_ADC3 + bool + +config STM32_HAVE_ADC4 + bool + +config STM32_HAVE_ADC5 + bool + +config STM32_HAVE_ADC1_DMA + bool + +config STM32_HAVE_ADC2_DMA + bool + +config STM32_HAVE_ADC3_DMA + bool + +config STM32_HAVE_ADC4_DMA + bool + +config STM32_HAVE_ADC5_DMA + bool + +config STM32_HAVE_ADC_OVERSAMPLE + bool + default STM32_STM32L0 || STM32_STM32G0 || STM32_STM32C0 + +config STM32_HAVE_ADC4_TIMER + bool + +config STM32_HAVE_ADC5_TIMER + bool + +config STM32_HAVE_CAN1 + bool + +config STM32_HAVE_CAN2 + bool + +config STM32_HAVE_CAN3 + bool + +config STM32_HAVE_COMP1 + bool + +config STM32_HAVE_COMP2 + bool + +config STM32_HAVE_COMP3 + bool + +config STM32_HAVE_COMP4 + bool + +config STM32_HAVE_COMP5 + bool + +config STM32_HAVE_COMP6 + bool + +config STM32_HAVE_COMP7 + bool + +config STM32_HAVE_CRS + bool + +config STM32_HAVE_CEC + bool + +config STM32_HAVE_CORDIC + bool + +config STM32_HAVE_DSIHOST + bool + +config STM32_HAVE_JPEG + bool + +config STM32_HAVE_INTERNAL_ULPI + bool + +config STM32_HAVE_EXTERNAL_ULPI + bool + +config STM32_HAVE_HRTIM1 + bool + +config STM32_HAVE_HRTIM1_PLLCLK + bool + +config STM32_HAVE_TIM18 + bool + +config STM32_HAVE_TIM19 + bool + +config STM32_HAVE_TIM20 + bool + +config STM32_HAVE_SDADC1 + bool + +config STM32_HAVE_SDADC2 + bool + +config STM32_HAVE_SDADC3 + bool + +config STM32_HAVE_SDADC1_DMA + bool + +config STM32_HAVE_SDADC2_DMA + bool + +config STM32_HAVE_SDADC3_DMA + bool + +config STM32_HAVE_SDIO + bool + +config STM32_HAVE_UCPD1 + bool + +config STM32_HAVE_UCPD2 + bool + +config STM32_HAVE_RTC_COUNTER + bool + +config STM32_HAVE_IP_DBGMCU_V1 + bool + +config STM32_HAVE_IP_DBGMCU_V2 + bool + +config STM32_HAVE_IP_DBGMCU_V3 + bool + +config STM32_HAVE_IP_I2C_V1 + bool + +config STM32_HAVE_IP_I2C_V2 + bool + +config STM32_HAVE_IP_DMA_V1 + bool + +config STM32_HAVE_IP_DMA_V2 + bool + +config STM32_HAVE_IP_TIMERS_V1 + bool + +config STM32_HAVE_IP_TIMERS_V2 + bool + +config STM32_HAVE_IP_TIMERS_V3 + bool + +config STM32_HAVE_IP_ADC_V1 + bool + +config STM32_HAVE_IP_ADC_V1_BASIC + bool + select STM32_HAVE_IP_ADC_V1 + +config STM32_HAVE_IP_ADC_V2 + bool + +config STM32_HAVE_IP_ADC_V2_BASIC + bool + select STM32_HAVE_IP_ADC_V2 + +config STM32_HAVE_IP_COMP_V1 + bool + +config STM32_HAVE_IP_COMP_V2 + bool + +config STM32_HAVE_IP_DAC_V1 + bool + +config STM32_HAVE_IP_DAC_V2 + bool + +config STM32_HAVE_IP_USART_V1 + bool + +config STM32_HAVE_IP_USART_V2 + bool + +config STM32_HAVE_IP_EXTI_V1 + bool + +config STM32_HAVE_IP_EXTI_V2 + bool + +config STM32_HAVE_FMAC + bool + +config STM32_HAVE_FLASH_ICACHE + bool + +config STM32_HAVE_FLASH_DCACHE + bool + +config STM32_HAVE_OVERDRIVE + bool + +config STM32_HAVE_DMA1_CHAN8 + bool + +config STM32_HAVE_DMA2_CHAN678 + bool + +config STM32_HAVE_UCPD + bool + +config STM32_HAVE_DAC1 + bool + +config STM32_HAVE_DAC2 + bool + +config STM32_HAVE_DAC3 + bool + +config STM32_HAVE_DAC4 + bool + +config STM32_HAVE_QSPI + bool + +config STM32_HAVE_RNG + bool + +config STM32_HAVE_VREFINT + bool + +config STM32_HAVE_I2C1 + bool + +config STM32_HAVE_I2C2 + bool + +config STM32_HAVE_I2C3 + bool + +config STM32_HAVE_I2C4 + bool + +config STM32_HAVE_SDMMC1 + bool + +config STM32_HAVE_SDMMC2 + bool + +config STM32_HAVE_LPTIM1 + bool + +config STM32_HAVE_LPUART1 + bool + +config STM32_HAVE_LPUART2 + bool + +config STM32_HAVE_SPI1 + bool + +config STM32_HAVE_SPI2 + bool + +config STM32_HAVE_SPI3 + bool + +config STM32_HAVE_I2S3 + bool + +config STM32_HAVE_I2S2 + bool + +config STM32_HAVE_SPI2S2 + bool + +config STM32_HAVE_SPI4 + bool + +config STM32_HAVE_SPI5 + bool + +config STM32_HAVE_SPI6 + bool + +config STM32_HAVE_SAIPLL + bool + +config STM32_HAVE_I2SPLL + bool + +config STM32_HAVE_OPAMP1 + bool + +config STM32_HAVE_OPAMP2 + bool + +config STM32_HAVE_OPAMP3 + bool + +config STM32_HAVE_OPAMP4 + bool + +config STM32_HAVE_OPAMP5 + bool + +config STM32_HAVE_OPAMP6 + bool + +config STM32_HAVE_IOCOMPENSATION + bool + +config STM32_HAVE_ICACHE + bool + +config STM32_HAVE_ETHMAC + bool + +config STM32_HAVE_ETHRNET + bool + +config STM32_HAVE_LPUART + bool + +config STM32_HAVE_SAI + bool + +config STM32_HAVE_USB + bool + +config STM32_GPIO_HAVE_PORTD + bool + +config STM32_GPIO_HAVE_PORTE + bool + +config STM32_HAVE_GPIOF + bool + +config STM32_HAVE_GPIOG + bool + +config STM32_HAVE_PWR_DIRECT_SMPS_SUPPLY + bool + +config STM32_HAVE_OTA_PARTITION + bool + +config STM32_HAVE_CM4 + bool + +config STM32_HAVE_USART4 + bool + +config STM32_HAVE_USART5 + bool + +config STM32_HAVE_USART7 + bool + +config STM32_HAVE_USART8 + bool + +config STM32_HAVE_UART9 + bool + +config STM32_HAVE_USART10 + bool + +config STM32_HAVE_USART11 + bool + +config STM32_HAVE_UART12 + bool + +config STM32_HAVE_ADC1 + bool + default y if STM32_COMMON_LEGACY + +config STM32_ADC1 + bool "ADC1" + depends on STM32_COMMON_LEGACY || STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5 || ARCH_CHIP_STM32U5 + select STM32_ADC if !ARCH_CHIP_STM32U5 + select STM32_HAVE_ADC1_DMA if STM32_COMMON_LEGACY && ((STM32_STM32F10XX || STM32_STM32F37XX) && STM32_DMA1 || !STM32_STM32F10XX && STM32_DMA2 || STM32_DMAMUX) + select STM32_HAVE_ADC1_DMA if ARCH_CHIP_STM32F7 && STM32_DMA2 + +config STM32_ADC2 + bool "ADC2" + depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32L4) && STM32_HAVE_ADC2 || STM32_COMMON_F7_H7_H5 + select STM32_ADC + select STM32_HAVE_ADC2_DMA if STM32_COMMON_LEGACY && STM32_HAVE_ADC2 && (STM32_DMA2 || STM32_DMAMUX) + select STM32_HAVE_ADC2_DMA if ARCH_CHIP_STM32F7 && STM32_DMA2 + +config STM32_ADC3 + bool "ADC3" + depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32L4) && STM32_HAVE_ADC3 || STM32_COMMON_F7_H7 + select STM32_ADC + select STM32_HAVE_ADC3_DMA if STM32_COMMON_LEGACY && STM32_HAVE_ADC3 && (STM32_DMA2 || STM32_DMAMUX) + select STM32_HAVE_ADC3_DMA if ARCH_CHIP_STM32F7 && STM32_DMA2 + +config STM32_ADC4 + bool "ADC4" + depends on (STM32_COMMON_LEGACY && STM32_HAVE_ADC4) || ARCH_CHIP_STM32U5 + select STM32_ADC if STM32_COMMON_LEGACY + select STM32_HAVE_ADC4_DMA if STM32_COMMON_LEGACY && STM32_HAVE_ADC4 && (STM32_DMA2 || STM32_DMAMUX) + +config STM32_COMP1 + bool "COMP1" + depends on STM32_HAVE_COMP1 + select STM32_COMP if STM32_COMMON_LEGACY && STM32_HAVE_COMP1 + +config STM32_COMP2 + bool "COMP2" + depends on STM32_HAVE_COMP2 + select STM32_COMP if STM32_COMMON_LEGACY && STM32_HAVE_COMP2 + +config STM32_CORDIC + bool "CORDIC Accelerator" + depends on (STM32_COMMON_LEGACY && STM32_HAVE_CORDIC && MATH_CORDIC_USE_Q31) || ARCH_CHIP_STM32U5 + +config STM32_BKP + bool "BKP" + depends on (STM32_COMMON_LEGACY && STM32_STM32F10XX) || STM32_COMMON_F0_L0_G0_C0 + +config STM32_BKPSRAM + bool "Enable BKP RAM Domain" + depends on STM32_COMMON_LEGACY && (STM32_STM32F20XX || STM32_STM32F4XXX) || STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32U5 + select STM32_PWR if ARCH_CHIP_STM32H7 + +config STM32_CAN1 + bool "CAN1" + depends on STM32_HAVE_CAN1 + select STM32_CAN + select CAN if !STM32_COMMON_LEGACY + +config STM32_CAN2 + bool "CAN2" + depends on STM32_HAVE_CAN2 + select STM32_CAN + select CAN if !STM32_COMMON_LEGACY + +config STM32_CAN3 + bool "CAN3" + depends on STM32_HAVE_CAN3 + select STM32_CAN + select CAN + +config STM32_AES + bool "128-bit AES" + depends on (STM32_COMMON_LEGACY || STM32_COMMON_F0_L0_G0_C0 || ARCH_CHIP_STM32L4) && STM32_HAVE_AES || ARCH_CHIP_STM32U5 + select CRYPTO_AES192_DISABLE if (STM32_COMMON_LEGACY && STM32_HAVE_AES) && CRYPTO_ALGTEST + select CRYPTO_AES256_DISABLE if (STM32_COMMON_LEGACY && STM32_HAVE_AES) && CRYPTO_ALGTEST + select CRYPTO_AES192_DISABLE if (STM32_COMMON_F0_L0_G0_C0 && STM32_HAVE_AES) && CRYPTO_ALGTEST + select CRYPTO_AES256_DISABLE if (STM32_COMMON_F0_L0_G0_C0 && STM32_HAVE_AES) && CRYPTO_ALGTEST + +config STM32_CEC + bool "CEC" + depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_VALUELINE || STM32_COMMON_F0_L0_G0_C0 && STM32_HAVE_CEC || ARCH_CHIP_STM32F7 + +config STM32_CRC + bool "CRC" + depends on STM32_COMMON_LEGACY || STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32U5 || ARCH_CHIP_STM32WB + +config STM32_CRS + bool "CRS (Clock Recovery System)" + depends on STM32_HAVE_CRS + +config STM32_CRYP + bool "CRYP" + depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_HAVE_CRYP || STM32_COMMON_F0_L0_G0_C0 && STM32_HAVE_HASH + +config STM32_DMA1 + bool "DMA1" + depends on STM32_COMMON_LEGACY || STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5 || ARCH_CHIP_STM32WB + select STM32_DMA + select ARCH_DMA + select STM32_DMAMUX1 if ARCH_CHIP_STM32L4 && STM32_HAVE_DMAMUX + +config STM32_DMA2 + bool "DMA2" + depends on STM32_HAVE_DMA2 + select STM32_DMA + select ARCH_DMA + select STM32_DMAMUX1 if ARCH_CHIP_STM32L4 && STM32_HAVE_DMAMUX + +config STM32_DMAMUX1 + bool "DMAMUX1" + depends on STM32_HAVE_DMAMUX + select STM32_DMAMUX + +config STM32_DAC1 + bool "DAC1" + depends on STM32_HAVE_DAC1 + select STM32_DAC if !ARCH_CHIP_STM32U5 + +config STM32_DAC2 + bool "DAC2" + depends on STM32_HAVE_DAC2 + select STM32_DAC + +config STM32_DCMI + bool "DCMI" + depends on STM32_HAVE_DCMI + ---help--- + The devices embed a camera interface that can connect with camera + modules and CMOS sensors through an 8-bit to 14-bit parallel interface, + to receive video data. + +config STM32_DSIHOST + bool "DSIHOST" + depends on STM32_HAVE_DSIHOST + ---help--- + The DSI Host is a dedicated peripheral for interfacing with MIPI DSI + compliant displays. + +config STM32_ETHMAC + bool "Ethernet MAC" + depends on STM32_HAVE_ETHERNET + select NETDEVICES + select ARCH_HAVE_PHY + select STM32_HAVE_PHY_POLLED if !STM32_COMMON_LEGACY + +config STM32_FDCAN1 + bool "FDCAN1" + depends on STM32_HAVE_FDCAN1 + select STM32_FDCAN if !ARCH_CHIP_STM32U5 + +config STM32_FDCAN2 + bool "FDCAN2" + depends on STM32_HAVE_FDCAN2 + select STM32_FDCAN + +config STM32_FDCAN3 + bool "FDCAN3" + depends on STM32_HAVE_FDCAN3 + select STM32_FDCAN + +config STM32_FSMC + bool "FSMC" + depends on STM32_HAVE_FSMC + +config STM32_FMC + bool "FMC" + depends on STM32_HAVE_FMC + ---help--- + Enable Flexible Memory Controller. + To correctly configure FMC for your hardware, you will have to define + a number of macros in your board.h file. See stm32_fmc.c for directions. + +config STM32_FMAC + bool "FMAC (Filter Math Accelerator)" + depends on STM32_HAVE_FMAC + +config STM32_HASH + bool "HASH" + depends on STM32_HAVE_HASH + select ARCH_HAVE_HASH if ARCH_CHIP_STM32F7 && STM32_HAVE_HASH + +config STM32_JPEG + bool "JPEG" + depends on STM32_HAVE_JPEG + ---help--- + The JPEG codec provides a hardware compressor and decompressor of JPEG + images with full management of JPEG headers. + +config STM32_I2C1 + bool "I2C1" + depends on STM32_HAVE_I2C1 + select STM32_I2C + select I2C if ARCH_CHIP_STM32WB + +config STM32_I2C2 + bool "I2C2" + depends on STM32_HAVE_I2C2 + select STM32_I2C + +config STM32_I2C3 + bool "I2C3" + depends on STM32_HAVE_I2C3 + select STM32_I2C + select I2C if ARCH_CHIP_STM32WB && STM32_HAVE_I2C3 + +config STM32_LPTIM1 + bool "LPTIM1" + depends on STM32_HAVE_LPTIM1 + select STM32_LPTIM if ARCH_CHIP_STM32H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32WB + +config STM32_LPUART1 + bool "LPUART1" + depends on STM32_HAVE_LPUART1 + select LPUART1_SERIALDRIVER if ARCH_CHIP_STM32L4 && STM32_HAVE_LPUART1 + select STM32_USART + select ARCH_HAVE_SERIAL_TERMIOS if !STM32_COMMON_LEGACY + select ARCH_HAVE_LPUART1 if ARCH_CHIP_STM32L4 && STM32_HAVE_LPUART1 || ARCH_CHIP_STM32WB && STM32_HAVE_LPUART + +config STM32_VREFINT + bool "Enable VREFINT" + depends on STM32_HAVE_VREFINT + +config STM32_USART4 + bool "USART4" + depends on STM32_HAVE_USART4 + select STM32_USART + +config STM32_USART5 + bool "USART5" + depends on STM32_HAVE_USART5 + select STM32_USART + +config STM32_USART7 + bool "USART7" + depends on STM32_HAVE_USART7 + select STM32_USART + +config STM32_USART8 + bool "USART8" + depends on STM32_HAVE_USART8 + select STM32_USART + +config STM32_LTDC + bool "LTDC" + depends on STM32_HAVE_LTDC + select FB + ---help--- + The STM32 LTDC is an LCD-TFT Display Controller available on + the STM32F429 and STM32F439 devices. It is a standard parallel + video interface (HSYNC, VSYNC, etc.) for controlling TFT + LCD displays. + +config STM32_DMA2D + bool "DMA2D" + depends on STM32_HAVE_DMA2D + select FB if STM32_COMMON_LEGACY && STM32_STM32F429 || ARCH_CHIP_STM32F7 && STM32_HAVE_DMA2D + select FB_OVERLAY if STM32_COMMON_LEGACY && STM32_STM32F429 || ARCH_CHIP_STM32F7 && STM32_HAVE_DMA2D + ---help--- + The STM32 DMA2D is an Chrom-Art Accelerator for image manipulation + available on the STM32F429 and STM32F439 devices. + +config STM32_RTC + bool "RTC" + depends on STM32_COMMON_LEGACY || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32L5 || ARCH_CHIP_STM32WB + select RTC if !ARCH_CHIP_STM32L5 + +config STM32_OTGFS + bool "OTG FS" + depends on STM32_HAVE_OTGFS + select USBHOST_HAVE_ASYNCH if !ARCH_CHIP_STM32U5 && USBHOST + +config STM32_OTGHS + bool "OTG HS" + depends on (STM32_COMMON_LEGACY && (STM32_STM32F20XX || STM32_STM32F4XXX)) || (ARCH_CHIP_STM32H7 && EXPERIMENTAL) || (ARCH_CHIP_STM32U5 && (STM32_STM32U59XX || STM32_STM32U59AXX || STM32_STM32U5A5XX || STM32_STM32U5A9XX)) + select USBHOST_HAVE_ASYNCH if !ARCH_CHIP_STM32U5 && USBHOST + +config STM32_OTGFSHS + bool "OTG FS/HS" + depends on ARCH_CHIP_STM32F7 + default n + select USBHOST_HAVE_ASYNCH if USBHOST + +config STM32_PWR + bool "PWR" + depends on STM32_COMMON_LEGACY || STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_F7_H7 || STM32_COMMON_L4_L5_U5 || ARCH_CHIP_STM32WB + +config STM32_QSPI + bool "QSPI (QUADSPI)" + depends on STM32_HAVE_QSPI + ---help--- + The STM32L4 QSPI block is intended to support one serial NOR flash device + +config STM32_RNG + bool "RNG" + depends on STM32_HAVE_RNG + select ARCH_HAVE_RNG if !ARCH_CHIP_STM32U5 + +config STM32_SDIO + bool "SDIO" + depends on (STM32_COMMON_LEGACY && !STM32_CONNECTIVITYLINE && !STM32_VALUELINE) || (STM32_COMMON_F0_L0_G0_C0 && STM32_HAVE_SDIO) + select ARCH_HAVE_SDIO + select ARCH_HAVE_SDIOWAIT_WRCOMPLETE + select ARCH_HAVE_SDIO_PREFLIGHT + +config STM32_SPI1 + bool "SPI1" + depends on STM32_HAVE_SPI1 + select SPI if !ARCH_CHIP_STM32WL5 + select STM32_SPI + +config STM32_SPI2 + bool "SPI2" + depends on STM32_HAVE_SPI2 + select SPI + select STM32_SPI + +config STM32_SPI3 + bool "SPI3" + depends on STM32_HAVE_SPI3 + select SPI + select STM32_SPI + +config STM32_I2S1 + bool "I2S1" + depends on ARCH_CHIP_STM32F7 && !STM32_SPI1 + select STM32_I2S + +config STM32_I2S2 + bool "I2S2" + depends on ARCH_CHIP_STM32F7 && !STM32_SPI2 + select STM32_I2S + +config STM32_I2S3 + bool "I2S3" + depends on STM32_HAVE_I2S3 + select I2S if STM32_COMMON_LEGACY + select STM32_I2S + +config STM32_SPI2S2 + bool "SPI2S2" + depends on STM32_HAVE_SPI2S2 + select STM32_SPI + +config STM32_SPDIFRX + bool "SPDIFRX" + depends on ARCH_CHIP_STM32F7 + +config STM32_SPI4 + bool "SPI4" + depends on STM32_HAVE_SPI4 + select SPI + select STM32_SPI + +config STM32_SPI5 + bool "SPI5" + depends on STM32_HAVE_SPI5 + select SPI + select STM32_SPI + +config STM32_SPI6 + bool "SPI6" + depends on STM32_HAVE_SPI6 + select SPI + select STM32_SPI + +config STM32_SYSCFG + bool "SYSCFG" + depends on STM32_HAVE_SYSCFG + default y + +config STM32_TIM1 + bool "TIM1" + depends on STM32_HAVE_TIM1 + select STM32_TIM if !(ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32U5 || ARCH_CHIP_STM32WB) + +config STM32_TIM2 + bool "TIM2" + depends on STM32_HAVE_TIM2 + select STM32_TIM if !(ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32U5 || ARCH_CHIP_STM32WB) + +config STM32_TIM3 + bool "TIM3" + depends on STM32_HAVE_TIM3 + select STM32_TIM if !(ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32U5) + +config STM32_TIM4 + bool "TIM4" + depends on STM32_HAVE_TIM4 + select STM32_TIM if !(ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32U5) + +config STM32_TIM5 + bool "TIM5" + depends on STM32_HAVE_TIM5 + select STM32_TIM if !(ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32U5) + +config STM32_TIM6 + bool "TIM6" + depends on STM32_HAVE_TIM6 + select STM32_TIM if !(ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32U5) + +config STM32_TIM7 + bool "TIM7" + depends on STM32_HAVE_TIM7 + select STM32_TIM if !(ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32U5) + +config STM32_TIM8 + bool "TIM8" + depends on STM32_HAVE_TIM8 + select STM32_TIM if !(ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32U5) + +config STM32_TIM9 + bool "TIM9" + depends on STM32_HAVE_TIM9 + select STM32_TIM + +config STM32_TIM10 + bool "TIM10" + depends on STM32_HAVE_TIM10 + select STM32_TIM + +config STM32_TIM11 + bool "TIM11" + depends on STM32_HAVE_TIM11 + select STM32_TIM + +config STM32_TIM12 + bool "TIM12" + depends on STM32_HAVE_TIM12 + select STM32_TIM + +config STM32_TIM13 + bool "TIM13" + depends on STM32_HAVE_TIM13 + select STM32_TIM + +config STM32_TIM14 + bool "TIM14" + depends on STM32_HAVE_TIM14 + select STM32_TIM + +config STM32_TIM15 + bool "TIM15" + depends on STM32_HAVE_TIM15 + select STM32_TIM if !(ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32U5) + +config STM32_TIM16 + bool "TIM16" + depends on STM32_HAVE_TIM16 + select STM32_TIM if !(ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32U5 || ARCH_CHIP_STM32WB) + +config STM32_TIM17 + bool "TIM17" + depends on STM32_HAVE_TIM17 + select STM32_TIM if !(ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32U5 || ARCH_CHIP_STM32WB) + +config STM32_TSC + bool "TSC" + depends on STM32_HAVE_TSC + +config STM32_USART1 + bool "USART1" + depends on STM32_HAVE_USART1 + select STM32_USART + select ARCH_HAVE_SERIAL_TERMIOS if !STM32_COMMON_LEGACY && !STM32_COMMON_F0_L0_G0_C0 + select USART1_SERIALDRIVER if STM32_COMMON_F7_H7 + +config STM32_USART2 + bool "USART2" + depends on STM32_HAVE_USART2 + select STM32_USART + select ARCH_HAVE_SERIAL_TERMIOS if !STM32_COMMON_LEGACY && !STM32_COMMON_F0_L0_G0_C0 + select USART2_SERIALDRIVER if STM32_COMMON_F7_H7 + +config STM32_USART3 + bool "USART3" + depends on STM32_HAVE_USART3 + select STM32_USART + select ARCH_HAVE_SERIAL_TERMIOS if !STM32_COMMON_LEGACY && !STM32_COMMON_F0_L0_G0_C0 + select USART3_SERIALDRIVER if STM32_COMMON_F7_H7 + +config STM32_UART4 + bool "UART4" + depends on STM32_HAVE_UART4 + select STM32_USART + select ARCH_HAVE_SERIAL_TERMIOS if !STM32_COMMON_LEGACY && !STM32_COMMON_F0_L0_G0_C0 + select UART4_SERIALDRIVER if STM32_COMMON_F7_H7 + +config STM32_UART5 + bool "UART5" + depends on STM32_HAVE_UART5 + select STM32_USART + select ARCH_HAVE_SERIAL_TERMIOS if !STM32_COMMON_LEGACY && !STM32_COMMON_F0_L0_G0_C0 + select UART5_SERIALDRIVER if STM32_COMMON_F7_H7 + +config STM32_USART6 + bool "USART6" + depends on STM32_HAVE_USART6 + select STM32_USART + select ARCH_HAVE_SERIAL_TERMIOS if !STM32_COMMON_LEGACY && !STM32_COMMON_F0_L0_G0_C0 + select USART6_SERIALDRIVER if STM32_COMMON_F7_H7 + +config STM32_UART7 + bool "UART7" + depends on STM32_HAVE_UART7 + select STM32_USART + select ARCH_HAVE_SERIAL_TERMIOS if !STM32_COMMON_LEGACY && !STM32_COMMON_F0_L0_G0_C0 + select UART7_SERIALDRIVER if STM32_COMMON_F7_H7 + +config STM32_UART8 + bool "UART8" + depends on STM32_HAVE_UART8 + select STM32_USART + select ARCH_HAVE_SERIAL_TERMIOS if !STM32_COMMON_LEGACY && !STM32_COMMON_F0_L0_G0_C0 + select UART8_SERIALDRIVER if STM32_COMMON_F7_H7 + +config STM32_USB + bool "USB Device" + depends on STM32_HAVE_USBDEV + select USBDEV + +config STM32_USBFS + bool "USB Full Speed Device" + depends on STM32_HAVE_USBFS + select USBDEV + select USBDEV if STM32_COMMON_LEGACY || ARCH_CHIP_STM32L4 + +config STM32_LCD + bool "Segment LCD" + depends on STM32_HAVE_LCD + select USBDEV if STM32_COMMON_F0_L0_G0_C0 && STM32_HAVE_LCD + +config STM32_IWDG + bool "IWDG" + depends on STM32_COMMON_LEGACY || STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 + select WATCHDOG + +config STM32_WWDG + bool "WWDG" + depends on STM32_COMMON_LEGACY || STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32U5 + select WATCHDOG if !ARCH_CHIP_STM32U5 + +config STM32_ADC + bool + +config STM32_DAC + bool + +config STM32_DMA + bool + select STM32_DMAMUX if ARCH_CHIP_STM32L4 && STM32_HAVE_DMAMUX + select STM32_DMAMUX if ARCH_CHIP_STM32WB + +config STM32_DMAMUX + bool + +config STM32_SPI + bool + +config STM32_SPI_DMA + bool "SPI DMA" + depends on STM32_SPI_CORE_DMA_CAPABLE + ---help--- + Use DMA to improve SPI transfer performance. Cannot be used with STM32_SPI_INTERRUPT. + +config STM32_I2S + bool + select STM32_SPI_DMA if STM32_COMMON_LEGACY + select STM32_SPI_DMA if ARCH_CHIP_STM32F7 + +config STM32_I2C + bool + +config STM32_CAN + bool + +config STM32_FDCAN + bool + select NET_CAN_HAVE_ERRORS if ARCH_CHIP_STM32H7 + select NET_CAN_HAVE_CANFD if ARCH_CHIP_STM32H7 + select NET_CAN_EXTID if ARCH_CHIP_STM32H7 + select NET_CAN_HAVE_TX_DEADLINE if ARCH_CHIP_STM32H7 + +config STM32_TIM + bool + +config STM32_PWM + bool + +config STM32_COMP + bool "COMP" + depends on STM32_HAVE_COMP + select COMP if ARCH_CHIP_STM32L4 && STM32_HAVE_COMP + +config STM32_OPAMP + bool "OPAMP" + depends on STM32_COMMON_LEGACY || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32U5 + +config STM32_SYSCFG_IOCOMPENSATION + bool "SYSCFG I/O Compensation" + depends on STM32_HAVE_IOCOMPENSATION + select STM32_CSI if ARCH_CHIP_STM32H7 + ---help--- + By default the I/O compensation cell is not used. However when the I/O + output buffer speed is configured in 50 MHz or 100 MHz mode, it is + recommended to use the compensation cell for slew rate control on I/O + tf(IO)out)/tr(IO)out commutation to reduce the I/O noise on power supply. + + The I/O compensation cell can be used only when the supply voltage ranges + from 2.4 to 3.6 V. + +config STM32_FLASH_WORKAROUND_DATA_CACHE_CORRUPTION_ON_RWW + bool "Workaround for FLASH data cache corruption" + depends on (STM32_COMMON_LEGACY && ((STM32_STM32F20XX || STM32_STM32F4XXX) && STM32_FLASH_DCACHE)) || (ARCH_CHIP_STM32L4 && (STM32_STM32L4X5 || STM32_STM32L4X6 || STM32_STM32L4XR)) + ---help--- + Enable the workaround to fix flash data cache corruption when reading + from one flash bank while writing on other flash bank. See your STM32 + errata to check if your STM32 is affected by this problem. + +config STM32_FLASH_PREFETCH + bool "Enable FLASH Pre-fetch" + depends on STM32_COMMON_LEGACY && (STM32_STM32F20XX || STM32_STM32F4XXX) || STM32_COMMON_L4_H5_L5_U5 || ARCH_CHIP_STM32WB + default STM32_STM32F427 || STM32_STM32F429 || STM32_STM32F446 if STM32_COMMON_LEGACY + default y + ---help--- + Enable FLASH prefetch in F2 and F4 parts (FLASH pre-fetch is always enabled + on F1 parts). Some early revisions of F4 parts do not support FLASH pre-fetch + properly and enabling this option may interfere with ADC accuracy. + +config STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG + bool "Disable IDLE Sleep (WFI) in debug mode" + depends on STM32_COMMON_LEGACY || STM32_COMMON_L4_H5_L5_U5 || ARCH_CHIP_STM32WB + ---help--- + In debug configuration, disables the WFI instruction in the IDLE loop + to prevent the JTAG from disconnecting. With some JTAG debuggers, such + as the ST-LINK2 with OpenOCD, if the ARM is put to sleep via the WFI + instruction, the debugger will disconnect, terminating the debug session. + +config STM32_DMACAPABLE + bool "Workaround non-DMA capable memory" + depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7) && ARCH_DMA + default STM32_STM32F4XXX && !STM32_CCMEXCLUDE if STM32_COMMON_LEGACY && ARCH_DMA + ---help--- + This option enables the DMA interface stm32_dmacapable that can be + used to check if it is possible to do DMA from the selected address. + Drivers then may use this information to determine if they should + attempt the DMA or fall back to a different transfer method. + +config STM32_EXTERNAL_RAM + bool "External RAM on FSMC/FMC" + depends on (STM32_COMMON_LEGACY && (STM32_FSMC || STM32_FMC)) || (ARCH_CHIP_STM32F7 && STM32_FMC) + select ARCH_HAVE_HEAP2 if STM32_COMMON_LEGACY && (STM32_FSMC || STM32_FMC) + select ARCH_HAVE_HEAP2 if ARCH_CHIP_STM32F7 && STM32_FMC + ---help--- + In addition to internal SRAM, external RAM may be available through the FSMC/FMC. + +config STM32_TICKLESS_TIMER + int "Tickless hardware timer" + depends on SCHED_TICKLESS + depends on (STM32_COMMON_LEGACY && STM32_TIM) || STM32_COMMON_F7_H7_H5 || ARCH_CHIP_STM32WB + default 2 + range 1 14 if STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7 + range 1 17 if STM32_COMMON_H7_H5 || ARCH_CHIP_STM32WB + ---help--- + If the Tickless OS feature is enabled, then one clock must be + assigned to provided the timer needed by the OS. + +config STM32_TICKLESS_CHANNEL + int "Tickless timer channel" + depends on SCHED_TICKLESS + depends on (STM32_COMMON_LEGACY && STM32_TIM) || STM32_COMMON_F7_H7_H5 || ARCH_CHIP_STM32WB + default 1 + range 1 4 + ---help--- + If the Tickless OS feature is enabled, the one clock must be + assigned to provided the free-running timer needed by the OS + and one channel on that clock is needed to handle intervals. + +config STM32_ONESHOT + bool "TIM one-shot wrapper" + depends on (STM32_COMMON_LEGACY && STM32_TIM) || STM32_COMMON_H7_H5 || ARCH_CHIP_STM32WB || STM32_COMMON_L4_L5_U5 + default y if STM32_COMMON_L4_L5_U5 && SCHED_TICKLESS + ---help--- + Enable a wrapper around the low level timer/counter functions to + support one-shot timer. + +config STM32_FREERUN + bool "TIM free-running wrapper" + depends on (STM32_COMMON_LEGACY && STM32_TIM) || ARCH_CHIP_STM32WB || STM32_COMMON_L4_L5_U5 + default y if STM32_COMMON_L4_L5_U5 && SCHED_TICKLESS + ---help--- + Enable a wrapper around the low level timer/counter functions to + support a free-running timer. + +config STM32_ONESHOT_MAXTIMERS + int "Maximum number of oneshot timers" + depends on STM32_ONESHOT + depends on (STM32_COMMON_LEGACY && STM32_TIM) || ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5 || ARCH_CHIP_STM32WB + default 1 + range 1 8 + ---help--- + Determines the maximum number of oneshot timers that can be + supported. This setting pre-allocates some minimal support for each + of the timers and places an upper limit on the number of oneshot + timers that you can use. + +config STM32_PWM_LL_OPS + bool "PWM low-level operations" + depends on (STM32_COMMON_LEGACY && STM32_TIM) || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5 + ---help--- + Enable low-level PWM ops. + +config STM32_TIM1_PWM + bool "TIM1 PWM" + depends on STM32_TIM1 + depends on STM32_TIM_PWM_COMMON + depends on !STM32_COMMON_LEGACY || STM32_TIM + select STM32_PWM if STM32_TIM_PWM_STM32PWM_COMMON + select PWM if ARCH_CHIP_STM32L5 + select ARCH_HAVE_PWM_PULSECOUNT if ARCH_CHIP_STM32L5 + ---help--- + Reserve timer 1 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32_TIM1 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +config STM32_TIM1_MODE + int "TIM1 Mode" + depends on STM32_TIM1_PWM + default 0 + range 0 4 + ---help--- + Specifies the timer mode. + +config STM32_TIM1_LOCK + int "TIM1 Lock Level Configuration" + depends on STM32_TIM1_PWM + depends on STM32_TIM_PWM_ADVANCED_COMMON + default 0 + range 0 3 + ---help--- + Timer 1 lock level configuration + +config STM32_TIM1_TDTS + int "TIM1 t_DTS Division" + depends on STM32_TIM1_PWM + depends on STM32_TIM_PWM_ADVANCED_COMMON + default 0 + range 0 2 + ---help--- + Timer 1 dead-time and sampling clock (t_DTS) division + +config STM32_TIM1_DEADTIME + int "TIM1 Initial Dead-time" + depends on STM32_TIM1_PWM + depends on STM32_TIM_PWM_ADVANCED_COMMON + default 0 + range 0 255 + ---help--- + Timer 1 initial dead-time + +config STM32_TIM1_CHANNEL1 + bool "TIM1 Channel 1" + depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 1. + +config STM32_TIM1_CH1MODE + int "TIM1 Channel 1 Mode" + depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL1 + default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + default 6 + range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON + range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM1_CH1OUT + bool "TIM1 Channel 1 Output" + depends on STM32_TIM1_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL = 1 && STM32_TIM_PWM_SINGLECHAN_COMMON) + ---help--- + Enables channel 1 output. + +config STM32_TIM1_CH1NOUT + bool "TIM1 Channel 1 Complementary Output" + depends on STM32_TIM1_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL = 1 && STM32_TIM_PWM_SINGLECHAN_COMMON) + depends on STM32_TIM_PWM_INTERNAL_COMMON || STM32_TIM1_CH1OUT || !STM32_PWM_MULTICHAN + ---help--- + Enables channel 1 Complementary Output. + +config STM32_TIM1_CHANNEL2 + bool "TIM1 Channel 2" + depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 2. + +config STM32_TIM1_CH2MODE + int "TIM1 Channel 2 Mode" + depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL2 + default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + default 6 + range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON + range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM1_CH2OUT + bool "TIM1 Channel 2 Output" + depends on STM32_TIM1_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL2) || (!STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL = 2 && STM32_TIM_PWM_SINGLECHAN_COMMON) + ---help--- + Enables channel 2 output. + +config STM32_TIM1_CH2NOUT + bool "TIM1 Channel 2 Complementary Output" + depends on STM32_TIM1_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL2) || (!STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL = 2 && STM32_TIM_PWM_SINGLECHAN_COMMON) + depends on STM32_TIM_PWM_INTERNAL_COMMON || STM32_TIM1_CH2OUT || !STM32_PWM_MULTICHAN + ---help--- + Enables channel 2 Complementary Output. + +config STM32_TIM1_CHANNEL3 + bool "TIM1 Channel 3" + depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 3. + +config STM32_TIM1_CH3MODE + int "TIM1 Channel 3 Mode" + depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL3 + default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + default 6 + range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON + range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM1_CH3OUT + bool "TIM1 Channel 3 Output" + depends on STM32_TIM1_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL3) || (!STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL = 3 && STM32_TIM_PWM_SINGLECHAN_COMMON) + ---help--- + Enables channel 3 output. + +config STM32_TIM1_CH3NOUT + bool "TIM1 Channel 3 Complementary Output" + depends on STM32_TIM1_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL3) || (!STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL = 3 && STM32_TIM_PWM_SINGLECHAN_COMMON) + depends on STM32_TIM_PWM_INTERNAL_COMMON || STM32_TIM1_CH3OUT || !STM32_PWM_MULTICHAN + ---help--- + Enables channel 3 Complementary Output. + +config STM32_TIM1_CHANNEL4 + bool "TIM1 Channel 4" + depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN + depends on STM32_COMMON_F0_L0_G0_C0 || STM32_TIM_PWM_ADVANCED_COMMON + ---help--- + Enables channel 4. + +config STM32_TIM1_CH4MODE + int "TIM1 Channel 4 Mode" + depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN + depends on STM32_TIM1_CHANNEL4 || (STM32_COMMON_L5_U5 && STM32_TIM1_CHANNEL5) + default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + default 6 + range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON + range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM1_CH4OUT + bool "TIM1 Channel 4 Output" + depends on STM32_TIM1_PWM + depends on STM32_PWM_MULTICHAN || (STM32_TIM1_CHANNEL = 4 && STM32_TIM_PWM_SINGLECHAN_COMMON) + depends on !STM32_PWM_MULTICHAN || STM32_TIM1_CHANNEL4 || (STM32_COMMON_L5_U5 && STM32_TIM1_CHANNEL5) + ---help--- + Enables channel 4 output. + +config STM32_TIM1_CHANNEL5 + bool "TIM1 Channel 5 (internal)" + depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN + depends on (STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2) || STM32_COMMON_F7_H7_H5 || STM32_COMMON_L5_U5 + ---help--- + Enables channel 5 (not available externally) + +config STM32_TIM1_CH5MODE + int "TIM1 Channel 5 Mode" + depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL5 + depends on STM32_TIM_PWM_INTERNAL_COMMON + default 6 + range 0 11 + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM1_CH5OUT + bool "TIM1 Channel 5 Output" + depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL5 + depends on STM32_TIM_PWM_INTERNAL_COMMON + ---help--- + Enables channel 5 output. + +config STM32_TIM1_CHANNEL6 + bool "TIM1 Channel 6 (internal)" + depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN + depends on (STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2) || STM32_COMMON_F7_H7_H5 + ---help--- + Enables channel 6 (not available externally) + +config STM32_TIM1_CH6MODE + int "TIM1 Channel 6 Mode" + depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL6 + depends on STM32_TIM_PWM_INTERNAL_COMMON + default 6 + range 0 11 + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM1_CH6OUT + bool "TIM1 Channel 6 Output" + depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL6 + depends on STM32_TIM_PWM_INTERNAL_COMMON + ---help--- + Enables channel 6 output. + +config STM32_TIM1_CHANNEL + int "TIM1 PWM Output Channel" + depends on (STM32_TIM1_PWM && !STM32_PWM_MULTICHAN) || (STM32_TIM1_CAP && ((STM32_COMMON_LEGACY && STM32_TIM) || ARCH_CHIP_STM32H7)) + default 1 + range 1 6 if ARCH_CHIP_STM32H7 && STM32_TIM1_CAP + range 1 4 if !ARCH_CHIP_STM32H7 || !STM32_TIM1_CAP + ---help--- + If TIM1 is enabled for PWM usage, you also need specifies the timer output + channel {1,..,4} + +config STM32_TIM1_CHMODE + int "TIM1 Channel Mode" + depends on STM32_TIM1_PWM && !STM32_PWM_MULTICHAN + default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + default 6 + range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON + range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM2_PWM + bool "TIM2 PWM" + depends on STM32_TIM2 + depends on STM32_TIM_PWM_COMMON + depends on !STM32_COMMON_LEGACY || STM32_TIM + select STM32_PWM if STM32_TIM_PWM_STM32PWM_COMMON + select PWM if ARCH_CHIP_STM32L5 + select ARCH_HAVE_PWM_PULSECOUNT if ARCH_CHIP_STM32L5 + ---help--- + Reserve timer 2 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32_TIM2 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +config STM32_TIM2_MODE + int "TIM2 Mode" + depends on STM32_TIM2_PWM + default 0 + range 0 4 + ---help--- + Specifies the timer mode. + +config STM32_TIM2_CHANNEL1 + bool "TIM2 Channel 1" + depends on STM32_TIM2_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 1. + +config STM32_TIM2_CH1MODE + int "TIM2 Channel 1 Mode" + depends on STM32_TIM2_PWM && STM32_PWM_MULTICHAN && STM32_TIM2_CHANNEL1 + default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + default 6 + range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON + range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM2_CH1OUT + bool "TIM2 Channel 1 Output" + depends on STM32_TIM2_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM2_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM2_CHANNEL = 1 && STM32_TIM_PWM_SINGLECHAN_COMMON) + ---help--- + Enables channel 1 output. + +config STM32_TIM2_CHANNEL2 + bool "TIM2 Channel 2" + depends on STM32_TIM2_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 2. + +config STM32_TIM2_CH2MODE + int "TIM2 Channel 2 Mode" + depends on STM32_TIM2_PWM && STM32_PWM_MULTICHAN && STM32_TIM2_CHANNEL2 + default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + default 6 + range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON + range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM2_CH2OUT + bool "TIM2 Channel 2 Output" + depends on STM32_TIM2_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM2_CHANNEL2) || (!STM32_PWM_MULTICHAN && STM32_TIM2_CHANNEL = 2 && STM32_TIM_PWM_SINGLECHAN_COMMON) + ---help--- + Enables channel 2 output. + +config STM32_TIM2_CHANNEL3 + bool "TIM2 Channel 3" + depends on STM32_TIM2_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 3. + +config STM32_TIM2_CH3MODE + int "TIM2 Channel 3 Mode" + depends on STM32_TIM2_PWM && STM32_PWM_MULTICHAN && STM32_TIM2_CHANNEL3 + default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + default 6 + range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON + range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM2_CH3OUT + bool "TIM2 Channel 3 Output" + depends on STM32_TIM2_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM2_CHANNEL3) || (!STM32_PWM_MULTICHAN && STM32_TIM2_CHANNEL = 3 && STM32_TIM_PWM_SINGLECHAN_COMMON) + ---help--- + Enables channel 3 output. + +config STM32_TIM2_CHANNEL4 + bool "TIM2 Channel 4" + depends on STM32_TIM2_PWM && STM32_PWM_MULTICHAN + depends on STM32_COMMON_F0_L0_G0_C0 || STM32_TIM_PWM_ADVANCED_COMMON + ---help--- + Enables channel 4. + +config STM32_TIM2_CH4MODE + int "TIM2 Channel 4 Mode" + depends on STM32_TIM2_PWM && STM32_PWM_MULTICHAN + depends on STM32_TIM2_CHANNEL4 || (STM32_COMMON_L5_U5 && STM32_TIM2_CHANNEL5) + default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + default 6 + range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON + range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM2_CH4OUT + bool "TIM2 Channel 4 Output" + depends on STM32_TIM2_PWM + depends on STM32_PWM_MULTICHAN || (STM32_TIM2_CHANNEL = 4 && STM32_TIM_PWM_SINGLECHAN_COMMON) + depends on !STM32_PWM_MULTICHAN || STM32_TIM2_CHANNEL4 || (STM32_COMMON_L5_U5 && STM32_TIM2_CHANNEL5) + ---help--- + Enables channel 4 output. + +config STM32_TIM2_CHANNEL + int "TIM2 PWM Output Channel" + depends on (STM32_TIM2_PWM && !STM32_PWM_MULTICHAN) || (STM32_TIM2_CAP && ((STM32_COMMON_LEGACY && STM32_TIM) || ARCH_CHIP_STM32H7)) + default 1 + range 1 4 + ---help--- + If TIM2 is enabled for PWM usage, you also need specifies the timer output + channel {1,..,4} + +config STM32_TIM2_CHMODE + int "TIM2 Channel Mode" + depends on STM32_TIM2_PWM && !STM32_PWM_MULTICHAN + default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + default 6 + range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON + range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM3_PWM + bool "TIM3 PWM" + depends on STM32_TIM3 + depends on STM32_TIM_PWM_COMMON + depends on !STM32_COMMON_LEGACY || STM32_TIM + select STM32_PWM if STM32_TIM_PWM_STM32PWM_COMMON + select PWM if ARCH_CHIP_STM32L5 + select ARCH_HAVE_PWM_PULSECOUNT if ARCH_CHIP_STM32L5 + ---help--- + Reserve timer 3 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32_TIM3 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +config STM32_TIM3_MODE + int "TIM3 Mode" + depends on STM32_TIM3_PWM + default 0 + range 0 4 + ---help--- + Specifies the timer mode. + +config STM32_TIM3_CHANNEL1 + bool "TIM3 Channel 1" + depends on STM32_TIM3_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 1. + +config STM32_TIM3_CH1MODE + int "TIM3 Channel 1 Mode" + depends on STM32_TIM3_PWM && STM32_PWM_MULTICHAN && STM32_TIM3_CHANNEL1 + default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + default 6 + range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON + range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM3_CH1OUT + bool "TIM3 Channel 1 Output" + depends on STM32_TIM3_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM3_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM3_CHANNEL = 1 && STM32_TIM_PWM_SINGLECHAN_COMMON) + ---help--- + Enables channel 1 output. + +config STM32_TIM3_CHANNEL2 + bool "TIM3 Channel 2" + depends on STM32_TIM3_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 2. + +config STM32_TIM3_CH2MODE + int "TIM3 Channel 2 Mode" + depends on STM32_TIM3_PWM && STM32_PWM_MULTICHAN && STM32_TIM3_CHANNEL2 + default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + default 6 + range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON + range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM3_CH2OUT + bool "TIM3 Channel 2 Output" + depends on STM32_TIM3_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM3_CHANNEL2) || (!STM32_PWM_MULTICHAN && STM32_TIM3_CHANNEL = 2 && STM32_TIM_PWM_SINGLECHAN_COMMON) + ---help--- + Enables channel 2 output. + +config STM32_TIM3_CHANNEL3 + bool "TIM3 Channel 3" + depends on STM32_TIM3_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 3. + +config STM32_TIM3_CH3MODE + int "TIM3 Channel 3 Mode" + depends on STM32_TIM3_PWM && STM32_PWM_MULTICHAN && STM32_TIM3_CHANNEL3 + default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + default 6 + range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON + range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM3_CH3OUT + bool "TIM3 Channel 3 Output" + depends on STM32_TIM3_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM3_CHANNEL3) || (!STM32_PWM_MULTICHAN && STM32_TIM3_CHANNEL = 3 && STM32_TIM_PWM_SINGLECHAN_COMMON) + ---help--- + Enables channel 3 output. + +config STM32_TIM3_CHANNEL4 + bool "TIM3 Channel 4" + depends on STM32_TIM3_PWM && STM32_PWM_MULTICHAN + depends on STM32_COMMON_F0_L0_G0_C0 || STM32_TIM_PWM_ADVANCED_COMMON + ---help--- + Enables channel 4. + +config STM32_TIM3_CH4MODE + int "TIM3 Channel 4 Mode" + depends on STM32_TIM3_PWM && STM32_PWM_MULTICHAN + depends on STM32_TIM3_CHANNEL4 || (STM32_COMMON_L5_U5 && STM32_TIM3_CHANNEL5) + default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + default 6 + range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON + range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM3_CH4OUT + bool "TIM3 Channel 4 Output" + depends on STM32_TIM3_PWM + depends on STM32_PWM_MULTICHAN || (STM32_TIM3_CHANNEL = 4 && STM32_TIM_PWM_SINGLECHAN_COMMON) + depends on !STM32_PWM_MULTICHAN || STM32_TIM3_CHANNEL4 || (STM32_COMMON_L5_U5 && STM32_TIM3_CHANNEL5) + ---help--- + Enables channel 4 output. + +config STM32_TIM3_CHANNEL + int "TIM3 PWM Output Channel" + depends on (STM32_TIM3_PWM && !STM32_PWM_MULTICHAN) || (STM32_TIM3_CAP && ((STM32_COMMON_LEGACY && STM32_TIM) || ARCH_CHIP_STM32H7)) + default 1 + range 1 4 + ---help--- + If TIM3 is enabled for PWM usage, you also need specifies the timer output + channel {1,..,4} + +config STM32_TIM3_CHMODE + int "TIM3 Channel Mode" + depends on STM32_TIM3_PWM && !STM32_PWM_MULTICHAN + default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + default 6 + range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON + range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM4_PWM + bool "TIM4 PWM" + depends on STM32_TIM4 + depends on STM32_TIM_PWM_NO_F0_COMMON + depends on !STM32_COMMON_LEGACY || STM32_TIM + select STM32_PWM if STM32_TIM_PWM_STM32PWM_COMMON + select PWM if ARCH_CHIP_STM32L5 + select ARCH_HAVE_PWM_PULSECOUNT if ARCH_CHIP_STM32L5 + ---help--- + Reserve timer 4 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32_TIM4 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +config STM32_TIM4_MODE + int "TIM4 Mode" + depends on STM32_TIM4_PWM + default 0 + range 0 4 + ---help--- + Specifies the timer mode. + +config STM32_TIM4_CHANNEL1 + bool "TIM4 Channel 1" + depends on STM32_TIM4_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 1. + +config STM32_TIM4_CH1MODE + int "TIM4 Channel 1 Mode" + depends on STM32_TIM4_PWM && STM32_PWM_MULTICHAN && STM32_TIM4_CHANNEL1 + default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + default 6 + range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON + range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM4_CH1OUT + bool "TIM4 Channel 1 Output" + depends on STM32_TIM4_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM4_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM4_CHANNEL = 1 && STM32_TIM_PWM_SINGLECHAN_COMMON) + ---help--- + Enables channel 1 output. + +config STM32_TIM4_CHANNEL2 + bool "TIM4 Channel 2" + depends on STM32_TIM4_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 2. + +config STM32_TIM4_CH2MODE + int "TIM4 Channel 2 Mode" + depends on STM32_TIM4_PWM && STM32_PWM_MULTICHAN && STM32_TIM4_CHANNEL2 + default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + default 6 + range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON + range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM4_CH2OUT + bool "TIM4 Channel 2 Output" + depends on STM32_TIM4_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM4_CHANNEL2) || (!STM32_PWM_MULTICHAN && STM32_TIM4_CHANNEL = 2 && STM32_TIM_PWM_SINGLECHAN_COMMON) + ---help--- + Enables channel 2 output. + +config STM32_TIM4_CHANNEL3 + bool "TIM4 Channel 3" + depends on STM32_TIM4_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 3. + +config STM32_TIM4_CH3MODE + int "TIM4 Channel 3 Mode" + depends on STM32_TIM4_PWM && STM32_PWM_MULTICHAN && STM32_TIM4_CHANNEL3 + default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + default 6 + range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON + range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM4_CH3OUT + bool "TIM4 Channel 3 Output" + depends on STM32_TIM4_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM4_CHANNEL3) || (!STM32_PWM_MULTICHAN && STM32_TIM4_CHANNEL = 3 && STM32_TIM_PWM_SINGLECHAN_COMMON) + ---help--- + Enables channel 3 output. + +config STM32_TIM4_CHANNEL4 + bool "TIM4 Channel 4" + depends on STM32_TIM4_PWM && STM32_PWM_MULTICHAN + depends on STM32_TIM_PWM_ADVANCED_COMMON + ---help--- + Enables channel 4. + +config STM32_TIM4_CH4MODE + int "TIM4 Channel 4 Mode" + depends on STM32_TIM4_PWM && STM32_PWM_MULTICHAN + depends on STM32_TIM4_CHANNEL4 || (STM32_COMMON_L5_U5 && STM32_TIM4_CHANNEL5) + default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + default 6 + range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON + range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM4_CH4OUT + bool "TIM4 Channel 4 Output" + depends on STM32_TIM4_PWM + depends on STM32_PWM_MULTICHAN || (STM32_TIM4_CHANNEL = 4 && STM32_TIM_PWM_SINGLECHAN_COMMON) + depends on !STM32_PWM_MULTICHAN || STM32_TIM4_CHANNEL4 || (STM32_COMMON_L5_U5 && STM32_TIM4_CHANNEL5) + ---help--- + Enables channel 4 output. + +config STM32_TIM4_CHANNEL + int "TIM4 PWM Output Channel" + depends on (STM32_TIM4_PWM && !STM32_PWM_MULTICHAN) || (STM32_TIM4_CAP && ((STM32_COMMON_LEGACY && STM32_TIM) || ARCH_CHIP_STM32H7)) + default 1 + range 1 4 + ---help--- + If TIM4 is enabled for PWM usage, you also need specifies the timer output + channel {1,..,4} + +config STM32_TIM4_CHMODE + int "TIM4 Channel Mode" + depends on STM32_TIM4_PWM && !STM32_PWM_MULTICHAN + default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + default 6 + range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON + range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM5_PWM + bool "TIM5 PWM" + depends on STM32_TIM5 + depends on STM32_TIM_PWM_NO_F0_COMMON + depends on !STM32_COMMON_LEGACY || STM32_TIM + select STM32_PWM if STM32_TIM_PWM_STM32PWM_COMMON + select PWM if ARCH_CHIP_STM32L5 + select ARCH_HAVE_PWM_PULSECOUNT if ARCH_CHIP_STM32L5 + ---help--- + Reserve timer 5 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32_TIM5 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +config STM32_TIM5_MODE + int "TIM5 Mode" + depends on STM32_TIM5_PWM + default 0 + range 0 4 + ---help--- + Specifies the timer mode. + +config STM32_TIM5_CHANNEL1 + bool "TIM5 Channel 1" + depends on STM32_TIM5_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 1. + +config STM32_TIM5_CH1MODE + int "TIM5 Channel 1 Mode" + depends on STM32_TIM5_PWM && STM32_PWM_MULTICHAN && STM32_TIM5_CHANNEL1 + default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + default 6 + range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON + range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM5_CH1OUT + bool "TIM5 Channel 1 Output" + depends on STM32_TIM5_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM5_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM5_CHANNEL = 1 && STM32_TIM_PWM_SINGLECHAN_COMMON) + ---help--- + Enables channel 1 output. + +config STM32_TIM5_CHANNEL2 + bool "TIM5 Channel 2" + depends on STM32_TIM5_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 2. + +config STM32_TIM5_CH2MODE + int "TIM5 Channel 2 Mode" + depends on STM32_TIM5_PWM && STM32_PWM_MULTICHAN && STM32_TIM5_CHANNEL2 + default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + default 6 + range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON + range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM5_CH2OUT + bool "TIM5 Channel 2 Output" + depends on STM32_TIM5_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM5_CHANNEL2) || (!STM32_PWM_MULTICHAN && STM32_TIM5_CHANNEL = 2 && STM32_TIM_PWM_SINGLECHAN_COMMON) + ---help--- + Enables channel 2 output. + +config STM32_TIM5_CHANNEL3 + bool "TIM5 Channel 3" + depends on STM32_TIM5_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 3. + +config STM32_TIM5_CH3MODE + int "TIM5 Channel 3 Mode" + depends on STM32_TIM5_PWM && STM32_PWM_MULTICHAN && STM32_TIM5_CHANNEL3 + default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + default 6 + range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON + range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM5_CH3OUT + bool "TIM5 Channel 3 Output" + depends on STM32_TIM5_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM5_CHANNEL3) || (!STM32_PWM_MULTICHAN && STM32_TIM5_CHANNEL = 3 && STM32_TIM_PWM_SINGLECHAN_COMMON) + ---help--- + Enables channel 3 output. + +config STM32_TIM5_CHANNEL4 + bool "TIM5 Channel 4" + depends on STM32_TIM5_PWM && STM32_PWM_MULTICHAN + depends on STM32_TIM_PWM_ADVANCED_COMMON + ---help--- + Enables channel 4. + +config STM32_TIM5_CH4MODE + int "TIM5 Channel 4 Mode" + depends on STM32_TIM5_PWM && STM32_PWM_MULTICHAN + depends on STM32_TIM5_CHANNEL4 || (STM32_COMMON_L5_U5 && STM32_TIM5_CHANNEL5) + default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + default 6 + range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON + range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM5_CH4OUT + bool "TIM5 Channel 4 Output" + depends on STM32_TIM5_PWM + depends on STM32_PWM_MULTICHAN || (STM32_TIM5_CHANNEL = 4 && STM32_TIM_PWM_SINGLECHAN_COMMON) + depends on !STM32_PWM_MULTICHAN || STM32_TIM5_CHANNEL4 || (STM32_COMMON_L5_U5 && STM32_TIM5_CHANNEL5) + ---help--- + Enables channel 4 output. + +config STM32_TIM5_CHANNEL + int "TIM5 PWM Output Channel" + depends on (STM32_TIM5_PWM && !STM32_PWM_MULTICHAN) || (STM32_TIM5_CAP && ((STM32_COMMON_LEGACY && STM32_TIM) || ARCH_CHIP_STM32H7)) + default 1 + range 1 4 + ---help--- + If TIM5 is enabled for PWM usage, you also need specifies the timer output + channel {1,..,4} + +config STM32_TIM5_CHMODE + int "TIM5 Channel Mode" + depends on STM32_TIM5_PWM && !STM32_PWM_MULTICHAN + default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + default 6 + range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON + range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM8_PWM + bool "TIM8 PWM" + depends on STM32_TIM8 + depends on STM32_TIM_PWM_NO_F0_COMMON + depends on !STM32_COMMON_LEGACY || STM32_TIM + select STM32_PWM if STM32_TIM_PWM_STM32PWM_COMMON + select PWM if ARCH_CHIP_STM32L5 + select ARCH_HAVE_PWM_PULSECOUNT if ARCH_CHIP_STM32L5 + ---help--- + Reserve timer 8 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32_TIM8 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +config STM32_TIM8_MODE + int "TIM8 Mode" + depends on STM32_TIM8_PWM + default 0 + range 0 4 + ---help--- + Specifies the timer mode. + +config STM32_TIM8_LOCK + int "TIM8 Lock Level Configuration" + depends on STM32_TIM8_PWM + depends on STM32_TIM_PWM_ADVANCED_COMMON + default 0 + range 0 3 + ---help--- + Timer 8 lock level configuration + +config STM32_TIM8_DEADTIME + int "TIM8 Initial Dead-time" + depends on STM32_TIM8_PWM + depends on STM32_TIM_PWM_ADVANCED_COMMON + default 0 + range 0 255 + ---help--- + Timer 8 initial dead-time + +config STM32_TIM8_TDTS + int "TIM8 t_DTS Division" + depends on STM32_TIM8_PWM + depends on STM32_TIM_PWM_ADVANCED_COMMON + default 0 + range 0 2 + ---help--- + Timer 8 dead-time and sampling clock (t_DTS) division + +config STM32_TIM8_CHANNEL1 + bool "TIM8 Channel 1" + depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 1. + +config STM32_TIM8_CH1MODE + int "TIM8 Channel 1 Mode" + depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL1 + default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + default 6 + range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON + range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM8_CH1OUT + bool "TIM8 Channel 1 Output" + depends on STM32_TIM8_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL = 1 && STM32_TIM_PWM_SINGLECHAN_COMMON) + ---help--- + Enables channel 1 output. + +config STM32_TIM8_CH1NOUT + bool "TIM8 Channel 1 Complementary Output" + depends on STM32_TIM8_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL = 1 && STM32_TIM_PWM_SINGLECHAN_COMMON) + depends on STM32_TIM_PWM_INTERNAL_COMMON || STM32_TIM8_CH1OUT || !STM32_PWM_MULTICHAN + ---help--- + Enables channel 1 Complementary Output. + +config STM32_TIM8_CHANNEL2 + bool "TIM8 Channel 2" + depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 2. + +config STM32_TIM8_CH2MODE + int "TIM8 Channel 2 Mode" + depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL2 + default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + default 6 + range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON + range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM8_CH2OUT + bool "TIM8 Channel 2 Output" + depends on STM32_TIM8_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL2) || (!STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL = 2 && STM32_TIM_PWM_SINGLECHAN_COMMON) + ---help--- + Enables channel 2 output. + +config STM32_TIM8_CH2NOUT + bool "TIM8 Channel 2 Complementary Output" + depends on STM32_TIM8_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL2) || (!STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL = 2 && STM32_TIM_PWM_SINGLECHAN_COMMON) + depends on STM32_TIM_PWM_INTERNAL_COMMON || STM32_TIM8_CH2OUT || !STM32_PWM_MULTICHAN + ---help--- + Enables channel 2 Complementary Output. + +config STM32_TIM8_CHANNEL3 + bool "TIM8 Channel 3" + depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 3. + +config STM32_TIM8_CH3MODE + int "TIM8 Channel 3 Mode" + depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL3 + default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + default 6 + range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON + range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM8_CH3OUT + bool "TIM8 Channel 3 Output" + depends on STM32_TIM8_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL3) || (!STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL = 3 && STM32_TIM_PWM_SINGLECHAN_COMMON) + ---help--- + Enables channel 3 output. + +config STM32_TIM8_CH3NOUT + bool "TIM8 Channel 3 Complementary Output" + depends on STM32_TIM8_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL3) || (!STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL = 3 && STM32_TIM_PWM_SINGLECHAN_COMMON) + depends on STM32_TIM_PWM_INTERNAL_COMMON || STM32_TIM8_CH3OUT || !STM32_PWM_MULTICHAN + ---help--- + Enables channel 3 Complementary Output. + +config STM32_TIM8_CHANNEL4 + bool "TIM8 Channel 4" + depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN + depends on STM32_TIM_PWM_ADVANCED_COMMON + ---help--- + Enables channel 4. + +config STM32_TIM8_CH4MODE + int "TIM8 Channel 4 Mode" + depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN + depends on STM32_TIM8_CHANNEL4 || (STM32_COMMON_L5_U5 && STM32_TIM8_CHANNEL5) + default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + default 6 + range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON + range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM8_CH4OUT + bool "TIM8 Channel 4 Output" + depends on STM32_TIM8_PWM + depends on STM32_PWM_MULTICHAN || (STM32_TIM8_CHANNEL = 4 && STM32_TIM_PWM_SINGLECHAN_COMMON) + depends on !STM32_PWM_MULTICHAN || STM32_TIM8_CHANNEL4 || (STM32_COMMON_L5_U5 && STM32_TIM8_CHANNEL5) + ---help--- + Enables channel 4 output. + +config STM32_TIM8_CHANNEL5 + bool "TIM8 Channel 5 (internal)" + depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN + depends on (STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2) || STM32_COMMON_F7_H7_H5 || STM32_COMMON_L5_U5 + ---help--- + Enables channel 5 (not available externally) + +config STM32_TIM8_CH5MODE + int "TIM8 Channel 5 Mode" + depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL5 + depends on STM32_TIM_PWM_INTERNAL_COMMON + default 6 + range 0 11 + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM8_CH5OUT + bool "TIM8 Channel 5 Output" + depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL5 + depends on STM32_TIM_PWM_INTERNAL_COMMON + ---help--- + Enables channel 5 output. + +config STM32_TIM8_CHANNEL6 + bool "TIM8 Channel 6 (internal)" + depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN + depends on (STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2) || STM32_COMMON_F7_H7_H5 + ---help--- + Enables channel 6 (not available externally) + +config STM32_TIM8_CH6MODE + int "TIM8 Channel 6 Mode" + depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL6 + depends on STM32_TIM_PWM_INTERNAL_COMMON + default 6 + range 0 11 + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM8_CH6OUT + bool "TIM8 Channel 6 Output" + depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL6 + depends on STM32_TIM_PWM_INTERNAL_COMMON + ---help--- + Enables channel 6 output. + +config STM32_TIM8_CHANNEL + int "TIM8 PWM Output Channel" + depends on (STM32_TIM8_PWM && !STM32_PWM_MULTICHAN) || (STM32_TIM8_CAP && ((STM32_COMMON_LEGACY && STM32_TIM) || ARCH_CHIP_STM32H7)) + default 1 + range 1 6 if ARCH_CHIP_STM32H7 && STM32_TIM8_CAP + range 1 4 if !ARCH_CHIP_STM32H7 || !STM32_TIM8_CAP + ---help--- + If TIM8 is enabled for PWM usage, you also need specifies the timer output + channel {1,..,4} + +config STM32_TIM8_CHMODE + int "TIM8 Channel Mode" + depends on STM32_TIM8_PWM && !STM32_PWM_MULTICHAN + default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + default 6 + range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON + range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM9_PWM + bool "TIM9 PWM" + depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM9) || (ARCH_CHIP_STM32F7 && STM32_TIM9) + select STM32_PWM if STM32_TIM_PWM_STM32PWM_COMMON + ---help--- + Reserve timer 9 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32_TIM9 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +config STM32_TIM9_CHANNEL1 + bool "TIM9 Channel 1" + depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM9_PWM && STM32_PWM_MULTICHAN) || (ARCH_CHIP_STM32F7 && STM32_TIM9_PWM && STM32_PWM_MULTICHAN) + ---help--- + Enables channel 1. + +config STM32_TIM9_CH1MODE + int "TIM9 Channel 1 Mode" + depends on STM32_TIM9_PWM && STM32_PWM_MULTICHAN && STM32_TIM9_CHANNEL1 + default 6 + range 0 11 if STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2 + range 0 9 if ARCH_CHIP_STM32F7 + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM9_CH1OUT + bool "TIM9 Channel 1 Output" + depends on STM32_TIM9_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM9_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM9_CHANNEL = 1) + ---help--- + Enables channel 1 output. + +config STM32_TIM9_CHANNEL2 + bool "TIM9 Channel 2" + depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM9_PWM && STM32_PWM_MULTICHAN) || (ARCH_CHIP_STM32F7 && STM32_TIM9_PWM && STM32_PWM_MULTICHAN) + ---help--- + Enables channel 2. + +config STM32_TIM9_CH2MODE + int "TIM9 Channel 2 Mode" + depends on STM32_TIM9_PWM && STM32_PWM_MULTICHAN && STM32_TIM9_CHANNEL2 + default 6 + range 0 11 if STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2 + range 0 9 if ARCH_CHIP_STM32F7 + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM9_CH2OUT + bool "TIM9 Channel 2 Output" + depends on STM32_TIM9_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM9_CHANNEL2) || (!STM32_PWM_MULTICHAN && STM32_TIM9_CHANNEL = 2) + ---help--- + Enables channel 2 output. + +config STM32_TIM9_CHANNEL + int "TIM9 PWM Output Channel" + depends on (STM32_TIM9_PWM && !STM32_PWM_MULTICHAN) || (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM9_CAP) + default 1 + range 1 4 if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM9_CAP + range 1 2 if !STM32_COMMON_LEGACY || !STM32_TIM9_CAP + ---help--- + If TIM9 is enabled for PWM usage, you also need specifies the timer output + channel {1,2} + +config STM32_TIM9_CHMODE + int "TIM9 Channel Mode" + depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM9_PWM && !STM32_PWM_MULTICHAN) || (ARCH_CHIP_STM32F7 && STM32_TIM9_PWM && !STM32_PWM_MULTICHAN) + default 6 + range 0 11 if STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2 + range 0 9 if ARCH_CHIP_STM32F7 + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM10_PWM + bool "TIM10 PWM" + depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM10) || (ARCH_CHIP_STM32F7 && STM32_TIM10) + select STM32_PWM if STM32_TIM_PWM_STM32PWM_COMMON + ---help--- + Reserve timer 10 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32_TIM10 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +config STM32_TIM10_CHANNEL1 + bool "TIM10 Channel 1" + depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM10_PWM && STM32_PWM_MULTICHAN) || (ARCH_CHIP_STM32F7 && STM32_TIM10_PWM && STM32_PWM_MULTICHAN) + ---help--- + Enables channel 1. + +config STM32_TIM10_CH1MODE + int "TIM10 Channel 1 Mode" + depends on STM32_TIM10_PWM && STM32_PWM_MULTICHAN && STM32_TIM10_CHANNEL1 + default 6 + range 0 11 if STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2 + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON || ARCH_CHIP_STM32F7 + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM10_CH1OUT + bool "TIM10 Channel 1 Output" + depends on STM32_TIM10_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM10_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM10_CHANNEL = 1) + ---help--- + Enables channel 1 output. + +config STM32_TIM10_CHANNEL + int "TIM10 PWM Output Channel" + depends on (STM32_TIM10_PWM && !STM32_PWM_MULTICHAN) || (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM10_CAP) + default 1 + range 1 4 if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM10_CAP + range 1 1 if !STM32_COMMON_LEGACY || !STM32_TIM10_CAP + ---help--- + If TIM10 is enabled for PWM usage, you also need specifies the timer output + channel {1} + +config STM32_TIM10_CHMODE + int "TIM10 Channel Mode" + depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM10_PWM && !STM32_PWM_MULTICHAN) || (ARCH_CHIP_STM32F7 && STM32_TIM10_PWM && !STM32_PWM_MULTICHAN) + default 6 + range 0 11 if STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2 + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON || ARCH_CHIP_STM32F7 + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM11_PWM + bool "TIM11 PWM" + depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM11) || (ARCH_CHIP_STM32F7 && STM32_TIM11) + select STM32_PWM if STM32_TIM_PWM_STM32PWM_COMMON + ---help--- + Reserve timer 11 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32_TIM11 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +config STM32_TIM11_CHANNEL1 + bool "TIM11 Channel 1" + depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM11_PWM && STM32_PWM_MULTICHAN) || (ARCH_CHIP_STM32F7 && STM32_TIM11_PWM && STM32_PWM_MULTICHAN) + ---help--- + Enables channel 1. + +config STM32_TIM11_CH1MODE + int "TIM11 Channel 1 Mode" + depends on STM32_TIM11_PWM && STM32_PWM_MULTICHAN && STM32_TIM11_CHANNEL1 + default 6 + range 0 11 if STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2 + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON || ARCH_CHIP_STM32F7 + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM11_CH1OUT + bool "TIM11 Channel 1 Output" + depends on STM32_TIM11_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM11_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM11_CHANNEL = 1) + ---help--- + Enables channel 1 output. + +config STM32_TIM11_CHANNEL + int "TIM11 PWM Output Channel" + depends on (STM32_TIM11_PWM && !STM32_PWM_MULTICHAN) || (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM11_CAP) + default 1 + range 1 4 if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM11_CAP + range 1 1 if !STM32_COMMON_LEGACY || !STM32_TIM11_CAP + ---help--- + If TIM11 is enabled for PWM usage, you also need specifies the timer output + channel {1} + +config STM32_TIM11_CHMODE + int "TIM11 Channel Mode" + depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM11_PWM && !STM32_PWM_MULTICHAN) || (ARCH_CHIP_STM32F7 && STM32_TIM11_PWM && !STM32_PWM_MULTICHAN) + default 6 + range 0 11 if STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2 + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON || ARCH_CHIP_STM32F7 + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM12_PWM + bool "TIM12 PWM" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM12 || (STM32_COMMON_F7_H7_H5) && STM32_TIM12 + select STM32_PWM if STM32_TIM_PWM_STM32PWM_COMMON + ---help--- + Reserve timer 12 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32_TIM12 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +config STM32_TIM12_CHANNEL1 + bool "TIM12 Channel 1" + depends on STM32_TIM12_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 1. + +config STM32_TIM12_CH1MODE + int "TIM12 Channel 1 Mode" + depends on STM32_TIM12_PWM && STM32_PWM_MULTICHAN && STM32_TIM12_CHANNEL1 + default 6 + range 0 11 if (STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2) || STM32_COMMON_H7_H5 + range 0 9 if ARCH_CHIP_STM32F7 + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM12_CH1OUT + bool "TIM12 Channel 1 Output" + depends on STM32_TIM12_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM12_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM12_CHANNEL = 1 && STM32_TIM_PWM_INTERNAL_COMMON) + ---help--- + Enables channel 1 output. + +config STM32_TIM12_CHANNEL2 + bool "TIM12 Channel 2" + depends on STM32_TIM12_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 2. + +config STM32_TIM12_CH2MODE + int "TIM12 Channel 2 Mode" + depends on STM32_TIM12_PWM && STM32_PWM_MULTICHAN && STM32_TIM12_CHANNEL2 + default 6 + range 0 11 if (STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2) || STM32_COMMON_H7_H5 + range 0 9 if ARCH_CHIP_STM32F7 + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM12_CH2OUT + bool "TIM12 Channel 2 Output" + depends on STM32_TIM12_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM12_CHANNEL2) || (!STM32_PWM_MULTICHAN && STM32_TIM12_CHANNEL = 2 && STM32_TIM_PWM_INTERNAL_COMMON) + ---help--- + Enables channel 2 output. + +config STM32_TIM12_CHANNEL + int "TIM12 PWM Output Channel" + depends on (STM32_TIM12_PWM && !STM32_PWM_MULTICHAN) || (STM32_TIM12_CAP && ((STM32_COMMON_LEGACY && STM32_TIM) || ARCH_CHIP_STM32H7)) + default 1 + range 1 4 if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM12_CAP + range 1 2 if !STM32_COMMON_LEGACY || !STM32_TIM12_CAP + ---help--- + If TIM12 is enabled for PWM usage, you also need specifies the timer output + channel {1,2} + +config STM32_TIM12_CHMODE + int "TIM12 Channel Mode" + depends on STM32_TIM12_PWM && !STM32_PWM_MULTICHAN + default 6 + range 0 11 if (STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2) || STM32_COMMON_H7_H5 + range 0 9 if ARCH_CHIP_STM32F7 + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM13_PWM + bool "TIM13 PWM" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM13 || (STM32_COMMON_F7_H7_H5) && STM32_TIM13 + select STM32_PWM if STM32_TIM_PWM_STM32PWM_COMMON + ---help--- + Reserve timer 13 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32_TIM13 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +config STM32_TIM13_CHANNEL1 + bool "TIM13 Channel 1" + depends on STM32_TIM13_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 1. + +config STM32_TIM13_CH1MODE + int "TIM13 Channel 1 Mode" + depends on STM32_TIM13_PWM && STM32_PWM_MULTICHAN && STM32_TIM13_CHANNEL1 + default 6 + range 0 11 if (STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2) || STM32_COMMON_H7_H5 + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON || ARCH_CHIP_STM32F7 + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM13_CH1OUT + bool "TIM13 Channel 1 Output" + depends on STM32_TIM13_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM13_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM13_CHANNEL = 1 && STM32_TIM_PWM_INTERNAL_COMMON) + ---help--- + Enables channel 1 output. + +config STM32_TIM13_CHANNEL + int "TIM13 PWM Output Channel" + depends on (STM32_TIM13_PWM && !STM32_PWM_MULTICHAN) || (STM32_TIM13_CAP && ((STM32_COMMON_LEGACY && STM32_TIM) || ARCH_CHIP_STM32H7)) + default 1 + range 1 4 if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM13_CAP + range 1 1 if !STM32_COMMON_LEGACY || !STM32_TIM13_CAP + ---help--- + If TIM13 is enabled for PWM usage, you also need specifies the timer output + channel {1} + +config STM32_TIM13_CHMODE + int "TIM13 Channel Mode" + depends on STM32_TIM13_PWM && !STM32_PWM_MULTICHAN + default 6 + range 0 11 if (STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2) || STM32_COMMON_H7_H5 + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON || ARCH_CHIP_STM32F7 + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM14_PWM + bool "TIM14 PWM" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM14 || (STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_F7_H7_H5) && STM32_TIM14 + select STM32_PWM if STM32_TIM_PWM_STM32PWM_COMMON + ---help--- + Reserve timer 14 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32_TIM14 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +config STM32_TIM14_CHANNEL1 + bool "TIM14 Channel 1" + depends on STM32_TIM14_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 1. + +config STM32_TIM14_CH1MODE + int "TIM14 Channel 1 Mode" + depends on STM32_TIM14_PWM && STM32_PWM_MULTICHAN && STM32_TIM14_CHANNEL1 + default 0 if STM32_COMMON_F0_L0_G0_C0 + default 6 + range 0 11 if (STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2) || STM32_COMMON_H7_H5 + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON || ARCH_CHIP_STM32F7 + range 0 1 if STM32_COMMON_F0_L0_G0_C0 + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM14_CH1OUT + bool "TIM14 Channel 1 Output" + depends on STM32_TIM14_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM14_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM14_CHANNEL = 1 && STM32_TIM_PWM_INTERNAL_COMMON) + ---help--- + Enables channel 1 output. + +config STM32_TIM14_CHANNEL + int "TIM14 PWM Output Channel" + depends on (STM32_TIM14_PWM && !STM32_PWM_MULTICHAN) || (STM32_TIM14_CAP && ((STM32_COMMON_LEGACY && STM32_TIM) || ARCH_CHIP_STM32H7)) + default 1 + range 1 4 if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM14_CAP + range 1 1 if !STM32_COMMON_LEGACY || !STM32_TIM14_CAP + ---help--- + If TIM14 is enabled for PWM usage, you also need specifies the timer output + channel {1} + +config STM32_TIM14_CHMODE + int "TIM14 Channel Mode" + depends on STM32_TIM14_PWM && !STM32_PWM_MULTICHAN + default 0 if STM32_COMMON_F0_L0_G0_C0 + default 6 + range 0 11 if (STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2) || STM32_COMMON_H7_H5 + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON || ARCH_CHIP_STM32F7 + range 0 1 if STM32_COMMON_F0_L0_G0_C0 + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM15_PWM + bool "TIM15 PWM" + depends on STM32_TIM15 + depends on (STM32_COMMON_LEGACY && STM32_TIM) || STM32_COMMON_F0_L0_G0_C0 || ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5 || STM32_COMMON_L5_U5 + select STM32_PWM if STM32_TIM_PWM_STM32PWM_COMMON + select PWM if ARCH_CHIP_STM32L5 + ---help--- + Reserve timer 15 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32_TIM15 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +config STM32_TIM15_LOCK + int "TIM15 Lock Level Configuration" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM15_PWM || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM15_PWM + default 0 + range 0 3 + ---help--- + Timer 15 lock level configuration + +config STM32_TIM15_TDTS + int "TIM15 t_DTS Division" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM15_PWM || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM15_PWM + default 0 + range 0 2 + ---help--- + Timer 15 dead-time and sampling clock (t_DTS) division + +config STM32_TIM15_DEADTIME + int "TIM15 Initial Dead-time" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM15_PWM || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM15_PWM + default 0 + range 0 255 + ---help--- + Timer 15 initial dead-time + +config STM32_TIM15_CHANNEL1 + bool "TIM15 Channel 1" + depends on STM32_TIM15_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 1. + +config STM32_TIM15_CH1MODE + int "TIM15 Channel 1 Mode" + depends on STM32_TIM15_PWM && STM32_PWM_MULTICHAN && STM32_TIM15_CHANNEL1 + default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + default 6 + range 0 11 if ARCH_CHIP_STM32L4 + range 0 9 if (STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2) || STM32_COMMON_H7_H5 + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON + range 0 3 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM15_CH1OUT + bool "TIM15 Channel 1 Output" + depends on STM32_TIM15_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM15_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM15_CHANNEL = 1 && STM32_TIM_PWM_SINGLECHAN_COMMON) + ---help--- + Enables channel 1 output. + +config STM32_TIM15_CH1NOUT + bool "TIM15 Channel 1 Complementary Output" + depends on STM32_TIM15_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM15_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM15_CHANNEL = 1 && STM32_TIM_PWM_SINGLECHAN_COMMON) + depends on STM32_TIM_PWM_INTERNAL_COMMON || STM32_TIM15_CH1OUT || !STM32_PWM_MULTICHAN + ---help--- + Enables channel 1 Complementary Output. + +config STM32_TIM15_CHANNEL2 + bool "TIM15 Channel 2" + depends on STM32_TIM15_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 2. + +config STM32_TIM15_CH2MODE + int "TIM15 Channel 2 Mode" + depends on STM32_TIM15_PWM && STM32_PWM_MULTICHAN && STM32_TIM15_CHANNEL2 + default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + default 6 + range 0 11 if ARCH_CHIP_STM32L4 + range 0 9 if (STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2) || STM32_COMMON_H7_H5 + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON + range 0 3 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM15_CH2OUT + bool "TIM15 Channel 2 Output" + depends on STM32_TIM15_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM15_CHANNEL2) || (!STM32_PWM_MULTICHAN && STM32_TIM15_CHANNEL = 2 && STM32_TIM_PWM_SINGLECHAN_COMMON) + ---help--- + Enables channel 2 output. + +config STM32_TIM15_CHANNEL + int "TIM15 PWM Output Channel" + depends on (STM32_TIM15_PWM && !STM32_PWM_MULTICHAN) || (ARCH_CHIP_STM32H7 && STM32_TIM15_CAP) + default 1 + range 1 2 + ---help--- + If TIM15 is enabled for PWM usage, you also need specifies the timer output + channel {1,2} + +config STM32_TIM15_CH2NOUT + bool "TIM15 Channel 2 Complementary Output" + depends on STM32_TIM15_PWM && !STM32_PWM_MULTICHAN && STM32_TIM15_CHANNEL = 2 + depends on STM32_TIM_PWM_SINGLECHAN_COMMON + ---help--- + Enables channel 2 Complementary Output. + +config STM32_TIM15_CHMODE + int "TIM15 Channel Mode" + depends on STM32_TIM15_PWM && !STM32_PWM_MULTICHAN + default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + default 6 + range 0 9 if (STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2) || ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5 + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON + range 0 3 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM16_PWM + bool "TIM16 PWM" + depends on STM32_TIM16 + depends on (STM32_COMMON_LEGACY && STM32_TIM) || STM32_COMMON_F0_L0_G0_C0 || ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5 || STM32_COMMON_L5_U5 + select STM32_PWM if STM32_TIM_PWM_STM32PWM_COMMON + select PWM if ARCH_CHIP_STM32L5 + ---help--- + Reserve timer 16 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32_TIM16 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +config STM32_TIM16_LOCK + int "TIM16 Lock Level Configuration" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM16_PWM || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM16_PWM + default 0 + range 0 3 + ---help--- + Timer 16 lock level configuration + +config STM32_TIM16_TDTS + int "TIM16 t_DTS division" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM16_PWM || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM16_PWM + default 0 + range 0 2 + ---help--- + Timer 16 dead-time and sampling clock (t_DTS) division + +config STM32_TIM16_DEADTIME + int "TIM16 Initial Dead-time" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM16_PWM || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM16_PWM + default 0 + range 0 255 + ---help--- + Timer 16 initial dead-time + +config STM32_TIM16_CHANNEL1 + bool "TIM16 Channel 1" + depends on STM32_TIM16_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 1. + +config STM32_TIM16_CH1MODE + int "TIM16 Channel 1 Mode" + depends on STM32_TIM16_PWM && STM32_PWM_MULTICHAN && STM32_TIM16_CHANNEL1 + default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + default 6 + range 0 7 if STM32_TIM_PWM_CHMODE_TIM16_17_EXTENDED_COMMON + range 0 1 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM16_CH1OUT + bool "TIM16 Channel 1 Output" + depends on STM32_TIM16_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM16_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM16_CHANNEL = 1 && STM32_TIM_PWM_SINGLECHAN_COMMON) + ---help--- + Enables channel 1 output. + +config STM32_TIM16_CHANNEL + int "TIM16 PWM Output Channel" + depends on (STM32_TIM16_PWM && !STM32_PWM_MULTICHAN) || (ARCH_CHIP_STM32H7 && STM32_TIM16_CAP) + default 1 + range 1 1 + ---help--- + If TIM16 is enabled for PWM usage, you also need specifies the timer output + channel {1} + +config STM32_TIM16_CHMODE + int "TIM16 Channel Mode" + depends on STM32_TIM16_PWM && !STM32_PWM_MULTICHAN + default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + default 6 + range 0 7 if STM32_TIM_PWM_CHMODE_TIM16_17_EXTENDED_COMMON + range 0 1 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM17_PWM + bool "TIM17 PWM" + depends on STM32_TIM17 + depends on (STM32_COMMON_LEGACY && STM32_TIM) || STM32_COMMON_F0_L0_G0_C0 || ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5 || STM32_COMMON_L5_U5 + select STM32_PWM if STM32_TIM_PWM_STM32PWM_COMMON + select PWM if ARCH_CHIP_STM32L5 + ---help--- + Reserve timer 17 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32_TIM17 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +config STM32_TIM17_LOCK + int "TIM17 Lock Level Configuration" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM17_PWM || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM17_PWM + default 0 + range 0 3 + ---help--- + Timer 17 lock level configuration + +config STM32_TIM17_TDTS + int "TIM17 t_DTS Division" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM17_PWM || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM17_PWM + default 0 + range 0 2 + ---help--- + Timer 17 dead-time and sampling clock (t_DTS) division + +config STM32_TIM17_DEADTIME + int "TIM17 Initial Dead-time" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM17_PWM || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM17_PWM + default 0 + range 0 255 + ---help--- + Timer 17 initial dead-time + +config STM32_TIM17_CHANNEL1 + bool "TIM17 Channel 1" + depends on STM32_TIM17_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 1. + +config STM32_TIM17_CH1MODE + int "TIM17 Channel 1 Mode" + depends on STM32_TIM17_PWM && STM32_PWM_MULTICHAN && STM32_TIM17_CHANNEL1 + default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + default 6 + range 0 7 if STM32_TIM_PWM_CHMODE_TIM16_17_EXTENDED_COMMON + range 0 1 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM17_CH1OUT + bool "TIM17 Channel 1 Output" + depends on STM32_TIM17_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM17_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM17_CHANNEL = 1 && STM32_TIM_PWM_SINGLECHAN_COMMON) + ---help--- + Enables channel 1 output. + +config STM32_TIM17_CHANNEL + int "TIM17 PWM Output Channel" + depends on (STM32_TIM17_PWM && !STM32_PWM_MULTICHAN) || (ARCH_CHIP_STM32H7 && STM32_TIM17_CAP) + default 1 + range 1 1 + ---help--- + If TIM17 is enabled for PWM usage, you also need specifies the timer output + channel {1} + +config STM32_TIM17_CHMODE + int "TIM17 Channel Mode" + depends on STM32_TIM17_PWM && !STM32_PWM_MULTICHAN + default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + default 6 + range 0 7 if STM32_TIM_PWM_CHMODE_TIM16_17_EXTENDED_COMMON + range 0 1 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_PWM_MULTICHAN + bool "PWM Multiple Output Channels" + depends on STM32_PWM_MULTICHAN_CAPABLE + ---help--- + Specifies that the PWM driver supports multiple output + channels per timer. + +config STM32_PULSECOUNT + bool + depends on STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5 + select ARCH_HAVE_PULSECOUNT + select PULSECOUNT + +config STM32_TIM1_PULSECOUNT + bool "TIM1 pulse count" + depends on STM32_TIM1 + depends on STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5 + select STM32_PULSECOUNT + ---help--- + Reserve timer 1 for pulse count output. + +if STM32_TIM1_PULSECOUNT + +config STM32_TIM1_PULSECOUNT_TDTS + int "TIM1 pulse count clock division" + default 0 + range 0 2 + depends on !STM32_COMMON_F0_L0_G0_C0 + +config STM32_TIM1_PULSECOUNT_CHANNEL + int "TIM1 pulse count channel" + default 1 + range 1 4 + ---help--- + Specifies the timer channel {1,..,4}. + +config STM32_TIM1_PULSECOUNT_POL + int "TIM1 pulse count output polarity" + default 0 + range 0 1 + depends on !STM32_COMMON_F0_L0_G0_C0 + +config STM32_TIM1_PULSECOUNT_IDLE + int "TIM1 pulse count idle state" + default 0 + range 0 1 + depends on !STM32_COMMON_F0_L0_G0_C0 + +endif # STM32_TIM1_PULSECOUNT + +config STM32_TIM8_PULSECOUNT + bool "TIM8 pulse count" + depends on STM32_TIM8 + depends on STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5 + select STM32_PULSECOUNT + ---help--- + Reserve timer 8 for pulse count output. + +if STM32_TIM8_PULSECOUNT + +config STM32_TIM8_PULSECOUNT_TDTS + int "TIM8 pulse count clock division" + default 0 + range 0 2 + +config STM32_TIM8_PULSECOUNT_CHANNEL + int "TIM8 pulse count channel" + default 1 + range 1 4 + ---help--- + Specifies the timer channel {1,..,4}. + +config STM32_TIM8_PULSECOUNT_POL + int "TIM8 pulse count output polarity" + default 0 + range 0 1 + +config STM32_TIM8_PULSECOUNT_IDLE + int "TIM8 pulse count idle state" + default 0 + range 0 1 + +endif # STM32_TIM8_PULSECOUNT + +config STM32_PWM_TRGO + bool "TIM PWM TRGO support" + depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_PWM) || (ARCH_CHIP_STM32F7 && STM32_PWM) + ---help--- + Enable TRGO support for PWM driver + +config STM32_TIM1_ADC + bool "TIM1 ADC" + depends on ((STM32_COMMON_LEGACY && STM32_TIM) || STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_F7_H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_ADC && STM32_TIM1 + ---help--- + Reserve timer 1 for use by ADC + + Timer devices may be used for different purposes. If STM32_TIM1 is + defined then the following may also be defined to indicate that the + timer is intended to be used for ADC conversion. Note that ADC usage + requires two definition: Not only do you have to assign the timer + for used by the ADC, but then you also have to configure which ADC + channel it is assigned to. + +config STM32_TIM2_ADC + bool "TIM2 ADC" + depends on ((STM32_COMMON_LEGACY && STM32_TIM) || STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_F7_H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_ADC && STM32_TIM2 + ---help--- + Reserve timer 1 for use by ADC + + Timer devices may be used for different purposes. If STM32_TIM2 is + defined then the following may also be defined to indicate that the + timer is intended to be used for ADC conversion. Note that ADC usage + requires two definition: Not only do you have to assign the timer + for used by the ADC, but then you also have to configure which ADC + channel it is assigned to. + +config STM32_TIM3_ADC + bool "TIM3 ADC" + depends on ((STM32_COMMON_LEGACY && STM32_TIM) || STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_F7_H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_ADC && STM32_TIM3 + ---help--- + Reserve timer 1 for use by ADC + + Timer devices may be used for different purposes. If STM32_TIM3 is + defined then the following may also be defined to indicate that the + timer is intended to be used for ADC conversion. Note that ADC usage + requires two definition: Not only do you have to assign the timer + for used by the ADC, but then you also have to configure which ADC + channel it is assigned to. + +config STM32_TIM4_ADC + bool "TIM4 ADC" + depends on ((STM32_COMMON_LEGACY && STM32_TIM) || STM32_COMMON_F7_H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_ADC && STM32_TIM4 + ---help--- + Reserve timer 1 for use by ADC + + Timer devices may be used for different purposes. If STM32_TIM4 is + defined then the following may also be defined to indicate that the + timer is intended to be used for ADC conversion. Note that ADC usage + requires two definition: Not only do you have to assign the timer + for used by the ADC, but then you also have to configure which ADC + channel it is assigned to. + +config STM32_TIM5_ADC + bool "TIM5 ADC" + depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM5 && STM32_ADC) || (ARCH_CHIP_STM32F7 && STM32_TIM5 && STM32_ADC) + ---help--- + Reserve timer 1 for use by ADC + + Timer devices may be used for different purposes. If STM32_TIM5 is + defined then the following may also be defined to indicate that the + timer is intended to be used for ADC conversion. Note that ADC usage + requires two definition: Not only do you have to assign the timer + for used by the ADC, but then you also have to configure which ADC + channel it is assigned to. + +config STM32_TIM8_ADC + bool "TIM8 ADC" + depends on ((STM32_COMMON_LEGACY && STM32_TIM) || STM32_COMMON_F7_H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_ADC && STM32_TIM8 + ---help--- + Reserve timer 1 for use by ADC + + Timer devices may be used for different purposes. If STM32_TIM8 is + defined then the following may also be defined to indicate that the + timer is intended to be used for ADC conversion. Note that ADC usage + requires two definition: Not only do you have to assign the timer + for used by the ADC, but then you also have to configure which ADC + channel it is assigned to. + +config STM32_HAVE_ADC1_TIMER + bool + +config STM32_HAVE_ADC2_TIMER + bool + +config STM32_HAVE_ADC3_TIMER + bool + +config STM32_ADC1_SAMPLE_FREQUENCY + int "ADC1 Sampling Frequency" + depends on STM32_ADC1_TIMER_FREQ_CAPABLE + default 100 + ---help--- + ADC1 sampling frequency. Default: 100Hz + +config STM32_ADC1_TIMTRIG + int "ADC1 Timer Trigger" + depends on STM32_ADC1_TIMTRIG_CAPABLE + default 0 + range 0 5 if STM32_ADC_TIMTRIG_TRGO2_COMMON + range 0 4 if STM32_ADC_TIMTRIG_TRGO_COMMON + ---help--- + Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO 5:TRGO2 + +config STM32_ADC2_SAMPLE_FREQUENCY + int "ADC2 Sampling Frequency" + depends on STM32_ADC2_TIMER_FREQ_CAPABLE + default 100 + ---help--- + ADC2 sampling frequency. Default: 100Hz + +config STM32_ADC2_TIMTRIG + int "ADC2 Timer Trigger" + depends on STM32_ADC2_TIMTRIG_CAPABLE + default 0 + range 0 5 if STM32_ADC_TIMTRIG_TRGO2_COMMON + range 0 4 if STM32_ADC_TIMTRIG_TRGO_COMMON + ---help--- + Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO 5:TRGO2 + +config STM32_ADC3_SAMPLE_FREQUENCY + int "ADC3 Sampling Frequency" + depends on STM32_ADC3_TIMER_CAPABLE + default 100 + ---help--- + ADC3 sampling frequency. Default: 100Hz + +config STM32_ADC3_TIMTRIG + int "ADC3 Timer Trigger" + depends on STM32_ADC3_TIMER_CAPABLE && !ARCH_CHIP_STM32L4 + default 0 + range 0 5 if STM32_ADC_TIMTRIG_TRGO2_COMMON + range 0 4 if STM32_ADC_TIMTRIG_TRGO_COMMON + ---help--- + Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO 5:TRGO2 + +config STM32_TIM1_DAC + bool "TIM1 DAC" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1 && STM32_DAC || (ARCH_CHIP_STM32F7 || STM32_COMMON_L4_L5_U5) && STM32_TIM1 && STM32_DAC + ---help--- + Reserve timer 1 for use by DAC + + Timer devices may be used for different purposes. If STM32_TIM1 is + defined then the following may also be defined to indicate that the + timer is intended to be used for DAC conversion. Note that DAC usage + requires two definition: Not only do you have to assign the timer + for used by the DAC, but then you also have to configure which DAC + channel it is assigned to. + +config STM32_TIM2_DAC + bool "TIM2 DAC" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM2 && STM32_DAC || (ARCH_CHIP_STM32F7 || STM32_COMMON_L4_L5_U5) && STM32_TIM2 && STM32_DAC + ---help--- + Reserve timer 2 for use by DAC + + Timer devices may be used for different purposes. If STM32_TIM2 is + defined then the following may also be defined to indicate that the + timer is intended to be used for DAC conversion. Note that DAC usage + requires two definition: Not only do you have to assign the timer + for used by the DAC, but then you also have to configure which DAC + channel it is assigned to. + +config STM32_TIM3_DAC + bool "TIM3 DAC" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM3 && STM32_DAC || (ARCH_CHIP_STM32F7 || STM32_COMMON_L4_L5_U5) && STM32_TIM3 && STM32_DAC + ---help--- + Reserve timer 3 for use by DAC + + Timer devices may be used for different purposes. If STM32_TIM3 is + defined then the following may also be defined to indicate that the + timer is intended to be used for DAC conversion. Note that DAC usage + requires two definition: Not only do you have to assign the timer + for used by the DAC, but then you also have to configure which DAC + channel it is assigned to. + +config STM32_TIM4_DAC + bool "TIM4 DAC" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM4 && STM32_DAC || (ARCH_CHIP_STM32F7 || STM32_COMMON_L4_L5_U5) && STM32_TIM4 && STM32_DAC + ---help--- + Reserve timer 4 for use by DAC + + Timer devices may be used for different purposes. If STM32_TIM4 is + defined then the following may also be defined to indicate that the + timer is intended to be used for DAC conversion. Note that DAC usage + requires two definition: Not only do you have to assign the timer + for used by the DAC, but then you also have to configure which DAC + channel it is assigned to. + +config STM32_TIM5_DAC + bool "TIM5 DAC" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM5 && STM32_DAC || (ARCH_CHIP_STM32F7 || STM32_COMMON_L4_L5_U5) && STM32_TIM5 && STM32_DAC + ---help--- + Reserve timer 5 for use by DAC + + Timer devices may be used for different purposes. If STM32_TIM5 is + defined then the following may also be defined to indicate that the + timer is intended to be used for DAC conversion. Note that DAC usage + requires two definition: Not only do you have to assign the timer + for used by the DAC, but then you also have to configure which DAC + channel it is assigned to. + +config STM32_TIM6_DAC + bool "TIM6 DAC" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM6 && STM32_DAC || (ARCH_CHIP_STM32F7 || STM32_COMMON_L4_L5_U5) && STM32_TIM6 && STM32_DAC + ---help--- + Reserve timer 6 for use by DAC + + Timer devices may be used for different purposes. If STM32_TIM6 is + defined then the following may also be defined to indicate that the + timer is intended to be used for DAC conversion. Note that DAC usage + requires two definition: Not only do you have to assign the timer + for used by the DAC, but then you also have to configure which DAC + channel it is assigned to. + +config STM32_TIM7_DAC + bool "TIM7 DAC" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM7 && STM32_DAC || (ARCH_CHIP_STM32F7 || STM32_COMMON_L4_L5_U5) && STM32_TIM7 && STM32_DAC + ---help--- + Reserve timer 7 for use by DAC + + Timer devices may be used for different purposes. If STM32_TIM7 is + defined then the following may also be defined to indicate that the + timer is intended to be used for DAC conversion. Note that DAC usage + requires two definition: Not only do you have to assign the timer + for used by the DAC, but then you also have to configure which DAC + channel it is assigned to. + +config STM32_TIM8_DAC + bool "TIM8 DAC" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8 && STM32_DAC || (ARCH_CHIP_STM32F7 || STM32_COMMON_L4_L5_U5) && STM32_TIM8 && STM32_DAC + ---help--- + Reserve timer 8 for use by DAC + + Timer devices may be used for different purposes. If STM32_TIM8 is + defined then the following may also be defined to indicate that the + timer is intended to be used for DAC conversion. Note that DAC usage + requires two definition: Not only do you have to assign the timer + for used by the DAC, but then you also have to configure which DAC + channel it is assigned to. + +config STM32_TIM9_DAC + bool "TIM9 DAC" + depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM9 && STM32_DAC) || (ARCH_CHIP_STM32F7 && STM32_TIM9 && STM32_DAC) + ---help--- + Reserve timer 9 for use by DAC + + Timer devices may be used for different purposes. If STM32_TIM9 is + defined then the following may also be defined to indicate that the + timer is intended to be used for DAC conversion. Note that DAC usage + requires two definition: Not only do you have to assign the timer + for used by the DAC, but then you also have to configure which DAC + channel it is assigned to. + +config STM32_TIM10_DAC + bool "TIM10 DAC" + depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM10 && STM32_DAC) || (ARCH_CHIP_STM32F7 && STM32_TIM10 && STM32_DAC) + ---help--- + Reserve timer 10 for use by DAC + + Timer devices may be used for different purposes. If STM32_TIM10 is + defined then the following may also be defined to indicate that the + timer is intended to be used for DAC conversion. Note that DAC usage + requires two definition: Not only do you have to assign the timer + for used by the DAC, but then you also have to configure which DAC + channel it is assigned to. + +config STM32_TIM11_DAC + bool "TIM11 DAC" + depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM11 && STM32_DAC) || (ARCH_CHIP_STM32F7 && STM32_TIM11 && STM32_DAC) + ---help--- + Reserve timer 11 for use by DAC + + Timer devices may be used for different purposes. If STM32_TIM11 is + defined then the following may also be defined to indicate that the + timer is intended to be used for DAC conversion. Note that DAC usage + requires two definition: Not only do you have to assign the timer + for used by the DAC, but then you also have to configure which DAC + channel it is assigned to. + +config STM32_TIM12_DAC + bool "TIM12 DAC" + depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM12 && STM32_DAC) || (ARCH_CHIP_STM32F7 && STM32_TIM12 && STM32_DAC) + ---help--- + Reserve timer 12 for use by DAC + + Timer devices may be used for different purposes. If STM32_TIM12 is + defined then the following may also be defined to indicate that the + timer is intended to be used for DAC conversion. Note that DAC usage + requires two definition: Not only do you have to assign the timer + for used by the DAC, but then you also have to configure which DAC + channel it is assigned to. + +config STM32_TIM13_DAC + bool "TIM13 DAC" + depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM13 && STM32_DAC) || (ARCH_CHIP_STM32F7 && STM32_TIM13 && STM32_DAC) + ---help--- + Reserve timer 13 for use by DAC + + Timer devices may be used for different purposes. If STM32_TIM13 is + defined then the following may also be defined to indicate that the + timer is intended to be used for DAC conversion. Note that DAC usage + requires two definition: Not only do you have to assign the timer + for used by the DAC, but then you also have to configure which DAC + channel it is assigned to. + +config STM32_TIM14_DAC + bool "TIM14 DAC" + depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM14 && STM32_DAC) || (ARCH_CHIP_STM32F7 && STM32_TIM14 && STM32_DAC) + ---help--- + Reserve timer 14 for use by DAC + + Timer devices may be used for different purposes. If STM32_TIM14 is + defined then the following may also be defined to indicate that the + timer is intended to be used for DAC conversion. Note that DAC usage + requires two definition: Not only do you have to assign the timer + for used by the DAC, but then you also have to configure which DAC + channel it is assigned to. + +config STM32_TIM1_CAP + bool "TIM1 Capture" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1 || (STM32_COMMON_F7_H7_H5) && STM32_TIM1 || STM32_COMMON_L4_L5_U5 && STM32_HAVE_TIM1 + select STM32_CAP if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1 + select STM32_TIMX_CAP if ARCH_CHIP_STM32H7 && STM32_TIM1 + ---help--- + Reserve timer 1 for use by Capture + + Timer devices may be used for different purposes. One special purpose is + to capture input. + +config STM32_TIM1_CLOCK + int "TIM1 work frequency for capture" + depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1_CAP) || (ARCH_CHIP_STM32H7 && STM32_TIM1_CAP) + default 1000000 if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1_CAP + default 100000 if ARCH_CHIP_STM32H7 && STM32_TIM1_CAP + ---help--- + This clock frequency limiting the count rate at the expense of resolution. + +config STM32_TIM2_CAP + bool "TIM2 Capture" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM2 || (STM32_COMMON_F7_H7_H5) && STM32_TIM2 || STM32_COMMON_L4_L5_U5 && STM32_HAVE_TIM2 + select STM32_CAP if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM2 + select STM32_TIMX_CAP if ARCH_CHIP_STM32H7 && STM32_TIM2 + ---help--- + Reserve timer 2 for use by Capture + + Timer devices may be used for different purposes. One special purpose is + to capture input. + +config STM32_TIM2_CLOCK + int "TIM2 work frequency for capture" + depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM2_CAP) || (ARCH_CHIP_STM32H7 && STM32_TIM2_CAP) + default 1000000 if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM2_CAP + default 100000 if ARCH_CHIP_STM32H7 && STM32_TIM2_CAP + ---help--- + This clock frequency limiting the count rate at the expense of resolution. + +config STM32_TIM3_CAP + bool "TIM3 Capture" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM3 || (STM32_COMMON_F7_H7_H5) && STM32_TIM3 || STM32_COMMON_L4_L5_U5 && STM32_HAVE_TIM3 + select STM32_CAP if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM3 + select STM32_TIMX_CAP if ARCH_CHIP_STM32H7 && STM32_TIM3 + ---help--- + Reserve timer 3 for use by Capture + + Timer devices may be used for different purposes. One special purpose is + to capture input. + +config STM32_TIM3_CLOCK + int "TIM3 work frequency for capture" + depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM3_CAP) || (ARCH_CHIP_STM32H7 && STM32_TIM3_CAP) + default 1000000 if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM3_CAP + default 100000 if ARCH_CHIP_STM32H7 && STM32_TIM3_CAP + ---help--- + This clock frequency limiting the count rate at the expense of resolution. + +config STM32_TIM4_CAP + bool "TIM4 Capture" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM4 || (STM32_COMMON_F7_H7_H5) && STM32_TIM4 || STM32_COMMON_L4_L5_U5 && STM32_HAVE_TIM4 + select STM32_CAP if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM4 + select STM32_TIMX_CAP if ARCH_CHIP_STM32H7 && STM32_TIM4 + ---help--- + Reserve timer 4 for use by Capture + + Timer devices may be used for different purposes. One special purpose is + to capture input. + +config STM32_TIM4_CLOCK + int "TIM4 work frequency for capture" + depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM4_CAP) || (ARCH_CHIP_STM32H7 && STM32_TIM4_CAP) + default 1000000 if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM4_CAP + default 100000 if ARCH_CHIP_STM32H7 && STM32_TIM4_CAP + ---help--- + This clock frequency limiting the count rate at the expense of resolution. + +config STM32_TIM5_CAP + bool "TIM5 Capture" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM5 || (STM32_COMMON_F7_H7_H5) && STM32_TIM5 || STM32_COMMON_L4_L5_U5 && STM32_HAVE_TIM5 + select STM32_CAP if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM5 + select STM32_TIMX_CAP if ARCH_CHIP_STM32H7 && STM32_TIM5 + ---help--- + Reserve timer 5 for use by Capture + + Timer devices may be used for different purposes. One special purpose is + to capture input. + +config STM32_TIM5_CLOCK + int "TIM5 work frequency for capture" + depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM5_CAP) || (ARCH_CHIP_STM32H7 && STM32_TIM5_CAP) + default 1000000 if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM5_CAP + default 100000 if ARCH_CHIP_STM32H7 && STM32_TIM5_CAP + ---help--- + This clock frequency limiting the count rate at the expense of resolution. + +config STM32_TIM8_CAP + bool "TIM8 Capture" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8 || (STM32_COMMON_F7_H7_H5) && STM32_TIM8 || STM32_COMMON_L4_L5_U5 && STM32_HAVE_TIM8 + select STM32_CAP if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8 + select STM32_TIMX_CAP if ARCH_CHIP_STM32H7 && STM32_TIM8 + ---help--- + Reserve timer 8 for use by Capture + + Timer devices may be used for different purposes. One special purpose is + to capture input. + +config STM32_TIM8_CLOCK + int "TIM8 work frequency for capture" + depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8_CAP) || (ARCH_CHIP_STM32H7 && STM32_TIM8_CAP) + default 1000000 if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8_CAP + default 100000 if ARCH_CHIP_STM32H7 && STM32_TIM8_CAP + ---help--- + This clock frequency limiting the count rate at the expense of resolution. + +config STM32_TIM9_CAP + bool "TIM9 Capture" + depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM9) || (ARCH_CHIP_STM32F7 && STM32_TIM9) + select STM32_CAP if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM9 + ---help--- + Reserve timer 9 for use by Capture + + Timer devices may be used for different purposes. One special purpose is + to capture input. + +config STM32_TIM10_CAP + bool "TIM10 Capture" + depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM10) || (ARCH_CHIP_STM32F7 && STM32_TIM10) + select STM32_CAP if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM10 + ---help--- + Reserve timer 10 for use by Capture + + Timer devices may be used for different purposes. One special purpose is + to capture input. + +config STM32_TIM11_CAP + bool "TIM11 Capture" + depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM11) || (ARCH_CHIP_STM32F7 && STM32_TIM11) + select STM32_CAP if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM11 + ---help--- + Reserve timer 11 for use by Capture + + Timer devices may be used for different purposes. One special purpose is + to capture input. + +config STM32_TIM12_CAP + bool "TIM12 Capture" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM12 || (STM32_COMMON_F7_H7_H5) && STM32_TIM12 + select STM32_CAP if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM12 + select STM32_TIMX_CAP if ARCH_CHIP_STM32H7 && STM32_TIM12 + ---help--- + Reserve timer 12 for use by Capture + + Timer devices may be used for different purposes. One special purpose is + to capture input. + +config STM32_TIM12_CLOCK + int "TIM12 work frequency for capture" + depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM12_CAP) || (ARCH_CHIP_STM32H7 && STM32_TIM12_CAP) + default 1000000 if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM12_CAP + default 100000 if ARCH_CHIP_STM32H7 && STM32_TIM12_CAP + ---help--- + This clock frequency limiting the count rate at the expense of resolution. + +config STM32_TIM13_CAP + bool "TIM13 Capture" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM13 || (STM32_COMMON_F7_H7_H5) && STM32_TIM13 + select STM32_CAP if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM13 + select STM32_TIMX_CAP if ARCH_CHIP_STM32H7 && STM32_TIM13 + ---help--- + Reserve timer 13 for use by Capture + + Timer devices may be used for different purposes. One special purpose is + to capture input. + +config STM32_TIM13_CLOCK + int "TIM13 work frequency for capture" + depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM13_CAP) || (ARCH_CHIP_STM32H7 && STM32_TIM13_CAP) + default 1000000 if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM13_CAP + default 100000 if ARCH_CHIP_STM32H7 && STM32_TIM13_CAP + ---help--- + This clock frequency limiting the count rate at the expense of resolution. + +config STM32_TIM14_CAP + bool "TIM14 Capture" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM14 || (STM32_COMMON_F7_H7_H5) && STM32_TIM14 + select STM32_CAP if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM14 + select STM32_TIMX_CAP if ARCH_CHIP_STM32H7 && STM32_TIM14 + ---help--- + Reserve timer 14 for use by Capture + + Timer devices may be used for different purposes. One special purpose is + to capture input. + +config STM32_TIM14_CLOCK + int "TIM14 work frequency for capture" + depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM14_CAP) || (ARCH_CHIP_STM32H7 && STM32_TIM14_CAP) + default 1000000 if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM14_CAP + default 100000 if ARCH_CHIP_STM32H7 && STM32_TIM14_CAP + ---help--- + This clock frequency limiting the count rate at the expense of resolution. + +config STM32_TIM1_CH1POL + int "TIM1 Channel 1 Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH1OUT + default 0 + range 0 1 + ---help--- + TIM1 Channel 1 output polarity + +config STM32_TIM1_CH1IDLE + int "TIM1 Channel 1 Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH1OUT + default 0 + range 0 1 + ---help--- + TIM1 Channel 1 output IDLE + +config STM32_TIM1_CH1NPOL + int "TIM1 Channel 1 Complementary Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1_CH1NOUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH1NOUT + default 0 + range 0 1 + ---help--- + TIM1 Channel 1 Complementary Output polarity + +config STM32_TIM1_CH1NIDLE + int "TIM1 Channel 1 Complementary Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1_CH1NOUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH1NOUT + default 0 + range 0 1 + ---help--- + TIM1 Channel 1 Complementary Output IDLE + +config STM32_TIM1_CH2POL + int "TIM1 Channel 2 Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH2OUT + default 0 + range 0 1 + ---help--- + TIM1 Channel 2 output polarity + +config STM32_TIM1_CH2IDLE + int "TIM1 Channel 2 Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH2OUT + default 0 + range 0 1 + ---help--- + TIM1 Channel 2 output IDLE + +config STM32_TIM1_CH2NPOL + int "TIM1 Channel 2 Complementary Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1_CH2NOUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH2NOUT + default 0 + range 0 1 + ---help--- + TIM1 Channel 2 Complementary Output polarity + +config STM32_TIM1_CH2NIDLE + int "TIM1 Channel 2 Complementary Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1_CH2NOUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH2NOUT + default 0 + range 0 1 + ---help--- + TIM1 Channel 2 Complementary Output IDLE + +config STM32_TIM1_CH3POL + int "TIM1 Channel 3 Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1_CH3OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH3OUT + default 0 + range 0 1 + ---help--- + TIM1 Channel 3 output polarity + +config STM32_TIM1_CH3IDLE + int "TIM1 Channel 3 Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1_CH3OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH3OUT + default 0 + range 0 1 + ---help--- + TIM1 Channel 3 output IDLE + +config STM32_TIM1_CH3NPOL + int "TIM1 Channel 3 Complementary Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1_CH3NOUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH3NOUT + default 0 + range 0 1 + ---help--- + TIM1 Channel 3 Complementary Output polarity + +config STM32_TIM1_CH3NIDLE + int "TIM1 Channel 3 Complementary Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1_CH3NOUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH3NOUT + default 0 + range 0 1 + ---help--- + TIM1 Channel 3 Complementary Output IDLE + +config STM32_TIM1_CH4POL + int "TIM1 Channel 4 Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1_CH4OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH4OUT + default 0 + range 0 1 + ---help--- + TIM1 Channel 4 output polarity + +config STM32_TIM1_CH4IDLE + int "TIM1 Channel 4 Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1_CH4OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH4OUT + default 0 + range 0 1 + ---help--- + TIM1 Channel 4 output IDLE + +config STM32_TIM1_CH5POL + int "TIM1 Channel 5 Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1_CH5OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH5OUT + default 0 + range 0 1 + ---help--- + TIM1 Channel 5 output polarity + +config STM32_TIM1_CH5IDLE + int "TIM1 Channel 5 Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1_CH5OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH5OUT + default 0 + range 0 1 + ---help--- + TIM1 Channel 5 output IDLE + +config STM32_TIM1_CH6POL + int "TIM1 Channel 6 Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1_CH6OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH6OUT + default 0 + range 0 1 + ---help--- + TIM1 Channel 6 output polarity + +config STM32_TIM1_CH6IDLE + int "TIM1 Channel 6 Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1_CH6OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH6OUT + default 0 + range 0 1 + ---help--- + TIM1 Channel 6 output IDLE + +config STM32_TIM2_CH1POL + int "TIM2 Channel 1 Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM2_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM2_CH1OUT + default 0 + range 0 1 + ---help--- + TIM2 Channel 1 output polarity + +config STM32_TIM2_CH1IDLE + int "TIM2 Channel 1 Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM2_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM2_CH1OUT + default 0 + range 0 1 + ---help--- + TIM2 Channel 1 output IDLE + +config STM32_TIM2_CH2POL + int "TIM2 Channel 2 Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM2_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM2_CH2OUT + default 0 + range 0 1 + ---help--- + TIM2 Channel 2 output polarity + +config STM32_TIM2_CH2IDLE + int "TIM2 Channel 2 Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM2_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM2_CH2OUT + default 0 + range 0 1 + ---help--- + TIM2 Channel 2 output IDLE + +config STM32_TIM2_CH3POL + int "TIM2 Channel 3 Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM2_CH3OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM2_CH3OUT + default 0 + range 0 1 + ---help--- + TIM2 Channel 3 output polarity + +config STM32_TIM2_CH3IDLE + int "TIM2 Channel 3 Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM2_CH3OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM2_CH3OUT + default 0 + range 0 1 + ---help--- + TIM2 Channel 3 output IDLE + +config STM32_TIM2_CH4POL + int "TIM2 Channel 4 Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM2_CH4OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM2_CH4OUT + default 0 + range 0 1 + ---help--- + TIM2 Channel 4 output polarity + +config STM32_TIM2_CH4IDLE + int "TIM2 Channel 4 Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM2_CH4OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM2_CH4OUT + default 0 + range 0 1 + ---help--- + TIM2 Channel 4 output IDLE + +config STM32_TIM3_CH1POL + int "TIM3 Channel 1 Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM3_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM3_CH1OUT + default 0 + range 0 1 + ---help--- + TIM3 Channel 1 output polarity + +config STM32_TIM3_CH1IDLE + int "TIM3 Channel 1 Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM3_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM3_CH1OUT + default 0 + range 0 1 + ---help--- + TIM3 Channel 1 output IDLE + +config STM32_TIM3_CH2POL + int "TIM3 Channel 2 Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM3_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM3_CH2OUT + default 0 + range 0 1 + ---help--- + TIM3 Channel 2 output polarity + +config STM32_TIM3_CH2IDLE + int "TIM3 Channel 2 Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM3_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM3_CH2OUT + default 0 + range 0 1 + ---help--- + TIM3 Channel 2 output IDLE + +config STM32_TIM3_CH3POL + int "TIM3 Channel 3 Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM3_CH3OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM3_CH3OUT + default 0 + range 0 1 + ---help--- + TIM3 Channel 3 output polarity + +config STM32_TIM3_CH3IDLE + int "TIM3 Channel 3 Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM3_CH3OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM3_CH3OUT + default 0 + range 0 1 + ---help--- + TIM3 Channel 3 output IDLE + +config STM32_TIM3_CH4POL + int "TIM3 Channel 4 Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM3_CH4OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM3_CH4OUT + default 0 + range 0 1 + ---help--- + TIM3 Channel 4 output polarity + +config STM32_TIM3_CH4IDLE + int "TIM3 Channel 4 Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM3_CH4OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM3_CH4OUT + default 0 + range 0 1 + ---help--- + TIM3 Channel 4 output IDLE + +config STM32_TIM4_CH1POL + int "TIM4 Channel 1 Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM4_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM4_CH1OUT + default 0 + range 0 1 + ---help--- + TIM4 Channel 1 output polarity + +config STM32_TIM4_CH1IDLE + int "TIM4 Channel 1 Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM4_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM4_CH1OUT + default 0 + range 0 1 + ---help--- + TIM4 Channel 1 output IDLE + +config STM32_TIM4_CH2POL + int "TIM4 Channel 2 Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM4_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM4_CH2OUT + default 0 + range 0 1 + ---help--- + TIM4 Channel 2 output polarity + +config STM32_TIM4_CH2IDLE + int "TIM4 Channel 2 Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM4_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM4_CH2OUT + default 0 + range 0 1 + ---help--- + TIM4 Channel 2 output IDLE + +config STM32_TIM4_CH3POL + int "TIM4 Channel 3 Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM4_CH3OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM4_CH3OUT + default 0 + range 0 1 + ---help--- + TIM4 Channel 3 output polarity + +config STM32_TIM4_CH3IDLE + int "TIM4 Channel 3 Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM4_CH3OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM4_CH3OUT + default 0 + range 0 1 + ---help--- + TIM4 Channel 3 output IDLE + +config STM32_TIM4_CH4POL + int "TIM4 Channel 4 Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM4_CH4OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM4_CH4OUT + default 0 + range 0 1 + ---help--- + TIM4 Channel 4 output polarity + +config STM32_TIM4_CH4IDLE + int "TIM4 Channel 4 Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM4_CH4OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM4_CH4OUT + default 0 + range 0 1 + ---help--- + TIM4 Channel 4 output IDLE + +config STM32_TIM5_CH1POL + int "TIM5 Channel 1 Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM5_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM5_CH1OUT + default 0 + range 0 1 + ---help--- + TIM5 Channel 1 output polarity + +config STM32_TIM5_CH1IDLE + int "TIM5 Channel 1 Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM5_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM5_CH1OUT + default 0 + range 0 1 + ---help--- + TIM5 Channel 1 output IDLE + +config STM32_TIM5_CH2POL + int "TIM5 Channel 2 Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM5_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM5_CH2OUT + default 0 + range 0 1 + ---help--- + TIM5 Channel 2 output polarity + +config STM32_TIM5_CH2IDLE + int "TIM5 Channel 2 Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM5_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM5_CH2OUT + default 0 + range 0 1 + ---help--- + TIM5 Channel 2 output IDLE + +config STM32_TIM5_CH3POL + int "TIM5 Channel 3 Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM5_CH3OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM5_CH3OUT + default 0 + range 0 1 + ---help--- + TIM5 Channel 3 output polarity + +config STM32_TIM5_CH3IDLE + int "TIM5 Channel 3 Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM5_CH3OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM5_CH3OUT + default 0 + range 0 1 + ---help--- + TIM5 Channel 3 output IDLE + +config STM32_TIM5_CH4POL + int "TIM5 Channel 4 Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM5_CH4OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM5_CH4OUT + default 0 + range 0 1 + ---help--- + TIM5 Channel 4 output polarity + +config STM32_TIM5_CH4IDLE + int "TIM5 Channel 4 Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM5_CH4OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM5_CH4OUT + default 0 + range 0 1 + ---help--- + TIM5 Channel 4 output IDLE + +config STM32_TIM8_CH1POL + int "TIM8 Channel 1 Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH1OUT + default 0 + range 0 1 + ---help--- + TIM8 Channel 1 output polarity + +config STM32_TIM8_CH1IDLE + int "TIM8 Channel 1 Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH1OUT + default 0 + range 0 1 + ---help--- + TIM8 Channel 1 output IDLE + +config STM32_TIM8_CH1NPOL + int "TIM8 Channel 1 Complementary Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8_CH1NOUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH1NOUT + default 0 + range 0 1 + ---help--- + TIM8 Channel 1 Complementary Output polarity + +config STM32_TIM8_CH1NIDLE + int "TIM8 Channel 1 Complementary Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8_CH1NOUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH1NOUT + default 0 + range 0 1 + ---help--- + TIM8 Channel 1 Complementary Output IDLE + +config STM32_TIM8_CH2POL + int "TIM8 Channel 2 Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH2OUT + default 0 + range 0 1 + ---help--- + TIM8 Channel 2 output polarity + +config STM32_TIM8_CH2IDLE + int "TIM8 Channel 2 Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH2OUT + default 0 + range 0 1 + ---help--- + TIM8 Channel 2 output IDLE + +config STM32_TIM8_CH2NPOL + int "TIM8 Channel 2 Complementary Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8_CH2NOUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH2NOUT + default 0 + range 0 1 + ---help--- + TIM8 Channel 2 Complementary Output polarity + +config STM32_TIM8_CH2NIDLE + int "TIM8 Channel 2 Complementary Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8_CH2NOUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH2NOUT + default 0 + range 0 1 + ---help--- + TIM8 Channel 2 Complementary Output IDLE + +config STM32_TIM8_CH3POL + int "TIM8 Channel 3 Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8_CH3OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH3OUT + default 0 + range 0 1 + ---help--- + TIM8 Channel 3 output polarity + +config STM32_TIM8_CH3IDLE + int "TIM8 Channel 3 Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8_CH3OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH3OUT + default 0 + range 0 1 + ---help--- + TIM8 Channel 3 output IDLE + +config STM32_TIM8_CH3NPOL + int "TIM8 Channel 3 Complementary Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8_CH3NOUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH3NOUT + default 0 + range 0 1 + ---help--- + TIM8 Channel 3 Complementary Output polarity + +config STM32_TIM8_CH3NIDLE + int "TIM8 Channel 3 Complementary Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8_CH3NOUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH3NOUT + default 0 + range 0 1 + ---help--- + TIM8 Channel 3 Complementary Output IDLE + +config STM32_TIM8_CH4POL + int "TIM8 Channel 4 Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8_CH4OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH4OUT + default 0 + range 0 1 + ---help--- + TIM8 Channel 4 output polarity + +config STM32_TIM8_CH4IDLE + int "TIM8 Channel 4 Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8_CH4OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH4OUT + default 0 + range 0 1 + ---help--- + TIM8 Channel 4 output IDLE + +config STM32_TIM8_CH5POL + int "TIM8 Channel 5 Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8_CH5OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH5OUT + default 0 + range 0 1 + ---help--- + TIM8 Channel 5 output polarity + +config STM32_TIM8_CH5IDLE + int "TIM8 Channel 5 Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8_CH5OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH5OUT + default 0 + range 0 1 + ---help--- + TIM8 Channel 5 output IDLE + +config STM32_TIM8_CH6POL + int "TIM8 Channel 6 Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8_CH6OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH6OUT + default 0 + range 0 1 + ---help--- + TIM8 Channel 6 output polarity + +config STM32_TIM8_CH6IDLE + int "TIM8 Channel 6 Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8_CH6OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH6OUT + default 0 + range 0 1 + ---help--- + TIM8 Channel 6 output IDLE + +config STM32_TIM9_CH1POL + int "TIM9 Channel 1 Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM9_CH1OUT || (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_TIM9_CH1OUT + default 0 + range 0 1 + ---help--- + TIM9 Channel 1 output polarity + +config STM32_TIM9_CH1IDLE + int "TIM9 Channel 1 Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM9_CH1OUT || (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_TIM9_CH1OUT + default 0 + range 0 1 + ---help--- + TIM9 Channel 1 output IDLE + +config STM32_TIM9_CH2POL + int "TIM9 Channel 2 Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM9_CH2OUT || (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_TIM9_CH2OUT + default 0 + range 0 1 + ---help--- + TIM9 Channel 2 output polarity + +config STM32_TIM9_CH2IDLE + int "TIM9 Channel 2 Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM9_CH2OUT || (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_TIM9_CH2OUT + default 0 + range 0 1 + ---help--- + TIM9 Channel 2 output IDLE + +config STM32_TIM10_CH1POL + int "TIM10 Channel 1 Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM10_CH1OUT || (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_TIM10_CH1OUT + default 0 + range 0 1 + ---help--- + TIM10 Channel 1 output polarity + +config STM32_TIM10_CH1IDLE + int "TIM10 Channel 1 Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM10_CH1OUT || (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_TIM10_CH1OUT + default 0 + range 0 1 + ---help--- + TIM10 Channel 1 output IDLE + +config STM32_TIM11_CH1POL + int "TIM11 Channel 1 Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM11_CH1OUT || (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_TIM11_CH1OUT + default 0 + range 0 1 + ---help--- + TIM11 Channel 1 output polarity + +config STM32_TIM11_CH1IDLE + int "TIM11 Channel 1 Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM11_CH1OUT || (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_TIM11_CH1OUT + default 0 + range 0 1 + ---help--- + TIM11 Channel 1 output IDLE + +config STM32_TIM12_CH1POL + int "TIM12 Channel 1 Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM12_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM12_CH1OUT + default 0 + range 0 1 + ---help--- + TIM12 Channel 1 output polarity + +config STM32_TIM12_CH1IDLE + int "TIM12 Channel 1 Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM12_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM12_CH1OUT + default 0 + range 0 1 + ---help--- + TIM12 Channel 1 output IDLE + +config STM32_TIM12_CH2POL + int "TIM12 Channel 2 Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM12_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM12_CH2OUT + default 0 + range 0 1 + ---help--- + TIM12 Channel 2 output polarity + +config STM32_TIM12_CH2IDLE + int "TIM12 Channel 2 Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM12_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM12_CH2OUT + default 0 + range 0 1 + ---help--- + TIM12 Channel 2 output IDLE + +config STM32_TIM13_CH1POL + int "TIM13 Channel 1 Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM13_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM13_CH1OUT + default 0 + range 0 1 + ---help--- + TIM13 Channel 1 output polarity + +config STM32_TIM13_CH1IDLE + int "TIM13 Channel 1 Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM13_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM13_CH1OUT + default 0 + range 0 1 + ---help--- + TIM13 Channel 1 output IDLE + +config STM32_TIM14_CH1POL + int "TIM14 Channel 1 Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM14_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM14_CH1OUT + default 0 + range 0 1 + ---help--- + TIM14 Channel 1 output polarity + +config STM32_TIM14_CH1IDLE + int "TIM14 Channel 1 Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM14_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM14_CH1OUT + default 0 + range 0 1 + ---help--- + TIM14 Channel 1 output IDLE + +config STM32_TIM15_CH1POL + int "TIM15 Channel 1 Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM15_CH1OUT || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM15_CH1OUT + default 0 + range 0 1 + ---help--- + TIM15 Channel 1 output polarity + +config STM32_TIM15_CH1IDLE + int "TIM15 Channel 1 Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM15_CH1OUT || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM15_CH1OUT + default 0 + range 0 1 + ---help--- + TIM15 Channel 1 output IDLE + +config STM32_TIM15_CH1NPOL + int "TIM15 Channel 1 Complementary Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM15_CH1NOUT || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM15_CH1NOUT + default 0 + range 0 1 + ---help--- + TIM15 Channel 1 Complementary Output polarity + +config STM32_TIM15_CH1NIDLE + int "TIM15 Channel 1 Complementary Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM15_CH1NOUT || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM15_CH1NOUT + default 0 + range 0 1 + ---help--- + TIM15 Channel 1 Complementary Output IDLE + +config STM32_TIM15_CH2POL + int "TIM15 Channel 2 Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM15_CH2OUT || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM15_CH2OUT + default 0 + range 0 1 + ---help--- + TIM15 Channel 2 output polarity + +config STM32_TIM15_CH2IDLE + int "TIM15 Channel 2 Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM15_CH2OUT || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM15_CH2OUT + default 0 + range 0 1 + ---help--- + TIM15 Channel 2 output IDLE + +config STM32_TIM15_CH2NPOL + int "TIM15 Channel 2 Complementary Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM15_CH2NOUT || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM15_CH2NOUT + default 0 + range 0 1 + ---help--- + TIM15 Channel 2 Complementary Output polarity + +config STM32_TIM15_CH2NIDLE + int "TIM15 Channel 2 Complementary Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM15_CH2NOUT || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM15_CH2NOUT + default 0 + range 0 1 + ---help--- + TIM15 Channel 2 Complementary Output IDLE + +config STM32_TIM16_CH1POL + int "TIM16 Channel 1 Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM16_CH1OUT || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM16_CH1OUT + default 0 + range 0 1 + ---help--- + TIM16 Channel 1 output polarity + +config STM32_TIM16_CH1IDLE + int "TIM16 Channel 1 Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM16_CH1OUT || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM16_CH1OUT + default 0 + range 0 1 + ---help--- + TIM16 Channel 1 output IDLE + +config STM32_TIM17_CH1POL + int "TIM17 Channel 1 Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM17_CH1OUT || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM17_CH1OUT + default 0 + range 0 1 + ---help--- + TIM17 Channel 1 output polarity + +config STM32_TIM17_CH1IDLE + int "TIM17 Channel 1 Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM17_CH1OUT || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM17_CH1OUT + default 0 + range 0 1 + ---help--- + TIM17 Channel 1 output IDLE + +config STM32_ADC1_RESOLUTION + int "ADC1 resolution" + depends on STM32_COMMON_LEGACY && STM32_ADC && STM32_ADC1 && !STM32_HAVE_IP_ADC_V1_BASIC || (STM32_COMMON_F0_L0_G0_C0 || ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_ADC && STM32_ADC1 + default 0 + range 0 3 + ---help--- + ADC1 resolution. 0 - 12 bit, 1 - 10 bit, 2 - 8 bit, 3 - 6 bit + +config STM32_ADC2_RESOLUTION + int "ADC2 resolution" + depends on STM32_COMMON_LEGACY && STM32_ADC && STM32_ADC2 && !STM32_HAVE_IP_ADC_V1_BASIC || (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_ADC && STM32_ADC2 + default 0 + range 0 3 + ---help--- + ADC2 resolution. 0 - 12 bit, 1 - 10 bit, 2 - 8 bit, 3 - 6 bit + +config STM32_ADC3_RESOLUTION + int "ADC3 resolution" + depends on STM32_COMMON_LEGACY && STM32_ADC && STM32_ADC3 && !STM32_HAVE_IP_ADC_V1_BASIC || (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_ADC && STM32_ADC3 + default 0 + range 0 3 + ---help--- + ADC3 resolution. 0 - 12 bit, 1 - 10 bit, 2 - 8 bit, 3 - 6 bit + +config STM32_ADC_MAX_SAMPLES + int "The maximum number of channels that can be sampled" + depends on STM32_ADC + default 1 if STM32_COMMON_F0_L0_G0_C0 && !STM32_ADC1_DMA + default 16 + ---help--- + The maximum number of samples which can be handled without + overrun depends on various factors. This is the user's + responsibility to correctly select this value. + Since the interface to update the sampling time is available + for all supported devices, the user can change the default + values in the board initialization logic and avoid ADC overrun. + +config STM32_ADC_NO_STARTUP_CONV + bool "Do not start conversion when opening ADC device" + depends on STM32_ADC + ---help--- + Do not start conversion when opening ADC device. + +config STM32_ADC_NOIRQ + bool "Do not use default ADC interrupts" + depends on STM32_ADC + ---help--- + Do not use default ADC interrupts handlers. + +config STM32_ADC_LL_OPS + bool "ADC low-level operations" + depends on STM32_ADC + ---help--- + Enable low-level ADC ops. + +config STM32_ADC_CHANGE_SAMPLETIME + bool "ADC sample time configuration" + depends on (STM32_COMMON_LEGACY || STM32_COMMON_F0_L0_G0_C0 || ARCH_CHIP_STM32F7) && STM32_ADC_LL_OPS + ---help--- + Enable ADC sample time configuration (SMPRx registers). + +config STM32_ADC_OVERSAMPLE + bool "Enable ADC hardware oversampling support" + depends on STM32_ADC1 && STM32_HAVE_ADC_OVERSAMPLE + ---help--- + Enable the on-chip ADC oversampling/accumulation block (CFGR2.OVSE). + Only STM32G0 and STM32L0 series include this hardware block. + +if STM32_ADC_OVERSAMPLE + +config STM32_ADC_TOVS + bool "Enable triggered oversampling (CFGR2.TOVS)" + ---help--- + If set, oversampling will only occur when a trigger event occurs. + If not set, oversampling occurs continuously (TOVS=0). + +config STM32_ADC_OVSR + int "Oversampling ratio (CFGR2.OVSR)" + default 0 + range 0 7 + ---help--- + Sets the oversampling ratio as 2^(OVSR+1). For example: + 0 -> 2x + 1 -> 4x + 2 -> 8x + ... + 7 -> 256x + +config STM32_ADC_OVSS + int "Oversampling right-shift bits (CFGR2.OVSS)" + default 0 + range 0 8 + ---help--- + Sets how many bits the accumulated result is right-shifted. + Max of 8-bits. + +endif # STM32_ADC_OVERSAMPLE + +config STM32_ADC1_DMA + bool "ADC1 DMA" + depends on (STM32_COMMON_LEGACY || STM32_COMMON_F0_L0_G0_C0 || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC1 && STM32_HAVE_ADC1_DMA || ARCH_CHIP_STM32H7 && STM32_ADC && STM32_ADC1 && EXPERIMENTAL || STM32_COMMON_L4_L5_U5 && STM32_ADC && STM32_ADC1 || ARCH_CHIP_STM32H5 && STM32_ADC && STM32_ADC1 && STM32_DMA + ---help--- + If DMA is selected, then the ADC may be configured to support + DMA transfer, which is necessary if multiple channels are read + or if very high trigger frequencies are used. + +config STM32_ADC1_SCAN + bool "ADC1 scan mode" + depends on (STM32_COMMON_LEGACY && STM32_ADC && STM32_ADC1 && STM32_HAVE_IP_ADC_V1) || (ARCH_CHIP_STM32F7 && STM32_ADC && STM32_ADC1) + default STM32_ADC1_DMA + +config STM32_ADC1_DMA_CFG + int "ADC1 DMA configuration" + depends on (STM32_COMMON_LEGACY || STM32_COMMON_F0_L0_G0_C0) && STM32_ADC && STM32_ADC1_DMA && !STM32_HAVE_IP_ADC_V1_BASIC || (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_ADC && STM32_ADC1_DMA + default 1 if ARCH_CHIP_STM32L4 + default 0 + range 0 1 + ---help--- + 0 - ADC1 DMA in One Shot Mode, 1 - ADC1 DMA in Circular Mode + +config STM32_ADC1_DMA_BATCH + int "ADC1 DMA number of conversions" + depends on (STM32_COMMON_LEGACY || STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_ADC && STM32_ADC1 && STM32_ADC1_DMA + default 1 + ---help--- + This option allows you to select the number of regular group conversions + that will trigger a DMA callback transerring data to the upper-half driver. + By default, this value is 1, which means that data is transferred after + each group conversion. + +config STM32_ADC1_ANIOC_TRIGGER + int "ADC1 software trigger (ANIOC_TRIGGER) configuration" + depends on ((STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC1) + default 3 + range 1 3 + ---help--- + 1 - ANIOC_TRIGGER only starts regular conversion + 2 - ANIOC_TRIGGER only starts injected conversion + 3 - ANIOC_TRIGGER starts both regular and injected conversions + +config STM32_ADC2_DMA + bool "ADC2 DMA" + depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC2 && STM32_HAVE_ADC2_DMA || ARCH_CHIP_STM32H7 && STM32_ADC && STM32_ADC2 && EXPERIMENTAL || STM32_COMMON_L4_L5_U5 && STM32_ADC && STM32_ADC2 || ARCH_CHIP_STM32H5 && STM32_ADC && STM32_ADC2 && STM32_DMA + ---help--- + If DMA is selected, then the ADC may be configured to support + DMA transfer, which is necessary if multiple channels are read + or if very high trigger frequencies are used. + +config STM32_ADC2_SCAN + bool "ADC2 scan mode" + depends on (STM32_COMMON_LEGACY && STM32_ADC && STM32_ADC2 && STM32_HAVE_IP_ADC_V1) || (ARCH_CHIP_STM32F7 && STM32_ADC && STM32_ADC2) + default STM32_ADC2_DMA + +config STM32_ADC2_DMA_CFG + int "ADC2 DMA configuration" + depends on STM32_COMMON_LEGACY && STM32_ADC && STM32_ADC2_DMA && !STM32_HAVE_IP_ADC_V1_BASIC || (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_ADC && STM32_ADC2_DMA || ARCH_CHIP_STM32H5 && STM32_ADC && STM32_ADC2_DMA && STM32_DMA + default 1 if ARCH_CHIP_STM32L4 + default 0 + range 0 1 + ---help--- + 0 - ADC2 DMA in One Shot Mode, 1 - ADC2 DMA in Circular Mode + +config STM32_ADC2_DMA_BATCH + int "ADC2 DMA number of conversions" + depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_ADC && STM32_ADC2 && STM32_ADC2_DMA + default 1 + ---help--- + This option allows you to select the number of regular group conversions + that will trigger a DMA callback transerring data to the upper-half driver. + By default, this value is 1, which means that data is transferred after + each group conversion. + +config STM32_ADC2_ANIOC_TRIGGER + int "ADC2 software trigger (ANIOC_TRIGGER) configuration" + depends on ((STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC2) + default 3 + range 1 3 + ---help--- + 1 - ANIOC_TRIGGER only starts regular conversion + 2 - ANIOC_TRIGGER only starts injected conversion + 3 - ANIOC_TRIGGER starts both regular and injected conversions + +config STM32_ADC3_DMA + bool "ADC3 DMA" + depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC3 && STM32_HAVE_ADC3_DMA || ARCH_CHIP_STM32H7 && STM32_ADC && STM32_ADC3 && EXPERIMENTAL || STM32_COMMON_L4_L5_U5 && STM32_ADC && STM32_ADC3 + ---help--- + If DMA is selected, then the ADC may be configured to support + DMA transfer, which is necessary if multiple channels are read + or if very high trigger frequencies are used. + +config STM32_ADC3_SCAN + bool "ADC3 scan mode" + depends on (STM32_COMMON_LEGACY && STM32_ADC && STM32_ADC3 && STM32_HAVE_IP_ADC_V1) || (ARCH_CHIP_STM32F7 && STM32_ADC && STM32_ADC3) + default STM32_ADC3_DMA + +config STM32_ADC3_DMA_CFG + int "ADC3 DMA configuration" + depends on STM32_COMMON_LEGACY && STM32_ADC && STM32_ADC3_DMA && !STM32_HAVE_IP_ADC_V1_BASIC || (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_ADC && STM32_ADC3_DMA + default 1 if ARCH_CHIP_STM32L4 + default 0 + range 0 1 + ---help--- + 0 - ADC3 DMA in One Shot Mode, 1 - ADC3 DMA in Circular Mode + +config STM32_ADC3_DMA_BATCH + int "ADC3 DMA number of conversions" + depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4) && STM32_ADC && STM32_ADC3 && STM32_ADC3_DMA + default 1 + ---help--- + This option allows you to select the number of regular group conversions + that will trigger a DMA callback transerring data to the upper-half driver. + By default, this value is 1, which means that data is transferred after + each group conversion. + +config STM32_ADC3_ANIOC_TRIGGER + int "ADC3 software trigger (ANIOC_TRIGGER) configuration" + depends on ((STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC3) + default 3 + range 1 3 + ---help--- + 1 - ANIOC_TRIGGER only starts regular conversion + 2 - ANIOC_TRIGGER only starts injected conversion + 3 - ANIOC_TRIGGER starts both regular and injected conversions + +config STM32_ADC1_INJECTED_CHAN + int "ADC1 injected channels" + depends on ((STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC1) + default 0 + range 0 4 + ---help--- + Support for ADC1 injected channels. + +config STM32_ADC2_INJECTED_CHAN + int "ADC2 injected channels" + depends on ((STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC2) + default 0 + range 0 4 + ---help--- + Support for ADC2 injected channels. + +config STM32_ADC3_INJECTED_CHAN + int "ADC3 injected channels" + depends on ((STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC3) + default 0 + range 0 4 + ---help--- + Support for ADC3 injected channels. + +config STM32_ADC1_EXTSEL + bool "ADC1 external trigger for regular group" + depends on (STM32_COMMON_LEGACY || STM32_COMMON_F0_L0_G0_C0 || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC1 && !STM32_HAVE_ADC1_TIMER + ---help--- + Enable EXTSEL for ADC1. + +config STM32_ADC2_EXTSEL + bool "ADC2 external trigger for regular group" + depends on ((STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC2) && !STM32_HAVE_ADC2_TIMER + ---help--- + Enable EXTSEL for ADC2. + +config STM32_ADC3_EXTSEL + bool "ADC3 external trigger for regular group" + depends on ((STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC3) && !STM32_HAVE_ADC3_TIMER + ---help--- + Enable EXTSEL for ADC3. + +config STM32_ADC1_JEXTSEL + bool "ADC1 external trigger for injected group" + depends on ((STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC1) + ---help--- + Enable JEXTSEL for ADC1. + +config STM32_ADC2_JEXTSEL + bool "ADC2 external trigger for injected group" + depends on ((STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC2) + ---help--- + Enable JEXTSEL for ADC2. + +config STM32_ADC3_JEXTSEL + bool "ADC3 external trigger for injected group" + depends on ((STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC3) + ---help--- + Enable JEXTSEL for ADC3. + +config STM32_USART + bool + +config USART1_RS485 + bool "RS-485 on USART1" + depends on STM32_USART1 && USART1_SERIALDRIVER + ---help--- + Enable RS-485 interface on USART1. Your board config will have to + provide GPIO_USART1_RS485_DIR pin definition. Currently it cannot be + used with USART1_RXDMA. + +if USART1_RS485 + +config USART1_RS485_DIR_POLARITY + int "USART1 RS-485 DIR pin polarity" + default 1 + range 0 1 + ---help--- + Polarity of DIR pin for RS-485 on USART1. Set to state on DIR pin which + enables TX (0 - low / nTXEN, 1 - high / TXEN). + +endif # USART1_RS485 + +config USART1_RXDMA + bool + depends on STM32_USART1 && USART1_SERIALDRIVER + depends on STM32_COMMON_LEGACY && ((STM32_STM32F10XX || STM32_STM32L15XX) && STM32_DMA1 || !STM32_STM32F10XX && STM32_DMA2) || ARCH_CHIP_STM32F7 && STM32_DMA2 || STM32_COMMON_L4_L5_U5 && (STM32_DMA1 || STM32_DMA2 || STM32_DMAMUX) || ARCH_CHIP_STM32H5 && (STM32_DMA1 || STM32_DMA2) || ARCH_CHIP_STM32WB && STM32_DMA + ---help--- + In high data rate usage, Rx DMA may eliminate Rx overrun errors + +config USART1_TXDMA + bool + depends on STM32_USART1 && USART1_SERIALDRIVER + depends on STM32_COMMON_LEGACY && ((STM32_STM32F10XX || STM32_STM32L15XX) && STM32_DMA1 || !STM32_STM32F10XX && STM32_DMA2) || ARCH_CHIP_STM32F7 && STM32_DMA2 + ---help--- + In high data rate usage, Tx DMA may reduce CPU load + +config USART2_RS485 + bool "RS-485 on USART2" + depends on STM32_USART2 && USART2_SERIALDRIVER + ---help--- + Enable RS-485 interface on USART2. Your board config will have to + provide GPIO_USART2_RS485_DIR pin definition. Currently it cannot be + used with USART2_RXDMA. + +if USART2_RS485 + +config USART2_RS485_DIR_POLARITY + int "USART2 RS-485 DIR pin polarity" + default 1 + range 0 1 + ---help--- + Polarity of DIR pin for RS-485 on USART2. Set to state on DIR pin which + enables TX (0 - low / nTXEN, 1 - high / TXEN). + +endif # USART2_RS485 + +config USART2_RXDMA + bool + depends on STM32_USART2 && USART2_SERIALDRIVER + depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_DMA1 || STM32_COMMON_L4_L5_U5 && (STM32_DMA1 || STM32_DMAMUX) || ARCH_CHIP_STM32H5 && (STM32_DMA1 || STM32_DMA2) + ---help--- + In high data rate usage, Rx DMA may eliminate Rx overrun errors + +config USART2_TXDMA + bool + depends on STM32_USART2 && USART2_SERIALDRIVER + depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_DMA1 + ---help--- + In high data rate usage, Tx DMA may reduce CPU load + +config USART3_RS485 + bool "RS-485 on USART3" + depends on STM32_USART3 && USART3_SERIALDRIVER + ---help--- + Enable RS-485 interface on USART3. Your board config will have to + provide GPIO_USART3_RS485_DIR pin definition. Currently it cannot be + used with USART3_RXDMA. + +if USART3_RS485 + +config USART3_RS485_DIR_POLARITY + int "USART3 RS-485 DIR pin polarity" + default 1 + range 0 1 + ---help--- + Polarity of DIR pin for RS-485 on USART3. Set to state on DIR pin which + enables TX (0 - low / nTXEN, 1 - high / TXEN). + +endif # USART3_RS485 + +config USART3_RXDMA + bool + depends on STM32_USART3 && USART3_SERIALDRIVER + depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_DMA1 || STM32_COMMON_L4_L5_U5 && (STM32_DMA1 || STM32_DMAMUX) || ARCH_CHIP_STM32H5 && (STM32_DMA1 || STM32_DMA2) + ---help--- + In high data rate usage, Rx DMA may eliminate Rx overrun errors + +config USART3_TXDMA + bool + depends on STM32_USART3 && USART3_SERIALDRIVER + depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_DMA1 + ---help--- + In high data rate usage, Tx DMA may reduce CPU load + +config UART4_RS485 + bool "RS-485 on UART4" + depends on STM32_UART4 && UART4_SERIALDRIVER + ---help--- + Enable RS-485 interface on UART4. Your board config will have to + provide GPIO_UART4_RS485_DIR pin definition. Currently it cannot be + used with UART4_RXDMA. + +if UART4_RS485 + +config UART4_RS485_DIR_POLARITY + int "UART4 RS-485 DIR pin polarity" + default 1 + range 0 1 + ---help--- + Polarity of DIR pin for RS-485 on UART4. Set to state on DIR pin which + enables TX (0 - low / nTXEN, 1 - high / TXEN). + +endif # UART4_RS485 + +config UART4_RXDMA + bool + depends on STM32_UART4 && UART4_SERIALDRIVER + depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_DMA1 || STM32_COMMON_L4_L5_U5 && (STM32_DMA2 || STM32_DMAMUX) || ARCH_CHIP_STM32H5 && (STM32_DMA1 || STM32_DMA2) + ---help--- + In high data rate usage, Rx DMA may eliminate Rx overrun errors + +config UART4_TXDMA + bool + depends on STM32_UART4 && UART4_SERIALDRIVER + depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_DMA1 + ---help--- + In high data rate usage, Tx DMA may reduce CPU load + +config UART5_RS485 + bool "RS-485 on UART5" + depends on STM32_UART5 && UART5_SERIALDRIVER + ---help--- + Enable RS-485 interface on UART5. Your board config will have to + provide GPIO_UART5_RS485_DIR pin definition. Currently it cannot be + used with UART5_RXDMA. + +if UART5_RS485 + +config UART5_RS485_DIR_POLARITY + int "UART5 RS-485 DIR pin polarity" + default 1 + range 0 1 + ---help--- + Polarity of DIR pin for RS-485 on UART5. Set to state on DIR pin which + enables TX (0 - low / nTXEN, 1 - high / TXEN). + +endif # UART5_RS485 + +config UART5_RXDMA + bool + depends on STM32_UART5 && UART5_SERIALDRIVER + depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_DMA1 || STM32_COMMON_L4_L5_U5 && (STM32_DMA2 || STM32_DMAMUX) || ARCH_CHIP_STM32H5 && (STM32_DMA1 || STM32_DMA2) + ---help--- + In high data rate usage, Rx DMA may eliminate Rx overrun errors + +config UART5_TXDMA + bool + depends on STM32_UART5 && UART5_SERIALDRIVER + depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_DMA1 + ---help--- + In high data rate usage, Tx DMA may reduce CPU load + +config USART6_RS485 + bool "RS-485 on USART6" + depends on STM32_USART6 && USART6_SERIALDRIVER + ---help--- + Enable RS-485 interface on USART6. Your board config will have to + provide GPIO_USART6_RS485_DIR pin definition. Currently it cannot be + used with USART6_RXDMA. + +if USART6_RS485 + +config USART6_RS485_DIR_POLARITY + int "USART6 RS-485 DIR pin polarity" + default 1 + range 0 1 + ---help--- + Polarity of DIR pin for RS-485 on USART6. Set to state on DIR pin which + enables TX (0 - low / nTXEN, 1 - high / TXEN). + +endif # USART6_RS485 + +config USART6_RXDMA + bool + depends on STM32_USART6 && USART6_SERIALDRIVER + depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_DMA2 || ARCH_CHIP_STM32H5 && (STM32_DMA1 || STM32_DMA2) + ---help--- + In high data rate usage, Rx DMA may eliminate Rx overrun errors + +config USART6_TXDMA + bool + depends on STM32_USART6 && USART6_SERIALDRIVER + depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_DMA2 + ---help--- + In high data rate usage, Tx DMA may reduce CPU load + +config UART7_RS485 + bool "RS-485 on UART7" + depends on STM32_UART7 && UART7_SERIALDRIVER + ---help--- + Enable RS-485 interface on UART7. Your board config will have to + provide GPIO_UART7_RS485_DIR pin definition. Currently it cannot be + used with UART7_RXDMA. + +if UART7_RS485 + +config UART7_RS485_DIR_POLARITY + int "UART7 RS-485 DIR pin polarity" + default 1 + range 0 1 + ---help--- + Polarity of DIR pin for RS-485 on UART7. Set to state on DIR pin which + enables TX (0 - low / nTXEN, 1 - high / TXEN). + +endif # UART7_RS485 + +config UART7_RXDMA + bool + depends on STM32_UART7 && UART7_SERIALDRIVER + depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_DMA1 || ARCH_CHIP_STM32H5 && (STM32_DMA1 || STM32_DMA2) + ---help--- + In high data rate usage, Rx DMA may eliminate Rx overrun errors + +config UART7_TXDMA + bool + depends on STM32_UART7 && UART7_SERIALDRIVER + depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_DMA1 + ---help--- + In high data rate usage, Tx DMA may reduce CPU load + +config UART8_RS485 + bool "RS-485 on UART8" + depends on STM32_UART8 && UART8_SERIALDRIVER + ---help--- + Enable RS-485 interface on UART8. Your board config will have to + provide GPIO_UART8_RS485_DIR pin definition. Currently it cannot be + used with UART8_RXDMA. + +if UART8_RS485 + +config UART8_RS485_DIR_POLARITY + int "UART8 RS-485 DIR pin polarity" + default 1 + range 0 1 + ---help--- + Polarity of DIR pin for RS-485 on UART8. Set to state on DIR pin which + enables TX (0 - low / nTXEN, 1 - high / TXEN). + +endif # UART8_RS485 + +config UART8_RXDMA + bool + depends on STM32_UART8 && UART8_SERIALDRIVER + depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_DMA1 || ARCH_CHIP_STM32H5 && (STM32_DMA1 || STM32_DMA2) + ---help--- + In high data rate usage, Rx DMA may eliminate Rx overrun errors + +config UART8_TXDMA + bool + depends on STM32_UART8 && UART8_SERIALDRIVER + depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_DMA1 + ---help--- + In high data rate usage, Tx DMA may reduce CPU load + +config LPUART1_RS485 + bool "RS-485 on LPUART1" + depends on STM32_LPUART1 && LPUART1_SERIALDRIVER + ---help--- + Enable RS-485 interface on LPUART1. Your board config will have to + provide GPIO_LPUART1_RS485_DIR pin definition. Currently it cannot be + used with LPUART1_RXDMA. + +if LPUART1_RS485 + +config LPUART1_RS485_DIR_POLARITY + int "LPUART1 RS-485 DIR pin polarity" + default 1 + range 0 1 + ---help--- + Polarity of DIR pin for RS-485 on LPUART1. Set to state on DIR pin which + enables TX (0 - low / nTXEN, 1 - high / TXEN). + +endif # LPUART1_RS485 + +config LPUART1_RXDMA + bool + depends on STM32_LPUART1 && LPUART1_SERIALDRIVER + depends on STM32_COMMON_LEGACY && STM32_DMA1 || STM32_COMMON_L4_L5_U5 && (STM32_DMA1 || STM32_DMA2 || STM32_DMAMUX) || ARCH_CHIP_STM32H5 && (STM32_DMA1 || STM32_DMA2) || ARCH_CHIP_STM32WB && STM32_DMA + ---help--- + In high data rate usage, Rx DMA may eliminate Rx overrun errors + +config STM32_SERIAL_RXDMA_BUFFER_SIZE + int "Rx DMA buffer size" + depends on STM32_USART && SERIAL_RXDMA + range 32 4096 + default 32 + ---help--- + The DMA buffer size when using RX DMA to emulate a FIFO. + + When streaming data, the generic serial layer will be called + every time the FIFO receives half or this number of bytes. + + Value given here will be rounded up to next multiple of 4 bytes. + +config STM32_SERIAL_DISABLE_REORDERING + bool "Disable reordering of ttySx devices." + depends on STM32_USART + ---help--- + NuttX per default reorders the serial ports (/dev/ttySx) so that the + console is always on /dev/ttyS0. If more than one UART is in use this + can, however, have the side-effect that all port mappings + (hardware USART1 -> /dev/ttyS0) change if the console is moved to another + UART. This is in particular relevant if a project uses the USB console + in some boards and a serial console in other boards, but does not + want the side effect of having all serial port names change when just + the console is moved from serial to USB. + +config STM32_FLOWCONTROL_BROKEN + bool "Use Software UART RTS flow control" + depends on STM32_USART + ---help--- + Enable UART RTS flow control using Software. Because STM + Current STM32 have broken HW based RTS behavior (they assert + nRTS after every byte received) Enable this setting workaround + this issue by using software based management of RTS + +config STM32_USART_BREAKS + bool "Add TIOxSBRK to support sending Breaks" + depends on STM32_USART + ---help--- + Add TIOCxBRK routines to send a line break per the STM32 manual, the + break will be a pulse based on the value M. This is not a BSD compatible + break. + +config STM32_SERIALBRK_BSDCOMPAT + bool "Use GPIO To send Break" + depends on STM32_USART_BREAKS + ---help--- + Enable using GPIO on the TX pin to send a BSD compatible break: + TIOCSBRK will start the break and TIOCCBRK will end the break. + The current STM32 U[S]ARTS have no way to leave the break on + (TX=LOW) because software starts the break and then the hardware + automatically clears the break. This makes it difficult to send + a long break. + +config STM32_USART_SINGLEWIRE + bool "Single Wire Support" + depends on STM32_USART + ---help--- + Enable single wire UART support. The option enables support for the + TIOCSSINGLEWIRE ioctl in the STM32 serial driver. + +config STM32_PM_SERIAL_ACTIVITY + int "PM serial activity" + depends on PM + depends on STM32_USART + default 10 + ---help--- + PM activity reported to power management logic on every serial + interrupt. + +config LPUART1_UNCONFIG_RX_ON_CLOSE + bool "Unconfigure LPUART1 RX pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && LPUART1_SERIALDRIVER + +config LPUART1_UNCONFIG_TX_ON_CLOSE + bool "Unconfigure LPUART1 TX pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && LPUART1_SERIALDRIVER + +config LPUART1_UNCONFIG_DIR_ON_CLOSE + bool "Unconfigure LPUART1 DIR pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && LPUART1_SERIALDRIVER && LPUART1_RS485 + +config USART1_UNCONFIG_RX_ON_CLOSE + bool "Unconfigure USART1 RX pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART1_SERIALDRIVER + +config USART1_UNCONFIG_TX_ON_CLOSE + bool "Unconfigure USART1 TX pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART1_SERIALDRIVER + +config USART1_UNCONFIG_DIR_ON_CLOSE + bool "Unconfigure USART1 DIR pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART1_SERIALDRIVER && USART1_RS485 + +config USART2_UNCONFIG_RX_ON_CLOSE + bool "Unconfigure USART2 RX pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART2_SERIALDRIVER + +config USART2_UNCONFIG_TX_ON_CLOSE + bool "Unconfigure USART2 TX pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART2_SERIALDRIVER + +config USART2_UNCONFIG_DIR_ON_CLOSE + bool "Unconfigure USART2 DIR pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART2_SERIALDRIVER && USART2_RS485 + +config USART3_UNCONFIG_RX_ON_CLOSE + bool "Unconfigure USART3 RX pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART3_SERIALDRIVER + +config USART3_UNCONFIG_TX_ON_CLOSE + bool "Unconfigure USART3 TX pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART3_SERIALDRIVER + +config USART3_UNCONFIG_DIR_ON_CLOSE + bool "Unconfigure USART3 DIR pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART3_SERIALDRIVER && USART3_RS485 + +config UART4_UNCONFIG_RX_ON_CLOSE + bool "Unconfigure UART4 RX pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART4_SERIALDRIVER + +config UART4_UNCONFIG_TX_ON_CLOSE + bool "Unconfigure UART4 TX pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART4_SERIALDRIVER + +config UART4_UNCONFIG_DIR_ON_CLOSE + bool "Unconfigure UART4 DIR pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART4_SERIALDRIVER && UART4_RS485 + +config UART5_UNCONFIG_RX_ON_CLOSE + bool "Unconfigure UART5 RX pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART5_SERIALDRIVER + +config UART5_UNCONFIG_TX_ON_CLOSE + bool "Unconfigure UART5 TX pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART5_SERIALDRIVER + +config UART5_UNCONFIG_DIR_ON_CLOSE + bool "Unconfigure UART5 DIR pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART5_SERIALDRIVER && UART5_RS485 + +config USART6_UNCONFIG_RX_ON_CLOSE + bool "Unconfigure USART6 RX pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART6_SERIALDRIVER + +config USART6_UNCONFIG_TX_ON_CLOSE + bool "Unconfigure USART6 TX pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART6_SERIALDRIVER + +config USART6_UNCONFIG_DIR_ON_CLOSE + bool "Unconfigure USART6 DIR pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART6_SERIALDRIVER && USART6_RS485 + +config UART7_UNCONFIG_RX_ON_CLOSE + bool "Unconfigure UART7 RX pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART7_SERIALDRIVER + +config UART7_UNCONFIG_TX_ON_CLOSE + bool "Unconfigure UART7 TX pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART7_SERIALDRIVER + +config UART7_UNCONFIG_DIR_ON_CLOSE + bool "Unconfigure UART7 DIR pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART7_SERIALDRIVER && UART7_RS485 + +config UART8_UNCONFIG_RX_ON_CLOSE + bool "Unconfigure UART8 RX pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART8_SERIALDRIVER + +config UART8_UNCONFIG_TX_ON_CLOSE + bool "Unconfigure UART8 TX pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART8_SERIALDRIVER + +config UART8_UNCONFIG_DIR_ON_CLOSE + bool "Unconfigure UART8 DIR pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART8_SERIALDRIVER && UART8_RS485 + +config UART9_UNCONFIG_RX_ON_CLOSE + bool "Unconfigure UART9 RX pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART9_SERIALDRIVER + +config UART9_UNCONFIG_TX_ON_CLOSE + bool "Unconfigure UART9 TX pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART9_SERIALDRIVER + +config UART9_UNCONFIG_DIR_ON_CLOSE + bool "Unconfigure UART9 DIR pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART9_SERIALDRIVER && UART9_RS485 + +config USART10_UNCONFIG_RX_ON_CLOSE + bool "Unconfigure USART10 RX pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART10_SERIALDRIVER + +config USART10_UNCONFIG_TX_ON_CLOSE + bool "Unconfigure USART10 TX pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART10_SERIALDRIVER + +config USART10_UNCONFIG_DIR_ON_CLOSE + bool "Unconfigure USART10 DIR pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART10_SERIALDRIVER && USART10_RS485 + +config USART11_UNCONFIG_RX_ON_CLOSE + bool "Unconfigure USART11 RX pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART11_SERIALDRIVER + +config USART11_UNCONFIG_TX_ON_CLOSE + bool "Unconfigure USART11 TX pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART11_SERIALDRIVER + +config USART11_UNCONFIG_DIR_ON_CLOSE + bool "Unconfigure USART11 DIR pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART11_SERIALDRIVER && USART11_RS485 + +config UART12_UNCONFIG_RX_ON_CLOSE + bool "Unconfigure UART12 RX pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART12_SERIALDRIVER + +config UART12_UNCONFIG_TX_ON_CLOSE + bool "Unconfigure UART12 TX pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART12_SERIALDRIVER + +config UART12_UNCONFIG_DIR_ON_CLOSE + bool "Unconfigure UART12 DIR pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART12_SERIALDRIVER && UART12_RS485 + +config STM32_SPI_INTERRUPTS + bool "Interrupt driver SPI" + depends on STM32_SPI + depends on STM32_COMMON_FULL_FEATURED || ARCH_CHIP_STM32WL5 || ARCH_CHIP_STM32WB && (STM32_SPI1 || STM32_SPI2) + ---help--- + Select to enable interrupt driven SPI support. Non-interrupt-driven, + poll-waiting is recommended if the interrupt rate would be to high in + the interrupt driven case. + +config STM32_SPI1_DMA + bool "SPI1 DMA" + depends on STM32_SPI && STM32_SPI1 + depends on STM32_SPI_DMA_FAMILY_WL5 && !STM32_SPI_INTERRUPT || STM32_COMMON_F0_L0_G0_C0 && !STM32_SPI_INTERRUPTS + select STM32_SPI_DMA + ---help--- + Use DMA to improve SPI1 transfer performance. Cannot be used with STM32_SPI_INTERRUPT. + +config STM32_SPI1_DMA_BUFFER + int "SPI1 DMA buffer size" + depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7_H5 || ARCH_CHIP_STM32WL5) && STM32_SPI1_DMA + default 0 + ---help--- + Add a properly aligned DMA buffer for RX and TX DMA for SPI1. + +config STM32_SPI_DMATHRESHOLD + int "SPI DMA threshold" + depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7_H5 || ARCH_CHIP_STM32WL5) && STM32_SPI_DMA + default 4 + ---help--- + When SPI DMA is enabled, small DMA transfers will still be performed + by polling logic. But we need a threshold value to determine what + is small. + +config STM32_SPI2_DMA + bool "SPI2 DMA" + depends on STM32_SPI && STM32_SPI2 + depends on STM32_SPI_DMA_FAMILY && !STM32_SPI_INTERRUPT || STM32_COMMON_F0_L0_G0_C0 && !STM32_SPI_INTERRUPTS + select STM32_SPI_DMA + ---help--- + Use DMA to improve SPI2 transfer performance. Cannot be used with STM32_SPI_INTERRUPT. + +config STM32_SPI2_DMA_BUFFER + int "SPI2 DMA buffer size" + depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7_H5) && STM32_SPI2_DMA + default 0 + ---help--- + Add a properly aligned DMA buffer for RX and TX DMA for SPI2. + +config STM32_SPI3_DMA + bool "SPI3 DMA" + depends on STM32_SPI && STM32_SPI3 + depends on STM32_SPI_DMA_FAMILY && !STM32_SPI_INTERRUPT || STM32_COMMON_F0_L0_G0_C0 && !STM32_SPI_INTERRUPTS + select STM32_SPI_DMA + ---help--- + Use DMA to improve SPI3 transfer performance. Cannot be used with STM32_SPI_INTERRUPT. + +config STM32_SPI3_DMA_BUFFER + int "SPI3 DMA buffer size" + depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7_H5) && STM32_SPI3_DMA + default 0 + ---help--- + Add a properly aligned DMA buffer for RX and TX DMA for SPI3. + +config STM32_SPI4_DMA + bool "SPI4 DMA" + depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7_H5) && STM32_SPI && STM32_SPI4 && !STM32_SPI_INTERRUPT + select STM32_SPI_DMA + ---help--- + Use DMA to improve SPI4 transfer performance. Cannot be used with STM32_SPI_INTERRUPT. + +config STM32_SPI4_DMA_BUFFER + int "SPI4 DMA buffer size" + depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7_H5) && STM32_SPI4_DMA + default 0 + ---help--- + Add a properly aligned DMA buffer for RX and TX DMA for SPI4. + +config STM32_SPI5_DMA + bool "SPI5 DMA" + depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7_H5) && STM32_SPI && STM32_SPI5 && !STM32_SPI_INTERRUPT + select STM32_SPI_DMA + ---help--- + Use DMA to improve SPI5 transfer performance. Cannot be used with STM32_SPI_INTERRUPT. + +config STM32_SPI5_DMA_BUFFER + int "SPI5 DMA buffer size" + depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7_H5) && STM32_SPI5_DMA + default 0 + ---help--- + Add a properly aligned DMA buffer for RX and TX DMA for SPI5. + +config STM32_SPI6_DMA + bool "SPI6 DMA" + depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7_H5) && STM32_SPI && STM32_SPI6 && !STM32_SPI_INTERRUPT + select STM32_SPI_DMA + ---help--- + Use DMA to improve SPI6 transfer performance. Cannot be used with STM32_SPI_INTERRUPT. + +config STM32_SPI2S2_DMA + bool "SPI2S2 DMA" + depends on STM32_SPI2 && !STM32_SPI_INTERRUPT + select STM32_SPI_DMA + ---help--- + Use DMA to improve SPI2S2 transfer performance. Cannot be used with + STM32_SPI_INTERRUPT. + +config STM32_SPI2S2_DMA_BUFFER + int "SPI2S2 DMA buffer size" + default 0 + depends on STM32_SPI2S2_DMA + ---help--- + Add a properly aligned DMA buffer for RX and TX DMA for SPI2S2. + +config STM32_I2S_MAXINFLIGHT + int "I2S queue size" + depends on (STM32_COMMON_LEGACY && STM32_I2S3) || (ARCH_CHIP_STM32F7 && STM32_I2S) + default 16 + ---help--- + This is the total number of transfers, both RX and TX, that can be + enqueue before the caller is required to wait. This setting + determines the number certain queue data structures that will be + pre-allocated. + +config STM32_I2S3_DATALEN + int "Data width (bits)" + depends on (STM32_COMMON_LEGACY && STM32_I2S3) || (ARCH_CHIP_STM32F7 && STM32_I2S && STM32_I2S3) + default 16 + ---help--- + Data width in bits. This is a default value and may be change + via the I2S interface + +config STM32_I2S1_MCK + bool "I2S1_MCK" + depends on ARCH_CHIP_STM32F7 && STM32_I2S1 + ---help--- + TBD. + +config STM32_I2S1_RX + bool "Enable I2S1 receiver" + depends on ARCH_CHIP_STM32F7 && STM32_I2S1 + ---help--- + Enable I2S receipt logic + +config STM32_I2S1_TX + bool "Enable I2S1 transmitter" + depends on ARCH_CHIP_STM32F7 && STM32_I2S1 + ---help--- + Enable I2S transmission logic + +config STM32_I2S1_DATALEN + int "I2S1 Data width (bits)" + depends on ARCH_CHIP_STM32F7 && STM32_I2S1 + default 16 + ---help--- + Data width in bits. This is a default value and may be changed via + the I2S interface. + +config STM32_I2S2_MCK + bool "I2S2_MCK" + depends on ARCH_CHIP_STM32F7 && STM32_I2S2 + ---help--- + TBD. + +config STM32_I2S2_RX + bool "Enable I2S2 receiver" + depends on ARCH_CHIP_STM32F7 && STM32_I2S2 + ---help--- + Enable I2S receipt logic + +config STM32_I2S2_TX + bool "Enable I2S2 transmitter" + depends on ARCH_CHIP_STM32F7 && STM32_I2S2 + ---help--- + Enable I2S transmission logic + +config STM32_I2S2_DATALEN + int "I2S2 Data width (bits)" + depends on ARCH_CHIP_STM32F7 && STM32_I2S2 + default 16 + ---help--- + Data width in bits. This is a default value and may be changed via + the I2S interface. + +config STM32_I2S3_MCK + bool "I2S3_MCK" + depends on ARCH_CHIP_STM32F7 && STM32_I2S3 + ---help--- + TBD. + +#if STM32_I2S + +config STM32_I2S3_RX + bool "Enable I2S receiver" + depends on (STM32_COMMON_LEGACY && STM32_I2S3) || (ARCH_CHIP_STM32F7 && STM32_I2S && STM32_I2S3) + ---help--- + Enable I2S receipt logic + +config STM32_I2S3_TX + bool "Enable I2S transmitter" + depends on (STM32_COMMON_LEGACY && STM32_I2S3) || (ARCH_CHIP_STM32F7 && STM32_I2S && STM32_I2S3) + ---help--- + Enable I2S transmission logic + +config STM32_I2S_DMADEBUG + bool "I2S DMA transfer debug" + depends on (STM32_COMMON_LEGACY && STM32_I2S3 && DEBUG_DMA) || (ARCH_CHIP_STM32F7 && STM32_I2S && DEBUG_DMA) + ---help--- + Enable special debug instrumentation analyze I2S DMA data transfers. + This logic is as non-invasive as possible: It samples DMA + registers at key points in the data transfer and then dumps all of + the registers at the end of the transfer. + +config STM32_I2S_REGDEBUG + bool "SSC Register level debug" + depends on (STM32_COMMON_LEGACY && STM32_I2S3 && DEBUG) || (ARCH_CHIP_STM32F7 && STM32_I2S && DEBUG) + ---help--- + Output detailed register-level SSC device debug information. + Very invasive! Requires also DEBUG. + +config STM32_I2C_DYNTIMEO + bool "Use dynamic timeouts" + depends on (STM32_COMMON_FULL_FEATURED) && STM32_I2C + +config STM32_I2C_DYNTIMEO_USECPERBYTE + int "Timeout Microseconds per Byte" + depends on (STM32_COMMON_FULL_FEATURED) && STM32_I2C && STM32_I2C_DYNTIMEO + default 500 + +config STM32_I2C_DYNTIMEO_STARTSTOP + int "Timeout for Start/Stop (Milliseconds)" + depends on (STM32_COMMON_FULL_FEATURED) && STM32_I2C && STM32_I2C_DYNTIMEO + default 1000 + +config STM32_I2CTIMEOSEC + int "Timeout seconds" + depends on (STM32_COMMON_FULL_FEATURED) && STM32_I2C + default 0 + +config STM32_I2CTIMEOMS + int "Timeout Milliseconds" + depends on (STM32_COMMON_FULL_FEATURED) && STM32_I2C && !STM32_I2C_DYNTIMEO + default 500 + +config STM32_I2CTIMEOTICKS + int "Timeout for Done and Stop (ticks)" + depends on (STM32_COMMON_FULL_FEATURED) && STM32_I2C && !STM32_I2C_DYNTIMEO + default 500 + +config STM32_BBSRAM + bool "BBSRAM File Support" + depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7) && STM32_BKPSRAM + select ARM_MPU if ARCH_CHIP_STM32H7 && STM32_BKPSRAM + +config STM32_BBSRAM_FILES + int "Max Files to support in BBSRAM" + depends on STM32_COMMON_LEGACY && STM32_BKPSRAM || STM32_COMMON_F7_H7 && STM32_BKPSRAM && STM32_BBSRAM + default 4 + +config STM32_SAVE_CRASHDUMP + bool "Enable Saving Panic to BBSRAM" + depends on STM32_COMMON_LEGACY && STM32_BKPSRAM || STM32_COMMON_F7_H7 && STM32_BKPSRAM && STM32_BBSRAM + +config STM32_HAVE_RTC_SUBSECONDS + bool + select ARCH_HAVE_RTC_SUBSECONDS + +config STM32_RTC_MAGIC_REG + int "BKP register" + depends on STM32_RTC_MAGIC_CAPABLE + default 0 + range 0 19 if STM32_COMMON_LEGACY && STM32_RTC && !STM32_HAVE_RTC_COUNTER + range 0 31 if STM32_HAVE_RTC_SUBSECONDS || ARCH_CHIP_STM32U5 + ---help--- + The BKP register used to store/check the Magic value to determine if + RTC is already setup + +config STM32_RTC_MAGIC + hex "RTC Magic 1" + depends on STM32_RTC_MAGIC_CAPABLE + default 0xfacefeed + ---help--- + Value used as Magic to determine if the RTC is already setup + +config STM32_RTC_MAGIC_TIME_SET + hex "RTC Magic 2" + depends on STM32_RTC_MAGIC_CAPABLE + default 0xf00dface + ---help--- + Value used as Magic to determine if the RTC has been setup and has + time set + +if STM32_ETHMAC + +config STM32_PHYADDR + int "PHY address" + default 1 if STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7 + default 0 + ---help--- + The 5-bit address of the PHY on the board. Default: 1 + +config STM32_PHYINIT + bool "Board-specific PHY Initialization" + ---help--- + Some boards require specialized initialization of the PHY before it can be used. + This may include such things as configuring GPIOs, resetting the PHY, etc. If + STM32_PHYINIT is defined in the configuration then the board specific logic must + provide stm32_phyinitialize(); The STM32 Ethernet driver will call this function + one time before it first uses the PHY. + +config STM32_MII + bool "Use MII interface" + ---help--- + Support Ethernet MII interface. + +config STM32_AUTONEG + bool "Use autonegotiation" + default y + ---help--- + Use PHY autonegotiation to determine speed and mode + +if !STM32_AUTONEG + +config STM32_ETHFD + bool "Full duplex" + ---help--- + If STM32_AUTONEG is not defined, then this may be defined to select full duplex + mode. Default: half-duplex + +config STM32_ETH100MBPS + bool "100 Mbps" + ---help--- + If STM32_AUTONEG is not defined, then this may be defined to select 100 MBps + speed. Default: 10 Mbps + +endif # !STM32_AUTONEG + +if STM32_AUTONEG + +config STM32_PHYSR + int "PHY Status Register Address (decimal)" + ---help--- + This must be provided if STM32_AUTONEG is defined. The PHY status register + address may diff from PHY to PHY. This configuration sets the address of + the PHY status register. + +config STM32_PHYSR_ALTCONFIG + bool "PHY Status Alternate Bit Layout" + ---help--- + Different PHYs present speed and mode information in different ways. Some + will present separate information for speed and mode (this is the default). + Those PHYs, for example, may provide a 10/100 Mbps indication and a separate + full/half duplex indication. This options selects an alternative representation + where speed and mode information are combined. This might mean, for example, + separate bits for 10HD, 100HD, 10FD and 100FD. + +if !STM32_PHYSR_ALTCONFIG + +config STM32_PHYSR_SPEED + hex "PHY Speed Mask" + ---help--- + This must be provided if STM32_AUTONEG is defined. This provides bit mask + for isolating the 10 or 100MBps speed indication. + +config STM32_PHYSR_100MBPS + hex "PHY 100Mbps Speed Value" + ---help--- + This must be provided if STM32_AUTONEG is defined. This provides the value + of the speed bit(s) indicating 100MBps speed. + +config STM32_PHYSR_MODE + hex "PHY Mode Mask" + ---help--- + This must be provided if STM32_AUTONEG is defined. This provide bit mask + for isolating the full or half duplex mode bits. + +config STM32_PHYSR_FULLDUPLEX + hex "PHY Full Duplex Mode Value" + ---help--- + This must be provided if STM32_AUTONEG is defined. This provides the + value of the mode bits indicating full duplex mode. + +endif # !STM32_PHYSR_ALTCONFIG + +if STM32_PHYSR_ALTCONFIG + +config STM32_PHYSR_ALTMODE + hex "PHY Mode Mask" + ---help--- + This must be provided if STM32_AUTONEG is defined. This provide bit mask + for isolating the speed and full/half duplex mode bits. + +config STM32_PHYSR_10HD + hex "10MBase-T Half Duplex Value" + ---help--- + This must be provided if STM32_AUTONEG is defined. This is the value + under the bit mask that represents the 10Mbps, half duplex setting. + +config STM32_PHYSR_100HD + hex "100Base-T Half Duplex Value" + ---help--- + This must be provided if STM32_AUTONEG is defined. This is the value + under the bit mask that represents the 100Mbps, half duplex setting. + +config STM32_PHYSR_10FD + hex "10Base-T Full Duplex Value" + ---help--- + This must be provided if STM32_AUTONEG is defined. This is the value + under the bit mask that represents the 10Mbps, full duplex setting. + +config STM32_PHYSR_100FD + hex "100Base-T Full Duplex Value" + ---help--- + This must be provided if STM32_AUTONEG is defined. This is the value + under the bit mask that represents the 100Mbps, full duplex setting. + +endif # STM32_PHYSR_ALTCONFIG + +endif # STM32_AUTONEG + +config STM32_ETH_PTP + bool "Precision Time Protocol (PTP)" + ---help--- + Enables Precision Time Protocol (PTP) hardware timer. + +config STM32_ETH_ENHANCEDDESC + bool "Enable enhanced RX/TX descriptors" + depends on STM32_COMMON_LEGACY + default n + ---help--- + Enables double-length DMA descriptors that have space for packet + timestamps and checksum offloading. + +config STM32_ETH_PTP_GPIO + bool "PTP pulse-per-second output signal" + depends on STM32_COMMON_LEGACY && STM32_ETH_PTP + default n + ---help--- + Enables pulse-per-second output on GPIO pin. + +config STM32_ETH_PTP_RTC_HIRES + bool "Use PTP timer as system high-resolution RTC" + depends on STM32_COMMON_LEGACY && STM32_ETH_PTP + default n + ---help--- + Uses the Ethernet peripheral PTP timer as the CONFIG_RTC_HIRES source. + This provides high resolution timestamps to clock_gettime(). + Note that PTP timer is disabled when Ethernet interface is down or + being reset. During this time g_rtc_enabled is set to false and system + uses the lower resolution system tick counter. + +config STM32_ETH_TIMESTAMP_RX + bool "Hardware timestamping of received packets" + depends on STM32_COMMON_LEGACY && STM32_ETH_PTP && NET_TIMESTAMP && STM32_ETH_ENHANCEDDESC + select ARCH_HAVE_NETDEV_TIMESTAMP + default n + ---help--- + Timestamp all received Ethernet packets. + Timestamp is available to application through SO_TIMESTAMP socket option. + +config STM32_RMII + bool + default !STM32_MII + +config STM32_ETHMAC_REGDEBUG + bool "Register-Level Debug" + depends on DEBUG_NET_INFO + ---help--- + Enable very low-level register access debug. Depends on CONFIG_DEBUG_FEATURES. + +endif # STM32_ETHMAC + +config STM32_USBHOST_REGDEBUG + bool "Register-Level Debug" + depends on STM32_COMMON_LEGACY && STM32_USBHOST && STM32_USBHOST && DEBUG_USB_INFO || STM32_COMMON_F7_H7 && USBHOST + ---help--- + Enable very low-level register access debug. + +config STM32_USBHOST_PKTDUMP + bool "Packet Dump Debug" + depends on STM32_COMMON_LEGACY && STM32_USBHOST && STM32_USBHOST && DEBUG_USB_INFO || STM32_COMMON_F7_H7 && USBHOST + ---help--- + Dump all incoming and outgoing USB packets. + +config STM32_USBFS_REGDEBUG + bool "Register-Level Debug" + depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32H5) && STM32_USBFS && STM32_USBFS && DEBUG_USB_INFO + ---help--- + Enable very low-level register access debug. + +config OTG_ID_GPIO_DISABLE + bool "Disable the use of GPIO_OTG_ID pin." + depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_OTGFS || ARCH_CHIP_STM32H7 && (STM32_OTGFS || STM32_OTGHS) + ---help--- + Disables/Enables the use of GPIO_OTG_ID pin. This allows non OTG use + cases to reuse this GPIO pin and ensure it is not set incorrectlty + during OS boot. + +menu "STM32_OTG_HS Configuration" + depends on ARCH_CHIP_STM32F7 && STM32_OTGFSHS + +choice + prompt "ULPI Selection" + default STM32_NO_ULPI + +config STM32_NO_ULPI + bool "No External ULPI" + ---help--- + Select to enable the presence of an external ULPI PHY + +config STM32_EXTERNAL_ULPI + bool "External ULPI" + depends on STM32_HAVE_EXTERNAL_ULPI + ---help--- + Select to enable the presence of an external ULPI PHY + +config STM32_INTERNAL_ULPI + bool "Internal ULPI PHY" + depends on STM32_HAVE_INTERNAL_ULPI + ---help--- + Select to enable the internal ULPI for USB HS + +endchoice # "ULPI Selection" + +endmenu # STM32_OTG_HS Configuration + +menu "OTG_HS Configuration" + depends on ARCH_CHIP_STM32H7 && STM32_OTGHS + +config STM32_OTGHS_FS + bool "OTGHS in FS mode" + default n + +choice + prompt "ULPI Selection" + default STM32_OTGHS_NO_ULPI + +config STM32_OTGHS_NO_ULPI + bool "No External ULPI on board." + ---help--- + Select to indicate that there is no external ULPI PHY. This means + the OTG_HS peripheral must use the internal full-speed PHY and will + be limited to full-speed mode. + +config STM32_OTGHS_EXTERNAL_ULPI + bool "External ULPI" + ---help--- + Select to indicate the presence of an external ULPI PHY and use it. + +endchoice # "ULPI Selection" + +endmenu # OTG_HS Configuration + +menu "OTG Configuration" + depends on ARCH_CHIP_STM32H7 && (STM32_OTGFS || STM32_OTGHS) + +choice + prompt "STM32H7 OTGFS role" + depends on STM32_OTGFS + default STM32_OTGFS_USBDEV if USBDEV + default STM32_OTGFS_HOST if !USBDEV && USBHOST + +config STM32_OTGFS_USBDEV + bool "OTGFS as USBDEV" + depends on USBDEV + +config STM32_OTGFS_HOST + bool "OTGFS as HOST" + depends on USBHOST + +endchoice # "STM32H7 OTGFS role" + +choice + prompt "STM32H7 OTGHS role (only USBDEV supported for now)" + depends on STM32_OTGHS + default STM32_OTGHS_USBDEV if USBDEV + +config STM32_OTGHS_USBDEV + bool "OTGHS as USBDEV" + depends on USBDEV + +endchoice # "STM32H7 OTGHS role" + +endmenu # OTG Configuration + +config STM32_USBHOST + bool "Enable USB Host Support" + depends on STM32_COMMON_LEGACY && (STM32_OTGFS || STM32_OTGHS) + default n + select USBHOST + +menu "USB FS Host Configuration" + depends on STM32_COMMON_LEGACY && STM32_OTGFS && STM32_USBHOST + +config STM32_OTGFS_RXFIFO_SIZE + int "Rx Packet Size" + default 128 + ---help--- + Size of the RX FIFO in 32-bit words. Default 128 (512 bytes) + +config STM32_OTGFS_NPTXFIFO_SIZE + int "Non-periodic Tx FIFO Size" + default 96 + ---help--- + Size of the non-periodic Tx FIFO in 32-bit words. Default 96 (384 bytes) + +config STM32_OTGFS_PTXFIFO_SIZE + int "Periodic Tx FIFO size" + default 128 + ---help--- + Size of the periodic Tx FIFO in 32-bit words. Default 96 (384 bytes) + +config STM32_OTGFS_DESCSIZE + int "Descriptor Size" + default 128 + ---help--- + Maximum size to allocate for descriptor memory descriptor. Default: 128 + +config STM32_OTGFS_SOFINTR + bool "Enable SOF interrupts" + default n + ---help--- + Enable SOF interrupts. Why would you ever want to do that? + +config STM32_OTGFS_VBUS_CONTROL + bool "Enable VBus Control" + default y + ---help--- + Enable VBus control. Used when the board has VBus sensing and + a power switch for the OTG FS USB port. Disable this config + if the board lacks this USB VBus control circuitry. + +endmenu # USB FS Host Configuration + +menu "USB HS Host Configuration" + depends on STM32_COMMON_LEGACY && STM32_OTGHS && STM32_USBHOST + +config STM32_OTGHS_RXFIFO_SIZE + int "Rx Packet Size" + default 128 + ---help--- + Size of the RX FIFO in 32-bit words. Default 128 (512 bytes) + +config STM32_OTGHS_NPTXFIFO_SIZE + int "Non-periodic Tx FIFO Size" + default 96 + ---help--- + Size of the non-periodic Tx FIFO in 32-bit words. Default 96 (384 bytes) + +config STM32_OTGHS_PTXFIFO_SIZE + int "Periodic Tx FIFO size" + default 128 + ---help--- + Size of the periodic Tx FIFO in 32-bit words. Default 96 (384 bytes) + +config STM32_OTGHS_DESCSIZE + int "Descriptor Size" + default 128 + ---help--- + Maximum size to allocate for descriptor memory descriptor. Default: 128 + +config STM32_OTGHS_SOFINTR + bool "Enable SOF interrupts" + default n + ---help--- + Enable SOF interrupts. Why would you ever want to do that? + +config STM32_OTGHS_VBUS_CONTROL + bool "Enable VBus Control" + default y + ---help--- + Enable VBus control. Used when the board has VBus sensing and + a power switch for the OTG HS USB port. Disable this config + if the board lacks this USB VBus control circuitry. + +endmenu # USB HS Host Configuration + +config STM32_CAN1_BAUD + int "CAN1 BAUD" + depends on STM32_CAN1 + default 250000 + ---help--- + CAN1 BAUD rate. Required if CONFIG_STM32_CAN1 is defined. + +config STM32_CAN2_BAUD + int "CAN2 BAUD" + depends on STM32_CAN2 + default 250000 + ---help--- + CAN2 BAUD rate. Required if CONFIG_STM32_CAN2 is defined. + +config STM32_CAN3_BAUD + int "CAN3 BAUD" + depends on STM32_CAN3 + default 250000 + ---help--- + CAN3 BAUD rate. Required if CONFIG_STM32_CAN3 is defined. + +config STM32_CAN_TSEG1 + int "TSEG1 quanta" + depends on STM32_CAN + default 6 + ---help--- + The number of CAN time quanta in segment 1. Default: 6 + +config STM32_CAN_TSEG2 + int "TSEG2 quanta" + depends on STM32_CAN + default 7 + ---help--- + The number of CAN time quanta in segment 2. Default: 7 + +config STM32_CAN_REGDEBUG + bool "CAN Register level debug" + depends on STM32_CAN && DEBUG_CAN_INFO + ---help--- + Output detailed register-level CAN device debug information. + Requires also CONFIG_DEBUG_CAN_INFO. + +config STM32_FDCAN_REGDEBUG + bool "FDCAN register-level debug" + depends on STM32_FDCAN && (DEBUG_CAN_INFO || DEBUG_NET_INFO) + ---help--- + Output detailed register-level CAN device debug information. + Requires also CONFIG_DEBUG_CAN_INFO. + +config STM32_FDCAN_QUEUE_MODE + bool "FDCAN QUEUE mode (vs FIFO mode)" + depends on STM32_FDCAN + +config STM32_FDCAN_LOOPBACK + bool "Enable FDCAN loopback mode" + depends on ARCH_CHIP_STM32H7 && STM32_FDCAN + default n + ---help--- + Enable the FDCAN local loopback mode for testing purposes. + Requires a further choice of internal or external loopback mode. + +choice + prompt "FDCAN Loopback Mode" + depends on STM32_FDCAN_LOOPBACK + default STM32_FDCAN_LOOPBACK_INTERNAL + +config STM32_FDCAN_LOOPBACK_INTERNAL + bool "Internal loopback mode" + ---help--- + Enable internal loopback mode, where both Tx and Rx are + disconnected from the CAN bus. This can be used for a "Hot Selftest", + meaning the FDCAN can be used without affecting a running CAN bus. + + All transmitted frames are treated as received frames and processed + accordingly. + +config STM32_FDCAN_LOOPBACK_EXTERNAL + bool "External loopback mode" + ---help--- + Enable external loopback mode, where the Rx pin is disconnected from + the CAN bus but the Tx pin remains connected. + + All transmitted frames are treated as received frames and processed + accordingly. + +endchoice # FDCAN Loopback Mode + +choice + prompt "FDCAN WorkQueue Selection" + depends on ARCH_CHIP_STM32H7 && STM32_FDCAN + default STM32_FDCAN_LPWORK + +config STM32_FDCAN_LPWORK + bool "Use LP work queue" + ---help--- + Use the low-priority (LP) work queue for reception and transmission + of new frames and for processing of transmission timeouts. + +config STM32_FDCAN_HPWORK + bool "Use HP work queue" + ---help--- + Use the high-priority (HP) work queue for reception and transmission + of new frames and for processing of transmission timeouts. + +endchoice # FDCAN WorkQueue Selection + +if STM32_FDCAN1 + +config STM32_FDCAN1_LOOPBACK + bool "Enable FDCAN1 loopback mode" + ---help--- + Enable the FDCAN1 local loopback mode for testing purposes. + +config STM32_FDCAN1_BITRATE + int "FDCAN1 bitrate" + default 500000 + range 0 1000000 + ---help--- + FDCAN1 bitrate in bits per second. Required if STM32_FDCAN1 is defined. + +config STM32_FDCAN1_AUTO_BIT_TIMING + bool "FDCAN1 automatic bit timing" + depends on ARCH_CHIP_STM32H5 + default y + ---help--- + Automatically determine FDCAN1 bit timing (nominal and data) + based on bitrate. + +if !STM32_FDCAN1_AUTO_BIT_TIMING + +comment "FDCAN1 nominal bit timing" + +config STM32_FDCAN1_NTSEG1 + int "FDCAN1 NTSEG1 (PropSeg + PhaseSeg1)" + default 6 + range 1 256 + ---help--- + The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). + +config STM32_FDCAN1_NTSEG2 + int "FDCAN1 NTSEG2 (PhaseSeg2)" + default 7 + range 1 128 + ---help--- + The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). + +config STM32_FDCAN1_NSJW + int "FDCAN1 synchronization jump width" + default 1 + range 1 128 + ---help--- + The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). + +endif # !STM32_FDCAN1_AUTO_BIT_TIMING + +config STM32_FDCAN1_DBITRATE + int "FDCAN1 data bitrate" + depends on CAN_FD && STM32_FDCAN1_FD_BRS + default 2000000 + ---help--- + FDCAN1 bitrate in bits per second. Required if operating in FD mode with bit rate switching (BRS). + +if CAN_FD && STM32_FDCAN1_FD_BRS && !STM32_FDCAN1_AUTO_BIT_TIMING + +comment "FDCAN1 data bit timing" + +config STM32_FDCAN1_DTSEG1 + int "FDCAN1 DTSEG1 (PropSeg + PhaseSeg1 of data phase)" + default 4 + range 1 31 + ---help--- + The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). + +config STM32_FDCAN1_DTSEG2 + int "FDCAN1 DTSEG2 (PhaseSeg2 of data phase)" + default 4 + range 1 15 + ---help--- + The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). + +config STM32_FDCAN1_DSJW + int "FDCAN1 fast synchronization jump width" + default 2 + range 1 15 + ---help--- + The duration of a synchronization jump is Tcan_clk x DSJW. + +endif # CAN_FD && STM32_FDCAN1_FD_BRS && !STM32_FDCAN1_AUTO_BIT_TIMING + +endif # STM32_FDCAN1 + +if STM32_FDCAN2 + +config STM32_FDCAN2_LOOPBACK + bool "Enable FDCAN2 loopback mode" + ---help--- + Enable the FDCAN2 local loopback mode for testing purposes. + +config STM32_FDCAN2_BITRATE + int "FDCAN2 bitrate" + default 500000 + range 0 1000000 + ---help--- + FDCAN2 bitrate in bits per second. Required if STM32_FDCAN2 is defined. + +config STM32_FDCAN2_AUTO_BIT_TIMING + bool "FDCAN2 automatic bit timing" + depends on ARCH_CHIP_STM32H5 + default y + ---help--- + Automatically determine FDCAN2 bit timing (nominal and data) + based on bitrate. + +if !STM32_FDCAN2_AUTO_BIT_TIMING + +comment "FDCAN2 nominal bit timing" + +config STM32_FDCAN2_NTSEG1 + int "FDCAN2 NTSEG1 (PropSeg + PhaseSeg1)" + default 6 + range 1 256 + ---help--- + The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). + +config STM32_FDCAN2_NTSEG2 + int "FDCAN2 NTSEG2 (PhaseSeg2)" + default 7 + range 1 128 + ---help--- + The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). + +config STM32_FDCAN2_NSJW + int "FDCAN2 synchronization jump width" + default 1 + range 1 128 + ---help--- + The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). + +endif # !STM32_FDCAN2_AUTO_BIT_TIMING + +config STM32_FDCAN2_DBITRATE + int "FDCAN2 data bitrate" + depends on CAN_FD && STM32_FDCAN2_FD_BRS + default 2000000 + ---help--- + FDCAN2 bitrate in bits per second. Required if operating in FD mode with bit rate switching (BRS). + +if CAN_FD && STM32_FDCAN2_FD_BRS && !STM32_FDCAN2_AUTO_BIT_TIMING + +comment "FDCAN2 data bit timing" + +config STM32_FDCAN2_DTSEG1 + int "FDCAN2 DTSEG1 (PropSeg + PhaseSeg1 of data phase)" + default 4 + range 1 31 + ---help--- + The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). + +config STM32_FDCAN2_DTSEG2 + int "FDCAN2 DTSEG2 (PhaseSeg2 of data phase)" + default 4 + range 1 15 + ---help--- + The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). + +config STM32_FDCAN2_DSJW + int "FDCAN2 fast synchronization jump width" + default 2 + range 1 15 + ---help--- + The duration of a synchronization jump is Tcan_clk x DSJW. + +endif # CAN_FD && STM32_FDCAN2_FD_BRS && !STM32_FDCAN2_AUTO_BIT_TIMING + +endif # STM32_FDCAN2 + +if STM32_FDCAN3 + +choice + prompt "FDCAN3 frame format" + default STM32_FDCAN3_ISO11898_1 + +config STM32_FDCAN3_ISO11898_1 + bool "ISO11898-1" + ---help--- + Enable ISO11898-1 frame format + +config STM32_FDCAN3_NONISO_FORMAT + bool "Non ISO" + ---help--- + Enable Non ISO, Bosch CAN FD Specification V1.0 + +endchoice # FDCAN3 frame format + +choice + prompt "FDCAN3 mode" + default STM32_FDCAN3_CLASSIC + +config STM32_FDCAN3_CLASSIC + bool "Classic CAN" + ---help--- + Enable Classic CAN mode + +config STM32_FDCAN3_FD + bool "CAN FD" + depends on CAN_FD || NET_CAN_CANFD + ---help--- + Enable CAN FD mode + +config STM32_FDCAN3_FD_BRS + bool "CAN FD with fast bit rate switching" + depends on CAN_FD || NET_CAN_CANFD + ---help--- + Enable CAN FD mode with fast bit rate switching mode. + +endchoice # FDCAN3 mode + +config STM32_FDCAN3_LOOPBACK + bool "Enable FDCAN3 loopback mode" + default n + ---help--- + Enable the FDCAN3 local loopback mode for testing purposes. + +config STM32_FDCAN3_BITRATE + int "FDCAN3 bitrate" + default 500000 + range 0 1000000 + ---help--- + FDCAN3 bitrate in bits per second. Required if STM32_FDCAN3 is defined. + +comment "FDCAN3 nominal bit timing" + +config STM32_FDCAN3_NTSEG1 + int "FDCAN3 NTSEG1 (PropSeg + PhaseSeg1)" + default 6 + range 1 256 if STM32_STM32G4XXX + ---help--- + The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). + +config STM32_FDCAN3_NTSEG2 + int "FDCAN3 NTSEG2 (PhaseSeg2)" + default 7 + range 1 128 if STM32_STM32G4XXX + ---help--- + The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). + +config STM32_FDCAN3_NSJW + int "FDCAN3 synchronization jump width" + default 1 + range 1 128 if STM32_STM32G4XXX + ---help--- + The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). + +config STM32_FDCAN3_DBITRATE + int "FDCAN3 data bitrate" + depends on CAN_FD && STM32_FDCAN3_FD_BRS + default 2000000 + ---help--- + FDCAN3 bitrate in bits per second. Required if operating in FD mode with bit rate switching (BRS). + +if CAN_FD && STM32_FDCAN3_FD_BRS + +comment "FDCAN3 data bit timing" + +config STM32_FDCAN3_DTSEG1 + int "FDCAN3 DTSEG1 (PropSeg + PhaseSeg1 of data phase)" + default 4 + range 1 31 if STM32_STM32G4XXX + ---help--- + The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). + +config STM32_FDCAN3_DTSEG2 + int "FDCAN3 DTSEG2 (PhaseSeg2 of data phase)" + default 4 + range 1 15 if STM32_STM32G4XXX + ---help--- + The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). + +config STM32_FDCAN3_DSJW + int "FDCAN3 fast synchronization jump width" + default 2 + range 1 15 if STM32_STM32G4XXX + ---help--- + The duration of a synchronization jump is Tcan_clk x DSJW. + +endif # CAN_FD && STM32_FDCAN3_FD_BRS + +endif # STM32_FDCAN3 + +if STM32_LTDC + +config STM32_LTDC_BACKLIGHT + bool "Backlight support" + default y + +config STM32_LTDC_DEFBACKLIGHT + hex "Default backlight level" + default 0xf0 + +config STM32_LTDC_BACKCOLOR + hex "Background color" + default 0x0 + ---help--- + This is the background color that will be used as the LTDC + background layer color. It is an RGB888 format value. + +config STM32_LTDC_DITHER + bool "Dither support" + +config STM32_LTDC_FB_DOUBLE_BUFFER + bool "Enable double buffering" + depends on ARCH_CHIP_STM32H7 + default n + ---help--- + Enable double buffering to allow updates to the framebuffer while + the display is being refreshed. This configuration requires two + framebuffers: one active and one inactive. When the display + refreshes, the active and inactive framebuffers are swapped, + enabling smooth and flicker-free updates. + +if STM32_LTDC_DITHER + +config STM32_LTDC_DITHER_RED + int "Dither red width" + range 0 7 + default 2 + ---help--- + This is the dither red width. + +config STM32_LTDC_DITHER_GREEN + int "Dither green width" + range 0 7 + default 2 + ---help--- + This is the dither green width. + +config STM32_LTDC_DITHER_BLUE + int "Dither blue width" + range 0 7 + default 2 + ---help--- + This is the dither blue width. + +endif # STM32_LTDC_DITHER + +config STM32_LTDC_FB_BASE + hex "Framebuffer memory start address" + default 0 + ---help--- + If you are using the LTDC, then you must provide the address + of the start of the framebuffer. This address will typically + be in the SRAM or SDRAM memory region of the FSMC/FMC. + +config STM32_LTDC_FB_SIZE + int "Framebuffer memory size (bytes)" + default 0 + ---help--- + Must be the whole size of the active LTDC layer. + +config STM32_LTDC_L1_CHROMAKEYEN + bool "Enable chromakey support for layer 1" + default y + +config STM32_LTDC_L1_CHROMAKEY + hex "Layer L1 initial chroma key" + default 0x00000000 + +config STM32_LTDC_L1_COLOR + hex "Layer L1 default color" + default 0x00000000 + +config STM32_LTDC_L2 + bool "Enable Layer 2 support" + default y + +if STM32_LTDC_L2 + +config STM32_LTDC_L2_COLOR + hex "Layer L2 default color" + default 0x00000000 + +config STM32_LTDC_L2_CHROMAKEYEN + bool "Enable chromakey support for layer 2" + default y + +config STM32_LTDC_L2_CHROMAKEY + hex "Layer L2 initial chroma key" + default 0x00000000 + +endif # STM32_LTDC_L2 + +config STM32_FB_CMAP + bool "Color map support" + default y + select FB_CMAP + ---help--- + Enabling color map support is necessary for LTDC L8 format. + +config STM32_FB_TRANSPARENCY + bool "Transparency color map support" + depends on STM32_FB_CMAP + default y + select FB_TRANSPARENCY + ---help--- + Enabling transparency color map support is necessary for LTDC L8 format. + +config STM32_LTDC_REGDEBUG + bool "LTDC Register level debug" + depends on (STM32_COMMON_LEGACY && DEBUG_INFO && DEBUG_LCD) || STM32_COMMON_F7_H7 + ---help--- + Output detailed register-level LTDC device debug information. + +endif # STM32_LTDC + +if STM32_DMA2D + +config STM32_DMA2D_NLAYERS + int "Number DMA2D overlays" + default 1 + range 1 256 + ---help--- + Number of supported DMA2D layer. + +config STM32_DMA2D_LAYER_SHARED + bool "Overlays shared memory region" + ---help--- + Several overlays can share the same memory region. + Setup a whole memory area (usually multiple size of the visible screen) + allows image preprocessing before they become visible by blit operation. + +config STM32_DMA2D_LAYER_PPLINE + int "Pixel per line" + default 1 + range 1 65535 + ---help--- + If you are using the DMA2D, then you must provide the pixel per line or + width of the overlay. + +config STM32_DMA2D_FB_BASE + hex "Framebuffer memory start address" + default 0 + ---help--- + If you are using the DMA2D, then you must provide the address + of the start of the DMA2D overlays framebuffer. This address will typically + be in the SRAM or SDRAM memory region of the FSMC/FMC. + +config STM32_DMA2D_FB_SIZE + int "Framebuffer memory size (bytes)" + default 0 + ---help--- + Must be the whole size of all DMA2D overlays. + +config STM32_DMA2D_L8 + bool "8 bpp L8 (8-bit CLUT)" + depends on STM32_FB_CMAP && STM32_LTDC_L1_L8 + default y + +config STM32_DMA2D_AL44 + bool "8 bpp AL44 (4-bit alpha + 4-bit CLUT)" + depends on STM32_FB_CMAP && STM32_LTDC_L1_AL44 + default y + +config STM32_DMA2D_AL88 + bool "16 bpp AL88 (8-bit alpha + 8-bit CLUT)" + depends on STM32_FB_CMAP && STM32_LTDC_L1_AL88 + default y + +config STM32_DMA2D_RGB565 + bool "16 bpp RGB 565" + depends on STM32_LTDC_L1_RGB565 + default y + +config STM32_DMA2D_ARGB4444 + bool "16 bpp ARGB 4444" + depends on STM32_LTDC_L1_ARGB4444 + default y + +config STM32_DMA2D_ARGB1555 + bool "16 bpp ARGB 1555" + depends on STM32_LTDC_L1_ARGB15555 + default y + +config STM32_DMA2D_RGB888 + bool "24 bpp RGB 888" + depends on STM32_LTDC_L1_RGB888 + default y + +config STM32_DMA2D_ARGB8888 + bool "32 bpp ARGB 8888" + depends on STM32_LTDC_L1_ARGB8888 + default y + +config STM32_DMA2D_REGDEBUG + bool "DMA2D Register level debug" + depends on DEBUG_INFO && DEBUG_LCD + ---help--- + Output detailed register-level DMA2D device debug information. + +endif # STM32_DMA2D + +config STM32_QENCODER_DISABLE_EXTEND16BTIMERS + bool "Disable QEncoder timers extension from 16-bit to 32-bit" + depends on STM32_QENCODER_16BIT_CAPABLE + ---help--- + Disable the extension of 16-bit timers to 32-bit via interrupt-based + overflow tracking. When enabled, timers will use their native hardware + counter width (16-bit or 32-bit). This reduces interrupt overhead but + limits the position range for 16-bit timers. + +config STM32_QENCODER_INDEX_PIN + bool "Enable QEncoder timers support for index pin" + depends on STM32_QENCODER_16BIT_CAPABLE + ---help--- + Enable support for quadrature encoder index pin. The index pin can be + used to reset the encoder position to a known value when the index + pulse is detected. + +config STM32_TIM1_QE + bool "TIM1 QE" + depends on (STM32_QENCODER_MAIN && STM32_TIM1) || (STM32_COMMON_F0_L0_G0_C0 && STM32_TIM1) + select STM32_QE if STM32_QENCODER_STM32 && STM32_TIM1 + ---help--- + Reserve TIM1 for use by QEncoder. + +config STM32_TIM1_QEPSC + int "TIM1 QE pulse prescaler" + depends on (STM32_QENCODER_MAIN || STM32_QENCODER_F0) && STM32_TIM1_QE + default 1 + ---help--- + This prescaler divides the number of recorded encoder pulses, + limiting the count rate at the expense of resolution. + +config STM32_TIM2_QE + bool "TIM2 QE" + depends on (STM32_QENCODER_MAIN && STM32_TIM2) || (STM32_COMMON_F0_L0_G0_C0 && STM32_TIM2) + select STM32_QE if STM32_QENCODER_STM32 && STM32_TIM2 + ---help--- + Reserve TIM2 for use by QEncoder. + +config STM32_TIM2_QEPSC + int "TIM2 QE pulse prescaler" + depends on (STM32_QENCODER_MAIN || STM32_QENCODER_F0) && STM32_TIM2_QE + default 1 + ---help--- + This prescaler divides the number of recorded encoder pulses, + limiting the count rate at the expense of resolution. + +config STM32_TIM3_QE + bool "TIM3 QE" + depends on (STM32_QENCODER_MAIN && STM32_TIM3) || (STM32_COMMON_F0_L0_G0_C0 && STM32_TIM3) + select STM32_QE if STM32_QENCODER_STM32 && STM32_TIM3 + ---help--- + Reserve TIM3 for use by QEncoder. + +config STM32_TIM3_QEPSC + int "TIM3 QE pulse prescaler" + depends on (STM32_QENCODER_MAIN || STM32_QENCODER_F0) && STM32_TIM3_QE + default 1 + ---help--- + This prescaler divides the number of recorded encoder pulses, + limiting the count rate at the expense of resolution. + +config STM32_TIM4_QE + bool "TIM4 QE" + depends on (STM32_QENCODER_MAIN && STM32_TIM4) || (STM32_COMMON_F0_L0_G0_C0 && STM32_TIM4) + select STM32_QE if STM32_QENCODER_STM32 && STM32_TIM4 + ---help--- + Reserve TIM4 for use by QEncoder. + +config STM32_TIM4_QEPSC + int "TIM4 QE pulse prescaler" + depends on (STM32_QENCODER_MAIN || STM32_QENCODER_F0) && STM32_TIM4_QE + default 1 + ---help--- + This prescaler divides the number of recorded encoder pulses, + limiting the count rate at the expense of resolution. + +config STM32_TIM5_QE + bool "TIM5 QE" + depends on STM32_QENCODER_MAIN && STM32_TIM5 + select STM32_QE if STM32_QENCODER_STM32 && STM32_TIM5 + ---help--- + Reserve TIM5 for use by QEncoder. + +config STM32_TIM5_QEPSC + int "TIM5 QE pulse prescaler" + depends on STM32_QENCODER_MAIN && STM32_TIM5_QE + default 1 + ---help--- + This prescaler divides the number of recorded encoder pulses, + limiting the count rate at the expense of resolution. + +config STM32_TIM8_QE + bool "TIM8 QE" + depends on STM32_QENCODER_MAIN && STM32_TIM8 + select STM32_QE if STM32_QENCODER_STM32 && STM32_TIM8 + ---help--- + Reserve TIM8 for use by QEncoder. + +config STM32_TIM8_QEPSC + int "TIM8 QE pulse prescaler" + depends on STM32_QENCODER_MAIN && STM32_TIM8_QE + default 1 + ---help--- + This prescaler divides the number of recorded encoder pulses, + limiting the count rate at the expense of resolution. + +config STM32_QENCODER_FILTER + bool "Enable filtering on STM32 QEncoder input" + depends on STM32_QENCODER_MAIN || STM32_QENCODER_F0 + default y + ---help--- + Enable input filtering on quadrature encoder channels to reduce noise. + +menuconfig STM32_FOC + bool "STM32 lower-half FOC support" + depends on STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7 + select ARCH_IRQPRIO + select STM32_ADC + select STM32_PWM_MULTICHAN + select STM32_PWM_LL_OPS + select STM32_ADC_LL_OPS + select STM32_ADC_CHANGE_SAMPLETIME + select STM32_ADC_NO_STARTUP_CONV + +config STM32_FOC_FOC0 + bool "FOC0 device (TIM1 for PWM modulation)" + depends on (STM32_COMMON_LEGACY && STM32_FOC && STM32_HAVE_TIM1) || (ARCH_CHIP_STM32F7 && STM32_FOC) + select STM32_FOC_USE_TIM1 + ---help--- + Enable support for FOC0 device that uses TIM1 for PWM modulation + +config STM32_FOC_FOC1 + bool "FOC1 device (TIM8 for PWM modulation)" + depends on (STM32_COMMON_LEGACY && STM32_FOC && STM32_HAVE_TIM8) || (ARCH_CHIP_STM32F7 && STM32_FOC) + select STM32_FOC_USE_TIM8 + ---help--- + Enable support for FOC1 device that uses TIM8 for PWM modulation + +config STM32_FOC_HAS_PWM_COMPLEMENTARY + bool "FOC PWM has complementary outputs" + depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_FOC + ---help--- + Enable complementary outputs for the FOC PWM (sometimes called 6-PWM mode) + +# hidden variables and automatic configuration + +config STM32_FOC_USE_TIM1 + bool + select STM32_TIM1 + select STM32_TIM1_PWM + select STM32_TIM1_CHANNEL1 + select STM32_TIM1_CHANNEL2 + select STM32_TIM1_CHANNEL3 + select STM32_TIM1_CHANNEL4 if STM32_FOC_ADC_CCR4 + select STM32_TIM1_CH1OUT + select STM32_TIM1_CH2OUT + select STM32_TIM1_CH3OUT + select STM32_TIM1_CH4OUT if STM32_FOC_ADC_CCR4 + select STM32_TIM1_CH1NOUT if STM32_FOC_HAS_PWM_COMPLEMENTARY + select STM32_TIM1_CH2NOUT if STM32_FOC_HAS_PWM_COMPLEMENTARY + select STM32_TIM1_CH3NOUT if STM32_FOC_HAS_PWM_COMPLEMENTARY + ---help--- + The TIM1 generates PWM for the FOC + +config STM32_FOC_USE_TIM8 + bool + select STM32_TIM8 + select STM32_TIM8_PWM + select STM32_TIM8_CHANNEL1 + select STM32_TIM8_CHANNEL2 + select STM32_TIM8_CHANNEL3 + select STM32_TIM8_CHANNEL4 if STM32_FOC_ADC_CCR4 + select STM32_TIM8_CH1OUT + select STM32_TIM8_CH2OUT + select STM32_TIM8_CH3OUT + select STM32_TIM8_CH4OUT if STM32_FOC_ADC_CCR4 + select STM32_TIM8_CH1NOUT if STM32_FOC_HAS_PWM_COMPLEMENTARY + select STM32_TIM8_CH2NOUT if STM32_FOC_HAS_PWM_COMPLEMENTARY + select STM32_TIM8_CH3NOUT if STM32_FOC_HAS_PWM_COMPLEMENTARY + ---help--- + The TIM8 generates PWM for the FOC + +config STM32_FOC_USE_ADC1 + bool + select STM32_ADC1 + select STM32_ADC1_SCAN if ARCH_CHIP_STM32F7 || STM32_HAVE_IP_ADC_V1 + select STM32_ADC1_JEXTSEL + +config STM32_FOC_USE_ADC2 + bool + select STM32_ADC2 + select STM32_ADC2_SCAN if ARCH_CHIP_STM32F7 || STM32_HAVE_IP_ADC_V1 + select STM32_ADC2_JEXTSEL + +config STM32_FOC_USE_ADC3 + bool + select STM32_ADC3 + select STM32_ADC3_SCAN if ARCH_CHIP_STM32F7 || STM32_HAVE_IP_ADC_V1 + select STM32_ADC3_JEXTSEL + +config STM32_PROGMEM + bool "Flash PROGMEM support" + depends on STM32_COMMON_F0_L0_G0_C0 && ARCH_HAVE_PROGMEM || STM32_COMMON_F7_H7_H5 + select MTD if STM32_COMMON_F0_L0_G0_C0 && ARCH_HAVE_PROGMEM + select MTD_PROGMEM if STM32_COMMON_F0_L0_G0_C0 && ARCH_HAVE_PROGMEM + ---help--- + Add progmem support, start block and end block options are provided to + obtain a uniform flash memory mapping. + +config STM32_HAVE_HSI48 + bool + +config STM32_HAVE_LCD + bool + +config STM32_HAVE_DMA2 + bool + +config STM32_TIM16_CH1NOUT + bool "TIM16 Channel 1 Complementary Output" + depends on (STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_L4_L5_U5) && STM32_TIM16_PWM && STM32_PWM_MULTICHAN && STM32_TIM16_CHANNEL1 && STM32_TIM16_CH1OUT + ---help--- + Enables channel 1 complementary output. + +config STM32_TIM17_CH1NOUT + bool "TIM17 Channel 1 Complementary Output" + depends on (STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_L4_L5_U5) && STM32_TIM17_PWM && STM32_PWM_MULTICHAN && STM32_TIM17_CHANNEL1 && STM32_TIM17_CH1OUT + ---help--- + Enables channel 1 complementary output. + +config STM32_TIM15_ADC + bool "TIM15 ADC" + depends on (STM32_COMMON_F0_L0_G0_C0 || ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM15 && STM32_ADC + ---help--- + Reserve timer 1 for use by ADC + +config USART1_RXFIFO_THRES + int "USART1 Rx FIFO Threshold" + depends on (STM32_COMMON_F0_L0_G0_C0 && STM32_USART && STM32_USART1_SERIALDRIVER && STM32_HAVE_IP_USART_V2) || (ARCH_CHIP_STM32H7 && STM32_USART && STM32_USART1) + default 3 + range 0 5 + ---help--- + Select the Rx FIFO threshold: + + 0 -> 1/8 full + 1 -> 1/4 full + 2 -> 1/2 full + 3 -> 3/4 full + 4 -> 7/8 full + 5 -> Full + + Higher values mean lower interrupt rates and better CPU performance. + Lower values may be needed at high BAUD rates to prevent Rx data + overrun errors. + +config USART2_RXFIFO_THRES + int "USART2 Rx FIFO Threshold" + depends on (STM32_COMMON_F0_L0_G0_C0 && STM32_USART && STM32_USART2_SERIALDRIVER && STM32_HAVE_IP_USART_V2) || (ARCH_CHIP_STM32H7 && STM32_USART && STM32_USART2) + default 3 + range 0 5 + ---help--- + Select the Rx FIFO threshold: + + 0 -> 1/8 full + 1 -> 1/4 full + 2 -> 1/2 full + 3 -> 3/4 full + 4 -> 7/8 full + 5 -> Full + + Higher values mean lower interrupt rates and better CPU performance. + Lower values may be needed at high BAUD rates to prevent Rx data + overrun errors. + +config STM32_SPI1_COMMTYPE + int "SPI1 Operation mode" + depends on (STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_H7_H5) && STM32_SPI && STM32_SPI1 + default 0 + range 0 3 + ---help--- + Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3) + +config STM32_SPI2_COMMTYPE + int "SPI2 Operation mode" + depends on (STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_H7_H5) && STM32_SPI && STM32_SPI2 + default 0 + range 0 3 + ---help--- + Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3) + +config STM32_SPI3_COMMTYPE + int "SPI3 Operation mode" + depends on (STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_H7_H5) && STM32_SPI && STM32_SPI3 + default 0 + range 0 3 + ---help--- + Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3) + +config STM32_IO_CONFIG_R + bool + select STM32_GPIO_HAVE_PORTD if ARCH_CHIP_STM32WB + select STM32_GPIO_HAVE_PORTE if ARCH_CHIP_STM32WB + +config STM32_IO_CONFIG_V + bool + select STM32_GPIO_HAVE_PORTD if ARCH_CHIP_STM32WB + select STM32_GPIO_HAVE_PORTE if ARCH_CHIP_STM32WB + +config STM32_IO_CONFIG_I + bool + +config STM32_IO_CONFIG_Z + bool + +config STM32_IO_CONFIG_B + bool + +config STM32_IO_CONFIG_A + bool + +config STM32_HAVE_PHY_POLLED + bool + +config STM32_HAVE_DCMI + bool + +config STM32_HAVE_DMA2D + bool + +config STM32_HAVE_HASH + bool + +config STM32_HAVE_DFSDM1 + bool + +config STM32_HAVE_SAI1 + bool + +config STM32_HAVE_SAI2 + bool + +config STM32_SAI + bool + +menu "SDIO Configuration" + depends on STM32_COMMON_LEGACY && STM32_SDIO + +config STM32_SDIO_CARD + bool "SDIO Card support" + default n + ---help--- + Build in additional support needed only for SDIO cards (vs. SD + memory cards) + +config STM32_SDIO_PULLUP + bool "Enable internal Pull-Ups" + default n + ---help--- + If you are using an external SDCard module that does not have the + pull-up resistors for the SDIO interface (like the Gadgeteer SD Card + Module) then enable this option to activate the internal pull-up + resistors. + +config STM32_SDIO_DMA + bool "Support DMA data transfers" + default STM32_DMA2 + select SDIO_DMA + depends on STM32_DMA2 + ---help--- + Support DMA data transfers. Requires STM32_SDIO and config STM32_DMA2. + +config STM32_SDIO_DMAPRIO + hex "SDIO DMA priority" + default 0x00001000 if STM32_STM32F10XX + default 0x00010000 if !STM32_STM32F10XX + ---help--- + Select SDIO DMA priority. + + For STM32 F1 family, options are: 0x00000000 low, 0x00001000 medium, + 0x00002000 high, 0x00003000 very high. Default: medium. + + For other STM32's, options are: 0x00000000 low, 0x00010000 medium, + 0x00020000 high, 0x00030000 very high. Default: medium. + +config STM32_SDIO_WIDTH_D1_ONLY + bool "Use D1 only" + default n + ---help--- + Select 1-bit transfer mode. Default: 4-bit transfer mode. + +endmenu # SDIO Configuration + +config STM32_SDMMC + bool + +config STM32_DFSDM1 + bool "DFSDM1" + depends on (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_HAVE_DFSDM1 + select ARCH_HAVE_DFSDM1 if ARCH_CHIP_STM32F7 && STM32_HAVE_DFSDM1 + +config STM32_I2C4 + bool "I2C4" + depends on STM32_HAVE_I2C4 + select STM32_I2C + +config STM32_QUADSPI + bool "QuadSPI" + depends on STM32_COMMON_F7_H7 + +config STM32_USBDEV_REGDEBUG + bool "OTG USBDEV REGDEBUG" + depends on STM32_COMMON_F7_H7 && USBDEV + +config STM32_SAI1 + bool "SAI1" + depends on STM32_HAVE_SAI1 + +config STM32_SAI1_A + bool "SAI1 Block A" + depends on (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_SAI1 + select AUDIO + select I2S + select SCHED_HPWORK + select STM32_SAI + +config STM32_SAI1_B + bool "SAI1 Block B" + depends on (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_SAI1 + select AUDIO + select I2S + select SCHED_HPWORK + select STM32_SAI + +config STM32_SAI2 + bool "SAI2" + depends on STM32_HAVE_SAI2 + +config STM32_SAI2_A + bool "SAI2 Block A" + depends on (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_SAI2 + select AUDIO + select I2S + select SCHED_HPWORK + select STM32_SAI + +config STM32_SAI2_B + bool "SAI2 Block B" + depends on (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_SAI2 + select AUDIO + select I2S + select SCHED_HPWORK + select STM32_SAI + +config STM32_SDMMC1 + bool "SDMMC1" + depends on STM32_HAVE_SDMMC1 + select STM32_SDMMC if !ARCH_CHIP_STM32U5 + select ARCH_HAVE_SDIO if !ARCH_CHIP_STM32U5 + select ARCH_HAVE_SDIOWAIT_WRCOMPLETE if !ARCH_CHIP_STM32U5 + select ARCH_HAVE_SDIO_PREFLIGHT if !ARCH_CHIP_STM32U5 + select SDIO_BLOCKSETUP if STM32_COMMON_F7_H7 + select SCHED_HPWORK if ARCH_CHIP_STM32L4 + select STM32_SAI1PLL if ARCH_CHIP_STM32L4 + +config STM32_SDMMC2 + bool "SDMMC2" + depends on STM32_HAVE_SDMMC2 + select STM32_SDMMC if !ARCH_CHIP_STM32U5 + select ARCH_HAVE_SDIO if !ARCH_CHIP_STM32U5 + select ARCH_HAVE_SDIOWAIT_WRCOMPLETE if !ARCH_CHIP_STM32U5 + select ARCH_HAVE_SDIO_PREFLIGHT if !ARCH_CHIP_STM32U5 + select SDIO_BLOCKSETUP if !ARCH_CHIP_STM32U5 + +config STM32_SDMMC_IDMA + bool "Support IDMA data transfers" + depends on ARCH_CHIP_STM32H7 && STM32_SDMMC + default y + select SDIO_DMA + ---help--- + Support IDMA data transfers. + +config STM32_USART_INVERT + bool "Signal Invert Support" + depends on STM32_USART + ---help--- + Enable signal inversion UART support. The option enables support for the + TIOCSINVERT ioctl in the STM32F7 serial driver. + +config STM32_USART_SWAP + bool "Swap RX/TX pins support" + depends on STM32_USART + ---help--- + Enable RX/TX pin swapping support. The option enables support for the + TIOCSSWAP ioctl in the STM32F7 serial driver. + +config STM32_QSPI_FLASH_SIZE + int "Size of attached serial flash, bytes" + depends on STM32_QUADSPI || STM32_QSPI || STM32_QSPI1 + default 16777216 + range 1 2147483647 if ARCH_CHIP_STM32L4 && STM32_QSPI + range 1 2147483648 if STM32_COMMON_F7_H7 && STM32_QUADSPI || ARCH_CHIP_STM32H5 && STM32_QSPI1 + ---help--- + The STM32F7 QSPI peripheral requires the size of the Flash be specified + +config STM32_QSPI_FIFO_THESHOLD + int "Number of bytes before asserting FIFO threshold flag" + depends on STM32_QUADSPI || STM32_QSPI || STM32_QSPI1 + default 4 + range 1 16 if STM32_COMMON_F7_H7 && STM32_QUADSPI || ARCH_CHIP_STM32L4 && STM32_QSPI + range 1 32 if ARCH_CHIP_STM32H5 && STM32_QSPI1 + ---help--- + The STM32F7 QSPI peripheral requires that the FIFO threshold be specified + I would leave it at the default value of 4 unless you know what you are doing. + +config STM32_QSPI_CSHT + int "Number of cycles Chip Select must be inactive between transactions" + depends on STM32_QUADSPI || STM32_QSPI || STM32_QSPI1 + default 5 if ARCH_CHIP_STM32H5 && STM32_QSPI1 + default 1 + range 1 8 if STM32_COMMON_F7_H7 && STM32_QUADSPI || ARCH_CHIP_STM32L4 && STM32_QSPI + range 1 64 if ARCH_CHIP_STM32H5 && STM32_QSPI1 + ---help--- + The STM32F7 QSPI peripheral requires that it be specified the minimum number + of AHB cycles that Chip Select be held inactive between transactions. + +config STM32_QSPI_DMATHRESHOLD + int "QSPI DMA threshold" + depends on (STM32_QUADSPI || STM32_QSPI || STM32_QSPI1) && STM32_QSPI_DMA + default 4 + ---help--- + When QSPI DMA is enabled, small DMA transfers will still be performed + by polling logic. This value is the threshold below which transfers + will still be performed by conventional register status polling. + +config STM32_QSPI_DMADEBUG + bool "QSPI DMA transfer debug" + depends on (STM32_QUADSPI || STM32_QSPI || STM32_QSPI1) && STM32_QSPI_DMA && DEBUG_SPI && DEBUG_DMA + ---help--- + Enable special debug instrumentation to analyze QSPI DMA data transfers. + This logic is as non-invasive as possible: It samples DMA + registers at key points in the data transfer and then dumps all of + the registers at the end of the transfer. + +config STM32_QSPI_REGDEBUG + bool "QSPI Register level debug" + depends on STM32_COMMON_F7_H7 && STM32_QUADSPI && DEBUG_SPI_INFO || ARCH_CHIP_STM32L4 && STM32_QSPI && DEBUG_SPI_INFO || ARCH_CHIP_STM32H5 && STM32_QSPI1 && DEBUG_SPI_INFO + ---help--- + Output detailed register-level QSPI device debug information. + Requires also CONFIG_DEBUG_SPI_INFO. + +config STM32_SPI6_DMA_BUFFER + int "SPI6 DMA buffer size" + depends on (STM32_COMMON_F7_H7_H5) && STM32_SPI6_DMA + default 0 + ---help--- + Add a properly aligned DMA buffer for RX and TX DMA for SPI6. + +if STM32_SDMMC + +config STM32_SDMMC_XFRDEBUG + bool "SDMMC transfer debug" + depends on DEBUG_FS_INFO + ---help--- + Enable special debug instrumentation analyze SDMMC data transfers. + This logic is as non-invasive as possible: It samples SDMMC + registers at key points in the data transfer and then dumps all of + the registers at the end of the transfer. If DEBUG_DMA is also + enabled, then DMA register will be collected as well. Requires also + DEBUG_FS and CONFIG_DEBUG_INFO. + +config STM32_SDMMC_DMA + bool "Support DMA data transfers" + depends on (ARCH_CHIP_STM32F7 || STM32_COMMON_L4_L5_U5) && STM32_SDMMC && STM32_DMA + select SDIO_DMA + ---help--- + Support DMA data transfers. + +config STM32_SDMMC1_DMAPRIO + hex "SDMMC1 DMA priority" + depends on (ARCH_CHIP_STM32F7 || STM32_COMMON_L4_L5_U5) && STM32_SDMMC1 + default 0x00010000 if ARCH_CHIP_STM32F7 + default 0x00001000 + ---help--- + Select SDMMC1 DMA priority. + + Options are: 0x00000000 low, 0x00010000 medium, + 0x00020000 high, 0x00030000 very high. Default: medium. + +config SDMMC1_WIDTH_D1_ONLY + bool "Use D1 only on SDMMC1" + depends on STM32_SDMMC1 + ---help--- + Select 1-bit transfer mode. Default: 4-bit transfer mode. + +config SDMMC1_SDIO_MODE + bool "SDIO Card Support" + depends on STM32_COMMON_F7_H7 && STM32_SDMMC && STM32_SDMMC1 + ---help--- + Build in additional support needed only for SDIO cards (vs. SD + memory cards) + +config SDMMC1_SDIO_PULLUP + bool "Enable internal Pull-Ups" + depends on STM32_COMMON_F7_H7 && STM32_SDMMC && STM32_SDMMC1 + ---help--- + If you are using an external SDCard module that does not have the + pull-up resistors for the SDIO interface (like the Gadgeteer SD Card + Module) then enable this option to activate the internal pull-up + resistors. + +config SDMMC2_WIDTH_D1_ONLY + bool "Use D1 only on SDMMC2" + depends on STM32_COMMON_F7_H7 && STM32_SDMMC && STM32_SDMMC2 + ---help--- + Select 1-bit transfer mode. Default: 4-bit transfer mode. + +config SDMMC2_SDIO_MODE + bool "SDIO Card Support" + depends on STM32_COMMON_F7_H7 && STM32_SDMMC && STM32_SDMMC2 + ---help--- + Build in additional support needed only for SDIO cards (vs. SD + memory cards) + +config SDMMC2_SDIO_PULLUP + bool "Enable internal Pull-Ups" + depends on STM32_COMMON_F7_H7 && STM32_SDMMC && STM32_SDMMC2 + ---help--- + If you are using an external SDCard module that does not have the + pull-up resistors for the SDIO interface (like the Gadgeteer SD Card + Module) then enable this option to activate the internal pull-up + resistors. + +endif # STM32_SDMMC + +config STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY + bool "Automatically boost the LSE oscillator drive capability level until it starts-up" + depends on (STM32_COMMON_F7_H7 || STM32_COMMON_L5_U5) && STM32_RTC && STM32_RTC_LSECLOCK + ---help--- + This will cycle through the values from low to high. To avoid + damaging the crystal. We want to use the lowest setting that gets + the OSC running. See app note AN2867 + + 0 = Low drive capability (default) + 1 = Medium high drive capability + 2 = Medium low drive capability + 3 = High drive capability + +config STM32_RTC_LSECLOCK_START_DRV_CAPABILITY + int "LSE oscillator drive capability level at LSE start-up" + depends on ((STM32_COMMON_F7_H7 || STM32_COMMON_L5_U5) && !STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32WB) && STM32_RTC && STM32_RTC_LSECLOCK + default 0 + range 0 3 if ((STM32_COMMON_F7_H7 || STM32_COMMON_L5_U5) && !STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY) || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32WB + ---help--- + 0 = Low drive capability (default) + 1 = Medium high drive capability + 2 = Medium low drive capability + 3 = High drive capability + +config STM32_RTC_LSECLOCK_RUN_DRV_CAPABILITY + int "LSE oscillator drive capability level after LSE start-up" + depends on ((STM32_COMMON_F7_H7 || STM32_COMMON_L5_U5) && !STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32WB) && STM32_RTC && STM32_RTC_LSECLOCK && !STM32_COMMON_L5_U5 + default 0 + range 0 3 if ((STM32_COMMON_F7_H7 || STM32_COMMON_L5_U5) && !STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY) || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32WB + ---help--- + 0 = Low drive capability (default) + 1 = Medium high drive capability + 2 = Medium low drive capability + 3 = High drive capability + +config STM32_CUSTOM_CLOCKCONFIG + bool "Custom clock configuration" + depends on STM32_COMMON_F7_H7 + ---help--- + Enables special, board-specific STM32 clock configuration. + +config STM32_DTCMEXCLUDE + bool "Exclude DTCM SRAM from the heap" + depends on STM32_COMMON_F7_H7 && ARMV7M_HAVE_DTCM + default LIBC_ARCH_ELF + ---help--- + Exclude DTCM SRAM from the HEAP because it appears to be impossible + to execute ELF modules from DTCM RAM (REVISIT!). + +config STM32_DTCM_PROCFS + bool "DTCM SRAM PROCFS support" + depends on STM32_COMMON_F7_H7 && ARMV7M_DTCM && FS_PROCFS + ---help--- + Select to build in support for /proc/dtcm. Reading from /proc/dtcm + will provide statistics about DTCM memory use similar to what you + would get from mallinfo() for the user heap. + +config STM32_DMACAPABLE_ASSUME_CACHE_ALIGNED + bool "Do not disqualify DMA capability based on cache alignment" + depends on STM32_COMMON_F7_H7 && STM32_DMACAPABLE && ARMV7M_DCACHE && !ARMV7M_DCACHE_WRITETHROUGH + ---help--- + This option configures the stm32_dmacapable to not disqualify + DMA operations on memory that is not dcache aligned based solely + on the starting address and byte count. + + Use this when ALL buffer extents are known to be aligned, but the + the count does not use the complete buffer. + +config STM32_PHY_POLLING + bool "Support network monitoring by polling the PHY" + depends on (STM32_COMMON_F7_H7_H5) && STM32_ETHMAC && STM32_HAVE_PHY_POLLED + select ARCH_PHY_POLLED + ---help--- + Some boards may not have an interrupt connected to the PHY. + This option allows the network monitor to be used by polling the + the PHY for status. + +config STM32_LTDC_USE_DSI + bool "Use DSI as display connection" + depends on STM32_COMMON_F7_H7 && STM32_LTDC && STM32_DSIHOST + ---help--- + Select this if your display is connected via DSI. + Deselect option if your display is connected via digital + RGB+HSYNC+VSYNC + +config STM32_HAVE_SMPS + bool + +config STM32_HAVE_ETHERNET + bool + +config STM32_LPTIM + bool + +config STM32_LPTIM2 + bool "LPTIM2" + depends on ARCH_CHIP_STM32H7 || ARCH_CHIP_STM32U5 || ARCH_CHIP_STM32WB || ARCH_CHIP_STM32L4 && STM32_HAVE_LPTIM2 + select STM32_LPTIM if ARCH_CHIP_STM32H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32WB + +config STM32_LPTIM3 + bool "LPTIM3" + depends on ARCH_CHIP_STM32H7 || ARCH_CHIP_STM32U5 + select STM32_LPTIM if ARCH_CHIP_STM32H7 + +config STM32_LPTIM4 + bool "LPTIM4" + depends on ARCH_CHIP_STM32H7 || ARCH_CHIP_STM32U5 + select STM32_LPTIM if ARCH_CHIP_STM32H7 + +config STM32_LPTIM5 + bool "LPTIM5" + depends on ARCH_CHIP_STM32H7 + select STM32_LPTIM + +config STM32_SPI4_COMMTYPE + int "SPI4 Operation mode" + depends on STM32_COMMON_H7_H5 && STM32_SPI && STM32_SPI4 + default 0 + range 0 3 + ---help--- + Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3) + +config STM32_SPI5_COMMTYPE + int "SPI5 Operation mode" + depends on STM32_COMMON_H7_H5 && STM32_SPI && STM32_SPI5 + default 0 + range 0 3 + ---help--- + Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3) + +config STM32_SPI6_COMMTYPE + int "SPI6 Operation mode" + depends on STM32_COMMON_H7_H5 && STM32_SPI && STM32_SPI6 + default 0 + range 0 3 + ---help--- + Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3) + +config STM32_TIM6_ADC + bool "TIM6 ADC" + depends on (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM6 && STM32_ADC + ---help--- + Reserve timer 6 for use by ADC + + Timer devices may be used for different purposes. If STM32_TIM6 is + defined then the following may also be defined to indicate that the + timer is intended to be used for ADC conversion. Note that ADC usage + requires two definition: Not only do you have to assign the timer + for used by the ADC, but then you also have to configure which ADC + channel it is assigned to. + +config STM32_TIMX_CAP + bool "Helpers for Capture Drivers" + depends on ARCH_CHIP_STM32H7 + default n + +config STM32_TIM15_CAP + bool "TIM15 Capture" + depends on STM32_COMMON_H7_H5 && STM32_TIM15 + select STM32_TIMX_CAP if ARCH_CHIP_STM32H7 && STM32_TIM15 + ---help--- + Reserve timer 15 for use by the capture driver. + +config STM32_TIM16_CAP + bool "TIM16 Capture" + depends on STM32_COMMON_H7_H5 && STM32_TIM16 + select STM32_TIMX_CAP if ARCH_CHIP_STM32H7 && STM32_TIM16 + ---help--- + Reserve timer 16 for use by the capture driver. + +config STM32_TIM17_CAP + bool "TIM17 Capture" + depends on STM32_COMMON_H7_H5 && STM32_TIM17 + select STM32_TIMX_CAP if ARCH_CHIP_STM32H7 && STM32_TIM17 + ---help--- + Reserve timer 17 for use by the capture driver. + +config STM32_TIM15_CLOCK + int "TIM15 capture frequency (Hz)" + depends on ARCH_CHIP_STM32H7 && STM32_TIM15_CAP + default 100000 + ---help--- + This clock frequency determines the timer's counting rate. + +config STM32_TIM16_CLOCK + int "TIM16 capture frequency (Hz)" + depends on ARCH_CHIP_STM32H7 && STM32_TIM16_CAP + default 100000 + ---help--- + This clock frequency determines the timer's counting rate. + +config STM32_TIM17_CLOCK + int "TIM17 capture frequency (Hz)" + depends on ARCH_CHIP_STM32H7 && STM32_TIM17_CAP + default 100000 + ---help--- + This clock frequency determines the timer's counting rate. + +config STM32_LPTIM1_CAP + bool "LPTIM1 Capture" + depends on ARCH_CHIP_STM32H7 && STM32_LPTIM1 + default n + select STM32_TIMX_CAP + ---help--- + Reserve low-power timer 1 for use by the capture driver. + +config STM32_LPTIM1_CLOCK + int "LPTIM1 capture frequency (Hz)" + depends on ARCH_CHIP_STM32H7 && STM32_LPTIM1_CAP + default 100000 + ---help--- + This clock frequency determines the timer's counting rate. + +config STM32_LPTIM2_CAP + bool "LPTIM2 Capture" + depends on ARCH_CHIP_STM32H7 && STM32_LPTIM2 + default n + select STM32_TIMX_CAP + ---help--- + Reserve low-power timer 2 for use by the capture driver. + +config STM32_LPTIM2_CLOCK + int "LPTIM2 capture frequency (Hz)" + depends on ARCH_CHIP_STM32H7 && STM32_LPTIM2_CAP + default 100000 + ---help--- + This clock frequency determines the timer's counting rate. + +config STM32_LPTIM1_CHANNEL + int "LPTIM1 Capture Input Channel" + depends on (ARCH_CHIP_STM32H7 && STM32_LPTIM1_CAP) || (ARCH_CHIP_STM32L4 && STM32_LPTIM1_PWM && !STM32_PWM_MULTICHAN) + default 1 + range 1 2 if ARCH_CHIP_STM32H7 && STM32_LPTIM1_CAP + range 1 1 if ARCH_CHIP_STM32L4 && STM32_LPTIM1_PWM && !STM32_PWM_MULTICHAN + ---help--- + Specifies the timer input channel {1,2} for LPTIM1. + +config STM32_LPTIM2_CHANNEL + int "LPTIM2 Capture Input Channel" + depends on (ARCH_CHIP_STM32H7 && STM32_LPTIM2_CAP) || (ARCH_CHIP_STM32L4 && STM32_LPTIM2_PWM && !STM32_PWM_MULTICHAN) + default 1 + range 1 2 if ARCH_CHIP_STM32H7 && STM32_LPTIM2_CAP + range 1 1 if ARCH_CHIP_STM32L4 && STM32_LPTIM2_PWM && !STM32_PWM_MULTICHAN + ---help--- + Specifies the timer input channel {1,2} for LPTIM2. + +config STM32_LPTIM3_CAP + bool "LPTIM3 Capture" + depends on ARCH_CHIP_STM32H7 && STM32_LPTIM3 + default n + select STM32_TIMX_CAP + ---help--- + Reserve low-power timer 3 for use by the capture driver. + +config STM32_LPTIM3_CHANNEL + int "LPTIM3 Capture Input Channel" + depends on ARCH_CHIP_STM32H7 && STM32_LPTIM3_CAP + default 1 + range 1 2 + ---help--- + Specifies the timer input channel {1,2} for LPTIM3. + +config STM32_LPTIM3_CLOCK + int "LPTIM3 capture frequency (Hz)" + depends on ARCH_CHIP_STM32H7 && STM32_LPTIM3_CAP + default 100000 + ---help--- + This clock frequency determines the timer's counting rate. + +config STM32_LPTIM4_CAP + bool "LPTIM4 Capture" + depends on ARCH_CHIP_STM32H7 && STM32_LPTIM4 + default n + select STM32_TIMX_CAP + ---help--- + Reserve low-power timer 4 for use by the capture driver. + +config STM32_LPTIM4_CHANNEL + int "LPTIM4 Capture Input Channel" + depends on ARCH_CHIP_STM32H7 && STM32_LPTIM4_CAP + default 1 + range 1 2 + ---help--- + Specifies the timer input channel {1,2} for LPTIM4. + +config STM32_LPTIM4_CLOCK + int "LPTIM4 capture frequency (Hz)" + depends on ARCH_CHIP_STM32H7 && STM32_LPTIM4_CAP + default 100000 + ---help--- + This clock frequency determines the timer's counting rate. + +config STM32_LPTIM5_CAP + bool "LPTIM5 Capture" + depends on ARCH_CHIP_STM32H7 && STM32_LPTIM5 + default n + select STM32_TIMX_CAP + ---help--- + Reserve low-power timer 5 for use by the capture driver. + +config STM32_LPTIM5_CHANNEL + int "LPTIM5 Capture Input Channel" + depends on ARCH_CHIP_STM32H7 && STM32_LPTIM5_CAP + default 1 + range 1 2 + ---help--- + Specifies the timer input channel {1,2} for LPTIM5. + +config STM32_LPTIM5_CLOCK + int "LPTIM5 capture frequency (Hz)" + depends on ARCH_CHIP_STM32H7 && STM32_LPTIM5_CAP + default 100000 + ---help--- + This clock frequency determines the timer's counting rate. + +config STM32_ETH_NRXDESC + int "Number of RX descriptors" + depends on STM32_COMMON_H7_H5 && STM32_ETHMAC + default 8 + ---help--- + Number of RX DMA descriptors to use. + +config STM32_ETH_NTXDESC + int "Number of TX descriptors" + depends on STM32_COMMON_H7_H5 && STM32_ETHMAC + default 4 + ---help--- + Number of TX DMA descriptors to use. + +config STM32_ETH_HWCHECKSUM + bool "Enable ethernet hardware checksum" + depends on ARCH_CHIP_STM32H5 && STM32_ETHMAC + ---help--- + Enable the IPv4/IPv6 header and TCP/UDP/ICMP payload checksum offload + engine in the Ethernet MAC. + When enabled, hardware generates checksums for TX and checks RX frames. + Be sure to disable software checksums (NET_TCP_CHECKSUMS, NET_UDP_CHECKSUMS, + NET_ICMP_CHECKSUMS, NET_IPV4_CHECKSUMS, NET_IPV6_CHECKSUMS) to avoid + redundant verification in the network stack. + +config STM32_NO_PHY + bool "MAC has no PHY" + depends on STM32_COMMON_H7_H5 && STM32_ETHMAC + +config STM32_IO_CONFIG_K + bool + +config STM32_IO_CONFIG_T + bool + +config STM32_IO_CONFIG_C + bool + select STM32_GPIO_HAVE_PORTE if ARCH_CHIP_STM32WB + +config STM32_IO_CONFIG_J + bool + +config STM32_IO_CONFIG_M + bool + +config STM32_IO_CONFIG_Q + bool + +config STM32_SRAM2_HEAP + bool "SRAM2 is used for heap" + depends on STM32_COMMON_SRAM2_OPTIONS + select STM32_SRAM2_INIT if !ARCH_CHIP_STM32U5 || STM32_SRAM2 + ---help--- + The STM32L4 SRAM2 region has special properties (power, protection, parity) + which may be used by the application for special purposes. But if these + special properties are not needed, it may be instead added to the heap for + use by malloc(). + NOTE: you must also select an appropriate number of memory regions in the + 'Memory Management' section. + +config STM32_SRAM2_INIT + bool "SRAM2 is initialized to zero" + depends on STM32_COMMON_SRAM2_OPTIONS + ---help--- + The STM32L4 SRAM2 region has parity checking. However, when the system + powers on, the memory is in an unknown state, and reads from uninitialized + memory can trigger parity faults from the random data. This can be + avoided by first writing to all locations to force the parity into a valid + state. + However, if the SRAM2 is being used for it's battery-backed capability, + this may be undesirable (because it will destroy the contents). In that + case, the board should handle the initialization itself at the appropriate + time. + +config STM32_SRAM3_HEAP + bool "SRAM3 is used for heap" + depends on (ARCH_CHIP_STM32L4 && STM32_STM32L4XR) || (ARCH_CHIP_STM32U5 && STM32_SRAM3) + default y if ARCH_CHIP_STM32L4 && STM32_STM32L4XR + ---help--- + Add the STM32L4 SRAM3 to the heap for use by malloc(). + NOTE: you must also select an appropriate number of memory regions in the + 'Memory Management' section. + +config STM32_HAVE_COMP + bool + +config STM32_HAVE_USART1 + bool + +config STM32_SAI1PLL + bool "SAI1PLL" + depends on STM32_COMMON_L4_L5_U5 + ---help--- + The STM32L4 has a separate PLL for the SAI1 block. + Set this true and provide configuration parameters in + board.h to use this PLL. + +config STM32_SAI2PLL + bool "SAI2PLL" + depends on STM32_COMMON_L4_L5_U5 && STM32_HAVE_SAI2 + ---help--- + The STM32L4 has a separate PLL for the SAI2 block. + Set this true and provide configuration parameters in + board.h to use this PLL. + +config STM32_TICKLESS_ONESHOT + int "Tickless one-shot timer channel" + depends on STM32_COMMON_L4_L5_U5 && SCHED_TICKLESS && STM32_ONESHOT + default 2 + range 1 8 + ---help--- + If the Tickless OS feature is enabled, then one clock must be + assigned to provide the one-shot timer needed by the OS. + +config STM32_TICKLESS_FREERUN + int "Tickless free-running timer channel" + depends on STM32_COMMON_L4_L5_U5 && SCHED_TICKLESS && STM32_FREERUN + default 5 + range 1 8 + ---help--- + If the Tickless OS feature is enabled, then one clock must be + assigned to provide the free-running timer needed by the OS. + +config STM32_LPTIM1_PWM + bool "LPTIM1 PWM" + depends on STM32_COMMON_L4_L5_U5 && STM32_LPTIM1 + select PWM + ---help--- + Reserve low-power timer 1 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32_LPTIM1 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +config STM32_LPTIM2_PWM + bool "LPTIM2 PWM" + depends on STM32_COMMON_L4_L5_U5 && STM32_LPTIM2 + select PWM + ---help--- + Reserve low-power timer 2 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32_LPTIM2 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +config STM32_LPTIM1_CH1OUT + bool "LPTIM1 Channel 1 Output" + depends on STM32_LPTIM1_CH1OUT_CAPABLE + ---help--- + Enables channel 1 output. + +config STM32_LPTIM1_CH1NOUT + bool "LPTIM1 Channel 1 Complementary Output" + depends on STM32_LPTIM1_CH1NOUT_CAPABLE + ---help--- + Enables channel 1 complementary output. + +config STM32_LPTIM2_CH1OUT + bool "LPTIM2 Channel 1 Output" + depends on STM32_LPTIM2_CH1OUT_CAPABLE + ---help--- + Enables channel 1 output. + +config STM32_LPTIM2_CH1NOUT + bool "LPTIM2 Channel 1 Complementary Output" + depends on STM32_LPTIM2_CH1NOUT_CAPABLE + ---help--- + Enables channel 1 complementary output. + +config STM32_ADC1_OUTPUT_DFSDM + bool "ADC1 output to DFSDM" + depends on STM32_ADC1_OUTPUT_DFSDM_CAPABLE + ---help--- + Route ADC1 output directly to DFSDM parallel inputs. + +config STM32_ADC2_OUTPUT_DFSDM + bool "ADC2 output to DFSDM" + depends on STM32_ADC2_OUTPUT_DFSDM_CAPABLE + ---help--- + Route ADC2 output directly to DFSDM parallel inputs. + +config STM32_ADC3_OUTPUT_DFSDM + bool "ADC3 output to DFSDM" + depends on STM32_ADC3_OUTPUT_DFSDM_CAPABLE + ---help--- + Route ADC3 output directly to DFSDM parallel inputs. + +config STM32_DAC1_DMA + bool "DAC1 DMA" + depends on STM32_COMMON_L4_L5_U5 && STM32_DAC && STM32_DAC1 + ---help--- + If DMA is selected, then a timer and output frequency must also be + provided to support the DMA transfer. The DMA transfer could be + supported by an EXTI trigger, but this feature is not currently + supported by the driver. + +config STM32_DAC1_TIMER + int "DAC1 timer" + depends on STM32_COMMON_L4_L5_U5 && STM32_DAC && STM32_DAC1_DMA + range 2 8 + +config STM32_DAC1_TIMER_FREQUENCY + int "DAC1 timer frequency" + depends on STM32_COMMON_L4_L5_U5 && STM32_DAC && STM32_DAC1_DMA + default 100 + ---help--- + DAC1 output frequency. Default: 100Hz + +config STM32_DAC1_DMA_BUFFER_SIZE + int "DAC1 DMA buffer size" + depends on STM32_COMMON_L4_L5_U5 && STM32_DAC && STM32_DAC1_DMA + default 1 + +config STM32_DAC1_OUTPUT_ADC + bool "DAC1 output to ADC" + depends on STM32_COMMON_L4_L5_U5 && STM32_DAC && STM32_DAC1 + ---help--- + Route DAC1 output to ADC input instead of external pin. + +config STM32_DAC2_DMA + bool "DAC2 DMA" + depends on STM32_COMMON_L4_L5_U5 && STM32_DAC && STM32_DAC2 + ---help--- + If DMA is selected, then a timer and output frequency must also be + provided to support the DMA transfer. The DMA transfer could be + supported by an EXTI trigger, but this feature is not currently + supported by the driver. + +config STM32_DAC2_TIMER + int "DAC2 timer" + depends on STM32_COMMON_L4_L5_U5 && STM32_DAC && STM32_DAC2_DMA + default 0 + range 2 8 + +config STM32_DAC2_TIMER_FREQUENCY + int "DAC2 timer frequency" + depends on STM32_COMMON_L4_L5_U5 && STM32_DAC && STM32_DAC2_DMA + default 100 + ---help--- + DAC2 output frequency. Default: 100Hz + +config STM32_DAC2_DMA_BUFFER_SIZE + int "DAC2 DMA buffer size" + depends on STM32_COMMON_L4_L5_U5 && STM32_DAC && STM32_DAC2_DMA + default 1 + +config STM32_DAC2_OUTPUT_ADC + bool "DAC2 output to ADC" + depends on STM32_COMMON_L4_L5_U5 && STM32_DAC && STM32_DAC2 + ---help--- + Route DAC2 output to ADC input instead of external pin. + +config STM32_DFSDM1_FLT0 + bool "DFSDM1 Filter 0" + depends on STM32_COMMON_L4_L5_U5 && STM32_DFSDM1 + select STM32_DFSDM + +config STM32_DFSDM1_FLT1 + bool "DFSDM1 Filter 1" + depends on STM32_COMMON_L4_L5_U5 && STM32_DFSDM1 + select STM32_DFSDM + +config STM32_DFSDM1_FLT2 + bool "DFSDM1 Filter 2" + depends on (ARCH_CHIP_STM32L4 && STM32_DFSDM1 && !STM32_STM32L4X3) || (ARCH_CHIP_STM32L5 && STM32_DFSDM1 && !STM32_STM32L5X3) || (ARCH_CHIP_STM32U5 && STM32_DFSDM1 && !STM32_STM32U5X3) + select STM32_DFSDM + +config STM32_DFSDM1_FLT3 + bool "DFSDM1 Filter 3" + depends on (ARCH_CHIP_STM32L4 && STM32_DFSDM1 && !STM32_STM32L4X3) || (ARCH_CHIP_STM32L5 && STM32_DFSDM1 && !STM32_STM32L5X3) || (ARCH_CHIP_STM32U5 && STM32_DFSDM1 && !STM32_STM32U5X3) + select STM32_DFSDM + +config STM32_DFSDM1_DMA + bool "DFSDM1 DMA" + depends on STM32_COMMON_L4_L5_U5 && STM32_DFSDM1 && STM32_DFSDM + ---help--- + If DMA is selected, then the DFSDM may be configured to support + DMA transfer, which is necessary if multiple channels are read + or if very high trigger frequencies are used. + +config STM32_RTC_LSECLOCK_LOWER_RUN_DRV_CAPABILITY + bool "Decrease LSE oscillator drive capability after LSE start-up" + depends on STM32_COMMON_L5_U5 && STM32_RTC && STM32_RTC_LSECLOCK && !STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY + ---help--- + The LSE oscillator drive capability can remain at the level used + during LSE start-up at run-time, or it can be reduced to the + 'Low drive capability' once the LSE started up successfully. + +config STM32_TIM2_CHANNEL5 + bool "TIM2 Channel 4" + depends on STM32_COMMON_L5_U5 && STM32_TIM2_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 4. + +config STM32_TIM3_CHANNEL5 + bool "TIM3 Channel 4" + depends on STM32_COMMON_L5_U5 && STM32_TIM3_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 4. + +config STM32_TIM4_CHANNEL5 + bool "TIM4 Channel 4" + depends on STM32_COMMON_L5_U5 && STM32_TIM4_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 4. + +config STM32_TIM5_CHANNEL5 + bool "TIM5 Channel 4" + depends on STM32_COMMON_L5_U5 && STM32_TIM5_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 4. + +config STM32_IPCC + bool "IPCC" + depends on ARCH_CHIP_STM32WB || ARCH_CHIP_STM32WL5 + select IPCC if ARCH_CHIP_STM32WL5 + ---help--- + IPCC - Inter Processor Communication Controller. A very simple + character device stream driver to exchange data between + CM0 and CM4. + +config STM32_IPCC_CHAN1_RX_SIZE + int "Channel 1 RX size" + default 256 + depends on STM32_IPCC + ---help--- + Size of the receive buffer. Another CPU will write to this buffer and + the currently running CPU will read from it. + +config STM32_IPCC_CHAN1_TX_SIZE + int "Channel 1 TX size" + default 256 + depends on STM32_IPCC + ---help--- + Size of the send buffer. Another CPU will read from this buffer and + the currently running CPU will write to it. + +config STM32_IPCC_CHAN2 + bool "Enable channel 2" + depends on STM32_IPCC + +if STM32_IPCC_CHAN2 + +config STM32_IPCC_CHAN2_RX_SIZE + int "Channel 2 RX size" + default 256 + +config STM32_IPCC_CHAN2_TX_SIZE + int "Channel 2 TX size" + default 256 + +config STM32_IPCC_CHAN3 + bool "Enable channel 3" + +if STM32_IPCC_CHAN3 + +config STM32_IPCC_CHAN3_RX_SIZE + int "Channel 3 RX size" + default 256 + +config STM32_IPCC_CHAN3_TX_SIZE + int "Channel 3 TX size" + default 256 + +config STM32_IPCC_CHAN4 + bool "Enable channel 4" + +if STM32_IPCC_CHAN4 + +config STM32_IPCC_CHAN4_RX_SIZE + int "Channel 4 RX size" + default 256 + +config STM32_IPCC_CHAN4_TX_SIZE + int "Channel 4 TX size" + default 256 + +config STM32_IPCC_CHAN5 + bool "Enable channel 5" + +if STM32_IPCC_CHAN5 + +config STM32_IPCC_CHAN5_RX_SIZE + int "Channel 5 RX size" + default 256 + +config STM32_IPCC_CHAN5_TX_SIZE + int "Channel 5 TX size" + default 256 + +config STM32_IPCC_CHAN6 + bool "Enable channel 6" + +if STM32_IPCC_CHAN6 + +config STM32_IPCC_CHAN6_RX_SIZE + int "Channel 6 RX size" + default 256 + +config STM32_IPCC_CHAN6_TX_SIZE + int "Channel 6 TX size" + default 256 + +endif # STM32_IPCC_CHAN2 +endif # STM32_IPCC_CHAN3 +endif # STM32_IPCC_CHAN4 +endif # STM32_IPCC_CHAN5 +endif # STM32_IPCC_CHAN6 + endmenu # Common STM32 Configuration Options diff --git a/arch/arm/src/stm32/Kconfig b/arch/arm/src/stm32/Kconfig index b0315f1a414..b8bcda25eee 100644 --- a/arch/arm/src/stm32/Kconfig +++ b/arch/arm/src/stm32/Kconfig @@ -5,6 +5,26 @@ comment "STM32 Configuration Options" +config STM32_COMMON_PERIPHERALS + bool + default y + depends on ARCH_CHIP_STM32F1 || ARCH_CHIP_STM32F2 || ARCH_CHIP_STM32F3 || ARCH_CHIP_STM32F4 || ARCH_CHIP_STM32G4 || ARCH_CHIP_STM32L1 + select STM32_HAVE_COMP if STM32_STM32L15XX || STM32_STM32F33XX || STM32_STM32G4XXX + select STM32_HAVE_DCMI if STM32_STM32F20XX || STM32_STM32F4XXX + select STM32_HAVE_DMA2 if !STM32_VALUELINE || (STM32_VALUELINE && STM32_HIGHDENSITY) + select STM32_HAVE_DMA2D if STM32_STM32F429 + select STM32_HAVE_ETHERNET if STM32_HAVE_ETHMAC + select STM32_HAVE_HASH if STM32_STM32F20XX || STM32_STM32F4XXX + select STM32_HAVE_I2C1 + select STM32_HAVE_LCD if STM32_STM32L15XX + select STM32_HAVE_SPI1 + select STM32_HAVE_SYSCFG if STM32_STM32L15XX || STM32_STM32F30XX + select STM32_HAVE_SYSCFG if STM32_STM32F33XX || STM32_STM32F37XX + select STM32_HAVE_SYSCFG if STM32_STM32F20XX || STM32_STM32F4XXX + select STM32_HAVE_SYSCFG if STM32_STM32G4XXX || STM32_CONNECTIVITYLINE + select STM32_HAVE_USART1 + select STM32_HAVE_USART2 + choice prompt "STM32 Chip Selection" default ARCH_CHIP_STM32F103ZE @@ -1210,40 +1230,9 @@ endchoice config STM32_FLASH_CONFIG_DEFAULT bool -config STM32_FLASH_CONFIG_4 - bool - -config STM32_FLASH_CONFIG_6 - bool - -config STM32_FLASH_CONFIG_8 - bool - -config STM32_FLASH_CONFIG_B - bool - config STM32_FLASH_CONFIG_Z bool -config STM32_FLASH_CONFIG_C - bool - -config STM32_FLASH_CONFIG_D - bool - -config STM32_FLASH_CONFIG_E - bool - -config STM32_FLASH_CONFIG_F - bool - -config STM32_FLASH_CONFIG_G - bool - -config STM32_FLASH_CONFIG_I - bool - -# This is really 15XX/16XX, but we treat the two the same. config STM32_STM32L15XX bool default n @@ -1254,6 +1243,7 @@ config STM32_STM32L15XX select STM32_HAVE_I2C2 select STM32_HAVE_SPI2 select STM32_HAVE_SPI3 + select STM32_HAVE_TIM2 select STM32_HAVE_TIM3 select STM32_HAVE_TIM4 select STM32_HAVE_TIM9 @@ -1269,12 +1259,6 @@ config STM32_STM32L15XX select STM32_HAVE_IP_DMA_V1 select STM32_HAVE_IP_I2C_V1 -config STM32_ENERGYLITE - bool - default n - select STM32_HAVE_TIM6 - select STM32_HAVE_TIM7 - config STM32_STM32F10XX bool default n @@ -1282,6 +1266,7 @@ config STM32_STM32F10XX select STM32_HAVE_SPI2 if STM32_HIGHDENSITY || STM32_MEDIUMDENSITY select STM32_HAVE_SPI3 if STM32_HIGHDENSITY || STM32_MEDIUMDENSITY select STM32_HAVE_RTC_COUNTER + select STM32_HAVE_TIM2 select STM32_HAVE_TIM3 select STM32_HAVE_IP_DBGMCU_V1 select STM32_HAVE_IP_TIMERS_V1 @@ -1290,25 +1275,6 @@ config STM32_STM32F10XX select STM32_HAVE_IP_DMA_V1 select STM32_HAVE_IP_I2C_V1 -config STM32_VALUELINE - bool - default n - select STM32_HAVE_USART3 - select STM32_HAVE_UART4 - select STM32_HAVE_UART5 - select STM32_HAVE_TIM1 - select STM32_HAVE_TIM5 - select STM32_HAVE_TIM6 - select STM32_HAVE_TIM7 - select STM32_HAVE_TIM12 - select STM32_HAVE_TIM13 - select STM32_HAVE_TIM14 - select STM32_HAVE_TIM15 - select STM32_HAVE_TIM16 - select STM32_HAVE_TIM17 - select STM32_HAVE_SPI2 if STM32_HIGHDENSITY - select STM32_HAVE_SPI3 if STM32_HIGHDENSITY - config STM32_CONNECTIVITYLINE bool default n @@ -1317,6 +1283,7 @@ config STM32_CONNECTIVITYLINE select STM32_HAVE_UART4 select STM32_HAVE_UART5 select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 select STM32_HAVE_TIM5 select STM32_HAVE_TIM6 select STM32_HAVE_TIM7 @@ -1335,6 +1302,7 @@ config STM32_PERFORMANCELINE select STM32_HAVE_UART4 select STM32_HAVE_UART5 select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 select STM32_HAVE_TIM5 select STM32_HAVE_TIM6 select STM32_HAVE_TIM7 @@ -1362,6 +1330,7 @@ config STM32_HIGHDENSITY select STM32_HAVE_UART4 select STM32_HAVE_UART5 select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 select STM32_HAVE_TIM5 select STM32_HAVE_TIM6 select STM32_HAVE_TIM7 @@ -1377,6 +1346,7 @@ config STM32_MEDIUMDENSITY select STM32_HAVE_UART4 select STM32_HAVE_UART5 select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 select STM32_HAVE_TIM5 select STM32_HAVE_TIM6 select STM32_HAVE_TIM7 @@ -1392,6 +1362,7 @@ config STM32_LOWDENSITY select STM32_HAVE_UART4 select STM32_HAVE_UART5 select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 select STM32_HAVE_TIM5 select STM32_HAVE_TIM6 select STM32_HAVE_TIM7 @@ -1413,6 +1384,7 @@ config STM32_STM32F20XX select STM32_HAVE_UART5 select STM32_HAVE_USART6 select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 select STM32_HAVE_TIM3 select STM32_HAVE_TIM4 select STM32_HAVE_TIM5 @@ -1462,6 +1434,7 @@ config STM32_STM32F30XX select STM32_HAVE_CAN1 select STM32_HAVE_DAC1 select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 select STM32_HAVE_TIM3 select STM32_HAVE_TIM6 select STM32_HAVE_TIM15 @@ -1507,6 +1480,7 @@ config STM32_STM32F33XX select STM32_HAVE_OPAMP2 select STM32_HAVE_CCM select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 select STM32_HAVE_TIM6 select STM32_HAVE_TIM7 select STM32_HAVE_TIM15 @@ -1534,6 +1508,7 @@ config STM32_STM32F37XX select ARCH_CORTEXM4 select ARCH_HAVE_FPU select STM32_HAVE_USBDEV + select STM32_HAVE_TIM2 select STM32_HAVE_TIM3 select STM32_HAVE_TIM4 select STM32_HAVE_TIM5 @@ -1594,6 +1569,7 @@ config STM32_STM32F401 select STM32_STM32F4XXX select STM32_HAVE_USART6 select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 select STM32_HAVE_TIM3 select STM32_HAVE_TIM4 select STM32_HAVE_TIM5 @@ -1611,6 +1587,7 @@ config STM32_STM32F410 default n select STM32_HAVE_USART6 select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 select STM32_HAVE_TIM5 select STM32_HAVE_TIM6 select STM32_HAVE_TIM9 @@ -1623,6 +1600,7 @@ config STM32_STM32F411 default n select STM32_HAVE_USART6 select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 select STM32_HAVE_TIM3 select STM32_HAVE_TIM4 select STM32_HAVE_TIM5 @@ -1674,6 +1652,7 @@ config STM32_STM32F405 select STM32_HAVE_UART5 select STM32_HAVE_USART6 select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 select STM32_HAVE_TIM3 select STM32_HAVE_TIM4 select STM32_HAVE_TIM5 @@ -1748,6 +1727,7 @@ config STM32_STM32F427 select STM32_HAVE_UART7 select STM32_HAVE_UART8 select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 select STM32_HAVE_TIM3 select STM32_HAVE_TIM4 select STM32_HAVE_TIM5 @@ -1793,6 +1773,7 @@ config STM32_STM32F429 select STM32_HAVE_UART7 select STM32_HAVE_UART8 select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 select STM32_HAVE_TIM3 select STM32_HAVE_TIM4 select STM32_HAVE_TIM5 @@ -2119,554 +2100,10 @@ config STM32_STM32G474V select STM32_HAVE_UART4 select STM32_HAVE_UART5 -config STM32_DFU - bool "DFU bootloader" - default n - depends on !STM32_VALUELINE - ---help--- - Configure and position code for use with the STMicro DFU bootloader. Do - not select this option if you will load code using JTAG/SWM. - menu "STM32 Peripheral Support" -# These "hidden" settings determine whether a peripheral option is available -# for the selected MCU - -config STM32_HAVE_FLASH_ICACHE - bool - default n - -config STM32_HAVE_FLASH_DCACHE - bool - default n - -config STM32_HAVE_OVERDRIVE - bool - default n - -config STM32_HAVE_AES - bool - default n - -config STM32_HAVE_CRYP - bool - default n - -config STM32_HAVE_CCM - bool - default n - -config STM32_HAVE_DMA1_CHAN8 - bool - default n - -config STM32_HAVE_DMA2_CHAN678 - bool - default n - -config STM32_HAVE_DMAMUX - bool - default n - -config STM32_HAVE_UCPD - bool - default n - -config STM32_HAVE_USBDEV - bool - default n - -config STM32_HAVE_USBFS - bool - default n - -config STM32_HAVE_OTGFS - bool - default n - -config STM32_HAVE_FMC - bool - default n - -config STM32_HAVE_FMAC - bool - default n - -config STM32_HAVE_FSMC - bool - default n - -config STM32_HAVE_FDCAN1 - bool - default n - -config STM32_HAVE_FDCAN2 - bool - default n - -config STM32_HAVE_FDCAN3 - bool - default n - -config STM32_HAVE_IOCOMPENSATION - bool - default n - -config STM32_HAVE_HRTIM1 - bool - default n - -config STM32_HAVE_HRTIM1_PLLCLK - bool - default n - -config STM32_HAVE_LTDC - bool - default n - -config STM32_HAVE_USART2 - bool - default n - -config STM32_HAVE_USART3 - bool - default n - -config STM32_HAVE_UART4 - bool - default n - -config STM32_HAVE_UART5 - bool - default n - -config STM32_HAVE_USART6 - bool - default n - -config STM32_HAVE_UART7 - bool - default n - -config STM32_HAVE_UART8 - bool - default n - -config STM32_HAVE_TIM1 - bool - default n - -config STM32_HAVE_TIM2 - bool - default n - -config STM32_HAVE_TIM3 - bool - default n - -config STM32_HAVE_TIM4 - bool - default n - -config STM32_HAVE_TIM5 - bool - default n - -config STM32_HAVE_TIM6 - bool - default n - -config STM32_HAVE_TIM7 - bool - default n - -config STM32_HAVE_TIM8 - bool - default n - -config STM32_HAVE_TIM9 - bool - default n - -config STM32_HAVE_TIM10 - bool - default n - -config STM32_HAVE_TIM11 - bool - default n - -config STM32_HAVE_TIM12 - bool - default n - -config STM32_HAVE_TIM13 - bool - default n - -config STM32_HAVE_TIM14 - bool - default n - -config STM32_HAVE_TIM15 - bool - default n - -config STM32_HAVE_TIM16 - bool - default n - -config STM32_HAVE_TIM17 - bool - default n - -config STM32_HAVE_TIM18 - bool - default n - -config STM32_HAVE_TIM19 - bool - default n - -config STM32_HAVE_TIM20 - bool - default n - -config STM32_HAVE_TSC - bool - default n - -config STM32_HAVE_ADC1 - bool - default y - -config STM32_HAVE_ADC2 - bool - default n - -config STM32_HAVE_ADC3 - bool - default n - -config STM32_HAVE_ADC4 - bool - default n - -config STM32_HAVE_ADC5 - bool - default n - -config STM32_HAVE_ADC1_DMA - bool - default n - -config STM32_HAVE_ADC2_DMA - bool - default n - -config STM32_HAVE_ADC3_DMA - bool - default n - -config STM32_HAVE_ADC4_DMA - bool - default n - -config STM32_HAVE_ADC5_DMA - bool - default n - -config STM32_HAVE_SDADC1 - bool - default n - -config STM32_HAVE_SDADC2 - bool - default n - -config STM32_HAVE_SDADC3 - bool - default n - -config STM32_HAVE_SDADC1_DMA - bool - default n - -config STM32_HAVE_SDADC2_DMA - bool - default n - -config STM32_HAVE_SDADC3_DMA - bool - default n - -config STM32_HAVE_CAN1 - bool - default n - -config STM32_HAVE_CAN2 - bool - default n - -config STM32_HAVE_COMP1 - bool - default n - -config STM32_HAVE_COMP2 - bool - default n - -config STM32_HAVE_COMP3 - bool - default n - -config STM32_HAVE_COMP4 - bool - default n - -config STM32_HAVE_COMP5 - bool - default n - -config STM32_HAVE_COMP6 - bool - default n - -config STM32_HAVE_COMP7 - bool - default n - -config STM32_HAVE_CORDIC - bool - default n - -config STM32_HAVE_CRS - bool - default n - -config STM32_HAVE_DAC1 - bool - default n - -config STM32_HAVE_DAC2 - bool - default n - -config STM32_HAVE_DAC3 - bool - default n - -config STM32_HAVE_DAC4 - bool - default n - -config STM32_HAVE_QSPI - bool - default n - -config STM32_HAVE_RNG - bool - default n - -config STM32_HAVE_ETHMAC - bool - default n - -config STM32_HAVE_I2C1 - bool - default n - -config STM32_HAVE_I2C2 - bool - default n - -config STM32_HAVE_I2C3 - bool - default n - -config STM32_HAVE_I2C4 - bool - default n - -config STM32_HAVE_LPTIM1 - bool - default n - -config STM32_HAVE_LPUART1 - bool - default n - -config STM32_HAVE_SPI1 - bool - default n - -config STM32_HAVE_SPI2 - bool - default n - -config STM32_HAVE_SPI3 - bool - default n - -config STM32_HAVE_I2S3 - bool - default n - -config STM32_HAVE_SPI4 - bool - default n - -config STM32_HAVE_SPI5 - bool - default n - -config STM32_HAVE_SPI6 - bool - default n - -config STM32_HAVE_SAIPLL - bool - default n - -config STM32_HAVE_I2SPLL - bool - default n - -config STM32_HAVE_OPAMP1 - bool - default n - -config STM32_HAVE_OPAMP2 - bool - default n - -config STM32_HAVE_OPAMP3 - bool - default n - -config STM32_HAVE_OPAMP4 - bool - default n - -config STM32_HAVE_OPAMP5 - bool - default n - -config STM32_HAVE_OPAMP6 - bool - default n - -# These are STM32 peripherals IP blocks - -config STM32_HAVE_IP_DBGMCU_V1 - bool - default n - -config STM32_HAVE_IP_DBGMCU_V2 - bool - default n - -config STM32_HAVE_IP_DBGMCU_V3 - bool - default n - -config STM32_HAVE_IP_I2C_V1 - bool - default n - -config STM32_HAVE_IP_I2C_V2 - bool - default n - -config STM32_HAVE_IP_DMA_V1 - bool - default n - -config STM32_HAVE_IP_DMA_V2 - bool - default n - -config STM32_HAVE_IP_TIMERS_V1 - bool - default n - -config STM32_HAVE_IP_TIMERS_V2 - bool - default n - -config STM32_HAVE_IP_TIMERS_V3 - bool - default n - -config STM32_HAVE_IP_ADC_V1 - bool - default n - -config STM32_HAVE_IP_ADC_V1_BASIC - bool - default n - select STM32_HAVE_IP_ADC_V1 - -config STM32_HAVE_IP_ADC_V2 - bool - default n - -config STM32_HAVE_IP_ADC_V2_BASIC - bool - default n - select STM32_HAVE_IP_ADC_V2 - -config STM32_HAVE_IP_COMP_V1 - bool - default n - -config STM32_HAVE_IP_COMP_V2 - bool - default n - -config STM32_HAVE_IP_DAC_V1 - bool - default n - -config STM32_HAVE_IP_DAC_V2 - bool - default n - # These are the peripheral selections proper -config STM32_ADC1 - bool "ADC1" - default n - select STM32_ADC - select STM32_HAVE_ADC1_DMA if STM32_STM32F10XX && STM32_DMA1 - select STM32_HAVE_ADC1_DMA if STM32_STM32F37XX && STM32_DMA1 - select STM32_HAVE_ADC1_DMA if !STM32_STM32F10XX && STM32_DMA2 - select STM32_HAVE_ADC1_DMA if STM32_DMAMUX - -config STM32_ADC2 - bool "ADC2" - default n - select STM32_ADC - depends on STM32_HAVE_ADC2 - select STM32_HAVE_ADC2_DMA if STM32_DMA2 - select STM32_HAVE_ADC2_DMA if STM32_DMAMUX - -config STM32_ADC3 - bool "ADC3" - default n - select STM32_ADC - depends on STM32_HAVE_ADC3 - select STM32_HAVE_ADC3_DMA if STM32_DMA2 - select STM32_HAVE_ADC3_DMA if STM32_DMAMUX - -config STM32_ADC4 - bool "ADC4" - default n - select STM32_ADC - depends on STM32_HAVE_ADC4 - select STM32_HAVE_ADC4_DMA if STM32_DMA2 - select STM32_HAVE_ADC4_DMA if STM32_DMAMUX - config STM32_ADC5 bool "ADC5" default n @@ -2696,18 +2133,6 @@ config STM32_SDADC3 depends on STM32_HAVE_SDADC3 select STM32_HAVE_SDADC3_DMA if STM32_DMA2 -config STM32_COMP1 - bool "COMP1" - default n - select STM32_COMP - depends on STM32_HAVE_COMP1 - -config STM32_COMP2 - bool "COMP2" - default n - select STM32_COMP - depends on STM32_HAVE_COMP2 - config STM32_COMP3 bool "COMP3" default n @@ -2738,90 +2163,11 @@ config STM32_COMP7 select STM32_COMP depends on STM32_HAVE_COMP7 -config STM32_CORDIC - bool "CORDIC Accelerator" - default n - depends on STM32_HAVE_CORDIC - depends on MATH_CORDIC_USE_Q31 - -config STM32_BKP - bool "BKP" - default n - depends on STM32_STM32F10XX - -config STM32_BKPSRAM - bool "Enable BKP RAM Domain" - default n - depends on STM32_STM32F20XX || STM32_STM32F4XXX - -config STM32_CAN1 - bool "CAN1" - default n - select STM32_CAN - depends on STM32_HAVE_CAN1 - -config STM32_CAN2 - bool "CAN2" - default n - select STM32_CAN - depends on STM32_HAVE_CAN2 - config STM32_CCMDATARAM bool "CMD/DATA RAM" default n depends on STM32_STM32F4XXX -config STM32_AES - bool "128-bit AES" - default n - depends on STM32_HAVE_AES - select CRYPTO_AES192_DISABLE if CRYPTO_ALGTEST - select CRYPTO_AES256_DISABLE if CRYPTO_ALGTEST - -config STM32_CEC - bool "CEC" - default n - depends on STM32_VALUELINE - -config STM32_CRC - bool "CRC" - default n - -config STM32_CRS - bool "CRS (Clock Recovery System)" - default n - depends on STM32_HAVE_CRS - -config STM32_CRYP - bool "CRYP" - default n - depends on STM32_HAVE_CRYP - -config STM32_DMA1 - bool "DMA1" - default n - select STM32_DMA - select ARCH_DMA - -config STM32_DMA2 - bool "DMA2" - default n - select STM32_DMA - select ARCH_DMA - depends on !STM32_VALUELINE || (STM32_VALUELINE && STM32_HIGHDENSITY) - -config STM32_DMAMUX1 - bool "DMAMUX1" - default n - depends on STM32_HAVE_DMAMUX - select STM32_DMAMUX - -config STM32_DAC1 - bool "DAC1" - default n - depends on STM32_HAVE_DAC1 - select STM32_DAC - if STM32_DAC1 config STM32_DAC1CH1 @@ -2834,12 +2180,6 @@ config STM32_DAC1CH2 endif #STM32_DAC1 -config STM32_DAC2 - bool "DAC2" - default n - depends on STM32_HAVE_DAC2 - select STM32_DAC - if STM32_DAC2 config STM32_DAC2CH1 @@ -2884,56 +2224,6 @@ config STM32_DAC4CH2 endif #STM32_DAC4 -config STM32_DCMI - bool "DCMI" - default n - depends on STM32_STM32F20XX || STM32_STM32F4XXX - -config STM32_ETHMAC - bool "Ethernet MAC" - default n - depends on STM32_HAVE_ETHMAC - select NETDEVICES - select ARCH_HAVE_PHY - -config STM32_FDCAN1 - bool "FDCAN1" - default n - depends on STM32_HAVE_FDCAN1 - select STM32_FDCAN - -config STM32_FDCAN2 - bool "FDCAN2" - default n - depends on STM32_HAVE_FDCAN2 - select STM32_FDCAN - -config STM32_FDCAN3 - bool "FDCAN3" - default n - depends on STM32_HAVE_FDCAN3 - select STM32_FDCAN - -config STM32_FSMC - bool "FSMC" - default n - depends on STM32_HAVE_FSMC - -config STM32_FMC - bool "FMC" - default n - depends on STM32_HAVE_FMC - -config STM32_FMAC - bool "FMAC (Filter Math Accelerator)" - default n - depends on STM32_HAVE_FMAC - -config STM32_HASH - bool "HASH" - default n - depends on STM32_STM32F20XX || STM32_STM32F4XXX - config STM32_HRTIM bool default n @@ -2984,23 +2274,6 @@ config STM32_HRTIM_TIME endif # STM32_HRTIM -config STM32_I2C1 - bool "I2C1" - default n - select STM32_I2C - -config STM32_I2C2 - bool "I2C2" - default n - depends on STM32_HAVE_I2C2 - select STM32_I2C - -config STM32_I2C3 - bool "I2C3" - default n - depends on STM32_HAVE_I2C3 - select STM32_I2C - config STM32_I2C1_SLAVE bool "I2C1 Slave" default n @@ -3019,38 +2292,6 @@ config STM32_I2C3_SLAVE depends on STM32_HAVE_I2C3 && !STM32_I2C3 && I2C_SLAVE select STM32_I2C_SLAVE -config STM32_LPTIM1 - bool "LPTIM1" - default n - depends on STM32_HAVE_LPTIM1 - -config STM32_LPUART1 - bool "LPUART1" - default n - depends on STM32_HAVE_LPUART1 - select STM32_USART - -config STM32_LTDC - bool "LTDC" - default n - select FB - depends on STM32_HAVE_LTDC - ---help--- - The STM32 LTDC is an LCD-TFT Display Controller available on - the STM32F429 and STM32F439 devices. It is a standard parallel - video interface (HSYNC, VSYNC, etc.) for controlling TFT - LCD displays. - -config STM32_DMA2D - bool "DMA2D" - default n - select FB - select FB_OVERLAY - depends on STM32_STM32F429 - ---help--- - The STM32 DMA2D is an Chrom-Art Accelerator for image manipulation - available on the STM32F429 and STM32F439 devices. - config STM32_OPAMP1 bool "OPAMP1" default n @@ -3075,280 +2316,12 @@ config STM32_OPAMP4 select STM32_OPAMP depends on STM32_HAVE_OPAMP4 -config STM32_RTC - bool "RTC" - default n - select RTC - -config STM32_OTGFS - bool "OTG FS" - default n - depends on STM32_HAVE_OTGFS - select USBHOST_HAVE_ASYNCH if STM32_USBHOST - -config STM32_OTGHS - bool "OTG HS" - default n - depends on STM32_STM32F20XX || STM32_STM32F4XXX - select USBHOST_HAVE_ASYNCH if STM32_USBHOST - -config STM32_PWR - bool "PWR" - default n - -config STM32_QSPI - bool "QSPI (QUADSPI)" - depends on STM32_HAVE_QSPI - default n - -config STM32_RNG - bool "RNG" - default n - depends on STM32_HAVE_RNG - select ARCH_HAVE_RNG - -# REVISIT: There are some lower-end STM32F401 parts without SDIO too. Others? - -config STM32_SDIO - bool "SDIO" - default n - depends on !STM32_CONNECTIVITYLINE && !STM32_VALUELINE - select ARCH_HAVE_SDIO - select ARCH_HAVE_SDIOWAIT_WRCOMPLETE - select ARCH_HAVE_SDIO_PREFLIGHT - -config STM32_SPI1 - bool "SPI1" - default n - select SPI - select STM32_SPI - -config STM32_SPI2 - bool "SPI2" - default n - depends on STM32_HAVE_SPI2 - select SPI - select STM32_SPI - -config STM32_SPI3 - bool "SPI3" - default n - depends on STM32_HAVE_SPI3 - select SPI - select STM32_SPI - -config STM32_I2S3 - bool "I2S3" - default n - depends on STM32_HAVE_I2S3 - select I2S - select STM32_I2S - -config STM32_SPI4 - bool "SPI4" - default n - depends on STM32_HAVE_SPI4 - select SPI - select STM32_SPI - -config STM32_SPI5 - bool "SPI5" - default n - depends on STM32_HAVE_SPI5 - select SPI - select STM32_SPI - -config STM32_SPI6 - bool "SPI6" - default n - depends on STM32_HAVE_SPI6 - select SPI - select STM32_SPI - -config STM32_SYSCFG - bool "SYSCFG" - default y - depends on STM32_STM32L15XX || STM32_STM32F30XX || STM32_STM32F33XX || STM32_STM32F37XX || STM32_STM32F20XX || STM32_STM32F4XXX || STM32_STM32G4XXX || STM32_CONNECTIVITYLINE - -config STM32_TIM1 - bool "TIM1" - default n - depends on STM32_HAVE_TIM1 - select STM32_TIM - -config STM32_TIM2 - bool "TIM2" - default n - select STM32_TIM - -config STM32_TIM3 - bool "TIM3" - default n - depends on STM32_HAVE_TIM3 - select STM32_TIM - -config STM32_TIM4 - bool "TIM4" - default n - depends on STM32_HAVE_TIM4 - select STM32_TIM - -config STM32_TIM5 - bool "TIM5" - default n - depends on STM32_HAVE_TIM5 - select STM32_TIM - -config STM32_TIM6 - bool "TIM6" - default n - depends on STM32_HAVE_TIM6 - select STM32_TIM - -config STM32_TIM7 - bool "TIM7" - default n - depends on STM32_HAVE_TIM7 - select STM32_TIM - -config STM32_TIM8 - bool "TIM8" - default n - depends on STM32_HAVE_TIM8 - select STM32_TIM - -config STM32_TIM9 - bool "TIM9" - default n - depends on STM32_HAVE_TIM9 - select STM32_TIM - -config STM32_TIM10 - bool "TIM10" - default n - depends on STM32_HAVE_TIM10 - select STM32_TIM - -config STM32_TIM11 - bool "TIM11" - default n - depends on STM32_HAVE_TIM11 - select STM32_TIM - -config STM32_TIM12 - bool "TIM12" - default n - depends on STM32_HAVE_TIM12 - select STM32_TIM - -config STM32_TIM13 - bool "TIM13" - default n - depends on STM32_HAVE_TIM13 - select STM32_TIM - -config STM32_TIM14 - bool "TIM14" - default n - depends on STM32_HAVE_TIM14 - select STM32_TIM - -config STM32_TIM15 - bool "TIM15" - default n - depends on STM32_HAVE_TIM15 - select STM32_TIM - -config STM32_TIM16 - bool "TIM16" - default n - depends on STM32_HAVE_TIM16 - select STM32_TIM - -config STM32_TIM17 - bool "TIM17" - default n - depends on STM32_HAVE_TIM17 - select STM32_TIM - -config STM32_TSC - bool "TSC" - default n - depends on STM32_HAVE_TSC - -config STM32_USART1 - bool "USART1" - default n - select STM32_USART - -config STM32_USART2 - bool "USART2" - default n - select STM32_USART - -config STM32_USART3 - bool "USART3" - default n - depends on STM32_HAVE_USART3 - select STM32_USART - -config STM32_UART4 - bool "UART4" - default n - depends on STM32_HAVE_UART4 - select STM32_USART - -config STM32_UART5 - bool "UART5" - default n - depends on STM32_HAVE_UART5 - select STM32_USART - -config STM32_USART6 - bool "USART6" - default n - depends on STM32_HAVE_USART6 - select STM32_USART - -config STM32_UART7 - bool "UART7" - default n - depends on STM32_HAVE_UART7 - select STM32_USART - -config STM32_UART8 - bool "UART8" - default n - depends on STM32_HAVE_UART8 - select STM32_USART - -config STM32_USB - bool "USB Device" - default n - depends on STM32_HAVE_USBDEV - select USBDEV - -config STM32_USBFS - bool "USB Full Speed Device" - default n - depends on STM32_HAVE_USBFS - select USBDEV - config STM32_UCPD bool "UCPD (USB Type C Power Delivery)" default n depends on STM32_HAVE_UCPD select USBDEV -config STM32_LCD - bool "Segment LCD" - default n - depends on STM32_STM32L15XX - -# -# STM32 LCD Clock Selection -# - if STM32_LCD choice @@ -3367,88 +2340,20 @@ config LCD_HSECLOCK endchoice endif # STM32_LCD -config STM32_IWDG - bool "IWDG" - default n - select WATCHDOG - -config STM32_WWDG - bool "WWDG" - default n - select WATCHDOG - endmenu -config STM32_ADC - bool - default n - config STM32_SDADC bool default n -config STM32_DAC - bool - default n - -config STM32_DMA - bool - default n - -config STM32_DMAMUX - bool - default n - -config STM32_SPI - bool - default n - -config STM32_SPI_DMA - bool - default n - -config STM32_I2S - bool - default n - select STM32_SPI_DMA - -config STM32_I2C - bool - default n - config STM32_I2C_SLAVE bool default n -config STM32_CAN - bool - default n - -config STM32_FDCAN - bool - default n - -config STM32_TIM - bool - default n - -config STM32_PWM - bool - default n - config STM32_CAP bool default n -config STM32_COMP - bool - default n - depends on STM32_STM32L15XX || STM32_STM32F33XX || STM32_STM32G4XXX - -config STM32_OPAMP - bool - default n - config STM32_NOEXT_VECTORS bool "Disable the ARMv7-M EXT vectors" default n @@ -3456,19 +2361,6 @@ config STM32_NOEXT_VECTORS Sometimes you may not need any Vector support beyond SysTick and wish to save memory. This applies only to ARMv7-M architectures. -config STM32_SYSCFG_IOCOMPENSATION - bool "SYSCFG I/O Compensation" - default n - depends on STM32_HAVE_IOCOMPENSATION - ---help--- - By default the I/O compensation cell is not used. However when the I/O - output buffer speed is configured in 50 MHz or 100 MHz mode, it is - recommended to use the compensation cell for slew rate control on I/O - tf(IO)out)/tr(IO)out commutation to reduce the I/O noise on power supply. - - The I/O compensation cell can be used only when the supply voltage ranges - from 2.4 to 3.6 V. - menu "Alternate Pin Mapping" depends on STM32_STM32F10XX || STM32_CONNECTIVITYLINE @@ -3666,34 +2558,6 @@ config STM32_FLASH_DCACHE ---help--- Enable the FLASH data cache. -config STM32_FLASH_WORKAROUND_DATA_CACHE_CORRUPTION_ON_RWW - bool "Workaround for FLASH data cache corruption" - default n - depends on (STM32_STM32F20XX || STM32_STM32F4XXX) && STM32_FLASH_DCACHE - ---help--- - Enable the workaround to fix flash data cache corruption when reading - from one flash bank while writing on other flash bank. See your STM32 - errata to check if your STM32 is affected by this problem. - -config STM32_FLASH_PREFETCH - bool "Enable FLASH Pre-fetch" - default STM32_STM32F427 || STM32_STM32F429 || STM32_STM32F446 - default n - depends on STM32_STM32F20XX || STM32_STM32F4XXX - ---help--- - Enable FLASH prefetch in F2 and F4 parts (FLASH pre-fetch is always enabled - on F1 parts). Some early revisions of F4 parts do not support FLASH pre-fetch - properly and enabling this option may interfere with ADC accuracy. - -config STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG - bool "Disable IDLE Sleep (WFI) in debug mode" - default n - ---help--- - In debug configuration, disables the WFI instruction in the IDLE loop - to prevent the JTAG from disconnecting. With some JTAG debuggers, such - as the ST-LINK2 with OpenOCD, if the ARM is put to sleep via the WFI - instruction, the debugger will disconnect, terminating the debug session. - config STM32_FORCEPOWER bool "Force power" default n @@ -3744,2870 +2608,11 @@ config STM32_CCM_PROCFS will provide statistics about CCM memory use similar to what you would get from mallinfo() for the user heap. -config STM32_DMACAPABLE - bool "Workaround non-DMA capable memory" - depends on ARCH_DMA - default STM32_STM32F4XXX && !STM32_CCMEXCLUDE - ---help--- - This option enables the DMA interface stm32_dmacapable that can be - used to check if it is possible to do DMA from the selected address. - Drivers then may use this information to determine if they should - attempt the DMA or fall back to a different transfer method. - -config STM32_EXTERNAL_RAM - bool "External RAM on FSMC/FMC" - default n - depends on STM32_FSMC || STM32_FMC - select ARCH_HAVE_HEAP2 - ---help--- - In addition to internal SRAM, external RAM may be available through the FSMC/FMC. - menu "Timer Configuration" depends on STM32_TIM -if SCHED_TICKLESS - -config STM32_TICKLESS_TIMER - int "Tickless hardware timer" - default 2 - range 1 14 - ---help--- - If the Tickless OS feature is enabled, then one clock must be - assigned to provided the timer needed by the OS. - -config STM32_TICKLESS_CHANNEL - int "Tickless timer channel" - default 1 - range 1 4 - ---help--- - If the Tickless OS feature is enabled, the one clock must be - assigned to provided the free-running timer needed by the OS - and one channel on that clock is needed to handle intervals. - -endif # SCHED_TICKLESS - -config STM32_ONESHOT - bool "TIM one-shot wrapper" - default n - ---help--- - Enable a wrapper around the low level timer/counter functions to - support one-shot timer. - -config STM32_FREERUN - bool "TIM free-running wrapper" - default n - ---help--- - Enable a wrapper around the low level timer/counter functions to - support a free-running timer. - -config STM32_ONESHOT_MAXTIMERS - int "Maximum number of oneshot timers" - default 1 - range 1 8 - depends on STM32_ONESHOT - ---help--- - Determines the maximum number of oneshot timers that can be - supported. This setting pre-allocates some minimal support for each - of the timers and places an upper limit on the number of oneshot - timers that you can use. - -config STM32_PWM_LL_OPS - bool "PWM low-level operations" - default n - ---help--- - Enable low-level PWM ops. - -config STM32_TIM1_PWM - bool "TIM1 PWM" - default n - depends on STM32_TIM1 - select STM32_PWM - ---help--- - Reserve timer 1 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32_TIM1 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32_TIM1_PWM - -config STM32_TIM1_MODE - int "TIM1 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -config STM32_TIM1_LOCK - int "TIM1 Lock Level Configuration" - default 0 - range 0 3 - ---help--- - Timer 1 lock level configuration - -config STM32_TIM1_TDTS - int "TIM1 t_DTS Division" - default 0 - range 0 2 - ---help--- - Timer 1 dead-time and sampling clock (t_DTS) division - -config STM32_TIM1_DEADTIME - int "TIM1 Initial Dead-time" - default 0 - range 0 255 - ---help--- - Timer 1 initial dead-time - -if STM32_PWM_MULTICHAN - -config STM32_TIM1_CHANNEL1 - bool "TIM1 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32_TIM1_CHANNEL1 - -config STM32_TIM1_CH1MODE - int "TIM1 Channel 1 Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM1_CH1OUT - bool "TIM1 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32_TIM1_CH1NOUT - bool "TIM1 Channel 1 Complementary Output" - default n - ---help--- - Enables channel 1 Complementary Output. - -endif # STM32_TIM1_CHANNEL1 - -config STM32_TIM1_CHANNEL2 - bool "TIM1 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32_TIM1_CHANNEL2 - -config STM32_TIM1_CH2MODE - int "TIM1 Channel 2 Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM1_CH2OUT - bool "TIM1 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -config STM32_TIM1_CH2NOUT - bool "TIM1 Channel 2 Complementary Output" - default n - ---help--- - Enables channel 2 Complementary Output. - -endif # STM32_TIM1_CHANNEL2 - -config STM32_TIM1_CHANNEL3 - bool "TIM1 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32_TIM1_CHANNEL3 - -config STM32_TIM1_CH3MODE - int "TIM1 Channel 3 Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM1_CH3OUT - bool "TIM1 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -config STM32_TIM1_CH3NOUT - bool "TIM1 Channel 3 Complementary Output" - default n - ---help--- - Enables channel 3 Complementary Output. - -endif # STM32_TIM1_CHANNEL3 - -config STM32_TIM1_CHANNEL4 - bool "TIM1 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32_TIM1_CHANNEL4 - -config STM32_TIM1_CH4MODE - int "TIM1 Channel 4 Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM1_CH4OUT - bool "TIM1 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32_TIM1_CHANNEL4 - -config STM32_TIM1_CHANNEL5 - bool "TIM1 Channel 5 (internal)" - default n - depends on STM32_HAVE_IP_TIMERS_V2 - ---help--- - Enables channel 5 (not available externally) - -if STM32_TIM1_CHANNEL5 - -config STM32_TIM1_CH5MODE - int "TIM1 Channel 5 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM1_CH5OUT - bool "TIM1 Channel 5 Output" - default n - ---help--- - Enables channel 5 output. - -endif # STM32_TIM1_CHANNEL5 - -config STM32_TIM1_CHANNEL6 - bool "TIM1 Channel 6 (internal)" - default n - depends on STM32_HAVE_IP_TIMERS_V2 - ---help--- - Enables channel 6 (not available externally) - -if STM32_TIM1_CHANNEL6 - -config STM32_TIM1_CH6MODE - int "TIM1 Channel 6 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM1_CH6OUT - bool "TIM1 Channel 6 Output" - default n - ---help--- - Enables channel 6 output. - -endif # STM32_TIM1_CHANNEL6 - -endif # STM32_PWM_MULTICHAN - -if !STM32_PWM_MULTICHAN - -config STM32_TIM1_CHANNEL - int "TIM1 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM1 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -if STM32_TIM1_CHANNEL = 1 - -config STM32_TIM1_CH1OUT - bool "TIM1 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32_TIM1_CH1NOUT - bool "TIM1 Channel 1 Complementary Output" - default n - ---help--- - Enables channel 1 Complementary Output. - -endif # STM32_TIM1_CHANNEL = 1 - -if STM32_TIM1_CHANNEL = 2 - -config STM32_TIM1_CH2OUT - bool "TIM1 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -config STM32_TIM1_CH2NOUT - bool "TIM1 Channel 2 Complementary Output" - default n - ---help--- - Enables channel 2 Complementary Output. - -endif # STM32_TIM1_CHANNEL = 2 - -if STM32_TIM1_CHANNEL = 3 - -config STM32_TIM1_CH3OUT - bool "TIM1 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -config STM32_TIM1_CH3NOUT - bool "TIM1 Channel 3 Complementary Output" - default n - ---help--- - Enables channel 3 Complementary Output. - -endif # STM32_TIM1_CHANNEL = 3 - -if STM32_TIM1_CHANNEL = 4 - -config STM32_TIM1_CH4OUT - bool "TIM1 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32_TIM1_CHANNEL = 4 - -config STM32_TIM1_CHMODE - int "TIM1 Channel Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32_PWM_MULTICHAN - -endif # STM32_TIM1_PWM - -config STM32_TIM2_PWM - bool "TIM2 PWM" - default n - depends on STM32_TIM2 - select STM32_PWM - ---help--- - Reserve timer 2 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32_TIM2 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32_TIM2_PWM - -config STM32_TIM2_MODE - int "TIM2 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -if STM32_PWM_MULTICHAN - -config STM32_TIM2_CHANNEL1 - bool "TIM2 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32_TIM2_CHANNEL1 - -config STM32_TIM2_CH1MODE - int "TIM2 Channel 1 Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM2_CH1OUT - bool "TIM2 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32_TIM2_CHANNEL1 - -config STM32_TIM2_CHANNEL2 - bool "TIM2 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32_TIM2_CHANNEL2 - -config STM32_TIM2_CH2MODE - int "TIM2 Channel 2 Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM2_CH2OUT - bool "TIM2 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32_TIM2_CHANNEL2 - -config STM32_TIM2_CHANNEL3 - bool "TIM2 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32_TIM2_CHANNEL3 - -config STM32_TIM2_CH3MODE - int "TIM2 Channel 3 Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM2_CH3OUT - bool "TIM2 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32_TIM2_CHANNEL3 - -config STM32_TIM2_CHANNEL4 - bool "TIM2 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32_TIM2_CHANNEL4 - -config STM32_TIM2_CH4MODE - int "TIM2 Channel 4 Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM2_CH4OUT - bool "TIM2 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32_TIM2_CHANNEL4 - -endif # STM32_PWM_MULTICHAN - -if !STM32_PWM_MULTICHAN - -config STM32_TIM2_CHANNEL - int "TIM2 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM2 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -if STM32_TIM2_CHANNEL = 1 - -config STM32_TIM2_CH1OUT - bool "TIM2 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32_TIM2_CHANNEL = 1 - -if STM32_TIM2_CHANNEL = 2 - -config STM32_TIM2_CH2OUT - bool "TIM2 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32_TIM2_CHANNEL = 2 - -if STM32_TIM2_CHANNEL = 3 - -config STM32_TIM2_CH3OUT - bool "TIM2 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32_TIM2_CHANNEL = 3 - -if STM32_TIM2_CHANNEL = 4 - -config STM32_TIM2_CH4OUT - bool "TIM2 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32_TIM2_CHANNEL = 4 - -config STM32_TIM2_CHMODE - int "TIM2 Channel Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32_PWM_MULTICHAN - -endif # STM32_TIM2_PWM - -config STM32_TIM3_PWM - bool "TIM3 PWM" - default n - depends on STM32_TIM3 - select STM32_PWM - ---help--- - Reserve timer 3 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32_TIM3 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32_TIM3_PWM - -config STM32_TIM3_MODE - int "TIM3 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -if STM32_PWM_MULTICHAN - -config STM32_TIM3_CHANNEL1 - bool "TIM3 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32_TIM3_CHANNEL1 - -config STM32_TIM3_CH1MODE - int "TIM3 Channel 1 Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM3_CH1OUT - bool "TIM3 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32_TIM3_CHANNEL1 - -config STM32_TIM3_CHANNEL2 - bool "TIM3 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32_TIM3_CHANNEL2 - -config STM32_TIM3_CH2MODE - int "TIM3 Channel 2 Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM3_CH2OUT - bool "TIM3 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32_TIM3_CHANNEL2 - -config STM32_TIM3_CHANNEL3 - bool "TIM3 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32_TIM3_CHANNEL3 - -config STM32_TIM3_CH3MODE - int "TIM3 Channel 3 Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM3_CH3OUT - bool "TIM3 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32_TIM3_CHANNEL3 - -config STM32_TIM3_CHANNEL4 - bool "TIM3 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32_TIM3_CHANNEL4 - -config STM32_TIM3_CH4MODE - int "TIM3 Channel 4 Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM3_CH4OUT - bool "TIM3 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32_TIM3_CHANNEL4 - -endif # STM32_PWM_MULTICHAN - -if !STM32_PWM_MULTICHAN - -config STM32_TIM3_CHANNEL - int "TIM3 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM3 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -if STM32_TIM3_CHANNEL = 1 - -config STM32_TIM3_CH1OUT - bool "TIM3 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32_TIM3_CHANNEL = 1 - -if STM32_TIM3_CHANNEL = 2 - -config STM32_TIM3_CH2OUT - bool "TIM3 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32_TIM3_CHANNEL = 2 - -if STM32_TIM3_CHANNEL = 3 - -config STM32_TIM3_CH3OUT - bool "TIM3 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32_TIM3_CHANNEL = 3 - -if STM32_TIM3_CHANNEL = 4 - -config STM32_TIM3_CH4OUT - bool "TIM3 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32_TIM3_CHANNEL = 4 - -config STM32_TIM3_CHMODE - int "TIM3 Channel Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32_PWM_MULTICHAN - -endif # STM32_TIM3_PWM - -config STM32_TIM4_PWM - bool "TIM4 PWM" - default n - depends on STM32_TIM4 - select STM32_PWM - ---help--- - Reserve timer 4 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32_TIM4 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32_TIM4_PWM - -config STM32_TIM4_MODE - int "TIM4 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -if STM32_PWM_MULTICHAN - -config STM32_TIM4_CHANNEL1 - bool "TIM4 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32_TIM4_CHANNEL1 - -config STM32_TIM4_CH1MODE - int "TIM4 Channel 1 Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM4_CH1OUT - bool "TIM4 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32_TIM4_CHANNEL1 - -config STM32_TIM4_CHANNEL2 - bool "TIM4 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32_TIM4_CHANNEL2 - -config STM32_TIM4_CH2MODE - int "TIM4 Channel 2 Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM4_CH2OUT - bool "TIM4 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32_TIM4_CHANNEL2 - -config STM32_TIM4_CHANNEL3 - bool "TIM4 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32_TIM4_CHANNEL3 - -config STM32_TIM4_CH3MODE - int "TIM4 Channel 3 Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM4_CH3OUT - bool "TIM4 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32_TIM4_CHANNEL3 - -config STM32_TIM4_CHANNEL4 - bool "TIM4 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32_TIM4_CHANNEL4 - -config STM32_TIM4_CH4MODE - int "TIM4 Channel 4 Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM4_CH4OUT - bool "TIM4 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32_TIM4_CHANNEL4 - -endif # STM32_PWM_MULTICHAN - -if !STM32_PWM_MULTICHAN - -config STM32_TIM4_CHANNEL - int "TIM4 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM4 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -if STM32_TIM4_CHANNEL = 1 - -config STM32_TIM4_CH1OUT - bool "TIM4 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32_TIM4_CHANNEL = 1 - -if STM32_TIM4_CHANNEL = 2 - -config STM32_TIM4_CH2OUT - bool "TIM4 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32_TIM4_CHANNEL = 2 - -if STM32_TIM4_CHANNEL = 3 - -config STM32_TIM4_CH3OUT - bool "TIM4 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32_TIM4_CHANNEL = 3 - -if STM32_TIM4_CHANNEL = 4 - -config STM32_TIM4_CH4OUT - bool "TIM4 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32_TIM4_CHANNEL = 4 - -config STM32_TIM4_CHMODE - int "TIM4 Channel Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32_PWM_MULTICHAN - -endif # STM32_TIM4_PWM - -config STM32_TIM5_PWM - bool "TIM5 PWM" - default n - depends on STM32_TIM5 - select STM32_PWM - ---help--- - Reserve timer 5 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32_TIM5 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32_TIM5_PWM - -config STM32_TIM5_MODE - int "TIM5 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -if STM32_PWM_MULTICHAN - -config STM32_TIM5_CHANNEL1 - bool "TIM5 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32_TIM5_CHANNEL1 - -config STM32_TIM5_CH1MODE - int "TIM5 Channel 1 Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM5_CH1OUT - bool "TIM5 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32_TIM5_CHANNEL1 - -config STM32_TIM5_CHANNEL2 - bool "TIM5 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32_TIM5_CHANNEL2 - -config STM32_TIM5_CH2MODE - int "TIM5 Channel 2 Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM5_CH2OUT - bool "TIM5 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32_TIM5_CHANNEL2 - -config STM32_TIM5_CHANNEL3 - bool "TIM5 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32_TIM5_CHANNEL3 - -config STM32_TIM5_CH3MODE - int "TIM5 Channel 3 Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM5_CH3OUT - bool "TIM5 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32_TIM5_CHANNEL3 - -config STM32_TIM5_CHANNEL4 - bool "TIM5 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32_TIM5_CHANNEL4 - -config STM32_TIM5_CH4MODE - int "TIM5 Channel 4 Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM5_CH4OUT - bool "TIM5 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32_TIM5_CHANNEL4 - -endif # STM32_PWM_MULTICHAN - -if !STM32_PWM_MULTICHAN - -config STM32_TIM5_CHANNEL - int "TIM5 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM5 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -if STM32_TIM5_CHANNEL = 1 - -config STM32_TIM5_CH1OUT - bool "TIM5 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32_TIM5_CHANNEL = 1 - -if STM32_TIM5_CHANNEL = 2 - -config STM32_TIM5_CH2OUT - bool "TIM5 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32_TIM5_CHANNEL = 2 - -if STM32_TIM5_CHANNEL = 3 - -config STM32_TIM5_CH3OUT - bool "TIM5 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32_TIM5_CHANNEL = 3 - -if STM32_TIM5_CHANNEL = 4 - -config STM32_TIM5_CH4OUT - bool "TIM5 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32_TIM5_CHANNEL = 4 - -config STM32_TIM5_CHMODE - int "TIM5 Channel Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32_PWM_MULTICHAN - -endif # STM32_TIM5_PWM - -config STM32_TIM8_PWM - bool "TIM8 PWM" - default n - depends on STM32_TIM8 - select STM32_PWM - ---help--- - Reserve timer 8 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32_TIM8 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32_TIM8_PWM - -config STM32_TIM8_MODE - int "TIM8 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -config STM32_TIM8_LOCK - int "TIM8 Lock Level Configuration" - default 0 - range 0 3 - ---help--- - Timer 8 lock level configuration - -config STM32_TIM8_DEADTIME - int "TIM8 Initial Dead-time" - default 0 - range 0 255 - ---help--- - Timer 8 initial dead-time - -config STM32_TIM8_TDTS - int "TIM8 t_DTS Division" - default 0 - range 0 2 - ---help--- - Timer 8 dead-time and sampling clock (t_DTS) division - -if STM32_PWM_MULTICHAN - -config STM32_TIM8_CHANNEL1 - bool "TIM8 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32_TIM8_CHANNEL1 - -config STM32_TIM8_CH1MODE - int "TIM8 Channel 1 Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM8_CH1OUT - bool "TIM8 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32_TIM8_CH1NOUT - bool "TIM8 Channel 1 Complementary Output" - default n - ---help--- - Enables channel 1 Complementary Output. - -endif # STM32_TIM8_CHANNEL1 - -config STM32_TIM8_CHANNEL2 - bool "TIM8 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32_TIM8_CHANNEL2 - -config STM32_TIM8_CH2MODE - int "TIM8 Channel 2 Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM8_CH2OUT - bool "TIM8 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -config STM32_TIM8_CH2NOUT - bool "TIM8 Channel 2 Complementary Output" - default n - ---help--- - Enables channel 2 Complementary Output. - -endif # STM32_TIM8_CHANNEL2 - -config STM32_TIM8_CHANNEL3 - bool "TIM8 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32_TIM8_CHANNEL3 - -config STM32_TIM8_CH3MODE - int "TIM8 Channel 3 Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM8_CH3OUT - bool "TIM8 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -config STM32_TIM8_CH3NOUT - bool "TIM8 Channel 3 Complementary Output" - default n - ---help--- - Enables channel 3 Complementary Output. - -endif # STM32_TIM8_CHANNEL3 - -config STM32_TIM8_CHANNEL4 - bool "TIM8 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32_TIM8_CHANNEL4 - -config STM32_TIM8_CH4MODE - int "TIM8 Channel 4 Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM8_CH4OUT - bool "TIM8 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32_TIM8_CHANNEL4 - -config STM32_TIM8_CHANNEL5 - bool "TIM8 Channel 5 (internal)" - default n - depends on STM32_HAVE_IP_TIMERS_V2 - ---help--- - Enables channel 5 (not available externally) - -if STM32_TIM8_CHANNEL5 - -config STM32_TIM8_CH5MODE - int "TIM8 Channel 5 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM8_CH5OUT - bool "TIM8 Channel 5 Output" - default n - ---help--- - Enables channel 5 output. - -endif # STM32_TIM8_CHANNEL5 - -config STM32_TIM8_CHANNEL6 - bool "TIM8 Channel 6 (internal)" - default n - depends on STM32_HAVE_IP_TIMERS_V2 - ---help--- - Enables channel 6 (not available externally) - -if STM32_TIM8_CHANNEL6 - -config STM32_TIM8_CH6MODE - int "TIM8 Channel 6 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM8_CH6OUT - bool "TIM8 Channel 6 Output" - default n - ---help--- - Enables channel 6 output. - -endif # STM32_TIM8_CHANNEL6 - -endif # STM32_PWM_MULTICHAN - -if !STM32_PWM_MULTICHAN - -config STM32_TIM8_CHANNEL - int "TIM8 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM8 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -if STM32_TIM8_CHANNEL = 1 - -config STM32_TIM8_CH1OUT - bool "TIM8 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32_TIM8_CH1NOUT - bool "TIM8 Channel 1 Complementary Output" - default n - ---help--- - Enables channel 1 Complementary Output. - -endif # STM32_TIM8_CHANNEL = 1 - -if STM32_TIM8_CHANNEL = 2 - -config STM32_TIM8_CH2OUT - bool "TIM8 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -config STM32_TIM8_CH2NOUT - bool "TIM8 Channel 2 Complementary Output" - default n - ---help--- - Enables channel 2 Complementary Output. - -endif # STM32_TIM8_CHANNEL = 2 - -if STM32_TIM8_CHANNEL = 3 - -config STM32_TIM8_CH3OUT - bool "TIM8 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -config STM32_TIM8_CH3NOUT - bool "TIM8 Channel 3 Complementary Output" - default n - ---help--- - Enables channel 3 Complementary Output. - -endif # STM32_TIM8_CHANNEL = 3 - -if STM32_TIM8_CHANNEL = 4 - -config STM32_TIM8_CH4OUT - bool "TIM8 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32_TIM8_CHANNEL = 4 - -config STM32_TIM8_CHMODE - int "TIM8 Channel Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32_PWM_MULTICHAN - -endif # STM32_TIM8_PWM - -config STM32_TIM9_PWM - bool "TIM9 PWM" - default n - depends on STM32_TIM9 - select STM32_PWM - ---help--- - Reserve timer 9 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32_TIM9 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32_TIM9_PWM - -if STM32_PWM_MULTICHAN - -config STM32_TIM9_CHANNEL1 - bool "TIM9 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32_TIM9_CHANNEL1 - -config STM32_TIM9_CH1MODE - int "TIM9 Channel 1 Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM9_CH1OUT - bool "TIM9 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32_TIM9_CHANNEL1 - -config STM32_TIM9_CHANNEL2 - bool "TIM9 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32_TIM9_CHANNEL2 - -config STM32_TIM9_CH2MODE - int "TIM9 Channel 2 Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM9_CH2OUT - bool "TIM9 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32_TIM9_CHANNEL2 - -endif # STM32_PWM_MULTICHAN - -if !STM32_PWM_MULTICHAN - -config STM32_TIM9_CHANNEL - int "TIM9 PWM Output Channel" - default 1 - range 1 2 - ---help--- - If TIM9 is enabled for PWM usage, you also need specifies the timer output - channel {1,2} - -if STM32_TIM9_CHANNEL = 1 - -config STM32_TIM9_CH1OUT - bool "TIM9 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32_TIM9_CHANNEL = 1 - -if STM32_TIM9_CHANNEL = 2 - -config STM32_TIM9_CH2OUT - bool "TIM9 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32_TIM9_CHANNEL = 2 - -config STM32_TIM9_CHMODE - int "TIM9 Channel Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32_PWM_MULTICHAN - -endif # STM32_TIM9_PWM - -config STM32_TIM10_PWM - bool "TIM10 PWM" - default n - depends on STM32_TIM10 - select STM32_PWM - ---help--- - Reserve timer 10 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32_TIM10 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32_TIM10_PWM - -if STM32_PWM_MULTICHAN - -config STM32_TIM10_CHANNEL1 - bool "TIM10 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32_TIM10_CHANNEL1 - -config STM32_TIM10_CH1MODE - int "TIM10 Channel 1 Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM10_CH1OUT - bool "TIM10 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32_TIM10_CHANNEL1 - -endif # STM32_PWM_MULTICHAN - -if !STM32_PWM_MULTICHAN - -config STM32_TIM10_CHANNEL - int "TIM10 PWM Output Channel" - default 1 - range 1 1 - ---help--- - If TIM10 is enabled for PWM usage, you also need specifies the timer output - channel {1} - -if STM32_TIM10_CHANNEL = 1 - -config STM32_TIM10_CH1OUT - bool "TIM10 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32_TIM10_CHANNEL = 1 - -config STM32_TIM10_CHMODE - int "TIM10 Channel Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32_PWM_MULTICHAN - -endif # STM32_TIM10_PWM - -config STM32_TIM11_PWM - bool "TIM11 PWM" - default n - depends on STM32_TIM11 - select STM32_PWM - ---help--- - Reserve timer 11 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32_TIM11 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32_TIM11_PWM - -if STM32_PWM_MULTICHAN - -config STM32_TIM11_CHANNEL1 - bool "TIM11 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32_TIM11_CHANNEL1 - -config STM32_TIM11_CH1MODE - int "TIM11 Channel 1 Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM11_CH1OUT - bool "TIM11 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32_TIM11_CHANNEL1 - -endif # STM32_PWM_MULTICHAN - -if !STM32_PWM_MULTICHAN - -config STM32_TIM11_CHANNEL - int "TIM11 PWM Output Channel" - default 1 - range 1 1 - ---help--- - If TIM11 is enabled for PWM usage, you also need specifies the timer output - channel {1} - -if STM32_TIM11_CHANNEL = 1 - -config STM32_TIM11_CH1OUT - bool "TIM11 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32_TIM11_CHANNEL = 1 - -config STM32_TIM11_CHMODE - int "TIM11 Channel Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32_PWM_MULTICHAN - -endif # STM32_TIM11_PWM - -config STM32_TIM12_PWM - bool "TIM12 PWM" - default n - depends on STM32_TIM12 - select STM32_PWM - ---help--- - Reserve timer 12 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32_TIM12 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32_TIM12_PWM - -if STM32_PWM_MULTICHAN - -config STM32_TIM12_CHANNEL1 - bool "TIM12 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32_TIM12_CHANNEL1 - -config STM32_TIM12_CH1MODE - int "TIM12 Channel 1 Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM12_CH1OUT - bool "TIM12 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32_TIM12_CHANNEL1 - -config STM32_TIM12_CHANNEL2 - bool "TIM12 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32_TIM12_CHANNEL2 - -config STM32_TIM12_CH2MODE - int "TIM12 Channel 2 Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM12_CH2OUT - bool "TIM12 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32_TIM12_CHANNEL2 - -endif # STM32_PWM_MULTICHAN - -if !STM32_PWM_MULTICHAN - -config STM32_TIM12_CHANNEL - int "TIM12 PWM Output Channel" - default 1 - range 1 2 - ---help--- - If TIM12 is enabled for PWM usage, you also need specifies the timer output - channel {1,2} - -if STM32_TIM12_CHANNEL = 1 - -config STM32_TIM12_CH1OUT - bool "TIM12 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32_TIM12_CHANNEL = 1 - -if STM32_TIM12_CHANNEL = 2 - -config STM32_TIM12_CH2OUT - bool "TIM12 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32_TIM12_CHANNEL = 2 - -config STM32_TIM12_CHMODE - int "TIM12 Channel Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32_PWM_MULTICHAN - -endif # STM32_TIM12_PWM - -config STM32_TIM13_PWM - bool "TIM13 PWM" - default n - depends on STM32_TIM13 - select STM32_PWM - ---help--- - Reserve timer 13 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32_TIM13 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32_TIM13_PWM - -if STM32_PWM_MULTICHAN - -config STM32_TIM13_CHANNEL1 - bool "TIM13 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32_TIM13_CHANNEL1 - -config STM32_TIM13_CH1MODE - int "TIM13 Channel 1 Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM13_CH1OUT - bool "TIM13 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32_TIM13_CHANNEL1 - -endif # STM32_PWM_MULTICHAN - -if !STM32_PWM_MULTICHAN - -config STM32_TIM13_CHANNEL - int "TIM13 PWM Output Channel" - default 1 - range 1 1 - ---help--- - If TIM13 is enabled for PWM usage, you also need specifies the timer output - channel {1} - -if STM32_TIM13_CHANNEL = 1 - -config STM32_TIM13_CH1OUT - bool "TIM13 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32_TIM13_CHANNEL = 1 - -config STM32_TIM13_CHMODE - int "TIM13 Channel Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32_PWM_MULTICHAN - -endif # STM32_TIM13_PWM - -config STM32_TIM14_PWM - bool "TIM14 PWM" - default n - depends on STM32_TIM14 - select STM32_PWM - ---help--- - Reserve timer 14 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32_TIM14 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32_TIM14_PWM - -if STM32_PWM_MULTICHAN - -config STM32_TIM14_CHANNEL1 - bool "TIM14 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32_TIM14_CHANNEL1 - -config STM32_TIM14_CH1MODE - int "TIM14 Channel 1 Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM14_CH1OUT - bool "TIM14 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32_TIM14_CHANNEL1 - -endif # STM32_PWM_MULTICHAN - -if !STM32_PWM_MULTICHAN - -config STM32_TIM14_CHANNEL - int "TIM14 PWM Output Channel" - default 1 - range 1 1 - ---help--- - If TIM14 is enabled for PWM usage, you also need specifies the timer output - channel {1} - -if STM32_TIM14_CHANNEL = 1 - -config STM32_TIM14_CH1OUT - bool "TIM14 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32_TIM14_CHANNEL = 1 - -config STM32_TIM14_CHMODE - int "TIM14 Channel Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32_PWM_MULTICHAN - -endif # STM32_TIM14_PWM - -config STM32_TIM15_PWM - bool "TIM15 PWM" - default n - depends on STM32_TIM15 - select STM32_PWM - ---help--- - Reserve timer 15 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32_TIM15 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32_TIM15_PWM - -config STM32_TIM15_LOCK - int "TIM15 Lock Level Configuration" - default 0 - range 0 3 - ---help--- - Timer 15 lock level configuration - -config STM32_TIM15_TDTS - int "TIM15 t_DTS Division" - default 0 - range 0 2 - ---help--- - Timer 15 dead-time and sampling clock (t_DTS) division - -config STM32_TIM15_DEADTIME - int "TIM15 Initial Dead-time" - default 0 - range 0 255 - ---help--- - Timer 15 initial dead-time - -if STM32_PWM_MULTICHAN - -config STM32_TIM15_CHANNEL1 - bool "TIM15 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32_TIM15_CHANNEL1 - -config STM32_TIM15_CH1MODE - int "TIM15 Channel 1 Mode" - default 6 - range 0 9 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM15_CH1OUT - bool "TIM15 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32_TIM15_CH1NOUT - bool "TIM15 Channel 1 Complementary Output" - default n - ---help--- - Enables channel 1 Complementary Output. - -endif # STM32_TIM15_CHANNEL1 - -config STM32_TIM15_CHANNEL2 - bool "TIM15 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32_TIM15_CHANNEL2 - -config STM32_TIM15_CH2MODE - int "TIM15 Channel 2 Mode" - default 6 - range 0 9 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM15_CH2OUT - bool "TIM15 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32_TIM15_CHANNEL2 - -endif # STM32_PWM_MULTICHAN - -if !STM32_PWM_MULTICHAN - -config STM32_TIM15_CHANNEL - int "TIM15 PWM Output Channel" - default 1 - range 1 2 - ---help--- - If TIM15 is enabled for PWM usage, you also need specifies the timer output - channel {1,2} - -if STM32_TIM15_CHANNEL = 1 - -config STM32_TIM15_CH1OUT - bool "TIM15 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32_TIM15_CH1NOUT - bool "TIM15 Channel 1 Complementary Output" - default n - ---help--- - Enables channel 1 Complementary Output. - -endif # STM32_TIM15_CHANNEL = 1 - -if STM32_TIM15_CHANNEL = 2 - -config STM32_TIM15_CH2OUT - bool "TIM15 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -config STM32_TIM15_CH2NOUT - bool "TIM15 Channel 2 Complementary Output" - default n - ---help--- - Enables channel 2 Complementary Output. - -endif # STM32_TIM15_CHANNEL = 2 - -config STM32_TIM15_CHMODE - int "TIM15 Channel Mode" - default 6 - range 0 9 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32_PWM_MULTICHAN - -endif # STM32_TIM15_PWM - -config STM32_TIM16_PWM - bool "TIM16 PWM" - default n - depends on STM32_TIM16 - select STM32_PWM - ---help--- - Reserve timer 16 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32_TIM16 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32_TIM16_PWM - -config STM32_TIM16_LOCK - int "TIM16 Lock Level Configuration" - default 0 - range 0 3 - ---help--- - Timer 16 lock level configuration - -config STM32_TIM16_TDTS - int "TIM16 t_DTS division" - default 0 - range 0 2 - ---help--- - Timer 16 dead-time and sampling clock (t_DTS) division - -config STM32_TIM16_DEADTIME - int "TIM16 Initial Dead-time" - default 0 - range 0 255 - ---help--- - Timer 16 initial dead-time - -if STM32_PWM_MULTICHAN - -config STM32_TIM16_CHANNEL1 - bool "TIM16 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32_TIM16_CHANNEL1 - -config STM32_TIM16_CH1MODE - int "TIM16 Channel 1 Mode" - default 6 - range 0 7 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM16_CH1OUT - bool "TIM16 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32_TIM16_CHANNEL1 - -endif # STM32_PWM_MULTICHAN - -if !STM32_PWM_MULTICHAN - -config STM32_TIM16_CHANNEL - int "TIM16 PWM Output Channel" - default 1 - range 1 1 - ---help--- - If TIM16 is enabled for PWM usage, you also need specifies the timer output - channel {1} - -if STM32_TIM16_CHANNEL = 1 - -config STM32_TIM16_CH1OUT - bool "TIM16 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32_TIM16_CHANNEL = 1 - -config STM32_TIM16_CHMODE - int "TIM16 Channel Mode" - default 6 - range 0 7 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32_PWM_MULTICHAN - -endif # STM32_TIM16_PWM - -config STM32_TIM17_PWM - bool "TIM17 PWM" - default n - depends on STM32_TIM17 - select STM32_PWM - ---help--- - Reserve timer 17 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32_TIM17 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32_TIM17_PWM - -config STM32_TIM17_LOCK - int "TIM17 Lock Level Configuration" - default 0 - range 0 3 - ---help--- - Timer 17 lock level configuration - -config STM32_TIM17_TDTS - int "TIM17 t_DTS Division" - default 0 - range 0 2 - ---help--- - Timer 17 dead-time and sampling clock (t_DTS) division - -config STM32_TIM17_DEADTIME - int "TIM17 Initial Dead-time" - default 0 - range 0 255 - ---help--- - Timer 17 initial dead-time - -if STM32_PWM_MULTICHAN - -config STM32_TIM17_CHANNEL1 - bool "TIM17 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32_TIM17_CHANNEL1 - -config STM32_TIM17_CH1MODE - int "TIM17 Channel 1 Mode" - default 6 - range 0 7 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM17_CH1OUT - bool "TIM17 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32_TIM17_CHANNEL1 - -endif # STM32_PWM_MULTICHAN - -if !STM32_PWM_MULTICHAN - -config STM32_TIM17_CHANNEL - int "TIM17 PWM Output Channel" - default 1 - range 1 1 - ---help--- - If TIM17 is enabled for PWM usage, you also need specifies the timer output - channel {1} - -if STM32_TIM17_CHANNEL = 1 - -config STM32_TIM17_CH1OUT - bool "TIM17 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32_TIM17_CHANNEL = 1 - -config STM32_TIM17_CHMODE - int "TIM17 Channel Mode" - default 6 - range 0 7 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32_PWM_MULTICHAN - -endif # STM32_TIM17_PWM - -config STM32_PWM_MULTICHAN - bool "PWM Multiple Output Channels" - default n - depends on STM32_PWM - ---help--- - Specifies that the PWM driver supports multiple output - channels per timer. - -config STM32_PWM_TRGO - bool "TIM PWM TRGO support" - default n - depends on STM32_PWM - ---help--- - Enable TRGO support for PWM driver - -config STM32_PULSECOUNT - bool - default n - select ARCH_HAVE_PULSECOUNT - select PULSECOUNT - -config STM32_TIM1_PULSECOUNT - bool "TIM1 pulse count" - default n - depends on STM32_TIM1 - select STM32_PULSECOUNT - ---help--- - Reserve timer 1 for pulse count output. - -if STM32_TIM1_PULSECOUNT - -config STM32_TIM1_PULSECOUNT_TDTS - int "TIM1 pulse count clock division" - default 0 - range 0 2 - -config STM32_TIM1_PULSECOUNT_CHANNEL - int "TIM1 pulse count channel" - default 1 - range 1 4 - ---help--- - Specifies the timer channel {1,..,4}. - -config STM32_TIM1_PULSECOUNT_POL - int "TIM1 pulse count output polarity" - default 0 - range 0 1 - -config STM32_TIM1_PULSECOUNT_IDLE - int "TIM1 pulse count idle state" - default 0 - range 0 1 - -endif # STM32_TIM1_PULSECOUNT - -config STM32_TIM8_PULSECOUNT - bool "TIM8 pulse count" - default n - depends on STM32_TIM8 - select STM32_PULSECOUNT - ---help--- - Reserve timer 8 for pulse count output. - -if STM32_TIM8_PULSECOUNT - -config STM32_TIM8_PULSECOUNT_TDTS - int "TIM8 pulse count clock division" - default 0 - range 0 2 - -config STM32_TIM8_PULSECOUNT_CHANNEL - int "TIM8 pulse count channel" - default 1 - range 1 4 - ---help--- - Specifies the timer channel {1,..,4}. - -config STM32_TIM8_PULSECOUNT_POL - int "TIM8 pulse count output polarity" - default 0 - range 0 1 - -config STM32_TIM8_PULSECOUNT_IDLE - int "TIM8 pulse count idle state" - default 0 - range 0 1 - -endif # STM32_TIM8_PULSECOUNT -config STM32_TIM1_ADC - bool "TIM1 ADC" - default n - depends on STM32_TIM1 && STM32_ADC - ---help--- - Reserve timer 1 for use by ADC - - Timer devices may be used for different purposes. If STM32_TIM1 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -config STM32_TIM2_ADC - bool "TIM2 ADC" - default n - depends on STM32_TIM2 && STM32_ADC - ---help--- - Reserve timer 1 for use by ADC - - Timer devices may be used for different purposes. If STM32_TIM2 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -config STM32_TIM3_ADC - bool "TIM3 ADC" - default n - depends on STM32_TIM3 && STM32_ADC - ---help--- - Reserve timer 1 for use by ADC - - Timer devices may be used for different purposes. If STM32_TIM3 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -config STM32_TIM4_ADC - bool "TIM4 ADC" - default n - depends on STM32_TIM4 && STM32_ADC - ---help--- - Reserve timer 1 for use by ADC - - Timer devices may be used for different purposes. If STM32_TIM4 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -config STM32_TIM5_ADC - bool "TIM5 ADC" - default n - depends on STM32_TIM5 && STM32_ADC - ---help--- - Reserve timer 1 for use by ADC - - Timer devices may be used for different purposes. If STM32_TIM5 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -config STM32_TIM8_ADC - bool "TIM8 ADC" - default n - depends on STM32_TIM8 && STM32_ADC - ---help--- - Reserve timer 1 for use by ADC - - Timer devices may be used for different purposes. If STM32_TIM8 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -config STM32_HAVE_ADC1_TIMER - bool - -config STM32_HAVE_ADC2_TIMER - bool - -config STM32_HAVE_ADC3_TIMER - bool - -config STM32_HAVE_ADC4_TIMER - bool - -config STM32_HAVE_ADC5_TIMER - bool - -config STM32_ADC1_SAMPLE_FREQUENCY - int "ADC1 Sampling Frequency" - default 100 - depends on STM32_HAVE_ADC1_TIMER - ---help--- - ADC1 sampling frequency. Default: 100Hz - -config STM32_ADC1_TIMTRIG - int "ADC1 Timer Trigger" - default 0 - range 0 5 - depends on STM32_HAVE_ADC1_TIMER - ---help--- - Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO 5:TRGO2 - -config STM32_ADC2_SAMPLE_FREQUENCY - int "ADC2 Sampling Frequency" - default 100 - depends on STM32_HAVE_ADC2_TIMER - ---help--- - ADC2 sampling frequency. Default: 100Hz - -config STM32_ADC2_TIMTRIG - int "ADC2 Timer Trigger" - default 0 - range 0 5 - depends on STM32_HAVE_ADC2_TIMER - ---help--- - Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO 5:TRGO2 - -config STM32_ADC3_SAMPLE_FREQUENCY - int "ADC3 Sampling Frequency" - default 100 - depends on STM32_HAVE_ADC3_TIMER - ---help--- - ADC3 sampling frequency. Default: 100Hz - -config STM32_ADC3_TIMTRIG - int "ADC3 Timer Trigger" - default 0 - range 0 5 - depends on STM32_HAVE_ADC3_TIMER - ---help--- - Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO 5:TRGO2 - -config STM32_TIM1_DAC - bool "TIM1 DAC" - default n - depends on STM32_TIM1 && STM32_DAC - ---help--- - Reserve timer 1 for use by DAC - - Timer devices may be used for different purposes. If STM32_TIM1 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -config STM32_TIM2_DAC - bool "TIM2 DAC" - default n - depends on STM32_TIM2 && STM32_DAC - ---help--- - Reserve timer 2 for use by DAC - - Timer devices may be used for different purposes. If STM32_TIM2 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -config STM32_TIM3_DAC - bool "TIM3 DAC" - default n - depends on STM32_TIM3 && STM32_DAC - ---help--- - Reserve timer 3 for use by DAC - - Timer devices may be used for different purposes. If STM32_TIM3 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -config STM32_TIM4_DAC - bool "TIM4 DAC" - default n - depends on STM32_TIM4 && STM32_DAC - ---help--- - Reserve timer 4 for use by DAC - - Timer devices may be used for different purposes. If STM32_TIM4 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -config STM32_TIM5_DAC - bool "TIM5 DAC" - default n - depends on STM32_TIM5 && STM32_DAC - ---help--- - Reserve timer 5 for use by DAC - - Timer devices may be used for different purposes. If STM32_TIM5 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -config STM32_TIM6_DAC - bool "TIM6 DAC" - default n - depends on STM32_TIM6 && STM32_DAC - ---help--- - Reserve timer 6 for use by DAC - - Timer devices may be used for different purposes. If STM32_TIM6 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -config STM32_TIM7_DAC - bool "TIM7 DAC" - default n - depends on STM32_TIM7 && STM32_DAC - ---help--- - Reserve timer 7 for use by DAC - - Timer devices may be used for different purposes. If STM32_TIM7 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -config STM32_TIM8_DAC - bool "TIM8 DAC" - default n - depends on STM32_TIM8 && STM32_DAC - ---help--- - Reserve timer 8 for use by DAC - - Timer devices may be used for different purposes. If STM32_TIM8 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -config STM32_TIM9_DAC - bool "TIM9 DAC" - default n - depends on STM32_TIM9 && STM32_DAC - ---help--- - Reserve timer 9 for use by DAC - - Timer devices may be used for different purposes. If STM32_TIM9 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -config STM32_TIM10_DAC - bool "TIM10 DAC" - default n - depends on STM32_TIM10 && STM32_DAC - ---help--- - Reserve timer 10 for use by DAC - - Timer devices may be used for different purposes. If STM32_TIM10 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -config STM32_TIM11_DAC - bool "TIM11 DAC" - default n - depends on STM32_TIM11 && STM32_DAC - ---help--- - Reserve timer 11 for use by DAC - - Timer devices may be used for different purposes. If STM32_TIM11 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -config STM32_TIM12_DAC - bool "TIM12 DAC" - default n - depends on STM32_TIM12 && STM32_DAC - ---help--- - Reserve timer 12 for use by DAC - - Timer devices may be used for different purposes. If STM32_TIM12 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -config STM32_TIM13_DAC - bool "TIM13 DAC" - default n - depends on STM32_TIM13 && STM32_DAC - ---help--- - Reserve timer 13 for use by DAC - - Timer devices may be used for different purposes. If STM32_TIM13 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -config STM32_TIM14_DAC - bool "TIM14 DAC" - default n - depends on STM32_TIM14 && STM32_DAC - ---help--- - Reserve timer 14 for use by DAC - - Timer devices may be used for different purposes. If STM32_TIM14 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -config STM32_TIM1_CAP - bool "TIM1 Capture" - default n - depends on STM32_TIM1 - select STM32_CAP - ---help--- - Reserve timer 1 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -if STM32_TIM1_CAP - -config STM32_TIM1_CHANNEL - int "TIM1 Capture Input Channel" - default 1 - range 1 4 - ---help--- - If TIM1 is enabled for capture usage, you also need specifies the timer input - channel {1,..,4} - -config STM32_TIM1_CLOCK - int "TIM1 work frequency for capture" - default 1000000 - ---help--- - This clock frequency limiting the count rate at the expense of resolution. - -endif # STM32_TIM1_CAP - -config STM32_TIM2_CAP - bool "TIM2 Capture" - default n - depends on STM32_TIM2 - select STM32_CAP - ---help--- - Reserve timer 2 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -if STM32_TIM2_CAP - -config STM32_TIM2_CHANNEL - int "TIM2 Capture Input Channel" - default 1 - range 1 4 - ---help--- - If TIM2 is enabled for capture usage, you also need specifies the timer input - channel {1,..,4} - -config STM32_TIM2_CLOCK - int "TIM2 work frequency for capture" - default 1000000 - ---help--- - This clock frequency limiting the count rate at the expense of resolution. - -endif # STM32_TIM2_CAP - -config STM32_TIM3_CAP - bool "TIM3 Capture" - default n - depends on STM32_TIM3 - select STM32_CAP - ---help--- - Reserve timer 3 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -if STM32_TIM3_CAP - -config STM32_TIM3_CHANNEL - int "TIM3 Capture Input Channel" - default 1 - range 1 4 - ---help--- - If TIM3 is enabled for capture usage, you also need specifies the timer input - channel {1,..,4} - -config STM32_TIM3_CLOCK - int "TIM3 work frequency for capture" - default 1000000 - ---help--- - This clock frequency limiting the count rate at the expense of resolution. - -endif # STM32_TIM3_CAP - -config STM32_TIM4_CAP - bool "TIM4 Capture" - default n - depends on STM32_TIM4 - select STM32_CAP - ---help--- - Reserve timer 4 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -if STM32_TIM4_CAP - -config STM32_TIM4_CHANNEL - int "TIM4 Capture Input Channel" - default 1 - range 1 4 - ---help--- - If TIM4 is enabled for capture usage, you also need specifies the timer input - channel {1,..,4} - -config STM32_TIM4_CLOCK - int "TIM4 work frequency for capture" - default 1000000 - ---help--- - This clock frequency limiting the count rate at the expense of resolution. - -endif # STM32_TIM4_CAP - -config STM32_TIM5_CAP - bool "TIM5 Capture" - default n - depends on STM32_TIM5 - select STM32_CAP - ---help--- - Reserve timer 5 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -if STM32_TIM5_CAP - -config STM32_TIM5_CHANNEL - int "TIM5 Capture Input Channel" - default 1 - range 1 4 - ---help--- - If TIM5 is enabled for capture usage, you also need specifies the timer input - channel {1,..,4} - -config STM32_TIM5_CLOCK - int "TIM5 work frequency for capture" - default 1000000 - ---help--- - This clock frequency limiting the count rate at the expense of resolution. - -endif # STM32_TIM5_CAP - -config STM32_TIM8_CAP - bool "TIM8 Capture" - default n - depends on STM32_TIM8 - select STM32_CAP - ---help--- - Reserve timer 8 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -if STM32_TIM8_CAP - -config STM32_TIM8_CHANNEL - int "TIM8 Capture Input Channel" - default 1 - range 1 4 - ---help--- - If TIM8 is enabled for capture usage, you also need specifies the timer input - channel {1,..,4} - -config STM32_TIM8_CLOCK - int "TIM8 work frequency for capture" - default 1000000 - ---help--- - This clock frequency limiting the count rate at the expense of resolution. - -endif # STM32_TIM8_CAP - -config STM32_TIM9_CAP - bool "TIM9 Capture" - default n - depends on STM32_TIM9 - select STM32_CAP - ---help--- - Reserve timer 9 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - if STM32_TIM9_CAP -config STM32_TIM9_CHANNEL - int "TIM9 Capture Input Channel" - default 1 - range 1 4 - ---help--- - If TIM9 is enabled for capture usage, you also need specifies the timer input - channel {1,..,4} - config STM32_TIM9_CLOCK int "TIM9 work frequency for capture" default 1000000 @@ -6616,27 +2621,8 @@ config STM32_TIM9_CLOCK endif # STM32_TIM9_CAP -config STM32_TIM10_CAP - bool "TIM10 Capture" - default n - depends on STM32_TIM10 - select STM32_CAP - ---help--- - Reserve timer 10 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - if STM32_TIM10_CAP -config STM32_TIM10_CHANNEL - int "TIM10 Capture Input Channel" - default 1 - range 1 4 - ---help--- - If TIM10 is enabled for capture usage, you also need specifies the timer input - channel {1,..,4} - config STM32_TIM10_CLOCK int "TIM10 work frequency for capture" default 1000000 @@ -6645,27 +2631,8 @@ config STM32_TIM10_CLOCK endif # STM32_TIM10_CAP -config STM32_TIM11_CAP - bool "TIM11 Capture" - default n - depends on STM32_TIM11 - select STM32_CAP - ---help--- - Reserve timer 11 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - if STM32_TIM11_CAP -config STM32_TIM11_CHANNEL - int "TIM11 Capture Input Channel" - default 1 - range 1 4 - ---help--- - If TIM11 is enabled for capture usage, you also need specifies the timer input - channel {1,..,4} - config STM32_TIM11_CLOCK int "TIM11 work frequency for capture" default 1000000 @@ -6674,865 +2641,6 @@ config STM32_TIM11_CLOCK endif # STM32_TIM11_CAP -config STM32_TIM12_CAP - bool "TIM12 Capture" - default n - depends on STM32_TIM12 - select STM32_CAP - ---help--- - Reserve timer 12 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -if STM32_TIM12_CAP - -config STM32_TIM12_CHANNEL - int "TIM12 Capture Input Channel" - default 1 - range 1 4 - ---help--- - If TIM12 is enabled for capture usage, you also need specifies the timer input - channel {1,..,4} - -config STM32_TIM12_CLOCK - int "TIM12 work frequency for capture" - default 1000000 - ---help--- - This clock frequency limiting the count rate at the expense of resolution. - -endif # STM32_TIM12_CAP - -config STM32_TIM13_CAP - bool "TIM13 Capture" - default n - depends on STM32_TIM13 - select STM32_CAP - ---help--- - Reserve timer 13 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -if STM32_TIM13_CAP - -config STM32_TIM13_CHANNEL - int "TIM13 Capture Input Channel" - default 1 - range 1 4 - ---help--- - If TIM13 is enabled for capture usage, you also need specifies the timer input - channel {1,..,4} - -config STM32_TIM13_CLOCK - int "TIM13 work frequency for capture" - default 1000000 - ---help--- - This clock frequency limiting the count rate at the expense of resolution. - -endif # STM32_TIM13_CAP - -config STM32_TIM14_CAP - bool "TIM14 Capture" - default n - depends on STM32_TIM14 - select STM32_CAP - ---help--- - Reserve timer 14 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -if STM32_TIM14_CAP - -config STM32_TIM14_CHANNEL - int "TIM14 Capture Input Channel" - default 1 - range 1 4 - ---help--- - If TIM14 is enabled for capture usage, you also need specifies the timer input - channel {1,..,4} - -config STM32_TIM14_CLOCK - int "TIM14 work frequency for capture" - default 1000000 - ---help--- - This clock frequency limiting the count rate at the expense of resolution. - -endif # STM32_TIM14_CAP - -menu "STM32 TIMx Outputs Configuration" - -config STM32_TIM1_CH1POL - int "TIM1 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM1_CH1OUT - ---help--- - TIM1 Channel 1 output polarity - -config STM32_TIM1_CH1IDLE - int "TIM1 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM1_CH1OUT - ---help--- - TIM1 Channel 1 output IDLE - -config STM32_TIM1_CH1NPOL - int "TIM1 Channel 1 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32_TIM1_CH1NOUT - ---help--- - TIM1 Channel 1 Complementary Output polarity - -config STM32_TIM1_CH1NIDLE - int "TIM1 Channel 1 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM1_CH1NOUT - ---help--- - TIM1 Channel 1 Complementary Output IDLE - -config STM32_TIM1_CH2POL - int "TIM1 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM1_CH2OUT - ---help--- - TIM1 Channel 2 output polarity - -config STM32_TIM1_CH2IDLE - int "TIM1 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM1_CH2OUT - ---help--- - TIM1 Channel 2 output IDLE - -config STM32_TIM1_CH2NPOL - int "TIM1 Channel 2 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32_TIM1_CH2NOUT - ---help--- - TIM1 Channel 2 Complementary Output polarity - -config STM32_TIM1_CH2NIDLE - int "TIM1 Channel 2 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM1_CH2NOUT - ---help--- - TIM1 Channel 2 Complementary Output IDLE - -config STM32_TIM1_CH3POL - int "TIM1 Channel 3 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM1_CH3OUT - ---help--- - TIM1 Channel 3 output polarity - -config STM32_TIM1_CH3IDLE - int "TIM1 Channel 3 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM1_CH3OUT - ---help--- - TIM1 Channel 3 output IDLE - -config STM32_TIM1_CH3NPOL - int "TIM1 Channel 3 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32_TIM1_CH3NOUT - ---help--- - TIM1 Channel 3 Complementary Output polarity - -config STM32_TIM1_CH3NIDLE - int "TIM1 Channel 3 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM1_CH3NOUT - ---help--- - TIM1 Channel 3 Complementary Output IDLE - -config STM32_TIM1_CH4POL - int "TIM1 Channel 4 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM1_CH4OUT - ---help--- - TIM1 Channel 4 output polarity - -config STM32_TIM1_CH4IDLE - int "TIM1 Channel 4 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM1_CH4OUT - ---help--- - TIM1 Channel 4 output IDLE - -config STM32_TIM1_CH5POL - int "TIM1 Channel 5 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM1_CH5OUT - ---help--- - TIM1 Channel 5 output polarity - -config STM32_TIM1_CH5IDLE - int "TIM1 Channel 5 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM1_CH5OUT - ---help--- - TIM1 Channel 5 output IDLE - -config STM32_TIM1_CH6POL - int "TIM1 Channel 6 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM1_CH6OUT - ---help--- - TIM1 Channel 6 output polarity - -config STM32_TIM1_CH6IDLE - int "TIM1 Channel 6 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM1_CH6OUT - ---help--- - TIM1 Channel 6 output IDLE - -config STM32_TIM2_CH1POL - int "TIM2 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM2_CH1OUT - ---help--- - TIM2 Channel 1 output polarity - -config STM32_TIM2_CH1IDLE - int "TIM2 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM2_CH1OUT - ---help--- - TIM2 Channel 1 output IDLE - -config STM32_TIM2_CH2POL - int "TIM2 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM2_CH2OUT - ---help--- - TIM2 Channel 2 output polarity - -config STM32_TIM2_CH2IDLE - int "TIM2 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM2_CH2OUT - ---help--- - TIM2 Channel 2 output IDLE - -config STM32_TIM2_CH3POL - int "TIM2 Channel 3 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM2_CH3OUT - ---help--- - TIM2 Channel 3 output polarity - -config STM32_TIM2_CH3IDLE - int "TIM2 Channel 3 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM2_CH3OUT - ---help--- - TIM2 Channel 3 output IDLE - -config STM32_TIM2_CH4POL - int "TIM2 Channel 4 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM2_CH4OUT - ---help--- - TIM2 Channel 4 output polarity - -config STM32_TIM2_CH4IDLE - int "TIM2 Channel 4 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM2_CH4OUT - ---help--- - TIM2 Channel 4 output IDLE - -config STM32_TIM3_CH1POL - int "TIM3 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM3_CH1OUT - ---help--- - TIM3 Channel 1 output polarity - -config STM32_TIM3_CH1IDLE - int "TIM3 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM3_CH1OUT - ---help--- - TIM3 Channel 1 output IDLE - -config STM32_TIM3_CH2POL - int "TIM3 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM3_CH2OUT - ---help--- - TIM3 Channel 2 output polarity - -config STM32_TIM3_CH2IDLE - int "TIM3 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM3_CH2OUT - ---help--- - TIM3 Channel 2 output IDLE - -config STM32_TIM3_CH3POL - int "TIM3 Channel 3 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM3_CH3OUT - ---help--- - TIM3 Channel 3 output polarity - -config STM32_TIM3_CH3IDLE - int "TIM3 Channel 3 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM3_CH3OUT - ---help--- - TIM3 Channel 3 output IDLE - -config STM32_TIM3_CH4POL - int "TIM3 Channel 4 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM3_CH4OUT - ---help--- - TIM3 Channel 4 output polarity - -config STM32_TIM3_CH4IDLE - int "TIM3 Channel 4 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM3_CH4OUT - ---help--- - TIM3 Channel 4 output IDLE - -config STM32_TIM4_CH1POL - int "TIM4 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM4_CH1OUT - ---help--- - TIM4 Channel 1 output polarity - -config STM32_TIM4_CH1IDLE - int "TIM4 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM4_CH1OUT - ---help--- - TIM4 Channel 1 output IDLE - -config STM32_TIM4_CH2POL - int "TIM4 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM4_CH2OUT - ---help--- - TIM4 Channel 2 output polarity - -config STM32_TIM4_CH2IDLE - int "TIM4 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM4_CH2OUT - ---help--- - TIM4 Channel 2 output IDLE - -config STM32_TIM4_CH3POL - int "TIM4 Channel 3 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM4_CH3OUT - ---help--- - TIM4 Channel 3 output polarity - -config STM32_TIM4_CH3IDLE - int "TIM4 Channel 3 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM4_CH3OUT - ---help--- - TIM4 Channel 3 output IDLE - -config STM32_TIM4_CH4POL - int "TIM4 Channel 4 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM4_CH4OUT - ---help--- - TIM4 Channel 4 output polarity - -config STM32_TIM4_CH4IDLE - int "TIM4 Channel 4 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM4_CH4OUT - ---help--- - TIM4 Channel 4 output IDLE - -config STM32_TIM5_CH1POL - int "TIM5 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM5_CH1OUT - ---help--- - TIM5 Channel 1 output polarity - -config STM32_TIM5_CH1IDLE - int "TIM5 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM5_CH1OUT - ---help--- - TIM5 Channel 1 output IDLE - -config STM32_TIM5_CH2POL - int "TIM5 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM5_CH2OUT - ---help--- - TIM5 Channel 2 output polarity - -config STM32_TIM5_CH2IDLE - int "TIM5 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM5_CH2OUT - ---help--- - TIM5 Channel 2 output IDLE - -config STM32_TIM5_CH3POL - int "TIM5 Channel 3 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM5_CH3OUT - ---help--- - TIM5 Channel 3 output polarity - -config STM32_TIM5_CH3IDLE - int "TIM5 Channel 3 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM5_CH3OUT - ---help--- - TIM5 Channel 3 output IDLE - -config STM32_TIM5_CH4POL - int "TIM5 Channel 4 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM5_CH4OUT - ---help--- - TIM5 Channel 4 output polarity - -config STM32_TIM5_CH4IDLE - int "TIM5 Channel 4 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM5_CH4OUT - ---help--- - TIM5 Channel 4 output IDLE - -config STM32_TIM8_CH1POL - int "TIM8 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM8_CH1OUT - ---help--- - TIM8 Channel 1 output polarity - -config STM32_TIM8_CH1IDLE - int "TIM8 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM8_CH1OUT - ---help--- - TIM8 Channel 1 output IDLE - -config STM32_TIM8_CH1NPOL - int "TIM8 Channel 1 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32_TIM8_CH1NOUT - ---help--- - TIM8 Channel 1 Complementary Output polarity - -config STM32_TIM8_CH1NIDLE - int "TIM8 Channel 1 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM8_CH1NOUT - ---help--- - TIM8 Channel 1 Complementary Output IDLE - -config STM32_TIM8_CH2POL - int "TIM8 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM8_CH2OUT - ---help--- - TIM8 Channel 2 output polarity - -config STM32_TIM8_CH2IDLE - int "TIM8 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM8_CH2OUT - ---help--- - TIM8 Channel 2 output IDLE - -config STM32_TIM8_CH2NPOL - int "TIM8 Channel 2 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32_TIM8_CH2NOUT - ---help--- - TIM8 Channel 2 Complementary Output polarity - -config STM32_TIM8_CH2NIDLE - int "TIM8 Channel 2 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM8_CH2NOUT - ---help--- - TIM8 Channel 2 Complementary Output IDLE - -config STM32_TIM8_CH3POL - int "TIM8 Channel 3 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM8_CH3OUT - ---help--- - TIM8 Channel 3 output polarity - -config STM32_TIM8_CH3IDLE - int "TIM8 Channel 3 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM8_CH3OUT - ---help--- - TIM8 Channel 3 output IDLE - -config STM32_TIM8_CH3NPOL - int "TIM8 Channel 3 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32_TIM8_CH3NOUT - ---help--- - TIM8 Channel 3 Complementary Output polarity - -config STM32_TIM8_CH3NIDLE - int "TIM8 Channel 3 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM8_CH3NOUT - ---help--- - TIM8 Channel 3 Complementary Output IDLE - -config STM32_TIM8_CH4POL - int "TIM8 Channel 4 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM8_CH4OUT - ---help--- - TIM8 Channel 4 output polarity - -config STM32_TIM8_CH4IDLE - int "TIM8 Channel 4 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM8_CH4OUT - ---help--- - TIM8 Channel 4 output IDLE - -config STM32_TIM8_CH5POL - int "TIM8 Channel 5 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM8_CH5OUT - ---help--- - TIM8 Channel 5 output polarity - -config STM32_TIM8_CH5IDLE - int "TIM8 Channel 5 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM8_CH5OUT - ---help--- - TIM8 Channel 5 output IDLE - -config STM32_TIM8_CH6POL - int "TIM8 Channel 6 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM8_CH6OUT - ---help--- - TIM8 Channel 6 output polarity - -config STM32_TIM8_CH6IDLE - int "TIM8 Channel 6 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM8_CH6OUT - ---help--- - TIM8 Channel 6 output IDLE - -config STM32_TIM9_CH1POL - int "TIM9 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM9_CH1OUT - ---help--- - TIM9 Channel 1 output polarity - -config STM32_TIM9_CH1IDLE - int "TIM9 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM9_CH1OUT - ---help--- - TIM9 Channel 1 output IDLE - -config STM32_TIM9_CH2POL - int "TIM9 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM9_CH2OUT - ---help--- - TIM9 Channel 2 output polarity - -config STM32_TIM9_CH2IDLE - int "TIM9 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM9_CH2OUT - ---help--- - TIM9 Channel 2 output IDLE - -config STM32_TIM10_CH1POL - int "TIM10 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM10_CH1OUT - ---help--- - TIM10 Channel 1 output polarity - -config STM32_TIM10_CH1IDLE - int "TIM10 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM10_CH1OUT - ---help--- - TIM10 Channel 1 output IDLE - -config STM32_TIM11_CH1POL - int "TIM11 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM11_CH1OUT - ---help--- - TIM11 Channel 1 output polarity - -config STM32_TIM11_CH1IDLE - int "TIM11 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM11_CH1OUT - ---help--- - TIM11 Channel 1 output IDLE - -config STM32_TIM12_CH1POL - int "TIM12 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM12_CH1OUT - ---help--- - TIM12 Channel 1 output polarity - -config STM32_TIM12_CH1IDLE - int "TIM12 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM12_CH1OUT - ---help--- - TIM12 Channel 1 output IDLE - -config STM32_TIM12_CH2POL - int "TIM12 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM12_CH2OUT - ---help--- - TIM12 Channel 2 output polarity - -config STM32_TIM12_CH2IDLE - int "TIM12 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM12_CH2OUT - ---help--- - TIM12 Channel 2 output IDLE - -config STM32_TIM13_CH1POL - int "TIM13 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM13_CH1OUT - ---help--- - TIM13 Channel 1 output polarity - -config STM32_TIM13_CH1IDLE - int "TIM13 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM13_CH1OUT - ---help--- - TIM13 Channel 1 output IDLE - -config STM32_TIM14_CH1POL - int "TIM14 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM14_CH1OUT - ---help--- - TIM14 Channel 1 output polarity - -config STM32_TIM14_CH1IDLE - int "TIM14 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM14_CH1OUT - ---help--- - TIM14 Channel 1 output IDLE - -config STM32_TIM15_CH1POL - int "TIM15 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM15_CH1OUT - ---help--- - TIM15 Channel 1 output polarity - -config STM32_TIM15_CH1IDLE - int "TIM15 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM15_CH1OUT - ---help--- - TIM15 Channel 1 output IDLE - -config STM32_TIM15_CH1NPOL - int "TIM15 Channel 1 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32_TIM15_CH1NOUT - ---help--- - TIM15 Channel 1 Complementary Output polarity - -config STM32_TIM15_CH1NIDLE - int "TIM15 Channel 1 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM15_CH1NOUT - ---help--- - TIM15 Channel 1 Complementary Output IDLE - -config STM32_TIM15_CH2POL - int "TIM15 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM15_CH2OUT - ---help--- - TIM15 Channel 2 output polarity - -config STM32_TIM15_CH2IDLE - int "TIM15 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM15_CH2OUT - ---help--- - TIM15 Channel 2 output IDLE - -config STM32_TIM15_CH2NPOL - int "TIM15 Channel 2 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32_TIM15_CH2NOUT - ---help--- - TIM15 Channel 2 Complementary Output polarity - -config STM32_TIM15_CH2NIDLE - int "TIM15 Channel 2 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM15_CH2NOUT - ---help--- - TIM15 Channel 2 Complementary Output IDLE - -config STM32_TIM16_CH1POL - int "TIM16 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM16_CH1OUT - ---help--- - TIM16 Channel 1 output polarity - -config STM32_TIM16_CH1IDLE - int "TIM16 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM16_CH1OUT - ---help--- - TIM16 Channel 1 output IDLE - -config STM32_TIM17_CH1POL - int "TIM17 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM17_CH1OUT - ---help--- - TIM17 Channel 1 output polarity - -config STM32_TIM17_CH1IDLE - int "TIM17 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM17_CH1OUT - ---help--- - TIM17 Channel 1 output IDLE - -endmenu #STM32 TIMx Outputs Configuration - endmenu # Timer Configuration menu "HRTIM Configuration" @@ -8119,30 +3227,6 @@ endmenu # "HRTIM Configuration" menu "ADC Configuration" depends on STM32_ADC -config STM32_ADC1_RESOLUTION - int "ADC1 resolution" - depends on STM32_ADC1 && !STM32_HAVE_IP_ADC_V1_BASIC - default 0 - range 0 3 - ---help--- - ADC1 resolution. 0 - 12 bit, 1 - 10 bit, 2 - 8 bit, 3 - 6 bit - -config STM32_ADC2_RESOLUTION - int "ADC2 resolution" - depends on STM32_ADC2 && !STM32_HAVE_IP_ADC_V1_BASIC - default 0 - range 0 3 - ---help--- - ADC2 resolution. 0 - 12 bit, 1 - 10 bit, 2 - 8 bit, 3 - 6 bit - -config STM32_ADC3_RESOLUTION - int "ADC3 resolution" - depends on STM32_ADC3 && !STM32_HAVE_IP_ADC_V1_BASIC - default 0 - range 0 3 - ---help--- - ADC3 resolution. 0 - 12 bit, 1 - 10 bit, 2 - 8 bit, 3 - 6 bit - config STM32_ADC4_RESOLUTION int "ADC4 resolution" depends on STM32_ADC4 && !STM32_HAVE_IP_ADC_V1_BASIC @@ -8159,171 +3243,6 @@ config STM32_ADC5_RESOLUTION ---help--- ADC5 resolution. 0 - 12 bit, 1 - 10 bit, 2 - 8 bit, 3 - 6 bit -config STM32_ADC_MAX_SAMPLES - int "The maximum number of channels that can be sampled" - default 16 - ---help--- - The maximum number of samples which can be handled without - overrun depends on various factors. This is the user's - responsibility to correctly select this value. - Since the interface to update the sampling time is available - for all supported devices, the user can change the default - values in the board initialization logic and avoid ADC overrun. - -config STM32_ADC_NO_STARTUP_CONV - bool "Do not start conversion when opening ADC device" - default n - ---help--- - Do not start conversion when opening ADC device. - -config STM32_ADC_NOIRQ - bool "Do not use default ADC interrupts" - default n - ---help--- - Do not use default ADC interrupts handlers. - -config STM32_ADC_LL_OPS - bool "ADC low-level operations" - default n - ---help--- - Enable low-level ADC ops. - -config STM32_ADC_CHANGE_SAMPLETIME - bool "ADC sample time configuration" - default n - depends on STM32_ADC_LL_OPS - ---help--- - Enable ADC sample time configuration (SMPRx registers). - -config STM32_ADC1_DMA - bool "ADC1 DMA" - depends on STM32_ADC1 && STM32_HAVE_ADC1_DMA - default n - ---help--- - If DMA is selected, then the ADC may be configured to support - DMA transfer, which is necessary if multiple channels are read - or if very high trigger frequencies are used. - -config STM32_ADC1_SCAN - bool "ADC1 scan mode" - depends on STM32_ADC1 && STM32_HAVE_IP_ADC_V1 - default STM32_ADC1_DMA - default n - -config STM32_ADC1_DMA_CFG - int "ADC1 DMA configuration" - depends on STM32_ADC1_DMA && !STM32_HAVE_IP_ADC_V1_BASIC - range 0 1 - default 0 - ---help--- - 0 - ADC1 DMA in One Shot Mode, 1 - ADC1 DMA in Circular Mode - -config STM32_ADC1_DMA_BATCH - int "ADC1 DMA number of conversions" - depends on STM32_ADC1 && STM32_ADC1_DMA - default 1 - ---help--- - This option allows you to select the number of regular group conversions - that will trigger a DMA callback transerring data to the upper-half driver. - By default, this value is 1, which means that data is transferred after - each group conversion. - -config STM32_ADC1_ANIOC_TRIGGER - int "ADC1 software trigger (ANIOC_TRIGGER) configuration" - depends on STM32_ADC1 - range 1 3 - default 3 - ---help--- - 1 - ANIOC_TRIGGER only starts regular conversion - 2 - ANIOC_TRIGGER only starts injected conversion - 3 - ANIOC_TRIGGER starts both regular and injected conversions - -config STM32_ADC2_DMA - bool "ADC2 DMA" - depends on STM32_ADC2 && STM32_HAVE_ADC2_DMA - default n - ---help--- - If DMA is selected, then the ADC may be configured to support - DMA transfer, which is necessary if multiple channels are read - or if very high trigger frequencies are used. - -config STM32_ADC2_SCAN - bool "ADC2 scan mode" - depends on STM32_ADC2 && STM32_HAVE_IP_ADC_V1 - default STM32_ADC2_DMA - default n - -config STM32_ADC2_DMA_CFG - int "ADC2 DMA configuration" - depends on STM32_ADC2_DMA && !STM32_HAVE_IP_ADC_V1_BASIC - range 0 1 - default 0 - ---help--- - 0 - ADC2 DMA in One Shot Mode, 1 - ADC2 DMA in Circular Mode - -config STM32_ADC2_DMA_BATCH - int "ADC2 DMA number of conversions" - depends on STM32_ADC2 && STM32_ADC2_DMA - default 1 - ---help--- - This option allows you to select the number of regular group conversions - that will trigger a DMA callback transerring data to the upper-half driver. - By default, this value is 1, which means that data is transferred after - each group conversion. - -config STM32_ADC2_ANIOC_TRIGGER - int "ADC2 software trigger (ANIOC_TRIGGER) configuration" - depends on STM32_ADC2 - range 1 3 - default 3 - ---help--- - 1 - ANIOC_TRIGGER only starts regular conversion - 2 - ANIOC_TRIGGER only starts injected conversion - 3 - ANIOC_TRIGGER starts both regular and injected conversions - -config STM32_ADC3_DMA - bool "ADC3 DMA" - depends on STM32_ADC3 && STM32_HAVE_ADC3_DMA - default n - ---help--- - If DMA is selected, then the ADC may be configured to support - DMA transfer, which is necessary if multiple channels are read - or if very high trigger frequencies are used. - -config STM32_ADC3_SCAN - bool "ADC3 scan mode" - depends on STM32_ADC3 && STM32_HAVE_IP_ADC_V1 - default STM32_ADC3_DMA - default n - -config STM32_ADC3_DMA_CFG - int "ADC3 DMA configuration" - depends on STM32_ADC3_DMA && !STM32_HAVE_IP_ADC_V1_BASIC - range 0 1 - default 0 - ---help--- - 0 - ADC3 DMA in One Shot Mode, 1 - ADC3 DMA in Circular Mode - -config STM32_ADC3_DMA_BATCH - int "ADC3 DMA number of conversions" - depends on STM32_ADC3 && STM32_ADC3_DMA - default 1 - ---help--- - This option allows you to select the number of regular group conversions - that will trigger a DMA callback transerring data to the upper-half driver. - By default, this value is 1, which means that data is transferred after - each group conversion. - -config STM32_ADC3_ANIOC_TRIGGER - int "ADC3 software trigger (ANIOC_TRIGGER) configuration" - depends on STM32_ADC3 - range 1 3 - default 3 - ---help--- - 1 - ANIOC_TRIGGER only starts regular conversion - 2 - ANIOC_TRIGGER only starts injected conversion - 3 - ANIOC_TRIGGER starts both regular and injected conversions - config STM32_ADC4_DMA bool "ADC4 DMA" depends on STM32_ADC4 && STM32_HAVE_ADC4_DMA @@ -8388,30 +3307,6 @@ config STM32_ADC5_DMA_BATCH By default, this value is 1, which means that data is transferred after each group conversion. -config STM32_ADC1_INJECTED_CHAN - int "ADC1 injected channels" - depends on STM32_ADC1 - range 0 4 - default 0 - ---help--- - Support for ADC1 injected channels. - -config STM32_ADC2_INJECTED_CHAN - int "ADC2 injected channels" - depends on STM32_ADC2 - range 0 4 - default 0 - ---help--- - Support for ADC2 injected channels. - -config STM32_ADC3_INJECTED_CHAN - int "ADC3 injected channels" - depends on STM32_ADC3 - range 0 4 - default 0 - ---help--- - Support for ADC3 injected channels. - config STM32_ADC4_INJECTED_CHAN int "ADC4 injected channels" depends on STM32_ADC4 @@ -8428,27 +3323,6 @@ config STM32_ADC5_INJECTED_CHAN ---help--- Support for ADC5 injected channels. -config STM32_ADC1_EXTSEL - bool "ADC1 external trigger for regular group" - depends on STM32_ADC1 && !STM32_HAVE_ADC1_TIMER - default n - ---help--- - Enable EXTSEL for ADC1. - -config STM32_ADC2_EXTSEL - bool "ADC2 external trigger for regular group" - depends on STM32_ADC2 && !STM32_HAVE_ADC2_TIMER - default n - ---help--- - Enable EXTSEL for ADC2. - -config STM32_ADC3_EXTSEL - bool "ADC3 external trigger for regular group" - depends on STM32_ADC3 && !STM32_HAVE_ADC3_TIMER - default n - ---help--- - Enable EXTSEL for ADC3. - config STM32_ADC4_EXTSEL bool "ADC4 external trigger for regular group" depends on STM32_ADC4 && !STM32_HAVE_ADC4_TIMER @@ -8463,27 +3337,6 @@ config STM32_ADC5_EXTSEL ---help--- Enable EXTSEL for ADC5. -config STM32_ADC1_JEXTSEL - bool "ADC1 external trigger for injected group" - depends on STM32_ADC1 - default n - ---help--- - Enable JEXTSEL for ADC1. - -config STM32_ADC2_JEXTSEL - bool "ADC2 external trigger for injected group" - depends on STM32_ADC2 - default n - ---help--- - Enable JEXTSEL for ADC2. - -config STM32_ADC3_JEXTSEL - bool "ADC3 external trigger for injected group" - depends on STM32_ADC3 - default n - ---help--- - Enable JEXTSEL for ADC3. - config STM32_ADC4_JEXTSEL bool "ADC4 external trigger for injected group" depends on STM32_ADC4 @@ -9230,22 +4083,6 @@ endif endmenu -config STM32_USART - bool - default n - -config STM32_SERIALDRIVER - bool - default n - -config STM32_1WIREDRIVER - bool - default n - -config STM32_HCIUART - bool - default n - config STM32_HCIUART_RXDMA bool default n @@ -9255,41 +4092,6 @@ menu "U[S]ART Configuration" comment "U[S]ART Device Configuration" -if STM32_USART1_SERIALDRIVER - -config USART1_RS485 - bool "RS-485 on USART1" - default n - ---help--- - Enable RS-485 interface on USART1. Your board config will have to - provide GPIO_USART1_RS485_DIR pin definition. Currently it cannot be - used with USART1_RXDMA. - -config USART1_RS485_DIR_POLARITY - int "USART1 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART1_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART1. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config USART1_RXDMA - bool "USART1 Rx DMA" - default n - depends on (((STM32_STM32F10XX || STM32_STM32L15XX) && STM32_DMA1) || (!STM32_STM32F10XX && STM32_DMA2)) - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config USART1_TXDMA - bool "USART1 Tx DMA" - default n - depends on (((STM32_STM32F10XX || STM32_STM32L15XX) && STM32_DMA1) || (!STM32_STM32F10XX && STM32_DMA2)) - ---help--- - In high data rate usage, Tx DMA may reduce CPU load - -endif # STM32_USART1_SERIALDRIVER - if STM32_USART1_HCIUART config STM32_HCIUART1_RXBUFSIZE @@ -9326,41 +4128,6 @@ config STM32_HCIUART1_RXDMA endif # STM32_USART1_HCIUART -if STM32_USART2_SERIALDRIVER - -config USART2_RS485 - bool "RS-485 on USART2" - default n - ---help--- - Enable RS-485 interface on USART2. Your board config will have to - provide GPIO_USART2_RS485_DIR pin definition. Currently it cannot be - used with USART2_RXDMA. - -config USART2_RS485_DIR_POLARITY - int "USART2 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART2_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART2. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config USART2_RXDMA - bool "USART2 Rx DMA" - default n - depends on STM32_DMA1 - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config USART2_TXDMA - bool "USART2 Tx DMA" - default n - depends on STM32_DMA1 - ---help--- - In high data rate usage, Tx DMA may reduce CPU load - -endif # STM32_USART2_SERIALDRIVER - if STM32_USART2_HCIUART config STM32_HCIUART2_RXBUFSIZE @@ -9397,41 +4164,6 @@ config STM32_HCIUART2_RXDMA endif # STM32_USART2_HCIUART -if STM32_USART3_SERIALDRIVER - -config USART3_RS485 - bool "RS-485 on USART3" - default n - ---help--- - Enable RS-485 interface on USART3. Your board config will have to - provide GPIO_USART3_RS485_DIR pin definition. Currently it cannot be - used with USART3_RXDMA. - -config USART3_RS485_DIR_POLARITY - int "USART3 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART3_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART3. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config USART3_RXDMA - bool "USART3 Rx DMA" - default n - depends on STM32_DMA1 - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config USART3_TXDMA - bool "USART3 Tx DMA" - default n - depends on STM32_DMA1 - ---help--- - In high data rate usage, Tx DMA may reduce CPU load - -endif # STM32_USART3_SERIALDRIVER - if STM32_USART3_HCIUART config STM32_HCIUART3_RXBUFSIZE @@ -9468,111 +4200,6 @@ config STM32_HCIUART3_RXDMA endif # STM32_USART3_HCIUART -if STM32_UART4_SERIALDRIVER - -config UART4_RS485 - bool "RS-485 on UART4" - default n - ---help--- - Enable RS-485 interface on UART4. Your board config will have to - provide GPIO_UART4_RS485_DIR pin definition. Currently it cannot be - used with UART4_RXDMA. - -config UART4_RS485_DIR_POLARITY - int "UART4 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on UART4_RS485 - ---help--- - Polarity of DIR pin for RS-485 on UART4. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config UART4_RXDMA - bool "UART4 Rx DMA" - default n - depends on STM32_DMA1 - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config UART4_TXDMA - bool "UART4 Tx DMA" - default n - depends on STM32_DMA1 - ---help--- - In high data rate usage, Tx DMA may reduce CPU load - -endif # STM32_UART4_SERIALDRIVER - -if STM32_UART5_SERIALDRIVER - -config UART5_RS485 - bool "RS-485 on UART5" - default n - ---help--- - Enable RS-485 interface on UART5. Your board config will have to - provide GPIO_UART5_RS485_DIR pin definition. Currently it cannot be - used with UART5_RXDMA. - -config UART5_RS485_DIR_POLARITY - int "UART5 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on UART5_RS485 - ---help--- - Polarity of DIR pin for RS-485 on UART5. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config UART5_RXDMA - bool "UART5 Rx DMA" - default n - depends on STM32_DMA1 - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config UART5_TXDMA - bool "UART5 Tx DMA" - default n - depends on STM32_DMA1 - ---help--- - In high data rate usage, Tx DMA may reduce CPU load - -endif # STM32_UART5_SERIALDRIVER - -if STM32_USART6_SERIALDRIVER - -config USART6_RS485 - bool "RS-485 on USART6" - default n - ---help--- - Enable RS-485 interface on USART6. Your board config will have to - provide GPIO_USART6_RS485_DIR pin definition. Currently it cannot be - used with USART6_RXDMA. - -config USART6_RS485_DIR_POLARITY - int "USART6 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART6_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART6. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config USART6_RXDMA - bool "USART6 Rx DMA" - default n - depends on STM32_DMA2 - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config USART6_TXDMA - bool "USART6 Tx DMA" - default n - depends on STM32_DMA2 - ---help--- - In high data rate usage, Tx DMA may reduce CPU load - -endif # STM32_USART6_SERIALDRIVER - if STM32_USART6_HCIUART config STM32_HCIUART6_RXBUFSIZE @@ -9609,218 +4236,8 @@ config STM32_HCIUART6_RXDMA endif # STM32_USART6_HCIUART -choice - prompt "UART7 Driver Configuration" - default STM32_UART7_SERIALDRIVER - depends on STM32_UART7 - -config STM32_UART7_SERIALDRIVER - bool "Standard serial driver" - select UART7_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - select STM32_SERIALDRIVER - -config STM32_UART7_1WIREDRIVER - bool "1-Wire driver" - select STM32_1WIREDRIVER - -config STM32_UART7_HCIUART - bool "Bluetooth HCI-UART" - select STM32_HCIUART - depends on WIRELESS_BLUETOOTH - -endchoice # UART7 Driver Configuration - -if STM32_UART7_SERIALDRIVER - -config UART7_RS485 - bool "RS-485 on UART7" - default n - ---help--- - Enable RS-485 interface on UART7. Your board config will have to - provide GPIO_UART7_RS485_DIR pin definition. Currently it cannot be - used with UART7_RXDMA. - -config UART7_RS485_DIR_POLARITY - int "UART7 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on UART7_RS485 - ---help--- - Polarity of DIR pin for RS-485 on UART7. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config UART7_RXDMA - bool "UART7 Rx DMA" - default n - depends on STM32_DMA1 - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config UART7_TXDMA - bool "UART7 Tx DMA" - default n - depends on STM32_DMA1 - ---help--- - In high data rate usage, Tx DMA may reduce CPU load - -endif # STM32_UART7_SERIALDRIVER - -if STM32_UART7_HCIUART - -config STM32_HCIUART7_RXBUFSIZE - int "HCI UART7 Rx buffer size" - default 80 - ---help--- - Characters are buffered as they are received. This specifies - the size of the receive buffer. Ideally this should be at least - the size of the largest frame that can be received - -config STM32_HCIUART7_TXBUFSIZE - int "HCI UART7 Transmit buffer size" - default 80 - ---help--- - Characters are buffered before being sent. This specifies - the size of the transmit buffer. Ideally this should be at least - the size of the largest frame that can be sent - -config STM32_HCIUART7_BAUD - int "HCI UART7 initial BAUD rate" - default 115200 - ---help--- - The configured initial BAUD of the HCIR USART used during bringup. - In most cases this initial rate can be increased by the upper half - HCI UART driver using vendor-specifi HCI UART commands. - -config STM32_HCIUART7_RXDMA - bool "HCI UART7 Rx DMA" - default n - depends on STM32_DMA2 - select STM32_HCIUART_RXDMA - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -endif # STM32_UART7_HCIUART - -choice - prompt "UART8 Driver Configuration" - default STM32_UART8_SERIALDRIVER - depends on STM32_UART8 - -config STM32_UART8_SERIALDRIVER - bool "Standard serial driver" - select UART8_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - select STM32_SERIALDRIVER - -config STM32_UART8_1WIREDRIVER - bool "1-Wire driver" - select STM32_1WIREDRIVER - -config STM32_UART8_HCIUART - bool "Bluetooth HCI-UART" - select STM32_HCIUART - depends on WIRELESS_BLUETOOTH - -endchoice # UART8 Driver Configuration - -if STM32_UART8_SERIALDRIVER - -config UART8_RS485 - bool "RS-485 on UART8" - default n - ---help--- - Enable RS-485 interface on UART8. Your board config will have to - provide GPIO_UART8_RS485_DIR pin definition. Currently it cannot be - used with UART8_RXDMA. - -config UART8_RS485_DIR_POLARITY - int "UART8 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on UART8_RS485 - ---help--- - Polarity of DIR pin for RS-485 on UART8. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config UART8_RXDMA - bool "UART8 Rx DMA" - default n - depends on STM32_DMA1 - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config UART8_TXDMA - bool "UART8 Tx DMA" - default n - depends on STM32_DMA1 - ---help--- - In high data rate usage, Tx DMA may reduce CPU load - -endif # STM32_UART8_SERIALDRIVER - -if STM32_UART8_HCIUART - -config STM32_HCIUART8_RXBUFSIZE - int "HCI UART8 Rx buffer size" - default 80 - ---help--- - Characters are buffered as they are received. This specifies - the size of the receive buffer. Ideally this should be at least - the size of the largest frame that can be received - -config STM32_HCIUART8_TXBUFSIZE - int "HCI UART8 Transmit buffer size" - default 80 - ---help--- - Characters are buffered before being sent. This specifies - the size of the transmit buffer. Ideally this should be at least - the size of the largest frame that can be sent - -config STM32_HCIUART8_BAUD - int "HCI UART8 initial BAUD rate" - default 115200 - ---help--- - The configured initial BAUD of the HCIR USART used during bringup. - In most cases this initial rate can be increased by the upper half - HCI UART driver using vendor-specifi HCI UART commands. - -config STM32_HCIUART8_RXDMA - bool "HCI UART8 Rx DMA" - default n - depends on STM32_DMA2 - select STM32_HCIUART_RXDMA - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -endif # STM32_UART8_HCIUART - if STM32_LPUART1_SERIALDRIVER -config LPUART1_RS485 - bool "RS-485 on LPUART1" - default n - ---help--- - Enable RS-485 interface on LPUART1. Your board config will have to - provide GPIO_LPUART1_RS485_DIR pin definition. Currently it cannot be - used with LPUART1_RXDMA. - -config LPUART1_RS485_DIR_POLARITY - int "LPUART1 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on LPUART1_RS485 - ---help--- - Polarity of DIR pin for RS-485 on LPUART1. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config LPUART1_RXDMA - bool "LPUART1 Rx DMA" - default n - depends on STM32_DMA1 - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - config LPUART1_TXDMA bool "LPUART1 Tx DMA" default n @@ -9830,73 +4247,6 @@ config LPUART1_TXDMA endif # STM32_LPUART1_SERIALDRIVER -menu "Serial Driver Configuration" - depends on STM32_SERIALDRIVER - -config STM32_SERIAL_RXDMA_BUFFER_SIZE - int "Rx DMA buffer size" - default 32 - range 32 4096 - ---help--- - The DMA buffer size when using RX DMA to emulate a FIFO. - - When streaming data, the generic serial layer will be called - every time the FIFO receives half or this number of bytes. - - Value given here will be rounded up to next multiple of 4 bytes. - -config STM32_SERIAL_DISABLE_REORDERING - bool "Disable reordering of ttySx devices." - default n - ---help--- - NuttX per default reorders the serial ports (/dev/ttySx) so that the - console is always on /dev/ttyS0. If more than one UART is in use this - can, however, have the side-effect that all port mappings - (hardware USART1 -> /dev/ttyS0) change if the console is moved to another - UART. This is in particular relevant if a project uses the USB console - in some boards and a serial console in other boards, but does not - want the side effect of having all serial port names change when just - the console is moved from serial to USB. - -config STM32_FLOWCONTROL_BROKEN - bool "Use Software UART RTS flow control" - default n - ---help--- - Enable UART RTS flow control using Software. Because STM - Current STM32 have broken HW based RTS behavior (they assert - nRTS after every byte received) Enable this setting workaround - this issue by using software based management of RTS - -config STM32_USART_BREAKS - bool "Add TIOxSBRK to support sending Breaks" - default n - ---help--- - Add TIOCxBRK routines to send a line break per the STM32 manual, the - break will be a pulse based on the value M. This is not a BSD compatible - break. - -config STM32_SERIALBRK_BSDCOMPAT - bool "Use GPIO To send Break" - depends on STM32_USART_BREAKS - default n - ---help--- - Enable using GPIO on the TX pin to send a BSD compatible break: - TIOCSBRK will start the break and TIOCCBRK will end the break. - The current STM32 U[S]ARTS have no way to leave the break on - (TX=LOW) because software starts the break and then the hardware - automatically clears the break. This makes it difficult to send - a long break. - -config STM32_USART_SINGLEWIRE - bool "Single Wire Support" - default n - depends on STM32_USART - ---help--- - Enable single wire UART support. The option enables support for the - TIOCSSINGLEWIRE ioctl in the STM32 serial driver. - -endmenu # Serial Driver Configuration - menu "HCI UART Driver Configuration" depends on STM32_SERIALDRIVER @@ -9964,131 +4314,8 @@ config STM32_HCIUART_LOWER_WATERMARK endmenu # HCI UART Driver Configuration -if PM - -config STM32_PM_SERIAL_ACTIVITY - int "PM serial activity" - default 10 - ---help--- - PM activity reported to power management logic on every serial - interrupt. - -endif - endmenu # U[S]ART Configuration -menu "SPI Configuration" - depends on STM32_SPI - -config STM32_SPI_INTERRUPTS - bool "Interrupt driver SPI" - default n - ---help--- - Select to enable interrupt driven SPI support. Non-interrupt-driven, - poll-waiting is recommended if the interrupt rate would be to high in - the interrupt driven case. - -config STM32_SPI1_DMA - bool "SPI1 DMA" - default n - depends on STM32_SPI1 && !STM32_SPI_INTERRUPT - select STM32_SPI_DMA - ---help--- - Use DMA to improve SPI1 transfer performance. Cannot be used with STM32_SPI_INTERRUPT. - -config STM32_SPI1_DMA_BUFFER - int "SPI1 DMA buffer size" - default 0 - depends on STM32_SPI1_DMA - ---help--- - Add a properly aligned DMA buffer for RX and TX DMA for SPI1. - -config STM32_SPI_DMATHRESHOLD - int "SPI DMA threshold" - default 4 - depends on STM32_SPI_DMA - ---help--- - When SPI DMA is enabled, small DMA transfers will still be performed - by polling logic. But we need a threshold value to determine what - is small. - -config STM32_SPI2_DMA - bool "SPI2 DMA" - default n - depends on STM32_SPI2 && !STM32_SPI_INTERRUPT - select STM32_SPI_DMA - ---help--- - Use DMA to improve SPI2 transfer performance. Cannot be used with STM32_SPI_INTERRUPT. - -config STM32_SPI2_DMA_BUFFER - int "SPI2 DMA buffer size" - default 0 - depends on STM32_SPI2_DMA - ---help--- - Add a properly aligned DMA buffer for RX and TX DMA for SPI2. - -config STM32_SPI3_DMA - bool "SPI3 DMA" - default n - depends on STM32_SPI3 && !STM32_SPI_INTERRUPT - select STM32_SPI_DMA - ---help--- - Use DMA to improve SPI3 transfer performance. Cannot be used with STM32_SPI_INTERRUPT. - -config STM32_SPI3_DMA_BUFFER - int "SPI3 DMA buffer size" - default 0 - depends on STM32_SPI3_DMA - ---help--- - Add a properly aligned DMA buffer for RX and TX DMA for SPI3. - -config STM32_SPI4_DMA - bool "SPI4 DMA" - default n - depends on STM32_SPI4 && !STM32_SPI_INTERRUPT - select STM32_SPI_DMA - ---help--- - Use DMA to improve SPI4 transfer performance. Cannot be used with STM32_SPI_INTERRUPT. - -config STM32_SPI4_DMA_BUFFER - int "SPI4 DMA buffer size" - default 0 - depends on STM32_SPI4_DMA - ---help--- - Add a properly aligned DMA buffer for RX and TX DMA for SPI4. - -config STM32_SPI5_DMA - bool "SPI5 DMA" - default n - depends on STM32_SPI5 && !STM32_SPI_INTERRUPT - select STM32_SPI_DMA - ---help--- - Use DMA to improve SPI5 transfer performance. Cannot be used with STM32_SPI_INTERRUPT. - -config STM32_SPI5_DMA_BUFFER - int "SPI5 DMA buffer size" - default 0 - depends on STM32_SPI5_DMA - ---help--- - Add a properly aligned DMA buffer for RX and TX DMA for SPI5. - -config STM32_SPI6_DMA - bool "SPI6 DMA" - default n - depends on STM32_SPI6 && !STM32_SPI_INTERRUPT - select STM32_SPI_DMA - ---help--- - Use DMA to improve SPI6 transfer performance. Cannot be used with STM32_SPI_INTERRUPT. - -config STM32_SPI5_DMA_BUFFER - int "SPI5 DMA buffer size" - default 0 - depends on STM32_SPI5_DMA - ---help--- - Add a properly aligned DMA buffer for RX and TX DMA for SPI6. - -endmenu # SPI Configuration - menu "I2S Configuration" depends on STM32_I2S3 @@ -10098,55 +4325,8 @@ config STM32_I2S_MCK ---help--- TBD. -config STM32_I2S_MAXINFLIGHT - int "I2S queue size" - default 16 - ---help--- - This is the total number of transfers, both RX and TX, that can be - enqueue before the caller is required to wait. This setting - determines the number certain queue data structures that will be - pre-allocated. - comment "I2S3 Configuration" -config STM32_I2S3_DATALEN - int "Data width (bits)" - default 16 - ---help--- - Data width in bits. This is a default value and may be change - via the I2S interface - -#if STM32_I2S -config STM32_I2S3_RX - bool "Enable I2S receiver" - default n - ---help--- - Enable I2S receipt logic - -config STM32_I2S3_TX - bool "Enable I2S transmitter" - default n - ---help--- - Enable I2S transmission logic - -config STM32_I2S_DMADEBUG - bool "I2S DMA transfer debug" - depends on DEBUG_DMA - default n - ---help--- - Enable special debug instrumentation analyze I2S DMA data transfers. - This logic is as non-invasive as possible: It samples DMA - registers at key points in the data transfer and then dumps all of - the registers at the end of the transfer. - -config STM32_I2S_REGDEBUG - bool "SSC Register level debug" - depends on DEBUG - default n - ---help--- - Output detailed register-level SSC device debug information. - Very invasive! Requires also DEBUG. - endmenu # I2S Configuration menu "I2C Configuration" @@ -10163,36 +4343,6 @@ config STM32_I2C_ALT because: (1) It has not yet been fully verified and (2) It is not certain that he scope of this workaround is needed only for the F103. -config STM32_I2C_DYNTIMEO - bool "Use dynamic timeouts" - default n - depends on STM32_I2C - -config STM32_I2C_DYNTIMEO_USECPERBYTE - int "Timeout Microseconds per Byte" - default 500 - depends on STM32_I2C_DYNTIMEO - -config STM32_I2C_DYNTIMEO_STARTSTOP - int "Timeout for Start/Stop (Milliseconds)" - default 1000 - depends on STM32_I2C_DYNTIMEO - -config STM32_I2CTIMEOSEC - int "Timeout seconds" - default 0 - depends on STM32_I2C - -config STM32_I2CTIMEOMS - int "Timeout Milliseconds" - default 500 - depends on STM32_I2C && !STM32_I2C_DYNTIMEO - -config STM32_I2CTIMEOTICKS - int "Timeout for Done and Stop (ticks)" - default 500 - depends on STM32_I2C && !STM32_I2C_DYNTIMEO - config STM32_I2C_DUTY16_9 bool "Frequency with Tlow/Thigh = 16/9" default n @@ -10234,429 +4384,8 @@ config STM32_I2C_SLAVE_RETRANSFER endmenu -menu "SDIO Configuration" - depends on STM32_SDIO - -config STM32_SDIO_CARD - bool "SDIO Card support" - default n - ---help--- - Build in additional support needed only for SDIO cards (vs. SD - memory cards) - -config STM32_SDIO_PULLUP - bool "Enable internal Pull-Ups" - default n - ---help--- - If you are using an external SDCard module that does not have the - pull-up resistors for the SDIO interface (like the Gadgeteer SD Card - Module) then enable this option to activate the internal pull-up - resistors. - -config STM32_SDIO_DMA - bool "Support DMA data transfers" - default STM32_DMA2 - select SDIO_DMA - depends on STM32_DMA2 - ---help--- - Support DMA data transfers. Requires STM32_SDIO and config STM32_DMA2. - -config STM32_SDIO_DMAPRIO - hex "SDIO DMA priority" - default 0x00001000 if STM32_STM32F10XX - default 0x00010000 if !STM32_STM32F10XX - ---help--- - Select SDIO DMA priority. - - For STM32 F1 family, options are: 0x00000000 low, 0x00001000 medium, - 0x00002000 high, 0x00003000 very high. Default: medium. - - For other STM32's, options are: 0x00000000 low, 0x00010000 medium, - 0x00020000 high, 0x00030000 very high. Default: medium. - -config STM32_SDIO_WIDTH_D1_ONLY - bool "Use D1 only" - default n - ---help--- - Select 1-bit transfer mode. Default: 4-bit transfer mode. - -endmenu - -if STM32_BKPSRAM - -config STM32_BBSRAM - bool "BBSRAM File Support" - default n - -config STM32_BBSRAM_FILES - int "Max Files to support in BBSRAM" - default 4 - -config STM32_SAVE_CRASHDUMP - bool "Enable Saving Panic to BBSRAM" - default n - -endif # STM32_BKPSRAM - -config STM32_HAVE_RTC_COUNTER - bool - default n - -config STM32_HAVE_RTC_SUBSECONDS - bool - select ARCH_HAVE_RTC_SUBSECONDS - default n - -menu "RTC Configuration" - depends on STM32_RTC - -config STM32_RTC_MAGIC_REG - int "BKP register" - default 0 - range 0 19 - depends on !STM32_HAVE_RTC_COUNTER - ---help--- - The BKP register used to store/check the Magic value to determine if - RTC is already setup - -config STM32_RTC_MAGIC - hex "RTC Magic 1" - default 0xfacefeed - depends on !STM32_HAVE_RTC_COUNTER - ---help--- - Value used as Magic to determine if the RTC is already setup - -config STM32_RTC_MAGIC_TIME_SET - hex "RTC Magic 2" - default 0xf00dface - depends on !STM32_HAVE_RTC_COUNTER - ---help--- - Value used as Magic to determine if the RTC has been setup and has - time set - -endmenu # RTC configuration - -menu "Ethernet MAC configuration" - depends on STM32_ETHMAC - -config STM32_PHYADDR - int "PHY address" - default 1 - ---help--- - The 5-bit address of the PHY on the board. Default: 1 - -config STM32_PHYINIT - bool "Board-specific PHY Initialization" - default n - ---help--- - Some boards require specialized initialization of the PHY before it can be used. - This may include such things as configuring GPIOs, resetting the PHY, etc. If - STM32_PHYINIT is defined in the configuration then the board specific logic must - provide stm32_phyinitialize(); The STM32 Ethernet driver will call this function - one time before it first uses the PHY. - -config STM32_MII - bool "Use MII interface" - default n - ---help--- - Support Ethernet MII interface. - -config STM32_AUTONEG - bool "Use autonegotiation" - default y - ---help--- - Use PHY autonegotiation to determine speed and mode - -config STM32_ETHFD - bool "Full duplex" - default n - depends on !STM32_AUTONEG - ---help--- - If STM32_AUTONEG is not defined, then this may be defined to select full duplex - mode. Default: half-duplex - -config STM32_ETH100MBPS - bool "100 Mbps" - default n - depends on !STM32_AUTONEG - ---help--- - If STM32_AUTONEG is not defined, then this may be defined to select 100 MBps - speed. Default: 10 Mbps - -config STM32_PHYSR - int "PHY Status Register Address (decimal)" - depends on STM32_AUTONEG - ---help--- - This must be provided if STM32_AUTONEG is defined. The PHY status register - address may diff from PHY to PHY. This configuration sets the address of - the PHY status register. - -config STM32_PHYSR_ALTCONFIG - bool "PHY Status Alternate Bit Layout" - default n - depends on STM32_AUTONEG - ---help--- - Different PHYs present speed and mode information in different ways. Some - will present separate information for speed and mode (this is the default). - Those PHYs, for example, may provide a 10/100 Mbps indication and a separate - full/half duplex indication. This options selects an alternative representation - where speed and mode information are combined. This might mean, for example, - separate bits for 10HD, 100HD, 10FD and 100FD. - -config STM32_PHYSR_SPEED - hex "PHY Speed Mask" - depends on STM32_AUTONEG && !STM32_PHYSR_ALTCONFIG - ---help--- - This must be provided if STM32_AUTONEG is defined. This provides bit mask - for isolating the 10 or 100MBps speed indication. - -config STM32_PHYSR_100MBPS - hex "PHY 100Mbps Speed Value" - depends on STM32_AUTONEG && !STM32_PHYSR_ALTCONFIG - ---help--- - This must be provided if STM32_AUTONEG is defined. This provides the value - of the speed bit(s) indicating 100MBps speed. - -config STM32_PHYSR_MODE - hex "PHY Mode Mask" - depends on STM32_AUTONEG && !STM32_PHYSR_ALTCONFIG - ---help--- - This must be provided if STM32_AUTONEG is defined. This provide bit mask - for isolating the full or half duplex mode bits. - -config STM32_PHYSR_FULLDUPLEX - hex "PHY Full Duplex Mode Value" - depends on STM32_AUTONEG && !STM32_PHYSR_ALTCONFIG - ---help--- - This must be provided if STM32_AUTONEG is defined. This provides the - value of the mode bits indicating full duplex mode. - -config STM32_PHYSR_ALTMODE - hex "PHY Mode Mask" - depends on STM32_AUTONEG && STM32_PHYSR_ALTCONFIG - ---help--- - This must be provided if STM32_AUTONEG is defined. This provide bit mask - for isolating the speed and full/half duplex mode bits. - -config STM32_PHYSR_10HD - hex "10MBase-T Half Duplex Value" - depends on STM32_AUTONEG && STM32_PHYSR_ALTCONFIG - ---help--- - This must be provided if STM32_AUTONEG is defined. This is the value - under the bit mask that represents the 10Mbps, half duplex setting. - -config STM32_PHYSR_100HD - hex "100Base-T Half Duplex Value" - depends on STM32_AUTONEG && STM32_PHYSR_ALTCONFIG - ---help--- - This must be provided if STM32_AUTONEG is defined. This is the value - under the bit mask that represents the 100Mbps, half duplex setting. - -config STM32_PHYSR_10FD - hex "10Base-T Full Duplex Value" - depends on STM32_AUTONEG && STM32_PHYSR_ALTCONFIG - ---help--- - This must be provided if STM32_AUTONEG is defined. This is the value - under the bit mask that represents the 10Mbps, full duplex setting. - -config STM32_PHYSR_100FD - hex "100Base-T Full Duplex Value" - depends on STM32_AUTONEG && STM32_PHYSR_ALTCONFIG - ---help--- - This must be provided if STM32_AUTONEG is defined. This is the value - under the bit mask that represents the 100Mbps, full duplex setting. - -config STM32_ETH_ENHANCEDDESC - bool "Enable enhanced RX/TX descriptors" - default n - ---help--- - Enables double-length DMA descriptors that have space for packet - timestamps and checksum offloading. - -config STM32_ETH_PTP - bool "Precision Time Protocol (PTP)" - default n - ---help--- - Enables Precision Time Protocol (PTP) hardware timer. - -config STM32_ETH_PTP_GPIO - bool "PTP pulse-per-second output signal" - depends on STM32_ETH_PTP - default n - ---help--- - Enables pulse-per-second output on GPIO pin. - -config STM32_ETH_PTP_RTC_HIRES - bool "Use PTP timer as system high-resolution RTC" - depends on STM32_ETH_PTP - default n - ---help--- - Uses the Ethernet peripheral PTP timer as the CONFIG_RTC_HIRES source. - This provides high resolution timestamps to clock_gettime(). - Note that PTP timer is disabled when Ethernet interface is down or - being reset. During this time g_rtc_enabled is set to false and system - uses the lower resolution system tick counter. - -config STM32_ETH_TIMESTAMP_RX - bool "Hardware timestamping of received packets" - depends on STM32_ETH_PTP && NET_TIMESTAMP && STM32_ETH_ENHANCEDDESC - select ARCH_HAVE_NETDEV_TIMESTAMP - default n - ---help--- - Timestamp all received Ethernet packets. - Timestamp is available to application through SO_TIMESTAMP socket option. - -config STM32_RMII - bool - default !STM32_MII - -config STM32_ETHMAC_REGDEBUG - bool "Register-Level Debug" - default n - depends on DEBUG_NET_INFO - ---help--- - Enable very low-level register access debug. Depends on CONFIG_DEBUG_FEATURES. - -endmenu # Ethernet MAC configuration - -config STM32_USBHOST - bool "Enable USB Host Support" - depends on STM32_OTGFS || STM32_OTGHS - default n - select USBHOST - -menu "USB FS Host Configuration" - depends on STM32_OTGFS && STM32_USBHOST - -config STM32_OTGFS_RXFIFO_SIZE - int "Rx Packet Size" - default 128 - ---help--- - Size of the RX FIFO in 32-bit words. Default 128 (512 bytes) - -config STM32_OTGFS_NPTXFIFO_SIZE - int "Non-periodic Tx FIFO Size" - default 96 - ---help--- - Size of the non-periodic Tx FIFO in 32-bit words. Default 96 (384 bytes) - -config STM32_OTGFS_PTXFIFO_SIZE - int "Periodic Tx FIFO size" - default 128 - ---help--- - Size of the periodic Tx FIFO in 32-bit words. Default 96 (384 bytes) - -config STM32_OTGFS_DESCSIZE - int "Descriptor Size" - default 128 - ---help--- - Maximum size to allocate for descriptor memory descriptor. Default: 128 - -config STM32_OTGFS_SOFINTR - bool "Enable SOF interrupts" - default n - ---help--- - Enable SOF interrupts. Why would you ever want to do that? - -config STM32_OTGFS_VBUS_CONTROL - bool "Enable VBus Control" - default y - ---help--- - Enable VBus control. Used when the board has VBus sensing and - a power switch for the OTG FS USB port. Disable this config - if the board lacks this USB VBus control circuitry. - -endmenu - -menu "USB HS Host Configuration" - depends on STM32_OTGHS && STM32_USBHOST - -config STM32_OTGHS_RXFIFO_SIZE - int "Rx Packet Size" - default 128 - ---help--- - Size of the RX FIFO in 32-bit words. Default 128 (512 bytes) - -config STM32_OTGHS_NPTXFIFO_SIZE - int "Non-periodic Tx FIFO Size" - default 96 - ---help--- - Size of the non-periodic Tx FIFO in 32-bit words. Default 96 (384 bytes) - -config STM32_OTGHS_PTXFIFO_SIZE - int "Periodic Tx FIFO size" - default 128 - ---help--- - Size of the periodic Tx FIFO in 32-bit words. Default 96 (384 bytes) - -config STM32_OTGHS_DESCSIZE - int "Descriptor Size" - default 128 - ---help--- - Maximum size to allocate for descriptor memory descriptor. Default: 128 - -config STM32_OTGHS_SOFINTR - bool "Enable SOF interrupts" - default n - ---help--- - Enable SOF interrupts. Why would you ever want to do that? - -config STM32_OTGHS_VBUS_CONTROL - bool "Enable VBus Control" - default y - ---help--- - Enable VBus control. Used when the board has VBus sensing and - a power switch for the OTG HS USB port. Disable this config - if the board lacks this USB VBus control circuitry. - -endmenu - -menu "USB Host Debug Configuration" - depends on STM32_USBHOST - -config STM32_USBHOST_REGDEBUG - bool "Register-Level Debug" - default n - depends on STM32_USBHOST && DEBUG_USB_INFO - ---help--- - Enable very low-level register access debug. - -config STM32_USBHOST_PKTDUMP - bool "Packet Dump Debug" - default n - depends on STM32_USBHOST && DEBUG_USB_INFO - ---help--- - Dump all incoming and outgoing USB packets. - -endmenu - comment "USB Device Configuration" -menu "USB Full Speed Debug Configuration" - depends on STM32_USBFS - -config STM32_USBFS_REGDEBUG - bool "Register-Level Debug" - default n - depends on STM32_USBFS && DEBUG_USB_INFO - ---help--- - Enable very low-level register access debug. - -endmenu - -menu "OTG Configuration" - depends on STM32_OTGFS - -config OTG_ID_GPIO_DISABLE - bool "Disable the use of GPIO_OTG_ID pin." - default n - ---help--- - Disables/Enables the use of GPIO_OTG_ID pin. This allows non OTG use - cases to reuse this GPIO pin and ensure it is not set incorrectlty - during OS boot. - -endmenu - config STM32_USB_ITRMP bool "Re-map USB interrupt" default STM32_CAN1 @@ -10668,779 +4397,12 @@ config STM32_USB_ITRMP their own dedicated vectors. The option is available only for the F3 family and selects the use of the dedicated USB interrupts. -menu "CAN driver configuration" - depends on STM32_CAN - -config STM32_CAN1_BAUD - int "CAN1 BAUD" - default 250000 - depends on STM32_CAN1 - ---help--- - CAN1 BAUD rate. Required if CONFIG_STM32_CAN1 is defined. - -config STM32_CAN2_BAUD - int "CAN2 BAUD" - default 250000 - depends on STM32_CAN2 - ---help--- - CAN2 BAUD rate. Required if CONFIG_STM32_CAN2 is defined. - -config STM32_CAN_TSEG1 - int "TSEG1 quanta" - default 6 - ---help--- - The number of CAN time quanta in segment 1. Default: 6 - -config STM32_CAN_TSEG2 - int "TSEG2 quanta" - default 7 - ---help--- - The number of CAN time quanta in segment 2. Default: 7 - -config STM32_CAN_REGDEBUG - bool "CAN Register level debug" - depends on DEBUG_CAN_INFO - default n - ---help--- - Output detailed register-level CAN device debug information. - Requires also CONFIG_DEBUG_CAN_INFO. - -endmenu # "CAN driver configuration" - -menu "FDCAN driver configuration" - depends on STM32_FDCAN - -config STM32_FDCAN_REGDEBUG - bool "CAN Register level debug" - depends on DEBUG_CAN_INFO - default n - ---help--- - Output detailed register-level CAN device debug information. - Requires also CONFIG_DEBUG_CAN_INFO. - -config STM32_FDCAN_QUEUE_MODE - bool "FDCAN QUEUE mode (vs FIFO mode)" - default n - -menu "FDCAN1 device driver options" - depends on STM32_FDCAN1 - -config STM32_FDCAN1_LOOPBACK - bool "Enable FDCAN1 loopback mode" - default n - ---help--- - Enable the FDCAN1 local loopback mode for testing purposes. - -comment "Nominal Bit Timing" - -config STM32_FDCAN1_BITRATE - int "FDCAN bitrate" - default 500000 - range 0 1000000 - ---help--- - FDCAN1 bitrate in bits per second. Required if STM32_FDCAN1 is defined. - -config STM32_FDCAN1_NTSEG1 - int "FDCAN1 NTSEG1 (PropSeg + PhaseSeg1)" - default 6 - range 1 256 if STM32_STM32G4XXX - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -config STM32_FDCAN1_NTSEG2 - int "FDCAN1 NTSEG2 (PhaseSeg2)" - default 7 - range 1 128 if STM32_STM32G4XXX - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -config STM32_FDCAN1_NSJW - int "FDCAN1 synchronization jump width" - default 1 - range 1 128 if STM32_STM32G4XXX - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -comment "Data Bit Timing" - depends on CAN_FD && STM32_FDCAN1_FD_BRS - -config STM32_FDCAN1_DBITRATE - int "FDCAN1 data bitrate" - default 2000000 - depends on CAN_FD && STM32_FDCAN1_FD_BRS - ---help--- - FDCAN1 bitrate in bits per second. Required if operating in FD mode with bit rate switching (BRS). - -config STM32_FDCAN1_DTSEG1 - int "FDCAN1 DTSEG1 (PropSeg + PhaseSeg1 of data phase)" - default 4 - range 1 31 if STM32_STM32G4XXX - depends on CAN_FD && STM32_FDCAN1_FD_BRS - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -config STM32_FDCAN1_DTSEG2 - int "FDCAN1 DTSEG2 (PhaseSeg2 of data phase)" - default 4 - range 1 15 if STM32_STM32G4XXX - depends on CAN_FD && STM32_FDCAN1_FD_BRS - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -config STM32_FDCAN1_DSJW - int "FDCAN1 fast synchronization jump width" - default 2 - range 1 15 if STM32_STM32G4XXX - depends on CAN_FD && STM32_FDCAN1_FD_BRS - ---help--- - The duration of a synchronization jump is Tcan_clk x DSJW. - -endmenu # FDCAN1 device driver options - -menu "FDCAN2 device driver options" - depends on STM32_FDCAN2 - -config STM32_FDCAN2_LOOPBACK - bool "Enable FDCAN2 loopback mode" - default n - ---help--- - Enable the FDCAN2 local loopback mode for testing purposes. - -comment "Nominal Bit Timing" - -config STM32_FDCAN2_BITRATE - int "FDCAN bitrate" - default 500000 - range 0 1000000 - ---help--- - FDCAN2 bitrate in bits per second. Required if STM32_FDCAN2 is defined. - -config STM32_FDCAN2_NTSEG1 - int "FDCAN2 NTSEG1 (PropSeg + PhaseSeg1)" - default 6 - range 1 256 if STM32_STM32G4XXX - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -config STM32_FDCAN2_NTSEG2 - int "FDCAN2 NTSEG2 (PhaseSeg2)" - default 7 - range 1 128 if STM32_STM32G4XXX - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -config STM32_FDCAN2_NSJW - int "FDCAN2 synchronization jump width" - default 1 - range 1 128 if STM32_STM32G4XXX - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -comment "Data Bit Timing" - depends on CAN_FD && STM32_FDCAN2_FD_BRS - -config STM32_FDCAN2_DBITRATE - int "FDCAN2 data bitrate" - default 2000000 - depends on CAN_FD && STM32_FDCAN2_FD_BRS - ---help--- - FDCAN2 bitrate in bits per second. Required if operating in FD mode with bit rate switching (BRS). - -config STM32_FDCAN2_DTSEG1 - int "FDCAN2 DTSEG1 (PropSeg + PhaseSeg1 of data phase)" - default 4 - range 1 31 if STM32_STM32G4XXX - depends on CAN_FD && STM32_FDCAN2_FD_BRS - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -config STM32_FDCAN2_DTSEG2 - int "FDCAN2 DTSEG2 (PhaseSeg2 of data phase)" - default 4 - range 1 15 if STM32_STM32G4XXX - depends on CAN_FD && STM32_FDCAN2_FD_BRS - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -config STM32_FDCAN2_DSJW - int "FDCAN2 fast synchronization jump width" - default 2 - range 1 15 if STM32_STM32G4XXX - depends on CAN_FD && STM32_FDCAN2_FD_BRS - ---help--- - The duration of a synchronization jump is Tcan_clk x DSJW. - -endmenu # FDCAN2 device driver options - -menu "FDCAN3 device driver options" - depends on STM32_FDCAN3 - -choice - prompt "FDCAN3 frame format" - default STM32_FDCAN3_ISO11898_1 - -config STM32_FDCAN3_ISO11898_1 - bool "ISO11898-1" - ---help--- - Enable ISO11898-1 frame format - -config STM32_FDCAN3_NONISO_FORMAT - bool "Non ISO" - ---help--- - Enable Non ISO, Bosch CAN FD Specification V1.0 - -endchoice # FDCAN3 frame format - -choice - prompt "FDCAN3 mode" - default STM32_FDCAN3_CLASSIC - -config STM32_FDCAN3_CLASSIC - bool "Classic CAN" - ---help--- - Enable Classic CAN mode - -config STM32_FDCAN3_FD - bool "CAN FD" - depends on CAN_FD || NET_CAN_CANFD - ---help--- - Enable CAN FD mode - -config STM32_FDCAN3_FD_BRS - bool "CAN FD with fast bit rate switching" - depends on CAN_FD || NET_CAN_CANFD - ---help--- - Enable CAN FD mode with fast bit rate switching mode. - -endchoice # FDCAN3 mode - -config STM32_FDCAN3_LOOPBACK - bool "Enable FDCAN3 loopback mode" - default n - ---help--- - Enable the FDCAN3 local loopback mode for testing purposes. - -comment "Nominal Bit Timing" - -config STM32_FDCAN3_BITRATE - int "FDCAN bitrate" - default 500000 - range 0 1000000 - ---help--- - FDCAN3 bitrate in bits per second. Required if STM32_FDCAN3 is defined. - -config STM32_FDCAN3_NTSEG1 - int "FDCAN3 NTSEG1 (PropSeg + PhaseSeg1)" - default 6 - range 1 256 if STM32_STM32G4XXX - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -config STM32_FDCAN3_NTSEG2 - int "FDCAN3 NTSEG2 (PhaseSeg2)" - default 7 - range 1 128 if STM32_STM32G4XXX - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -config STM32_FDCAN3_NSJW - int "FDCAN3 synchronization jump width" - default 1 - range 1 128 if STM32_STM32G4XXX - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -comment "Data Bit Timing" - depends on CAN_FD && STM32_FDCAN3_FD_BRS - -config STM32_FDCAN3_DBITRATE - int "FDCAN3 data bitrate" - default 2000000 - depends on CAN_FD && STM32_FDCAN3_FD_BRS - ---help--- - FDCAN3 bitrate in bits per second. Required if operating in FD mode with bit rate switching (BRS). - -config STM32_FDCAN3_DTSEG1 - int "FDCAN3 DTSEG1 (PropSeg + PhaseSeg1 of data phase)" - default 4 - range 1 31 if STM32_STM32G4XXX - depends on CAN_FD && STM32_FDCAN3_FD_BRS - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -config STM32_FDCAN3_DTSEG2 - int "FDCAN3 DTSEG2 (PhaseSeg2 of data phase)" - default 4 - range 1 15 if STM32_STM32G4XXX - depends on CAN_FD && STM32_FDCAN3_FD_BRS - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -config STM32_FDCAN3_DSJW - int "FDCAN3 fast synchronization jump width" - default 2 - range 1 15 if STM32_STM32G4XXX - depends on CAN_FD && STM32_FDCAN3_FD_BRS - ---help--- - The duration of a synchronization jump is Tcan_clk x DSJW. - -endmenu # FDCAN3 device driver options - -endmenu # "FDCAN driver configuration" - -if STM32_LTDC - -menu "LTDC Configuration" - -config STM32_LTDC_BACKLIGHT - bool "Backlight support" - default y - -config STM32_LTDC_DEFBACKLIGHT - hex "Default backlight level" - default 0xf0 - -config STM32_LTDC_BACKCOLOR - hex "Background color" - default 0x0 - ---help--- - This is the background color that will be used as the LTDC - background layer color. It is an RGB888 format value. - -config STM32_LTDC_DITHER - bool "Dither support" - default n - -config STM32_LTDC_DITHER_RED - depends on STM32_LTDC_DITHER - int "Dither red width" - range 0 7 - default 2 - ---help--- - This is the dither red width. - -config STM32_LTDC_DITHER_GREEN - depends on STM32_LTDC_DITHER - int "Dither green width" - range 0 7 - default 2 - ---help--- - This is the dither green width. - -config STM32_LTDC_DITHER_BLUE - depends on STM32_LTDC_DITHER - int "Dither blue width" - range 0 7 - default 2 - ---help--- - This is the dither blue width. - -config STM32_LTDC_FB_BASE - hex "Framebuffer memory start address" - default 0 - ---help--- - If you are using the LTDC, then you must provide the address - of the start of the framebuffer. This address will typically - be in the SRAM or SDRAM memory region of the FSMC/FMC. - -config STM32_LTDC_FB_SIZE - int "Framebuffer memory size (bytes)" - default 0 - ---help--- - Must be the whole size of the active LTDC layer. - -config STM32_LTDC_L1_CHROMAKEYEN - bool "Enable chromakey support for layer 1" - default y - -config STM32_LTDC_L1_CHROMAKEY - hex "Layer L1 initial chroma key" - default 0x00000000 - -config STM32_LTDC_L1_COLOR - hex "Layer L1 default color" - default 0x00000000 - -config STM32_LTDC_L2 - bool "Enable Layer 2 support" - default y - -if STM32_LTDC_L2 - -config STM32_LTDC_L2_COLOR - hex "Layer L2 default color" - default 0x00000000 - -config STM32_LTDC_L2_CHROMAKEYEN - bool "Enable chromakey support for layer 2" - default y - -config STM32_LTDC_L2_CHROMAKEY - hex "Layer L2 initial chroma key" - default 0x00000000 - -endif # STM32_LTDC_L2 - -config STM32_FB_CMAP - bool "Color map support" - default y - select FB_CMAP - ---help--- - Enabling color map support is necessary for LTDC L8 format. - -config STM32_FB_TRANSPARENCY - bool "Transparency color map support" - default y - depends on STM32_FB_CMAP - select FB_TRANSPARENCY - ---help--- - Enabling transparency color map support is necessary for LTDC L8 format. - -config STM32_LTDC_REGDEBUG - bool "LTDC Register level debug" - depends on DEBUG_INFO && DEBUG_LCD - default n - ---help--- - Output detailed register-level LTDC device debug information. -endmenu - -endif # STM32_LTDC - -if STM32_DMA2D - -menu "DMA2D Configuration" - -config STM32_DMA2D_NLAYERS - int "Number DMA2D overlays" - default 1 - range 1 256 - ---help--- - Number of supported DMA2D layer. - -config STM32_DMA2D_LAYER_SHARED - bool "Overlays shared memory region" - default n - ---help--- - Several overlays can share the same memory region. - Setup a whole memory area (usually multiple size of the visible screen) - allows image preprocessing before they become visible by blit operation. - -config STM32_DMA2D_LAYER_PPLINE - int "Pixel per line" - default 1 - range 1 65535 - ---help--- - If you are using the DMA2D, then you must provide the pixel per line or - width of the overlay. - -config STM32_DMA2D_FB_BASE - hex "Framebuffer memory start address" - default 0 - ---help--- - If you are using the DMA2D, then you must provide the address - of the start of the DMA2D overlays framebuffer. This address will typically - be in the SRAM or SDRAM memory region of the FSMC/FMC. - -config STM32_DMA2D_FB_SIZE - int "Framebuffer memory size (bytes)" - default 0 - ---help--- - Must be the whole size of all DMA2D overlays. - -menu "Supported pixel format" - -config STM32_DMA2D_L8 - depends on STM32_FB_CMAP && STM32_LTDC_L1_L8 - bool "8 bpp L8 (8-bit CLUT)" - default y - -config STM32_DMA2D_AL44 - depends on STM32_FB_CMAP && STM32_LTDC_L1_AL44 - bool "8 bpp AL44 (4-bit alpha + 4-bit CLUT)" - default y - -config STM32_DMA2D_AL88 - depends on STM32_FB_CMAP && STM32_LTDC_L1_AL88 - bool "16 bpp AL88 (8-bit alpha + 8-bit CLUT)" - default y - -config STM32_DMA2D_RGB565 - bool "16 bpp RGB 565" - depends on STM32_LTDC_L1_RGB565 - default y - -config STM32_DMA2D_ARGB4444 - bool "16 bpp ARGB 4444" - depends on STM32_LTDC_L1_ARGB4444 - default y - -config STM32_DMA2D_ARGB1555 - bool "16 bpp ARGB 1555" - depends on STM32_LTDC_L1_ARGB15555 - default y - -config STM32_DMA2D_RGB888 - bool "24 bpp RGB 888" - depends on STM32_LTDC_L1_RGB888 - default y - -config STM32_DMA2D_ARGB8888 - bool "32 bpp ARGB 8888" - depends on STM32_LTDC_L1_ARGB8888 - default y - -endmenu - -config STM32_DMA2D_REGDEBUG - bool "DMA2D Register level debug" - depends on DEBUG_INFO && DEBUG_LCD - default n - ---help--- - Output detailed register-level DMA2D device debug information. - -endmenu -endif # STM32_DMA2D - config STM32_QE bool default n -menu "STM32 QEncoder Driver" - depends on SENSORS_QENCODER - depends on STM32_TIM1 || STM32_TIM2 || STM32_TIM3 || STM32_TIM4 || STM32_TIM5 || STM32_TIM8 - -config STM32_QENCODER_DISABLE_EXTEND16BTIMERS - bool "Disable QEncoder timers extension from 16-bit to 32-bit" - default n - -config STM32_QENCODER_INDEX_PIN - bool "Enable QEncoder timers support for index pin" - default n - -config STM32_TIM1_QE - bool "TIM1 QE" - default n - depends on STM32_TIM1 - select STM32_QE - ---help--- - Reserve TIM1 for use by QEncoder. - -if STM32_TIM1_QE - -config STM32_TIM1_QEPSC - int "TIM1 QE pulse prescaler" - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, - limiting the count rate at the expense of resolution. - -endif - -config STM32_TIM2_QE - bool "TIM2 QE" - default n - depends on STM32_TIM2 - select STM32_QE - ---help--- - Reserve TIM2 for use by QEncoder. - -if STM32_TIM2_QE - -config STM32_TIM2_QEPSC - int "TIM2 QE pulse prescaler" - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, - limiting the count rate at the expense of resolution. - -endif - -config STM32_TIM3_QE - bool "TIM3 QE" - default n - depends on STM32_TIM3 - select STM32_QE - ---help--- - Reserve TIM3 for use by QEncoder. - -if STM32_TIM3_QE - -config STM32_TIM3_QEPSC - int "TIM3 QE pulse prescaler" - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, - limiting the count rate at the expense of resolution. - -endif - -config STM32_TIM4_QE - bool "TIM4 QE" - default n - depends on STM32_TIM4 - select STM32_QE - ---help--- - Reserve TIM4 for use by QEncoder. - -if STM32_TIM4_QE - -config STM32_TIM4_QEPSC - int "TIM4 QE pulse prescaler" - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, - limiting the count rate at the expense of resolution. - -endif - -config STM32_TIM5_QE - bool "TIM5 QE" - default n - depends on STM32_TIM5 - select STM32_QE - ---help--- - Reserve TIM5 for use by QEncoder. - -if STM32_TIM5_QE - -config STM32_TIM5_QEPSC - int "TIM5 QE pulse prescaler" - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, - limiting the count rate at the expense of resolution. - -endif - -config STM32_TIM8_QE - bool "TIM8 QE" - default n - depends on STM32_TIM8 - select STM32_QE - ---help--- - Reserve TIM8 for use by QEncoder. - -if STM32_TIM8_QE - -config STM32_TIM8_QEPSC - int "TIM8 QE pulse prescaler" - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, - limiting the count rate at the expense of resolution. - -endif - -config STM32_QENCODER_FILTER - bool "Enable filtering on STM32 QEncoder input" - default y - -endmenu - -menuconfig STM32_FOC - bool "STM32 lower-half FOC support" - default n - select ARCH_IRQPRIO - select STM32_ADC - select STM32_PWM_MULTICHAN - select STM32_PWM_LL_OPS - select STM32_ADC_LL_OPS - select STM32_ADC_CHANGE_SAMPLETIME - select STM32_ADC_NO_STARTUP_CONV - if STM32_FOC -config STM32_FOC_FOC0 - bool "FOC0 device (TIM1 for PWM modulation)" - default n - depends on STM32_HAVE_TIM1 - select STM32_FOC_USE_TIM1 - ---help--- - Enable support for FOC0 device that uses TIM1 for PWM modulation - -config STM32_FOC_FOC1 - bool "FOC1 device (TIM8 for PWM modulation)" - default n - depends on STM32_HAVE_TIM8 - select STM32_FOC_USE_TIM8 - ---help--- - Enable support for FOC1 device that uses TIM8 for PWM modulation - -if STM32_FOC_FOC0 - -endif # STM32_FOC_FOC0 - -if STM32_FOC_FOC1 - -endif # STM32_FOC_FOC1 - -config STM32_FOC_HAS_PWM_COMPLEMENTARY - bool "FOC PWM has complementary outputs" - default n - ---help--- - Enable complementary outputs for the FOC PWM (sometimes called 6-PWM mode) - -# hidden variables and automatic configuration - -config STM32_FOC_USE_TIM1 - bool - default n - select STM32_TIM1 - select STM32_TIM1_PWM - select STM32_TIM1_CHANNEL1 - select STM32_TIM1_CHANNEL2 - select STM32_TIM1_CHANNEL3 - select STM32_TIM1_CHANNEL4 if STM32_FOC_ADC_CCR4 - select STM32_TIM1_CH1OUT - select STM32_TIM1_CH2OUT - select STM32_TIM1_CH3OUT - select STM32_TIM1_CH4OUT if STM32_FOC_ADC_CCR4 - select STM32_TIM1_CH1NOUT if STM32_FOC_HAS_PWM_COMPLEMENTARY - select STM32_TIM1_CH2NOUT if STM32_FOC_HAS_PWM_COMPLEMENTARY - select STM32_TIM1_CH3NOUT if STM32_FOC_HAS_PWM_COMPLEMENTARY - ---help--- - The TIM1 generates PWM for the FOC - -config STM32_FOC_USE_TIM8 - bool - default n - select STM32_TIM8 - select STM32_TIM8_PWM - select STM32_TIM8_CHANNEL1 - select STM32_TIM8_CHANNEL2 - select STM32_TIM8_CHANNEL3 - select STM32_TIM8_CHANNEL4 if STM32_FOC_ADC_CCR4 - select STM32_TIM8_CH1OUT - select STM32_TIM8_CH2OUT - select STM32_TIM8_CH3OUT - select STM32_TIM8_CH4OUT if STM32_FOC_ADC_CCR4 - select STM32_TIM8_CH1NOUT if STM32_FOC_HAS_PWM_COMPLEMENTARY - select STM32_TIM8_CH2NOUT if STM32_FOC_HAS_PWM_COMPLEMENTARY - select STM32_TIM8_CH3NOUT if STM32_FOC_HAS_PWM_COMPLEMENTARY - ---help--- - The TIM8 generates PWM for the FOC - -config STM32_FOC_USE_ADC1 - bool - default n - select STM32_ADC1 - select STM32_ADC1_SCAN if STM32_HAVE_IP_ADC_V1 - select STM32_ADC1_JEXTSEL - -config STM32_FOC_USE_ADC2 - bool - default n - select STM32_ADC2 - select STM32_ADC2_SCAN if STM32_HAVE_IP_ADC_V1 - select STM32_ADC2_JEXTSEL - -config STM32_FOC_USE_ADC3 - bool - default n - select STM32_ADC3 - select STM32_ADC3_SCAN if STM32_HAVE_IP_ADC_V1 - select STM32_ADC3_JEXTSEL - config STM32_FOC_USE_ADC4 bool default n diff --git a/arch/arm/src/stm32f0l0g0/Kconfig b/arch/arm/src/stm32f0l0g0/Kconfig index 1ae81719d04..3680c9a8ac3 100644 --- a/arch/arm/src/stm32f0l0g0/Kconfig +++ b/arch/arm/src/stm32f0l0g0/Kconfig @@ -5,6 +5,17 @@ comment "STM32F0/L0/G0 Configuration Options" +config STM32_F0L0G0_PERIPHERALS + bool + default y + depends on ARCH_CHIP_STM32F0 || ARCH_CHIP_STM32L0 || ARCH_CHIP_STM32G0 || ARCH_CHIP_STM32C0 + select STM32_HAVE_COMP + select STM32_HAVE_I2C1 + select STM32_HAVE_SPI1 + select STM32_HAVE_SYSCFG + select STM32_HAVE_USART1 + select STM32_HAVE_USART2 + choice prompt "ST STM32F0/L0/G0 Chip Selection" default ARCH_CHIP_STM32F051R8 if ARCH_CHIP_STM32F0 @@ -643,86 +654,6 @@ config ARCH_CHIP_STM32G0B1VE select STM32_FLASH_CONFIG_E depends on ARCH_CHIP_STM32G0 -config ARCH_CHIP_STM32G0B1KB - bool "STM32G0B1KB" - select STM32_STM32G0B1 - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G0B1CB - bool "STM32G0B1CB" - select STM32_STM32G0B1 - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G0B1RB - bool "STM32G0B1RB" - select STM32_STM32G0B1 - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G0B1MB - bool "STM32G0B1MB" - select STM32_STM32G0B1 - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G0B1VB - bool "STM32G0B1VB" - select STM32_STM32G0B1 - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G0B1KC - bool "STM32G0B1KC" - select STM32_STM32G0B1 - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G0B1CC - bool "STM32G0B1CC" - select STM32_STM32G0B1 - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G0B1RC - bool "STM32G0B1RC" - select STM32_STM32G0B1 - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G0B1MC - bool "STM32G0B1MC" - select STM32_STM32G0B1 - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G0B1VC - bool "STM32G0B1VC" - select STM32_STM32G0B1 - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G0B1KE - bool "STM32G0B1KE" - select STM32_STM32G0B1 - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G0B1CE - bool "STM32G0B1CE" - select STM32_STM32G0B1 - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G0B1RE - bool "STM32G0B1RE" - select STM32_STM32G0B1 - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G0B1NE - bool "STM32G0B1NE" - select STM32_STM32G0B1 - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G0B1ME - bool "STM32G0B1ME" - select STM32_STM32G0B1 - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G0B1VE - bool "STM32G0B1VE" - select STM32_STM32G0B1 - depends on ARCH_CHIP_STM32G0 - config ARCH_CHIP_STM32L053C8 bool "STM32L053C8" select ARCH_CHIP_STM32L053XX @@ -1115,46 +1046,6 @@ endchoice # ST STM32F0/L0/G0/C0 Chip Selection # Flash configurations -config STM32_FLASH_CONFIG_4 - bool - default n - -config STM32_FLASH_CONFIG_6 - bool - default n - -config STM32_FLASH_CONFIG_8 - bool - default n - -config STM32_FLASH_CONFIG_B - bool - default n - -config STM32_FLASH_CONFIG_C - bool - default n - -config STM32_FLASH_CONFIG_D - bool - default n - -config STM32_FLASH_CONFIG_E - bool - default n - -config STM32_FLASH_CONFIG_F - bool - default n - -config STM32_FLASH_CONFIG_G - bool - default n - -config STM32_FLASH_CONFIG_I - bool - default n - config STM32_FLASH_OVERRIDE bool "Override Flash Designator" default n @@ -1196,6 +1087,7 @@ config STM32_STM32L0 bool default n select STM32_ENERGYLITE + select STM32_HAVE_LCD select STM32_HAVE_VREFINT select STM32_HAVE_ADC1_DMA select STM32_HAVE_IP_USART_V1 @@ -1227,16 +1119,20 @@ config STM32_STM32F04X bool default n select STM32_STM32F0 + select STM32_HAVE_HSI48 config STM32_STM32F05X bool default n select STM32_STM32F0 + select STM32_HAVE_DMA2 config STM32_STM32F07X bool default n select STM32_STM32F0 + select STM32_HAVE_HSI48 + select STM32_HAVE_DMA2 config STM32_STM32F09X bool @@ -1428,12 +1324,6 @@ config STM32_STM32G0C1 select STM32_HAVE_CEC select STM32_HAVE_HSI48 -config STM32_VALUELINE - bool - default n - select STM32_HAVE_USART5 - select STM32_HAVE_SPI2 - config STM32_ACCESSLINE bool default n @@ -1456,10 +1346,6 @@ config STM32_USBLINE select STM32_HAVE_SPI2 select STM32_HAVE_USBDEV -config STM32_ENERGYLITE - bool - default n - config ARCH_CHIP_STM32L053XX bool select STM32_STM32L0 @@ -1516,24 +1402,6 @@ config ARCH_CHIP_STM32C092XX select STM32_HAVE_USART4 select STM32_HAVE_FDCAN1 -config STM32_DFU - bool "DFU bootloader" - default n - depends on !STM32_VALUELINE - ---help--- - Configure and position code for use with the STMicro DFU bootloader. Do - not select this option if you will load code using JTAG/SWM. - -config STM32_PROGMEM - bool "Flash PROGMEM support" - default n - depends on ARCH_HAVE_PROGMEM - select MTD - select MTD_PROGMEM - ---help--- - Add progmem support, start block and end block options are provided to - obtain a uniform flash memory mapping. - choice prompt "SysTick clock source" default STM32_SYSTICK_CORECLK @@ -1551,38 +1419,10 @@ menu "STM32 Peripheral Support" # These "hidden" settings determine whether a peripheral option is available # for the selected MCU -config STM32_HAVE_AES - bool - default n - config STM32_HAVE_VREFINT bool default n -config STM32_HAVE_CCM - bool - default n - -config STM32_HAVE_HSI48 - bool - default n - -config STM32_HAVE_LCD - bool - default n - -config STM32_HAVE_USBDEV - bool - default n - -config STM32_HAVE_FSMC - bool - default n - -config STM32_HAVE_USART3 - bool - default n - config STM32_HAVE_USART4 bool default n @@ -1591,10 +1431,6 @@ config STM32_HAVE_USART5 bool default n -config STM32_HAVE_USART6 - bool - default n - config STM32_HAVE_USART7 bool default n @@ -1603,62 +1439,10 @@ config STM32_HAVE_USART8 bool default n -config STM32_HAVE_LPUART1 - bool - default n - config STM32_HAVE_LPUART2 bool default n -config STM32_HAVE_TIM1 - bool - default n - -config STM32_HAVE_TIM2 - bool - default n - -config STM32_HAVE_TIM3 - bool - default n - -config STM32_HAVE_TIM4 - bool - default n - -config STM32_HAVE_TIM6 - bool - default n - -config STM32_HAVE_TIM7 - bool - default n - -config STM32_HAVE_TIM14 - bool - default n - -config STM32_HAVE_TIM15 - bool - default n - -config STM32_HAVE_TIM16 - bool - default n - -config STM32_HAVE_TIM17 - bool - default n - -config STM32_HAVE_TSC - bool - default n - -config STM32_HAVE_ADC1_DMA - bool - default n - config STM32_HAVE_ADC_OVERSAMPLE bool default STM32_STM32L0 || STM32_STM32G0 || STM32_STM32C0 @@ -1667,94 +1451,10 @@ config STM32_HAVE_CEC bool default n -config STM32_HAVE_CAN1 - bool - default n - -config STM32_HAVE_COMP1 - bool - default n - -config STM32_HAVE_COMP2 - bool - default n - -config STM32_HAVE_COMP3 - bool - default n - -config STM32_HAVE_DAC1 - bool - default n - -config STM32_HAVE_DMAMUX - bool - default n - -config STM32_HAVE_DMA2 - bool - default n - -config STM32_HAVE_RNG - bool - default n - -config STM32_HAVE_CRS - bool - default n - -config STM32_HAVE_I2C2 - bool - default n - -config STM32_HAVE_I2C3 - bool - default n - -config STM32_HAVE_SPI2 - bool - default n - -config STM32_HAVE_SPI3 - bool - default n - -config STM32_HAVE_SAIPLL - bool - default n - config STM32_HAVE_SDIO bool default n -config STM32_HAVE_I2SPLL - bool - default n - -config STM32_HAVE_OPAMP1 - bool - default n - -config STM32_HAVE_OPAMP2 - bool - default n - -config STM32_HAVE_OPAMP3 - bool - default n - -config STM32_HAVE_OPAMP4 - bool - default n - -config STM32_HAVE_FDCAN1 - bool - default n - -config STM32_HAVE_FDCAN2 - bool - default n - config STM32_HAVE_I2S2 bool default n @@ -1787,231 +1487,11 @@ config STM32_HAVE_IP_EXTI_V2 # These are the peripheral selections proper -config STM32_ADC1 - bool "ADC1" - default n - select STM32_ADC - -config STM32_COMP1 - bool "COMP1" - default n - depends on STM32_HAVE_COMP1 - -config STM32_COMP2 - bool "COMP2" - default n - depends on STM32_HAVE_COMP2 - -config STM32_BKP - bool "BKP" - default n - -config STM32_BKPSRAM - bool "Enable BKP RAM Domain" - default n - -config STM32_CAN1 - bool "CAN1" - default n - select CAN - select STM32_CAN - depends on STM32_HAVE_CAN1 - -config STM32_AES - bool "128-bit AES" - default n - depends on STM32_HAVE_AES - select CRYPTO_AES192_DISABLE if CRYPTO_ALGTEST - select CRYPTO_AES256_DISABLE if CRYPTO_ALGTEST - config STM32_VREFINT bool "Enable VREFINT" default n depends on STM32_HAVE_VREFINT -config STM32_CEC - bool "CEC" - default n - depends on STM32_HAVE_CEC - -config STM32_CRC - bool "CRC" - default n - -config STM32_CRYP - bool "CRYP" - default n - depends on STM32_HAVE_HASH - -config STM32_DMA1 - bool "DMA1" - default n - select ARCH_DMA - select STM32_DMA - -config STM32_DMA2 - bool "DMA2" - default n - depends on STM32_HAVE_DMA2 - select ARCH_DMA - select STM32_DMA - -config STM32_DAC1 - bool "DAC1" - default n - depends on STM32_HAVE_DAC1 - select STM32_DAC - -config STM32_FDCAN1 - bool "FDCAN1" - default n - depends on STM32_HAVE_FDCAN1 - select STM32_FDCAN - -config STM32_FSMC - bool "FSMC" - default n - depends on STM32_HAVE_FSMC - -config STM32_HASH - bool "HASH" - default n - depends on STM32_HAVE_HASH - -config STM32_I2C1 - bool "I2C1" - default n - select STM32_I2C - -config STM32_I2C2 - bool "I2C2" - default n - depends on STM32_HAVE_I2C2 - select STM32_I2C - -config STM32_I2C3 - bool "I2C3" - default n - depends on STM32_HAVE_I2C3 - select STM32_I2C - -config STM32_PWR - bool "PWR" - default n - -config STM32_RNG - bool "RNG" - default n - depends on STM32_HAVE_RNG - select ARCH_HAVE_RNG - -config STM32_SDIO - bool "SDIO" - default n - depends on STM32_HAVE_SDIO - select ARCH_HAVE_SDIO - select ARCH_HAVE_SDIOWAIT_WRCOMPLETE - select ARCH_HAVE_SDIO_PREFLIGHT - -config STM32_SPI1 - bool "SPI1" - default n - select SPI - select STM32_SPI - -config STM32_SPI2 - bool "SPI2" - default n - depends on STM32_HAVE_SPI2 - select SPI - select STM32_SPI - -config STM32_SPI3 - bool "SPI3" - default n - depends on STM32_HAVE_SPI3 - select SPI - select STM32_SPI - -config STM32_SYSCFG - bool "SYSCFG" - default y - -config STM32_TIM1 - bool "TIM1" - default n - depends on STM32_HAVE_TIM1 - select STM32_TIM - -config STM32_TIM2 - bool "TIM2" - default n - depends on STM32_HAVE_TIM2 - select STM32_TIM - -config STM32_TIM3 - bool "TIM3" - default n - depends on STM32_HAVE_TIM3 - select STM32_TIM - -config STM32_TIM6 - bool "TIM6" - default n - depends on STM32_HAVE_TIM6 - select STM32_TIM - -config STM32_TIM7 - bool "TIM7" - default n - depends on STM32_HAVE_TIM7 - select STM32_TIM - -config STM32_TIM14 - bool "TIM14" - default n - depends on STM32_HAVE_TIM14 - select STM32_TIM - -config STM32_TIM15 - bool "TIM15" - default n - depends on STM32_HAVE_TIM15 - select STM32_TIM - -config STM32_TIM16 - bool "TIM16" - default n - depends on STM32_HAVE_TIM16 - select STM32_TIM - -config STM32_TIM17 - bool "TIM17" - default n - depends on STM32_HAVE_TIM17 - select STM32_TIM - -config STM32_TSC - bool "TSC" - default n - depends on STM32_HAVE_TSC - -config STM32_USART1 - bool "USART1" - default n - select STM32_USART - -config STM32_USART2 - bool "USART2" - default n - select STM32_USART - -config STM32_USART3 - bool "USART3" - default n - depends on STM32_HAVE_USART3 - select STM32_USART - config STM32_USART4 bool "USART4" default n @@ -2024,12 +1504,6 @@ config STM32_USART5 depends on STM32_HAVE_USART5 select STM32_USART -config STM32_USART6 - bool "USART6" - default n - depends on STM32_HAVE_USART6 - select STM32_USART - config STM32_USART7 bool "USART7" default n @@ -2042,1558 +1516,11 @@ config STM32_USART8 depends on STM32_HAVE_USART8 select STM32_USART -config STM32_USB - bool "USB Device" - default n - depends on STM32_HAVE_USBDEV - select USBDEV - -config STM32_LCD - bool "Segment LCD" - default n - depends on STM32_HAVE_LCD - select USBDEV - -config STM32_IWDG - bool "IWDG" - default n - select WATCHDOG - -config STM32_WWDG - bool "WWDG" - default n - select WATCHDOG - endmenu # STM32 Peripheral Support -config STM32_COMP - bool - default n - -config STM32_ADC - bool - default n - -config STM32_DAC - bool - default n - -config STM32_DMA - bool - default n - -config STM32_SPI - bool - -config STM32_SPI_DMA - bool - default n - -config STM32_I2C - bool - default n - -config STM32_CAN - bool - default n - -config STM32_PWM - bool - default n - -config STM32_USART - bool - default n - -config STM32_TIM - bool - default n - -config STM32_FDCAN - bool - default n - -config STM32_SERIALDRIVER - bool - default n - -config STM32_1WIREDRIVER - bool - default n - -menu "Timer Configuration" - -config STM32_TIM1_PULSECOUNT - bool "TIM1 pulse count" - default n - depends on STM32_TIM1 - select ARCH_HAVE_PULSECOUNT - select PULSECOUNT - ---help--- - Reserve timer 1 for use by the pulse count driver. - - Timer devices may be used for different purposes. If STM32_TIM1 - is defined then this option may also be defined to indicate that TIM1 is - intended to generate a fixed number of output pulses. - -config STM32_TIM1_PWM - bool "TIM1 PWM" - default n - depends on STM32_TIM1 && !STM32_TIM1_PULSECOUNT - select STM32_PWM - ---help--- - Reserve timer 1 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If - STM32_TIM1 is defined then THIS option may also be defined to - indicate that the timer is intended to be used for pulsed output modulation. - - Valid channel modes: - - 0 -> PWM Mode 1 - 1 -> PWM Mode 2 - 2 -> Combined PWM mode 1 - 3 -> Combined PWM mode 2 - 4 -> Asymmetric PWM mode 1 - 5 -> Asymmetric PWM mode 2 - -if STM32_TIM1_PWM - -config STM32_TIM1_MODE - int "TIM1 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode: - - 0 -> Upcounting mode - 1 -> Downcounting mode - 2 -> Center-aligned mode 1 - 3 -> Center-aligned mode 2 - 4 -> Center-aligned mode 3 - -if STM32_PWM_MULTICHAN - -config STM32_TIM1_CHANNEL1 - bool "TIM1 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32_TIM1_CHANNEL1 - -config STM32_TIM1_CH1MODE - int "TIM1 Channel 1 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. See STM32_TIM1_PWM description for available modes. - -config STM32_TIM1_CH1OUT - bool "TIM1 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32_TIM1_CH1NOUT - bool "TIM1 Channel 1 Complementary Output" - default n - depends on STM32_TIM1_CH1OUT - ---help--- - Enables channel 1 complementary output. - -endif # STM32_TIM1_CHANNEL1 - -config STM32_TIM1_CHANNEL2 - bool "TIM1 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32_TIM1_CHANNEL2 - -config STM32_TIM1_CH2MODE - int "TIM1 Channel 2 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. See STM32_TIM1_PWM description for available modes. - -config STM32_TIM1_CH2OUT - bool "TIM1 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -config STM32_TIM1_CH2NOUT - bool "TIM1 Channel 2 Complementary Output" - default n - depends on STM32_TIM1_CH2OUT - ---help--- - Enables channel 2 complementary output. - -endif # STM32_TIM1_CHANNEL2 - -config STM32_TIM1_CHANNEL3 - bool "TIM1 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32_TIM1_CHANNEL3 - -config STM32_TIM1_CH3MODE - int "TIM1 Channel 3 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. See STM32_TIM1_PWM description for available modes. - -config STM32_TIM1_CH3OUT - bool "TIM1 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -config STM32_TIM1_CH3NOUT - bool "TIM1 Channel 3 Complementary Output" - default n - depends on STM32_TIM1_CH3OUT - ---help--- - Enables channel 3 complementary output. - -endif # STM32_TIM1_CHANNEL3 - -config STM32_TIM1_CHANNEL4 - bool "TIM1 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32_TIM1_CHANNEL4 - -config STM32_TIM1_CH4MODE - int "TIM1 Channel 4 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. See STM32_TIM1_PWM description for available modes. - -config STM32_TIM1_CH4OUT - bool "TIM1 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32_TIM1_CHANNEL4 - -endif # STM32_PWM_MULTICHAN - -if !STM32_PWM_MULTICHAN - -config STM32_TIM1_CHANNEL - int "TIM1 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM1 is enabled for output usage, you also need specifies the timer output - channel {1,..,4} - -config STM32_TIM1_CHMODE - int "TIM1 Channel Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. See STM32_TIM1_PWM description for available modes. - -endif # !STM32_PWM_MULTICHAN - -endif # STM32_TIM1_PWM - -if STM32_TIM1_PULSECOUNT - -config STM32_TIM1_PULSECOUNT_CHANNEL - int "TIM1 pulse count channel" - default 1 - range 1 4 - ---help--- - Specifies the timer channel {1,..,4}. - -endif # STM32_TIM1_PULSECOUNT - -config STM32_TIM1_QE - bool "TIM1 Quadrature Encoder" - default n - depends on STM32_TIM1 - ---help--- - Reserve TIM1 for use by Quadrature Encoder. - -config STM32_TIM2_PWM - bool "TIM2 PWM" - default n - depends on STM32_TIM2 - select STM32_PWM - ---help--- - Reserve timer 2 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If - STM32_TIM2 is defined then THIS option may also be defined to - indicate that the timer is intended to be used for pulsed output modulation. - - Valid channel modes: - - 0 -> PWM Mode 1 - 1 -> PWM Mode 2 - 2 -> Combined PWM mode 1 - 3 -> Combined PWM mode 2 - 4 -> Asymmetric PWM mode 1 - 5 -> Asymmetric PWM mode 2 - -if STM32_TIM2_PWM - -config STM32_TIM2_MODE - int "TIM2 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode: - - 0 -> Upcounting mode - 1 -> Downcounting mode - 2 -> Center-aligned mode 1 - 3 -> Center-aligned mode 2 - 4 -> Center-aligned mode 3 - -if STM32_PWM_MULTICHAN - -config STM32_TIM2_CHANNEL1 - bool "TIM2 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32_TIM2_CHANNEL1 - -config STM32_TIM2_CH1MODE - int "TIM2 Channel 1 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. See STM32_TIM2_PWM description for available modes. - -config STM32_TIM2_CH1OUT - bool "TIM2 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32_TIM2_CHANNEL1 - -config STM32_TIM2_CHANNEL2 - bool "TIM2 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32_TIM2_CHANNEL2 - -config STM32_TIM2_CH2MODE - int "TIM2 Channel 2 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. See STM32_TIM2_PWM description for available modes. - -config STM32_TIM2_CH2OUT - bool "TIM2 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32_TIM2_CHANNEL2 - -config STM32_TIM2_CHANNEL3 - bool "TIM2 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32_TIM2_CHANNEL3 - -config STM32_TIM2_CH3MODE - int "TIM2 Channel 3 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. See STM32_TIM2_PWM description for available modes. - -config STM32_TIM2_CH3OUT - bool "TIM2 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32_TIM2_CHANNEL3 - -config STM32_TIM2_CHANNEL4 - bool "TIM2 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32_TIM2_CHANNEL4 - -config STM32_TIM2_CH4MODE - int "TIM2 Channel 4 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. See STM32_TIM2_PWM description for available modes. - -config STM32_TIM2_CH4OUT - bool "TIM2 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32_TIM2_CHANNEL4 - -endif # STM32_PWM_MULTICHAN - -if !STM32_PWM_MULTICHAN - -config STM32_TIM2_CHANNEL - int "TIM2 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM2 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -config STM32_TIM2_CHMODE - int "TIM2 Channel Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. See STM32_TIM2_PWM description for available modes. - -endif # !STM32_PWM_MULTICHAN - -endif # STM32_TIM2_PWM - -config STM32_TIM2_QE - bool "TIM2 Quadrature Encoder" - default n - depends on STM32_TIM2 - ---help--- - Reserve TIM2 for use by Quadrature Encoder. - -config STM32_TIM3_PWM - bool "TIM3 PWM" - default n - depends on STM32_TIM3 - select STM32_PWM - ---help--- - Reserve timer 3 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If - STM32_TIM3 is defined then THIS option may also be defined to - indicate that the timer is intended to be used for pulsed output modulation. - - Valid channel modes: - - 0 -> PWM Mode 1 - 1 -> PWM Mode 2 - 2 -> Combined PWM mode 1 - 3 -> Combined PWM mode 2 - 4 -> Asymmetric PWM mode 1 - 5 -> Asymmetric PWM mode 2 - -if STM32_TIM3_PWM - -config STM32_TIM3_MODE - int "TIM3 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode: - - 0 -> Upcounting mode - 1 -> Downcounting mode - 2 -> Center-aligned mode 1 - 3 -> Center-aligned mode 2 - 4 -> Center-aligned mode 3 - -if STM32_PWM_MULTICHAN - -config STM32_TIM3_CHANNEL1 - bool "TIM3 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32_TIM3_CHANNEL1 - -config STM32_TIM3_CH1MODE - int "TIM3 Channel 1 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. See STM32_TIM3_PWM description for available modes. - -config STM32_TIM3_CH1OUT - bool "TIM3 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32_TIM3_CHANNEL1 - -config STM32_TIM3_CHANNEL2 - bool "TIM3 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32_TIM3_CHANNEL2 - -config STM32_TIM3_CH2MODE - int "TIM3 Channel 2 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. See STM32_TIM3_PWM description for available modes. - -config STM32_TIM3_CH2OUT - bool "TIM3 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32_TIM3_CHANNEL2 - -config STM32_TIM3_CHANNEL3 - bool "TIM3 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32_TIM3_CHANNEL3 - -config STM32_TIM3_CH3MODE - int "TIM3 Channel 3 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. See STM32_TIM3_PWM description for available modes. - -config STM32_TIM3_CH3OUT - bool "TIM3 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32_TIM3_CHANNEL3 - -config STM32_TIM3_CHANNEL4 - bool "TIM3 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32_TIM3_CHANNEL4 - -config STM32_TIM3_CH4MODE - int "TIM3 Channel 4 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. See STM32_TIM3_PWM description for available modes. - -config STM32_TIM3_CH4OUT - bool "TIM3 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32_TIM3_CHANNEL4 - -endif # STM32_PWM_MULTICHAN - -if !STM32_PWM_MULTICHAN - -config STM32_TIM3_CHANNEL - int "TIM3 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM3 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -config STM32_TIM3_CHMODE - int "TIM3 Channel Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. See STM32_TIM3_PWM description for available modes. - -endif # !STM32_PWM_MULTICHAN - -endif # STM32_TIM3_PWM - -config STM32_TIM3_QE - bool "TIM3 Quadrature Encoder" - default n - depends on STM32_TIM3 - ---help--- - Reserve TIM3 for use by Quadrature Encoder. - -config STM32_TIM4_QE - bool "TIM3 Quadrature Encoder" - default n - depends on STM32_TIM4 - ---help--- - Reserve TIM4 for use by Quadrature Encoder. - -menu "STM32F0L0G0 QEncoder Driver" - depends on SENSORS_QENCODER - depends on STM32_TIM1 || STM32_TIM2 || STM32_TIM3 || STM32_TIM4 - -config STM32_TIM1_QEPSC - int "TIM1 QE pulse prescaler" - default 1 - depends on STM32_TIM1_QE - ---help--- - This prescaler divides the number of recorded encoder pulses, - limiting the count rate at the expense of resolution. - -config STM32_TIM2_QEPSC - int "TIM2 QE pulse prescaler" - default 1 - depends on STM32_TIM2_QE - ---help--- - This prescaler divides the number of recorded encoder pulses, - limiting the count rate at the expense of resolution. - -config STM32_TIM3_QEPSC - int "TIM3 QE pulse prescaler" - default 1 - depends on STM32_TIM3_QE - ---help--- - This prescaler divides the number of recorded encoder pulses, - limiting the count rate at the expense of resolution. - -config STM32_TIM4_QEPSC - int "TIM3 QE pulse prescaler" - default 1 - depends on STM32_TIM4_QE - ---help--- - This prescaler divides the number of recorded encoder pulses, - limiting the count rate at the expense of resolution. - -config STM32_QENCODER_DISABLE_EXTEND16BTIMERS - bool "Disable QEncoder timers extension from 16-bit to 32-bit" - default n - ---help--- - Disable the extension of 16-bit timers to 32-bit via interrupt-based - overflow tracking. When enabled, timers will use their native hardware - counter width (16-bit or 32-bit). This reduces interrupt overhead but - limits the position range for 16-bit timers. - -config STM32_QENCODER_INDEX_PIN - bool "Enable QEncoder timers support for index pin" - default n - ---help--- - Enable support for quadrature encoder index pin. The index pin can be - used to reset the encoder position to a known value when the index - pulse is detected. - -config STM32_QENCODER_FILTER - bool "Enable filtering on STM32F0L0G0 QEncoder input" - default y - ---help--- - Enable input filtering on quadrature encoder channels to reduce noise. - -endmenu # STM32F0L0G0 QEncoder Driver - -config STM32_TIM14_PWM - bool "TIM14 PWM" - default n - depends on STM32_TIM14 - select STM32_PWM - ---help--- - Reserve timer 14 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32_TIM14 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32_TIM14_PWM - -if STM32_PWM_MULTICHAN - -config STM32_TIM14_CHANNEL1 - bool "TIM14 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32_TIM14_CHANNEL1 - -config STM32_TIM14_CH1MODE - int "TIM14 Channel 1 Mode" - default 0 - range 0 1 - ---help--- - Specifies the channel mode. - -config STM32_TIM14_CH1OUT - bool "TIM14 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32_TIM14_CHANNEL1 - -endif # STM32_PWM_MULTICHAN - -if !STM32_PWM_MULTICHAN - -config STM32_TIM14_CHANNEL - int "TIM14 PWM Output Channel" - default 1 - range 1 1 - ---help--- - If TIM14 is enabled for PWM usage, you also need specifies the timer output - channel {1} - -config STM32_TIM14_CHMODE - int "TIM14 Channel Mode" - default 0 - range 0 1 - ---help--- - Specifies the channel mode. - -endif # !STM32_PWM_MULTICHAN - -endif # STM32_TIM14_PWM - -config STM32_TIM15_PWM - bool "TIM15 PWM" - default n - depends on STM32_TIM15 - select STM32_PWM - ---help--- - Reserve timer 15 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32_TIM15 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32_TIM15_PWM - -if STM32_PWM_MULTICHAN - -config STM32_TIM15_CHANNEL1 - bool "TIM15 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32_TIM15_CHANNEL1 - -config STM32_TIM15_CH1MODE - int "TIM15 Channel 1 Mode" - default 0 - range 0 3 - ---help--- - Specifies the channel mode. - -config STM32_TIM15_CH1OUT - bool "TIM15 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32_TIM15_CH1NOUT - bool "TIM15 Channel 1 Complementary Output" - default n - depends on STM32_TIM15_CH1OUT - ---help--- - Enables channel 1 complementary output. - -endif # STM32_TIM15_CHANNEL1 - -config STM32_TIM15_CHANNEL2 - bool "TIM15 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32_TIM15_CHANNEL2 - -config STM32_TIM15_CH2MODE - int "TIM15 Channel 2 Mode" - default 0 - range 0 3 - ---help--- - Specifies the channel mode. - -config STM32_TIM15_CH2OUT - bool "TIM15 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32_TIM15_CHANNEL2 - -endif # STM32_PWM_MULTICHAN - -if !STM32_PWM_MULTICHAN - -config STM32_TIM15_CHANNEL - int "TIM15 PWM Output Channel" - default 1 - range 1 2 - ---help--- - If TIM15 is enabled for PWM usage, you also need specifies the timer output - channel {1,2} - -config STM32_TIM15_CHMODE - int "TIM15 Channel Mode" - default 0 - range 0 3 - ---help--- - Specifies the channel mode. - -endif # !STM32_PWM_MULTICHAN - -endif # STM32_TIM15_PWM - -config STM32_TIM16_PWM - bool "TIM16 PWM" - default n - depends on STM32_TIM16 - select STM32_PWM - ---help--- - Reserve timer 16 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32_TIM16 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32_TIM16_PWM - -if STM32_PWM_MULTICHAN - -config STM32_TIM16_CHANNEL1 - bool "TIM16 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32_TIM16_CHANNEL1 - -config STM32_TIM16_CH1MODE - int "TIM16 Channel 1 Mode" - default 0 - range 0 1 - ---help--- - Specifies the channel mode. - -config STM32_TIM16_CH1OUT - bool "TIM16 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32_TIM16_CH1NOUT - bool "TIM16 Channel 1 Complementary Output" - default n - depends on STM32_TIM16_CH1OUT - ---help--- - Enables channel 1 complementary output. - -endif # STM32_TIM16_CHANNEL1 - -endif # STM32_PWM_MULTICHAN - -if !STM32_PWM_MULTICHAN - -config STM32_TIM16_CHANNEL - int "TIM16 PWM Output Channel" - default 1 - range 1 1 - ---help--- - If TIM16 is enabled for PWM usage, you also need specifies the timer output - channel {1} - -config STM32_TIM16_CHMODE - int "TIM16 Channel Mode" - default 0 - range 0 1 - ---help--- - Specifies the channel mode. - -endif # !STM32_PWM_MULTICHAN - -endif # STM32_TIM16_PWM - -config STM32_TIM17_PWM - bool "TIM17 PWM" - default n - depends on STM32_TIM17 - select STM32_PWM - ---help--- - Reserve timer 17 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32_TIM17 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32_TIM17_PWM - -if STM32_PWM_MULTICHAN - -config STM32_TIM17_CHANNEL1 - bool "TIM17 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32_TIM17_CHANNEL1 - -config STM32_TIM17_CH1MODE - int "TIM17 Channel 1 Mode" - default 0 - range 0 1 - ---help--- - Specifies the channel mode. - -config STM32_TIM17_CH1OUT - bool "TIM17 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32_TIM17_CH1NOUT - bool "TIM17 Channel 1 Complementary Output" - default n - depends on STM32_TIM17_CH1OUT - ---help--- - Enables channel 1 complementary output. - -endif # STM32_TIM17_CHANNEL1 - -endif # STM32_PWM_MULTICHAN - -if !STM32_PWM_MULTICHAN - -config STM32_TIM17_CHANNEL - int "TIM17 PWM Output Channel" - default 1 - range 1 1 - ---help--- - If TIM17 is enabled for PWM usage, you also need specifies the timer output - channel {1} - -config STM32_TIM17_CHMODE - int "TIM17 Channel Mode" - default 0 - range 0 1 - ---help--- - Specifies the channel mode. - -endif # !STM32_PWM_MULTICHAN - -endif # STM32_TIM17_PWM - -config STM32_PWM_MULTICHAN - bool "PWM Multiple Output Channels" - default n - depends on STM32_PWM - ---help--- - Specifies that the PWM driver supports multiple output channels per timer. - -config STM32_TIM1_ADC - bool "TIM1 ADC" - default n - depends on STM32_TIM1 && STM32_ADC - ---help--- - Reserve timer 1 for use by ADC - -config STM32_TIM2_ADC - bool "TIM2 ADC" - default n - depends on STM32_TIM2 && STM32_ADC - ---help--- - Reserve timer 1 for use by ADC - -config STM32_TIM3_ADC - bool "TIM3 ADC" - default n - depends on STM32_TIM3 && STM32_ADC - ---help--- - Reserve timer 1 for use by ADC - -config STM32_TIM15_ADC - bool "TIM15 ADC" - default n - depends on STM32_TIM15 && STM32_ADC - ---help--- - Reserve timer 1 for use by ADC - -config STM32_HAVE_ADC1_TIMER - bool - -config STM32_ADC1_SAMPLE_FREQUENCY - int "ADC1 Sampling Frequency" - default 100 - depends on STM32_HAVE_ADC1_TIMER - ---help--- - ADC1 sampling frequency. Default: 100Hz - -config STM32_ADC1_TIMTRIG - int "ADC1 Timer Trigger" - default 0 - range 0 5 - depends on STM32_HAVE_ADC1_TIMER - ---help--- - Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO 5:TRGO2. - This option must match with the MCU's supported EXTSEL. - -endmenu # Timer Configuration - -menu "FDCAN driver configuration" - depends on STM32_FDCAN - -config STM32_FDCAN_REGDEBUG - bool "CAN Register level debug" - depends on DEBUG_CAN_INFO - default n - ---help--- - Output detailed register-level CAN device debug information. - Requires also CONFIG_DEBUG_CAN_INFO. - -config STM32_FDCAN_QUEUE_MODE - bool "FDCAN QUEUE mode (vs FIFO mode)" - default n - -menu "FDCAN1 device driver options" - depends on STM32_FDCAN1 - -config STM32_FDCAN1_LOOPBACK - bool "Enable FDCAN1 loopback mode" - default n - ---help--- - Enable the FDCAN1 local loopback mode for testing purposes. - -comment "Nominal Bit Timing" - -config STM32_FDCAN1_BITRATE - int "FDCAN bitrate" - default 500000 - range 0 1000000 - ---help--- - FDCAN1 bitrate in bits per second. Required if STM32_FDCAN1 is defined. - -config STM32_FDCAN1_NTSEG1 - int "FDCAN1 NTSEG1 (PropSeg + PhaseSeg1)" - default 6 - range 1 256 - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -config STM32_FDCAN1_NTSEG2 - int "FDCAN1 NTSEG2 (PhaseSeg2)" - default 7 - range 1 128 - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -config STM32_FDCAN1_NSJW - int "FDCAN1 synchronization jump width" - default 1 - range 1 128 - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -comment "Data Bit Timing" - depends on CAN_FD && STM32_FDCAN1_FD_BRS - -config STM32_FDCAN1_DBITRATE - int "FDCAN1 data bitrate" - default 2000000 - depends on CAN_FD && STM32_FDCAN1_FD_BRS - ---help--- - FDCAN1 bitrate in bits per second. Required if operating in FD mode with bit rate switching (BRS). - -config STM32_FDCAN1_DTSEG1 - int "FDCAN1 DTSEG1 (PropSeg + PhaseSeg1 of data phase)" - default 4 - range 1 31 - depends on CAN_FD && STM32_FDCAN1_FD_BRS - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -config STM32_FDCAN1_DTSEG2 - int "FDCAN1 DTSEG2 (PhaseSeg2 of data phase)" - default 4 - range 1 15 - depends on CAN_FD && STM32_FDCAN1_FD_BRS - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -config STM32_FDCAN1_DSJW - int "FDCAN1 fast synchronization jump width" - default 2 - range 1 15 - depends on CAN_FD && STM32_FDCAN1_FD_BRS - ---help--- - The duration of a synchronization jump is Tcan_clk x DSJW. - -endmenu # FDCAN1 device driver options - -endmenu # "FDCAN driver configuration" - -menu "U[S]ART Configuration" - depends on STM32_USART - -comment "U[S]ART Device Configuration" - -if STM32_USART1_SERIALDRIVER - -config USART1_RXFIFO_THRES - int "USART1 Rx FIFO Threshold" - default 3 - range 0 5 - depends on STM32_HAVE_IP_USART_V2 - ---help--- - Select the Rx FIFO threshold: - - 0 -> 1/8 full - 1 -> 1/4 full - 2 -> 1/2 full - 3 -> 3/4 full - 4 -> 7/8 full - 5 -> Full - - Higher values mean lower interrupt rates and better CPU performance. - Lower values may be needed at high BAUD rates to prevent Rx data - overrun errors. - -config USART1_RS485 - bool "RS-485 on USART1" - default n - ---help--- - Enable RS-485 interface on USART1. Your board config will have to - provide GPIO_USART1_RS485_DIR pin definition. - -config USART1_RS485_DIR_POLARITY - int "USART1 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART1_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART1. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -endif # STM32_USART1_SERIALDRIVER - -if STM32_USART2_SERIALDRIVER - -config USART2_RXFIFO_THRES - int "USART2 Rx FIFO Threshold" - default 3 - range 0 5 - depends on STM32_HAVE_IP_USART_V2 - ---help--- - Select the Rx FIFO threshold: - - 0 -> 1/8 full - 1 -> 1/4 full - 2 -> 1/2 full - 3 -> 3/4 full - 4 -> 7/8 full - 5 -> Full - - Higher values mean lower interrupt rates and better CPU performance. - Lower values may be needed at high BAUD rates to prevent Rx data - overrun errors. - -config USART2_RS485 - bool "RS-485 on USART2" - default n - ---help--- - Enable RS-485 interface on USART2. Your board config will have to - provide GPIO_USART2_RS485_DIR pin definition. - -config USART2_RS485_DIR_POLARITY - int "USART2 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART2_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART2. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -endif # STM32_USART2_SERIALDRIVER - -if STM32_USART3_SERIALDRIVER - -config USART3_RS485 - bool "RS-485 on USART3" - default n - ---help--- - Enable RS-485 interface on USART3. Your board config will have to - provide GPIO_USART3_RS485_DIR pin definition. - -config USART3_RS485_DIR_POLARITY - int "USART3 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART3_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART3. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -endif # STM32_USART3_SERIALDRIVER - -choice - prompt "USART4 Driver Configuration" - default STM32_USART4_SERIALDRIVER - depends on STM32_USART4 - -config STM32_USART4_SERIALDRIVER - bool "Standard serial driver" - select USART4_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - select STM32_SERIALDRIVER - -config STM32_USART4_1WIREDRIVER - bool "1-Wire driver" - select STM32_1WIREDRIVER - -endchoice # USART4 Driver Configuration - -if STM32_USART4_SERIALDRIVER - -config USART4_RS485 - bool "RS-485 on USART4" - default n - ---help--- - Enable RS-485 interface on USART4. Your board config will have to - provide GPIO_USART4_RS485_DIR pin definition. - -config USART4_RS485_DIR_POLARITY - int "USART4 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART4_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART4. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -endif # STM32_USART4_SERIALDRIVER - -choice - prompt "USART5 Driver Configuration" - default STM32_USART5_SERIALDRIVER - depends on STM32_USART5 - -config STM32_USART5_SERIALDRIVER - bool "Standard serial driver" - select USART5_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - select STM32_SERIALDRIVER - -config STM32_USART5_1WIREDRIVER - bool "1-Wire driver" - select STM32_1WIREDRIVER - -endchoice # USART5 Driver Configuration - -if STM32_USART5_SERIALDRIVER - -config USART5_RS485 - bool "RS-485 on USART5" - default n - ---help--- - Enable RS-485 interface on USART5. Your board config will have to - provide GPIO_USART5_RS485_DIR pin definition. - -config USART5_RS485_DIR_POLARITY - int "USART5 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART5_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART5. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -endif # STM32_USART5_SERIALDRIVER - -if STM32_USART6_SERIALDRIVER - -config USART6_RS485 - bool "RS-485 on USART6" - default n - ---help--- - Enable RS-485 interface on USART6. Your board config will have to - provide GPIO_USART6_RS485_DIR pin definition. - -config USART6_RS485_DIR_POLARITY - int "USART6 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART6_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART6. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -endif # STM32_USART6_SERIALDRIVER - -choice - prompt "USART7 Driver Configuration" - default STM32_USART7_SERIALDRIVER - depends on STM32_USART7 - -config STM32_USART7_SERIALDRIVER - bool "Standard serial driver" - select USART7_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - select STM32_SERIALDRIVER - -config STM32_USART7_1WIREDRIVER - bool "1-Wire driver" - select STM32_1WIREDRIVER - -endchoice # USART7 Driver Configuration - -if STM32_USART7_SERIALDRIVER - -config USART7_RS485 - bool "RS-485 on USART7" - default n - ---help--- - Enable RS-485 interface on USART7. Your board config will have to - provide GPIO_USART7_RS485_DIR pin definition. - -config USART7_RS485_DIR_POLARITY - int "USART7 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART7_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART7. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -endif # STM32_USART7_SERIALDRIVER - -choice - prompt "USART8 Driver Configuration" - default STM32_USART8_SERIALDRIVER - depends on STM32_USART8 - -config STM32_USART8_SERIALDRIVER - bool "Standard serial driver" - select USART8_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - select STM32_SERIALDRIVER - -config STM32_USART8_1WIREDRIVER - bool "1-Wire driver" - select STM32_1WIREDRIVER - -endchoice # USART8 Driver Configuration - -if STM32_USART8_SERIALDRIVER - -config USART8_RS485 - bool "RS-485 on USART8" - default n - ---help--- - Enable RS-485 interface on USART8. Your board config will have to - provide GPIO_USART8_RS485_DIR pin definition. - -config USART8_RS485_DIR_POLARITY - int "USART8 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART8_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART8. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -endif # STM32_USART8_SERIALDRIVER - -menu "Serial Driver Configuration" - depends on STM32_SERIALDRIVER - -config STM32_SERIAL_DISABLE_REORDERING - bool "Disable reordering of ttySx devices." - default n - ---help--- - NuttX per default reorders the serial ports (/dev/ttySx) so that the - console is always on /dev/ttyS0. If more than one UART is in use this - can, however, have the side-effect that all port mappings - (hardware USART1 -> /dev/ttyS0) change if the console is moved to another - UART. This is in particular relevant if a project uses the USB console - in some boards and a serial console in other boards, but does not - want the side effect of having all serial port names change when just - the console is moved from serial to USB. - -config STM32_USART_SINGLEWIRE - bool "Single Wire Support" - default n - depends on STM32_USART - ---help--- - Enable single wire UART support. The option enables support for the - TIOCSSINGLEWIRE ioctl in the STM32F0 serial driver. - -endmenu # Serial Driver Configuration - -if PM - -config STM32_PM_SERIAL_ACTIVITY - int "PM serial activity" - default 10 - ---help--- - PM activity reported to power management logic on every serial - interrupt. - -endif # PM - -endmenu # U[S]ART Configuration - menu "ADC Configuration" depends on STM32_ADC -config STM32_ADC1_RESOLUTION - int "ADC1 resolution" - depends on STM32_ADC1 - default 0 - range 0 3 - ---help--- - ADC1 resolution. 0 - 12 bit, 1 - 10 bit, 2 - 8 bit, 3 - 6 bit - -config STM32_ADC_MAX_SAMPLES - int "The maximum number of channels that can be sampled" - default 16 if STM32_ADC1_DMA - default 1 if !STM32_ADC1_DMA - ---help--- - The maximum number of samples which can be handled without - overrun depends on various factors. This is the user's - responsibility to correctly select this value. - Since the interface to update the sampling time is available - for all supported devices, the user can change the default - values in the board initialization logic and avoid ADC overrun. - -config STM32_ADC_NO_STARTUP_CONV - bool "Do not start conversion when opening ADC device" - default n - ---help--- - Do not start conversion when opening ADC device. - -config STM32_ADC_NOIRQ - bool "Do not use default ADC interrupts" - default n - ---help--- - Do not use default ADC interrupts handlers. - -config STM32_ADC_LL_OPS - bool "ADC low-level operations" - default n - ---help--- - Enable low-level ADC ops. - -config STM32_ADC_CHANGE_SAMPLETIME - bool "ADC sample time configuration" - default n - depends on STM32_ADC_LL_OPS - ---help--- - Enable ADC sample time configuration (SMPRx registers). - -config STM32_ADC1_DMA - bool "ADC1 DMA" - depends on STM32_ADC1 && STM32_HAVE_ADC1_DMA - default n - ---help--- - If DMA is selected, then the ADC may be configured to support - DMA transfer, which is necessary if multiple channels are read - or if very high trigger frequencies are used. - -config STM32_ADC1_DMA_CFG - int "ADC1 DMA configuration" - depends on STM32_ADC1_DMA && !STM32_HAVE_IP_ADC_V1_BASIC - range 0 1 - default 0 - ---help--- - 0 - ADC1 DMA in One Shot Mode, 1 - ADC1 DMA in Circular Mode - -config STM32_ADC_OVERSAMPLE - bool "Enable ADC hardware oversampling support" - depends on STM32_ADC1 && STM32_HAVE_ADC_OVERSAMPLE - default n - ---help--- - Enable the on-chip ADC oversampling/accumulation block (CFGR2.OVSE). - Only STM32G0 and STM32L0 series include this hardware block. - -if STM32_ADC_OVERSAMPLE - -config STM32_ADC_TOVS - bool "Enable triggered oversampling (CFGR2.TOVS)" - default n - ---help--- - If set, oversampling will only occur when a trigger event occurs. - If not set, oversampling occurs continuously (TOVS=0). - -config STM32_ADC_OVSR - int "Oversampling ratio (CFGR2.OVSR)" - default 0 - range 0 7 - ---help--- - Sets the oversampling ratio as 2^(OVSR+1). For example: - 0 -> 2× - 1 -> 4× - 2 -> 8× - ... - 7 -> 256× - -config STM32_ADC_OVSS - int "Oversampling right-shift bits (CFGR2.OVSS)" - default 0 - range 0 8 - ---help--- - Sets how many bits the accumulated result is right-shifted. - Max of 8-bits. - -endif # STM32_ADC_OVERSAMPLE - -config STM32_ADC1_DMA_BATCH - int "ADC1 DMA number of conversions" - depends on STM32_ADC1 && STM32_ADC1_DMA - default 1 - ---help--- - This option allows you to select the number of regular group conversions - that will trigger a DMA callback transerring data to the upper-half driver. - By default, this value is 1, which means that data is transferred after - each group conversion. - -config STM32_ADC1_EXTSEL - bool "ADC1 external trigger for regular group" - depends on STM32_ADC1 && !STM32_HAVE_ADC1_TIMER - default n - ---help--- - Enable EXTSEL for ADC1. - config STM32_ADC1_CONTINUOUS bool "Enable ADC1 Continuous Conversion Mode" default n @@ -3605,99 +1532,3 @@ config STM32_ADC1_CONTINUOUS the same time endmenu # ADC Configuration - -menu "SPI Configuration" - depends on STM32_SPI - -config STM32_SPI_INTERRUPTS - bool "Interrupt driver SPI" - default n - ---help--- - Select to enable interrupt driven SPI support. Non-interrupt-driven, - poll-waiting is recommended if the interrupt rate would be to high in - the interrupt driven case. - -config STM32_SPI1_DMA - bool "SPI1 DMA" - default n - depends on STM32_SPI1 && !STM32_SPI_INTERRUPTS - select STM32_SPI_DMA - ---help--- - Use DMA to improve SPI1 transfer performance. Cannot be used with STM32_SPI_INTERRUPT. - -config STM32_SPI2_DMA - bool "SPI2 DMA" - default n - depends on STM32_SPI2 && !STM32_SPI_INTERRUPTS - select STM32_SPI_DMA - ---help--- - Use DMA to improve SPI2 transfer performance. Cannot be used with STM32_SPI_INTERRUPT. - -config STM32_SPI3_DMA - bool "SPI3 DMA" - default n - depends on STM32_SPI3 && !STM32_SPI_INTERRUPTS - select STM32_SPI_DMA - ---help--- - Use DMA to improve SPI3 transfer performance. Cannot be used with STM32_SPI_INTERRUPT. - -config STM32_SPI1_COMMTYPE - int "SPI1 Operation mode" - default 0 - range 0 3 - depends on STM32_SPI1 - ---help--- - Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3) - -config STM32_SPI2_COMMTYPE - int "SPI2 Operation mode" - default 0 - range 0 3 - depends on STM32_SPI2 - ---help--- - Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3) - -config STM32_SPI3_COMMTYPE - int "SPI3 Operation mode" - default 0 - range 0 3 - depends on STM32_SPI3 - ---help--- - Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3) - -endmenu # SPI Configuration - -menu "I2C Configuration" - depends on STM32_I2C - -config STM32_I2C_DYNTIMEO - bool "Use dynamic timeouts" - default n - depends on STM32_I2C - -config STM32_I2C_DYNTIMEO_USECPERBYTE - int "Timeout Microseconds per Byte" - default 500 - depends on STM32_I2C_DYNTIMEO - -config STM32_I2C_DYNTIMEO_STARTSTOP - int "Timeout for Start/Stop (Milliseconds)" - default 1000 - depends on STM32_I2C_DYNTIMEO - -config STM32_I2CTIMEOSEC - int "Timeout seconds" - default 0 - depends on STM32_I2C - -config STM32_I2CTIMEOMS - int "Timeout Milliseconds" - default 500 - depends on STM32_I2C && !STM32_I2C_DYNTIMEO - -config STM32_I2CTIMEOTICKS - int "Timeout for Done and Stop (ticks)" - default 500 - depends on STM32_I2C && !STM32_I2C_DYNTIMEO - -endmenu #I2C Configuration