From f7684abdd289458f4ec05e11d69c46c9f35bfe0e Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sun, 17 May 2015 08:06:56 -0600 Subject: [PATCH] Rename sam_gclk.h to samd_gclk.h. Add saml_gclk.h --- arch/arm/src/samdl/Make.defs | 6 +- .../samdl/chip/{sam_gclk.h => samd_gclk.h} | 11 +- arch/arm/src/samdl/chip/saml_gclk.h | 194 ++++++++++++++++++ arch/arm/src/samdl/sam_lowputc.c | 4 +- arch/arm/src/samdl/sam_sercom.c | 10 +- arch/arm/src/samdl/sam_spi.c | 4 +- arch/arm/src/samdl/sam_usart.c | 8 +- arch/arm/src/samdl/samd_clockconfig.c | 2 +- configs/samd20-xplained/nsh/setenv.sh | 1 + 9 files changed, 218 insertions(+), 22 deletions(-) rename arch/arm/src/samdl/chip/{sam_gclk.h => samd_gclk.h} (97%) create mode 100644 arch/arm/src/samdl/chip/saml_gclk.h diff --git a/arch/arm/src/samdl/Make.defs b/arch/arm/src/samdl/Make.defs index 962aa1f8588..ed9169a3bd6 100644 --- a/arch/arm/src/samdl/Make.defs +++ b/arch/arm/src/samdl/Make.defs @@ -71,13 +71,11 @@ CHIP_ASRCS = CHIP_CSRCS = sam_idle.c sam_irq.c sam_lowputc.c sam_port.c sam_sercom.c CHIP_CSRCS += sam_serial.c sam_start.c sam_usart.c -ifneq ($(CONFIG_ARCH_FAMILY_SAMD20),y) +ifeq ($(CONFIG_ARCH_FAMILY_SAMD20),y) CHIP_CSRCS += samd_clockconfig.c -else -ifneq ($(CONFIG_ARCH_FAMILY_SAML21),y) +else ifeq ($(CONFIG_ARCH_FAMILY_SAML21),y) CHIP_CSRCS += saml_clockconfig.c endif -endif ifneq ($(CONFIG_SCHED_TICKLESS),y) CHIP_CSRCS += sam_timerisr.c diff --git a/arch/arm/src/samdl/chip/sam_gclk.h b/arch/arm/src/samdl/chip/samd_gclk.h similarity index 97% rename from arch/arm/src/samdl/chip/sam_gclk.h rename to arch/arm/src/samdl/chip/samd_gclk.h index 5b578cc3ba7..bb2e3620212 100644 --- a/arch/arm/src/samdl/chip/sam_gclk.h +++ b/arch/arm/src/samdl/chip/samd_gclk.h @@ -1,5 +1,5 @@ /******************************************************************************************** - * arch/arm/src/samdl/chip/sam_gclk.h + * arch/arm/src/samdl/chip/samd_gclk.h * * Copyright (C) 2014 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -37,8 +37,8 @@ * ********************************************************************************************/ -#ifndef __ARCH_ARM_SRC_SAMDL_CHIP_SAM_GCLK_H -#define __ARCH_ARM_SRC_SAMDL_CHIP_SAM_GCLK_H +#ifndef __ARCH_ARM_SRC_SAMDL_CHIP_SAMD_GCLK_H +#define __ARCH_ARM_SRC_SAMDL_CHIP_SAMD_GCLK_H /******************************************************************************************** * Included Files @@ -48,6 +48,8 @@ #include "chip.h" +#ifdef CONFIG_ARCH_FAMILY_SAMD20 + /******************************************************************************************** * Pre-processor Definitions ********************************************************************************************/ @@ -185,4 +187,5 @@ * Public Functions ********************************************************************************************/ -#endif /* __ARCH_ARM_SRC_SAMDL_CHIP_SAM_GCLK_H */ +#endif /* CONFIG_ARCH_FAMILY_SAMD20 */ +#endif /* __ARCH_ARM_SRC_SAMDL_CHIP_SAMD_GCLK_H */ diff --git a/arch/arm/src/samdl/chip/saml_gclk.h b/arch/arm/src/samdl/chip/saml_gclk.h new file mode 100644 index 00000000000..4e64e7c8bfa --- /dev/null +++ b/arch/arm/src/samdl/chip/saml_gclk.h @@ -0,0 +1,194 @@ +/******************************************************************************************** + * arch/arm/src/samdl/chip/saml_gclk.h + * + * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * References: + * "Atmel SAM L21E / SAM L21G / SAM L21J Smart ARM-Based Microcontroller + * Datasheet", Atmel-42385C-SAML21_Datasheet_Preliminary-03/20/15 + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ********************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAMDL_CHIP_SAML_GCLK_H +#define __ARCH_ARM_SRC_SAMDL_CHIP_SAML_GCLK_H + +/******************************************************************************************** + * Included Files + ********************************************************************************************/ + +#include + +#include "chip.h" + +#ifdef CONFIG_ARCH_FAMILY_SAML21 + +/******************************************************************************************** + * Pre-processor Definitions + ********************************************************************************************/ +/* GCLK register offsets ********************************************************************/ + +#define SAM_GCLK_CTRLA_OFFSET 0x0000 /* Control register */ +#define SAM_GCLK_SYNCHBUSY_OFFSET 0x0004 /* Status register */ + +#define SAM_GCLK_GENCTRL_OFFSET(n) (0x0020 + ((n) << 2) /* General clock generator n */ +#define SAM_GCLK_PCHCTRL_OFFSET(m) (0x0080 + ((m) << 2) /* Peripheral channel control m */ + +/* GCLK register addresses ******************************************************************/ + +#define SAM_GCLK_CTRLA (SAM_GCLK_BASE+SAM_GCLK_CTRLA_OFFSET) +#define SAM_GCLK_SYNCHBUSY (SAM_GCLK_BASE+SAM_GCLK_SYNCHBUSY_OFFSET) + +#define SAM_GCLK_GENCTRL(n) (SAM_GCLK_BASE+SAM_GCLK_GENCTRL_OFFSET(n)) +#define SAM_GCLK_PCHCTRL(m) (SAM_GCLK_BASE+SAM_GCLK_PCHCTRL_OFFSET(m)) + + +/* GCLK register bit definitions ************************************************************/ + +/* Control register */ + +#define GCLK_CTRLA_SWRST (1 << 0) /* Bit 0: Software Reset */ + +/* Status register */ + +#define GCLK_SYNCHBUSY_SWRST (1 << 0) /* Bit 0: SWRST synchronization busy */ +#define GCLK_SYNCHBUSY_GENCTRL0 (1 << 2) /* Bit 2: Generator control 0 busy */ +#define GCLK_SYNCHBUSY_GENCTRL1 (1 << 3) /* Bit 3: Generator control 1 busy */ +#define GCLK_SYNCHBUSY_GENCTRL2 (1 << 4) /* Bit 4: Generator control 2 busy */ +#define GCLK_SYNCHBUSY_GENCTRL3 (1 << 5) /* Bit 5: Generator control 3 busy */ +#define GCLK_SYNCHBUSY_GENCTRL4 (1 << 6) /* Bit 6: Generator control 4 busy */ +#define GCLK_SYNCHBUSY_GENCTRL5 (1 << 7) /* Bit 7: Generator control 5 busy */ +#define GCLK_SYNCHBUSY_GENCTRL6 (1 << 8) /* Bit 8: Generator control 6 busy */ +#define GCLK_SYNCHBUSY_GENCTRL7 (1 << 9) /* Bit 9: Generator control 7 busy */ +#define GCLK_SYNCHBUSY_GENCTRL8 (1 << 10) /* Bit 10: Generator control 8 busy */ + +/* General clock generator n */ + +#define GCLK_GENCTRL_SRC_SHIFT (0) /* Bits 0-4: Generator source selection */ +#define GCLK_GENCTRL_SRC_MASK (31 << GCLK_GENCTRL_SRC_SHIFT) +# define GCLK_GENCTRL_SRC_XOSC (0 << GCLK_GENCTRL_SRC_SHIFT) /* XOSC oscillator inpupt */ +# define GCLK_GENCTRL_SRC_GCLK_IN (1 << GCLK_GENCTRL_SRC_SHIFT) /* Generator input pad */ +# define GCLK_GENCTRL_SRC_GLCK_GEN1 (2 << GCLK_GENCTRL_SRC_SHIFT) /* Generic clock generater 1 output */ +# define GCLK_GENCTRL_SRC_OSCULP32K (3 << GCLK_GENCTRL_SRC_SHIFT) /* OSCULP32K oscillator output */ +# define GCLK_GENCTRL_SRC_OSC32K (4 << GCLK_GENCTRL_SRC_SHIFT) /* OSC32K osccillator output */ +# define GCLK_GENCTRL_SRC_XOSC32K (5 << GCLK_GENCTRL_SRC_SHIFT) /* XOSC32K oscillator output */ +# define GCLK_GENCTRL_SRC_OSC16M (6 << GCLK_GENCTRL_SRC_SHIFT) /* OSC16M oscillator output */ +# define GCLK_GENCTRL_SRC_DFLL48M (7 << GCLK_GENCTRL_SRC_SHIFT) /* DFLL48M output */ +# define GCLK_GENCTRL_SRC_DPLL96M (8 << GCLK_GENCTRL_SRC_SHIFT) /* DPLL96M output */ +#define GCLK_GENCTRL_GENEN (1 << 8) /* Bit 8: Generator enable */ +#define GCLK_GENCTRL_IDC (1 << 9) /* Bit 9: Improve duty cycle */ +#define GCLK_GENCTRL_OOV (1 << 10) /* Bit 10: Clock output selection */ +#define GCLK_GENCTRL_OE (1 << 11) /* Bit 11: Clock output enable */ +#define GCLK_GENCTRL_DIVSEL (1 << 12) /* Bit 12: Clock source divider */ +#define GCLK_GENCTRL_RUNSTDBY (1 << 13) /* Bit 13: Run in standby */ +#define GCLK_GENCTRL_DIV_SHIFT (16) /* Bits 16-31: Generator 0,2-8 Division factor */ +#define GCLK_GENCTRL_DIV_MASK (0xff << GCLK_GENCTRL_DIV_SHIFT) +# define GCLK_GENCTRL_DIV(n) ((uint32_t)(n) << GCLK_GENCTRL_DIV_SHIFT) +#define GCLK_GENCTRL1_DIV_SHIFT (16) /* Bits 16-23: Generator 1 Division factor **/ +#define GCLK_GENCTRL1_DIV_MASK (0xffff << GCLK_GENCTRL1_DIV_SHIFT) +# define GCLK_GENCTRL1_DIV(n) ((uint32_t)(n) << GCLK_GENCTRL1_DIV_SHIFT) + +/* Peripheral channel control m */ + +#define GCLK_PCHCTRL_GEN_SHIFT (0) /* Bits 0-3: Generator selection */ +#define GCLK_PCHCTRL_GEN_MASK (15 << GCLK_PCHCTRL_GEN_SHIFT) +# define GCLK_PCHCTRL_GEN(n) ((uint32_t)(n) << GCLK_PCHCTRL_GEN_SHIFT) +# define GCLK_PCHCTRL_GEN0 (0 << GCLK_PCHCTRL_GEN_SHIFT) +# define GCLK_PCHCTRL_GEN1 (1 << GCLK_PCHCTRL_GEN_SHIFT) +# define GCLK_PCHCTRL_GEN2 (2 << GCLK_PCHCTRL_GEN_SHIFT) +# define GCLK_PCHCTRL_GEN3 (3 << GCLK_PCHCTRL_GEN_SHIFT) +# define GCLK_PCHCTRL_GEN4 (4 << GCLK_PCHCTRL_GEN_SHIFT) +# define GCLK_PCHCTRL_GEN5 (5 << GCLK_PCHCTRL_GEN_SHIFT) +# define GCLK_PCHCTRL_GEN6 (6 << GCLK_PCHCTRL_GEN_SHIFT) +# define GCLK_PCHCTRL_GEN7 (7 << GCLK_PCHCTRL_GEN_SHIFT) +# define GCLK_PCHCTRL_GEN8 (8 << GCLK_PCHCTRL_GEN_SHIFT) +#define GCLK_PCHCTRL_CHEN (1 << 6) /* Bit 6: Channel enable */ +#define GCLK_PCHCTRL_WRTLOCK (1 << 7) /* Bit 7: Write lock */ + +/* PCHCTRL mapping **************************************************************************/ + +#define GCLK__DFLL48M_REF 0 /* DFLL48M Reference */ +#define GCLK__DPLL 1 /* FDPLL96M input clock source for reference */ +#define GCLK__DPLL_32K 2 /* FDPLL96M 32kHz clock for FDPLL96M internal lock timer */ +#define GCLK__EIC 3 /* EIC */ +#define GCLK__USB 4 /* USB */ +#define GCLK__EVSYS_CHANNEL_0 5 /* EVSYS_CHANNEL_0 */ +#define GCLK__EVSYS_CHANNEL_1 6 /* EVSYS_CHANNEL_1 */ +#define GCLK__EVSYS_CHANNEL_2 7 /* EVSYS_CHANNEL_2 */ +#define GCLK__EVSYS_CHANNEL_3 8 /* EVSYS_CHANNEL_3 */ +#define GCLK__EVSYS_CHANNEL_4 9 /* EVSYS_CHANNEL_4 */ +#define GCLK__EVSYS_CHANNEL_5 10 /* EVSYS_CHANNEL_5 */ +#define GCLK__EVSYS_CHANNEL_6 11 /* EVSYS_CHANNEL_6 */ +#define GCLK__EVSYS_CHANNEL_7 12 /* EVSYS_CHANNEL_7 */ +#define GCLK__EVSYS_CHANNEL_8 13 /* EVSYS_CHANNEL_8 */ +#define GCLK__EVSYS_CHANNEL_9 14 /* EVSYS_CHANNEL_9 */ +#define GCLK__EVSYS_CHANNEL_10 15 /* EVSYS_CHANNEL_10 */ +#define GCLK__EVSYS_CHANNEL_11 16 /* EVSYS_CHANNEL_11 */ +#define GCLK__SERCOM0_SLOW 17 /* SERCOM0_SLOW */ +#define GCLK__SERCOM1_SLOW 17 /* SERCOM1_SLOW */ +#define GCLK__SERCOM2_SLOW 17 /* SERCOM2_SLOW */ +#define GCLK__SERCOM3_SLOW 17 /* SERCOM3_SLOW */ +#define GCLK__SERCOM4_SLOW 17 /* SERCOM4_SLOW */ +#define GCLK__SERCOM0_CORE 18 /* SERCOM0_CORE */ +#define GCLK__SERCOM1_CORE 19 /* SERCOM1_CORE */ +#define GCLK__SERCOM2_CORE 20 /* SERCOM2_CORE */ +#define GCLK__SERCOM3_CORE 21 /* SERCOM3_CORE */ +#define GCLK__SERCOM4_CORE 22 /* SERCOM4_CORE */ +#define GCLK__SERCOM5_SLOW 23 /* SERCOM5_SLOW */ +#define GCLK__SERCOM5_CORE 24 /* SERCOM5_CORE */ +#define GCLK_TCC0 25 /* TCC0 */ +#define GCLK_TCC1 25 /* TCC1 */ +#define GCLK_TCC2 26 /* TCC2 */ +#define GCLK_TC3_1 26 /* TC3 */ +#define GCLK_TC0 27 /* TC0 */ +#define GCLK_TC1 27 /* TC1 */ +#define GCLK_TC2 28 /* TC2 */ +#define GCLK_TC3_2 28 /* TC3 */ +#define GCLK__TC4 29 /* TC4 */ +#define GCLK__ADC 30 /* ADC */ +#define GCLK__AC 31 /* AC */ +#define GCLK__DAC 32 /* DAC */ +#define GCLK__PTC 33 /* PTC */ +#define GCLK__CCL 34 /* CCL */ + +/******************************************************************************************** + * Public Types + ********************************************************************************************/ + +/******************************************************************************************** + * Public Data + ********************************************************************************************/ + +/******************************************************************************************** + * Public Functions + ********************************************************************************************/ + +#endif /* CONFIG_ARCH_FAMILY_SAML21 */ +#endif /* __ARCH_ARM_SRC_SAMDL_CHIP_SAML_GCLK_H */ diff --git a/arch/arm/src/samdl/sam_lowputc.c b/arch/arm/src/samdl/sam_lowputc.c index 5844b98a586..ada594fc4f8 100644 --- a/arch/arm/src/samdl/sam_lowputc.c +++ b/arch/arm/src/samdl/sam_lowputc.c @@ -1,7 +1,7 @@ /**************************************************************************** * arch/arm/src/samdl/sam_lowputc.c * - * Copyright (C) 2014 Gregory Nutt. All rights reserved. + * Copyright (C) 2014-2015 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * References: @@ -59,10 +59,10 @@ #include #include "chip/sam_pm.h" -#include "chip/sam_gclk.h" #include "chip/sam_usart.h" #include "sam_usart.h" +#include "sam_gclk.h" #include "sam_lowputc.h" /**************************************************************************** diff --git a/arch/arm/src/samdl/sam_sercom.c b/arch/arm/src/samdl/sam_sercom.c index fe47b03c3f3..ca3f6b7f092 100644 --- a/arch/arm/src/samdl/sam_sercom.c +++ b/arch/arm/src/samdl/sam_sercom.c @@ -1,7 +1,7 @@ /**************************************************************************** * arch/arm/src/samdl/sam_lowputc.c * - * Copyright (C) 2014 Gregory Nutt. All rights reserved. + * Copyright (C) 2014-2015 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * References: @@ -51,9 +51,9 @@ #include "sam_config.h" #include "chip/sam_pm.h" -#include "chip/sam_gclk.h" #include "chip/sam_sercom.h" +#include "sam_gclk.h" #include "sam_sercom.h" /**************************************************************************** @@ -92,12 +92,12 @@ void sercom_coreclk_configure(int sercom, int gclkgen, bool wrlock) { uint16_t regval; - uint8_t glckcore; + uint8_t gclkcore; /* Set up the SERCOMn_GCLK_ID_CORE clock */ - glckcore = (uint8_t)SERCOM_GCLK_ID_CORE(sercom); - regval = ((uint16_t)glckcore << GCLK_CLKCTRL_ID_SHIFT); + gclkcore = (uint8_t)SERCOM_GCLK_ID_CORE(sercom); + regval = ((uint16_t)gclkcore << GCLK_CLKCTRL_ID_SHIFT); /* Select and disable the SERCOMn_GCLK_ID_CORE generic clock */ diff --git a/arch/arm/src/samdl/sam_spi.c b/arch/arm/src/samdl/sam_spi.c index 3f16b729f32..43a6f823f2b 100644 --- a/arch/arm/src/samdl/sam_spi.c +++ b/arch/arm/src/samdl/sam_spi.c @@ -1,7 +1,7 @@ /**************************************************************************** * arch/arm/src/samdl/sam_spi.c * - * Copyright (C) 2014 Gregory Nutt. All rights reserved. + * Copyright (C) 2014-2015 Gregory Nutt. All rights reserved. * Authors: Gregory Nutt * * References: @@ -64,11 +64,11 @@ #include "chip.h" #include "chip/sam_port.h" #include "chip/sam_pinmap.h" -#include "chip/sam_gclk.h" #include "chip/sam_spi.h" #include +#include "sam_gclk.h" #include "sam_port.h" #include "sam_sercom.h" #include "sam_spi.h" diff --git a/arch/arm/src/samdl/sam_usart.c b/arch/arm/src/samdl/sam_usart.c index 8e9fd37e77e..3bd84c2bef6 100644 --- a/arch/arm/src/samdl/sam_usart.c +++ b/arch/arm/src/samdl/sam_usart.c @@ -1,7 +1,7 @@ /**************************************************************************** * arch/arm/src/samdl/sam_usart.c * - * Copyright (C) 2014 Gregory Nutt. All rights reserved. + * Copyright (C) 2014-2015 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -43,13 +43,13 @@ #include #include "chip/sam_pinmap.h" -#include "chip/sam_gclk.h" #include "chip/sam_usart.h" -#include - +#include "sam_gclk.h" #include "sam_usart.h" +#include + /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ diff --git a/arch/arm/src/samdl/samd_clockconfig.c b/arch/arm/src/samdl/samd_clockconfig.c index 80264829fb8..6ac485d49f2 100644 --- a/arch/arm/src/samdl/samd_clockconfig.c +++ b/arch/arm/src/samdl/samd_clockconfig.c @@ -56,7 +56,7 @@ #include "chip/sam_pm.h" #include "chip/samd_sysctrl.h" -#include "chip/sam_gclk.h" +#include "chip/samd_gclk.h" #include "chip/sam_nvmctrl.h" #include "chip/sam_fuses.h" diff --git a/configs/samd20-xplained/nsh/setenv.sh b/configs/samd20-xplained/nsh/setenv.sh index 625446b717e..cb61ecf66fc 100755 --- a/configs/samd20-xplained/nsh/setenv.sh +++ b/configs/samd20-xplained/nsh/setenv.sh @@ -57,6 +57,7 @@ fi # the CodeSourcery toolchain in any other location #export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/CodeSourcery/Sourcery G++ Lite/bin" export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/CodeSourcery/Sourcery_CodeBench_Lite_for_ARM_EABI/bin" +#export TOOLCHAIN_BIN="/cygdrive/c/Users/MyName/MentorGraphics/Sourcery_CodeBench_Lite_for_ARM_EABI/bin" # These are the Cygwin paths to the locations where I installed the Atollic # toolchain under windows. You will also have to edit this if you install