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Fix nxstyle warning

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Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
This commit is contained in:
Xiang Xiao 2020-08-07 01:41:45 +08:00 • committed by Alan Carvalho de Assis
parent 4c706771c3
commit f618de9c97
58 changed files with 2765 additions and 2165 deletions
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243
arch/arm/src/c5471/c5471_ethernet.c
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@ -77,6 +77,7 @@
****************************************************************************/
/* Configuration ************************************************************/
/* If processing is not done at the interrupt level, then work queue support
* is required.
*/
@ -128,9 +129,9 @@
/* This should be disabled unless you are performing very low level debug */
#undef CONFIG_C5471_NET_DUMPBUFFER
//#define CONFIG_C5471_NET_DUMPBUFFER 1
/* Timing values ************************************************************/
/* TX poll deley = 1 seconds. CLK_TCK=number of clock ticks per second */
#define C5471_WDDELAY (1*CLK_TCK)
@ -175,6 +176,7 @@
#define NUM_DESC_RX 64
/* TX descriptor, word #1 */
/* Bit 15: reserved */
#define EIM_TXDESC_PADCRC 0x00004000 /* Bit 14: Enable padding small frames */
/* Bits 11-13: reserved */
@ -202,10 +204,12 @@
#define EIM_RXDESC_PADCRC 0x00004000 /* Enable padding for small frames */
/* RX descriptor, word #1 */
/* Bits 11-15: reserved */
#define EIM_RXDESC_BYTEMASK 0x000007ff /* Bits 0-10: Descriptor byte count */
/* EIM_CPU_FILTER bit settings */
/* Bits 5-31: reserved */
#define EIM_FILTER_MACLA 0x00000010 /* Bit 4: Enable logical address+multicast filtering */
#define EIM_FILTER_LOGICAL 0x00000008 /* Bit 3: Enable ENET logical filtering */
@ -214,6 +218,7 @@
#define EIM_FILTER_UNICAST 0x00000001 /* Bit 0: Enable dest CPU address matching */
/* EIM_CTRL bit settings */
/* Bits 16-31: Reserved */
#define EIM_CTRL_ESM_EN 0x00008000 /* Bit 15: Ethernet state machine enable */
/* Bits 9-14: reserved */
@ -227,6 +232,7 @@
#define EIM_CTRL_TXCPU_EN 0x00000001 /* Bit 0: Enable processing of CPU TX queue */
/* EIM_STATUS bit settings */
/* Bits 10-31: reserved */
#define EIM_STATUS_CPU_TXLIF 0x00000200 /* Bit 9: Last descriptor of TX packet filled */
#define EIM_STATUS_CPU_RXLIF 0x00000100 /* Bit 8: Last descriptor of RX queue processed */
@ -243,7 +249,7 @@
#define EIM_INTEN_CPU_RXLIF 0x00000100 /* Bit 8: Last descriptor of RX queue processed */
#define EIM_INTEN_CPU_TX 0x00000080 /* Bit 7: Descriptor filled in TX queue */
#define EIM_INTEN_CPU_RX 0x00000040 /* Bit 6: Descriptor filled in RX queue */
/* Bits 3-5: reserved */
/* Bits 3-5: reserved */
#define EIM_INTEN_ENET0_ERR 0x00000004 /* Bit 2: ENET0 error interrupt */
#define EIM_INTEN_ENET0_TX 0x00000002 /* Bit 1: ENET0 TX interrupt */
#define EIM_INTEN_ENET0_RX 0x00000001 /* Bit 0: ENET0 RX interrupt */
@ -256,6 +262,7 @@
#define ENET_ADDR_PCOMPARE 0x00000001 /* Bit 0: Enable physical address comparison */
/* ENET0_MODE bit settings */
/* Bits 16-31: reserved */
#define ENET_MODO_FIFO_EN 0x00008000 /* Bit 15: Fifo enable */
/* Bits 8-14: reserved */
@ -292,7 +299,7 @@
#define nop() asm(" nop");
/* This is a helper pointer for accessing the contents of the Ethernet header */
/* This is a helper pointer for accessing the contents of Ethernet header */
#define BUF ((struct eth_hdr_s *)priv->c_dev.d_buf)
@ -316,10 +323,11 @@ struct c5471_driver_s
struct work_s c_irqwork; /* For deferring interrupt work to the work queue */
struct work_s c_pollwork; /* For deferring poll work to the work queue */
/* Note: According to the C547x documentation: "The software has to maintain
* two pointers to the current RX-CPU and TX-CPU descriptors. At init time,
* they have to be set to the first descriptors of each queue, and they have
* to be incremented each time a descriptor ownership is give to the SWITCH".
/* Note: According to the C547x documentation: "The software has to
* maintain two pointers to the current RX-CPU and TX-CPU descriptors.
* At init time, they have to be set to the first descriptors of each
* queue, and they have to be incremented each time a descriptor
* ownership is give to the SWITCH".
*/
volatile uint32_t c_txcpudesc;
@ -449,8 +457,8 @@ static void c5471_macassign(struct c5471_driver_s *priv);
static inline void c5471_dumpbuffer(const char *msg, const uint8_t *buffer,
unsigned int nbytes)
{
/* CONFIG_DEBUG_FEATURES, CONFIG_DEBUG_INFO, and CONFIG_DEBUG_NET have to be
* defined or the following does nothing.
/* CONFIG_DEBUG_FEATURES, CONFIG_DEBUG_INFO, and CONFIG_DEBUG_NET have to
* be defined or the following does nothing.
*/
ninfodumpbuffer(msg, buffer, nbytes);
@ -481,8 +489,8 @@ static inline void c5471_dumpbuffer(const char *msg, const uint8_t *buffer,
static void c5471_mdtxbit (int bit_state)
{
/* Note: any non-zero "bit_state" supplied by the caller means we should clk a "1"
* out the MDIO pin.
/* Note: any non-zero "bit_state" supplied by the caller means we should
* clk a "1" out the MDIO pin.
*/
/* Config MDIO as output pin. */
@ -722,17 +730,17 @@ static int c5471_mdread (int adr, int reg)
* handle the physical layer (PHY). It's a h/w block that on the one end
* offers a Media Independent Interface (MII) which is connected to the
* Ethernet Interface Module (EIM) internal to the C547x and on the other
* end offers either the 10baseT or 100baseT electrical interface connecting
* to an RJ45 onboard network connector. The PHY transeiver has several
* internal registers allowing host configuration and status access. These
* internal registers are accessible by clocking serial data in/out of the
* MDIO pin of the LU3X31T-T64 chip. For c547X, the MDC and the MDIO pins
* are connected to the C547x GPIO15 and GPIO14 pins respectively. Host
* software twiddles the GPIO pins appropriately to get data serially into
* and out of the chip. This is typically a one time operation at boot and
* normal operation of the transeiver involves EIM/Transeiver interaction at
* the other pins of the transeiver chip and doesn't require host intervention
* at the MDC and MDIO pins.
* end offers either the 10baseT or 100baseT electrical interface
* connecting to an RJ45 onboard network connector. The PHY transeiver has
* several internal registers allowing host configuration and status
* access. These internal registers are accessible by clocking serial data
* in/out of the MDIO pin of the LU3X31T-T64 chip. For c547X, the MDC and
* the MDIO pins are connected to the C547x GPIO15 and GPIO14 pins
* respectively. Host software twiddles the GPIO pins appropriately to get
* data serially into and out of the chip. This is typically a one time
* operation at boot and normal operation of the transeiver involves
* EIM/Transeiver interaction at the other pins of the transeiver chip and
* doesn't require host intervention at the MDC and MDIO pins.
*
****************************************************************************/
@ -746,7 +754,7 @@ static int c5471_phyinit (void)
/* enable gpio bits 15,14 */
putreg32((getreg32(GPIO_EN) | 0x0000C000), GPIO_EN);
putreg32((getreg32(GPIO_EN) | 0x0000c000), GPIO_EN);
/* config gpio(15); out -> MDCLK */
@ -758,7 +766,7 @@ static int c5471_phyinit (void)
/* initial pin state; MDCLK = 0 */
putreg32((getreg32(GPIO_IO) & 0x000F3FFF), GPIO_IO);
putreg32((getreg32(GPIO_IO) & 0x000f3fff), GPIO_IO);
/* Next, request a chip reset */
@ -770,7 +778,8 @@ static int c5471_phyinit (void)
/* Next, Read out the chip ID */
phyid = (c5471_mdread(0, MD_PHY_MSB_REG) << 16) | c5471_mdread(0, MD_PHY_LSB_REG);
phyid = (c5471_mdread(0, MD_PHY_MSB_REG) << 16) |
c5471_mdread(0, MD_PHY_LSB_REG);
if (phyid != LU3X31_T64_PHYID)
{
nerr("ERROR: Unrecognized PHY ID: %08x\n", phyid);
@ -805,10 +814,10 @@ static int c5471_phyinit (void)
/* Next, Setup GPIO pins to talk serially to the Lucent transeiver chip */
putreg32((getreg32(GPIO_EN) | 0x0000C000), GPIO_EN); /* enable gpio bits 15,14 */
putreg32((getreg32(GPIO_EN) | 0x0000c000), GPIO_EN); /* enable gpio bits 15,14 */
putreg32((getreg32(GPIO_CIO) & ~0x00008000), GPIO_CIO); /* config gpio(15); out -> MDCLK */
putreg32((getreg32(GPIO_CIO) | 0x00004000), GPIO_CIO); /* config gpio(14); in <- MDIO */
putreg32((getreg32(GPIO_IO) & 0x000F3FFF), GPIO_IO); /* initial pin state; MDCLK = 0 */
putreg32((getreg32(GPIO_CIO) | 0x00004000), GPIO_CIO); /* config gpio(14); in <- MDIO */
putreg32((getreg32(GPIO_IO) & 0x000f3fff), GPIO_IO); /* initial pin state; MDCLK = 0 */
return 1;
}
@ -902,8 +911,9 @@ static int c5471_transmit(struct c5471_driver_s *priv)
while (nbytes)
{
/* Verify that the hardware is ready to send another packet */
/* Words #0 and #1 of descriptor */
/* Verify that the hardware is ready to send another packet
* Words #0 and #1 of descriptor
*/
while (EIM_TXDESC_OWN_HOST & getreg32(priv->c_rxcpudesc))
{
@ -914,18 +924,22 @@ static int c5471_transmit(struct c5471_driver_s *priv)
if (bfirstframe)
{
putreg32((getreg32(priv->c_rxcpudesc) | EIM_RXDESC_FIF), priv->c_rxcpudesc);
putreg32((getreg32(priv->c_rxcpudesc) | EIM_RXDESC_FIF),
priv->c_rxcpudesc);
}
else
{
putreg32((getreg32(priv->c_rxcpudesc) & ~EIM_RXDESC_FIF), priv->c_rxcpudesc);
putreg32((getreg32(priv->c_rxcpudesc) & ~EIM_RXDESC_FIF),
priv->c_rxcpudesc);
}
putreg32((getreg32(priv->c_rxcpudesc) & ~EIM_RXDESC_PADCRC), priv->c_rxcpudesc);
putreg32((getreg32(priv->c_rxcpudesc) & ~EIM_RXDESC_PADCRC),
priv->c_rxcpudesc);
if (bfirstframe)
{
putreg32((getreg32(priv->c_rxcpudesc) | EIM_RXDESC_PADCRC), priv->c_rxcpudesc);
putreg32((getreg32(priv->c_rxcpudesc) | EIM_RXDESC_PADCRC),
priv->c_rxcpudesc);
}
if (nbytes >= EIM_PACKET_BYTES)
@ -937,8 +951,10 @@ static int c5471_transmit(struct c5471_driver_s *priv)
framelen = nbytes;
}
/* Submit ether frame bytes to the C5472 Ether Module packet memory space. */
/* Get the number of 16-bit values to transfer by dividing by 2 with round up. */
/* Submit ether frame bytes to the C5472 Ether Module packet memory
* space. Get the number of 16-bit values to transfer by dividing by
* 2 with round up.
*/
nshorts = (framelen + 1) >> 1;
@ -952,25 +968,31 @@ static int c5471_transmit(struct c5471_driver_s *priv)
packetmem[i] = htons(((uint16_t *)dev->d_buf)[j]);
}
putreg32(((getreg32(priv->c_rxcpudesc) & ~EIM_RXDESC_BYTEMASK) | framelen),
priv->c_rxcpudesc);
putreg32(((getreg32(priv->c_rxcpudesc) & ~EIM_RXDESC_BYTEMASK) |
framelen), priv->c_rxcpudesc);
nbytes -= framelen;
ninfo("Wrote framelen: %d nbytes: %d nshorts: %d\n", framelen, nbytes, nshorts);
ninfo("Wrote framelen: %d nbytes: %d nshorts: %d\n",
framelen, nbytes, nshorts);
if (0 == nbytes)
{
putreg32((getreg32(priv->c_rxcpudesc) | EIM_RXDESC_LIF), priv->c_rxcpudesc);
putreg32((getreg32(priv->c_rxcpudesc) | EIM_RXDESC_LIF),
priv->c_rxcpudesc);
}
else
{
putreg32((getreg32(priv->c_rxcpudesc) & ~EIM_RXDESC_LIF), priv->c_rxcpudesc);
putreg32((getreg32(priv->c_rxcpudesc) & ~EIM_RXDESC_LIF),
priv->c_rxcpudesc);
}
/* We're done with that descriptor; give access rights back to h/w */
putreg32((getreg32(priv->c_rxcpudesc) | EIM_RXDESC_OWN_HOST), priv->c_rxcpudesc);
putreg32((getreg32(priv->c_rxcpudesc) | EIM_RXDESC_OWN_HOST),
priv->c_rxcpudesc);
/* Next, tell Ether Module that those submitted bytes are ready for the wire */
/* Next, tell Ether Module that
* those submitted bytes are ready for the wire
*/
putreg32(0x00000001, EIM_CPU_RXREADY);
priv->c_lastdescend = priv->c_rxcpudesc;
@ -998,8 +1020,9 @@ static int c5471_transmit(struct c5471_driver_s *priv)
* Function: c5471_txpoll
*
* Description:
* The transmitter is available, check if the network has any outgoing packets ready
* to send. This is a callback from devif_poll(). devif_poll() may be called:
* The transmitter is available, check if the network has any outgoing
* packets ready to send. This is a callback from devif_poll().
* devif_poll() may be called:
*
* 1. When the preceding TX packet send is complete,
* 2. When the preceding TX packet send timesout and the interface is reset
@ -1053,8 +1076,8 @@ static int c5471_txpoll(struct net_driver_s *dev)
c5471_transmit(priv);
/* Check if the ESM has let go of the RX descriptor giving us access
* rights to submit another Ethernet frame.
/* Check if the ESM has let go of the RX descriptor giving us
* access rights to submit another Ethernet frame.
*/
if ((EIM_TXDESC_OWN_HOST & getreg32(priv->c_rxcpudesc)) != 0)
@ -1066,8 +1089,8 @@ static int c5471_txpoll(struct net_driver_s *dev)
}
}
/* If zero is returned, the polling will continue until all connections have
* been examined.
/* If zero is returned, the polling will continue until all connections
* have been examined.
*/
return 0;
@ -1114,7 +1137,9 @@ static void c5471_rxstatus(struct c5471_driver_s *priv)
break;
}
/* This packet is made up of several descriptors, find next one in chain. */
/* This packet is made up of several descriptors,
* find next one in chain.
*/
if (EIM_TXDESC_WRAP_NEXT & getreg32(desc))
{
@ -1203,8 +1228,9 @@ static void c5471_receive(struct c5471_driver_s *priv)
int j = 0;
/* Walk the newly received packet contained within the EIM and transfer
* its contents to the network buffer. This frees up the memory contained within
* the EIM for additional packets that might be received later from the network.
* its contents to the network buffer. This frees up the memory contained
* within the EIM for additional packets that might be received later from
* the network.
*/
ninfo("Reading TX CPU desc: %08x\n", priv->c_txcpudesc);
@ -1226,24 +1252,28 @@ static void c5471_receive(struct c5471_driver_s *priv)
framelen = (getreg32(priv->c_txcpudesc) & EIM_TXDESC_BYTEMASK);
packetlen += framelen;
/* Check if the received packet will fit within the network packet buffer */
/* Check if the received packet will fit
* within the network packet buffer
*/
if (packetlen < (CONFIG_NET_ETH_PKTSIZE + 4))
{
/* Get the packet memory from words #2 and #3 of descriptor */
packetmem = (uint16_t *)getreg32(priv->c_txcpudesc + sizeof(uint32_t));
packetmem = (uint16_t *)
getreg32(priv->c_txcpudesc + sizeof(uint32_t));
/* Divide by 2 with round up to get the number of 16-bit words. */
nshorts = (framelen + 1) >> 1;
ninfo("Reading framelen: %d packetlen: %d nshorts: %d packetmen: %p\n",
ninfo("Reading framelen: "
"%d packetlen: %d nshorts: %d packetmen: %p\n",
framelen, packetlen, nshorts, packetmem);
for (i = 0 ; i < nshorts; i++, j++)
{
/* Copy the data data from the hardware to priv->c_dev.d_buf 16-bits at
* a time.
/* Copy the data data from the hardware to priv->c_dev.d_buf
* 16-bits at a time.
*/
((uint16_t *)dev->d_buf)[j] = htons(packetmem[i]);
@ -1259,23 +1289,30 @@ static void c5471_receive(struct c5471_driver_s *priv)
bmore = false;
}
/* Next, Clear all bits of words0/1 of the emptied descriptor except preserve
* the settings of a select few. Can leave descriptor words 2/3 alone.
/* Next, Clear all bits of words0/1 of the emptied descriptor
* except preserve the settings of a select few. Can leave
* descriptor words 2/3 alone.
*/
putreg32((getreg32(priv->c_txcpudesc) & (EIM_TXDESC_WRAP_NEXT | EIM_TXDESC_INTRE)),
putreg32((getreg32(priv->c_txcpudesc) &
(EIM_TXDESC_WRAP_NEXT | EIM_TXDESC_INTRE)),
priv->c_txcpudesc);
/* Next, Give ownership of now emptied descriptor back to the Ether Module's SWITCH */
/* Next, Give ownership of now emptied descriptor back to
* the Ether Module's SWITCH
*/
putreg32((getreg32(priv->c_txcpudesc) | EIM_TXDESC_OWN_HOST), priv->c_txcpudesc);
putreg32((getreg32(priv->c_txcpudesc) | EIM_TXDESC_OWN_HOST),
priv->c_txcpudesc);
/* Advance to the next data buffer */
c5471_inctxcpu(priv);
}
/* Adjust the packet length to remove the CRC bytes that the network doesn't care about. */
/* Adjust the packet length to remove the CRC bytes
* that the network doesn't care about.
*/
packetlen -= 4;
@ -1285,8 +1322,8 @@ static void c5471_receive(struct c5471_driver_s *priv)
priv->c_rxpackets++;
#endif
/* If we successfully transferred the data into the network buffer, then pass it on
* to the network for processing.
/* If we successfully transferred the data into the network buffer,
* then pass it on to the network for processing.
*/
if (packetlen > 0 && packetlen < CONFIG_NET_ETH_PKTSIZE)
@ -1294,11 +1331,12 @@ static void c5471_receive(struct c5471_driver_s *priv)
/* Set amount of data in priv->c_dev.d_len. */
dev->d_len = packetlen;
ninfo("Received packet, packetlen: %d type: %02x\n", packetlen, ntohs(BUF->type));
ninfo("Received packet, packetlen: %d type: %02x\n",
packetlen, ntohs(BUF->type));
c5471_dumpbuffer("Received packet", dev->d_buf, dev->d_len);
#ifdef CONFIG_NET_PKT
/* When packet sockets are enabled, feed the frame into the packet tap */
/* When packet sockets are enabled, feed the frame into the tap */
pkt_input(dev);
#endif
@ -1318,9 +1356,9 @@ static void c5471_receive(struct c5471_driver_s *priv)
ipv4_input(dev);
/* If the above function invocation resulted in data that should be
* sent out on the network, the field d_len will set to a value > 0.
* Send that data now if ESM has let go of the RX descriptor giving us
* access rights to submit another Ethernet frame.
* sent out on the network, d_len field will set to a value > 0.
* Send that data now if ESM has let go of the RX descriptor giving
* us access rights to submit another Ethernet frame.
*/
if (dev->d_len > 0 &&
@ -1358,9 +1396,9 @@ static void c5471_receive(struct c5471_driver_s *priv)
ipv6_input(dev);
/* If the above function invocation resulted in data that should be
* sent out on the network, the field d_len will set to a value > 0.
* Send that data now if ESM has let go of the RX descriptor giving us
* access rights to submit another Ethernet frame.
* sent out on the network, d_len field will set to a value > 0.
* Send that data now if ESM has let go of the RX descriptor giving
* us access rights to submit another Ethernet frame.
*/
if (dev->d_len > 0 &&
@ -1394,9 +1432,9 @@ static void c5471_receive(struct c5471_driver_s *priv)
arp_arpin(dev);
/* If the above function invocation resulted in data that should be
* sent out on the network, the field d_len will set to a value > 0.
* Send that data now if ESM has let go of the RX descriptor giving us
* access rights to submit another Ethernet frame.
* sent out on the network, d_len field will set to a value > 0.
* Send that data now if ESM has let go of the RX descriptor giving
* us access rights to submit another Ethernet frame.
*/
if (dev->d_len > 0 &&
@ -1453,7 +1491,9 @@ static void c5471_txstatus(struct c5471_driver_s *priv)
break;
}
/* This packet is made up of several descriptors, find next one in chain. */
/* This packet is made up of several descriptors,
* find next one in chain.
*/
if (EIM_RXDESC_WRAP_NEXT & getreg32(priv->c_rxcpudesc))
{
@ -1572,13 +1612,14 @@ static void c5471_interrupt_work(FAR void *arg)
priv->c_eimstatus = getreg32(EIM_STATUS);
/* Handle interrupts according to status bit settings */
/* Check if we received an incoming packet, if so, call c5471_receive() */
if ((EIM_STATUS_CPU_TX & priv->c_eimstatus) != 0)
{
/* An incoming packet has been received by the EIM from the network and
* the interrupt associated with EIM's CPU TX queue has been asserted. It
* is the EIM's CPU TX queue that we need to read from to get those
* the interrupt associated with EIM's CPU TX queue has been asserted.
* It is the EIM's CPU TX queue that we need to read from to get those
* packets. We use this terminology to stay consistent with the Orion
* documentation.
*/
@ -1594,12 +1635,14 @@ static void c5471_interrupt_work(FAR void *arg)
c5471_receive(priv);
}
/* Check is a packet transmission just completed. If so, call c5471_txdone */
/* Check is a packet transmission just completed.
* If so, call c5471_txdone
*/
if ((EIM_STATUS_CPU_RX & priv->c_eimstatus) != 0)
{
/* An outgoing packet has been processed by the EIM and the interrupt
* associated with EIM's CPU RX queue has been asserted. It is the EIM's
* associated with EIM's CPU RX queue has been asserted. It is EIM's
* CPU RX queue that we put packets on to send them *out*. TWe use this
* terminology to stay consistent with the Orion documentation.
*/
@ -1776,7 +1819,9 @@ static void c5471_poll_work(FAR void *arg)
net_lock();
if ((EIM_TXDESC_OWN_HOST & getreg32(priv->c_rxcpudesc)) == 0)
{
/* If so, update TCP timing states and poll the network for new XMIT data */
/* If so, update TCP timing states and
* poll the network for new XMIT data
*/
devif_timer(&priv->c_dev, C5471_WDDELAY, c5471_txpoll);
}
@ -1860,11 +1905,11 @@ static int c5471_ifup(struct net_driver_s *dev)
putreg32(((getreg32(EIM_INTEN) | EIM_INTEN_CPU_TX | EIM_INTEN_CPU_RX)),
EIM_INTEN);
/* Next, go on-line. According to the C547X documentation the enables have to
* occur in this order to insure proper operation; ESM first then the ENET.
/* Next, go on-line. According to the C547X documentation the enables have
* to occur in this order to insure proper operation; ESM first then ENET.
*/
putreg32((getreg32(EIM_CTRL) | EIM_CTRL_ESM_EN), EIM_CTRL); /* enable ESM */
putreg32((getreg32(EIM_CTRL) | EIM_CTRL_ESM_EN), EIM_CTRL); /* enable ESM */
putreg32((getreg32(ENET0_MODE) | ENET_MODE_ENABLE), ENET0_MODE); /* enable ENET */
up_mdelay(100);
@ -2035,7 +2080,8 @@ static int c5471_txavail(FAR struct net_driver_s *dev)
#ifdef CONFIG_NET_MCASTGROUP
static int c5471_addmac(struct net_driver_s *dev, FAR const uint8_t *mac)
{
FAR struct c5471_driver_s *priv = (FAR struct c5471_driver_s *)dev->d_private;
FAR struct c5471_driver_s *priv =
(FAR struct c5471_driver_s *)dev->d_private;
/* Add the MAC address to the hardware multicast routing table */
@ -2048,8 +2094,8 @@ static int c5471_addmac(struct net_driver_s *dev, FAR const uint8_t *mac)
* Function: c5471_rmmac
*
* Description:
* NuttX Callback: Remove the specified MAC address from the hardware multicast
* address filtering
* NuttX Callback: Remove the specified MAC address from the hardware
* multicast address filtering
*
* Input Parameters:
* dev - Reference to the NuttX driver state structure
@ -2065,7 +2111,8 @@ static int c5471_addmac(struct net_driver_s *dev, FAR const uint8_t *mac)
#ifdef CONFIG_NET_MCASTGROUP
static int c5471_rmmac(struct net_driver_s *dev, FAR const uint8_t *mac)
{
FAR struct c5471_driver_s *priv = (FAR struct c5471_driver_s *)dev->d_private;
FAR struct c5471_driver_s *priv =
(FAR struct c5471_driver_s *)dev->d_private;
/* Add the MAC address to the hardware multicast routing table */
@ -2140,13 +2187,13 @@ static void c5471_eimconfig(struct c5471_driver_s *priv)
int i;
desc = EIM_RAM_START;
pbuf = EIM_RAM_START + 0x6C0;
pbuf = EIM_RAM_START + 0x6c0;
/* TX ENET 0 */
ninfo("TX ENET0 desc: %08x pbuf: %08x\n", desc, pbuf);
putreg32((desc & 0x0000ffff), ENET0_TDBA); /* 16-bit offset address */
for (i = NUM_DESC_TX-1; i >= 0; i--)
for (i = NUM_DESC_TX - 1; i >= 0; i--)
{
if (i == 0)
val = EIM_TXDESC_WRAP_NEXT;
@ -2173,7 +2220,7 @@ static void c5471_eimconfig(struct c5471_driver_s *priv)
ninfo("RX ENET0 desc: %08x pbuf: %08x\n", desc, pbuf);
putreg32((desc & 0x0000ffff), ENET0_RDBA); /* 16-bit offset address */
for (i = NUM_DESC_RX-1; i >= 0; i--)
for (i = NUM_DESC_RX - 1; i >= 0; i--)
{
if (i == 0)
val = EIM_RXDESC_WRAP_NEXT;
@ -2201,7 +2248,7 @@ static void c5471_eimconfig(struct c5471_driver_s *priv)
ninfo("TX CPU desc: %08x pbuf: %08x\n", desc, pbuf);
priv->c_txcpudesc = desc;
putreg32((desc & 0x0000ffff), EIM_CPU_TXBA); /* 16-bit offset address */
for (i = NUM_DESC_TX-1; i >= 0; i--)
for (i = NUM_DESC_TX - 1; i >= 0; i--)
{
/* Set words 1+2 of the TXDESC */
@ -2231,7 +2278,7 @@ static void c5471_eimconfig(struct c5471_driver_s *priv)
ninfo("RX CPU desc: %08x pbuf: %08x\n", desc, pbuf);
priv->c_rxcpudesc = desc;
putreg32((desc & 0x0000ffff), EIM_CPU_RXBA); /* 16-bit offset address */
for (i = NUM_DESC_RX-1; i >= 0; i--)
for (i = NUM_DESC_RX - 1; i >= 0; i--)
{
/* Set words 1+2 of the RXDESC */
@ -2266,9 +2313,10 @@ static void c5471_eimconfig(struct c5471_driver_s *priv)
#if 0
putreg32(EIM_FILTER_UNICAST, EIM_CPU_FILTER);
#elif 0
putreg32(EIM_FILTER_LOGICAL | EIM_FILTER_UNICAST | EIM_FILTER_MULTICAST |
EIM_FILTER_BROADCAST, EIM_CPU_FILTER);
#else
// putreg32(EIM_FILTER_LOGICAL | EIM_FILTER_UNICAST | EIM_FILTER_MULTICAST |
// EIM_FILTER_BROADCAST, EIM_CPU_FILTER);
putreg32(EIM_FILTER_UNICAST | EIM_FILTER_MULTICAST | EIM_FILTER_BROADCAST,
EIM_CPU_FILTER);
#endif
@ -2440,7 +2488,8 @@ void arm_netinitialize(void)
/* Initialize the driver structure */
memset(g_c5471, 0, CONFIG_C5471_NET_NINTERFACES*sizeof(struct c5471_driver_s));
memset(g_c5471, 0,
CONFIG_C5471_NET_NINTERFACES * sizeof(struct c5471_driver_s));
g_c5471[0].c_dev.d_buf = g_pktbuf; /* Single packet buffer */
g_c5471[0].c_dev.d_ifup = c5471_ifup; /* I/F down callback */
g_c5471[0].c_dev.d_ifdown = c5471_ifdown; /* I/F up (new IP address) callback */

6
arch/arm/src/imxrt/imxrt_enet.c
View file

@ -685,7 +685,7 @@ static inline void imxrt_dispatch(FAR struct imxrt_driver_s *priv)
NETDEV_RXPACKETS(&priv->dev);
#ifdef CONFIG_NET_PKT
/* When packet sockets are enabled, feed the frame into the packet tap */
/* When packet sockets are enabled, feed the frame into the tap */
pkt_input(&priv->dev);
#endif
@ -706,7 +706,7 @@ static inline void imxrt_dispatch(FAR struct imxrt_driver_s *priv)
ipv4_input(&priv->dev);
/* If the above function invocation resulted in data that should be
* sent out on the network, the field d_len will set to a value > 0.
* sent out on the network, d_len field will set to a value > 0.
*/
if (priv->dev.d_len > 0)
@ -746,7 +746,7 @@ static inline void imxrt_dispatch(FAR struct imxrt_driver_s *priv)
ipv6_input(&priv->dev);
/* If the above function invocation resulted in data that should be
* sent out on the network, the field d_len will set to a value > 0.
* sent out on the network, d_len field will set to a value > 0.
*/
if (priv->dev.d_len > 0)

6
arch/arm/src/kinetis/kinetis_enet.c
View file

@ -645,11 +645,9 @@ static void kinetis_receive(FAR struct kinetis_driver_s *priv)
(uint8_t *)kinesis_swap32((uint32_t)priv->rxdesc[priv->rxtail].data);
#ifdef CONFIG_NET_PKT
/* When packet sockets are enabled, feed the frame into the packet
* tap
*/
/* When packet sockets are enabled, feed the frame into the tap */
pkt_input(&priv->dev);
pkt_input(&priv->dev);
#endif
/* We only accept IP packets of the configured type and ARP packets */

28
arch/arm/src/lpc17xx_40xx/lpc17_40_ethernet.c
View file

@ -157,7 +157,9 @@
/* Timing *******************************************************************/
/* TX poll deley = 1 seconds. CLK_TCK is the number of clock ticks per second */
/* TX poll deley = 1 seconds.
* CLK_TCK is the number of clock ticks per second
*/
#define LPC17_40_WDDELAY (1*CLK_TCK)
@ -174,7 +176,7 @@
/* Misc. Helpers ************************************************************/
/* This is a helper pointer for accessing the contents of the Ethernet header */
/* This is a helper pointer for accessing the contents of Ethernet header */
#define BUF ((struct eth_hdr_s *)priv->lp_dev.d_buf)
@ -966,7 +968,9 @@ static void lpc17_40_rxdone_work(FAR void *arg)
pkt_input(&priv->lp_dev);
#endif
/* We only accept IP packets of the configured type and ARP packets */
/* We only accept IP packets of the configured type and ARP
* packets
*/
#ifdef CONFIG_NET_IPv4
if (BUF->type == HTONS(ETHTYPE_IP))
@ -988,7 +992,7 @@ static void lpc17_40_rxdone_work(FAR void *arg)
if (priv->lp_dev.d_len > 0)
{
/* Update the Ethernet header with the correct MAC address */
/* Update Ethernet header with the correct MAC address */
#ifdef CONFIG_NET_IPv6
if (IFF_IS_IPv4(priv->lp_dev.d_flags))
@ -1027,7 +1031,7 @@ static void lpc17_40_rxdone_work(FAR void *arg)
if (priv->lp_dev.d_len > 0)
{
/* Update the Ethernet header with the correct MAC address */
/* Update Ethernet header with the correct MAC address */
#ifdef CONFIG_NET_IPv4
if (IFF_IS_IPv4(priv->lp_dev.d_flags))
@ -1139,7 +1143,9 @@ static void lpc17_40_txdone_work(FAR void *arg)
net_lock();
if (priv->lp_txpending)
{
/* Clear the pending condition, send the packet, and restore Rx interrupts */
/* Clear the pending condition, send the packet,
* and restore Rx interrupts
*/
priv->lp_txpending = false;
@ -1675,7 +1681,9 @@ static int lpc17_40_ifup(struct net_driver_s *dev)
lpc17_40_macmode(priv->lp_mode);
/* Initialize EMAC DMA memory -- descriptors, status, packet buffers, etc. */
/* Initialize EMAC DMA memory --
* descriptors, status, packet buffers, etc.
*/
lpc17_40_txdescinit(priv);
lpc17_40_rxdescinit(priv);
@ -1838,7 +1846,7 @@ static void lpc17_40_txavail_work(FAR void *arg)
net_lock();
if (priv->lp_ifup)
{
/* Check if there is room in the hardware to hold another outgoing packet. */
/* Check if there is room in the hardware to hold another packet. */
if (lpc17_40_txdesc(priv) == OK)
{
@ -3288,7 +3296,7 @@ static inline int lpc17_40_ethinitialize(int intf)
/* Initialize the driver structure */
memset(priv, 0, sizeof(struct lpc17_40_driver_s));
priv->lp_dev.d_buf = pktbuf; /* Single packet buffer */
priv->lp_dev.d_buf = pktbuf; /* Single packet buffer */
priv->lp_dev.d_ifup = lpc17_40_ifup; /* I/F down callback */
priv->lp_dev.d_ifdown = lpc17_40_ifdown; /* I/F up (new IP address) callback */
priv->lp_dev.d_txavail = lpc17_40_txavail; /* New TX data callback */
@ -3299,7 +3307,7 @@ static inline int lpc17_40_ethinitialize(int intf)
#ifdef CONFIG_NETDEV_IOCTL
priv->lp_dev.d_ioctl = lpc17_40_eth_ioctl; /* Handle network IOCTL commands */
#endif
priv->lp_dev.d_private = (void *)priv; /* Used to recover private state from dev */
priv->lp_dev.d_private = (void *)priv; /* Used to recover private state from dev */
#if CONFIG_LPC17_40_NINTERFACES > 1
# error "A mechanism to associate base address an IRQ with an interface is needed"

1
arch/arm/src/lpc17xx_40xx/lpc17_40_i2c.c
View file

@ -403,6 +403,7 @@ static int lpc17_40_i2c_interrupt(int irq, FAR void *context, void *arg)
{
case 0x08: /* A START condition has been transmitted. */
case 0x10: /* A Repeated START condition has been transmitted. */
/* Set address */
putreg32(((I2C_M_READ & msg->flags) == I2C_M_READ) ?

12
arch/arm/src/lpc2378/lpc23xx_i2c.c
View file

@ -119,7 +119,7 @@ struct lpc2378_i2cdev_s
sem_t wait; /* Place to wait for state machine completion */
volatile uint8_t state; /* State of state machine */
WDOG_ID timeout; /* Watchdog to timeout when bus hung */
uint32_t frequency; /* Current I2C frequency */
uint32_t frequency; /* Current I2C frequency */
struct i2c_msg_s *msgs; /* remaining transfers - first one is in progress */
unsigned int nmsg; /* number of transfer remaining */
@ -314,9 +314,9 @@ static int lpc2378_i2c_interrupt(int irq, FAR void *context, FAR void *arg)
state &= 0xf8; /* state mask, only 0xX8 is possible */
switch (state)
{
case 0x08: /* A START condition has been transmitted. */
case 0x10: /* A Repeated START condition has been transmitted. */
case 0x08: /* A START condition has been transmitted. */
case 0x10: /* A Repeated START condition has been transmitted. */
/* Set address */
putreg32(((I2C_M_READ & msg->flags) == I2C_M_READ) ?
@ -401,7 +401,7 @@ static int lpc2378_i2c_transfer(FAR struct i2c_master_s *dev,
struct lpc2378_i2cdev_s *priv = (struct lpc2378_i2cdev_s *)dev;
int ret;
DEBUGASSERT(dev != NULL && msgs != NULL && count > 0);
DEBUGASSERT(dev != NULL && msgs != NULL && count > 0);
/* Get exclusive access to the I2C bus */
@ -430,7 +430,7 @@ static int lpc2378_i2c_transfer(FAR struct i2c_master_s *dev,
return ret;
}
/************************************************************************************
/****************************************************************************
* Name: lpc2378_i2c_reset
*
* Description:
@ -442,7 +442,7 @@ static int lpc2378_i2c_transfer(FAR struct i2c_master_s *dev,
* Returned Value:
* Zero (OK) on success; a negated errno value on failure.
*
************************************************************************************/
****************************************************************************/
#ifdef CONFIG_I2C_RESET
static int lpc2378_i2c_reset(FAR struct i2c_master_s * dev)

75
arch/arm/src/lpc31xx/lpc31_i2c.c
View file

@ -3,7 +3,8 @@
*
* Author: David Hewson
*
* Copyright (C) 2010-2011, 2014, 2016-2017 Gregory Nutt. All rights reserved.
* Copyright (C) 2010-2011, 2014, 2016-2017 Gregory Nutt. All rights
* reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
@ -78,6 +79,7 @@
/****************************************************************************
* Private Data
****************************************************************************/
struct lpc31_i2cdev_s
{
struct i2c_master_s dev; /* Generic I2C device */
@ -116,7 +118,8 @@ static int i2c_interrupt(int irq, FAR void *context, FAR void *arg);
static void i2c_progress(struct lpc31_i2cdev_s *priv);
static void i2c_timeout(int argc, wdparm_t arg, ...);
static void i2c_hwreset(struct lpc31_i2cdev_s *priv);
static void i2c_setfrequency(struct lpc31_i2cdev_s *priv, uint32_t frequency);
static void i2c_setfrequency(struct lpc31_i2cdev_s *priv,
uint32_t frequency);
static int i2c_transfer(FAR struct i2c_master_s *dev,
FAR struct i2c_msg_s *msgs, int count);
#ifdef CONFIG_I2C_RESET
@ -204,7 +207,8 @@ static int i2c_interrupt(int irq, FAR void *context, FAR void *arg)
static void i2c_progress(struct lpc31_i2cdev_s *priv)
{
struct i2c_msg_s *msg;
uint32_t stat, ctrl;
uint32_t stat;
uint32_t ctrl;
stat = getreg32(priv->base + LPC31_I2C_STAT_OFFSET);
@ -233,8 +237,9 @@ static void i2c_progress(struct lpc31_i2cdev_s *priv)
case I2C_STATE_START:
if ((msg->flags & I2C_M_TEN) != 0)
{
priv->header[0] = I2C_TX_START | 0xF0 | ((msg->addr & 0x300) >> 7);
priv->header[1] = msg->addr & 0xFF;
priv->header[0] = I2C_TX_START | 0xf0 |
((msg->addr & 0x300) >> 7);
priv->header[1] = msg->addr & 0xff;
priv->hdrcnt = 2;
if (msg->flags & I2C_M_READ)
{
@ -244,7 +249,8 @@ static void i2c_progress(struct lpc31_i2cdev_s *priv)
}
else
{
priv->header[0] = I2C_TX_START | (msg->addr << 1) | (msg->flags & I2C_M_READ);
priv->header[0] = I2C_TX_START | (msg->addr << 1) |
(msg->flags & I2C_M_READ);
priv->hdrcnt = 1;
}
@ -252,12 +258,14 @@ static void i2c_progress(struct lpc31_i2cdev_s *priv)
priv->state = I2C_STATE_HEADER;
priv->wrcnt = 0;
/* DROP THROUGH */
case I2C_STATE_HEADER:
while ((priv->wrcnt != priv->hdrcnt) && (stat & I2C_STAT_TFF) == 0)
{
putreg32(priv->header[priv->wrcnt], priv->base + LPC31_I2C_TX_OFFSET);
putreg32(priv->header[priv->wrcnt],
priv->base + LPC31_I2C_TX_OFFSET);
priv->wrcnt++;
stat = getreg32(priv->base + LPC31_I2C_STAT_OFFSET);
@ -267,21 +275,25 @@ static void i2c_progress(struct lpc31_i2cdev_s *priv)
{
/* Enable Tx FIFO Not Full Interrupt */
putreg32(ctrl | I2C_CTRL_TFFIE, priv->base + LPC31_I2C_CTRL_OFFSET);
putreg32(ctrl | I2C_CTRL_TFFIE,
priv->base + LPC31_I2C_CTRL_OFFSET);
goto out;
}
priv->state = I2C_STATE_TRANSFER;
priv->wrcnt = 0;
priv->rdcnt = 0;
/* DROP THROUGH */
case I2C_STATE_TRANSFER:
if (msg->flags & I2C_M_READ)
{
while ((priv->rdcnt != msg->length) && (stat & I2C_STAT_RFE) == 0)
while ((priv->rdcnt != msg->length) &&
(stat & I2C_STAT_RFE) == 0)
{
msg->buffer[priv->rdcnt] = getreg32 (priv->base + LPC31_I2C_RX_OFFSET);
msg->buffer[priv->rdcnt] =
getreg32(priv->base + LPC31_I2C_RX_OFFSET);
priv->rdcnt++;
stat = getreg32(priv->base + LPC31_I2C_STAT_OFFSET);
@ -289,13 +301,17 @@ static void i2c_progress(struct lpc31_i2cdev_s *priv)
if (priv->rdcnt < msg->length)
{
/* Not all data received, fill the Tx FIFO with more dummies */
/* Not all data received,
* fill the Tx FIFO with more dummies
*/
while ((priv->wrcnt != msg->length) && (stat & I2C_STAT_TFF) == 0)
while ((priv->wrcnt != msg->length) &&
(stat & I2C_STAT_TFF) == 0)
{
if ((priv->wrcnt + 1) == msg->length && priv->nmsg == 1)
if (priv->wrcnt + 1 == msg->length && priv->nmsg == 1)
{
putreg32(I2C_TX_STOP, priv->base + LPC31_I2C_TX_OFFSET);
putreg32(I2C_TX_STOP,
priv->base + LPC31_I2C_TX_OFFSET);
}
else
{
@ -309,30 +325,37 @@ static void i2c_progress(struct lpc31_i2cdev_s *priv)
if (priv->wrcnt < msg->length)
{
/* Enable Tx FIFO not full and Rx Fifo Avail Interrupts */
/* Enable Tx FIFO not full and
* Rx Fifo Avail Interrupts
*/
putreg32(ctrl | I2C_CTRL_TFFIE | I2C_CTRL_RFDAIE, priv->base + LPC31_I2C_CTRL_OFFSET);
putreg32(ctrl | I2C_CTRL_TFFIE | I2C_CTRL_RFDAIE,
priv->base + LPC31_I2C_CTRL_OFFSET);
}
else
{
/* Enable Rx Fifo Avail Interrupts */
putreg32(ctrl | I2C_CTRL_RFDAIE, priv->base + LPC31_I2C_CTRL_OFFSET);
putreg32(ctrl | I2C_CTRL_RFDAIE,
priv->base + LPC31_I2C_CTRL_OFFSET);
}
goto out;
}
}
else /* WRITE */
{
while ((priv->wrcnt != msg->length) && (stat & I2C_STAT_TFF) == 0)
while (!!(priv->wrcnt != msg->length) && (stat & I2C_STAT_TFF))
{
if ((priv->wrcnt + 1) == msg->length && priv->nmsg == 1)
{
putreg32(I2C_TX_STOP | msg->buffer[priv->wrcnt], priv->base + LPC31_I2C_TX_OFFSET);
putreg32(I2C_TX_STOP | msg->buffer[priv->wrcnt],
priv->base + LPC31_I2C_TX_OFFSET);
}
else
{
putreg32(msg->buffer[priv->wrcnt], priv->base + LPC31_I2C_TX_OFFSET);
putreg32(msg->buffer[priv->wrcnt],
priv->base + LPC31_I2C_TX_OFFSET);
}
priv->wrcnt++;
@ -344,7 +367,8 @@ static void i2c_progress(struct lpc31_i2cdev_s *priv)
{
/* Enable Tx Fifo not full Interrupt */
putreg32(ctrl | I2C_CTRL_TFFIE, priv->base + LPC31_I2C_CTRL_OFFSET);
putreg32(ctrl | I2C_CTRL_TFFIE,
priv->base + LPC31_I2C_CTRL_OFFSET);
goto out;
}
}
@ -447,7 +471,7 @@ static void i2c_hwreset(struct lpc31_i2cdev_s *priv)
/* Wait for Reset to complete */
while ((getreg32(priv->base + LPC31_I2C_CTRL_OFFSET) & I2C_CTRL_RESET) != 0)
while (!!(getreg32(priv->base + LPC31_I2C_CTRL_OFFSET) & I2C_CTRL_RESET))
;
}
@ -459,7 +483,8 @@ static void i2c_hwreset(struct lpc31_i2cdev_s *priv)
*
****************************************************************************/
static int i2c_transfer(FAR struct i2c_master_s *dev, FAR struct i2c_msg_s *msgs, int count)
static int i2c_transfer(FAR struct i2c_master_s *dev,
FAR struct i2c_msg_s *msgs, int count)
{
struct lpc31_i2cdev_s *priv = (struct lpc31_i2cdev_s *) dev;
irqstate_t flags;
@ -507,7 +532,7 @@ static int i2c_transfer(FAR struct i2c_master_s *dev, FAR struct i2c_msg_s *msgs
return ret;
}
/************************************************************************************
/****************************************************************************
* Name: i2c_reset
*
* Description:
@ -519,7 +544,7 @@ static int i2c_transfer(FAR struct i2c_master_s *dev, FAR struct i2c_msg_s *msgs
* Returned Value:
* Zero (OK) on success; a negated errno value on failure.
*
************************************************************************************/
****************************************************************************/
#ifdef CONFIG_I2C_RESET
static int i2c_reset(FAR struct i2c_master_s * dev)

528
arch/arm/src/lpc43xx/lpc43_ethernet.c
View file

File diff suppressed because it is too large Load diff

17
arch/arm/src/lpc43xx/lpc43_i2c.c
View file

@ -102,7 +102,7 @@ struct lpc43_i2cdev_s
struct i2c_master_s dev; /* Generic I2C device */
unsigned int base; /* Base address of registers */
uint16_t irqid; /* IRQ for this device */
uint32_t base_freq; /* branch frequency */
uint32_t base_freq; /* branch frequency */
sem_t mutex; /* Only one thread can access at a time */
sem_t wait; /* Place to wait for state machine completion */
@ -295,8 +295,9 @@ static int lpc43_i2c_interrupt(int irq, FAR void *context, FAR void *arg)
state &= 0xf8; /* state mask, only 0xX8 is possible */
switch (state)
{
case 0x08: /* A START condition has been transmitted. */
case 0x10: /* A Repeated START condition has been transmitted. */
case 0x08: /* A START condition has been transmitted. */
case 0x10: /* A Repeated START condition has been transmitted. */
/* Set address */
putreg32(((I2C_M_READ & msg->flags) == I2C_M_READ) ?
@ -344,7 +345,8 @@ static int lpc43_i2c_interrupt(int irq, FAR void *context, FAR void *arg)
case 0x50: /* Data byte has been received; ACK has been returned. */
priv->rdcnt++;
msg->buffer[priv->rdcnt - 1] = getreg32(priv->base + LPC43_I2C_BUFR_OFFSET);
msg->buffer[priv->rdcnt - 1] =
getreg32(priv->base + LPC43_I2C_BUFR_OFFSET);
if (priv->rdcnt >= (msg->length - 1))
{
@ -353,7 +355,8 @@ static int lpc43_i2c_interrupt(int irq, FAR void *context, FAR void *arg)
break;
case 0x58: /* Data byte has been received; NACK has been returned. */
msg->buffer[priv->rdcnt] = getreg32(priv->base + LPC43_I2C_BUFR_OFFSET);
msg->buffer[priv->rdcnt] =
getreg32(priv->base + LPC43_I2C_BUFR_OFFSET);
lpc32_i2c_nextmsg(priv);
break;
@ -410,7 +413,7 @@ static int lpc43_i2c_transfer(FAR struct i2c_master_s *dev,
return ret;
}
/************************************************************************************
/****************************************************************************
* Name: lpc43_i2c_reset
*
* Description:
@ -422,7 +425,7 @@ static int lpc43_i2c_transfer(FAR struct i2c_master_s *dev,
* Returned Value:
* Zero (OK) on success; a negated errno value on failure.
*
************************************************************************************/
****************************************************************************/
#ifdef CONFIG_I2C_RESET
static int lpc43_i2c_reset(FAR struct i2c_master_s * dev)

158
arch/arm/src/lpc54xx/hardware/lpc54_ethernet.h
View file

@ -90,8 +90,8 @@
#define LPC54_ETH_MAC_SYS_TIMESTMP_ADDEND_OFFSET 0x0b18 /* Timestamp addend */
#define LPC54_ETH_MAC_SYS_TIME_HWORD_SCND_OFFSET 0x0b1c /* System time-higher word seconds */
#define LPC54_ETH_MAC_SYS_TIMESTMP_STAT_OFFSET 0x0b20 /* Timestamp status */
#define LPC54_ETH_MAC_Tx_TIMESTAMP_STATUS_NSECS_OFFSET 0x0b30 /* Tx timestamp status nanoseconds */
#define LPC54_ETH_MAC_Tx_TIMESTAMP_STATUS_SECS_OFFSET 0x0b34 /* Tx timestamp status seconds */
#define LPC54_ETH_MAC_TX_TIMESTAMP_STATUS_NSECS_OFFSET 0x0b30 /* Tx timestamp status nanoseconds */
#define LPC54_ETH_MAC_TX_TIMESTAMP_STATUS_SECS_OFFSET 0x0b34 /* Tx timestamp status seconds */
#define LPC54_ETH_MAC_TIMESTAMP_INGRESS_CORR_NSEC_OFFSET 0x0b58 /* Timestamp ingress correction */
#define LPC54_ETH_MAC_TIMESTAMP_EGRESS_CORR_NSEC_OFFSET 0x0b5c /* Timestamp egress correction */
@ -185,8 +185,8 @@
#define LPC54_ETH_MAC_SYS_TIMESTMP_ADDEND (LPC54_ETHERNET_BASE + LPC54_ETH_MAC_SYS_TIMESTMP_ADDEND_OFFSET)
#define LPC54_ETH_MAC_SYS_TIME_HWORD_SCND (LPC54_ETHERNET_BASE + LPC54_ETH_MAC_SYS_TIME_HWORD_SCND_OFFSET)
#define LPC54_ETH_MAC_SYS_TIMESTMP_STAT (LPC54_ETHERNET_BASE + LPC54_ETH_MAC_SYS_TIMESTMP_STAT_OFFSET)
#define LPC54_ETH_MAC_Tx_TIMESTAMP_STATUS_NSECS (LPC54_ETHERNET_BASE + LPC54_ETH_MAC_Tx_TIMESTAMP_STATUS_NSECS_OFFSET)
#define LPC54_ETH_MAC_Tx_TIMESTAMP_STATUS_SECS (LPC54_ETHERNET_BASE + LPC54_ETH_MAC_Tx_TIMESTAMP_STATUS_SECS_OFFSET)
#define LPC54_ETH_MAC_TX_TIMESTAMP_STATUS_NSECS (LPC54_ETHERNET_BASE + LPC54_ETH_MAC_TX_TIMESTAMP_STATUS_NSECS_OFFSET)
#define LPC54_ETH_MAC_TX_TIMESTAMP_STATUS_SECS (LPC54_ETHERNET_BASE + LPC54_ETH_MAC_TX_TIMESTAMP_STATUS_SECS_OFFSET)
#define LPC54_ETH_MAC_TIMESTAMP_INGRESS_CORR_NSEC (LPC54_ETHERNET_BASE + LPC54_ETH_MAC_TIMESTAMP_INGRESS_CORR_NSEC_OFFSET)
#define LPC54_ETH_MAC_TIMESTAMP_EGRESS_CORR_NSEC (LPC54_ETHERNET_BASE + LPC54_ETH_MAC_TIMESTAMP_EGRESS_CORR_NSEC_OFFSET)
@ -248,30 +248,30 @@
# define ETH_MAC_CONFIG_PRELEN_7 (0 << ETH_MAC_CONFIG_PRELEN_SHIFT) /* 7 bytes of preamble */
# define ETH_MAC_CONFIG_PRELEN_5 (1 << ETH_MAC_CONFIG_PRELEN_SHIFT) /* 5 bytes of preamble */
# define ETH_MAC_CONFIG_PRELEN_3 (2 << ETH_MAC_CONFIG_PRELEN_SHIFT) /* 3 bytes of preamble */
#define ETH_MAC_CONFIG_DC (1 << 4) /* Bit 4: Deferral check */
#define ETH_MAC_CONFIG_BL_SHIFT (5) /* Bits 5-6: Back-off limit */
#define ETH_MAC_CONFIG_DC (1 << 4) /* Bit 4: Deferral check */
#define ETH_MAC_CONFIG_BL_SHIFT (5) /* Bits 5-6: Back-off limit */
#define ETH_MAC_CONFIG_BL_MASK (3 << ETH_MAC_CONFIG_BL_SHIFT)
# define ETH_MAC_CONFIG_BL_10 (0 << ETH_MAC_CONFIG_BL_SHIFT) /* k = min (n, 10) */
# define ETH_MAC_CONFIG_BL_8 (1 << ETH_MAC_CONFIG_BL_SHIFT) /* k = min (n, 8) */
# define ETH_MAC_CONFIG_BL_4 (2 << ETH_MAC_CONFIG_BL_SHIFT) /* k = min (n, 4) */
# define ETH_MAC_CONFIG_BL_1 (3 << ETH_MAC_CONFIG_BL_SHIFT) /* k = min (n, 1) */
#define ETH_MAC_CONFIG_DR (1 << 8) /* Bit 8: Disable retry */
#define ETH_MAC_CONFIG_DCRS (1 << 9) /* Bit 9: Disable carrier sense during transmission */
#define ETH_MAC_CONFIG_DO (1 << 10) /* Bit 10: Disable receive own */
#define ETH_MAC_CONFIG_ECRSFD (1 << 11) /* Bit 11: Enable carrier sense full-duplex mode before transmission */
#define ETH_MAC_CONFIG_LM (1 << 12) /* Bit 12: Loopback mode */
#define ETH_MAC_CONFIG_DM (1 << 13) /* Bit 13: Duplex mode */
#define ETH_MAC_CONFIG_FES (1 << 14) /* Bit 14: Speed */
#define ETH_MAC_CONFIG_PS (1 << 15) /* Bit 15: Port select */
#define ETH_MAC_CONFIG_JE (1 << 16) /* Bit 16: Jumbo frame enable */
#define ETH_MAC_CONFIG_JD (1 << 17) /* Bit 17: Jabber disable */
#define ETH_MAC_CONFIG_BE (1 << 18) /* Bit 18: Packet burst enable */
#define ETH_MAC_CONFIG_WD (1 << 19) /* Bit 19: Watchdog disable */
#define ETH_MAC_CONFIG_ACS (1 << 20) /* Bit 20: Automatic pad or CRC stripping */
#define ETH_MAC_CONFIG_CST (1 << 21) /* Bit 21: CRC stripping for type packets */
#define ETH_MAC_CONFIG_S2KP (1 << 22) /* Bit 22: IEEE 802.3as support for 2K packets */
#define ETH_MAC_CONFIG_GPSLCE (1 << 23) /* Bit 23: Giant packet size limit control enable */
#define ETH_MAC_CONFIG_IPG_SHIFT (24) /* Bits 24-26: Inter-packet gap */
#define ETH_MAC_CONFIG_DR (1 << 8) /* Bit 8: Disable retry */
#define ETH_MAC_CONFIG_DCRS (1 << 9) /* Bit 9: Disable carrier sense during transmission */
#define ETH_MAC_CONFIG_DO (1 << 10) /* Bit 10: Disable receive own */
#define ETH_MAC_CONFIG_ECRSFD (1 << 11) /* Bit 11: Enable carrier sense full-duplex mode before transmission */
#define ETH_MAC_CONFIG_LM (1 << 12) /* Bit 12: Loopback mode */
#define ETH_MAC_CONFIG_DM (1 << 13) /* Bit 13: Duplex mode */
#define ETH_MAC_CONFIG_FES (1 << 14) /* Bit 14: Speed */
#define ETH_MAC_CONFIG_PS (1 << 15) /* Bit 15: Port select */
#define ETH_MAC_CONFIG_JE (1 << 16) /* Bit 16: Jumbo frame enable */
#define ETH_MAC_CONFIG_JD (1 << 17) /* Bit 17: Jabber disable */
#define ETH_MAC_CONFIG_BE (1 << 18) /* Bit 18: Packet burst enable */
#define ETH_MAC_CONFIG_WD (1 << 19) /* Bit 19: Watchdog disable */
#define ETH_MAC_CONFIG_ACS (1 << 20) /* Bit 20: Automatic pad or CRC stripping */
#define ETH_MAC_CONFIG_CST (1 << 21) /* Bit 21: CRC stripping for type packets */
#define ETH_MAC_CONFIG_S2KP (1 << 22) /* Bit 22: IEEE 802.3as support for 2K packets */
#define ETH_MAC_CONFIG_GPSLCE (1 << 23) /* Bit 23: Giant packet size limit control enable */
#define ETH_MAC_CONFIG_IPG_SHIFT (24) /* Bits 24-26: Inter-packet gap */
#define ETH_MAC_CONFIG_IPG_MASK (7 << ETH_MAC_CONFIG_IPG_SHIFT)
# define ETH_MAC_CONFIG_IPG_96 (0 << ETH_MAC_CONFIG_IPG_SHIFT) /* 96 bit times */
# define ETH_MAC_CONFIG_IPG_88 (1 << ETH_MAC_CONFIG_IPG_SHIFT) /* 88 bit times */
@ -281,7 +281,7 @@
# define ETH_MAC_CONFIG_IPG_56 (5 << ETH_MAC_CONFIG_IPG_SHIFT) /* 56 bit times */
# define ETH_MAC_CONFIG_IPG_48 (6 << ETH_MAC_CONFIG_IPG_SHIFT) /* 48 bit times */
# define ETH_MAC_CONFIG_IPG_40 (7 << ETH_MAC_CONFIG_IPG_SHIFT) /* 40 bit times */
#define ETH_MAC_CONFIG_IPC (1 << 27) /* Bit 27: Checksum offload */
#define ETH_MAC_CONFIG_IPC (1 << 27) /* Bit 27: Checksum offload */
/* MAC extended configuration */
#define ETH_MAC_EXT_CONFIG_
@ -298,9 +298,9 @@
# define ETH_MAC_FRAME_FILTER_PCF_PAUSE (1 << ETH_MAC_FRAME_FILTER_PCF_SHIFT) /* All but pause control frames accepted */
# define ETH_MAC_FRAME_FILTER_PCF_ALL (2 << ETH_MAC_FRAME_FILTER_PCF_SHIFT) /* All control frames accepted */
# define ETH_MAC_FRAME_FILTER_PCF_FILTERED (3 << ETH_MAC_FRAME_FILTER_PCF_SHIFT) /* Control frames accepted if pass the address filter */
#define ETH_MAC_FRAME_FILTER_SAIF (1 << 8) /* Bit 8: SA inverse filtering */
#define ETH_MAC_FRAME_FILTER_SAF (1 << 9) /* Bit 9: Source address filter enable */
#define ETH_MAC_FRAME_FILTER_RA (1 << 31) /* Bit 31: Receive all */
#define ETH_MAC_FRAME_FILTER_SAIF (1 << 8) /* Bit 8: SA inverse filtering */
#define ETH_MAC_FRAME_FILTER_SAF (1 << 9) /* Bit 9: Source address filter enable */
#define ETH_MAC_FRAME_FILTER_RA (1 << 31) /* Bit 31: Receive all */
/* MAC watchdog timeout */
#define ETH_MAC_WD_TIMEROUT_
@ -339,7 +339,7 @@
#define ETH_MAC_RXQ_CTRL0_RXQ0EN_MASK (3 << ETH_MAC_RXQ_CTRL0_RXQ0EN_SHIFT)
# define ETH_MAC_RXQ_CTRL0_RXQ0EN_DISABLE (0 << ETH_MAC_RXQ_CTRL0_RXQ0EN_SHIFT) /* Disable */
# define ETH_MAC_RXQ_CTRL0_RXQ0EN_ENABLE (1 << ETH_MAC_RXQ_CTRL0_RXQ0EN_SHIFT) /* Queue 0 enabled for AV */
#define ETH_MAC_RXQ_CTRL0_RXQ1EN_SHIFT (2) /* Bits 2-3: Rx Queue 1 enable */
#define ETH_MAC_RXQ_CTRL0_RXQ1EN_SHIFT (2) /* Bits 2-3: Rx Queue 1 enable */
#define ETH_MAC_RXQ_CTRL0_RXQ1EN_MASK (3 << ETH_MAC_RXQ_CTRL0_RXQ1EN_SHIFT)
# define ETH_MAC_RXQ_CTRL0_RXQ1EN_DISABLE (0 << ETH_MAC_RXQ_CTRL0_RXQ1EN_SHIFT) /* Disable */
# define ETH_MAC_RXQ_CTRL0_RXQ1EN_ENABLE (1 << ETH_MAC_RXQ_CTRL0_RXQ1EN_SHIFT) /* Queue 1 enabled for AV */
@ -349,16 +349,16 @@
#define ETH_MAC_RXQ_CTRL1_AVCPQ_SHIFT (0) /* Bits 0-2: AV untagged control packets queue */
#define ETH_MAC_RXQ_CTRL1_AVCPQ_MASK (7 < ETH_MAC_RXQ_CTRL1_AVCPQ_SHIFT)
# define ETH_MAC_RXQ_CTRL1_AVCPQ(n) ((uint32_t)(n) < ETH_MAC_RXQ_CTRL1_AVCPQ_SHIFT) /* Rx Queue n, n=0..1 */
#define ETH_MAC_RXQ_CTRL1_AVPTPQ_SHIFT (4) /* Bits 4-6: AV PTP packets queue */
#define ETH_MAC_RXQ_CTRL1_AVPTPQ_SHIFT (4) /* Bits 4-6: AV PTP packets queue */
#define ETH_MAC_RXQ_CTRL1_AVPTPQ_MASK (7 < ETH_MAC_RXQ_CTRL1_AVCPQ_SHIFT)
# define ETH_MAC_RXQ_CTRL1_AVPTPQ(n) ((uint32_t)(n) < ETH_MAC_RXQ_CTRL1_AVCPQ_SHIFT) /* Rx Queue n, n=0..1 */
#define ETH_MAC_RXQ_CTRL1_UPQ_SHIFT (12) /* Bits 12-14: Untagged packet queue */
#define ETH_MAC_RXQ_CTRL1_UPQ_SHIFT (12) /* Bits 12-14: Untagged packet queue */
#define ETH_MAC_RXQ_CTRL1_UPQ_MASK (7 < ETH_MAC_RXQ_CTRL1_AVCPQ_SHIFT)
# define ETH_MAC_RXQ_CTRL1_UPQ(n) ((uint32_t)(n) < ETH_MAC_RXQ_CTRL1_AVCPQ_SHIFT) /* Rx Queue n, n=0..1 */
#define ETH_MAC_RXQ_CTRL1_MCBCQ_SHIFT (16) /* Bits 16-18: Multicast and broadcast queue */
#define ETH_MAC_RXQ_CTRL1_MCBCQ_SHIFT (16) /* Bits 16-18: Multicast and broadcast queue */
#define ETH_MAC_RXQ_CTRL1_MCBCQ_MASK (7 < ETH_MAC_RXQ_CTRL1_AVCPQ_SHIFT)
# define ETH_MAC_RXQ_CTRL1_MCBCQ(n) ((uint32_t)(n) < ETH_MAC_RXQ_CTRL1_AVCPQ_SHIFT) /* Rx Queue n, n=0..1 */
#define ETH_MAC_RXQ_CTRL1_MCBCQEN (1 << 20) /* Bit 20: Multicast and broadcast queue enable */
#define ETH_MAC_RXQ_CTRL1_MCBCQEN (1 << 20) /* Bit 20: Multicast and broadcast queue enable */
/* Receive Queue control 2 */
@ -421,13 +421,13 @@
#define ETH_MAC_MDIO_ADDR_MOC_MASK (3 << ETH_MAC_MDIO_ADDR_MOC_SHIFT)
# define ETH_MAC_MDIO_ADDR_MOC_WRITE (1 << ETH_MAC_MDIO_ADDR_MOC_SHIFT) /* Write */
# define ETH_MAC_MDIO_ADDR_MOC_READ (3 << ETH_MAC_MDIO_ADDR_MOC_SHIFT) /* Read */
#define ETH_MAC_MDIO_ADDR_CR_SHIFT (8) /* Bits 8-11: CSR clock range */
#define ETH_MAC_MDIO_ADDR_CR_SHIFT (8) /* Bits 8-11: CSR clock range */
#define ETH_MAC_MDIO_ADDR_CR_MASK (15 << ETH_MAC_MDIO_ADDR_CR_SHIFT)
# define ETH_MAC_MDIO_ADDR_CR_DIV42 (0 << ETH_MAC_MDIO_ADDR_CR_SHIFT) /* CSR=60-100 MHz; MDC=CSR/42 */
# define ETH_MAC_MDIO_ADDR_CR_DIV62 (1 << ETH_MAC_MDIO_ADDR_CR_SHIFT) /* CSR=100-150 MHz; MDC=CSR/62 */
# define ETH_MAC_MDIO_ADDR_CR_DIV16 (2 << ETH_MAC_MDIO_ADDR_CR_SHIFT) /* CSR=20-35 MHz; MDC=CSR/16 */
# define ETH_MAC_MDIO_ADDR_CR_DIV26 (3 << ETH_MAC_MDIO_ADDR_CR_SHIFT) /* CSR=35-60 MHz; MDC=CSR/26 */
#define ETH_MAC_MDIO_ADDR_NTC_SHIFT (12) /* Bits 12-14: Number of training clocks */
#define ETH_MAC_MDIO_ADDR_NTC_SHIFT (12) /* Bits 12-14: Number of training clocks */
#define ETH_MAC_MDIO_ADDR_NTC_MASK (7 << ETH_MAC_MDIO_ADDR_NTC_SHIFT)
# define ETH_MAC_MDIO_ADDR_NTC(n) ((uint32_t)(n) << ETH_MAC_MDIO_ADDR_NTC_SHIFT)
#define ETH_MAC_MDIO_ADDR_RDA_SHIFT (16) /* Bits 16-20: Register/device address */
@ -471,9 +471,9 @@
/* Timestamp status */
#define ETH_MAC_SYS_TIMESTMP_STAT_
/* Tx timestamp status nanoseconds */
#define ETH_MAC_Tx_TIMESTAMP_STATUS_NSECS_
#define ETH_MAC_TX_TIMESTAMP_STATUS_NSECS_
/* Tx timestamp status seconds */
#define ETH_MAC_Tx_TIMESTAMP_STATUS_SECS_
#define ETH_MAC_TX_TIMESTAMP_STATUS_SECS_
/* Timestamp ingress correction */
#define ETH_MAC_TIMESTAMP_INGRESS_CORR_NSEC_
/* Timestamp egress correction */
@ -508,7 +508,7 @@
#define ETH_MTL_TXQ_OP_MODE_TXQEN_MASK (3 << ETH_MTL_TXQ_OP_MODE_TXQEN_SHIFT)
# define ETH_MTL_TXQ_OP_MODE_TXQEN_DISABLE (0 << ETH_MTL_TXQ_OP_MODE_TXQEN_SHIFT) /* Not enabled */
# define ETH_MTL_TXQ_OP_MODE_TXQEN_ENABLE (2 << ETH_MTL_TXQ_OP_MODE_TXQEN_SHIFT) /* Enabled */
#define ETH_MTL_TXQ_OP_MODE_TTC_SHIFT (4) /* Bits 4-6: Transmit threshold control */
#define ETH_MTL_TXQ_OP_MODE_TTC_SHIFT (4) /* Bits 4-6: Transmit threshold control */
#define ETH_MTL_TXQ_OP_MODE_TTC_MASK (7 << ETH_MTL_TXQ_OP_MODE_TTC_SHIFT)
# define ETH_MTL_TXQ_OP_MODE_TTC_32 (0 << ETH_MTL_TXQ_OP_MODE_TTC_SHIFT)
# define ETH_MTL_TXQ_OP_MODE_TTC_64 (1 << ETH_MTL_TXQ_OP_MODE_TTC_SHIFT)
@ -583,8 +583,8 @@
# define ETH_DMA_MODE_TAA_FIXED (0 << ETH_DMA_MODE_TAA_SHIFT) /* Fixed priority */
# define ETH_DMA_MODE_TAA_WSP (1 << ETH_DMA_MODE_TAA_SHIFT) /* Weighted strict priority */
# define ETH_DMA_MODE_TAA_WRR (2 << ETH_DMA_MODE_TAA_SHIFT) /* Weighted round-robin */
#define ETH_DMA_MODE_TXPR (1 << 11) /* Bit 11: Transmit priority */
#define ETH_DMA_MODE_PR_SHIFT (12) /* Bits 12-14: Priority ratio */
#define ETH_DMA_MODE_TXPR (1 << 11) /* Bit 11: Transmit priority */
#define ETH_DMA_MODE_PR_SHIFT (12) /* Bits 12-14: Priority ratio */
#define ETH_DMA_MODE_PR_MASK (7 << ETH_DMA_MODE_PR_SHIFT)
# define ETH_DMA_MODE_PR_1TO1 (0 << ETH_DMA_MODE_PR_SHIFT) /* Priority ratio is 1:1 */
# define ETH_DMA_MODE_PR_3TO1 (2 << ETH_DMA_MODE_PR_SHIFT) /* Priority ratio is 3:1 */
@ -623,9 +623,9 @@
#define ETH_DMACH_TX_CTRL_TCW_MASK (7 << ETH_DMACH_TX_CTRL_TCW_SHIFT)
# define ETH_DMACH_TX_CTRL_TCW(n) ((uint32_t)(n) << ETH_DMACH_TX_CTRL_TCW_SHIFT)
#define ETH_DMACH_TX_CTRL_OSF (1 << 4) /* Bit 4: Operate on second frame */
#define ETH_DMACH_TX_CTRL_TxPBL_SHIFT (16) /* Bits 16-21: Transmit programmable burst length */
#define ETH_DMACH_TX_CTRL_TxPBL_MASK (0x3f << ETH_DMACH_TX_CTRL_TxPBL_SHIFT)
# define ETH_DMACH_TX_CTRL_TxPBL(n) ((uint32_t)(n) << ETH_DMACH_TX_CTRL_TxPBL_SHIFT)
#define ETH_DMACH_TX_CTRL_TXPBL_SHIFT (16) /* Bits 16-21: Transmit programmable burst length */
#define ETH_DMACH_TX_CTRL_TXPBL_MASK (0x3f << ETH_DMACH_TX_CTRL_TXPBL_SHIFT)
# define ETH_DMACH_TX_CTRL_TXPBL(n) ((uint32_t)(n) << ETH_DMACH_TX_CTRL_TXPBL_SHIFT)
/* DMA channel n receive control */
@ -633,14 +633,17 @@
#define ETH_DMACH_RX_CTRL_RBSZ_SHIFT (3) /* Bits 3-14: Receive buffer size */
#define ETH_DMACH_RX_CTRL_RBSZ_MASK (0xfff << ETH_DMACH_RX_CTRL_RBSZ_SHIFT)
# define ETH_DMACH_RX_CTRL_RBSZ(n) ((uint32_t)(n) << ETH_DMACH_RX_CTRL_RBSZ_SHIFT)
#define ETH_DMACH_RX_CTRL_RxPBL_SHIFT (16) /* Bits 16-21: Receive programmable burst length */
#define ETH_DMACH_RX_CTRL_RxPBL_MASK (0x3f << ETH_DMACH_RX_CTRL_RxPBL_SHIFT)
# define ETH_DMACH_RX_CTRL_RxPBL(n) ((uint32_t)(n) << ETH_DMACH_RX_CTRL_RxPBL_SHIFT)
#define ETH_DMACH_RX_CTRL_RXPBL_SHIFT (16) /* Bits 16-21: Receive programmable burst length */
#define ETH_DMACH_RX_CTRL_RXPBL_MASK (0x3f << ETH_DMACH_RX_CTRL_RXPBL_SHIFT)
# define ETH_DMACH_RX_CTRL_RXPBL(n) ((uint32_t)(n) << ETH_DMACH_RX_CTRL_RXPBL_SHIFT)
#define ETH_DMACH_RX_CTRL_RPF (1 << 31) /* Bit 31: DMA Rx channel n packet flush */
/* DMA channel n Tx descriptor list address (32-bit, word-aligned address) */
/* DMA channel n Rx descriptor list address (32-bit, word-aligned address) */
/* DMA channel n Tx descriptor tail pointer (32-bit, word-aligned address) */
/* DMA channel n Rx descriptor tail pointer (32-bit, word-aligned address) */
/* DMA channel n Tx descriptor ring length */
@ -689,8 +692,11 @@
/* DMA descriptors ******************************************************************************************/
/* Receive descriptor (read-format) */
/* RDES0: 32-bit address */
/* RDES1: Reserved */
/* RDES2: 32-bit address */
/* RDES3: */
@ -701,6 +707,7 @@
#define ETH_RXDES3_OWN (1 << 31) /* Bit 31: Own bit */
/* Receive descriptor (writeback-format) */
/* RDES0: Reserved */
/* RDES1: */
@ -715,12 +722,12 @@
# define ETH_RXDES1_PT_AVUCP (5 << ETH_RXDES1_PT_SHIFT) /* AV untagged control packet */
# define ETH_RXDES1_PT_AVTDP (6 << ETH_RXDES1_PT_SHIFT) /* AV tagged data packet */
# define ETH_RXDES1_PT_AVTCP (7 << ETH_RXDES1_PT_SHIFT) /* AV tagged control packet */
#define ETH_RXDES1_IPHE (1 << 3) /* Bit 3: IP header error */
#define ETH_RXDES1_IPV4 (1 << 4) /* Bit 4: IPV4 header present */
#define ETH_RXDES1_IPV6 (1 << 5) /* Bit 5: IPv6 header present */
#define ETH_RXDES1_IPCB (1 << 6) /* Bit 6: IP checksum bypassed */
#define ETH_RXDES1_IPCE (1 << 7) /* Bit 7: IP payload error */
#define ETH_RXDES1_PMT_SHIFT (8) /* Bits 8-11: PTP message type */
#define ETH_RXDES1_IPHE (1 << 3) /* Bit 3: IP header error */
#define ETH_RXDES1_IPV4 (1 << 4) /* Bit 4: IPV4 header present */
#define ETH_RXDES1_IPV6 (1 << 5) /* Bit 5: IPv6 header present */
#define ETH_RXDES1_IPCB (1 << 6) /* Bit 6: IP checksum bypassed */
#define ETH_RXDES1_IPCE (1 << 7) /* Bit 7: IP payload error */
#define ETH_RXDES1_PMT_SHIFT (8) /* Bits 8-11: PTP message type */
#define ETH_RXDES1_PMT_MASK (15 << ETH_RXDES1_PMT_SHIFT)
# define ETH_RXDES1_PMT_NONE (0 << ETH_RXDES1_PMT_SHIFT) /* No PTP message received */
# define ETH_RXDES1_PMT_SYNC (1 << ETH_RXDES1_PMT_SHIFT) /* SYNC */
@ -734,11 +741,11 @@
# define ETH_RXDES1_PMT_MGMNT (9 << ETH_RXDES1_PMT_SHIFT) /* Management */
# define ETH_RXDES1_PMT_SIGNALING (10 << ETH_RXDES1_PMT_SHIFT) /* Signaling */
# define ETH_RXDES1_PMT_RESERVERD (15 << ETH_RXDES1_PMT_SHIFT) /* Reserved message type */
#define ETH_RXDES1_PFT (1 << 12) /* Bit 12: PTP packet type */
#define ETH_RXDES1_PV (1 << 13) /* Bit 13: PTP version */
#define ETH_RXDES1_TSA (1 << 14) /* Bit 14: Timestamp available */
#define ETH_RXDES1_TD (1 << 15) /* Bit 15: Timestamp dropped */
#define ETH_RXDES1_OPC_SHIFT (16) /* Bits 16-31: OAM sub-type code */
#define ETH_RXDES1_PFT (1 << 12) /* Bit 12: PTP packet type */
#define ETH_RXDES1_PV (1 << 13) /* Bit 13: PTP version */
#define ETH_RXDES1_TSA (1 << 14) /* Bit 14: Timestamp available */
#define ETH_RXDES1_TD (1 << 15) /* Bit 15: Timestamp dropped */
#define ETH_RXDES1_OPC_SHIFT (16) /* Bits 16-31: OAM sub-type code */
/* RXDES2: */
@ -761,21 +768,22 @@
# define ETH_RXDES3_LT_DVLAN (5 << ETH_RXDES3_LT_SHIFT) /* Packet is a type packet with double VLAN tag */
# define ETH_RXDES3_LT_CTRLPKT (6 << ETH_RXDES3_LT_SHIFT) /* Packet is a MAC control packet type */
# define ETH_RXDES3_LT_OAM (7 << ETH_RXDES3_LT_SHIFT) /* Packet is a OAM packet type */
#define ETH_RXDES3_DE (1 << 19) /* Bit 19: Dribble bit error */
#define ETH_RXDES3_RE (1 << 20) /* Bit 20: Receive error */
#define ETH_RXDES3_OE (1 << 21) /* Bit 21: Overflow error */
#define ETH_RXDES3_RWT (1 << 22) /* Bit 22: Receive watchdog timeout */
#define ETH_RXDES3_GP (1 << 23) /* Bit 23: Giant packet */
#define ETH_RXDES3_CE (1 << 24) /* Bit 24: CRC error */
#define ETH_RXDES3_RS0V (1 << 25) /* Bit 25: Receive status RDES0 valid */
#define ETH_RXDES3_RS1V (1 << 26) /* Bit 26: Receive status RDES1 valid */
#define ETH_RXDES3_RS2V (1 << 27) /* Bit 27: Receive status RDES2 valid */
#define ETH_RXDES3_LD (1 << 28) /* Bit 28: Last descriptor */
#define ETH_RXDES3_FD (1 << 29) /* Bit 29: First descriptor */
#define ETH_RXDES3_CTXT (1 << 30) /* Bit 30: Receive context descriptor */
/* Bit 31: Own bit (see read-format) */
#define ETH_RXDES3_DE (1 << 19) /* Bit 19: Dribble bit error */
#define ETH_RXDES3_RE (1 << 20) /* Bit 20: Receive error */
#define ETH_RXDES3_OE (1 << 21) /* Bit 21: Overflow error */
#define ETH_RXDES3_RWT (1 << 22) /* Bit 22: Receive watchdog timeout */
#define ETH_RXDES3_GP (1 << 23) /* Bit 23: Giant packet */
#define ETH_RXDES3_CE (1 << 24) /* Bit 24: CRC error */
#define ETH_RXDES3_RS0V (1 << 25) /* Bit 25: Receive status RDES0 valid */
#define ETH_RXDES3_RS1V (1 << 26) /* Bit 26: Receive status RDES1 valid */
#define ETH_RXDES3_RS2V (1 << 27) /* Bit 27: Receive status RDES2 valid */
#define ETH_RXDES3_LD (1 << 28) /* Bit 28: Last descriptor */
#define ETH_RXDES3_FD (1 << 29) /* Bit 29: First descriptor */
#define ETH_RXDES3_CTXT (1 << 30) /* Bit 30: Receive context descriptor */
/* Bit 31: Own bit (see read-format) */
/* Transmit normal descriptor (read-format) */
/* TDES0/1: 32-bit address */
/* TDES2: */
@ -800,7 +808,7 @@
# define ETH_TXDES3_CIC_IPHDR (1 << ETH_TXDES3_CIC_SHIFT) /* Only IP header checksum */
# define ETH_TXDES3_CIC_PAYLOAD (2 << ETH_TXDES3_CIC_SHIFT) /* IP header checksum and payload checksum */
# define ETH_TXDES3_CIC_ALL (3 << ETH_TXDES3_CIC_SHIFT) /* IP Header checksum, payload, and pseudo-header checksum */
#define ETH_TXDES3_SLOTNUM_SHIFT (19) /* Bits 19-22: Slot number control bits in AV mode */
#define ETH_TXDES3_SLOTNUM_SHIFT (19) /* Bits 19-22: Slot number control bits in AV mode */
#define ETH_TXDES3_SLOTNUM_MASK (15 << ETH_TXDES3_SLOTNUM_SHIFT)
#define ETH_TXDES3_CPC_SHIFT (26) /* Bits 26-27: CRC pad control */
#define ETH_TXDES3_CPC_MASK (3 << ETH_TXDES2_B1L_SHIFT)
@ -808,13 +816,15 @@
# define ETH_TXDES3_CPC_CRC (1 << ETH_TXDES2_B1L_SHIFT) /* CRC insertion (disable pad insertion) */
# define ETH_TXDES3_CPC_DISABLED (2 << ETH_TXDES2_B1L_SHIFT) /* Disable CRC insertion */
# define ETH_TXDES3_CPC_REPLACMENT (3 << ETH_TXDES2_B1L_SHIFT) /* CRC replacement */
#define ETH_TXDES3_LD (1 << 28) /* Bit 28: Last descriptor */
#define ETH_TXDES3_FD (1 << 29) /* Bit 29: First descriptor */
#define ETH_TXDES3_CTXT (1 << 30) /* Bit 30: Context type */
#define ETH_TXDES3_OWN (1 << 31) /* Bit 31: Own bit */
#define ETH_TXDES3_LD (1 << 28) /* Bit 28: Last descriptor */
#define ETH_TXDES3_FD (1 << 29) /* Bit 29: First descriptor */
#define ETH_TXDES3_CTXT (1 << 30) /* Bit 30: Context type */
#define ETH_TXDES3_OWN (1 << 31) /* Bit 31: Own bit */
/* Transmit normal descriptor (writeback-format) */
/* TDES0/1: 64-bit transmit packet timestamp */
/* TDES2: Reserved */
/* TDES3: */

110
arch/arm/src/lpc54xx/lpc54_ethernet.c
View file

@ -132,7 +132,9 @@
#define ETHWORK LPWORK
/* TX poll delay = 1 seconds. CLK_TCK is the number of clock ticks per second */
/* TX poll delay = 1 seconds.
* CLK_TCK is the number of clock ticks per second
*/
#define LPC54_WDDELAY (1*CLK_TCK)
@ -206,31 +208,31 @@
#if CONFIG_LPC54_ETH_BURSTLEN < 2
# define LPC54_BURSTLEN 1
# define LPC54_PBLx8 0
# define LPC54_PBLX8 0
#elif CONFIG_LPC54_ETH_BURSTLEN < 4
# define LPC54_BURSTLEN 2
# define LPC54_PBLx8 0
# define LPC54_PBLX8 0
#elif CONFIG_LPC54_ETH_BURSTLEN < 8
# define LPC54_BURSTLEN 4
# define LPC54_PBLx8 0
# define LPC54_PBLX8 0
#elif CONFIG_LPC54_ETH_BURSTLEN < 16
# define LPC54_BURSTLEN 8
# define LPC54_PBLx8 0
# define LPC54_PBLX8 0
#elif CONFIG_LPC54_ETH_BURSTLEN < 32
# define LPC54_BURSTLEN 16
# define LPC54_PBLx8 0
# define LPC54_PBLX8 0
#elif CONFIG_LPC54_ETH_BURSTLEN < 64
# define LPC54_BURSTLEN 32
# define LPC54_PBLx8 0
# define LPC54_PBLX8 0
#elif CONFIG_LPC54_ETH_BURSTLEN < 128
# define LPC54_BURSTLEN 8
# define LPC54_PBLx8 ETH_DMACH_CTRL_PBLx8
# define LPC54_PBLX8 ETH_DMACH_CTRL_PBLx8
#elif CONFIG_LPC54_ETH_BURSTLEN < 256
# define LPC54_BURSTLEN 16
# define LPC54_PBLx8 ETH_DMACH_CTRL_PBLx8
# define LPC54_PBLX8 ETH_DMACH_CTRL_PBLx8
#else
# define LPC54_BURSTLEN 32
# define LPC54_PBLx8 ETH_DMACH_CTRL_PBLx8
# define LPC54_PBLX8 ETH_DMACH_CTRL_PBLx8
#endif
#ifdef CONFIG_LPC54_ETH_DYNAMICMAP
@ -514,7 +516,7 @@ static uint32_t lpc54_getreg(uintptr_t addr)
{
/* Yes.. then show how many times the value repeated */
ninfo("[repeats %d more times]\n", count-3);
ninfo("[repeats %d more times]\n", count - 3);
}
/* Save the new address, value, and count */
@ -811,15 +813,15 @@ static int lpc54_eth_txpoll(struct net_driver_s *dev)
#ifdef CONFIG_LPC54_ETH_MULTIQUEUE
txring1 = &priv->eth_txring[1];
/* We cannot perform the Tx poll now if all of the Tx descriptors for
* both channels are in-use.
/* We cannot perform the Tx poll now if all of the Tx descriptors
* for both channels are in-use.
*/
if (txring0->tr_inuse >= txring0->tr_ndesc ||
txring1->tr_inuse >= txring1->tr_ndesc)
#else
/* We cannot continue the Tx poll now if all of the Tx descriptors for
* this channel 0 are in-use.
/* We cannot continue the Tx poll now if all of the Tx descriptors
* for this channel 0 are in-use.
*/
if (txring0->tr_inuse >= txring0->tr_ndesc)
@ -834,9 +836,9 @@ static int lpc54_eth_txpoll(struct net_driver_s *dev)
* to perform the poll.
*/
priv->eth_dev.d_buf = (uint8_t *)lpc54_pktbuf_alloc(priv);
if (priv->eth_dev.d_buf == NULL)
{
priv->eth_dev.d_buf = (uint8_t *)lpc54_pktbuf_alloc(priv);
if (priv->eth_dev.d_buf == NULL)
{
/* Stop the poll.. no more packet buffers */
return 1;
@ -885,7 +887,7 @@ static void lpc54_eth_reply(struct lpc54_ethdriver_s *priv)
/* Update the Ethernet header with the correct MAC address */
#ifdef CONFIG_LPC54_ETH_MULTIQUEUE
/* Check for an outgoing 802.1q VLAN packet */
/* Check for an outgoing 802.1q VLAN packet */
#warning Missing Logic
#endif
@ -944,9 +946,9 @@ static void lpc54_eth_reply(struct lpc54_ethdriver_s *priv)
static void lpc54_eth_rxdispatch(struct lpc54_ethdriver_s *priv)
{
#ifdef CONFIG_NET_PKT
/* When packet sockets are enabled, feed the frame into the packet tap */
/* When packet sockets are enabled, feed the frame into the tap */
pkt_input(&priv->eth_dev);
pkt_input(&priv->eth_dev);
#endif
/* We only accept IP packets of the configured type and ARP packets */
@ -957,7 +959,9 @@ static void lpc54_eth_rxdispatch(struct lpc54_ethdriver_s *priv)
ninfo("IPv4 packet\n");
NETDEV_RXIPV4(&priv->eth_dev);
/* Handle ARP on input, then dispatch IPv4 packet to the network layer */
/* Handle ARP on input,
* then dispatch IPv4 packet to the network layer
*/
arp_ipin(&priv->eth_dev);
ipv4_input(&priv->eth_dev);
@ -1012,7 +1016,7 @@ static void lpc54_eth_rxdispatch(struct lpc54_ethdriver_s *priv)
NETDEV_RXARP(&priv->eth_dev);
/* If the above function invocation resulted in data that should be
* sent out on the network, the field d_len will set to a value > 0.
* sent out on the network, d_len field will set to a value > 0.
*/
if (priv->eth_dev.d_len > 0)
@ -1150,7 +1154,8 @@ static int lpc54_eth_receive(struct lpc54_ethdriver_s *priv,
* this extra array of saved allocation addresses.
*/
priv->eth_dev.d_buf = (uint8_t *)(rxring->rr_buffers)[supply];
priv->eth_dev.d_buf = (uint8_t *)
(rxring->rr_buffers)[supply];
(rxring->rr_buffers)[supply] = NULL;
DEBUGASSERT(priv->eth_dev.d_buf != NULL);
@ -1185,7 +1190,8 @@ static int lpc54_eth_receive(struct lpc54_ethdriver_s *priv,
* owned by DMA.
*/
regval = ETH_RXDES3_BUF1V | ETH_RXDES3_IOC | ETH_RXDES3_OWN;
regval = ETH_RXDES3_BUF1V | ETH_RXDES3_IOC |
ETH_RXDES3_OWN;
#if LPC54_BUFFER_SIZE > LPC54_BUFFER_MAX
regval |= ETH_RXDES3_BUF2V;
#endif
@ -1227,7 +1233,9 @@ static int lpc54_eth_receive(struct lpc54_ethdriver_s *priv,
lpc54_putreg(ETH_DMACH_INT_RBU, LPC54_ETH_DMACH_STAT(chan));
/* Writing to the tail pointer register will restart the Rx processing */
/* Writing to the tail pointer register
* will restart the Rx processing
*/
regval = lpc54_getreg(regaddr);
lpc54_putreg(regval, regaddr);
@ -1415,7 +1423,9 @@ static void lpc54_eth_channel_work(struct lpc54_ethdriver_s *priv,
lpc54_putreg(ETH_DMACH_INT_RI | ETH_DMACH_INT_NI, regaddr);
pending &= ~(ETH_DMACH_INT_RI | ETH_DMACH_INT_NI);
/* Loop until all available Rx packets in the ring have been processed */
/* Loop until all available Rx packets
* in the ring have been processed
*/
for (; ; )
{
@ -1901,7 +1911,8 @@ static void lpc54_eth_poll_expiry(int argc, wdparm_t arg, ...)
static int lpc54_eth_ifup(struct net_driver_s *dev)
{
struct lpc54_ethdriver_s *priv = (struct lpc54_ethdriver_s *)dev->d_private;
struct lpc54_ethdriver_s *priv =
(struct lpc54_ethdriver_s *)dev->d_private;
uint8_t *mptr;
uintptr_t base;
uint32_t regval;
@ -1930,6 +1941,7 @@ static int lpc54_eth_ifup(struct net_driver_s *dev)
}
/* Initialize Ethernet DMA ************************************************/
/* Reset DMA. Resets the logic and all internal registers of the OMA, MTL,
* and MAC. This bit is automatically cleared after the reset operation
* is complete in all Ethernet Block clock domains.
@ -1950,16 +1962,16 @@ static int lpc54_eth_ifup(struct net_driver_s *dev)
for (i = 0; i < LPC54_NRINGS; i++)
{
base = LPC54_ETH_DMACH_BASE(i);
lpc54_putreg(LPC54_PBLx8, base + LPC54_ETH_DMACH_CTRL_OFFSET);
lpc54_putreg(LPC54_PBLX8, base + LPC54_ETH_DMACH_CTRL_OFFSET);
regval = lpc54_getreg(base + LPC54_ETH_DMACH_TX_CTRL_OFFSET);
regval &= ~ETH_DMACH_TX_CTRL_TxPBL_MASK;
regval |= ETH_DMACH_TX_CTRL_TxPBL(LPC54_BURSTLEN);
regval &= ~ETH_DMACH_TX_CTRL_TXPBL_MASK;
regval |= ETH_DMACH_TX_CTRL_TXPBL(LPC54_BURSTLEN);
lpc54_putreg(regval, base + LPC54_ETH_DMACH_TX_CTRL_OFFSET);
regval = lpc54_getreg(base + LPC54_ETH_DMACH_RX_CTRL_OFFSET);
regval &= ~ETH_DMACH_RX_CTRL_RxPBL_MASK;
regval |= ETH_DMACH_RX_CTRL_RxPBL(LPC54_BURSTLEN);
regval &= ~ETH_DMACH_RX_CTRL_RXPBL_MASK;
regval |= ETH_DMACH_RX_CTRL_RXPBL(LPC54_BURSTLEN);
lpc54_putreg(regval, base + LPC54_ETH_DMACH_RX_CTRL_OFFSET);
}
@ -2034,6 +2046,7 @@ static int lpc54_eth_ifup(struct net_driver_s *dev)
#endif
/* Initialize the Ethernet MAC ********************************************/
/* Instantiate the MAC address that application logic should have set in
* the device structure.
*
@ -2077,7 +2090,7 @@ static int lpc54_eth_ifup(struct net_driver_s *dev)
lpc54_putreg(regval, LPC54_ETH_MAC_TX_FLOW_CTRL_Q1);
#endif
/* Set the 1uS tick counter*/
/* Set the 1uS tick counter */
regval = ETH_MAC_1US_TIC_COUNTR(BOARD_MAIN_CLK / USEC_PER_SEC);
lpc54_putreg(regval, LPC54_ETH_MAC_1US_TIC_COUNTR);
@ -2185,7 +2198,8 @@ static int lpc54_eth_ifup(struct net_driver_s *dev)
static int lpc54_eth_ifdown(struct net_driver_s *dev)
{
struct lpc54_ethdriver_s *priv = (struct lpc54_ethdriver_s *)dev->d_private;
struct lpc54_ethdriver_s *priv =
(struct lpc54_ethdriver_s *)dev->d_private;
irqstate_t flags;
uint32_t regval;
int ret;
@ -2304,7 +2318,8 @@ static void lpc54_eth_txavail_work(void *arg)
static int lpc54_eth_txavail(struct net_driver_s *dev)
{
struct lpc54_ethdriver_s *priv = (struct lpc54_ethdriver_s *)dev->d_private;
struct lpc54_ethdriver_s *priv =
(struct lpc54_ethdriver_s *)dev->d_private;
/* Is our single work structure available? It may not be if there are
* pending interrupt actions and we will have to ignore the Tx
@ -2315,7 +2330,8 @@ static int lpc54_eth_txavail(struct net_driver_s *dev)
{
/* Schedule to serialize the poll on the worker thread. */
work_queue(ETHWORK, &priv->eth_pollwork, lpc54_eth_txavail_work, priv, 0);
work_queue(ETHWORK, &priv->eth_pollwork,
lpc54_eth_txavail_work, priv, 0);
}
return OK;
@ -2353,8 +2369,8 @@ static int lpc54_eth_addmac(struct net_driver_s *dev, const uint8_t *mac)
* Name: lpc54_eth_rmmac
*
* Description:
* NuttX Callback: Remove the specified MAC address from the hardware multicast
* address filtering
* NuttX Callback: Remove the specified MAC address from the hardware
* multicast address filtering
*
* Input Parameters:
* dev - Reference to the NuttX driver state structure
@ -2401,7 +2417,8 @@ static int lpc54_eth_ioctl(struct net_driver_s *dev, int cmd,
unsigned long arg)
{
#ifdef CONFIG_NETDEV_PHY_IOCTL
struct lpc54_ethdriver_s *priv = (struct lpc54_ethdriver_s *)dev->d_private;
struct lpc54_ethdriver_s *priv =
(struct lpc54_ethdriver_s *)dev->d_private;
#endif
int ret;
@ -2412,7 +2429,8 @@ static int lpc54_eth_ioctl(struct net_driver_s *dev, int cmd,
#ifdef CONFIG_NETDEV_PHY_IOCTL
case SIOCGMIIPHY: /* Get MII PHY address */
{
struct mii_ioctl_data_s *req = (struct mii_ioctl_data_s *)((uintptr_t)arg);
struct mii_ioctl_data_s *req =
(struct mii_ioctl_data_s *)((uintptr_t)arg);
req->phy_id = CONFIG_LPC54_ETH_PHYADDR;
ret = OK;
}
@ -2420,7 +2438,8 @@ static int lpc54_eth_ioctl(struct net_driver_s *dev, int cmd,
case SIOCGMIIREG: /* Get register from MII PHY */
{
struct mii_ioctl_data_s *req = (struct mii_ioctl_data_s *)((uintptr_t)arg);
struct mii_ioctl_data_s *req =
(struct mii_ioctl_data_s *)((uintptr_t)arg);
req->val_out = lpc54_phy_read(priv, req->reg_num);
ret = OK
}
@ -2428,7 +2447,8 @@ static int lpc54_eth_ioctl(struct net_driver_s *dev, int cmd,
case SIOCSMIIREG: /* Set register in MII PHY */
{
struct mii_ioctl_data_s *req = (struct mii_ioctl_data_s *)((uintptr_t)arg);
struct mii_ioctl_data_s *req =
(struct mii_ioctl_data_s *)((uintptr_t)arg);
lpc54_phy_write(priv, req->reg_num, req->val_in);
ret = OK
}
@ -2642,7 +2662,7 @@ static void lpc54_rxring_initialize(struct lpc54_ethdriver_s *priv,
rxdesc->buffer2 = 0;
#endif
/* Buffer1 (and maybe 2) valid, interrupt on completion, owned by DMA. */
/* Buffer1 and maybe 2 valid, interrupt on completion, owned by DMA. */
rxdesc->ctrl = regval;
}
@ -2897,7 +2917,6 @@ static int lpc54_phy_autonegotiate(struct lpc54_ethdriver_s *priv)
}
phyval = lpc54_phy_read(priv, MII_LAN8720_SCSR);
}
while ((phyval & MII_LAN8720_SPSCR_ANEGDONE) == 0);
#else
@ -3076,6 +3095,7 @@ int arm_netinitialize(int intf)
DEBUGASSERT(priv->eth_txpoll != NULL && priv->eth_txtimeout != NULL);
/* Configure GPIO pins to support Ethernet */
/* Common MIIM interface */
lpc54_gpio_config(GPIO_ENET_MDIO); /* Ethernet MIIM data input and output */

14
arch/arm/src/lpc54xx/lpc54_i2c_master.c
View file

@ -308,8 +308,8 @@ static void lpc54_i2c_setfrequency(struct lpc54_i2cdev_s *priv,
if (err == 0 || divider >= 0x10000)
{
/* Break out of the loop early ifeither exact value was found or
* the divider is at its maximum value.
/* Break out of the loop early ifeither exact value was found
* or the divider is at its maximum value.
*/
break;
@ -472,8 +472,9 @@ static bool lpc54_i2c_nextmsg(struct lpc54_i2cdev_s *priv)
}
else
{
/* That was the last message... we are done. */
/* Cancel any timeout */
/* That was the last message... we are done.
* Cancel any timeout
*/
wd_cancel(priv->timeout);
@ -792,7 +793,7 @@ static int lpc54_i2c_transfer(FAR struct i2c_master_s *dev,
return ret;
}
/************************************************************************************
/****************************************************************************
* Name: lpc54_i2c_reset
*
* Description:
@ -804,7 +805,7 @@ static int lpc54_i2c_transfer(FAR struct i2c_master_s *dev,
* Returned Value:
* Zero (OK) on success; a negated errno value on failure.
*
************************************************************************************/
****************************************************************************/
#ifdef CONFIG_I2C_RESET
static int lpc54_i2c_reset(FAR struct i2c_master_s * dev)
@ -837,6 +838,7 @@ struct i2c_master_s *lpc54_i2cbus_initialize(int port)
flags = enter_critical_section();
/* Configure the requestin I2C peripheral */
/* NOTE: The basic FLEXCOMM initialization was performed in
* lpc54_lowputc.c.
*/

19
arch/arm/src/s32k1xx/s32k1xx_enet.c
View file

@ -250,7 +250,7 @@
#define CRITICAL_ERROR (ENET_INT_UN | ENET_INT_RL | ENET_INT_EBERR )
/* This is a helper pointer for accessing the contents of the Ethernet header */
/* This is a helper pointer for accessing the contents of Ethernet header */
#define BUF ((struct eth_hdr_s *)priv->dev.d_buf)
@ -646,8 +646,8 @@ static int s32k1xx_txpoll(struct net_driver_s *dev)
/* Send the packet */
s32k1xx_transmit(priv);
priv->dev.d_buf =
(uint8_t *)s32k1xx_swap32((uint32_t)priv->txdesc[priv->txhead].data);
priv->dev.d_buf = (uint8_t *)
s32k1xx_swap32((uint32_t)priv->txdesc[priv->txhead].data);
/* Check if there is room in the device to hold another packet. If
* not, return a non-zero value to terminate the poll.
@ -692,7 +692,7 @@ static inline void s32k1xx_dispatch(FAR struct s32k1xx_driver_s *priv)
NETDEV_RXPACKETS(&priv->dev);
#ifdef CONFIG_NET_PKT
/* When packet sockets are enabled, feed the frame into the packet tap */
/* When packet sockets are enabled, feed the frame into the tap */
pkt_input(&priv->dev);
#endif
@ -713,7 +713,7 @@ static inline void s32k1xx_dispatch(FAR struct s32k1xx_driver_s *priv)
ipv4_input(&priv->dev);
/* If the above function invocation resulted in data that should be
* sent out on the network, the field d_len will set to a value > 0.
* sent out on the network, d_len field will set to a value > 0.
*/
if (priv->dev.d_len > 0)
@ -753,7 +753,7 @@ static inline void s32k1xx_dispatch(FAR struct s32k1xx_driver_s *priv)
ipv6_input(&priv->dev);
/* If the above function invocation resulted in data that should be
* sent out on the network, the field d_len will set to a value > 0.
* sent out on the network, d_len field will set to a value > 0.
*/
if (priv->dev.d_len > 0)
@ -873,8 +873,8 @@ static void s32k1xx_receive(FAR struct s32k1xx_driver_s *priv)
* queue is not full.
*/
priv->dev.d_buf =
(uint8_t *)s32k1xx_swap32((uint32_t)priv->txdesc[priv->txhead].data);
priv->dev.d_buf = (uint8_t *)
s32k1xx_swap32((uint32_t)priv->txdesc[priv->txhead].data);
rxdesc->status1 |= RXDESC_E;
/* Update the index to the next descriptor */
@ -2404,7 +2404,8 @@ static void s32k1xx_initbuffers(struct s32k1xx_driver_s *priv)
/* Get an aligned RX descriptor (array) address */
addr += CONFIG_S32K1XX_ENET_NTXBUFFERS * sizeof(struct enet_desc_s);
addr += CONFIG_S32K1XX_ENET_NTXBUFFERS *
sizeof(struct enet_desc_s);
priv->rxdesc = (struct enet_desc_s *)addr;
/* Get the beginning of the first aligned buffer */

144
arch/arm/src/sam34/sam_emac.c
View file

@ -91,6 +91,7 @@
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Configuration ************************************************************/
/* If processing is not done at the interrupt level, then work queue support
@ -238,8 +239,9 @@
#endif
/* Timing *******************************************************************/
/* TX poll delay = 1 seconds. CLK_TCK is the number of clock ticks per
* second
/* TX poll delay = 1 seconds.
* CLK_TCK is the number of clock ticks per second
*/
#define SAM_WDDELAY (1*CLK_TCK)
@ -253,6 +255,7 @@
#define PHY_RETRY_MAX 1000000
/* Helpers ******************************************************************/
/* This is a helper pointer for accessing the contents of the EMAC
* header
*/
@ -263,7 +266,7 @@
* Private Types
****************************************************************************/
/* The sam_emac_s encapsulates all state information for the EMAC peripheral */
/* The sam_emac_s encapsulates all state information for EMAC peripheral */
struct sam_emac_s
{
@ -320,6 +323,7 @@ static uint8_t g_pktbuf[MAX_NETDEV_PKTSIZE + CONFIG_NET_GUARDSIZE];
#ifdef CONFIG_SAM34_EMAC_PREALLOCATE
/* Preallocated data */
/* TX descriptors list */
static struct emac_txdesc_s g_txdesc[CONFIG_SAM34_EMAC_NTXBUFFERS]
@ -332,9 +336,9 @@ static struct emac_rxdesc_s g_rxdesc[CONFIG_SAM34_EMAC_NRXBUFFERS]
/* Transmit Buffers
*
* Section 3.6 of AMBA 2.0 spec states that burst should not cross 1K Boundaries.
* Receive buffer manager writes are burst of 2 words => 3 lsb bits of the address
* shall be set to 0
* Section 3.6 of AMBA 2.0 spec states that burst should not cross 1K
* Boundaries. Receive buffer manager writes are burst of 2 words => 3
* lsb bits of the address shall be set to 0
*/
static uint8_t g_txbuffer[CONFIG_SAM34_EMAC_NTXBUFFERS * EMAC_TX_UNITSIZE];
@ -350,13 +354,15 @@ static uint8_t g_rxbuffer[CONFIG_SAM34_EMAC_NRXBUFFERS * EMAC_RX_UNITSIZE]
/****************************************************************************
* Private Function Prototypes
****************************************************************************/
/* Register operations ******************************************************/
#if defined(CONFIG_SAM34_EMAC_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES)
static bool sam_checkreg(struct sam_emac_s *priv, bool wr,
uint32_t regval, uintptr_t address);
static uint32_t sam_getreg(struct sam_emac_s *priv, uintptr_t addr);
static void sam_putreg(struct sam_emac_s *priv, uintptr_t addr, uint32_t val);
static void sam_putreg(struct sam_emac_s *priv,
uintptr_t addr, uint32_t val);
#else
# define sam_getreg(priv,addr) getreg32(addr)
# define sam_putreg(priv,addr,val) putreg32(val,addr)
@ -534,8 +540,8 @@ static uint32_t sam_getreg(struct sam_emac_s *priv, uintptr_t address)
****************************************************************************/
#ifdef CONFIG_SAM34_EMAC_REGDEBUG
static void sam_putreg(struct sam_emac_s *priv, uintptr_t address,
uint32_t regval)
static void sam_putreg(struct sam_emac_s *priv,
uintptr_t address, uint32_t regval)
{
if (sam_checkreg(priv, true, regval, address))
{
@ -592,7 +598,7 @@ static uint16_t sam_txfree(struct sam_emac_s *priv)
* the configured size minus 1.
*/
return (CONFIG_SAM34_EMAC_NTXBUFFERS-1) - sam_txinuse(priv);
return (CONFIG_SAM34_EMAC_NTXBUFFERS - 1) - sam_txinuse(priv);
}
/****************************************************************************
@ -784,7 +790,7 @@ static int sam_transmit(struct sam_emac_s *priv)
/* Update TX descriptor status. */
status = dev->d_len | EMACTXD_STA_LAST;
if (priv->txhead == CONFIG_SAM34_EMAC_NTXBUFFERS-1)
if (priv->txhead == CONFIG_SAM34_EMAC_NTXBUFFERS - 1)
{
status |= EMACTXD_STA_WRAP;
}
@ -837,8 +843,9 @@ static int sam_transmit(struct sam_emac_s *priv)
* Function: sam_txpoll
*
* Description:
* The transmitter is available, check if the network has any outgoing packets ready
* to send. This is a callback from devif_poll(). devif_poll() may be called:
* The transmitter is available, check if the network has any outgoing
* packets ready to send. This is a callback from devif_poll().
* devif_poll() may be called:
*
* 1. When the preceding TX packet send is complete,
* 2. When the preceding TX packet send timesout and the interface is reset
@ -910,8 +917,8 @@ static int sam_txpoll(struct net_driver_s *dev)
}
}
/* If zero is returned, the polling will continue until all connections have
* been examined.
/* If zero is returned, the polling will continue until all connections
* have been examined.
*/
return 0;
@ -950,7 +957,9 @@ static void sam_dopoll(struct sam_emac_s *priv)
if (sam_txfree(priv) > 0)
{
/* If we have the descriptor, then poll the network for new XMIT data. */
/* If we have the descriptor,
* then poll the network for new XMIT data.
*/
devif_poll(dev, sam_txpoll);
}
@ -1135,7 +1144,8 @@ static int sam_recvframe(struct sam_emac_s *priv)
if (pktlen < dev->d_len)
{
nerr("ERROR: Buffer size %d; frame size %d\n", dev->d_len, pktlen);
nerr("ERROR: Buffer size %d; frame size %d\n",
dev->d_len, pktlen);
return -E2BIG;
}
@ -1143,7 +1153,9 @@ static int sam_recvframe(struct sam_emac_s *priv)
}
}
/* We have not encount the SOF yet... discard this fragment and keep looking */
/* We have not encount the SOF yet...
* discard this fragment and keep looking
*/
else
{
@ -1214,8 +1226,8 @@ static void sam_receive(struct sam_emac_s *priv)
{
sam_dumppacket("Received packet", dev->d_buf, dev->d_len);
/* Check if the packet is a valid size for the network buffer configuration
* (this should not happen)
/* Check if the packet is a valid size for the network buffer
* configuration (this should not happen)
*/
if (dev->d_len > CONFIG_NET_ETH_PKTSIZE)
@ -1225,9 +1237,9 @@ static void sam_receive(struct sam_emac_s *priv)
}
#ifdef CONFIG_NET_PKT
/* When packet sockets are enabled, feed the frame into the packet tap */
/* When packet sockets are enabled, feed the frame into the tap */
pkt_input(&priv->dev);
pkt_input(&priv->dev);
#endif
/* We only accept IP packets of the configured type and ARP packets */
@ -1245,7 +1257,7 @@ static void sam_receive(struct sam_emac_s *priv)
ipv4_input(&priv->dev);
/* If the above function invocation resulted in data that should be
* sent out on the network, the field d_len will set to a value > 0.
* sent out on the network, d_len field will set to a value > 0.
*/
if (priv->dev.d_len > 0)
@ -1282,7 +1294,7 @@ static void sam_receive(struct sam_emac_s *priv)
ipv6_input(&priv->dev);
/* If the above function invocation resulted in data that should be
* sent out on the network, the field d_len will set to a value > 0.
* sent out on the network, d_len field will set to a value > 0.
*/
if (priv->dev.d_len > 0)
@ -1319,7 +1331,7 @@ static void sam_receive(struct sam_emac_s *priv)
arp_arpin(&priv->dev);
/* If the above function invocation resulted in data that should be
* sent out on the network, the field d_len will set to a value > 0.
* sent out on the network, d_len field will set to a value > 0.
*/
if (priv->dev.d_len > 0)
@ -1377,14 +1389,15 @@ static void sam_txdone(struct sam_emac_s *priv)
/* Yes.. the descriptor is still in use. However, I have seen a
* case (only repeatable on start-up) where the USED bit is never
* set. Yikes! If we have encountered the first still busy
* descriptor, then we should also have TQBD equal to the descriptor
* address. If it is not, then treat is as used anyway.
* descriptor, then we should also have TQBD equal to the
* descriptor address. If it is not, then treat is as used anyway.
*/
#if 0 /* The issue does not exist in the current configuration, but may return */
#warning REVISIT
if (priv->txtail == 0 &&
sam_physramaddr((uintptr_t)txdesc) != sam_getreg(priv, SAM_EMAC_TBQB))
sam_physramaddr((uintptr_t)txdesc) !=
sam_getreg(priv, SAM_EMAC_TBQB))
{
txdesc->status = (uint32_t)EMACTXD_STA_USED;
}
@ -1461,12 +1474,12 @@ static void sam_interrupt_work(FAR void *arg)
ninfo("isr: %08x pending: %08x\n", isr, pending);
/* Check for the completion of a transmission. This should be done before
* checking for received data (because receiving can cause another transmission
* before we had a chance to handle the last one).
* checking for received data (because receiving can cause another
* transmission before we had a chance to handle the last one).
*
* ISR:TCOMP is set when a frame has been transmitted. Cleared on read.
* TSR:TXCOMP is set when a frame has been transmitted. Cleared by writing a
* one to this bit.
* TSR:TXCOMP is set when a frame has been transmitted. Cleared by writing
* a one to this bit.
*/
if ((pending & EMAC_INT_TCOMP) != 0 || (tsr & EMAC_TSR_TXCOMP) != 0)
@ -1503,7 +1516,8 @@ static void sam_interrupt_work(FAR void *arg)
if ((tsr & EMAC_TSR_TFC) != 0)
{
nerr("ERROR: Transmit Frame Corruption due to AHB error: %08x\n", tsr);
nerr("ERROR: Transmit Frame Corruption due to AHB error: %08x\n",
tsr);
clrbits |= EMAC_TSR_TFC;
}
@ -1649,8 +1663,8 @@ static int sam_emac_interrupt(int irq, void *context, FAR void *arg)
*
* ISR:TCOMP is set when a frame has been transmitted. Cleared on read (so
* we cannot read it here).
* TSR:TXCOMP is set when a frame has been transmitted. Cleared by writing a
* one to this bit.
* TSR:TXCOMP is set when a frame has been transmitted. Cleared by writing
* a one to this bit.
*/
tsr = sam_getreg(priv, SAM_EMAC_TSR);
@ -2042,7 +2056,8 @@ static unsigned int sam_hashindx(const uint8_t *mac)
unsigned int ndx;
/* Isolate: mac[0]
* ... 05 04 03 02 01 00] */
* ... 05 04 03 02 01 00]
*/
ndx = mac[0];
@ -2213,8 +2228,8 @@ static int sam_addmac(struct net_driver_s *dev, const uint8_t *mac)
* Function: sam_rmmac
*
* Description:
* NuttX Callback: Remove the specified MAC address from the hardware multicast
* address filtering
* NuttX Callback: Remove the specified MAC address from the hardware
* multicast address filtering
*
* Input Parameters:
* dev - Reference to the NuttX driver state structure
@ -2311,9 +2326,9 @@ static int sam_rmmac(struct net_driver_s *dev, const uint8_t *mac)
* specified using the req->reg_no struct field and then write its output
* to the req->val_out field.
*
* When called with SIOCSMIIREG it will write to a register of the PHY that
* is specified using the req->reg_no struct field and use req->val_in as
* its input.
* When called with SIOCSMIIREG it will write to a register of the PHY
* that is specified using the req->reg_no struct field and use req->
* val_in as its input.
*
* Input Parameters:
* dev - Ethernet device structure
@ -2340,7 +2355,8 @@ static int sam_ioctl(struct net_driver_s *dev, int cmd, unsigned long arg)
#ifdef CONFIG_ARCH_PHY_INTERRUPT
case SIOCMIINOTIFY: /* Set up for PHY event notifications */
{
struct mii_ioctl_notify_s *req = (struct mii_ioctl_notify_s *)((uintptr_t)arg);
struct mii_ioctl_notify_s *req =
(struct mii_ioctl_notify_s *)((uintptr_t)arg);
ret = phy_notify_subscribe(dev->d_ifname, req->pid, &req->event);
if (ret == OK)
@ -2355,7 +2371,8 @@ static int sam_ioctl(struct net_driver_s *dev, int cmd, unsigned long arg)
case SIOCGMIIPHY: /* Get MII PHY address */
{
struct mii_ioctl_data_s *req = (struct mii_ioctl_data_s *)((uintptr_t)arg);
struct mii_ioctl_data_s *req =
(struct mii_ioctl_data_s *)((uintptr_t)arg);
req->phy_id = priv->phyaddr;
ret = OK;
}
@ -2363,7 +2380,8 @@ static int sam_ioctl(struct net_driver_s *dev, int cmd, unsigned long arg)
case SIOCGMIIREG: /* Get register from MII PHY */
{
struct mii_ioctl_data_s *req = (struct mii_ioctl_data_s *)((uintptr_t)arg);
struct mii_ioctl_data_s *req =
(struct mii_ioctl_data_s *)((uintptr_t)arg);
uint32_t regval;
/* Enable management port */
@ -2383,7 +2401,8 @@ static int sam_ioctl(struct net_driver_s *dev, int cmd, unsigned long arg)
case SIOCSMIIREG: /* Set register in MII PHY */
{
struct mii_ioctl_data_s *req = (struct mii_ioctl_data_s *)((uintptr_t)arg);
struct mii_ioctl_data_s *req =
(struct mii_ioctl_data_s *)((uintptr_t)arg);
uint32_t regval;
/* Enable management port */
@ -3042,6 +3061,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
sam_putreg(priv, SAM_EMAC_UR, regval);
errout:
/* Disable management port */
regval = sam_getreg(priv, SAM_EMAC_NCR);
@ -3138,6 +3158,7 @@ static bool sam_linkup(struct sam_emac_s *priv)
linkup = true;
errout:
/* Disable management port */
regval = sam_getreg(priv, SAM_EMAC_NCR);
@ -3171,13 +3192,13 @@ static int sam_phyinit(struct sam_emac_s *priv)
regval = sam_getreg(priv, SAM_EMAC_NCFGR);
regval &= ~EMAC_NCFGR_CLK_MASK;
#if BOARD_MCK_FREQUENCY > (160*1000*1000)
#if BOARD_MCK_FREQUENCY > (160 * 1000 * 1000)
# error Supported MCK frequency
#elif BOARD_MCK_FREQUENCY > (80*1000*1000)
#elif BOARD_MCK_FREQUENCY > (80 * 1000 * 1000)
regval |= EMAC_NCFGR_CLK_DIV64; /* MCK divided by 64 (MCK up to 160 MHz) */
#elif BOARD_MCK_FREQUENCY > (40*1000*1000)
#elif BOARD_MCK_FREQUENCY > (40 * 1000 * 1000)
regval |= EMAC_NCFGR_CLK_DIV32; /* MCK divided by 32 (MCK up to 80 MHz) */
#elif BOARD_MCK_FREQUENCY > (20*1000*1000)
#elif BOARD_MCK_FREQUENCY > (20 * 1000 * 1000)
regval |= EMAC_NCFGR_CLK_DIV16; /* MCK divided by 16 (MCK up to 40 MHz) */
#else
regval |= EMAC_NCFGR_CLK_DIV8; /* MCK divided by 8 (MCK up to 20 MHz) */
@ -3229,7 +3250,9 @@ static inline void sam_ethgpioconfig(struct sam_emac_s *priv)
sam_configgpio(GPIO_EMAC_TX1); /* Transmit data TXD1 */
sam_configgpio(GPIO_EMAC_TX2); /* Transmit data TXD2 */
sam_configgpio(GPIO_EMAC_TX3); /* Transmit data TXD3 */
//sam_configgpio(GPIO_EMAC_TXER); /* Transmit Coding Error */
#if 0
sam_configgpio(GPIO_EMAC_TXER); /* Transmit Coding Error */
#endif
sam_configgpio(GPIO_EMAC_RXCK); /* Receive Clock */
sam_configgpio(GPIO_EMAC_RXDV); /* Receive Data Valid */
sam_configgpio(GPIO_EMAC_RX0); /* Receive data RXD0 */
@ -3282,7 +3305,9 @@ static void sam_txreset(struct sam_emac_s *priv)
{
bufaddr = (uint32_t)(&(txbuffer[ndx * EMAC_TX_UNITSIZE]));
/* Set the buffer address and mark the descriptor as in used by firmware */
/* Set the buffer address and mark the descriptor
* as in used by firmware
*/
txdesc[ndx].addr = bufaddr;
txdesc[ndx].status = EMACTXD_STA_USED;
@ -3437,9 +3462,12 @@ static void sam_macaddress(struct sam_emac_s *priv)
ninfo("%s MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
dev->d_ifname,
dev->d_mac.ether.ether_addr_octet[0], dev->d_mac.ether.ether_addr_octet[1],
dev->d_mac.ether.ether_addr_octet[2], dev->d_mac.ether.ether_addr_octet[3],
dev->d_mac.ether.ether_addr_octet[4], dev->d_mac.ether.ether_addr_octet[5]);
dev->d_mac.ether.ether_addr_octet[0],
dev->d_mac.ether.ether_addr_octet[1],
dev->d_mac.ether.ether_addr_octet[2],
dev->d_mac.ether.ether_addr_octet[3],
dev->d_mac.ether.ether_addr_octet[4],
dev->d_mac.ether.ether_addr_octet[5]);
/* Set the MAC address */
@ -3608,7 +3636,7 @@ static int sam_emac_configure(struct sam_emac_s *priv)
/* Setup the interrupts for TX events, RX events, and error events */
regval = (EMAC_INT_RCOMP | EMAC_INT_RXUBR | EMAC_INT_TUR | EMAC_INT_RLEX |
EMAC_INT_TFC | EMAC_INT_TCOMP | EMAC_INT_ROVR | EMAC_INT_HRESP |
EMAC_INT_TFC | EMAC_INT_TCOMP | EMAC_INT_ROVR | EMAC_INT_HRESP |
EMAC_INT_PFNZ | EMAC_INT_PTZ);
sam_putreg(priv, SAM_EMAC_IER, regval);
return OK;
@ -3692,7 +3720,8 @@ void arm_netinitialize(void)
ret = irq_attach(SAM_IRQ_EMAC, sam_emac_interrupt, NULL);
if (ret < 0)
{
nerr("ERROR: Failed to attach the handler to the IRQ%d\n", SAM_IRQ_EMAC);
nerr("ERROR: Failed to attach the handler to the IRQ%d\n",
SAM_IRQ_EMAC);
goto errout_with_buffers;
}
@ -3705,7 +3734,8 @@ void arm_netinitialize(void)
ret = sam_ifdown(&priv->dev);
if (ret < 0)
{
nerr("ERROR: Failed to put the interface in the down state: %d\n", ret);
nerr("ERROR: Failed to put the interface in the down state: %d\n",
ret);
goto errout_with_buffers;
}

154
arch/arm/src/sama5/sam_emaca.c
View file

@ -92,6 +92,7 @@
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Configuration ************************************************************/
/* If processing is not done at the interrupt level, then work queue support
@ -242,8 +243,9 @@
#endif
/* Timing *******************************************************************/
/* TX poll delay = 1 seconds. CLK_TCK is the number of clock ticks per
* second
/* TX poll delay = 1 seconds.
* CLK_TCK is the number of clock ticks per second
*/
#define SAM_WDDELAY (1*CLK_TCK)
@ -257,6 +259,7 @@
#define PHY_RETRY_MAX 1000000
/* Helpers ******************************************************************/
/* This is a helper pointer for accessing the contents of the EMAC
* header
*/
@ -267,7 +270,7 @@
* Private Types
****************************************************************************/
/* The sam_emac_s encapsulates all state information for the EMAC peripheral */
/* The sam_emac_s encapsulates all state information for EMAC peripheral */
struct sam_emac_s
{
@ -324,6 +327,7 @@ static uint8_t g_pktbuf[MAX_NETDEV_PKTSIZE + CONFIG_NET_GUARDSIZE];
#ifdef CONFIG_SAMA5_EMACA_PREALLOCATE
/* Preallocated data */
/* TX descriptors list */
static struct emac_txdesc_s g_txdesc[CONFIG_SAMA5_EMAC_NTXBUFFERS]
@ -336,9 +340,9 @@ static struct emac_rxdesc_s g_rxdesc[CONFIG_SAMA5_EMAC_NRXBUFFERS]
/* Transmit Buffers
*
* Section 3.6 of AMBA 2.0 spec states that burst should not cross 1K Boundaries.
* Receive buffer manager writes are burst of 2 words => 3 lsb bits of the address
* shall be set to 0
* Section 3.6 of AMBA 2.0 spec states that burst should not cross 1K
* Boundaries. Receive buffer manager writes are burst of 2 words => 3
* lsb bits of the address shall be set to 0
*/
static uint8_t g_txbuffer[CONFIG_SAMA5_EMAC_NTXBUFFERS * EMAC_TX_UNITSIZE];
@ -354,13 +358,15 @@ static uint8_t g_rxbuffer[CONFIG_SAMA5_EMAC_NRXBUFFERS * EMAC_RX_UNITSIZE]
/****************************************************************************
* Private Function Prototypes
****************************************************************************/
/* Register operations ******************************************************/
#ifdef CONFIG_SAMA5_EMACA_REGDEBUG
static bool sam_checkreg(struct sam_emac_s *priv, bool wr,
uint32_t regval, uintptr_t address);
static uint32_t sam_getreg(struct sam_emac_s *priv, uintptr_t addr);
static void sam_putreg(struct sam_emac_s *priv, uintptr_t addr, uint32_t val);
static void sam_putreg(struct sam_emac_s *priv,
uintptr_t addr, uint32_t val);
#else
# define sam_getreg(priv,addr) getreg32(addr)
# define sam_putreg(priv,addr,val) putreg32(val,addr)
@ -452,8 +458,8 @@ static int sam_emac_configure(struct sam_emac_s *priv);
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: sam_checkreg
*
* Description:
* Check if the current register access is a duplicate of the preceding.
@ -537,8 +543,8 @@ static uint32_t sam_getreg(struct sam_emac_s *priv, uintptr_t address)
****************************************************************************/
#ifdef CONFIG_SAMA5_EMACA_REGDEBUG
static void sam_putreg(struct sam_emac_s *priv, uintptr_t address,
uint32_t regval)
static void sam_putreg(struct sam_emac_s *priv,
uintptr_t address, uint32_t regval)
{
if (sam_checkreg(priv, true, regval, address))
{
@ -595,7 +601,7 @@ static uint16_t sam_txfree(struct sam_emac_s *priv)
* the configured size minus 1.
*/
return (CONFIG_SAMA5_EMAC_NTXBUFFERS-1) - sam_txinuse(priv);
return (CONFIG_SAMA5_EMAC_NTXBUFFERS - 1) - sam_txinuse(priv);
}
/****************************************************************************
@ -790,7 +796,7 @@ static int sam_transmit(struct sam_emac_s *priv)
/* Update TX descriptor status. */
status = dev->d_len | EMACTXD_STA_LAST;
if (priv->txhead == CONFIG_SAMA5_EMAC_NTXBUFFERS-1)
if (priv->txhead == CONFIG_SAMA5_EMAC_NTXBUFFERS - 1)
{
status |= EMACTXD_STA_WRAP;
}
@ -845,8 +851,9 @@ static int sam_transmit(struct sam_emac_s *priv)
* Function: sam_txpoll
*
* Description:
* The transmitter is available, check if the network has any outgoing packets ready
* to send. This is a callback from devif_poll(). devif_poll() may be called:
* The transmitter is available, check if the network has any outgoing
* packets ready to send. This is a callback from devif_poll().
* devif_poll() may be called:
*
* 1. When the preceding TX packet send is complete,
* 2. When the preceding TX packet send timesout and the interface is reset
@ -918,8 +925,8 @@ static int sam_txpoll(struct net_driver_s *dev)
}
}
/* If zero is returned, the polling will continue until all connections have
* been examined.
/* If zero is returned, the polling will continue until all connections
* have been examined.
*/
return 0;
@ -934,7 +941,8 @@ static int sam_txpoll(struct net_driver_s *dev)
*
* 1. After completion of a transmission (sam_txdone),
* 2. When new TX data is available (sam_txavail), and
* 3. After a TX timeout to restart the sending process (sam_txtimeout_expiry).
* 3. After a TX timeout to restart the sending process
* (sam_txtimeout_expiry).
*
* Input Parameters:
* priv - Reference to the driver state structure
@ -957,7 +965,9 @@ static void sam_dopoll(struct sam_emac_s *priv)
if (sam_txfree(priv) > 0)
{
/* If we have the descriptor, then poll the network for new XMIT data. */
/* If we have the descriptor,
* then poll the network for new XMIT data.
*/
devif_poll(dev, sam_txpoll);
}
@ -1163,7 +1173,8 @@ static int sam_recvframe(struct sam_emac_s *priv)
if (pktlen < dev->d_len)
{
nerr("ERROR: Buffer size %d; frame size %d\n", dev->d_len, pktlen);
nerr("ERROR: Buffer size %d; frame size %d\n",
dev->d_len, pktlen);
return -E2BIG;
}
@ -1251,8 +1262,8 @@ static void sam_receive(struct sam_emac_s *priv)
{
sam_dumppacket("Received packet", dev->d_buf, dev->d_len);
/* Check if the packet is a valid size for the network buffer configuration
* (this should not happen)
/* Check if the packet is a valid size for the network buffer
* configuration (this should not happen)
*/
if (dev->d_len > CONFIG_NET_ETH_PKTSIZE)
@ -1262,9 +1273,9 @@ static void sam_receive(struct sam_emac_s *priv)
}
#ifdef CONFIG_NET_PKT
/* When packet sockets are enabled, feed the frame into the packet tap */
/* When packet sockets are enabled, feed the frame into the tap */
pkt_input(&priv->dev);
pkt_input(&priv->dev);
#endif
/* We only accept IP packets of the configured type and ARP packets */
@ -1282,7 +1293,7 @@ static void sam_receive(struct sam_emac_s *priv)
ipv4_input(&priv->dev);
/* If the above function invocation resulted in data that should be
* sent out on the network, the field d_len will set to a value > 0.
* sent out on the network, d_len field will set to a value > 0.
*/
if (priv->dev.d_len > 0)
@ -1319,7 +1330,7 @@ static void sam_receive(struct sam_emac_s *priv)
ipv6_input(&priv->dev);
/* If the above function invocation resulted in data that should be
* sent out on the network, the field d_len will set to a value > 0.
* sent out on the network, d_len field will set to a value > 0.
*/
if (priv->dev.d_len > 0)
@ -1356,7 +1367,7 @@ static void sam_receive(struct sam_emac_s *priv)
arp_arpin(&priv->dev);
/* If the above function invocation resulted in data that should be
* sent out on the network, the field d_len will set to a value > 0.
* sent out on the network, d_len field will set to a value > 0.
*/
if (priv->dev.d_len > 0)
@ -1414,18 +1425,19 @@ static void sam_txdone(struct sam_emac_s *priv)
/* Yes.. the descriptor is still in use. However, I have seen a
* case (only repeatable on start-up) where the USED bit is never
* set. Yikes! If we have encountered the first still busy
* descriptor, then we should also have TQBD equal to the descriptor
* address. If it is not, then treat is as used anyway.
* descriptor, then we should also have TQBD equal to the
* descriptor address. If it is not, then treat is as used anyway.
*/
#if 0 /* The issue does not exist in the current configuration, but may return */
#warning REVISIT
if (priv->txtail == 0 &&
sam_physramaddr((uintptr_t)txdesc) != sam_getreg(priv, SAM_EMAC_TBQP))
sam_physramaddr((uintptr_t)txdesc) !=
sam_getreg(priv, SAM_EMAC_TBQP))
{
txdesc->status = (uint32_t)EMACTXD_STA_USED;
up_clean_dcache((uintptr_t)txdesc,
(uintptr_t)txdesc + sizeof(struct emac_txdesc_s));
up_clean_dcache((uintptr_t)txdesc,
(uintptr_t)txdesc + sizeof(struct emac_txdesc_s));
}
else
#endif
@ -1500,8 +1512,8 @@ static void sam_interrupt_work(FAR void *arg)
ninfo("isr: %08x pending: %08x\n", isr, pending);
/* Check for the completion of a transmission. This should be done before
* checking for received data (because receiving can cause another transmission
* before we had a chance to handle the last one).
* checking for received data (because receiving can cause another
* transmission before we had a chance to handle the last one).
*
* ISR:TCOMP is set when a frame has been transmitted. Cleared on read.
* TSR:COMP is set when a frame has been transmitted. Cleared by writing a
@ -1627,7 +1639,8 @@ static void sam_interrupt_work(FAR void *arg)
#ifdef CONFIG_DEBUG_NET
/* Check for PAUSE Frame received (PFRE).
*
* ISR:PFRE indicates that a pause frame has been received. Cleared on a read.
* ISR:PFRE indicates that a pause frame has been received.
* Cleared on a read.
*/
if ((pending & EMAC_INT_PFR) != 0)
@ -1686,8 +1699,8 @@ static int sam_emac_interrupt(int irq, void *context, FAR void *arg)
*
* ISR:TCOMP is set when a frame has been transmitted. Cleared on read (so
* we cannot read it here).
* TSR:TXCOMP is set when a frame has been transmitted. Cleared by writing a
* one to this bit.
* TSR:TXCOMP is set when a frame has been transmitted. Cleared by writing
* a one to this bit.
*/
tsr = sam_getreg(priv, SAM_EMAC_TSR_OFFSET);
@ -2077,7 +2090,8 @@ static unsigned int sam_hashindx(const uint8_t *mac)
unsigned int ndx;
/* Isolate: mac[0]
* ... 05 04 03 02 01 00] */
* ... 05 04 03 02 01 00]
*/
ndx = mac[0];
@ -2248,8 +2262,8 @@ static int sam_addmac(struct net_driver_s *dev, const uint8_t *mac)
* Function: sam_rmmac
*
* Description:
* NuttX Callback: Remove the specified MAC address from the hardware multicast
* address filtering
* NuttX Callback: Remove the specified MAC address from the hardware
* multicast address filtering
*
* Input Parameters:
* dev - Reference to the NuttX driver state structure
@ -2346,9 +2360,9 @@ static int sam_rmmac(struct net_driver_s *dev, const uint8_t *mac)
* specified using the req->reg_no struct field and then write its output
* to the req->val_out field.
*
* When called with SIOCSMIIREG it will write to a register of the PHY that
* is specified using the req->reg_no struct field and use req->val_in as
* its input.
* When called with SIOCSMIIREG it will write to a register of the PHY
* that is specified using the req->reg_no struct field and use req->
* val_in as its input.
*
* Input Parameters:
* dev - Ethernet device structure
@ -2375,7 +2389,8 @@ static int sam_ioctl(struct net_driver_s *dev, int cmd, unsigned long arg)
#ifdef CONFIG_ARCH_PHY_INTERRUPT
case SIOCMIINOTIFY: /* Set up for PHY event notifications */
{
struct mii_ioctl_notify_s *req = (struct mii_ioctl_notify_s *)((uintptr_t)arg);
struct mii_ioctl_notify_s *req =
(struct mii_ioctl_notify_s *)((uintptr_t)arg);
ret = phy_notify_subscribe(dev->d_ifname, req->pid, &req->event);
if (ret == OK)
@ -2390,7 +2405,8 @@ static int sam_ioctl(struct net_driver_s *dev, int cmd, unsigned long arg)
case SIOCGMIIPHY: /* Get MII PHY address */
{
struct mii_ioctl_data_s *req = (struct mii_ioctl_data_s *)((uintptr_t)arg);
struct mii_ioctl_data_s *req =
(struct mii_ioctl_data_s *)((uintptr_t)arg);
req->phy_id = priv->phyaddr;
ret = OK;
}
@ -2398,7 +2414,8 @@ static int sam_ioctl(struct net_driver_s *dev, int cmd, unsigned long arg)
case SIOCGMIIREG: /* Get register from MII PHY */
{
struct mii_ioctl_data_s *req = (struct mii_ioctl_data_s *)((uintptr_t)arg);
struct mii_ioctl_data_s *req =
(struct mii_ioctl_data_s *)((uintptr_t)arg);
uint32_t regval;
/* Enable management port */
@ -2418,7 +2435,8 @@ static int sam_ioctl(struct net_driver_s *dev, int cmd, unsigned long arg)
case SIOCSMIIREG: /* Set register in MII PHY */
{
struct mii_ioctl_data_s *req = (struct mii_ioctl_data_s *)((uintptr_t)arg);
struct mii_ioctl_data_s *req =
(struct mii_ioctl_data_s *)((uintptr_t)arg);
uint32_t regval;
/* Enable management port */
@ -3063,6 +3081,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
sam_putreg(priv, SAM_EMAC_USRIO, regval);
errout:
/* Disable management port */
regval = sam_getreg(priv, SAM_EMAC_NCR);
@ -3159,6 +3178,7 @@ static bool sam_linkup(struct sam_emac_s *priv)
linkup = true;
errout:
/* Disable management port */
regval = sam_getreg(priv, SAM_EMAC_NCR);
@ -3194,20 +3214,20 @@ static int sam_phyinit(struct sam_emac_s *priv)
regval &= ~EMAC_NCFGR_CLK_MASK;
mck = BOARD_MCK_FREQUENCY;
if (mck > (160*1000*1000))
if (mck > (160 * 1000 * 1000))
{
nerr("ERROR: Cannot realize PHY clock\n");
return -EINVAL;
}
else if (mck > (80*1000*1000))
else if (mck > (80 * 1000 * 1000))
{
regval |= EMAC_NCFGR_CLK_DIV64; /* MCK divided by 64 (MCK up to 160 MHz) */
}
else if (mck > (40*1000*1000))
else if (mck > (40 * 1000 * 1000))
{
regval |= EMAC_NCFGR_CLK_DIV32; /* MCK divided by 32 (MCK up to 80 MHz) */
}
else if (mck > (20*1000*1000))
else if (mck > (20 * 1000 * 1000))
{
regval |= EMAC_NCFGR_CLK_DIV16; /* MCK divided by 16 (MCK up to 40 MHz) */
}
@ -3255,6 +3275,7 @@ static int sam_phyinit(struct sam_emac_s *priv)
static inline void sam_ethgpioconfig(struct sam_emac_s *priv)
{
/* Configure PIO pins to support EMAC */
/* Configure EMAC PIO pins common to both MII and RMII */
sam_configpio(PIO_EMAC_TX0);
@ -3309,7 +3330,9 @@ static void sam_txreset(struct sam_emac_s *priv)
{
bufaddr = (uint32_t)(&(txbuffer[ndx * EMAC_TX_UNITSIZE]));
/* Set the buffer address and mark the descriptor as in used by firmware */
/* Set the buffer address and mark the descriptor
* as in used by firmware
*/
physaddr = sam_physramaddr(bufaddr);
txdesc[ndx].addr = physaddr;
@ -3323,9 +3346,8 @@ static void sam_txreset(struct sam_emac_s *priv)
/* Flush the entire TX descriptor table to RAM */
up_clean_dcache((uintptr_t)txdesc,
(uintptr_t)txdesc +
CONFIG_SAMA5_EMAC_NTXBUFFERS * sizeof(struct emac_txdesc_s));
up_clean_dcache((uintptr_t)txdesc, (uintptr_t)txdesc +
CONFIG_SAMA5_EMAC_NTXBUFFERS * sizeof(struct emac_txdesc_s));
/* Set the Transmit Buffer Queue Pointer Register */
@ -3387,9 +3409,8 @@ static void sam_rxreset(struct sam_emac_s *priv)
/* Flush the entire RX descriptor table to RAM */
up_clean_dcache((uintptr_t)rxdesc,
(uintptr_t)rxdesc +
CONFIG_SAMA5_EMAC_NRXBUFFERS * sizeof(struct emac_rxdesc_s));
up_clean_dcache((uintptr_t)rxdesc, (uintptr_t)rxdesc +
CONFIG_SAMA5_EMAC_NRXBUFFERS * sizeof(struct emac_rxdesc_s));
/* Set the Receive Buffer Queue Pointer Register */
@ -3478,9 +3499,12 @@ static void sam_macaddress(struct sam_emac_s *priv)
ninfo("%s MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
dev->d_ifname,
dev->d_mac.ether.ether_addr_octet[0], dev->d_mac.ether.ether_addr_octet[1],
dev->d_mac.ether.ether_addr_octet[2], dev->d_mac.ether.ether_addr_octet[3],
dev->d_mac.ether.ether_addr_octet[4], dev->d_mac.ether.ether_addr_octet[5]);
dev->d_mac.ether.ether_addr_octet[0],
dev->d_mac.ether.ether_addr_octet[1],
dev->d_mac.ether.ether_addr_octet[2],
dev->d_mac.ether.ether_addr_octet[3],
dev->d_mac.ether.ether_addr_octet[4],
dev->d_mac.ether.ether_addr_octet[5]);
/* Set the MAC address */
@ -3649,8 +3673,8 @@ static int sam_emac_configure(struct sam_emac_s *priv)
/* Setup the interrupts for TX events, RX events, and error events */
regval = (EMAC_INT_RCOMP | EMAC_INT_RXUBR | EMAC_INT_TUND | EMAC_INT_RLE |
EMAC_INT_TXERR | EMAC_INT_TCOMP | EMAC_INT_ROVR | EMAC_INT_HRESP |
EMAC_INT_PFR | EMAC_INT_PTZ);
EMAC_INT_TXERR | EMAC_INT_TCOMP | EMAC_INT_ROVR |
EMAC_INT_HRESP | EMAC_INT_PFR | EMAC_INT_PTZ);
sam_putreg(priv, SAM_EMAC_IER, regval);
return OK;
}
@ -3735,7 +3759,8 @@ int sam_emac_initialize(void)
ret = irq_attach(SAM_IRQ_EMAC, sam_emac_interrupt, NULL);
if (ret < 0)
{
nerr("ERROR: Failed to attach the handler to the IRQ%d\n", SAM_IRQ_EMAC);
nerr("ERROR: Failed to attach the handler to the IRQ%d\n",
SAM_IRQ_EMAC);
goto errout_with_buffers;
}
@ -3748,7 +3773,8 @@ int sam_emac_initialize(void)
ret = sam_ifdown(&priv->dev);
if (ret < 0)
{
nerr("ERROR: Failed to put the interface in the down state: %d\n", ret);
nerr("ERROR: Failed to put the interface in the down state: %d\n",
ret);
goto errout_with_buffers;
}

192
arch/arm/src/sama5/sam_emacb.c
View file

@ -106,6 +106,7 @@
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Configuration ************************************************************/
/* If processing is not done at the interrupt level, then work queue support
@ -317,8 +318,9 @@
#define EMAC_TX_UNITSIZE CONFIG_NET_ETH_PKTSIZE /* MAX size for Ethernet packet */
/* Timing *******************************************************************/
/* TX poll delay = 1 seconds. CLK_TCK is the number of clock ticks per
* second
/* TX poll delay = 1 seconds.
* CLK_TCK is the number of clock ticks per second
*/
#define SAM_WDDELAY (1*CLK_TCK)
@ -332,6 +334,7 @@
#define PHY_RETRY_MAX 1000000
/* Helpers ******************************************************************/
/* This is a helper pointer for accessing the contents of the EMAC
* header
*/
@ -341,6 +344,7 @@
/****************************************************************************
* Private Types
****************************************************************************/
/* This structure defines the constant an configured attributes of an EMAC */
struct sam_emacattr_s
@ -359,14 +363,14 @@ struct sam_emacattr_s
uint8_t lsoui; /* LS 2 bits of the 18-bit OUI */
bool rmii; /* True: RMII vs. False: MII */
bool clause45; /* True: Clause 45 behavior */
//bool autoneg; /* True: Autonegotiate rate and *plex */
bool autoneg; /* True: Autonegotiate rate and *plex */
bool sralt; /* True: Alternate PHYSR bit access */
union
{
/* "Standard" form: Individual bits determine speed and half/full
* duplex.
*/
/* "Standard" form: Individual bits determine speed and half/full
* duplex.
*/
struct
{
@ -375,9 +379,9 @@ struct sam_emacattr_s
uint16_t fduplex; /* Full duplex bit */
} std;
/* Alternative form: Speed and duplex are encoded in a single,
* multi-bit field.
*/
/* Alternative form: Speed and duplex are encoded in a single,
* multi-bit field.
*/
struct
{
@ -404,7 +408,7 @@ struct sam_emacattr_s
#endif
};
/* The sam_emac_s encapsulates all state information for the EMAC peripheral */
/* The sam_emac_s encapsulates all state information for EMAC peripheral */
struct sam_emac_s
{
@ -450,6 +454,7 @@ struct sam_emac_s
/****************************************************************************
* Private Function Prototypes
****************************************************************************/
/* Register operations ******************************************************/
#if defined(CONFIG_SAMA5_EMACB_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES)
@ -458,7 +463,8 @@ static bool sam_checkreg(struct sam_emac_s *priv, bool wr,
#endif
static uint32_t sam_getreg(struct sam_emac_s *priv, uint16_t offset);
static void sam_putreg(struct sam_emac_s *priv, uint16_t offset, uint32_t val);
static void sam_putreg(struct sam_emac_s *priv,
uint16_t offset, uint32_t val);
/* Buffer management */
@ -574,18 +580,20 @@ static struct emac_rxdesc_s g_emac0_rxdesc[CONFIG_SAMA5_EMAC0_NRXBUFFERS]
/* EMAC0 Transmit Buffers
*
* Section 3.6 of AMBA 2.0 spec states that burst should not cross 1K Boundaries.
* Receive buffer manager writes are burst of 2 words => 3 lsb bits of the address
* shall be set to 0
* Section 3.6 of AMBA 2.0 spec states that burst should not cross 1K
* Boundaries. Receive buffer manager writes are burst of 2 words => 3
* lsb bits of the address shall be set to 0
*/
static uint8_t g_emac0_txbuffer[CONFIG_SAMA5_EMAC0_NTXBUFFERS * EMAC_TX_UNITSIZE];
__attribute__((aligned(8)))
static uint8_t
g_emac0_txbuffer[CONFIG_SAMA5_EMAC0_NTXBUFFERS * EMAC_TX_UNITSIZE]
__attribute__((aligned(8)));
/* EMAC0 Receive Buffers */
static uint8_t g_emac0_rxbuffer[CONFIG_SAMA5_EMAC0_NRXBUFFERS * EMAC_RX_UNITSIZE]
__attribute__((aligned(8)));
static uint8_t
g_emac0_rxbuffer[CONFIG_SAMA5_EMAC0_NRXBUFFERS * EMAC_RX_UNITSIZE]
__attribute__((aligned(8)));
#endif
@ -602,18 +610,20 @@ static struct emac_rxdesc_s g_emac1_rxdesc[CONFIG_SAMA5_EMAC1_NRXBUFFERS]
/* EMAC1 Transmit Buffers
*
* Section 3.6 of AMBA 2.0 spec states that burst should not cross 1K Boundaries.
* Receive buffer manager writes are burst of 2 words => 3 lsb bits of the address
* shall be set to 0
* Section 3.6 of AMBA 2.0 spec states that burst should not cross 1K
* Boundaries. Receive buffer manager writes are burst of 2 words => 3
* lsb bits of the address shall be set to 0
*/
static uint8_t g_emac1_txbuffer[CONFIG_SAMA5_EMAC1_NTXBUFFERS * EMAC_TX_UNITSIZE];
__attribute__((aligned(8)))
static uint8_t
g_emac1_txbuffer[CONFIG_SAMA5_EMAC1_NTXBUFFERS * EMAC_TX_UNITSIZE]
__attribute__((aligned(8)));
/* EMAC1 Receive Buffers */
static uint8_t g_emac1_rxbuffer[CONFIG_SAMA5_EMAC1_NRXBUFFERS * EMAC_RX_UNITSIZE]
__attribute__((aligned(8)));
static uint8_t
g_emac1_rxbuffer[CONFIG_SAMA5_EMAC1_NRXBUFFERS * EMAC_RX_UNITSIZE]
__attribute__((aligned(8)));
#endif
#endif
@ -642,7 +652,7 @@ static const struct sam_emacattr_s g_emac0_attr =
.clause45 = true,
#endif
#ifdef CONFIG_SAMA5_EMAC0_AUTONEG
//.autoneg = true,
.autoneg = true,
#endif
#ifdef CONFIG_SAMA5_EMAC0_PHYSR_ALTCONFIG
.sralt = true,
@ -662,7 +672,8 @@ static const struct sam_emacattr_s g_emac0_attr =
#else
.std =
{
.stdmask = (CONFIG_SAMA5_EMAC0_PHYSR_SPEED | CONFIG_SAMA5_EMAC0_PHYSR_MODE),
.stdmask = CONFIG_SAMA5_EMAC0_PHYSR_SPEED |
CONFIG_SAMA5_EMAC0_PHYSR_MODE,
.speed100 = CONFIG_SAMA5_EMAC0_PHYSR_100MBPS,
.fduplex = CONFIG_SAMA5_EMAC0_PHYSR_FULLDUPLEX,
},
@ -722,7 +733,7 @@ static const struct sam_emacattr_s g_emac1_attr =
.clause45 = true,
#endif
#ifdef CONFIG_SAMA5_EMAC1_AUTONEG
//.autoneg = true,
.autoneg = true,
#endif
#ifdef CONFIG_SAMA5_EMAC1_PHYSR_ALTCONFIG
.sralt = true,
@ -742,7 +753,8 @@ static const struct sam_emacattr_s g_emac1_attr =
#else
.std =
{
.stdmask = (CONFIG_SAMA5_EMAC1_PHYSR_SPEED | CONFIG_SAMA5_EMAC1_PHYSR_MODE),
.stdmask = CONFIG_SAMA5_EMAC1_PHYSR_SPEED |
CONFIG_SAMA5_EMAC1_PHYSR_MODE,
.speed100 = CONFIG_SAMA5_EMAC1_PHYSR_100MBPS,
.fduplex = CONFIG_SAMA5_EMAC1_PHYSR_FULLDUPLEX,
},
@ -783,8 +795,8 @@ static struct sam_emac_s g_emac1;
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: sam_checkreg
*
* Description:
* Check if the current register access is a duplicate of the preceding.
@ -869,8 +881,8 @@ static uint32_t sam_getreg(struct sam_emac_s *priv, uint16_t offset)
*
****************************************************************************/
static void sam_putreg(struct sam_emac_s *priv, uint16_t offset,
uint32_t regval)
static void sam_putreg(struct sam_emac_s *priv,
uint16_t offset, uint32_t regval)
{
uintptr_t regaddr = priv->attr->base + (uintptr_t)offset;
@ -930,7 +942,7 @@ static uint16_t sam_txfree(struct sam_emac_s *priv)
* the configured size minus 1.
*/
return (priv->attr->ntxbuffers-1) - sam_txinuse(priv);
return (priv->attr->ntxbuffers - 1) - sam_txinuse(priv);
}
/****************************************************************************
@ -1125,7 +1137,7 @@ static int sam_transmit(struct sam_emac_s *priv)
/* Update TX descriptor status. */
status = dev->d_len | EMACTXD_STA_LAST;
if (priv->txhead == priv->attr->ntxbuffers-1)
if (priv->txhead == priv->attr->ntxbuffers - 1)
{
status |= EMACTXD_STA_WRAP;
}
@ -1180,8 +1192,9 @@ static int sam_transmit(struct sam_emac_s *priv)
* Function: sam_txpoll
*
* Description:
* The transmitter is available, check if the network has any outgoing packets ready
* to send. This is a callback from devif_poll(). devif_poll() may be called:
* The transmitter is available, check if the network has any outgoing
* packets ready to send. This is a callback from devif_poll().
* devif_poll() may be called:
*
* 1. When the preceding TX packet send is complete,
* 2. When the preceding TX packet send timesout and the interface is reset
@ -1253,8 +1266,8 @@ static int sam_txpoll(struct net_driver_s *dev)
}
}
/* If zero is returned, the polling will continue until all connections have
* been examined.
/* If zero is returned, the polling will continue until all connections
* have been examined.
*/
return 0;
@ -1293,7 +1306,9 @@ static void sam_dopoll(struct sam_emac_s *priv)
if (sam_txfree(priv) > 0)
{
/* If we have the descriptor, then poll the network for new XMIT data. */
/* If we have the descriptor,
* then poll the network for new XMIT data.
*/
devif_poll(dev, sam_txpoll);
}
@ -1586,8 +1601,8 @@ static void sam_receive(struct sam_emac_s *priv)
{
sam_dumppacket("Received packet", dev->d_buf, dev->d_len);
/* Check if the packet is a valid size for the network buffer configuration
* (this should not happen)
/* Check if the packet is a valid size for the network buffer
* configuration (this should not happen)
*/
if (dev->d_len > CONFIG_NET_ETH_PKTSIZE)
@ -1597,9 +1612,9 @@ static void sam_receive(struct sam_emac_s *priv)
}
#ifdef CONFIG_NET_PKT
/* When packet sockets are enabled, feed the frame into the packet tap */
/* When packet sockets are enabled, feed the frame into the tap */
pkt_input(&priv->dev);
pkt_input(&priv->dev);
#endif
/* We only accept IP packets of the configured type and ARP packets */
@ -1617,7 +1632,7 @@ static void sam_receive(struct sam_emac_s *priv)
ipv4_input(&priv->dev);
/* If the above function invocation resulted in data that should be
* sent out on the network, the field d_len will set to a value > 0.
* sent out on the network, d_len field will set to a value > 0.
*/
if (priv->dev.d_len > 0)
@ -1654,7 +1669,7 @@ static void sam_receive(struct sam_emac_s *priv)
ipv6_input(&priv->dev);
/* If the above function invocation resulted in data that should be
* sent out on the network, the field d_len will set to a value > 0.
* sent out on the network, d_len field will set to a value > 0.
*/
if (priv->dev.d_len > 0)
@ -1691,7 +1706,7 @@ static void sam_receive(struct sam_emac_s *priv)
arp_arpin(&priv->dev);
/* If the above function invocation resulted in data that should be
* sent out on the network, the field d_len will set to a value > 0.
* sent out on the network, d_len field will set to a value > 0.
*/
if (priv->dev.d_len > 0)
@ -1765,18 +1780,19 @@ static void sam_txdone(struct sam_emac_s *priv)
/* Yes.. the descriptor is still in use. However, I have seen a
* case (only repeatable on start-up) where the USED bit is never
* set. Yikes! If we have encountered the first still busy
* descriptor, then we should also have TQBD equal to the descriptor
* address. If it is not, then treat is as used anyway.
* descriptor, then we should also have TQBD equal to the
* descriptor address. If it is not, then treat is as used anyway.
*/
#if 0 /* The issue does not exist in the current configuration, but may return */
#warning REVISIT
if (priv->txtail == 0 &&
sam_physramaddr((uintptr_t)txdesc) != sam_getreg(priv, SAM_EMAC_TBQB_OFFSET))
sam_physramaddr((uintptr_t)txdesc) !=
sam_getreg(priv, SAM_EMAC_TBQB_OFFSET))
{
txdesc->status = (uint32_t)EMACTXD_STA_USED;
up_clean_dcache((uintptr_t)txdesc,
(uintptr_t)txdesc + sizeof(struct emac_txdesc_s));
(uintptr_t)txdesc + sizeof(struct emac_txdesc_s));
}
else
#endif
@ -1859,12 +1875,12 @@ static void sam_interrupt_work(FAR void *arg)
ninfo("isr: %08x pending: %08x\n", isr, pending);
/* Check for the completion of a transmission. This should be done before
* checking for received data (because receiving can cause another transmission
* before we had a chance to handle the last one).
* checking for received data (because receiving can cause another
* transmission before we had a chance to handle the last one).
*
* ISR:TCOMP is set when a frame has been transmitted. Cleared on read.
* TSR:TXCOMP is set when a frame has been transmitted. Cleared by writing a
* one to this bit.
* TSR:TXCOMP is set when a frame has been transmitted. Cleared by writing
* a one to this bit.
*/
if ((pending & EMAC_INT_TCOMP) != 0 || (tsr & EMAC_TSR_TXCOMP) != 0)
@ -1901,7 +1917,8 @@ static void sam_interrupt_work(FAR void *arg)
if ((tsr & EMAC_TSR_TFC) != 0)
{
nerr("ERROR: Transmit Frame Corruption due to AHB error: %08x\n", tsr);
nerr("ERROR: Transmit Frame Corruption due to AHB error: %08x\n",
tsr);
clrbits |= EMAC_TSR_TFC;
}
@ -2047,8 +2064,8 @@ static int sam_emac_interrupt(int irq, void *context, FAR void *arg)
*
* ISR:TCOMP is set when a frame has been transmitted. Cleared on read (so
* we cannot read it here).
* TSR:TXCOMP is set when a frame has been transmitted. Cleared by writing a
* one to this bit.
* TSR:TXCOMP is set when a frame has been transmitted. Cleared by writing
* a one to this bit.
*/
tsr = sam_getreg(priv, SAM_EMAC_TSR_OFFSET);
@ -2446,7 +2463,8 @@ static unsigned int sam_hashindx(const uint8_t *mac)
unsigned int ndx;
/* Isolate: mac[0]
* ... 05 04 03 02 01 00] */
* ... 05 04 03 02 01 00]
*/
ndx = mac[0];
@ -2616,8 +2634,8 @@ static int sam_addmac(struct net_driver_s *dev, const uint8_t *mac)
* Function: sam_rmmac
*
* Description:
* NuttX Callback: Remove the specified MAC address from the hardware multicast
* address filtering
* NuttX Callback: Remove the specified MAC address from the hardware
* multicast address filtering
*
* Input Parameters:
* dev - Reference to the NuttX driver state structure
@ -2713,9 +2731,9 @@ static int sam_rmmac(struct net_driver_s *dev, const uint8_t *mac)
* specified using the req->reg_no struct field and then write its output
* to the req->val_out field.
*
* When called with SIOCSMIIREG it will write to a register of the PHY that
* is specified using the req->reg_no struct field and use req->val_in as
* its input.
* When called with SIOCSMIIREG it will write to a register of the PHY
* that is specified using the req->reg_no struct field and use req->
* val_in as its input.
*
* Input Parameters:
* dev - Ethernet device structure
@ -2742,7 +2760,8 @@ static int sam_ioctl(struct net_driver_s *dev, int cmd, unsigned long arg)
#ifdef CONFIG_ARCH_PHY_INTERRUPT
case SIOCMIINOTIFY: /* Set up for PHY event notifications */
{
struct mii_ioctl_notify_s *req = (struct mii_ioctl_notify_s *)((uintptr_t)arg);
struct mii_ioctl_notify_s *req =
(struct mii_ioctl_notify_s *)((uintptr_t)arg);
ret = phy_notify_subscribe(dev->d_ifname, req->pid, &req->event);
if (ret == OK)
@ -2757,7 +2776,8 @@ static int sam_ioctl(struct net_driver_s *dev, int cmd, unsigned long arg)
case SIOCGMIIPHY: /* Get MII PHY address */
{
struct mii_ioctl_data_s *req = (struct mii_ioctl_data_s *)((uintptr_t)arg);
struct mii_ioctl_data_s *req =
(struct mii_ioctl_data_s *)((uintptr_t)arg);
req->phy_id = priv->phyaddr;
ret = OK;
}
@ -2765,7 +2785,8 @@ static int sam_ioctl(struct net_driver_s *dev, int cmd, unsigned long arg)
case SIOCGMIIREG: /* Get register from MII PHY */
{
struct mii_ioctl_data_s *req = (struct mii_ioctl_data_s *)((uintptr_t)arg);
struct mii_ioctl_data_s *req =
(struct mii_ioctl_data_s *)((uintptr_t)arg);
uint32_t regval;
/* Enable management port */
@ -2785,7 +2806,8 @@ static int sam_ioctl(struct net_driver_s *dev, int cmd, unsigned long arg)
case SIOCSMIIREG: /* Set register in MII PHY */
{
struct mii_ioctl_data_s *req = (struct mii_ioctl_data_s *)((uintptr_t)arg);
struct mii_ioctl_data_s *req =
(struct mii_ioctl_data_s *)((uintptr_t)arg);
uint32_t regval;
/* Enable management port */
@ -2984,7 +3006,8 @@ static int sam_phyintenable(struct sam_emac_s *priv)
/* Does this MAC support a KSZ80X1 PHY? */
if (priv->phytype == SAMA5_PHY_KSZ8051 || priv->phytype == SAMA5_PHY_KSZ8081)
if (priv->phytype == SAMA5_PHY_KSZ8051 ||
priv->phytype == SAMA5_PHY_KSZ8081)
{
/* Enable management port */
@ -3262,7 +3285,7 @@ static int sam_phyread(struct sam_emac_s *priv, uint8_t phyaddr,
/* Return data */
*phyval = (uint16_t)(sam_getreg(priv, SAM_EMAC_MAN_OFFSET) & EMAC_MAN_DATA_MASK);
*phyval = sam_getreg(priv, SAM_EMAC_MAN_OFFSET) & EMAC_MAN_DATA_MASK;
return OK;
}
@ -3549,6 +3572,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
sam_putreg(priv, SAM_EMAC_UR_OFFSET, regval);
errout:
/* Disable management port */
regval = sam_getreg(priv, SAM_EMAC_NCR_OFFSET);
@ -3645,6 +3669,7 @@ static bool sam_linkup(struct sam_emac_s *priv)
linkup = true;
errout:
/* Disable management port */
regval = sam_getreg(priv, SAM_EMAC_NCR_OFFSET);
@ -3680,20 +3705,20 @@ static int sam_phyinit(struct sam_emac_s *priv)
regval &= ~EMAC_NCFGR_CLK_MASK;
mck = BOARD_MCK_FREQUENCY;
if (mck > (160*1000*1000))
if (mck > (160 * 1000 * 1000))
{
nerr("ERROR: Cannot realize PHY clock\n");
return -EINVAL;
}
else if (mck > (80*1000*1000))
else if (mck > (80 * 1000 * 1000))
{
regval |= EMAC_NCFGR_CLK_DIV64; /* MCK divided by 64 (MCK up to 160 MHz) */
}
else if (mck > (40*1000*1000))
else if (mck > (40 * 1000 * 1000))
{
regval |= EMAC_NCFGR_CLK_DIV32; /* MCK divided by 32 (MCK up to 80 MHz) */
}
else if (mck > (20*1000*1000))
else if (mck > (20 * 1000 * 1000))
{
regval |= EMAC_NCFGR_CLK_DIV16; /* MCK divided by 16 (MCK up to 40 MHz) */
}
@ -3869,7 +3894,9 @@ static void sam_txreset(struct sam_emac_s *priv)
{
bufaddr = (uint32_t)(&(txbuffer[ndx * EMAC_TX_UNITSIZE]));
/* Set the buffer address and mark the descriptor as in used by firmware */
/* Set the buffer address and mark the descriptor
* as in used by firmware
*/
physaddr = sam_physramaddr(bufaddr);
txdesc[ndx].addr = physaddr;
@ -4126,9 +4153,12 @@ static void sam_macaddress(struct sam_emac_s *priv)
ninfo("%s MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
dev->d_ifname,
dev->d_mac.ether.ether_addr_octet[0], dev->d_mac.ether.ether_addr_octet[1],
dev->d_mac.ether.ether_addr_octet[2], dev->d_mac.ether.ether_addr_octet[3],
dev->d_mac.ether.ether_addr_octet[4], dev->d_mac.ether.ether_addr_octet[5]);
dev->d_mac.ether.ether_addr_octet[0],
dev->d_mac.ether.ether_addr_octet[1],
dev->d_mac.ether.ether_addr_octet[2],
dev->d_mac.ether.ether_addr_octet[3],
dev->d_mac.ether.ether_addr_octet[4],
dev->d_mac.ether.ether_addr_octet[5]);
/* Set the MAC address */
@ -4297,7 +4327,7 @@ static int sam_emac_configure(struct sam_emac_s *priv)
/* Setup the interrupts for TX events, RX events, and error events */
regval = (EMAC_INT_RCOMP | EMAC_INT_RXUBR | EMAC_INT_TUR | EMAC_INT_RLEX |
EMAC_INT_TFC | EMAC_INT_TCOMP | EMAC_INT_ROVR | EMAC_INT_HRESP |
EMAC_INT_TFC | EMAC_INT_TCOMP | EMAC_INT_ROVR | EMAC_INT_HRESP |
EMAC_INT_PFNZ | EMAC_INT_PTZ);
sam_putreg(priv, SAM_EMAC_IER_OFFSET, regval);
return OK;
@ -4424,7 +4454,8 @@ int sam_emac_initialize(int intf)
ret = irq_attach(priv->attr->irq, sam_emac_interrupt, priv);
if (ret < 0)
{
nerr("ERROR: Failed to attach the handler to the IRQ%d\n", priv->attr->irq);
nerr("ERROR: Failed to attach the handler to the IRQ%d\n",
priv->attr->irq);
goto errout_with_buffers;
}
@ -4437,7 +4468,8 @@ int sam_emac_initialize(int intf)
ret = sam_ifdown(&priv->dev);
if (ret < 0)
{
nerr("ERROR: Failed to put the interface in the down state: %d\n", ret);
nerr("ERROR: Failed to put the interface in the down state: %d\n",
ret);
goto errout_with_buffers;
}

31
arch/arm/src/sama5/sam_gmac.c
View file

@ -170,8 +170,8 @@
/* Timing *******************************************************************/
/* TX poll delay = 1 seconds. CLK_TCK is the number of clock ticks per
* second
/* TX poll delay = 1 seconds.
* CLK_TCK is the number of clock ticks per second
*/
#define SAM_WDDELAY (1*CLK_TCK)
@ -196,7 +196,7 @@
* Private Types
****************************************************************************/
/* The sam_gmac_s encapsulates all state information for the GMAC peripheral */
/* The sam_gmac_s encapsulates all state information for GMAC peripheral */
struct sam_gmac_s
{
@ -475,8 +475,8 @@ static uint32_t sam_getreg(struct sam_gmac_s *priv, uintptr_t address)
****************************************************************************/
#ifdef CONFIG_SAMA5_GMAC_REGDEBUG
static void sam_putreg(struct sam_gmac_s *priv, uintptr_t address,
uint32_t regval)
static void sam_putreg(struct sam_gmac_s *priv,
uintptr_t address, uint32_t regval)
{
if (sam_checkreg(priv, true, regval, address))
{
@ -907,7 +907,9 @@ static void sam_dopoll(struct sam_gmac_s *priv)
if (sam_txfree(priv) > 0)
{
/* If we have the descriptor, then poll the network for new XMIT data. */
/* If we have the descriptor,
* then poll the network for new XMIT data.
*/
devif_poll(dev, sam_txpoll);
}
@ -1217,7 +1219,7 @@ static void sam_receive(struct sam_gmac_s *priv)
* tap
*/
pkt_input(&priv->dev);
pkt_input(&priv->dev);
#endif
/* We only accept IP packets of the configured type and ARP packets */
@ -1362,7 +1364,7 @@ static void sam_txdone(struct sam_gmac_s *priv)
txdesc = &priv->txdesc[priv->txtail];
up_invalidate_dcache((uintptr_t)txdesc,
(uintptr_t)txdesc + sizeof(struct gmac_txdesc_s));
(uintptr_t)txdesc + sizeof(struct gmac_txdesc_s));
/* Is this TX descriptor done transmitting? (SAMA5D36 datasheet,
* p. 934)
@ -2524,13 +2526,13 @@ static int sam_phyintenable(struct sam_gmac_s *priv)
* interrupts
*/
ret = sam_phyread(priv, priv->phyaddr, GMII_KSZ90x1_ICS, &phyval);
ret = sam_phyread(priv, priv->phyaddr, GMII_KSZ90X1_ICS, &phyval);
if (ret == OK)
{
/* Enable link up/down interrupts */
ret = sam_phywrite(priv, priv->phyaddr, GMII_KSZ90x1_ICS,
(GMII_KSZ90x1_INT_LDEN | GMII_KSZ90x1_INT_LUEN));
ret = sam_phywrite(priv, priv->phyaddr, GMII_KSZ90X1_ICS,
(GMII_KSZ90X1_INT_LDEN | GMII_KSZ90X1_INT_LUEN));
}
/* Disable the management port */
@ -2961,15 +2963,16 @@ static int sam_autonegotiate(struct sam_gmac_s *priv)
#ifdef SAMA5_GMAC_PHY_KSZ90x1
/* Set up the KSZ9020/31 PHY */
phyval = GMII_KSZ90x1_RCCPSR | GMII_ERCR_WRITE;
phyval = GMII_KSZ90X1_RCCPSR | GMII_ERCR_WRITE;
sam_phywrite(priv, priv->phyaddr, GMII_ERCR, phyval);
sam_phywrite(priv, priv->phyaddr, GMII_ERDWR, 0xf2f4);
phyval = GMII_KSZ90x1_RRDPSR | GMII_ERCR_WRITE;
phyval = GMII_KSZ90X1_RRDPSR | GMII_ERCR_WRITE;
sam_phywrite(priv, priv->phyaddr, GMII_ERCR, phyval);
sam_phywrite(priv, priv->phyaddr, GMII_ERDWR, 0x2222);
ret = sam_phywrite(priv, priv->phyaddr, GMII_KSZ90x1_ICS, 0xff00);
ret = sam_phywrite(priv, priv->phyaddr,
GMII_KSZ90X1_ICS, 0xff00);
#endif
/* Set the Auto_negotiation Advertisement Register, MII advertising for

10
arch/arm/src/sama5/sam_sdmmc.c
View file

@ -158,12 +158,12 @@ struct sam_dev_s
/* Event support */
uint32_t base; /* SDMMC register base address */
sem_t waitsem; /* Implements event waiting */
sdio_eventset_t waitevents; /* Set of events to be waited for */
uint32_t waitints; /* Interrupt enables for event waiting */
uint32_t base; /* SDMMC register base address */
sem_t waitsem; /* Implements event waiting */
sdio_eventset_t waitevents; /* Set of events to be waited for */
uint32_t waitints; /* Interrupt enables for event waiting */
volatile sdio_eventset_t wkupevent; /* The event that caused the wakeup */
WDOG_ID waitwdog; /* Watchdog that handles event timeouts */
WDOG_ID waitwdog; /* Watchdog that handles event timeouts */
/* Callback support */

134
arch/arm/src/samd5e5/sam_gmac.c
View file

@ -168,8 +168,8 @@
/* Timing *******************************************************************/
/* TX poll delay = 1 seconds. CLK_TCK is the number of clock ticks per
* second
/* TX poll delay = 1 seconds.
* CLK_TCK is the number of clock ticks per second
*/
#define SAM_WDDELAY (1*CLK_TCK)
@ -194,7 +194,7 @@
* Private Types
****************************************************************************/
/* The sam_gmac_s encapsulates all state information for the GMAC peripheral */
/* The sam_gmac_s encapsulates all state information for GMAC peripheral */
struct sam_gmac_s
{
@ -264,9 +264,9 @@ static struct gmac_rxdesc_s g_rxdesc[CONFIG_SAMD5E5_GMAC_NRXBUFFERS]
/* Transmit Buffers
*
* Section 3.6 of AMBA 2.0 spec states that burst should not cross 1K Boundaries.
* Receive buffer manager writes are burst of 2 words => 3 lsb bits of the address
* shall be set to 0
* Section 3.6 of AMBA 2.0 spec states that burst should not cross 1K
* Boundaries. Receive buffer manager writes are burst of 2 words => 3
* lsb bits of the address shall be set to 0
*/
static uint8_t g_txbuffer[CONFIG_SAMD5E5_GMAC_NTXBUFFERS * GMAC_TX_UNITSIZE]
@ -288,7 +288,8 @@ static uint8_t g_rxbuffer[CONFIG_SAMD5E5_GMAC_NRXBUFFERS * GMAC_RX_UNITSIZE]
static bool sam_checkreg(struct sam_gmac_s *priv, bool wr,
uint32_t regval, uintptr_t address);
static uint32_t sam_getreg(struct sam_gmac_s *priv, uintptr_t addr);
static void sam_putreg(struct sam_gmac_s *priv, uintptr_t addr, uint32_t val);
static void sam_putreg(struct sam_gmac_s *priv,
uintptr_t addr, uint32_t val);
#else
# define sam_getreg(priv,addr) getreg32(addr)
# define sam_putreg(priv,addr,val) putreg32(val,addr)
@ -472,8 +473,8 @@ static uint32_t sam_getreg(struct sam_gmac_s *priv, uintptr_t address)
****************************************************************************/
#ifdef CONFIG_SAMD5E5_GMAC_REGDEBUG
static void sam_putreg(struct sam_gmac_s *priv, uintptr_t address,
uint32_t regval)
static void sam_putreg(struct sam_gmac_s *priv,
uintptr_t address, uint32_t regval)
{
if (sam_checkreg(priv, true, regval, address))
{
@ -781,8 +782,9 @@ static int sam_transmit(struct sam_gmac_s *priv)
* Function: sam_txpoll
*
* Description:
* The transmitter is available, check if the network has any outgoing packets ready
* to send. This is a callback from devif_poll(). devif_poll() may be called:
* The transmitter is available, check if the network has any outgoing
* packets ready to send. This is a callback from devif_poll().
* devif_poll() may be called:
*
* 1. When the preceding TX packet send is complete,
* 2. When the preceding TX packet send timesout and the interface is reset
@ -854,8 +856,8 @@ static int sam_txpoll(struct net_driver_s *dev)
}
}
/* If zero is returned, the polling will continue until all connections have
* been examined.
/* If zero is returned, the polling will continue until all connections
* have been examined.
*/
return 0;
@ -870,7 +872,8 @@ static int sam_txpoll(struct net_driver_s *dev)
*
* 1. After completion of a transmission (sam_txdone),
* 2. When new TX data is available (sam_txavail), and
* 3. After a TX timeout to restart the sending process (sam_txtimeout_expiry).
* 3. After a TX timeout to restart the sending process
* (sam_txtimeout_expiry).
*
* Input Parameters:
* priv - Reference to the driver state structure
@ -893,7 +896,9 @@ static void sam_dopoll(struct sam_gmac_s *priv)
if (sam_txfree(priv) > 0)
{
/* If we have the descriptor, then poll the network for new XMIT data. */
/* If we have the descriptor,
* then poll the network for new XMIT data.
*/
devif_poll(dev, sam_txpoll);
}
@ -1099,7 +1104,8 @@ static int sam_recvframe(struct sam_gmac_s *priv)
if (pktlen < dev->d_len)
{
nerr("ERROR: Buffer size %d; frame size %d\n", dev->d_len, pktlen);
nerr("ERROR: Buffer size %d; frame size %d\n",
dev->d_len, pktlen);
return -E2BIG;
}
@ -1107,7 +1113,9 @@ static int sam_recvframe(struct sam_gmac_s *priv)
}
}
/* We have not encount the SOF yet... discard this fragment and keep looking */
/* We have not encount the SOF yet...
* discard this fragment and keep looking
*/
else
{
@ -1185,7 +1193,7 @@ static void sam_receive(struct sam_gmac_s *priv)
{
sam_dumppacket("Received packet", dev->d_buf, dev->d_len);
/* Check if the packet is a valid size for the network buffer configuration
/* Check if the packet is a valid size for the network buffer
* (this should not happen)
*/
@ -1196,9 +1204,9 @@ static void sam_receive(struct sam_gmac_s *priv)
}
#ifdef CONFIG_NET_PKT
/* When packet sockets are enabled, feed the frame into the packet tap */
/* When packet sockets are enabled, feed the frame into the tap */
pkt_input(&priv->dev);
pkt_input(&priv->dev);
#endif
/* We only accept IP packets of the configured type and ARP packets */
@ -1216,7 +1224,7 @@ static void sam_receive(struct sam_gmac_s *priv)
ipv4_input(&priv->dev);
/* If the above function invocation resulted in data that should be
* sent out on the network, the field d_len will set to a value > 0.
* sent out on the network, d_len field will set to a value > 0.
*/
if (priv->dev.d_len > 0)
@ -1253,7 +1261,7 @@ static void sam_receive(struct sam_gmac_s *priv)
ipv6_input(&priv->dev);
/* If the above function invocation resulted in data that should be
* sent out on the network, the field d_len will set to a value > 0.
* sent out on the network, d_len field will set to a value > 0.
*/
if (priv->dev.d_len > 0)
@ -1290,7 +1298,7 @@ static void sam_receive(struct sam_gmac_s *priv)
arp_arpin(&priv->dev);
/* If the above function invocation resulted in data that should be
* sent out on the network, the field d_len will set to a value > 0.
* sent out on the network, d_len field will set to a value > 0.
*/
if (priv->dev.d_len > 0)
@ -1339,7 +1347,7 @@ static void sam_txdone(struct sam_gmac_s *priv)
txdesc = &priv->txdesc[priv->txtail];
up_invalidate_dcache((uintptr_t)txdesc,
(uintptr_t)txdesc + sizeof(struct gmac_txdesc_s));
(uintptr_t)txdesc + sizeof(struct gmac_txdesc_s));
/* Is this TX descriptor still in use? */
@ -1348,8 +1356,8 @@ static void sam_txdone(struct sam_gmac_s *priv)
/* Yes.. the descriptor is still in use. However, I have seen a
* case (only repeatable on start-up) where the USED bit is never
* set. Yikes! If we have encountered the first still busy
* descriptor, then we should also have TQBD equal to the descriptor
* address. If it is not, then treat is as used anyway.
* descriptor, then we should also have TQBD equal to the
* descriptor address. If it is not, then treat is as used anyway.
*/
#warning REVISIT
@ -1358,7 +1366,7 @@ static void sam_txdone(struct sam_gmac_s *priv)
{
txdesc->status = (uint32_t)GMACTXD_STA_USED;
up_clean_dcache((uintptr_t)txdesc,
(uintptr_t)txdesc + sizeof(struct gmac_txdesc_s));
(uintptr_t)txdesc + sizeof(struct gmac_txdesc_s));
}
else
{
@ -1432,8 +1440,8 @@ static void sam_interrupt_work(FAR void *arg)
ninfo("isr: %08x pending: %08x\n", isr, pending);
/* Check for the completion of a transmission. This should be done before
* checking for received data (because receiving can cause another transmission
* before we had a chance to handle the last one).
* checking for received data (because receiving can cause another
* transmission before we had a chance to handle the last one).
*
* ISR:TCOMP is set when a frame has been transmitted. Cleared on read.
* TSR:COMP is set when a frame has been transmitted. Cleared by writing a
@ -1583,7 +1591,8 @@ static void sam_interrupt_work(FAR void *arg)
#ifdef CONFIG_DEBUG_NET
/* Check for PAUSE Frame received (PFRE).
*
* ISR:PFRE indicates that a pause frame has been received. Cleared on a read.
* ISR:PFRE indicates that a pause frame has been received.
* Cleared on a read.
*/
if ((pending & GMAC_INT_PFNZ) != 0)
@ -1642,8 +1651,8 @@ static int sam_gmac_interrupt(int irq, void *context, FAR void *arg)
*
* ISR:TCOMP is set when a frame has been transmitted. Cleared on read (so
* we cannot read it here).
* TSR:TXCOMP is set when a frame has been transmitted. Cleared by writing a
* one to this bit.
* TSR:TXCOMP is set when a frame has been transmitted. Cleared by writing
* a one to this bit.
*/
tsr = sam_getreg(priv, SAM_GMAC_TSR_OFFSET);
@ -2208,8 +2217,8 @@ static int sam_addmac(struct net_driver_s *dev, const uint8_t *mac)
* Function: sam_rmmac
*
* Description:
* NuttX Callback: Remove the specified MAC address from the hardware multicast
* address filtering
* NuttX Callback: Remove the specified MAC address from the hardware
* multicast address filtering
*
* Input Parameters:
* dev - Reference to the NuttX driver state structure
@ -2306,9 +2315,9 @@ static int sam_rmmac(struct net_driver_s *dev, const uint8_t *mac)
* specified using the req->reg_no struct field and then write its output
* to the req->val_out field.
*
* When called with SIOCSMIIREG it will write to a register of the PHY that
* is specified using the req->reg_no struct field and use req->val_in as
* its input.
* When called with SIOCSMIIREG it will write to a register of the PHY
* that is specified using the req->reg_no struct field and use req->
* val_in as its input.
*
* Input Parameters:
* dev - Ethernet device structure
@ -2351,7 +2360,8 @@ static int sam_ioctl(struct net_driver_s *dev, int cmd, unsigned long arg)
case SIOCGMIIPHY: /* Get MII PHY address */
{
struct mii_ioctl_data_s *req = (struct mii_ioctl_data_s *)((uintptr_t)arg);
struct mii_ioctl_data_s *req =
(struct mii_ioctl_data_s *)((uintptr_t)arg);
req->phy_id = priv->phyaddr;
ret = OK;
}
@ -2359,7 +2369,8 @@ static int sam_ioctl(struct net_driver_s *dev, int cmd, unsigned long arg)
case SIOCGMIIREG: /* Get register from MII PHY */
{
struct mii_ioctl_data_s *req = (struct mii_ioctl_data_s *)((uintptr_t)arg);
struct mii_ioctl_data_s *req =
(struct mii_ioctl_data_s *)((uintptr_t)arg);
/* Enable the management port */
@ -2377,7 +2388,8 @@ static int sam_ioctl(struct net_driver_s *dev, int cmd, unsigned long arg)
case SIOCSMIIREG: /* Set register in MII PHY */
{
struct mii_ioctl_data_s *req = (struct mii_ioctl_data_s *)((uintptr_t)arg);
struct mii_ioctl_data_s *req =
(struct mii_ioctl_data_s *)((uintptr_t)arg);
/* Enable the management port */
@ -2478,13 +2490,13 @@ static int sam_phyintenable(struct sam_gmac_s *priv)
* interrupts
*/
ret = sam_phyread(priv, priv->phyaddr, GMII_KSZ90x1_ICS, &phyval);
ret = sam_phyread(priv, priv->phyaddr, GMII_KSZ90X1_ICS, &phyval);
if (ret == OK)
{
/* Enable link up/down interrupts */
ret = sam_phywrite(priv, priv->phyaddr, GMII_KSZ90x1_ICS,
(GMII_KSZ90x1_INT_LDEN | GMII_KSZ90x1_INT_LUEN));
ret = sam_phywrite(priv, priv->phyaddr, GMII_KSZ90X1_ICS,
(GMII_KSZ90X1_INT_LDEN | GMII_KSZ90X1_INT_LUEN));
}
/* Disable the management port */
@ -2913,15 +2925,16 @@ static int sam_autonegotiate(struct sam_gmac_s *priv)
#ifdef SAMD5E5_GMAC_PHY_KSZ90x1
/* Set up the KSZ9020/31 PHY */
phyval = GMII_KSZ90x1_RCCPSR | GMII_ERCR_WRITE;
phyval = GMII_KSZ90X1_RCCPSR | GMII_ERCR_WRITE;
sam_phywrite(priv, priv->phyaddr, GMII_ERCR, phyval);
sam_phywrite(priv, priv->phyaddr, GMII_ERDWR, 0xf2f4);
phyval = GMII_KSZ90x1_RRDPSR | GMII_ERCR_WRITE;
phyval = GMII_KSZ90X1_RRDPSR | GMII_ERCR_WRITE;
sam_phywrite(priv, priv->phyaddr, GMII_ERCR, phyval);
sam_phywrite(priv, priv->phyaddr, GMII_ERDWR, 0x2222);
ret = sam_phywrite(priv, priv->phyaddr, GMII_KSZ90x1_ICS, 0xff00);
ret = sam_phywrite(priv, priv->phyaddr,
GMII_KSZ90X1_ICS, 0xff00);
#endif
/* Set the Auto_negotiation Advertisement Register, MII advertising for
@ -3353,9 +3366,8 @@ static void sam_txreset(struct sam_gmac_s *priv)
/* Flush the entire TX descriptor table to RAM */
up_clean_dcache((uintptr_t)txdesc,
(uintptr_t)txdesc +
CONFIG_SAMD5E5_GMAC_NTXBUFFERS * sizeof(struct gmac_txdesc_s));
up_clean_dcache((uintptr_t)txdesc, (uintptr_t)txdesc +
CONFIG_SAMD5E5_GMAC_NTXBUFFERS * sizeof(struct gmac_txdesc_s));
/* Set the Transmit Buffer Queue Base Register */
@ -3417,9 +3429,8 @@ static void sam_rxreset(struct sam_gmac_s *priv)
/* Flush the entire RX descriptor table to RAM */
up_clean_dcache((uintptr_t)rxdesc,
(uintptr_t)rxdesc +
CONFIG_SAMD5E5_GMAC_NRXBUFFERS * sizeof(struct gmac_rxdesc_s));
up_clean_dcache((uintptr_t)rxdesc, (uintptr_t)rxdesc +
CONFIG_SAMD5E5_GMAC_NRXBUFFERS * sizeof(struct gmac_rxdesc_s));
/* Set the Receive Buffer Queue Base Register */
@ -3509,9 +3520,12 @@ static void sam_macaddress(struct sam_gmac_s *priv)
ninfo("%s MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
dev->d_ifname,
dev->d_mac.ether.ether_addr_octet[0], dev->d_mac.ether.ether_addr_octet[1],
dev->d_mac.ether.ether_addr_octet[2], dev->d_mac.ether.ether_addr_octet[3],
dev->d_mac.ether.ether_addr_octet[4], dev->d_mac.ether.ether_addr_octet[5]);
dev->d_mac.ether.ether_addr_octet[0],
dev->d_mac.ether.ether_addr_octet[1],
dev->d_mac.ether.ether_addr_octet[2],
dev->d_mac.ether.ether_addr_octet[3],
dev->d_mac.ether.ether_addr_octet[4],
dev->d_mac.ether.ether_addr_octet[5]);
/* Set the MAC address */
@ -3704,8 +3718,8 @@ static int sam_gmac_configure(struct sam_gmac_s *priv)
GMAC_INT_TUR | GMAC_INT_RLEX | GMAC_INT_TFC | GMAC_INT_TCOMP |
GMAC_INT_ROVR | GMAC_INT_HRESP | GMAC_INT_PFNZ | GMAC_INT_PTZ |
GMAC_INT_PFTR | GMAC_INT_EXINT | GMAC_INT_DRQFR | GMAC_INT_SFR |
GMAC_INT_DRQFT | GMAC_INT_SFT | GMAC_INT_PDRQFR | GMAC_INT_PDRSFR |
GMAC_INT_PDRQFT | GMAC_INT_PDRSFT;
GMAC_INT_DRQFT | GMAC_INT_SFT | GMAC_INT_PDRQFR |
GMAC_INT_PDRSFR | GMAC_INT_PDRQFT | GMAC_INT_PDRSFT;
sam_putreg(priv, SAM_GMAC_IER, regval);
return OK;
}
@ -3790,7 +3804,8 @@ int sam_gmac_initialize(void)
ret = irq_attach(SAM_IRQ_GMAL, sam_gmac_interrupt, NULL);
if (ret < 0)
{
nerr("ERROR: Failed to attach the handler to the IRQ%d\n", SAM_IRQ_GMAL);
nerr("ERROR: Failed to attach the handler to the IRQ%d\n",
SAM_IRQ_GMAL);
goto errout_with_buffers;
}
@ -3804,7 +3819,8 @@ int sam_gmac_initialize(void)
ret = sam_ifdown(&priv->dev);
if (ret < 0)
{
nerr("ERROR: Failed to put the interface in the down state: %d\n", ret);
nerr("ERROR: Failed to put the interface in the down state: %d\n",
ret);
goto errout_with_buffers;
}

176
arch/arm/src/samv7/sam_emac.c
View file

@ -97,6 +97,7 @@
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Configuration ************************************************************/
/* If processing is not done at the interrupt level, then work queue support
@ -410,8 +411,9 @@
#define EMAC1_TX_BUFSIZE (CONFIG_SAMV7_EMAC1_NTXBUFFERS * EMAC_TX_UNITSIZE)
/* Timing *******************************************************************/
/* TX poll delay = 1 seconds. CLK_TCK is the number of clock ticks per
* second
/* TX poll delay = 1 seconds.
* CLK_TCK is the number of clock ticks per second
*/
#define SAM_WDDELAY (1*CLK_TCK)
@ -425,6 +427,7 @@
#define PHY_RETRY_MAX 1000000
/* Helpers ******************************************************************/
/* This is a helper pointer for accessing the contents of the EMAC
* header
*/
@ -434,6 +437,7 @@
/****************************************************************************
* Private Types
****************************************************************************/
/* This structure defines the constant an configured attributes of an EMAC */
struct sam_emacattr_s
@ -452,14 +456,14 @@ struct sam_emacattr_s
uint8_t lsoui; /* LS 2 bits of the 18-bit OUI */
bool rmii; /* True: RMII vs. False: MII */
bool clause45; /* True: Clause 45 behavior */
//bool autoneg; /* True: Autonegotiate rate and *plex */
bool autoneg; /* True: Autonegotiate rate and *plex */
bool sralt; /* True: Alternate PHYSR bit access */
union
{
/* "Standard" form: Individual bits determine speed and half/full
* duplex.
*/
/* "Standard" form: Individual bits determine speed and half/full
* duplex.
*/
struct
{
@ -468,9 +472,9 @@ struct sam_emacattr_s
uint16_t fduplex; /* Full duplex bit */
} std;
/* Alternative form: Speed and duplex are encoded in a single,
* multi-bit field.
*/
/* Alternative form: Speed and duplex are encoded in a single,
* multi-bit field.
*/
struct
{
@ -520,7 +524,7 @@ struct sam_queue_s
uint16_t txtail; /* Buffer tail pointer */
};
/* The sam_emac_s encapsulates all state information for the EMAC peripheral */
/* The sam_emac_s encapsulates all state information for EMAC peripheral */
struct sam_emac_s
{
@ -562,6 +566,7 @@ struct sam_emac_s
/****************************************************************************
* Private Function Prototypes
****************************************************************************/
/* Register operations ******************************************************/
#ifdef CONFIG_SAMV7_EMAC_REGDEBUG
@ -570,7 +575,8 @@ static bool sam_checkreg(struct sam_emac_s *priv, bool wr,
#endif
static uint32_t sam_getreg(struct sam_emac_s *priv, uint16_t offset);
static void sam_putreg(struct sam_emac_s *priv, uint16_t offset, uint32_t val);
static void sam_putreg(struct sam_emac_s *priv,
uint16_t offset, uint32_t val);
/* Buffer management */
@ -704,9 +710,9 @@ static struct emac_rxdesc_s g_emac0_rx1desc[DUMMY_NBUFFERS]
/* EMAC0 Transmit Buffers
*
* Section 3.6 of AMBA 2.0 spec states that burst should not cross 1K Boundaries.
* Receive buffer manager writes are burst of 2 words => 3 lsb bits of the address
* shall be set to 0
* Section 3.6 of AMBA 2.0 spec states that burst should not cross 1K
* Boundaries. Receive buffer manager writes are burst of 2 words => 3
* lsb bits of the address shall be set to 0
*/
static uint8_t g_emac0_tx0buffer[EMAC0_TX_BUFSIZE]
@ -720,9 +726,6 @@ static uint8_t g_emac0_tx1buffer[DUMMY_NBUFFERS * DUMMY_BUFSIZE]
static uint8_t g_emac0_rx0buffer[EMAC0_RX_BUFSIZE]
__attribute__((aligned(EMAC_ALIGN)));
static uint8_t pRxDummyBuffer[DUMMY_NBUFFERS * DUMMY_BUFSIZE]
__attribute__((aligned(EMAC_ALIGN)));
#endif
#ifdef CONFIG_SAMV7_EMAC1
@ -752,9 +755,9 @@ static struct emac_rxdesc_s g_emac1_rx1desc[DUMMY_NBUFFERS]
/* EMAC1 Transmit Buffers
*
* Section 3.6 of AMBA 2.0 spec states that burst should not cross 1K Boundaries.
* Receive buffer manager writes are burst of 2 words => 3 lsb bits of the address
* shall be set to 0
* Section 3.6 of AMBA 2.0 spec states that burst should not cross 1K
* Boundaries. Receive buffer manager writes are burst of 2 words => 3
* lsb bits of the address shall be set to 0
*/
static uint8_t g_emac1_tx1buffer[EMAC1_TX_BUFSIZE]
@ -798,7 +801,7 @@ static const struct sam_emacattr_s g_emac0_attr =
.clause45 = true,
#endif
#ifdef CONFIG_SAMV7_EMAC0_AUTONEG
//.autoneg = true,
.autoneg = true,
#endif
#ifdef CONFIG_SAMV7_EMAC0_PHYSR_ALTCONFIG
.sralt = true,
@ -818,7 +821,8 @@ static const struct sam_emacattr_s g_emac0_attr =
#else
.std =
{
.stdmask = (CONFIG_SAMV7_EMAC0_PHYSR_SPEED | CONFIG_SAMV7_EMAC0_PHYSR_MODE),
.stdmask = CONFIG_SAMV7_EMAC0_PHYSR_SPEED |
CONFIG_SAMV7_EMAC0_PHYSR_MODE,
.speed100 = CONFIG_SAMV7_EMAC0_PHYSR_100MBPS,
.fduplex = CONFIG_SAMV7_EMAC0_PHYSR_FULLDUPLEX,
},
@ -878,7 +882,7 @@ static const struct sam_emacattr_s g_emac1_attr =
.clause45 = true,
#endif
#ifdef CONFIG_SAMV7_EMAC1_AUTONEG
//.autoneg = true,
.autoneg = true,
#endif
#ifdef CONFIG_SAMV7_EMAC1_PHYSR_ALTCONFIG
.sralt = true,
@ -898,7 +902,8 @@ static const struct sam_emacattr_s g_emac1_attr =
#else
.std =
{
.stdmask = (CONFIG_SAMV7_EMAC1_PHYSR_SPEED | CONFIG_SAMV7_EMAC1_PHYSR_MODE),
.stdmask = CONFIG_SAMV7_EMAC1_PHYSR_SPEED |
CONFIG_SAMV7_EMAC1_PHYSR_MODE,
.speed100 = CONFIG_SAMV7_EMAC1_PHYSR_100MBPS,
.fduplex = CONFIG_SAMV7_EMAC1_PHYSR_FULLDUPLEX,
},
@ -947,6 +952,7 @@ static uint8_t g_emac_nqueues = EMAC_NQUEUES_REVA; /* Assume Rev A */
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: sam_checkreg
*
@ -1033,8 +1039,8 @@ static uint32_t sam_getreg(struct sam_emac_s *priv, uint16_t offset)
*
****************************************************************************/
static void sam_putreg(struct sam_emac_s *priv, uint16_t offset,
uint32_t regval)
static void sam_putreg(struct sam_emac_s *priv,
uint16_t offset, uint32_t regval)
{
uintptr_t regaddr = priv->attr->base + (uintptr_t)offset;
@ -1161,8 +1167,9 @@ static int sam_buffer_allocate(struct sam_emac_s *priv)
/* Allocate Queue 0 buffers */
allocsize = EMAC_ALIGN_UP(priv->attr->ntxbuffers * sizeof(struct emac_txdesc_s));
priv->xfrq[0].txdesc = (struct emac_txdesc_s *)kmm_memalign(EMAC_ALIGN, allocsize);
allocsize = EMAC_ALIGN_UP(priv->attr->ntxbuffers *
sizeof(struct emac_txdesc_s));
priv->xfrq[0].txdesc = kmm_memalign(EMAC_ALIGN, allocsize);
if (!priv->xfrq[0].txdesc)
{
nerr("ERROR: Failed to allocate TX descriptors\n");
@ -1172,8 +1179,9 @@ static int sam_buffer_allocate(struct sam_emac_s *priv)
memset(priv->xfrq[0].txdesc, 0, allocsize);
priv->xfrq[0].ntxbuffers = priv->attr->ntxbuffers;
allocsize = EMAC_ALIGN_UP(priv->attr->nrxbuffers * sizeof(struct emac_rxdesc_s));
priv->xfrq[0].rxdesc = (struct emac_rxdesc_s *)kmm_memalign(EMAC_ALIGN, allocsize);
allocsize = EMAC_ALIGN_UP(priv->attr->nrxbuffers *
sizeof(struct emac_rxdesc_s));
priv->xfrq[0].rxdesc = kmm_memalign(EMAC_ALIGN, allocsize);
if (!priv->xfrq[0].rxdesc)
{
nerr("ERROR: Failed to allocate RX descriptors\n");
@ -1209,7 +1217,7 @@ static int sam_buffer_allocate(struct sam_emac_s *priv)
/* Allocate Queue 1 buffers */
allocsize = EMAC_ALIGN_UP(DUMMY_NBUFFERS * sizeof(struct emac_txdesc_s));
priv->xfrq[1].txdesc = (struct emac_txdesc_s *)kmm_memalign(EMAC_ALIGN, allocsize);
priv->xfrq[1].txdesc = kmm_memalign(EMAC_ALIGN, allocsize);
if (!priv->xfrq[1].txdesc)
{
nerr("ERROR: Failed to allocate TX descriptors\n");
@ -1220,7 +1228,7 @@ static int sam_buffer_allocate(struct sam_emac_s *priv)
priv->xfrq[1].ntxbuffers = DUMMY_NBUFFERS;
allocsize = EMAC_ALIGN_UP(DUMMY_NBUFFERS * sizeof(struct emac_rxdesc_s));
priv->xfrq[1].rxdesc = (struct emac_rxdesc_s *)kmm_memalign(EMAC_ALIGN, allocsize);
priv->xfrq[1].rxdesc = kmm_memalign(EMAC_ALIGN, allocsize);
if (!priv->xfrq[1].rxdesc)
{
nerr("ERROR: Failed to allocate RX descriptors\n");
@ -1563,8 +1571,8 @@ static int sam_txpoll(struct net_driver_s *dev)
}
}
/* If zero is returned, the polling will continue until all connections have
* been examined.
/* If zero is returned, the polling will continue until all connections
* have been examined.
*/
return 0;
@ -1605,7 +1613,9 @@ static void sam_dopoll(struct sam_emac_s *priv, int qid)
if (sam_txfree(priv, qid) > 0)
{
/* If we have the descriptor, then poll the network for new XMIT data. */
/* If we have the descriptor,
* then poll the network for new XMIT data.
*/
devif_poll(dev, sam_txpoll);
}
@ -1937,9 +1947,9 @@ static void sam_receive(struct sam_emac_s *priv, int qid)
}
#ifdef CONFIG_NET_PKT
/* When packet sockets are enabled, feed the frame into the packet tap */
/* When packet sockets are enabled, feed the frame into the tap */
pkt_input(&priv->dev);
pkt_input(&priv->dev);
#endif
/* We only accept IP packets of the configured type and ARP packets */
@ -1958,7 +1968,7 @@ static void sam_receive(struct sam_emac_s *priv, int qid)
ipv4_input(&priv->dev);
/* If the above function invocation resulted in data that should be
* sent out on the network, the field d_len will set to a value > 0.
* sent out on the network, d_len field will set to a value > 0.
*/
if (priv->dev.d_len > 0)
@ -1996,7 +2006,7 @@ static void sam_receive(struct sam_emac_s *priv, int qid)
ipv6_input(&priv->dev);
/* If the above function invocation resulted in data that should be
* sent out on the network, the field d_len will set to a value > 0.
* sent out on the network, d_len field will set to a value > 0.
*/
if (priv->dev.d_len > 0)
@ -2034,7 +2044,7 @@ static void sam_receive(struct sam_emac_s *priv, int qid)
arp_arpin(&priv->dev);
/* If the above function invocation resulted in data that should be
* sent out on the network, the field d_len will set to a value > 0.
* sent out on the network, d_len field will set to a value > 0.
*/
if (priv->dev.d_len > 0)
@ -2123,7 +2133,7 @@ static void sam_txdone(struct sam_emac_s *priv, int qid)
txdesc = &xfrq->txdesc[tail];
up_invalidate_dcache((uintptr_t)txdesc,
(uintptr_t)txdesc + sizeof(struct emac_txdesc_s));
(uintptr_t)txdesc + sizeof(struct emac_txdesc_s));
}
/* Go to first buffer of the next frame */
@ -2236,7 +2246,7 @@ static void sam_txerr_interrupt(FAR struct sam_emac_s *priv, int qid)
txdesc = &xfrq->txdesc[tail];
up_invalidate_dcache((uintptr_t)txdesc,
(uintptr_t)txdesc + sizeof(struct emac_txdesc_s));
(uintptr_t)txdesc + sizeof(struct emac_txdesc_s));
}
/* Go to first buffer of the next frame */
@ -2389,17 +2399,18 @@ static void sam_interrupt_work(FAR void *arg)
}
/* Check for the completion of a transmission. This should be done before
* checking for received data (because receiving can cause another transmission
* before we had a chance to handle the last one).
* checking for received data (because receiving can cause another
* transmission before we had a chance to handle the last one).
*
* ISR:TCOMP is set when a frame has been transmitted. Cleared on read.
* TSR:TXCOMP is set when a frame has been transmitted. Cleared by writing a
* one to this bit.
* TSR:TXCOMP is set when a frame has been transmitted. Cleared by writing
* a one to this bit.
*/
if ((pending & EMAC_INT_TCOMP) != 0 || (tsr & EMAC_TSR_TXCOMP) != 0)
{
/* A frame has been transmitted */
/* Check for Retry Limit Exceeded (RLE) */
if ((tsr & EMAC_TSR_RLE) != 0)
@ -2428,7 +2439,8 @@ static void sam_interrupt_work(FAR void *arg)
if ((tsr & EMAC_TSR_TFC) != 0)
{
nerr("ERROR: Transmit Frame Corruption due to AHB error: %08x\n", tsr);
nerr("ERROR: Transmit Frame Corruption due to AHB error: %08x\n",
tsr);
NETDEV_TXERRORS(&priv->dev);
}
@ -2512,8 +2524,8 @@ static int sam_emac_interrupt(int irq, void *context, FAR void *arg)
*
* ISR:TCOMP is set when a frame has been transmitted. Cleared on read (so
* we cannot read it here).
* TSR:TXCOMP is set when a frame has been transmitted. Cleared by writing a
* one to this bit.
* TSR:TXCOMP is set when a frame has been transmitted. Cleared by writing
* a one to this bit.
*/
tsr = sam_getreg(priv, SAM_EMAC_TSR_OFFSET);
@ -2924,7 +2936,8 @@ static unsigned int sam_hashindx(const uint8_t *mac)
unsigned int ndx;
/* Isolate: mac[0]
* ... 05 04 03 02 01 00] */
* ... 05 04 03 02 01 00]
*/
ndx = mac[0];
@ -3094,8 +3107,8 @@ static int sam_addmac(struct net_driver_s *dev, const uint8_t *mac)
* Function: sam_rmmac
*
* Description:
* NuttX Callback: Remove the specified MAC address from the hardware multicast
* address filtering
* NuttX Callback: Remove the specified MAC address from the hardware
* multicast address filtering
*
* Input Parameters:
* dev - Reference to the NuttX driver state structure
@ -3191,9 +3204,9 @@ static int sam_rmmac(struct net_driver_s *dev, const uint8_t *mac)
* specified using the req->reg_no struct field and then write its output
* to the req->val_out field.
*
* When called with SIOCSMIIREG it will write to a register of the PHY that
* is specified using the req->reg_no struct field and use req->val_in as
* its input.
* When called with SIOCSMIIREG it will write to a register of the PHY
* that is specified using the req->reg_no struct field and use req->
* val_in as its input.
*
* Input Parameters:
* dev - Ethernet device structure
@ -3220,7 +3233,8 @@ static int sam_ioctl(struct net_driver_s *dev, int cmd, unsigned long arg)
#ifdef CONFIG_ARCH_PHY_INTERRUPT
case SIOCMIINOTIFY: /* Set up for PHY event notifications */
{
struct mii_ioctl_notify_s *req = (struct mii_ioctl_notify_s *)((uintptr_t)arg);
struct mii_ioctl_notify_s *req =
(struct mii_ioctl_notify_s *)((uintptr_t)arg);
ret = phy_notify_subscribe(dev->d_ifname, req->pid, &req->event);
if (ret == OK)
@ -3235,7 +3249,8 @@ static int sam_ioctl(struct net_driver_s *dev, int cmd, unsigned long arg)
case SIOCGMIIPHY: /* Get MII PHY address */
{
struct mii_ioctl_data_s *req = (struct mii_ioctl_data_s *)((uintptr_t)arg);
struct mii_ioctl_data_s *req =
(struct mii_ioctl_data_s *)((uintptr_t)arg);
req->phy_id = priv->phyaddr;
ret = OK;
}
@ -3243,7 +3258,8 @@ static int sam_ioctl(struct net_driver_s *dev, int cmd, unsigned long arg)
case SIOCGMIIREG: /* Get register from MII PHY */
{
struct mii_ioctl_data_s *req = (struct mii_ioctl_data_s *)((uintptr_t)arg);
struct mii_ioctl_data_s *req =
(struct mii_ioctl_data_s *)((uintptr_t)arg);
uint32_t regval;
/* Enable management port */
@ -3263,7 +3279,8 @@ static int sam_ioctl(struct net_driver_s *dev, int cmd, unsigned long arg)
case SIOCSMIIREG: /* Set register in MII PHY */
{
struct mii_ioctl_data_s *req = (struct mii_ioctl_data_s *)((uintptr_t)arg);
struct mii_ioctl_data_s *req =
(struct mii_ioctl_data_s *)((uintptr_t)arg);
uint32_t regval;
/* Enable management port */
@ -3744,7 +3761,7 @@ static int sam_phyread(struct sam_emac_s *priv, uint8_t phyaddr,
/* Return data */
*phyval = (uint16_t)(sam_getreg(priv, SAM_EMAC_MAN_OFFSET) & EMAC_MAN_DATA_MASK);
*phyval = sam_getreg(priv, SAM_EMAC_MAN_OFFSET) & EMAC_MAN_DATA_MASK;
return OK;
}
@ -4037,6 +4054,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
sam_putreg(priv, SAM_EMAC_NCR_OFFSET, ncr);
errout:
/* Disable management port */
regval = sam_getreg(priv, SAM_EMAC_NCR_OFFSET);
@ -4133,6 +4151,7 @@ static bool sam_linkup(struct sam_emac_s *priv)
linkup = true;
errout:
/* Disable management port */
regval = sam_getreg(priv, SAM_EMAC_NCR_OFFSET);
@ -4168,28 +4187,28 @@ static int sam_phyinit(struct sam_emac_s *priv)
regval &= ~EMAC_NCFGR_CLK_MASK;
mck = BOARD_MCK_FREQUENCY;
if (mck > (240*1000*1000))
if (mck > (240 * 1000 * 1000))
{
nerr("ERROR: Cannot realize PHY clock\n");
return -EINVAL;
}
else if (mck > (160*1000*1000))
else if (mck > (160 * 1000 * 1000))
{
regval |= EMAC_NCFGR_CLK_DIV96; /* MCK divided by 64 (MCK up to 240 MHz) */
}
else if (mck > (120*1000*1000))
else if (mck > (120 * 1000 * 1000))
{
regval |= EMAC_NCFGR_CLK_DIV64; /* MCK divided by 64 (MCK up to 160 MHz) */
}
else if (mck > (80*1000*1000))
else if (mck > (80 * 1000 * 1000))
{
regval |= EMAC_NCFGR_CLK_DIV48; /* MCK divided by 64 (MCK up to 120 MHz) */
}
else if (mck > (40*1000*1000))
else if (mck > (40 * 1000 * 1000))
{
regval |= EMAC_NCFGR_CLK_DIV32; /* MCK divided by 32 (MCK up to 80 MHz) */
}
else if (mck > (20*1000*1000))
else if (mck > (20 * 1000 * 1000))
{
regval |= EMAC_NCFGR_CLK_DIV16; /* MCK divided by 16 (MCK up to 40 MHz) */
}
@ -4373,7 +4392,9 @@ static void sam_txreset(struct sam_emac_s *priv, int qid)
{
bufaddr = (uintptr_t)&txbuffer[ndx * xfrq->txbufsize];
/* Set the buffer address and mark the descriptor as in used by firmware */
/* Set the buffer address and mark the descriptor
* as in used by firmware
*/
txdesc[ndx].addr = bufaddr;
txdesc[ndx].status = EMACTXD_STA_USED;
@ -4674,9 +4695,12 @@ static void sam_macaddress(struct sam_emac_s *priv)
ninfo("%s MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
dev->d_ifname,
dev->d_mac.ether.ether_addr_octet[0], dev->d_mac.ether.ether_addr_octet[1],
dev->d_mac.ether.ether_addr_octet[2], dev->d_mac.ether.ether_addr_octet[3],
dev->d_mac.ether.ether_addr_octet[4], dev->d_mac.ether.ether_addr_octet[5]);
dev->d_mac.ether.ether_addr_octet[0],
dev->d_mac.ether.ether_addr_octet[1],
dev->d_mac.ether.ether_addr_octet[2],
dev->d_mac.ether.ether_addr_octet[3],
dev->d_mac.ether.ether_addr_octet[4],
dev->d_mac.ether.ether_addr_octet[5]);
/* Set the MAC address */
@ -5077,7 +5101,8 @@ int sam_emac_initialize(int intf)
ret = sam_ifdown(&priv->dev);
if (ret < 0)
{
nerr("ERROR: Failed to put the interface in the down state: %d\n", ret);
nerr("ERROR: Failed to put the interface in the down state: %d\n",
ret);
goto errout_with_buffers;
}
@ -5163,9 +5188,12 @@ int sam_emac_setmacaddr(int intf, uint8_t mac[6])
ninfo("%s MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
dev->d_ifname,
dev->d_mac.ether.ether_addr_octet[0], dev->d_mac.ether.ether_addr_octet[1],
dev->d_mac.ether.ether_addr_octet[2], dev->d_mac.ether.ether_addr_octet[3],
dev->d_mac.ether.ether_addr_octet[4], dev->d_mac.ether.ether_addr_octet[5]);
dev->d_mac.ether.ether_addr_octet[0],
dev->d_mac.ether.ether_addr_octet[1],
dev->d_mac.ether.ether_addr_octet[2],
dev->d_mac.ether.ether_addr_octet[3],
dev->d_mac.ether.ether_addr_octet[4],
dev->d_mac.ether.ether_addr_octet[5]);
return OK;
}

537
arch/arm/src/stm32/stm32_eth.c
View file

File diff suppressed because it is too large Load diff

495
arch/arm/src/stm32f7/stm32_ethernet.c
View file

@ -298,8 +298,8 @@
/* Timing *******************************************************************/
/* TX poll delay = 1 seconds. CLK_TCK is the number of clock ticks per
* second
/* TX poll delay = 1 seconds.
* CLK_TCK is the number of clock ticks per second
*/
#define STM32_WDDELAY (1*CLK_TCK)
@ -329,22 +329,22 @@
* are cleared unconditionally). Per the reference manual, all reserved bits
* must be retained at their reset value.
*
* ETH_MACCR_RE Bit 2: Receiver enable
* ETH_MACCR_TE Bit 3: Transmitter enable
* ETH_MACCR_DC Bit 4: Deferral check
* ETH_MACCR_BL Bits 5-6: Back-off limit
* ETH_MACCR_APCS Bit 7: Automatic pad/CRC stripping
* ETH_MACCR_RD Bit 9: Retry disable
* ETH_MACCR_IPCO Bit 10: IPv4 checksum offload
* ETH_MACCR_DM Bit 11: Duplex mode
* ETH_MACCR_LM Bit 12: Loopback mode
* ETH_MACCR_ROD Bit 13: Receive own disable
* ETH_MACCR_FES Bit 14: Fast Ethernet speed
* ETH_MACCR_CSD Bit 16: Carrier sense disable
* ETH_MACCR_IFG Bits 17-19: Interframe gap
* ETH_MACCR_JD Bit 22: Jabber disable
* ETH_MACCR_WD Bit 23: Watchdog disable
* ETH_MACCR_CSTF Bits 25: CRC stripping for Type frames (F2/F4 only)
* ETH_MACCR_RE Bit 2: Receiver enable
* ETH_MACCR_TE Bit 3: Transmitter enable
* ETH_MACCR_DC Bit 4: Deferral check
* ETH_MACCR_BL Bits 5-6: Back-off limit
* ETH_MACCR_APCS Bit 7: Automatic pad/CRC stripping
* ETH_MACCR_RD Bit 9: Retry disable
* ETH_MACCR_IPCO Bit 10: IPv4 checksum offload
* ETH_MACCR_DM Bit 11: Duplex mode
* ETH_MACCR_LM Bit 12: Loopback mode
* ETH_MACCR_ROD Bit 13: Receive own disable
* ETH_MACCR_FES Bit 14: Fast Ethernet speed
* ETH_MACCR_CSD Bit 16: Carrier sense disable
* ETH_MACCR_IFG Bits 17-19: Interframe gap
* ETH_MACCR_JD Bit 22: Jabber disable
* ETH_MACCR_WD Bit 23: Watchdog disable
* ETH_MACCR_CSTF Bits 25: CRC stripping for Type frames (F2/F4 only)
*/
#define MACCR_CLEAR_BITS \
@ -355,20 +355,21 @@
/* The following bits are set or left zero unconditionally in all modes.
*
* ETH_MACCR_RE Receiver enable 0 (disabled)
* ETH_MACCR_TE Transmitter enable 0 (disabled)
* ETH_MACCR_DC Deferral check 0 (disabled)
* ETH_MACCR_BL Back-off limit 0 (10)
* ETH_MACCR_APCS Automatic pad/CRC stripping 0 (disabled)
* ETH_MACCR_RD Retry disable 1 (disabled)
* ETH_MACCR_IPCO IPv4 checksum offload Depends on CONFIG_STM32F7_ETH_HWCHECKSUM
* ETH_MACCR_LM Loopback mode 0 (disabled)
* ETH_MACCR_ROD Receive own disable 0 (enabled)
* ETH_MACCR_CSD Carrier sense disable 0 (enabled)
* ETH_MACCR_IFG Interframe gap 0 (96 bits)
* ETH_MACCR_JD Jabber disable 0 (enabled)
* ETH_MACCR_WD Watchdog disable 0 (enabled)
* ETH_MACCR_CSTF CRC stripping for Type frames 0 (disabled, F2/F4 only)
* ETH_MACCR_RE Receiver enable 0 (disabled)
* ETH_MACCR_TE Transmitter enable 0 (disabled)
* ETH_MACCR_DC Deferral check 0 (disabled)
* ETH_MACCR_BL Back-off limit 0 (10)
* ETH_MACCR_APCS Automatic pad/CRC stripping 0 (disabled)
* ETH_MACCR_RD Retry disable 1 (disabled)
* ETH_MACCR_IPCO IPv4 checksum offload Depends on
* CONFIG_STM32F7_ETH_HWCHECKSUM
* ETH_MACCR_LM Loopback mode 0 (disabled)
* ETH_MACCR_ROD Receive own disable 0 (enabled)
* ETH_MACCR_CSD Carrier sense disable 0 (enabled)
* ETH_MACCR_IFG Interframe gap 0 (96 bits)
* ETH_MACCR_JD Jabber disable 0 (enabled)
* ETH_MACCR_WD Watchdog disable 0 (enabled)
* ETH_MACCR_CSTF CRC stripping for Type frames 0 (disabled, F2/F4 only)
*
* The following are set conditionally based on mode and speed.
*
@ -388,17 +389,17 @@
* are cleared unconditionally). Per the reference manual, all reserved bits
* must be retained at their reset value.
*
* ETH_MACFFR_PM Bit 0: Promiscuous mode
* ETH_MACFFR_HU Bit 1: Hash unicast
* ETH_MACFFR_HM Bit 2: Hash multicast
* ETH_MACFFR_DAIF Bit 3: Destination address inverse filtering
* ETH_MACFFR_PAM Bit 4: Pass all multicast
* ETH_MACFFR_BFD Bit 5: Broadcast frames disable
* ETH_MACFFR_PCF Bits 6-7: Pass control frames
* ETH_MACFFR_SAIF Bit 8: Source address inverse filtering
* ETH_MACFFR_SAF Bit 9: Source address filter
* ETH_MACFFR_HPF Bit 10: Hash or perfect filter
* ETH_MACFFR_RA Bit 31: Receive all
* ETH_MACFFR_PM Bit 0: Promiscuous mode
* ETH_MACFFR_HU Bit 1: Hash unicast
* ETH_MACFFR_HM Bit 2: Hash multicast
* ETH_MACFFR_DAIF Bit 3: Destination address inverse filtering
* ETH_MACFFR_PAM Bit 4: Pass all multicast
* ETH_MACFFR_BFD Bit 5: Broadcast frames disable
* ETH_MACFFR_PCF Bits 6-7: Pass control frames
* ETH_MACFFR_SAIF Bit 8: Source address inverse filtering
* ETH_MACFFR_SAF Bit 9: Source address filter
* ETH_MACFFR_HPF Bit 10: Hash or perfect filter
* ETH_MACFFR_RA Bit 31: Receive all
*/
#define MACFFR_CLEAR_BITS \
@ -408,24 +409,26 @@
/* The following bits are set or left zero unconditionally in all modes.
*
* ETH_MACFFR_PM Promiscuous mode 0 (disabled)
* ETH_MACFFR_HU Hash unicast 0 (perfect dest filtering)
* ETH_MACFFR_HM Hash multicast 0 (perfect dest filtering)
* ETH_MACFFR_DAIF Destination address inverse filtering 0 (normal)
* ETH_MACFFR_PAM Pass all multicast 0 (Depends on HM bit)
* ETH_MACFFR_BFD Broadcast frames disable 0 (enabled)
* ETH_MACFFR_PCF Pass control frames 1 (block all but PAUSE)
* ETH_MACFFR_SAIF Source address inverse filtering 0 (not used)
* ETH_MACFFR_SAF Source address filter 0 (disabled)
* ETH_MACFFR_HPF Hash or perfect filter 0 (Only matching frames passed)
* ETH_MACFFR_RA Receive all 0 (disabled)
* ETH_MACFFR_PM Promiscuous mode 0 (disabled)
* ETH_MACFFR_HU Hash unicast 0 (perfect dest filtering)
* ETH_MACFFR_HM Hash multicast 0 (perfect dest filtering)
* ETH_MACFFR_DAIF Destination address 0 (normal)
* inverse filtering
* ETH_MACFFR_PAM Pass all multicast 0 (Depends on HM bit)
* ETH_MACFFR_BFD Broadcast frames disable 0 (enabled)
* ETH_MACFFR_PCF Pass control frames 1 (block all but PAUSE)
* ETH_MACFFR_SAIF Source address inverse 0 (not used)
* filtering
* ETH_MACFFR_SAF Source address filter 0 (disabled)
* ETH_MACFFR_HPF Hash or perfect filter 0 (Only matching frames passed)
* ETH_MACFFR_RA Receive all 0 (disabled)
*/
#define MACFFR_SET_BITS (ETH_MACFFR_PCF_PAUSE)
/* Clear the MACFCR bits that will be setup during MAC initialization (or that
* are cleared unconditionally). Per the reference manual, all reserved bits
* must be retained at their reset value.
/* Clear the MACFCR bits that will be setup during MAC initialization (or
* that are cleared unconditionally). Per the reference manual, all reserved
* bits must be retained at their reset value.
*
* ETH_MACFCR_FCB_BPA Bit 0: Flow control busy/back pressure activate
* ETH_MACFCR_TFCE Bit 1: Transmit flow control enable
@ -442,33 +445,34 @@
/* The following bits are set or left zero unconditionally in all modes.
*
* ETH_MACFCR_FCB_BPA Flow control busy/back pressure activate 0 (no pause control frame)
* ETH_MACFCR_TFCE Transmit flow control enable 0 (disabled)
* ETH_MACFCR_RFCE Receive flow control enable 0 (disabled)
* ETH_MACFCR_UPFD Unicast pause frame detect 0 (disabled)
* ETH_MACFCR_PLT Pause low threshold 0 (pause time - 4)
* ETH_MACFCR_ZQPD Zero-quanta pause disable 1 (disabled)
* ETH_MACFCR_PT Pause time 0
* ETH_MACFCR_FCB_BPA Flow control busy/back 0 (no pause control frame)
* activate pressure
* ETH_MACFCR_TFCE Transmit flow control enable 0 (disabled)
* ETH_MACFCR_RFCE Receive flow control enable 0 (disabled)
* ETH_MACFCR_UPFD Unicast pause frame detect 0 (disabled)
* ETH_MACFCR_PLT Pause low threshold 0 (pause time - 4)
* ETH_MACFCR_ZQPD Zero-quanta pause disable 1 (disabled)
* ETH_MACFCR_PT Pause time 0
*/
#define MACFCR_SET_MASK (ETH_MACFCR_PLT_M4 | ETH_MACFCR_ZQPD)
/* Clear the DMAOMR bits that will be setup during MAC initialization (or that
* are cleared unconditionally). Per the reference manual, all reserved bits
* must be retained at their reset value.
/* Clear the DMAOMR bits that will be setup during MAC initialization (or
* that are cleared unconditionally). Per the reference manual, all reserved
* bits must be retained at their reset value.
*
* ETH_DMAOMR_SR Bit 1: Start/stop receive
* TH_DMAOMR_OSF Bit 2: Operate on second frame
* ETH_DMAOMR_RTC Bits 3-4: Receive threshold control
* ETH_DMAOMR_FUGF Bit 6: Forward undersized good frames
* ETH_DMAOMR_FEF Bit 7: Forward error frames
* ETH_DMAOMR_ST Bit 13: Start/stop transmission
* ETH_DMAOMR_TTC Bits 14-16: Transmit threshold control
* ETH_DMAOMR_FTF Bit 20: Flush transmit FIFO
* ETH_DMAOMR_TSF Bit 21: Transmit store and forward
* ETH_DMAOMR_DFRF Bit 24: Disable flushing of received frames
* ETH_DMAOMR_RSF Bit 25: Receive store and forward
* TH_DMAOMR_DTCEFD Bit 26: Dropping of TCP/IP checksum error frames disable
* ETH_DMAOMR_SR Bit 1: Start/stop receive
* TH_DMAOMR_OSF Bit 2: Operate on second frame
* ETH_DMAOMR_RTC Bits 3-4: Receive threshold control
* ETH_DMAOMR_FUGF Bit 6: Forward undersized good frames
* ETH_DMAOMR_FEF Bit 7: Forward error frames
* ETH_DMAOMR_ST Bit 13: Start/stop transmission
* ETH_DMAOMR_TTC Bits 14-16: Transmit threshold control
* ETH_DMAOMR_FTF Bit 20: Flush transmit FIFO
* ETH_DMAOMR_TSF Bit 21: Transmit store and forward
* ETH_DMAOMR_DFRF Bit 24: Disable flushing of received frames
* ETH_DMAOMR_RSF Bit 25: Receive store and forward
* TH_DMAOMR_DTCEFD Bit 26: Dropping of TCP/IP checksum error frames disable
*/
#define DMAOMR_CLEAR_MASK \
@ -478,19 +482,23 @@
/* The following bits are set or left zero unconditionally in all modes.
*
* ETH_DMAOMR_SR Start/stop receive 0 (not running)
* TH_DMAOMR_OSF Operate on second frame 1 (enabled)
* ETH_DMAOMR_RTC Receive threshold control 0 (64 bytes)
* ETH_DMAOMR_FUGF Forward undersized good frames 0 (disabled)
* ETH_DMAOMR_FEF Forward error frames 0 (disabled)
* ETH_DMAOMR_ST Start/stop transmission 0 (not running)
* ETH_DMAOMR_TTC Transmit threshold control 0 (64 bytes)
* ETH_DMAOMR_FTF Flush transmit FIFO 0 (no flush)
* ETH_DMAOMR_TSF Transmit store and forward Depends on CONFIG_STM32F7_ETH_HWCHECKSUM
* ETH_DMAOMR_DFRF Disable flushing of received frames 0 (enabled)
* ETH_DMAOMR_RSF Receive store and forward Depends on CONFIG_STM32F7_ETH_HWCHECKSUM
* TH_DMAOMR_DTCEFD Dropping of TCP/IP checksum error Depends on CONFIG_STM32F7_ETH_HWCHECKSUM
* frames disable
* ETH_DMAOMR_SR Start/stop receive 0 (not running)
* TH_DMAOMR_OSF Operate on second frame 1 (enabled)
* ETH_DMAOMR_RTC Receive threshold control 0 (64 bytes)
* ETH_DMAOMR_FUGF Forward undersized good 0 (disabled)
* frames
* ETH_DMAOMR_FEF Forward error frames 0 (disabled)
* ETH_DMAOMR_ST Start/stop transmission 0 (not running)
* ETH_DMAOMR_TTC Transmit threshold control 0 (64 bytes)
* ETH_DMAOMR_FTF Flush transmit FIFO 0 (no flush)
* ETH_DMAOMR_TSF Transmit store and forward Depends on
* CONFIG_STM32F7_ETH_HWCHECKSUM
* ETH_DMAOMR_DFRF Disable flushing of 0 (enabled)
* received frames
* ETH_DMAOMR_RSF Receive store and forward Depends on
* CONFIG_STM32F7_ETH_HWCHECKSUM
* TH_DMAOMR_DTCEFD Dropping of TCP/IP checksum Depends on
* error frames disable CONFIG_STM32F7_ETH_HWCHECKSUM
*
* When the checksum offload feature is enabled, we need to enable the Store
* and Forward mode: the store and forward guarantee that a whole frame is
@ -508,22 +516,22 @@
ETH_DMAOMR_DTCEFD)
#endif
/* Clear the DMABMR bits that will be setup during MAC initialization (or that
* are cleared unconditionally). Per the reference manual, all reserved bits
* must be retained at their reset value.
/* Clear the DMABMR bits that will be setup during MAC initialization (or
* that are cleared unconditionally). Per the reference manual, all reserved
* bits must be retained at their reset value.
*
* ETH_DMABMR_SR Bit 0: Software reset
* ETH_DMABMR_DA Bit 1: DMA Arbitration
* ETH_DMABMR_DSL Bits 2-6: Descriptor skip length
* ETH_DMABMR_EDFE Bit 7: Enhanced descriptor format enable
* ETH_DMABMR_PBL Bits 8-13: Programmable burst length
* ETH_DMABMR_RTPR Bits 14-15: RX TX priority ratio
* ETH_DMABMR_FB Bit 16: Fixed burst
* ETH_DMABMR_RDP Bits 17-22: RX DMA PBL
* ETH_DMABMR_USP Bit 23: Use separate PBL
* ETH_DMABMR_FPM Bit 24: 4xPBL mode
* ETH_DMABMR_AAB Bit 25: Address-aligned beats
* ETH_DMABMR_MB Bit 26: Mixed burst (F2/F4 only)
* ETH_DMABMR_SR Bit 0: Software reset
* ETH_DMABMR_DA Bit 1: DMA Arbitration
* ETH_DMABMR_DSL Bits 2-6: Descriptor skip length
* ETH_DMABMR_EDFE Bit 7: Enhanced descriptor format enable
* ETH_DMABMR_PBL Bits 8-13: Programmable burst length
* ETH_DMABMR_RTPR Bits 14-15: RX TX priority ratio
* ETH_DMABMR_FB Bit 16: Fixed burst
* ETH_DMABMR_RDP Bits 17-22: RX DMA PBL
* ETH_DMABMR_USP Bit 23: Use separate PBL
* ETH_DMABMR_FPM Bit 24: 4xPBL mode
* ETH_DMABMR_AAB Bit 25: Address-aligned beats
* ETH_DMABMR_MB Bit 26: Mixed burst (F2/F4 only)
*/
#define DMABMR_CLEAR_MASK \
@ -534,18 +542,19 @@
/* The following bits are set or left zero unconditionally in all modes.
*
*
* ETH_DMABMR_SR Software reset 0 (no reset)
* ETH_DMABMR_DA DMA Arbitration 0 (round robin)
* ETH_DMABMR_DSL Descriptor skip length 0
* ETH_DMABMR_EDFE Enhanced descriptor format enable Depends on CONFIG_STM32F7_ETH_ENHANCEDDESC
* ETH_DMABMR_PBL Programmable burst length 32 beats
* ETH_DMABMR_RTPR RX TX priority ratio 2:1
* ETH_DMABMR_FB Fixed burst 1 (enabled)
* ETH_DMABMR_RDP RX DMA PBL 32 beats
* ETH_DMABMR_USP Use separate PBL 1 (enabled)
* ETH_DMABMR_FPM 4xPBL mode 0 (disabled)
* ETH_DMABMR_AAB Address-aligned beats 1 (enabled)
* ETH_DMABMR_MB Mixed burst 0 (disabled, F2/F4 only)
* ETH_DMABMR_SR Software reset 0 (no reset)
* ETH_DMABMR_DA DMA Arbitration 0 (round robin)
* ETH_DMABMR_DSL Descriptor skip length 0
* ETH_DMABMR_EDFE Enhanced descriptor Depends on
* format enable CONFIG_STM32F7_ETH_ENHANCEDDESC
* ETH_DMABMR_PBL Programmable burst length 32 beats
* ETH_DMABMR_RTPR RX TX priority ratio 2:1
* ETH_DMABMR_FB Fixed burst 1 (enabled)
* ETH_DMABMR_RDP RX DMA PBL 32 beats
* ETH_DMABMR_USP Use separate PBL 1 (enabled)
* ETH_DMABMR_FPM 4xPBL mode 0 (disabled)
* ETH_DMABMR_AAB Address-aligned beats 1 (enabled)
* ETH_DMABMR_MB Mixed burst 0 (disabled, F2/F4 only)
*/
#ifdef CONFIG_STM32F7_ETH_ENHANCEDDESC
@ -560,9 +569,9 @@
/* Interrupt bit sets *******************************************************/
/* All interrupts in the normal and abnormal interrupt summary. Early transmit
* interrupt (ETI) is excluded from the abnormal set because it causes too
* many interrupts and is not interesting.
/* All interrupts in the normal and abnormal interrupt summary. Early
* transmit interrupt (ETI) is excluded from the abnormal set because it
* causes too many interrupts and is not interesting.
*/
#define ETH_DMAINT_NORMAL \
@ -613,8 +622,8 @@ union stm32_rxdesc_u
struct eth_rxdesc_s rxdesc;
};
/* The stm32_ethmac_s encapsulates all state information for a single hardware
* interface
/* The stm32_ethmac_s encapsulates all state information for a single
* hardware interface
*/
struct stm32_ethmac_s
@ -637,8 +646,8 @@ struct stm32_ethmac_s
struct eth_txdesc_s *txhead; /* Next available TX descriptor */
struct eth_rxdesc_s *rxhead; /* Next available RX descriptor */
struct eth_txdesc_s *txtail; /* First "in_flight" TX descriptor */
struct eth_rxdesc_s *rxcurr; /* First RX descriptor of the segment */
struct eth_txdesc_s *txtail; /* First "in_flight" TX descriptor */
struct eth_rxdesc_s *rxcurr; /* First RX descriptor of the segment */
uint16_t segments; /* RX segment count */
uint16_t inflight; /* Number of TX transfers "in_flight" */
sq_queue_t freeb; /* The free buffer list */
@ -999,7 +1008,8 @@ static inline uint8_t *stm32_allocbuffer(struct stm32_ethmac_s *priv)
*
****************************************************************************/
static inline void stm32_freebuffer(struct stm32_ethmac_s *priv, uint8_t *buffer)
static inline void stm32_freebuffer(struct stm32_ethmac_s *priv,
uint8_t *buffer)
{
/* Free the buffer by adding it to the end of the free buffer list */
@ -1056,8 +1066,8 @@ static int stm32_transmit(struct stm32_ethmac_s *priv)
struct eth_txdesc_s *txdesc;
struct eth_txdesc_s *txfirst;
/* The internal (optimal) network buffer size may be configured to be larger
* than the Ethernet buffer size.
/* The internal (optimal) network buffer size may be configured to be
* larger than the Ethernet buffer size.
*/
#if OPTIMAL_ETH_BUFSIZE > ALIGNED_BUFSIZE
@ -1227,9 +1237,9 @@ static int stm32_transmit(struct stm32_ethmac_s *priv)
ninfo("txhead: %p txtail: %p inflight: %d\n",
priv->txhead, priv->txtail, priv->inflight);
/* If all TX descriptors are in-flight, then we have to disable receive interrupts
* too. This is because receive events can trigger more un-stoppable transmit
* events.
/* If all TX descriptors are in-flight, then we have to disable receive
* interrupts too. This is because receive events can trigger more
* un-stoppable transmit events.
*/
if (priv->inflight >= CONFIG_STM32F7_ETH_NTXDESC)
@ -1267,8 +1277,9 @@ static int stm32_transmit(struct stm32_ethmac_s *priv)
* Function: stm32_txpoll
*
* Description:
* The transmitter is available, check if the network has any outgoing packets ready
* to send. This is a callback from devif_poll(). devif_poll() may be called:
* The transmitter is available, check if the network has any outgoing
* packets ready to send. This is a callback from devif_poll().
* devif_poll() may be called:
*
* 1. When the preceding TX packet send is complete,
* 2. When the preceding TX packet send timesout and the interface is reset
@ -1328,14 +1339,14 @@ static int stm32_txpoll(struct net_driver_s *dev)
stm32_transmit(priv);
DEBUGASSERT(dev->d_len == 0 && dev->d_buf == NULL);
/* Check if the next TX descriptor is owned by the Ethernet DMA or CPU. We
* cannot perform the TX poll if we are unable to accept another packet for
* transmission.
/* Check if the next TX descriptor is owned by the Ethernet DMA or
* CPU. We cannot perform the TX poll if we are unable to accept
* another packet for transmission.
*
* In a race condition, ETH_TDES0_OWN may be cleared BUT still not available
* because stm32_freeframe() has not yet run. If stm32_freeframe() has run,
* the buffer1 pointer (tdes2) will be nullified (and inflight should be <
* CONFIG_STM32F7_ETH_NTXDESC).
* In a race condition, ETH_TDES0_OWN may be cleared BUT still
* not available because stm32_freeframe() has not yet run. If
* stm32_freeframe() has run, the buffer1 pointer (tdes2) will be
* nullified (and inflight should be < CONFIG_STM32F7_ETH_NTXDESC).
*/
if ((priv->txhead->tdes0 & ETH_TDES0_OWN) != 0 ||
@ -1365,8 +1376,8 @@ static int stm32_txpoll(struct net_driver_s *dev)
}
}
/* If zero is returned, the polling will continue until all connections have
* been examined.
/* If zero is returned, the polling will continue until all connections
* have been examined.
*/
return 0;
@ -1403,10 +1414,10 @@ static void stm32_dopoll(struct stm32_ethmac_s *priv)
* CPU. We cannot perform the TX poll if we are unable to accept
* another packet for transmission.
*
* In a race condition, ETH_TDES0_OWN may be cleared BUT still not available
* because stm32_freeframe() has not yet run. If stm32_freeframe() has run,
* the buffer1 pointer (tdes2) will be nullified (and inflight should be <
* CONFIG_STM32F7_ETH_NTXDESC).
* In a race condition, ETH_TDES0_OWN may be cleared BUT still
* not available because stm32_freeframe() has not yet run. If
* stm32_freeframe() has run, the buffer1 pointer (tdes2) will be
* nullified (and inflight should be < CONFIG_STM32F7_ETH_NTXDESC).
*/
if ((priv->txhead->tdes0 & ETH_TDES0_OWN) == 0 &&
@ -1686,7 +1697,8 @@ static int stm32_recvframe(struct stm32_ethmac_s *priv)
* bytes of the CRC
*/
dev->d_len = ((rxdesc->rdes0 & ETH_RDES0_FL_MASK) >> ETH_RDES0_FL_SHIFT) - 4;
dev->d_len = ((rxdesc->rdes0 & ETH_RDES0_FL_MASK) >>
ETH_RDES0_FL_SHIFT) - 4;
/* Get a buffer from the free list. We don't even check if
* this is successful because we already assure the free
@ -1696,9 +1708,9 @@ static int stm32_recvframe(struct stm32_ethmac_s *priv)
buffer = stm32_allocbuffer(priv);
/* Take the buffer from the RX descriptor of the first free
* segment, put it into the network device structure, then replace
* the buffer in the RX descriptor with the newly allocated
* buffer.
* segment, put it into the network device structure, then
* replace the buffer in the RX descriptor with the newly
* allocated buffer.
*/
DEBUGASSERT(dev->d_buf == NULL);
@ -1710,10 +1722,10 @@ static int stm32_recvframe(struct stm32_ethmac_s *priv)
*/
up_clean_dcache((uintptr_t)rxcurr,
(uintptr_t)rxdesc + sizeof(struct eth_rxdesc_s));
(uintptr_t)rxdesc + sizeof(struct eth_rxdesc_s));
/* Remember where we should re-start scanning and reset the segment
* scanning logic
/* Remember where we should re-start scanning and reset the
* segment scanning logic
*/
priv->rxhead = (struct eth_rxdesc_s *)rxdesc->rdes3;
@ -1739,7 +1751,8 @@ static int stm32_recvframe(struct stm32_ethmac_s *priv)
* scanning logic, and continue scanning with the next frame.
*/
nwarn("WARNING: DROPPED RX descriptor errors: %08x\n", rxdesc->rdes0);
nwarn("WARNING: DROPPED RX descriptor errors: %08x\n",
rxdesc->rdes0);
stm32_freesegment(priv, rxcurr, priv->segments);
}
}
@ -1754,8 +1767,9 @@ static int stm32_recvframe(struct stm32_ethmac_s *priv)
(uintptr_t)rxdesc + sizeof(struct eth_rxdesc_s));
}
/* We get here after all of the descriptors have been scanned or when rxdesc points
* to the first descriptor owned by the DMA. Remember where we left off.
/* We get here after all of the descriptors have been scanned or when
* rxdesc points to the first descriptor owned by the DMA. Remember
* where we left off.
*/
priv->rxhead = rxdesc;
@ -1794,13 +1808,13 @@ static void stm32_receive(struct stm32_ethmac_s *priv)
while (stm32_recvframe(priv) == OK)
{
#ifdef CONFIG_NET_PKT
/* When packet sockets are enabled, feed the frame into the packet tap */
/* When packet sockets are enabled, feed the frame into the tap */
pkt_input(&priv->dev);
pkt_input(&priv->dev);
#endif
/* Check if the packet is a valid size for the network buffer configuration
* (this should not happen)
/* Check if the packet is a valid size for the network buffer
* configuration (this should not happen)
*/
if (dev->d_len > CONFIG_NET_ETH_PKTSIZE)
@ -1834,7 +1848,7 @@ static void stm32_receive(struct stm32_ethmac_s *priv)
ipv4_input(&priv->dev);
/* If the above function invocation resulted in data that should be
* sent out on the network, the field d_len will set to a value > 0.
* sent out on the network, d_len field will set to a value > 0.
*/
if (priv->dev.d_len > 0)
@ -1871,7 +1885,7 @@ static void stm32_receive(struct stm32_ethmac_s *priv)
ipv6_input(&priv->dev);
/* If the above function invocation resulted in data that should be
* sent out on the network, the field d_len will set to a value > 0.
* sent out on the network, d_len field will set to a value > 0.
*/
if (priv->dev.d_len > 0)
@ -1908,7 +1922,7 @@ static void stm32_receive(struct stm32_ethmac_s *priv)
arp_arpin(&priv->dev);
/* If the above function invocation resulted in data that should be
* sent out on the network, the field d_len will set to a value > 0.
* sent out on the network, d_len field will set to a value > 0.
*/
if (priv->dev.d_len > 0)
@ -1942,7 +1956,7 @@ static void stm32_receive(struct stm32_ethmac_s *priv)
* Function: stm32_freeframe
*
* Description:
* Scans the TX descriptors and frees the buffers of completed TX transfers.
* Scans the TX descriptors and frees the buffers of completed transfers.
*
* Input Parameters:
* priv - Reference to the driver state structure
@ -2014,8 +2028,9 @@ static void stm32_freeframe(struct stm32_ethmac_s *priv)
priv->inflight--;
/* If all of the TX descriptors were in-flight, then RX interrupts
* may have been disabled... we can re-enable them now.
/* If all of the TX descriptors were in-flight,
* then RX interrupts may have been disabled...
* we can re-enable them now.
*/
stm32_enableint(priv, ETH_DMAINT_RI);
@ -2037,7 +2052,7 @@ static void stm32_freeframe(struct stm32_ethmac_s *priv)
/* Force re-reading of the TX descriptor for physical memory */
up_invalidate_dcache((uintptr_t)txdesc,
(uintptr_t)txdesc + sizeof(struct eth_txdesc_s));
(uintptr_t)txdesc + sizeof(struct eth_txdesc_s));
}
/* We get here if (1) there are still frames "in-flight". Remember
@ -2126,8 +2141,8 @@ static void stm32_interrupt_work(void *arg)
dmasr = stm32_getreg(STM32_ETH_DMASR);
/* Mask only enabled interrupts. This depends on the fact that the interrupt
* related bits (0-16) correspond in these two registers.
/* Mask only enabled interrupts. This depends on the fact that the
* interrupt related bits (0-16) correspond in these two registers.
*/
dmasr &= stm32_getreg(STM32_ETH_DMAIER);
@ -2352,15 +2367,14 @@ static void stm32_poll_work(void *arg)
struct stm32_ethmac_s *priv = (struct stm32_ethmac_s *)arg;
struct net_driver_s *dev = &priv->dev;
/* Check if the next TX descriptor is owned by the Ethernet DMA or CPU. We
* cannot perform the timer poll if we are unable to accept another packet
* for transmission. Hmmm.. might be bug here. Does this mean if there is
* a transmit in progress, we will miss TCP time state updates?
/* Check if the next TX descriptor is owned by the Ethernet DMA or
* CPU. We cannot perform the TX poll if we are unable to accept
* another packet for transmission.
*
* In a race condition, ETH_TDES0_OWN may be cleared BUT still not available
* because stm32_freeframe() has not yet run. If stm32_freeframe() has run,
* the buffer1 pointer (tdes2) will be nullified (and inflight should be <
* CONFIG_STM32F7_ETH_NTXDESC).
* In a race condition, ETH_TDES0_OWN may be cleared BUT still
* not available because stm32_freeframe() has not yet run. If
* stm32_freeframe() has run, the buffer1 pointer (tdes2) will be
* nullified (and inflight should be < CONFIG_STM32F7_ETH_NTXDESC).
*/
net_lock();
@ -2721,8 +2735,8 @@ static int stm32_addmac(struct net_driver_s *dev, const uint8_t *mac)
* Function: stm32_rmmac
*
* Description:
* NuttX Callback: Remove the specified MAC address from the hardware multicast
* address filtering
* NuttX Callback: Remove the specified MAC address from the hardware
* multicast address filtering
*
* Input Parameters:
* dev - Reference to the NuttX driver state structure
@ -2800,12 +2814,11 @@ static int stm32_rmmac(struct net_driver_s *dev, const uint8_t *mac)
static void stm32_txdescinit(struct stm32_ethmac_s *priv,
union stm32_txdesc_u *txtable)
{
struct eth_txdesc_s *txdesc;
int i;
/* priv->txhead will point to the first, available TX descriptor in the chain.
/* priv->txhead point to the first, available TX descriptor in the chain.
* Set the priv->txhead pointer to the first descriptor in the table.
*/
@ -2841,7 +2854,9 @@ static void stm32_txdescinit(struct stm32_ethmac_s *priv,
txdesc->tdes2 = 0;
/* Initialize the next descriptor with the Next Descriptor Polling Enable */
/* Initialize the next descriptor with
* the Next Descriptor Polling Enable
*/
if (i < (CONFIG_STM32F7_ETH_NTXDESC - 1))
{
@ -2931,7 +2946,9 @@ static void stm32_rxdescinit(struct stm32_ethmac_s *priv,
rxdesc->rdes2 = (uint32_t)&rxbuffer[i * ALIGNED_BUFSIZE];
/* Initialize the next descriptor with the Next Descriptor Polling Enable */
/* Initialize the next descriptor with
* the Next Descriptor Polling Enable
*/
if (i < (CONFIG_STM32F7_ETH_NRXDESC - 1))
{
@ -3005,7 +3022,8 @@ static int stm32_ioctl(struct net_driver_s *dev, int cmd, unsigned long arg)
#ifdef CONFIG_ARCH_PHY_INTERRUPT
case SIOCMIINOTIFY: /* Set up for PHY event notifications */
{
struct mii_ioctl_notify_s *req = (struct mii_ioctl_notify_s *)((uintptr_t)arg);
struct mii_ioctl_notify_s *req =
(struct mii_ioctl_notify_s *)((uintptr_t)arg);
ret = phy_notify_subscribe(dev->d_ifname, req->pid, &req->event);
if (ret == OK)
@ -3020,7 +3038,8 @@ static int stm32_ioctl(struct net_driver_s *dev, int cmd, unsigned long arg)
case SIOCGMIIPHY: /* Get MII PHY address */
{
struct mii_ioctl_data_s *req = (struct mii_ioctl_data_s *)((uintptr_t)arg);
struct mii_ioctl_data_s *req =
(struct mii_ioctl_data_s *)((uintptr_t)arg);
req->phy_id = CONFIG_STM32F7_PHYADDR;
ret = OK;
}
@ -3028,14 +3047,16 @@ static int stm32_ioctl(struct net_driver_s *dev, int cmd, unsigned long arg)
case SIOCGMIIREG: /* Get register from MII PHY */
{
struct mii_ioctl_data_s *req = (struct mii_ioctl_data_s *)((uintptr_t)arg);
struct mii_ioctl_data_s *req =
(struct mii_ioctl_data_s *)((uintptr_t)arg);
ret = stm32_phyread(req->phy_id, req->reg_num, &req->val_out);
}
break;
case SIOCSMIIREG: /* Set register in MII PHY */
{
struct mii_ioctl_data_s *req = (struct mii_ioctl_data_s *)((uintptr_t)arg);
struct mii_ioctl_data_s *req =
(struct mii_ioctl_data_s *)((uintptr_t)arg);
ret = stm32_phywrite(req->phy_id, req->reg_num, req->val_in);
}
break;
@ -3095,12 +3116,15 @@ static int stm32_phyintenable(struct stm32_ethmac_s *priv)
*
****************************************************************************/
static int stm32_phyread(uint16_t phydevaddr, uint16_t phyregaddr, uint16_t *value)
static int stm32_phyread(uint16_t phydevaddr,
uint16_t phyregaddr, uint16_t *value)
{
volatile uint32_t timeout;
uint32_t regval;
/* Configure the MACMIIAR register, preserving CSR Clock Range CR[2:0] bits */
/* Configure the MACMIIAR register,
* preserving CSR Clock Range CR[2:0] bits
*/
regval = stm32_getreg(STM32_ETH_MACMIIAR);
regval &= ETH_MACMIIAR_CR_MASK;
@ -3109,8 +3133,8 @@ static int stm32_phyread(uint16_t phydevaddr, uint16_t phyregaddr, uint16_t *val
* the ETH_MACMIIAR_MW is clear, indicating a read operation.
*/
regval |= (((uint32_t)phydevaddr << ETH_MACMIIAR_PA_SHIFT) & ETH_MACMIIAR_PA_MASK);
regval |= (((uint32_t)phyregaddr << ETH_MACMIIAR_MR_SHIFT) & ETH_MACMIIAR_MR_MASK);
regval |= (phydevaddr << ETH_MACMIIAR_PA_SHIFT) & ETH_MACMIIAR_PA_MASK;
regval |= (phyregaddr << ETH_MACMIIAR_MR_SHIFT) & ETH_MACMIIAR_MR_MASK;
regval |= ETH_MACMIIAR_MB;
stm32_putreg(regval, STM32_ETH_MACMIIAR);
@ -3150,12 +3174,15 @@ static int stm32_phyread(uint16_t phydevaddr, uint16_t phyregaddr, uint16_t *val
*
****************************************************************************/
static int stm32_phywrite(uint16_t phydevaddr, uint16_t phyregaddr, uint16_t value)
static int stm32_phywrite(uint16_t phydevaddr,
uint16_t phyregaddr, uint16_t value)
{
volatile uint32_t timeout;
uint32_t regval;
/* Configure the MACMIIAR register, preserving CSR Clock Range CR[2:0] bits */
/* Configure the MACMIIAR register,
* preserving CSR Clock Range CR[2:0] bits
*/
regval = stm32_getreg(STM32_ETH_MACMIIAR);
regval &= ETH_MACMIIAR_CR_MASK;
@ -3164,12 +3191,12 @@ static int stm32_phywrite(uint16_t phydevaddr, uint16_t phyregaddr, uint16_t val
* the ETH_MACMIIAR_MW is set, indicating a write operation.
*/
regval |= (((uint32_t)phydevaddr << ETH_MACMIIAR_PA_SHIFT) & ETH_MACMIIAR_PA_MASK);
regval |= (((uint32_t)phyregaddr << ETH_MACMIIAR_MR_SHIFT) & ETH_MACMIIAR_MR_MASK);
regval |= (phydevaddr << ETH_MACMIIAR_PA_SHIFT) & ETH_MACMIIAR_PA_MASK;
regval |= (phyregaddr << ETH_MACMIIAR_MR_SHIFT) & ETH_MACMIIAR_MR_MASK;
regval |= (ETH_MACMIIAR_MB | ETH_MACMIIAR_MW);
/* Write the value into the MACIIDR register before setting the new MACMIIAR
* register value.
/* Write the value into the MACIIDR register before setting the new
* MACMIIAR register value.
*/
stm32_putreg(value, STM32_ETH_MACMIIDR);
@ -3185,7 +3212,8 @@ static int stm32_phywrite(uint16_t phydevaddr, uint16_t phyregaddr, uint16_t val
}
}
ninfo("MII transfer timed out: phydevaddr: %04x phyregaddr: %04x value: %04x\n",
ninfo("MII transfer timed out: "
"phydevaddr: %04x phyregaddr: %04x value: %04x\n",
phydevaddr, phyregaddr, value);
return -ETIMEDOUT;
@ -3226,7 +3254,9 @@ static inline int stm32_dm9161(struct stm32_ethmac_s *priv)
return ret;
}
/* If we failed to read the PHY ID1 register, the reset the MCU to recover */
/* If we failed to read the PHY ID1 register,
* then reset the MCU to recover
*/
else if (phyval == 0xffff)
{
@ -3235,7 +3265,7 @@ static inline int stm32_dm9161(struct stm32_ethmac_s *priv)
ninfo("PHY ID1: 0x%04X\n", phyval);
/* Now check the "DAVICOM Specified Configuration Register (DSCR)", Register 16 */
/* Now check the "DAVICOM Specified Configuration Register (DSCR)"(16) */
ret = stm32_phyread(CONFIG_STM32F7_PHYADDR, 16, &phyval);
if (ret < 0)
@ -3244,8 +3274,8 @@ static inline int stm32_dm9161(struct stm32_ethmac_s *priv)
return ret;
}
/* Bit 8 of the DSCR register is zero, then the DM9161 has not selected RMII.
* If RMII is not selected, then reset the MCU to recover.
/* Bit 8 of the DSCR register is zero, then the DM9161 has not selected
* RMII. If RMII is not selected, then reset the MCU to recover.
*/
else if ((phyval & (1 << 8)) == 0)
@ -3397,10 +3427,10 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv)
ninfo("PHYSR[%d]: %04x\n", CONFIG_STM32F7_PHYSR, phyval);
/* Different PHYs present speed and mode information in different ways. IF
* This CONFIG_STM32F7_PHYSR_ALTCONFIG is selected, this indicates that the PHY
* represents speed and mode information are combined, for example, with
* separate bits for 10HD, 100HD, 10FD and 100FD.
/* Different PHYs present speed and mode information in different ways.
* IF This CONFIG_STM32F7_PHYSR_ALTCONFIG is selected, this indicates that
* the PHY represents speed and mode information are combined, for example,
* with separate bits for 10HD, 100HD, 10FD and 100FD.
*/
#ifdef CONFIG_STM32F7_PHYSR_ALTCONFIG
@ -3432,14 +3462,15 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv)
break;
}
/* Different PHYs present speed and mode information in different ways. Some
* will present separate information for speed and mode (this is the default).
* Those PHYs, for example, may provide a 10/100 Mbps indication and a separate
* full/half duplex indication.
/* Different PHYs present speed and mode information in different ways.
* Some will present separate information for speed and mode (this is the
* default). Those PHYs, for example, may provide a 10/100 Mbps indication
* and a separate full/half duplex indication.
*/
#else
if ((phyval & CONFIG_STM32F7_PHYSR_MODE) == CONFIG_STM32F7_PHYSR_FULLDUPLEX)
if ((phyval & CONFIG_STM32F7_PHYSR_MODE) ==
CONFIG_STM32F7_PHYSR_FULLDUPLEX)
{
priv->fduplex = 1;
}
@ -3486,7 +3517,7 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv)
return OK;
}
/************************************************************************************
/****************************************************************************
* Name: stm32_selectmii
*
* Description:
@ -3498,7 +3529,7 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv)
* Returned Value:
* None
*
************************************************************************************/
****************************************************************************/
#ifdef CONFIG_STM32F7_MII
static inline void stm32_selectmii(void)
@ -3511,7 +3542,7 @@ static inline void stm32_selectmii(void)
}
#endif
/************************************************************************************
/****************************************************************************
* Name: stm32_selectrmii
*
* Description:
@ -3523,7 +3554,7 @@ static inline void stm32_selectmii(void)
* Returned Value:
* None
*
************************************************************************************/
****************************************************************************/
static inline void stm32_selectrmii(void)
{
@ -3571,8 +3602,8 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv)
/* Provide clocking via MCO, MCO1 or MCO2:
*
* "MCO1 (microcontroller clock output), used to output HSI, LSE, HSE or PLL
* clock (through a configurable prescaler) on PA8 pin."
* "MCO1 (microcontroller clock output), used to output HSI, LSE, HSE or
* PLL clock (through a configurable prescaler) on PA8 pin."
*
* "MCO2 (microcontroller clock output), used to output HSE, PLL, SYSCLK or
* PLLI2S clock (through a configurable prescaler) on PC9 pin."
@ -3603,8 +3634,8 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv)
/* MII interface pins (17):
*
* MII_TX_CLK, MII_TXD[3:0], MII_TX_EN, MII_RX_CLK, MII_RXD[3:0], MII_RX_ER,
* MII_RX_DV, MII_CRS, MII_COL, MDC, MDIO
* MII_TX_CLK, MII_TXD[3:0], MII_TX_EN, MII_RX_CLK, MII_RXD[3:0],
* MII_RX_ER, MII_RX_DV, MII_CRS, MII_COL, MDC, MDIO
*/
stm32_configgpio(GPIO_ETH_MII_COL);
@ -3633,8 +3664,8 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv)
/* Provide clocking via MCO, MCO1 or MCO2:
*
* "MCO1 (microcontroller clock output), used to output HSI, LSE, HSE or PLL
* clock (through a configurable prescaler) on PA8 pin."
* "MCO1 (microcontroller clock output), used to output HSI, LSE, HSE or
* PLL clock (through a configurable prescaler) on PA8 pin."
*
* "MCO2 (microcontroller clock output), used to output HSE, PLL, SYSCLK or
* PLLI2S clock (through a configurable prescaler) on PC9 pin."
@ -3729,7 +3760,7 @@ static void stm32_ethreset(struct stm32_ethmac_s *priv)
stm32_putreg(regval, STM32_ETH_DMABMR);
/* Wait for software reset to complete. The SR bit is cleared automatically
* after the reset operation has completed in all of the core clock domains.
* after the reset operation has completed in all core clock domains.
*/
timeout = MAC_READY_USTIMEOUT;
@ -3846,9 +3877,12 @@ static void stm32_macaddress(struct stm32_ethmac_s *priv)
ninfo("%s MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
dev->d_ifname,
dev->d_mac.ether.ether_addr_octet[0], dev->d_mac.ether.ether_addr_octet[1],
dev->d_mac.ether.ether_addr_octet[2], dev->d_mac.ether.ether_addr_octet[3],
dev->d_mac.ether.ether_addr_octet[4], dev->d_mac.ether.ether_addr_octet[5]);
dev->d_mac.ether.ether_addr_octet[0],
dev->d_mac.ether.ether_addr_octet[1],
dev->d_mac.ether.ether_addr_octet[2],
dev->d_mac.ether.ether_addr_octet[3],
dev->d_mac.ether.ether_addr_octet[4],
dev->d_mac.ether.ether_addr_octet[5]);
/* Set the MAC address high register */
@ -4007,7 +4041,7 @@ static int stm32_macenable(struct stm32_ethmac_s *priv)
* event. The wake-up interrupt is not used by this driver.
*
* The first Ethernet vector is reserved for interrupts generated by the
* MAC and the DMA. The MAC provides PMT and time stamp trigger interrupts,
* MAC and the DMA. The MAC provides PMT and time stamp trigger interrupts,
* neither of which are used by this driver.
*/
@ -4020,7 +4054,8 @@ static int stm32_macenable(struct stm32_ethmac_s *priv)
* events will only be enabled when a transmit interrupt is expected.
*/
stm32_putreg((ETH_DMAINT_RECV_ENABLE | ETH_DMAINT_ERROR_ENABLE), STM32_ETH_DMAIER);
stm32_putreg(ETH_DMAINT_RECV_ENABLE | ETH_DMAINT_ERROR_ENABLE,
STM32_ETH_DMAIER);
return OK;
}
@ -4145,7 +4180,7 @@ int stm32_ethinitialize(int intf)
#ifdef CONFIG_NETDEV_IOCTL
priv->dev.d_ioctl = stm32_ioctl; /* Support PHY ioctl() calls */
#endif
priv->dev.d_private = (void *)g_stm32ethmac; /* Used to recover private state from dev */
priv->dev.d_private = g_stm32ethmac; /* Used to recover private state from dev */
priv->intf = intf; /* Remember the interface number */
/* Create a watchdog for timing polling for and timing of transmissions */
@ -4195,7 +4230,7 @@ int stm32_ethinitialize(int intf)
*
* Description:
* This is the "standard" network initialization logic called from the
* low-level initialization logic in arm_initialize.c. If STM32F7_NETHERNET
* low-level initialization logic in arm_initialize.c. If STM32F7_NETHERNET
* greater than one, then board specific logic will have to supply a
* version of arm_netinitialize() that calls stm32_ethinitialize() with
* the appropriate interface number.

41
arch/arm/src/stm32h7/stm32_ethernet.c
View file

@ -269,8 +269,8 @@
/* Timing *******************************************************************/
/* TX poll delay = 1 seconds. CLK_TCK is the number of clock ticks per
* second
/* TX poll delay = 1 seconds.
* CLK_TCK is the number of clock ticks per second
*/
#define STM32_WDDELAY (1*CLK_TCK)
@ -1355,8 +1355,8 @@ static int stm32_txpoll(struct net_driver_s *dev)
* CPU. We cannot perform the TX poll if we are unable to accept
* another packet for transmission.
*
* In a race condition, ETH_TDES3_OWN may be cleared BUT still not
* available because stm32_freeframe() has not yet run. If
* In a race condition, ETH_TDES3_OWN may be cleared BUT still
* not available because stm32_freeframe() has not yet run. If
* stm32_freeframe() has run, the buffer1 pointer (tdes2) will be
* nullified (and inflight should be < CONFIG_STM32H7_ETH_NTXDESC).
*/
@ -1429,8 +1429,8 @@ static void stm32_dopoll(struct stm32_ethmac_s *priv)
* CPU. We cannot perform the TX poll if we are unable to accept
* another packet for transmission.
*
* In a race condition, ETH_TDES3_RD_OWN may be cleared BUT still not
* available because stm32_freeframe() has not yet run. If
* In a race condition, ETH_TDES3_RD_OWN may be cleared BUT still
* not available because stm32_freeframe() has not yet run. If
* stm32_freeframe() has run, the buffer1 pointer (des0) will be
* nullified (and inflight should be < CONFIG_STM32H7_ETH_NTXDESC).
*/
@ -1848,8 +1848,8 @@ static int stm32_recvframe(struct stm32_ethmac_s *priv)
}
/* We get here after all of the descriptors have been scanned or when
* rxdesc points to the first descriptor owned by the DMA. Remember where
* we left off.
* rxdesc points to the first descriptor owned by the DMA. Remember
* where we left off.
*/
priv->rxhead = rxdesc;
@ -1892,7 +1892,7 @@ static void stm32_receive(struct stm32_ethmac_s *priv)
* tap
*/
pkt_input(&priv->dev);
pkt_input(&priv->dev);
#endif
/* Check if the packet is a valid size for the network buffer
@ -2114,9 +2114,9 @@ static void stm32_freeframe(struct stm32_ethmac_s *priv)
priv->inflight--;
/* If all of the TX descriptors were in-flight, then RX
* interrupts may have been disabled... we can re-enable them
* now.
/* If all of the TX descriptors were in-flight,
* then RX interrupts may have been disabled...
* we can re-enable them now.
*/
stm32_enableint(priv, ETH_DMACIER_RIE);
@ -2454,15 +2454,16 @@ static void stm32_poll_work(void *arg)
struct stm32_ethmac_s *priv = (struct stm32_ethmac_s *)arg;
struct net_driver_s *dev = &priv->dev;
/* Check if the next TX descriptor is owned by the Ethernet DMA or CPU.
* We cannot perform the timer poll if we are unable to accept another
* packet for transmission. Hmmm.. might be bug here. Does this mean if
* there is a transmit in progress, we will miss TCP time state updates?
/* Check if the next TX descriptor is owned by the Ethernet DMA or
* CPU. We cannot perform the timer poll if we are unable to accept
* another packet for transmission. Hmmm.. might be bug here.
* Does this mean if there is a transmit in progress, we will miss
* TCP time state updates?
*
* In a race condition, ETH_TDES3_OWN may be cleared BUT still not
* available because stm32_freeframe() has not yet run. If
* stm32_freeframe() has run, the buffer1 pointer (des2) will be nullified
* (and inflight should be < CONFIG_STM32H7_ETH_NTXDESC).
* In a race condition, ETH_TDES3_OWN may be cleared BUT still
* not available because stm32_freeframe() has not yet run. If
* stm32_freeframe() has run, the buffer1 pointer (des2) will be
* nullified (and inflight should be < CONFIG_STM32H7_ETH_NTXDESC).
*/
net_lock();

113
arch/arm/src/tiva/lm/lm3s_ethernet.c
View file

@ -103,7 +103,9 @@
# define TIVA_DUPLEX_CLRBITS 0
#endif
/* Auto CRC generation can be suppressed if CONFIG_TIVA_ETHNOAUTOCRC is definde */
/* Auto CRC generation can be suppressed
* if CONFIG_TIVA_ETHNOAUTOCRC is defined
*/
#ifdef CONFIG_TIVA_ETHNOAUTOCRC
# define TIVA_CRC_SETBITS 0
@ -159,7 +161,7 @@
#define TIVA_RCTCL_SETBITS (TIVA_AMUL_SETBITS|TIVA_PRMS_SETBITS|TIVA_BADCRC_SETBITS)
#define TIVA_RCTCL_CLRBITS (TIVA_AMUL_CLRBITS|TIVA_PRMS_CLRBITS|TIVA_BADCRC_CLRBITS)
/* CONFIG_TIVA_DUMPPACKET will dump the contents of each packet to the console. */
/* CONFIG_TIVA_DUMPPACKET will dump the contents of each packet. */
#ifdef CONFIG_TIVA_DUMPPACKET
# define tiva_dumppacket(m,a,n) lib_dumpbuffer(m,a,n)
@ -167,7 +169,9 @@
# define tiva_dumppacket(m,a,n)
#endif
/* TX poll deley = 1 seconds. CLK_TCK is the number of clock ticks per second */
/* TX poll deley = 1 seconds.
* CLK_TCK is the number of clock ticks per second
*/
#define TIVA_WDDELAY (1*CLK_TCK)
@ -175,7 +179,7 @@
#define TIVA_TXTIMEOUT (60*CLK_TCK)
/* This is a helper pointer for accessing the contents of the Ethernet header */
/* This is a helper pointer for accessing the contents of Ethernet header */
#define ETHBUF ((struct eth_hdr_s *)priv->ld_dev.d_buf)
@ -231,14 +235,17 @@ static struct tiva_driver_s g_lm3sdev[TIVA_NETHCONTROLLERS];
#if TIVA_NETHCONTROLLERS > 1
static uint32_t tiva_ethin(struct tiva_driver_s *priv, int offset);
static void tiva_ethout(struct tiva_driver_s *priv, int offset, uint32_t value);
static void tiva_ethout(struct tiva_driver_s *priv,
int offset, uint32_t value);
#else
static inline uint32_t tiva_ethin(struct tiva_driver_s *priv, int offset);
static inline void tiva_ethout(struct tiva_driver_s *priv, int offset, uint32_t value);
static inline void tiva_ethout(struct tiva_driver_s *priv,
int offset, uint32_t value);
#endif
static void tiva_ethreset(struct tiva_driver_s *priv);
#if 0 /* Not used */
static void tiva_phywrite(struct tiva_driver_s *priv, int regaddr, uint16_t value);
static void tiva_phywrite(struct tiva_driver_s *priv,
int regaddr, uint16_t value);
#endif
#ifndef CONFIG_TIVA_WITH_QEMU
static uint16_t tiva_phyread(struct tiva_driver_s *priv, int regaddr);
@ -326,12 +333,14 @@ static inline uint32_t tiva_ethin(struct tiva_driver_s *priv, int offset)
****************************************************************************/
#if TIVA_NETHCONTROLLERS > 1
static void tiva_ethout(struct tiva_driver_s *priv, int offset, uint32_t value)
static void tiva_ethout(struct tiva_driver_s *priv,
int offset, uint32_t value)
{
putreg32(value, priv->ld_base + offset);
}
#else
static inline void tiva_ethout(struct tiva_driver_s *priv, int offset, uint32_t value)
static inline void tiva_ethout(struct tiva_driver_s *priv,
int offset, uint32_t value)
{
putreg32(value, TIVA_ETHCON_BASE + offset);
}
@ -362,7 +371,7 @@ static void tiva_ethreset(struct tiva_driver_s *priv)
# error "If multiple interfaces are supported, this function would have to be redesigned"
#endif
/* Make sure that clocking is enabled for the Ethernet (and PHY) peripherals */
/* Make sure that clocking is enabled for the Ethernet&PHY peripherals */
flags = enter_critical_section();
regval = getreg32(TIVA_SYSCON_RCGC2);
@ -386,7 +395,9 @@ static void tiva_ethreset(struct tiva_driver_s *priv)
putreg32(regval, TIVA_SYSCON_SRCR2);
ninfo("SRCR2: %08x\n", regval);
/* Wait just a bit, again. If we touch the ethernet too soon, we may busfault. */
/* Wait just a bit, again.
* If we touch the ethernet too soon, we may busfault.
*/
up_mdelay(2);
@ -429,7 +440,8 @@ static void tiva_ethreset(struct tiva_driver_s *priv)
****************************************************************************/
#if 0 /* Not used */
static void tiva_phywrite(struct tiva_driver_s *priv, int regaddr, uint16_t value)
static void tiva_phywrite(struct tiva_driver_s *priv,
int regaddr, uint16_t value)
{
/* Wait for any MII transactions in progress to complete */
@ -444,7 +456,8 @@ static void tiva_phywrite(struct tiva_driver_s *priv, int regaddr, uint16_t valu
regaddr <<= MAC_MCTL_REGADR_SHIFT;
DEBUGASSERT((regaddr & MAC_MTXD_MASK) == regaddr);
tiva_ethout(priv, TIVA_MAC_MCTL_OFFSET, regaddr | MAC_MCTL_WRITE | MAC_MCTL_START);
tiva_ethout(priv, TIVA_MAC_MCTL_OFFSET,
regaddr | MAC_MCTL_WRITE | MAC_MCTL_START);
/* Wait for the write transaction to complete */
@ -523,7 +536,8 @@ static int tiva_transmit(struct tiva_driver_s *priv)
/* Increment statistics */
NETDEV_TXPACKETS(&priv->ld_dev);
tiva_dumppacket("Transmit packet", priv->ld_dev.d_buf, priv->ld_dev.d_len);
tiva_dumppacket("Transmit packet",
priv->ld_dev.d_buf, priv->ld_dev.d_len);
/* Transfer the packet into the Tx FIFO. The LS 16-bits of the first
* 32-bit word written to the Tx FIFO contains the Ethernet payload
@ -596,8 +610,9 @@ static int tiva_transmit(struct tiva_driver_s *priv)
* Function: tiva_txpoll
*
* Description:
* The transmitter is available, check if the network has any outgoing packets ready
* to send. This is a callback from devif_poll(). devif_poll() may be called:
* The transmitter is available, check if the network has any outgoing
* packets ready to send. This is a callback from devif_poll().
* devif_poll() may be called:
*
* 1. When the preceding TX packet send is complete,
* 2. When the preceding TX packet send timesout and the interface is reset
@ -625,7 +640,7 @@ static int tiva_txpoll(struct net_driver_s *dev)
ninfo("Poll result: d_len=%d\n", priv->ld_dev.d_len);
if (priv->ld_dev.d_len > 0)
{
DEBUGASSERT((tiva_ethin(priv, TIVA_MAC_TR_OFFSET) & MAC_TR_NEWTX) == 0);
DEBUGASSERT(!!(tiva_ethin(priv, TIVA_MAC_TR_OFFSET) & MAC_TR_NEWTX));
/* Look up the destination MAC address and add it to the Ethernet
* header.
@ -659,8 +674,8 @@ static int tiva_txpoll(struct net_driver_s *dev)
}
}
/* If zero is returned, the polling will continue until all connections have
* been examined.
/* If zero is returned, the polling will continue until all connections
* have been examined.
*/
return ret;
@ -721,7 +736,7 @@ static void tiva_receive(struct tiva_driver_s *priv)
* and 4 byte FCS that are not copied into the network packet.
*/
if (pktlen > (CONFIG_NET_ETH_PKTSIZE + 6) || pktlen <= (ETH_HDRLEN + 6))
if (pktlen > CONFIG_NET_ETH_PKTSIZE + 6 || pktlen <= ETH_HDRLEN + 6)
{
int wordlen;
@ -730,8 +745,9 @@ static void tiva_receive(struct tiva_driver_s *priv)
nwarn("WARNING: Bad packet size dropped (%d)\n", pktlen);
NETDEV_RXERRORS(&priv->ld_dev);
/* The number of bytes and words left to read is pktlen - 4 (including,
* the final, possibly partial word) because we've already read 4 bytes.
/* The number of bytes and words left to read is pktlen - 4
* (including, the final, possibly partial word) because we've
* already read 4 bytes.
*/
wordlen = (pktlen - 1) >> 2;
@ -793,15 +809,16 @@ static void tiva_receive(struct tiva_driver_s *priv)
}
}
/* Pass the packet length to the network MINUS 2 bytes for the length and
* 4 bytes for the FCS.
/* Pass the packet length to the network MINUS 2 bytes for the length
* and 4 bytes for the FCS.
*/
priv->ld_dev.d_len = pktlen - 6;
tiva_dumppacket("Received packet", priv->ld_dev.d_buf, priv->ld_dev.d_len);
tiva_dumppacket("Received packet",
priv->ld_dev.d_buf, priv->ld_dev.d_len);
#ifdef CONFIG_NET_PKT
/* When packet sockets are enabled, feed the frame into the packet tap */
/* When packet sockets are enabled, feed the frame into the tap */
pkt_input(&priv->ld_dev);
#endif
@ -822,7 +839,7 @@ static void tiva_receive(struct tiva_driver_s *priv)
ipv4_input(&priv->ld_dev);
/* If the above function invocation resulted in data that should be
* sent out on the network, the field d_len will set to a value > 0.
* sent out on the network, d_len field will set to a value > 0.
*/
if (priv->ld_dev.d_len > 0)
@ -861,7 +878,7 @@ static void tiva_receive(struct tiva_driver_s *priv)
ipv6_input(&priv->ld_dev);
/* If the above function invocation resulted in data that should be
* sent out on the network, the field d_len will set to a value > 0.
* sent out on the network, d_len field will set to a value > 0.
*/
if (priv->dev.d_len > 0)
@ -897,7 +914,7 @@ static void tiva_receive(struct tiva_driver_s *priv)
arp_arpin(&priv->ld_dev);
/* If the above function invocation resulted in data that should be
* sent out on the network, the field d_len will set to a value > 0.
* sent out on the network, d_len field will set to a value > 0.
*/
if (priv->ld_dev.d_len > 0)
@ -1312,8 +1329,8 @@ static int tiva_ifup(struct net_driver_s *dev)
/* Then configure the Ethernet Controller for normal operation
*
* Setup the transmit control register (Full duplex, TX CRC Auto Generation,
* TX Padding Enabled).
* Setup the transmit control register (Full duplex, TX CRC Auto
* Generation, TX Padding Enabled).
*/
regval = tiva_ethin(priv, TIVA_MAC_TCTL_OFFSET);
@ -1534,10 +1551,11 @@ static void tiva_txavail_work(void *arg)
*/
net_lock();
if (priv->ld_bifup && (tiva_ethin(priv, TIVA_MAC_TR_OFFSET) & MAC_TR_NEWTX) == 0)
if (priv->ld_bifup &&
(tiva_ethin(priv, TIVA_MAC_TR_OFFSET) & MAC_TR_NEWTX) == 0)
{
/* If the interface is up and we can use the Tx FIFO, then poll the network
* for new Tx data
/* If the interface is up and we can use the Tx FIFO, then poll the
* network for new Tx data
*/
devif_poll(&priv->ld_dev, tiva_txpoll);
@ -1618,8 +1636,8 @@ static int tiva_addmac(struct net_driver_s *dev, const uint8_t *mac)
* Function: tiva_rmmac
*
* Description:
* NuttX Callback: Remove the specified MAC address from the hardware multicast
* address filtering
* NuttX Callback: Remove the specified MAC address from the hardware
* multicast address filtering
*
* Input Parameters:
* dev - Reference to the NuttX driver state structure
@ -1680,7 +1698,8 @@ static inline int tiva_ethinitialize(int intf)
#if TIVA_NETHCONTROLLERS > 1
# error "This debug check only works with one interface"
#else
DEBUGASSERT((getreg32(TIVA_SYSCON_DC4) & (SYSCON_DC4_EMAC0 | SYSCON_DC4_EPHY0)) ==
DEBUGASSERT((getreg32(TIVA_SYSCON_DC4) &
(SYSCON_DC4_EMAC0 | SYSCON_DC4_EPHY0)) ==
(SYSCON_DC4_EMAC0 | SYSCON_DC4_EPHY0));
#endif
DEBUGASSERT((unsigned)intf < TIVA_NETHCONTROLLERS);
@ -1714,12 +1733,12 @@ static inline int tiva_ethinitialize(int intf)
* is called (and the MAC can be overwritten with a netdev ioctl call).
*/
tiva_ethernetmac(&priv->ld_dev.d_mac.ether);
tiva_ethernetmac(&priv->ld_dev.d_mac.ether);
#endif
/* Perform minimal, one-time initialization -- just reset the controller and
* leave it disabled. The Ethernet controller will be reset and properly
* re-initialized each time tiva_ifup() is called.
/* Perform minimal, one-time initialization -- just reset the controller
* and leave it disabled. The Ethernet controller will be reset and
* properly re-initialized each time tiva_ifup() is called.
*/
tiva_ethreset(priv);
@ -1745,16 +1764,16 @@ static inline int tiva_ethinitialize(int intf)
return OK;
}
/************************************************************************************
/****************************************************************************
* Name: arm_netinitialize
*
* Description:
* Initialize the first network interface. If there are more than one interface
* in the chip, then board-specific logic will have to provide this function to
* determine which, if any, Ethernet controllers should be initialized.
* Initialize the first network interface. If there are more than one
* interface in the chip, then board-specific logic will have to provide
* this function to determine which, if any, Ethernet controllers should
* be initialized.
*
************************************************************************************/
****************************************************************************/
#if TIVA_NETHCONTROLLERS == 1 && !defined(CONFIG_NETDEV_LATEINIT)
void arm_netinitialize(void)

463
arch/arm/src/tiva/tm4c/tm4c_ethernet.c
View file

@ -73,6 +73,7 @@
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Configuration ************************************************************/
#if TIVA_NETHCONTROLLERS > 1
@ -240,6 +241,7 @@
#endif
/* Clocking *****************************************************************/
/* Set MIIADDR CR bits depending on SysClk frequency */
#if SYSCLK_FREQUENCY >= 20000000 && SYSCLK_FREQUENCY < 35000000
@ -257,8 +259,9 @@
#endif
/* Timing *******************************************************************/
/* TX poll delay = 1 seconds. CLK_TCK is the number of clock ticks per
* second
/* TX poll delay = 1 seconds.
* CLK_TCK is the number of clock ticks per second
*/
#define TIVA_WDDELAY (1*CLK_TCK)
@ -303,7 +306,7 @@
* EMAC_CFG_WDDIS Bit 23: Watchdog disable
* EMAC_CFG_CST Bit 25: CRC stripping for Type frames
* EMAC_CFG_TWOKPEN Bit 27: IEEE 802
* EMAC_CFG_SADDR Bits 28-30: Source Address Insertion or Replacement Control
* EMAC_CFG_SADDR Bits 28-30: Source Address Insertion/Replacement Control
*/
#define MACCR_CLEAR_BITS \
@ -314,23 +317,24 @@
/* The following bits are set or left zero unconditionally in all modes.
*
* EMAC_CFG_RE Receiver enable 0 (disabled)
* EMAC_CFG_TE Transmitter enable 0 (disabled)
* EMAC_CFG_DC Deferral check 0 (disabled)
* EMAC_CFG_BL Back-off limit 0 (10)
* EMAC_CFG_ACS Automatic pad/CRC stripping 0 (disabled)
* EMAC_CFG_DR Retry disable 1 (disabled)
* EMAC_CFG_IPC IPv4 checksum offload Depends on CONFIG_TIVA_EMAC_HWCHECKSUM
* EMAC_CFG_LOOPBM Loopback mode 0 (disabled)
* EMAC_CFG_DRO Receive own disable 0 (enabled)
* EMAC_CFG_PS Port Select (read-only)
* EMAC_CFG_DISCRS Carrier sense disable 0 (enabled)
* EMAC_CFG_IFG Interframe gap 0 (96 bits)
* EMAC_CFG_JFEN Jumbo Frame Enable 0 (jumbo frame creates error)
* EMAC_CFG_JD Jabber disable 0 (enabled)
* EMAC_CFG_WDDIS Watchdog disable 0 (enabled)
* EMAC_CFG_CST CRC stripping for Type frames 0 (disabled, F2/F4 only)
* EMAC_CFG_TWOKPEN IEEE 802 0 (>1518 == giant frame)
* EMAC_CFG_RE Receiver enable 0 (disabled)
* EMAC_CFG_TE Transmitter enable 0 (disabled)
* EMAC_CFG_DC Deferral check 0 (disabled)
* EMAC_CFG_BL Back-off limit 0 (10)
* EMAC_CFG_ACS Automatic pad/CRC stripping 0 (disabled)
* EMAC_CFG_DR Retry disable 1 (disabled)
* EMAC_CFG_IPC IPv4 checksum offload Depends on
* CONFIG_TIVA_EMAC_HWCHECKSUM
* EMAC_CFG_LOOPBM Loopback mode 0 (disabled)
* EMAC_CFG_DRO Receive own disable 0 (enabled)
* EMAC_CFG_PS Port Select (read-only)
* EMAC_CFG_DISCRS Carrier sense disable 0 (enabled)
* EMAC_CFG_IFG Interframe gap 0 (96 bits)
* EMAC_CFG_JFEN Jumbo Frame Enable 0 (jumbo frame create error)
* EMAC_CFG_JD Jabber disable 0 (enabled)
* EMAC_CFG_WDDIS Watchdog disable 0 (enabled)
* EMAC_CFG_CST Type frames CRC stripping 0 (disabled, F2/F4 only)
* EMAC_CFG_TWOKPEN IEEE 802 0 (>1518 == giant frame)
* EMAC_CFG_SADDR Source Address Insertion or
* Replacement Control
*
@ -373,25 +377,28 @@
/* The following bits are set or left zero unconditionally in all modes.
*
* EMAC_FRAMEFLTR_PR Promiscuous mode 0 (disabled)
* EMAC_FRAMEFLTR_HUC Hash unicast 0 (perfect dest filtering)
* EMAC_FRAMEFLTR_HMC Hash multicast 0 (perfect dest filtering)
* EMAC_FRAMEFLTR_DAIF Destination address inverse filtering 0 (normal)
* EMAC_FRAMEFLTR_PM Pass all multicast 0 (Depends on HM bit)
* EMAC_FRAMEFLTR_DBF Broadcast frames disable 0 (enabled)
* EMAC_FRAMEFLTR_PCF Pass control frames 1 (block all but PAUSE)
* EMAC_FRAMEFLTR_SAIF Source address inverse filtering 0 (not used)
* EMAC_FRAMEFLTR_SAF Source address filter 0 (disabled)
* EMAC_FRAMEFLTR_HPF Hash or perfect filter 0 (Only matching frames passed)
* EMAC_FRAMEFLTR_VTFE VLAN Tag Filter Enable 0 (VLAN tag ignored)
* EMAC_FRAMEFLTR_RA Receive all 0 (disabled)
* EMAC_FRAMEFLTR_PR Promiscuous mode 0 (disabled)
* EMAC_FRAMEFLTR_HUC Hash unicast 0 (perfect dest filtering)
* EMAC_FRAMEFLTR_HMC Hash multicast 0 (perfect dest filtering)
* EMAC_FRAMEFLTR_DAIF Destination address 0 (normal)
* inverse filtering
* EMAC_FRAMEFLTR_PM Pass all multicast 0 (Depends on HM bit)
* EMAC_FRAMEFLTR_DBF Broadcast frames 0 (enabled)
* disable
* EMAC_FRAMEFLTR_PCF Pass control frames 1 (block all but PAUSE)
* EMAC_FRAMEFLTR_SAIF Source address 0 (not used)
* inverse filtering
* EMAC_FRAMEFLTR_SAF Source address filter 0 (disabled)
* EMAC_FRAMEFLTR_HPF Hash or perfect filter 0 (Only matching frames passed)
* EMAC_FRAMEFLTR_VTFE VLAN Tag Filter Enable 0 (VLAN tag ignored)
* EMAC_FRAMEFLTR_RA Receive all 0 (disabled)
*/
#define FRAMEFLTR_SET_BITS (EMAC_FRAMEFLTR_PCF_PAUSE)
/* Clear the FLOWCTL bits that will be setup during MAC initialization (or that
* are cleared unconditionally). Per the reference manual, all reserved bits
* must be retained at their reset value.
/* Clear the FLOWCTL bits that will be setup during MAC initialization (or
* that are cleared unconditionally). Per the reference manual, all reserved
* bits must be retained at their reset value.
*
* EMAC_FLOWCTL_FCBBPA Bit 0: Flow control busy/back pressure activate
* EMAC_FLOWCTL_TFE Bit 1: Transmit flow control enable
@ -408,20 +415,21 @@
/* The following bits are set or left zero unconditionally in all modes.
*
* EMAC_FLOWCTL_FCBBPA Flow control busy/back pressure activate 0 (no pause control frame)
* EMAC_FLOWCTL_TFE Transmit flow control enable 0 (disabled)
* EMAC_FLOWCTL_RFE Receive flow control enable 0 (disabled)
* EMAC_FLOWCTL_UP Unicast pause frame detect 0 (disabled)
* EMAC_FLOWCTL_PLT Pause low threshold 0 (pause time - 4)
* EMAC_FLOWCTL_DZQP Zero-quanta pause disable 1 (disabled)
* EMAC_FLOWCTL_PT Pause time 0
* EMAC_FLOWCTL_FCBBPA Flow control busy/back 0 (no pause control frame)
* pressure activate
* EMAC_FLOWCTL_TFE Transmit flow control enable 0 (disabled)
* EMAC_FLOWCTL_RFE Receive flow control enable 0 (disabled)
* EMAC_FLOWCTL_UP Unicast pause frame detect 0 (disabled)
* EMAC_FLOWCTL_PLT Pause low threshold 0 (pause time - 4)
* EMAC_FLOWCTL_DZQP Zero-quanta pause disable 1 (disabled)
* EMAC_FLOWCTL_PT Pause time 0
*/
#define FLOWCTL_SET_MASK (EMAC_FLOWCTL_PLT_M4 | EMAC_FLOWCTL_DZQP)
/* Clear the DMAOPMODE bits that will be setup during MAC initialization (or that
* are cleared unconditionally). Per the reference manual, all reserved bits
* must be retained at their reset value.
/* Clear the DMAOPMODE bits that will be setup during MAC initialization (or
* that are cleared unconditionally). Per the reference manual, all reserved
* bits must be retained at their reset value.
*
* EMAC_DMAOPMODE_SR Bit 1: Start/stop receive
* EMAC_DMAOPMODE_OSF Bit 2: Operate on second frame
@ -435,7 +443,8 @@
* EMAC_DMAOPMODE_TSF Bit 21: Transmit store and forward
* EMAC_DMAOPMODE_DFF Bit 24: Disable flushing of received frames
* EMAC_DMAOPMODE_RSF Bit 25: Receive store and forward
* EMAC_DMAOPMODE_DT Bit 26: Dropping of TCP/IP checksum error frames disable
* EMAC_DMAOPMODE_DT Bit 26: Dropping of TCP/IP checksum error
* frames disable
*/
#define DMAOPMODE_CLEAR_MASK \
@ -446,19 +455,23 @@
/* The following bits are set or left zero unconditionally in all modes.
*
* EMAC_DMAOPMODE_SR Start/stop receive 0 (not running)
* EMAC_DMAOPMODE_OSF Operate on second frame 1 (enabled)
* EMAC_DMAOPMODE_RTC Receive threshold control 0 (64 bytes)
* EMAC_DMAOPMODE_FUF Forward undersized good frames 0 (disabled)
* EMAC_DMAOPMODE_FEF Forward error frames 0 (disabled)
* EMAC_DMAOPMODE_ST Start/stop transmission 0 (not running)
* EMAC_DMAOPMODE_TTC Transmit threshold control 0 (64 bytes)
* EMAC_DMAOPMODE_FTF Flush transmit FIFO 0 (no flush)
* EMAC_DMAOPMODE_TSF Transmit store and forward Depends on CONFIG_TIVA_EMAC_HWCHECKSUM
* EMAC_DMAOPMODE_DFF Disable flushing of received frames 0 (enabled)
* EMAC_DMAOPMODE_RSF Receive store and forward Depends on CONFIG_TIVA_EMAC_HWCHECKSUM
* EMAC_DMAOPMODE_DT Dropping of TCP/IP checksum error Depends on CONFIG_TIVA_EMAC_HWCHECKSUM
* frames disable
* EMAC_DMAOPMODE_SR Start/stop receive 0 (not running)
* EMAC_DMAOPMODE_OSF Operate on second frame 1 (enabled)
* EMAC_DMAOPMODE_RTC Receive threshold control 0 (64 bytes)
* EMAC_DMAOPMODE_FUF Forward undersized 0 (disabled)
* good frames
* EMAC_DMAOPMODE_FEF Forward error frames 0 (disabled)
* EMAC_DMAOPMODE_ST Start/stop transmission 0 (not running)
* EMAC_DMAOPMODE_TTC Transmit threshold control 0 (64 bytes)
* EMAC_DMAOPMODE_FTF Flush transmit FIFO 0 (no flush)
* EMAC_DMAOPMODE_TSF Transmit store and forward Depends on
* CONFIG_TIVA_EMAC_HWCHECKSUM
* EMAC_DMAOPMODE_DFF Disable flushing ofs 0 (enabled)
* received frame
* EMAC_DMAOPMODE_RSF Receive store and forward Depends on
* CONFIG_TIVA_EMAC_HWCHECKSUM
* EMAC_DMAOPMODE_DT Dropping of TCP/IP checksum Depends on
* error frames disable CONFIG_TIVA_EMAC_HWCHECKSUM
*
* When the checksum offload feature is enabled, we need to enable the Store
* and Forward mode: the store and forward guarantee that a whole frame is
@ -476,9 +489,9 @@
EMAC_DMAOPMODE_DT)
#endif
/* Clear the DMABUSMOD bits that will be setup during MAC initialization (or that
* are cleared unconditionally). Per the reference manual, all reserved bits
* must be retained at their reset value.
/* Clear the DMABUSMOD bits that will be setup during MAC initialization (or
* that are cleared unconditionally). Per the reference manual, all reserved
* bits must be retained at their reset value.
*
* EMAC_DMABUSMOD_SWR Bit 0: Software reset
* EMAC_DMABUSMOD_DA Bit 1: DMA Arbitration
@ -505,20 +518,24 @@
/* The following bits are set or left zero unconditionally in all modes.
*
* EMAC_DMABUSMOD_SWR Software reset 0 (no reset)
* EMAC_DMABUSMOD_DA DMA Arbitration 1 (fixed priority)
* EMAC_DMABUSMOD_DSL Descriptor skip length 0
* EMAC_DMABUSMOD_ATDS Enhanced descriptor format enable Depends on CONFIG_TIVA_EMAC_ENHANCEDDESC
* EMAC_DMABUSMOD_PBL Programmable burst length Depends on EMAC_DMA_RXBURST
* EMAC_DMABUSMOD_PR RX TX priority ratio 0 1:1
* EMAC_DMABUSMOD_FB Fixed burst 0 (disabled)
* EMAC_DMABUSMOD_RPBL RX DMA programmable burst length Depends on EMAC_DMA_TXBURST
* EMAC_DMABUSMOD_USP Use separate PBL Depends on EMAC_DMA_RX/TXBURST
* EMAC_DMABUSMOD_8XPBL 8x programmable burst length mode Depends on EMAC_DMA_RX/TXBURST
* EMAC_DMABUSMOD_AAL Address-aligned beats 0 (disabled)
* EMAC_DMABUSMOD_MB Mixed burst 1 (enabled)
* EMAC_DMABUSMOD_TXPR Transmit Priority 0 (RX DMA has priority over TX)
* EMAC_DMABUSMOD_RIB Rebuild Burst 0
* EMAC_DMABUSMOD_SWR Software reset 0 (no reset)
* EMAC_DMABUSMOD_DA DMA Arbitration 1 (fixed priority)
* EMAC_DMABUSMOD_DSL Descriptor skip length 0
* EMAC_DMABUSMOD_ATDS Enhanced descriptor Depends on
* format enable CONFIG_TIVA_EMAC_ENHANCEDDESC
* EMAC_DMABUSMOD_PBL Programmable burst Depends on EMAC_DMA_RXBURST
* length
* EMAC_DMABUSMOD_PR RX TX priority ratio 0 1:1
* EMAC_DMABUSMOD_FB Fixed burst 0 (disabled)
* EMAC_DMABUSMOD_RPBL RX DMA programmable Depends on EMAC_DMA_TXBURST
* burst length
* EMAC_DMABUSMOD_USP Use separate PBL Depends on EMAC_DMA_RX/TXBURST
* EMAC_DMABUSMOD_8XPBL 8x programmable burst Depends on EMAC_DMA_RX/TXBURST
* length mode
* EMAC_DMABUSMOD_AAL Address-aligned beats 0(disabled)
* EMAC_DMABUSMOD_MB Mixed burst 1(enabled)
* EMAC_DMABUSMOD_TXPR Transmit Priority 0(RX DMA has priority over TX)
* EMAC_DMABUSMOD_RIB Rebuild Burst 0
*/
#define EMAC_DMA_RXBURST 4
@ -564,9 +581,10 @@
__EMAC_DMABUSMOD_8XPBL | EMAC_DMABUSMOD_MB)
/* Interrupt bit sets *******************************************************/
/* All interrupts in the normal and abnormal interrupt summary. Early transmit
* interrupt (ETI) is excluded from the abnormal set because it causes too
* many interrupts and is not interesting.
/* All interrupts in the normal and abnormal interrupt summary. Early
* transmit interrupt (ETI) is excluded from the abnormal set because it
* causes too many interrupts and is not interesting.
*/
#define EMAC_DMAINT_NORMAL \
@ -590,6 +608,7 @@
#endif
/* Helpers ******************************************************************/
/* This is a helper pointer for accessing the contents of the Ethernet
* header
*/
@ -654,6 +673,7 @@ static struct tiva_ethmac_s g_tiva_ethmac[TIVA_NETHCONTROLLERS];
/****************************************************************************
* Private Function Prototypes
****************************************************************************/
/* Register operations ******************************************************/
#if defined(CONFIG_TIVA_ETHERNET_REGDEBUG) && defined(CONFIG_DEBUG_INFO)
@ -811,7 +831,7 @@ static uint32_t tiva_getreg(uint32_t addr)
{
/* Yes.. then show how many times the value repeated */
_info("[repeats %d more times]\n", count-3);
_info("[repeats %d more times]\n", count - 3);
}
/* Save the new address, value, and count */
@ -961,7 +981,8 @@ static inline uint8_t *tiva_allocbuffer(FAR struct tiva_ethmac_s *priv)
*
****************************************************************************/
static inline void tiva_freebuffer(FAR struct tiva_ethmac_s *priv, uint8_t *buffer)
static inline void tiva_freebuffer(FAR struct tiva_ethmac_s *priv,
uint8_t *buffer)
{
/* Free the buffer by adding it to the end of the free buffer list */
@ -1018,8 +1039,8 @@ static int tiva_transmit(FAR struct tiva_ethmac_s *priv)
struct emac_txdesc_s *txdesc;
struct emac_txdesc_s *txfirst;
/* The internal (optimal) network buffer size may be configured to be larger
* than the Ethernet buffer size.
/* The internal (optimal) network buffer size may be configured to be
* larger than the Ethernet buffer size.
*/
#if OPTIMAL_EMAC_BUFSIZE > OPTIMAL_EMAC_BUFSIZE
@ -1051,7 +1072,8 @@ static int tiva_transmit(FAR struct tiva_ethmac_s *priv)
{
/* Yes... how many buffers will be need to send the packet? */
bufcount = (priv->dev.d_len + (OPTIMAL_EMAC_BUFSIZE-1)) / OPTIMAL_EMAC_BUFSIZE;
bufcount = (priv->dev.d_len + (OPTIMAL_EMAC_BUFSIZE - 1)) /
OPTIMAL_EMAC_BUFSIZE;
lastsize = priv->dev.d_len - (bufcount - 1) * OPTIMAL_EMAC_BUFSIZE;
ninfo("bufcount: %d lastsize: %d\n", bufcount, lastsize);
@ -1076,7 +1098,7 @@ static int tiva_transmit(FAR struct tiva_ethmac_s *priv)
/* Set the buffer size in all TX descriptors */
if (i == (bufcount-1))
if (i == (bufcount - 1))
{
/* This is the last segment. Set the last segment bit in the
* last TX descriptor and ask for an interrupt when this
@ -1167,9 +1189,9 @@ static int tiva_transmit(FAR struct tiva_ethmac_s *priv)
ninfo("txhead: %p txtail: %p inflight: %d\n",
priv->txhead, priv->txtail, priv->inflight);
/* If all TX descriptors are in-flight, then we have to disable receive interrupts
* too. This is because receive events can trigger more un-stoppable transmit
* events.
/* If all TX descriptors are in-flight, then we have to disable receive
* interrupts too. This is because receive events can trigger more un-
* stoppable transmit events.
*/
if (priv->inflight >= CONFIG_TIVA_EMAC_NTXDESC)
@ -1205,8 +1227,9 @@ static int tiva_transmit(FAR struct tiva_ethmac_s *priv)
* Function: tiva_txpoll
*
* Description:
* The transmitter is available, check if the network has any outgoing packets ready
* to send. This is a callback from devif_poll(). devif_poll() may be called:
* The transmitter is available, check if the network has any outgoing
* packets ready to send. This is a callback from devif_poll().
* devif_poll() may be called:
*
* 1. When the preceding TX packet send is complete,
* 2. When the preceding TX packet send timesout and the interface is reset
@ -1227,7 +1250,8 @@ static int tiva_transmit(FAR struct tiva_ethmac_s *priv)
static int tiva_txpoll(struct net_driver_s *dev)
{
FAR struct tiva_ethmac_s *priv = (FAR struct tiva_ethmac_s *)dev->d_private;
FAR struct tiva_ethmac_s *priv =
(FAR struct tiva_ethmac_s *)dev->d_private;
DEBUGASSERT(priv->dev.d_buf != NULL);
@ -1266,14 +1290,14 @@ static int tiva_txpoll(struct net_driver_s *dev)
tiva_transmit(priv);
DEBUGASSERT(dev->d_len == 0 && dev->d_buf == NULL);
/* Check if the next TX descriptor is owned by the Ethernet DMA or CPU. We
* cannot perform the TX poll if we are unable to accept another packet for
* transmission.
/* Check if the next TX descriptor is owned by the Ethernet DMA or
* CPU. We cannot perform the TX poll if we are unable to accept
* another packet for transmission.
*
* In a race condition, EMAC_TDES0_OWN may be cleared BUT still not available
* because tiva_freeframe() has not yet run. If tiva_freeframe() has run,
* the buffer1 pointer (tdes2) will be nullified (and inflight should be <
* CONFIG_TIVA_EMAC_NTXDESC).
* In a race condition, EMAC_TDES0_OWN may be cleared BUT still
* not available because tiva_freeframe() has not yet run. If
* tiva_freeframe() has run, the buffer1 pointer (tdes2) will be
* nullified (and inflight should be < CONFIG_TIVA_EMAC_NTXDESC).
*/
if ((priv->txhead->tdes0 & EMAC_TDES0_OWN) != 0 ||
@ -1303,8 +1327,8 @@ static int tiva_txpoll(struct net_driver_s *dev)
}
}
/* If zero is returned, the polling will continue until all connections have
* been examined.
/* If zero is returned, the polling will continue until all connections
* have been examined.
*/
return 0;
@ -1341,10 +1365,10 @@ static void tiva_dopoll(FAR struct tiva_ethmac_s *priv)
* CPU. We cannot perform the TX poll if we are unable to accept
* another packet for transmission.
*
* In a race condition, EMAC_TDES0_OWN may be cleared BUT still not available
* because tiva_freeframe() has not yet run. If tiva_freeframe() has run,
* the buffer1 pointer (tdes2) will be nullified (and inflight should be <
* CONFIG_TIVA_EMAC_NTXDESC).
* In a race condition, EMAC_TDES0_OWN may be cleared BUT still
* not available because tiva_freeframe() has not yet run. If
* tiva_freeframe() has run, the buffer1 pointer (tdes2) will be
* nullified (and inflight should be < CONFIG_TIVA_EMAC_NTXDESC).
*/
if ((priv->txhead->tdes0 & EMAC_TDES0_OWN) == 0 &&
@ -1462,7 +1486,7 @@ static void tiva_disableint(FAR struct tiva_ethmac_s *priv, uint32_t ierbit)
****************************************************************************/
static void tiva_freesegment(FAR struct tiva_ethmac_s *priv,
FAR struct emac_rxdesc_s *rxfirst, int segments)
FAR struct emac_rxdesc_s *rxfirst, int segments)
{
struct emac_rxdesc_s *rxdesc;
int i;
@ -1604,7 +1628,8 @@ static int tiva_recvframe(FAR struct tiva_ethmac_s *priv)
* bytes of the CRC
*/
dev->d_len = ((rxdesc->rdes0 & EMAC_RDES0_FL_MASK) >> EMAC_RDES0_FL_SHIFT) - 4;
dev->d_len = ((rxdesc->rdes0 & EMAC_RDES0_FL_MASK) >>
EMAC_RDES0_FL_SHIFT) - 4;
/* Get a buffer from the free list. We don't even check if
* this is successful because we already assure the free
@ -1614,17 +1639,17 @@ static int tiva_recvframe(FAR struct tiva_ethmac_s *priv)
buffer = tiva_allocbuffer(priv);
/* Take the buffer from the RX descriptor of the first free
* segment, put it into the network device structure, then replace
* the buffer in the RX descriptor with the newly allocated
* buffer.
* segment, put it into the network device structure, then
* replace the buffer in the RX descriptor with the newly
* allocated buffer.
*/
DEBUGASSERT(dev->d_buf == NULL);
dev->d_buf = (uint8_t *)rxcurr->rdes2;
rxcurr->rdes2 = (uint32_t)buffer;
/* Return success, remembering where we should re-start scanning
* and resetting the segment scanning logic
/* Return success, remembering where we should re-start
* scanning and resetting the segment scanning logic
*/
priv->rxhead = (struct emac_rxdesc_s *)rxdesc->rdes3;
@ -1651,8 +1676,9 @@ static int tiva_recvframe(FAR struct tiva_ethmac_s *priv)
rxdesc = (struct emac_rxdesc_s *)rxdesc->rdes3;
}
/* We get here after all of the descriptors have been scanned or when rxdesc points
* to the first descriptor owned by the DMA. Remember where we left off.
/* We get here after all of the descriptors have been scanned or when
* rxdesc points to the first descriptor owned by the DMA. Remember
* where we left off.
*/
priv->rxhead = rxdesc;
@ -1691,13 +1717,13 @@ static void tiva_receive(FAR struct tiva_ethmac_s *priv)
while (tiva_recvframe(priv) == OK)
{
#ifdef CONFIG_NET_PKT
/* When packet sockets are enabled, feed the frame into the packet tap */
/* When packet sockets are enabled, feed the frame into the tap */
pkt_input(&priv->dev);
pkt_input(&priv->dev);
#endif
/* Check if the packet is a valid size for the network buffer configuration
* (this should not happen)
/* Check if the packet is a valid size for the network buffer
* configuration (this should not happen)
*/
if (dev->d_len > CONFIG_NET_ETH_PKTSIZE)
@ -1721,7 +1747,7 @@ static void tiva_receive(FAR struct tiva_ethmac_s *priv)
ipv4_input(&priv->dev);
/* If the above function invocation resulted in data that should be
* sent out on the network, the field d_len will set to a value > 0.
* sent out on the network, d_len field will set to a value > 0.
*/
if (priv->dev.d_len > 0)
@ -1740,6 +1766,7 @@ static void tiva_receive(FAR struct tiva_ethmac_s *priv)
neighbor_out(&priv->dev);
}
#endif
/* And send the packet */
tiva_transmit(priv);
@ -1757,7 +1784,7 @@ static void tiva_receive(FAR struct tiva_ethmac_s *priv)
ipv6_input(&priv->dev);
/* If the above function invocation resulted in data that should be
* sent out on the network, the field d_len will set to a value > 0.
* sent out on the network, d_len field will set to a value > 0.
*/
if (priv->dev.d_len > 0)
@ -1794,7 +1821,7 @@ static void tiva_receive(FAR struct tiva_ethmac_s *priv)
arp_arpin(&priv->dev);
/* If the above function invocation resulted in data that should be
* sent out on the network, the field d_len will set to a value > 0.
* sent out on the network, d_len field will set to a value > 0.
*/
if (priv->dev.d_len > 0)
@ -1828,7 +1855,7 @@ static void tiva_receive(FAR struct tiva_ethmac_s *priv)
* Function: tiva_freeframe
*
* Description:
* Scans the TX descriptors and frees the buffers of completed TX transfers.
* Scans the TX descriptors and frees the buffers of completed transfers.
*
* Input Parameters:
* priv - Reference to the driver state structure
@ -1888,8 +1915,9 @@ static void tiva_freeframe(FAR struct tiva_ethmac_s *priv)
priv->inflight--;
/* If all of the TX descriptors were in-flight, then RX interrupts
* may have been disabled... we can re-enable them now.
/* If all of the TX descriptors were in-flight,
* then RX interrupts may have been disabled...
* we can re-enable them now.
*/
tiva_enableint(priv, EMAC_DMAINT_RI);
@ -1999,8 +2027,8 @@ static void tiva_interrupt_work(FAR void *arg)
dmaris = tiva_getreg(TIVA_EMAC_DMARIS);
/* Mask only enabled interrupts. This depends on the fact that the interrupt
* related bits (0-16) correspond in these two registers.
/* Mask only enabled interrupts. This depends on the fact that the
* interrupt related bits (0-16) correspond in these two registers.
*/
dmaris &= tiva_getreg(TIVA_EMAC_DMAIM);
@ -2240,15 +2268,14 @@ static void tiva_poll_work(FAR void *arg)
FAR struct tiva_ethmac_s *priv = (FAR struct tiva_ethmac_s *)arg;
FAR struct net_driver_s *dev = &priv->dev;
/* Check if the next TX descriptor is owned by the Ethernet DMA or CPU. We
* cannot perform the timer poll if we are unable to accept another packet
* for transmission. Hmmm.. might be bug here. Does this mean if there is
* a transmit in progress, we will miss TCP time state updates?
/* Check if the next TX descriptor is owned by the Ethernet DMA or
* CPU. We cannot perform the TX poll if we are unable to accept
* another packet for transmission.
*
* In a race condition, EMAC_TDES0_OWN may be cleared BUT still not available
* because tiva_freeframe() has not yet run. If tiva_freeframe() has run,
* the buffer1 pointer (tdes2) will be nullified (and inflight should be <
* CONFIG_TIVA_EMAC_NTXDESC).
* In a race condition, EMAC_TDES0_OWN may be cleared BUT still
* not available because tiva_freeframe() has not yet run. If
* tiva_freeframe() has run, the buffer1 pointer (tdes2) will be
* nullified (and inflight should be < CONFIG_TIVA_EMAC_NTXDESC).
*/
net_lock();
@ -2337,7 +2364,8 @@ static void tiva_poll_expiry(int argc, wdparm_t arg, ...)
static int tiva_ifup(struct net_driver_s *dev)
{
FAR struct tiva_ethmac_s *priv = (FAR struct tiva_ethmac_s *)dev->d_private;
FAR struct tiva_ethmac_s *priv =
(FAR struct tiva_ethmac_s *)dev->d_private;
int ret;
#ifdef CONFIG_NET_IPv4
@ -2392,7 +2420,8 @@ static int tiva_ifup(struct net_driver_s *dev)
static int tiva_ifdown(struct net_driver_s *dev)
{
FAR struct tiva_ethmac_s *priv = (FAR struct tiva_ethmac_s *)dev->d_private;
FAR struct tiva_ethmac_s *priv =
(FAR struct tiva_ethmac_s *)dev->d_private;
irqstate_t flags;
ninfo("Taking the network down\n");
@ -2478,7 +2507,8 @@ static void tiva_txavail_work(FAR void *arg)
static int tiva_txavail(struct net_driver_s *dev)
{
FAR struct tiva_ethmac_s *priv = (FAR struct tiva_ethmac_s *)dev->d_private;
FAR struct tiva_ethmac_s *priv =
(FAR struct tiva_ethmac_s *)dev->d_private;
/* Is our single work structure available? It may not be if there are
* pending interrupt actions and we will have to ignore the Tx
@ -2526,6 +2556,7 @@ static uint32_t tiva_calcethcrc(const uint8_t *data, size_t length)
if (((crc >> 31) ^ (data[i] >> j)) & 0x01)
{
/* x^26+x^23+x^22+x^16+x^12+x^11+x^10+x^8+x^7+x^5+x^4+x^2+x+1 */
crc = (crc << 1) ^ 0x04c11db7;
}
else
@ -2572,7 +2603,7 @@ static int tiva_addmac(struct net_driver_s *dev, FAR const uint8_t *mac)
crc = tiva_calcethcrc(mac, 6);
hashindex = (crc >> 26) & 0x3F;
hashindex = (crc >> 26) & 0x3f;
if (hashindex > 31)
{
@ -2600,8 +2631,8 @@ static int tiva_addmac(struct net_driver_s *dev, FAR const uint8_t *mac)
* Function: tiva_rmmac
*
* Description:
* NuttX Callback: Remove the specified MAC address from the hardware multicast
* address filtering
* NuttX Callback: Remove the specified MAC address from the hardware
* multicast address filtering
*
* Input Parameters:
* dev - Reference to the NuttX driver state structure
@ -2629,7 +2660,7 @@ static int tiva_rmmac(struct net_driver_s *dev, FAR const uint8_t *mac)
crc = tiva_calcethcrc(mac, 6);
hashindex = (crc >> 26) & 0x3F;
hashindex = (crc >> 26) & 0x3f;
if (hashindex > 31)
{
@ -2680,8 +2711,9 @@ static void tiva_txdescinit(FAR struct tiva_ethmac_s *priv)
struct emac_txdesc_s *txdesc;
int i;
/* priv->txhead will point to the first, available TX descriptor in the chain.
* Set the priv->txhead pointer to the first descriptor in the table.
/* priv->txhead will point to the first, available TX descriptor in the
* chain. Set the priv->txhead pointer to the first descriptor in the
* table.
*/
priv->txhead = priv->txtable;
@ -2691,8 +2723,8 @@ static void tiva_txdescinit(FAR struct tiva_ethmac_s *priv)
* transfers.
*/
priv->txtail = NULL;
priv->inflight = 0;
priv->txtail = NULL;
priv->inflight = 0;
/* Initialize each TX descriptor */
@ -2716,15 +2748,17 @@ static void tiva_txdescinit(FAR struct tiva_ethmac_s *priv)
txdesc->tdes2 = 0;
/* Initialize the next descriptor with the Next Descriptor Polling Enable */
/* Initialize the next descriptor with
* the Next Descriptor Polling Enable
*/
if (i < (CONFIG_TIVA_EMAC_NTXDESC-1))
if (i < (CONFIG_TIVA_EMAC_NTXDESC - 1))
{
/* Set next descriptor address register with next descriptor base
* address
*/
txdesc->tdes3 = (uint32_t)&priv->txtable[i+1];
txdesc->tdes3 = (uint32_t)&priv->txtable[i + 1];
}
else
{
@ -2793,17 +2827,19 @@ static void tiva_rxdescinit(FAR struct tiva_ethmac_s *priv)
/* Set Buffer1 address pointer */
rxdesc->rdes2 = (uint32_t)&priv->rxbuffer[i*OPTIMAL_EMAC_BUFSIZE];
rxdesc->rdes2 = (uint32_t)&priv->rxbuffer[i * OPTIMAL_EMAC_BUFSIZE];
/* Initialize the next descriptor with the Next Descriptor Polling Enable */
/* Initialize the next descriptor with
* the Next Descriptor Polling Enable
*/
if (i < (CONFIG_TIVA_EMAC_NRXDESC-1))
if (i < (CONFIG_TIVA_EMAC_NRXDESC - 1))
{
/* Set next descriptor address register with next descriptor base
* address
*/
rxdesc->rdes3 = (uint32_t)&priv->rxtable[i+1];
rxdesc->rdes3 = (uint32_t)&priv->rxtable[i + 1];
}
else
{
@ -2860,7 +2896,8 @@ static int tiva_ioctl(struct net_driver_s *dev, int cmd, unsigned long arg)
#ifdef CONFIG_TIVA_PHY_INTERRUPTS
case SIOCMIINOTIFY: /* Set up for PHY event notifications */
{
struct mii_ioctl_notify_s *req = (struct mii_ioctl_notify_s *)((uintptr_t)arg);
struct mii_ioctl_notify_s *req =
(struct mii_ioctl_notify_s *)((uintptr_t)arg);
ret = phy_notify_subscribe(dev->d_ifname, req->pid, &req->event);
if (ret == OK)
@ -2875,7 +2912,8 @@ static int tiva_ioctl(struct net_driver_s *dev, int cmd, unsigned long arg)
case SIOCGMIIPHY: /* Get MII PHY address */
{
struct mii_ioctl_data_s *req = (struct mii_ioctl_data_s *)((uintptr_t)arg);
struct mii_ioctl_data_s *req =
(struct mii_ioctl_data_s *)((uintptr_t)arg);
req->phy_id = CONFIG_TIVA_PHYADDR;
ret = OK;
}
@ -2883,14 +2921,16 @@ static int tiva_ioctl(struct net_driver_s *dev, int cmd, unsigned long arg)
case SIOCGMIIREG: /* Get register from MII PHY */
{
struct mii_ioctl_data_s *req = (struct mii_ioctl_data_s *)((uintptr_t)arg);
struct mii_ioctl_data_s *req =
(struct mii_ioctl_data_s *)((uintptr_t)arg);
ret = tiva_phyread(req->phy_id, req->reg_num, &req->val_out);
}
break;
case SIOCSMIIREG: /* Set register in MII PHY */
{
struct mii_ioctl_data_s *req = (struct mii_ioctl_data_s *)((uintptr_t)arg);
struct mii_ioctl_data_s *req =
(struct mii_ioctl_data_s *)((uintptr_t)arg);
ret = tiva_phywrite(req->phy_id, req->reg_num, req->val_in);
}
break;
@ -2936,6 +2976,7 @@ static void tiva_phy_intenable(bool enable)
tiva_putreg(0, TIVA_EPHY_IM);
/* Enable/disable event based PHY interrupts */
/* REVISIT: There is an issue here: The PHY interrupt handler is called
* from the interrupt level and it, in turn, will call this function to
* disabled further interrupts. Subsequent link status processing will
@ -2960,7 +3001,8 @@ static void tiva_phy_intenable(bool enable)
if (ret == OK)
{
phyval |= EPHY_SCR_INTEN;
ret = tiva_phywrite(CONFIG_TIVA_PHYADDR, TIVA_EPHY_SCR, phyval);
ret = tiva_phywrite(CONFIG_TIVA_PHYADDR,
TIVA_EPHY_SCR, phyval);
if (ret == OK)
{
/* Enable PHY interrupts */
@ -3019,12 +3061,15 @@ static void tiva_phy_intenable(bool enable)
*
****************************************************************************/
static int tiva_phyread(uint16_t phydevaddr, uint16_t phyregaddr, uint16_t *value)
static int tiva_phyread(uint16_t phydevaddr,
uint16_t phyregaddr, uint16_t *value)
{
volatile uint32_t timeout;
uint32_t regval;
/* Configure the MIIADDR register, preserving CSR Clock Range CR[2:0] bits */
/* Configure the MIIADDR register,
* preserving CSR Clock Range CR[2:0] bits
*/
regval = tiva_getreg(TIVA_EMAC_MIIADDR);
regval &= EMAC_MIIADDR_CR_MASK;
@ -3033,8 +3078,8 @@ static int tiva_phyread(uint16_t phydevaddr, uint16_t phyregaddr, uint16_t *valu
* the EMAC_MIIADDR_MIIW is clear, indicating a read operation.
*/
regval |= (((uint32_t)phydevaddr << EMAC_MIIADDR_PLA_SHIFT) & EMAC_MIIADDR_PLA_MASK);
regval |= (((uint32_t)phyregaddr << EMAC_MIIADDR_MII_SHIFT) & EMAC_MIIADDR_MII_MASK);
regval |= (phydevaddr << EMAC_MIIADDR_PLA_SHIFT) & EMAC_MIIADDR_PLA_MASK;
regval |= (phyregaddr << EMAC_MIIADDR_MII_SHIFT) & EMAC_MIIADDR_MII_MASK;
regval |= EMAC_MIIADDR_MIIB;
tiva_putreg(regval, TIVA_EMAC_MIIADDR);
@ -3074,12 +3119,15 @@ static int tiva_phyread(uint16_t phydevaddr, uint16_t phyregaddr, uint16_t *valu
*
****************************************************************************/
static int tiva_phywrite(uint16_t phydevaddr, uint16_t phyregaddr, uint16_t value)
static int tiva_phywrite(uint16_t phydevaddr,
uint16_t phyregaddr, uint16_t value)
{
volatile uint32_t timeout;
uint32_t regval;
/* Configure the MIIADDR register, preserving CSR Clock Range CR[2:0] bits */
/* Configure the MIIADDR register,
* preserving CSR Clock Range CR[2:0] bits
*/
regval = tiva_getreg(TIVA_EMAC_MIIADDR);
regval &= EMAC_MIIADDR_CR_MASK;
@ -3088,8 +3136,8 @@ static int tiva_phywrite(uint16_t phydevaddr, uint16_t phyregaddr, uint16_t valu
* the EMAC_MIIADDR_MIIW is set, indicating a write operation.
*/
regval |= (((uint32_t)phydevaddr << EMAC_MIIADDR_PLA_SHIFT) & EMAC_MIIADDR_PLA_MASK);
regval |= (((uint32_t)phyregaddr << EMAC_MIIADDR_MII_SHIFT) & EMAC_MIIADDR_MII_MASK);
regval |= (phydevaddr << EMAC_MIIADDR_PLA_SHIFT) & EMAC_MIIADDR_PLA_MASK;
regval |= (phyregaddr << EMAC_MIIADDR_MII_SHIFT) & EMAC_MIIADDR_MII_MASK;
regval |= (EMAC_MIIADDR_MIIB | EMAC_MIIADDR_MIIW);
/* Write the value into the MACIIDR register before setting the new MIIADDR
@ -3109,7 +3157,8 @@ static int tiva_phywrite(uint16_t phydevaddr, uint16_t phyregaddr, uint16_t valu
}
}
nerr("ERROR: MII transfer timed out: phydevaddr: %04x phyregaddr: %04x value: %04x\n",
nerr("ERROR: MII transfer timed out: "
"phydevaddr: %04x phyregaddr: %04x value: %04x\n",
phydevaddr, phyregaddr, value);
return -ETIMEDOUT;
@ -3232,10 +3281,10 @@ static int tiva_phyinit(FAR struct tiva_ethmac_s *priv)
ninfo("PHYSR[%d]: %04x\n", CONFIG_TIVA_PHYSR, phyval);
/* Different PHYs present speed and mode information in different ways. IF
* This CONFIG_TIVA_PHYSR_ALTCONFIG is selected, this indicates that the PHY
* represents speed and mode information are combined, for example, with
* separate bits for 10HD, 100HD, 10FD and 100FD.
/* Different PHYs present speed and mode information in different ways.
* IF This CONFIG_TIVA_PHYSR_ALTCONFIG is selected, this indicates that
* the PHY represents speed and mode information are combined, for
* example, with separate bits for 10HD, 100HD, 10FD and 100FD.
*/
#ifdef CONFIG_TIVA_PHYSR_ALTCONFIG
@ -3263,10 +3312,10 @@ static int tiva_phyinit(FAR struct tiva_ethmac_s *priv)
break;
}
/* Different PHYs present speed and mode information in different ways. Some
* will present separate information for speed and mode (this is the default).
* Those PHYs, for example, may provide a 10/100 Mbps indication and a separate
* full/half duplex indication.
/* Different PHYs present speed and mode information in different ways.
* Some will present separate information for speed and mode (this is the
* default). Those PHYs, for example, may provide a 10/100 Mbps indication
* and a separate full/half duplex indication.
*/
#else
@ -3429,8 +3478,8 @@ static inline void tiva_phy_initialize(FAR struct tiva_ethmac_s *priv)
ninfo("Enable EPHY power\n");
tiva_ephy_enablepwr();
/* What until the PREPHY register indicates that the PHY registers are ready
* to be accessed.
/* What until the PREPHY register indicates that the PHY registers are
* ready to be accessed.
*/
while (!tiva_ephy_periphrdy());
@ -3445,16 +3494,18 @@ static inline void tiva_phy_initialize(FAR struct tiva_ethmac_s *priv)
#ifdef CONFIG_TIVA_PHY_INTERNAL
/* Integrated PHY:
*
* "The Ethernet Controller Module and Integrated PHY receive two clock inputs:
* - A gated system clock acts as the clock source to the Control and Status
* registers (CSR) of the Ethernet MAC. The SYSCLK frequency for Run, Sleep
* and Deep Sleep mode is programmed in the System Control module. ...
* - The PHY receives the main oscillator (MOSC) which must be 25 MHz ± 50 ppm
* for proper operation. The MOSC source can be a single-ended source or a
* crystal."
* "The Ethernet Controller Module and Integrated PHY receive two clock
* inputs:
* - A gated system clock acts as the clock source to the Control and
* Status registers (CSR) of the Ethernet MAC. The SYSCLK frequency
* for Run, Sleep and Deep Sleep mode is programmed in the System
* Control module. ...
* - The PHY receives the main oscillator (MOSC) which must be 25 MHz
* ± 50 ppm for proper operation. The MOSC source can be a single-
* ended source or a crystal."
*
* These are currently set up in tiva_clock_reconfigure() before this function
* runs.
* These are currently set up in tiva_clock_reconfigure() before this
* function runs.
*
* MII/RMII Clocking:
*
@ -3483,6 +3534,7 @@ static inline void tiva_phy_initialize(FAR struct tiva_ethmac_s *priv)
tiva_configgpio(GPIO_EN0_INTRN);
/* Configure GPIO pins to support MII or RMII */
/* MDC and MDIO are common to both modes */
tiva_configgpio(GPIO_EN0_MDC);
@ -3516,8 +3568,8 @@ static inline void tiva_phy_initialize(FAR struct tiva_ethmac_s *priv)
/* MII interface pins (17):
*
* MII_TX_CLK, MII_TXD[3:0], MII_TX_EN, MII_RX_CLK, MII_RXD[3:0], MII_RX_ER,
* MII_RX_DV, MII_CRS, MII_COL, MDC, MDIO
* MII_TX_CLK, MII_TXD[3:0], MII_TX_EN, MII_RX_CLK, MII_RXD[3:0],
* MII_RX_ER, MII_RX_DV, MII_CRS, MII_COL, MDC, MDIO
*/
tiva_configgpio(GPIO_EN0_MII_COL);
@ -3619,17 +3671,18 @@ static void tiva_ethreset(FAR struct tiva_ethmac_s *priv)
up_udelay(250);
#endif
/* Perform a software reset by setting the SWR bit in the DMABUSMOD register.
* This Resets all MAC subsystem internal registers and logic. After this
* reset all the registers holds their reset values.
/* Perform a software reset by setting the SWR bit in the DMABUSMOD
* register. This Resets all MAC subsystem internal registers and logic.
* After this reset all the registers holds their reset values.
*/
regval = tiva_getreg(TIVA_EMAC_DMABUSMOD);
regval |= EMAC_DMABUSMOD_SWR;
tiva_putreg(regval, TIVA_EMAC_DMABUSMOD);
/* Wait for software reset to complete. The SWR bit is cleared automatically
* after the reset operation has completed in all of the core clock domains.
/* Wait for software reset to complete. The SWR bit is cleared
* automatically after the reset operation has completed in all
* core clock domains.
*/
while ((tiva_getreg(TIVA_EMAC_DMABUSMOD) & EMAC_DMABUSMOD_SWR) != 0);
@ -3708,6 +3761,7 @@ static int tiva_macconfig(FAR struct tiva_ethmac_s *priv)
tiva_putreg(0, TIVA_EMAC_VLANTG);
/* DMA Configuration */
/* Set up the DMAOPMODE register */
regval = tiva_getreg(TIVA_EMAC_DMAOPMODE);
@ -3748,9 +3802,12 @@ static void tiva_macaddress(FAR struct tiva_ethmac_s *priv)
ninfo("%s MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
dev->d_ifname,
dev->d_mac.ether.ether_addr_octet[0], dev->d_mac.ether.ether_addr_octet[1],
dev->d_mac.ether.ether_addr_octet[2], dev->d_mac.ether.ether_addr_octet[3],
dev->d_mac.ether.ether_addr_octet[4], dev->d_mac.ether.ether_addr_octet[5]);
dev->d_mac.ether.ether_addr_octet[0],
dev->d_mac.ether.ether_addr_octet[1],
dev->d_mac.ether.ether_addr_octet[2],
dev->d_mac.ether.ether_addr_octet[3],
dev->d_mac.ether.ether_addr_octet[4],
dev->d_mac.ether.ether_addr_octet[5]);
/* Set the MAC address high register */
@ -4053,20 +4110,20 @@ int tiva_ethinitialize(int intf)
/* Enable power and clocking to the Ethernet MAC
*
* - Enable Power: Applies power (only) to the EMAC peripheral. This is not
* - Enable Power: Applies power (only) to the EMAC peripheral. This is not
* an essential step since enabling clocking will also apply power. The
* only significance is that the EMAC state will be retained if the EMAC
* clocking is subsequently disabled.
* - Enable Clocking: Applies both power and clocking to the EMAC peripheral,
* bringing it a fully functional state.
* - Enable Clocking: Applies both power and clocking to the EMAC
* peripheral, bringing it a fully functional state.
*/
ninfo("Enable EMAC clocking\n");
tiva_emac_enablepwr(); /* Ethernet MAC Power Control */
tiva_emac_enableclk(); /* Ethernet MAC Run Mode Clock Gating Control */
/* What until the PREMAC register indicates that the EMAC registers are ready
* to be accessed.
/* What until the PREMAC register indicates that the EMAC registers are
* ready to be accessed.
*/
while (!tiva_emac_periphrdy());
@ -4094,7 +4151,7 @@ int tiva_ethinitialize(int intf)
}
/* Wait for EMAC to come out of reset. The SWR bit is cleared automatically
* after the reset operation has completed in all of the core clock domains.
* after the reset operation has completed in all core clock domains.
*/
while ((tiva_getreg(TIVA_EMAC_DMABUSMOD) & EMAC_DMABUSMOD_SWR) != 0);
@ -4131,8 +4188,8 @@ int tiva_ethinitialize(int intf)
* Function: arm_netinitialize
*
* Description:
* This is the "standard" network initialization logic called from the
* low-level initialization logic in arm_initialize.c. If TIVA_NETHCONTROLLERS
* This is the "standard" network initialization logic called from the low
* -level initialization logic in arm_initialize.c. If TIVA_NETHCONTROLLERS
* greater than one, then board specific logic will have to supply a
* version of arm_netinitialize() that calls tiva_ethinitialize() with
* the appropriate interface number.
@ -4231,7 +4288,7 @@ int arch_phy_irq(FAR const char *intf, xcpt_t handler, void *arg,
#if TIVA_NETHCONTROLLERS > 1
/* REVISIT: Additional logic needed if there are multiple EMACs */
warning Missing logic
# warning Missing logic
#endif
priv = g_tiva_ethmac;

68
arch/hc/src/m9s12/m9s12_ethernet.c
View file

@ -71,7 +71,9 @@
# define CONFIG_HCS12_NINTERFACES 1
#endif
/* TX poll deley = 1 seconds. CLK_TCK is the number of clock ticks per second */
/* TX poll deley = 1 seconds.
* CLK_TCK is the number of clock ticks per second
*/
#define HCS12_WDDELAY (1*CLK_TCK)
@ -79,7 +81,7 @@
#define HCS12_TXTIMEOUT (60*CLK_TCK)
/* This is a helper pointer for accessing the contents of the Ethernet header */
/* This is a helper pointer for accessing the contents of Ethernet header */
#define BUF ((struct eth_hdr_s *)priv->d_dev.d_buf)
@ -215,7 +217,8 @@ static int emac_transmit(FAR struct emac_driver_s *priv)
static int emac_txpoll(struct net_driver_s *dev)
{
FAR struct emac_driver_s *priv = (FAR struct emac_driver_s *)dev->d_private;
FAR struct emac_driver_s *priv =
(FAR struct emac_driver_s *)dev->d_private;
/* If the polling resulted in data that should be sent out on the network,
* the field d_len is set to a value > 0.
@ -251,14 +254,14 @@ static int emac_txpoll(struct net_driver_s *dev)
emac_transmit(priv);
/* Check if there is room in the device to hold another packet. If not,
* return a non-zero value to terminate the poll.
/* Check if there is room in the device to hold another packet.
* If not, return a non-zero value to terminate the poll.
*/
}
}
/* If zero is returned, the polling will continue until all connections have
* been examined.
/* If zero is returned, the polling will continue until all connections
* have been examined.
*/
return 0;
@ -287,14 +290,16 @@ static void emac_receive(FAR struct emac_driver_s *priv)
{
/* Check for errors and update statistics */
/* Check if the packet is a valid size for the network buffer configuration */
/* Check if the packet is a valid size for the network buffer
* configuration
*/
/* Copy the data data from the hardware to priv->d_dev.d_buf. Set
* amount of data in priv->d_dev.d_len
*/
#ifdef CONFIG_NET_PKT
/* When packet sockets are enabled, feed the frame into the packet tap */
/* When packet sockets are enabled, feed the frame into the tap */
pkt_input(&priv->d_dev);
#endif
@ -314,7 +319,7 @@ static void emac_receive(FAR struct emac_driver_s *priv)
ipv4_input(&priv->d_dev);
/* If the above function invocation resulted in data that should be
* sent out on the network, the field d_len will set to a value > 0.
* sent out on the network, d_len field will set to a value > 0.
*/
if (priv->d_dev.d_len > 0)
@ -351,11 +356,11 @@ static void emac_receive(FAR struct emac_driver_s *priv)
ipv6_input(&priv->d_dev);
/* If the above function invocation resulted in data that should be
* sent out on the network, the field d_len will set to a value > 0.
* sent out on the network, d_len field will set to a value > 0.
*/
if (priv->d_dev.d_len > 0)
{
{
/* Update the Ethernet header with the correct MAC address */
#ifdef CONFIG_NET_IPv4
@ -384,7 +389,7 @@ static void emac_receive(FAR struct emac_driver_s *priv)
arp_arpin(&priv->d_dev);
/* If the above function invocation resulted in data that should be
* sent out on the network, the field d_len will set to a value > 0.
* sent out on the network, d_len field will set to a value > 0.
*/
if (priv->d_dev.d_len > 0)
@ -526,9 +531,9 @@ static void emac_polltimer(int argc, wdparm_t arg, ...)
* the TX poll if he are unable to accept another packet for transmission.
*/
/* If so, update TCP timing states and poll the network for new XMIT data. Hmmm..
* might be bug here. Does this mean if there is a transmit in progress,
* we will missing TCP time state updates?
/* If so, update TCP timing states and poll the network for new XMIT data.
* Hmmm.. might be bug here. Does this mean if there is a transmit in
* progress, we will missing TCP time state updates?
*/
devif_timer(&priv->d_dev, HCS12_WDDELAY, emac_txpoll);
@ -557,13 +562,14 @@ static void emac_polltimer(int argc, wdparm_t arg, ...)
static int emac_ifup(struct net_driver_s *dev)
{
FAR struct emac_driver_s *priv = (FAR struct emac_driver_s *)dev->d_private;
FAR struct emac_driver_s *priv =
(FAR struct emac_driver_s *)dev->d_private;
ninfo("Bringing up: %d.%d.%d.%d\n",
dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff,
(dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24 );
(dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24);
/* Initialize PHYs, the Ethernet interface, and setup up Ethernet interrupts */
/* Initialize PHYs, Ethernet interface, and setup up Ethernet interrupts */
/* Set and activate a timer process */
@ -594,7 +600,8 @@ static int emac_ifup(struct net_driver_s *dev)
static int emac_ifdown(struct net_driver_s *dev)
{
FAR struct emac_driver_s *priv = (FAR struct emac_driver_s *)dev->d_private;
FAR struct emac_driver_s *priv =
(FAR struct emac_driver_s *)dev->d_private;
irqstate_t flags;
/* Disable the Ethernet interrupt */
@ -640,7 +647,8 @@ static int emac_ifdown(struct net_driver_s *dev)
static int emac_txavail(struct net_driver_s *dev)
{
FAR struct emac_driver_s *priv = (FAR struct emac_driver_s *)dev->d_private;
FAR struct emac_driver_s *priv =
(FAR struct emac_driver_s *)dev->d_private;
irqstate_t flags;
/* Disable interrupts because this function may be called from interrupt
@ -653,7 +661,7 @@ static int emac_txavail(struct net_driver_s *dev)
if (priv->d_bifup)
{
/* Check if there is room in the hardware to hold another outgoing packet. */
/* Check if there is room in the hardware to hold another packet. */
/* If so, then poll the network for new XMIT data */
@ -685,7 +693,8 @@ static int emac_txavail(struct net_driver_s *dev)
#ifdef CONFIG_NET_MCASTGROUP
static int emac_addmac(struct net_driver_s *dev, FAR const uint8_t *mac)
{
FAR struct emac_driver_s *priv = (FAR struct emac_driver_s *)dev->d_private;
FAR struct emac_driver_s *priv =
(FAR struct emac_driver_s *)dev->d_private;
/* Add the MAC address to the hardware multicast routing table */
@ -697,8 +706,8 @@ static int emac_addmac(struct net_driver_s *dev, FAR const uint8_t *mac)
* Function: emac_rmmac
*
* Description:
* NuttX Callback: Remove the specified MAC address from the hardware multicast
* address filtering
* NuttX Callback: Remove the specified MAC address from the hardware
* multicast address filtering
*
* Input Parameters:
* dev - Reference to the NuttX driver state structure
@ -714,7 +723,8 @@ static int emac_addmac(struct net_driver_s *dev, FAR const uint8_t *mac)
#ifdef CONFIG_NET_MCASTGROUP
static int emac_rmmac(struct net_driver_s *dev, FAR const uint8_t *mac)
{
FAR struct emac_driver_s *priv = (FAR struct emac_driver_s *)dev->d_private;
FAR struct emac_driver_s *priv =
(FAR struct emac_driver_s *)dev->d_private;
/* Add the MAC address to the hardware multicast routing table */
@ -752,7 +762,7 @@ int emac_initialize(int intf)
DEBUGASSERT(inf < CONFIG_HCS12_NINTERFACES);
priv = &g_emac[intf];
/* Check if a Ethernet chip is recognized at its I/O base */
/* Check if a Ethernet chip is recognized at its I/O base */
/* Attach the IRQ to the driver */
@ -785,7 +795,9 @@ int emac_initialize(int intf)
* the device and/or calling emac_ifdown().
*/
/* Read the MAC address from the hardware into priv->d_dev.d_mac.ether.ether_addr_octet */
/* Read the MAC address from the hardware into
* priv->d_dev.d_mac.ether.ether_addr_octet
*/
/* Register the device with the OS so that socket IOCTLs can be performed */

91
arch/mips/src/pic32mx/pic32mx_ethernet.c
View file

@ -114,8 +114,8 @@
#endif
/* The logic here has a few hooks for support for multiple interfaces, but
* that capability is not yet in place (and I won't worry about it until I get
* the first multi-interface PIC32MX).
* that capability is not yet in place (and I won't worry about it until I
* get the first multi-interface PIC32MX).
*/
#if CONFIG_PIC32MX_NINTERFACES > 1
@ -159,7 +159,7 @@
#define PIC32MX_NBUFFERS (CONFIG_PIC32MX_ETH_NRXDESC + \
CONFIG_PIC32MX_ETH_NTXDESC + 1)
/* Debug Configuration *****************************************************/
/* Debug Configuration ******************************************************/
/* CONFIG_NET_DUMPPACKET will dump the contents of each packet to the
* console.
@ -225,7 +225,7 @@
#define ETH_RXINTS (ETH_INT_RXOVFLW | ETH_INT_RXBUFNA | ETH_INT_RXDONE | ETH_INT_RXBUSE)
#define ETH_TXINTS (ETH_INT_TXABORT | ETH_INT_TXDONE | ETH_INT_TXBUSE)
/* Misc. Helpers ***********************************************************/
/* Misc. Helpers ************************************************************/
/* This is a helper pointer for accessing the contents of the Ethernet
* header
@ -395,7 +395,8 @@ static inline struct pic32mx_txdesc_s *
pic32mx_txdesc(struct pic32mx_driver_s *priv);
static inline void pic32mx_txnext(struct pic32mx_driver_s *priv);
static inline void pic32mx_rxreturn(struct pic32mx_rxdesc_s *rxdesc);
static struct pic32mx_rxdesc_s *pic32mx_rxdesc(struct pic32mx_driver_s *priv);
static struct pic32mx_rxdesc_s *
pic32mx_rxdesc(struct pic32mx_driver_s *priv);
/* Common TX logic */
@ -714,7 +715,8 @@ static uint8_t *pic32mx_allocbuffer(struct pic32mx_driver_s *priv)
*
****************************************************************************/
static void pic32mx_freebuffer(struct pic32mx_driver_s *priv, uint8_t *buffer)
static void pic32mx_freebuffer(struct pic32mx_driver_s *priv,
uint8_t *buffer)
{
/* Add the buffer to the end of the free buffer list */
@ -989,8 +991,8 @@ static struct pic32mx_rxdesc_s *pic32mx_rxdesc(struct pic32mx_driver_s *priv)
int i;
/* Inspect the list of RX descriptors to see if the EOWN bit is cleared.
* If it is, this descriptor is now under software control and a message was
* received. Use SOP and EOP to extract the message, use BYTE_COUNT,
* If it is, this descriptor is now under software control and a message
* was received. Use SOP and EOP to extract the message, use BYTE_COUNT,
* RXF_RSV, RSV and PKT_CHECKSUM to get the message characteristics.
*/
@ -1055,9 +1057,9 @@ static int pic32mx_transmit(struct pic32mx_driver_s *priv)
*
* The SOP, EOP, DATA_BUFFER_ADDRESS and BYTE_COUNT will be updated when a
* particular message has to be transmitted. The DATA_BUFFER_ADDRESS will
* contain the physical address of the message, the BYTE_COUNT message size.
* SOP and EOP are set depending on how many packets are needed to transmit
* the message.
* contain the physical address of the message, the BYTE_COUNT message
* size. SOP and EOP are set depending on how many packets are needed to
* transmit the message.
*/
/* Find the next available TX descriptor. We are guaranteed that is will
@ -1083,9 +1085,9 @@ static int pic32mx_transmit(struct pic32mx_driver_s *priv)
status = ((uint32_t)priv->pd_dev.d_len << TXDESC_STATUS_BYTECOUNT_SHIFT);
priv->pd_dev.d_len = 0;
/* Set EOWN = 1 to indicate that the packet belongs to Ethernet and set both
* SOP and EOP to indicate that the packet both begins and ends with this
* frame.
/* Set EOWN = 1 to indicate that the packet belongs to Ethernet and set
* both SOP and EOP to indicate that the packet both begins and ends with
* this frame.
*/
status |= (TXDESC_STATUS_EOWN | TXDESC_STATUS_NPV |
@ -1188,7 +1190,9 @@ static int pic32mx_txpoll(struct net_driver_s *dev)
if (pic32mx_txdesc(priv) == NULL)
{
/* There are no more TX descriptors/buffers available.. stop the poll */
/* There are no more TX descriptors/buffers available..
* stop the poll
*/
return -EAGAIN;
}
@ -1207,8 +1211,8 @@ static int pic32mx_txpoll(struct net_driver_s *dev)
}
}
/* If zero is returned, the polling will continue until all connections have
* been examined.
/* If zero is returned, the polling will continue until all connections
* have been examined.
*/
return ret;
@ -1313,7 +1317,7 @@ static void pic32mx_timerpoll(struct pic32mx_driver_s *priv)
*
* Description:
* While processing an RxDone event, higher logic decides to send a packet,
* possibly a response to the incoming packet (but probably not, in reality)
* possibly a response to the incoming packet(but probably not, in reality)
* However, since the Rx and Tx operations are decoupled, there is no
* guarantee that there will be a Tx descriptor available at that time.
* This function will perform that check and, if no Tx descriptor is
@ -1499,7 +1503,7 @@ static void pic32mx_rxdone(struct pic32mx_driver_s *priv)
if (priv->pd_dev.d_len > 0)
{
/* Update the Ethernet header with the correct MAC address */
/* Update Ethernet header with the correct MAC address */
#ifdef CONFIG_NET_IPv6
if (IFF_IS_IPv4(priv->pd_dev.d_flags))
@ -1538,7 +1542,7 @@ static void pic32mx_rxdone(struct pic32mx_driver_s *priv)
if (priv->pd_dev.d_len > 0)
{
/* Update the Ethernet header with the correct MAC address */
/* Update Ethernet header with the correct MAC address */
#ifdef CONFIG_NET_IPv4
if (IFF_IS_IPv4(priv->pd_dev.d_flags))
@ -1660,7 +1664,8 @@ static void pic32mx_txdone(struct pic32mx_driver_s *priv)
/* Free the TX buffer */
pic32mx_freebuffer(priv, (uint8_t *)VIRT_ADDR(txdesc->address));
pic32mx_freebuffer(priv,
(uint8_t *)VIRT_ADDR(txdesc->address));
txdesc->address = 0;
/* Reset status */
@ -1759,7 +1764,8 @@ static void pic32mx_interrupt_work(void *arg)
if ((status & ETH_INT_RXBUFNA) != 0)
{
nerr("ERROR: RX buffer descriptor overrun. status: %08x\n", status);
nerr("ERROR: RX buffer descriptor overrun. status: %08x\n",
status);
NETDEV_RXERRORS(&priv->pd_dev);
}
@ -1851,15 +1857,15 @@ static void pic32mx_interrupt_work(void *arg)
/* EWMARK: Empty Watermark Interrupt. This bit is set when the RX
* Descriptor Buffer Count is less than or equal to the value in the
* RXEWM bit (ETHRXWM:0-7) value. It is cleared by BUFCNT bit
* (ETHSTAT:16-23) being incremented by hardware. Writing a ‘0’ or a ‘1’
* has no effect.
* (ETHSTAT:16-23) being incremented by hardware. Writing a ‘0’ or
* a ‘1’ has no effect.
*/
/* FWMARK: Full Watermark Interrupt. This bit is set when the RX
* escriptor Buffer Count is greater than or equal to the value in the
* RXFWM bit (ETHRXWM:16-23) field. It is cleared by writing the BUFCDEC
* (ETHCON1:0) bit to decrement the BUFCNT counter. Writing a ‘0’ or a
* ‘1’ has no effect.
* RXFWM bit (ETHRXWM:16-23) field. It is cleared by writing the
* BUFCDEC (ETHCON1:0) bit to decrement the BUFCNT counter. Writing a
* ‘0’ or a ‘1’ has no effect.
*/
}
@ -2138,8 +2144,9 @@ static int pic32mx_ifup(struct net_driver_s *dev)
/* Pin Configuration:
*
* No GPIO pin configuration is required. Enabling the Ethernet Controller
* will configure the IO pin direction as defined by the Ethernet Controller
* control bits. The port TRIS and LATCH registers will be overridden.
* will configure the IO pin direction as defined by the Ethernet
* Controller control bits. The port TRIS and LATCH registers will be
* overridden.
*
* I/O Pin MII RMII Pin Description
* Name Required Required Type
@ -2155,7 +2162,8 @@ static int pic32mx_ifup(struct net_driver_s *dev)
* ERXCLK Yes No I Ethernet MII RX Clock
* EREF_CLK No Yes I Ethernet RMII Ref Clock
* ERXDV Yes No I Ethernet MII Receive Data Valid
* ECRS_DV No Yes I Ethernet RMII Carrier Sense/Receive Data Valid
* ECRS_DV No Yes I Ethernet RMII Carrier Sense/
* Receive Data Valid
* ERXD0 Yes Yes I Ethernet Data Receive 0
* ERXD1 Yes Yes I Ethernet Data Receive 1
* ERXD2 Yes No I Ethernet Data Receive 2
@ -2200,7 +2208,8 @@ static int pic32mx_ifup(struct net_driver_s *dev)
* preamble, no scan increment.
*/
regval &= ~(EMAC1_MCFG_CLKSEL_MASK | EMAC1_MCFG_NOPRE | EMAC1_MCFG_SCANINC);
regval &= ~(EMAC1_MCFG_CLKSEL_MASK |
EMAC1_MCFG_NOPRE | EMAC1_MCFG_SCANINC);
regval |= EMAC1_MCFG_CLKSEL_DIV;
pic32mx_putreg(regval, PIC32MX_EMAC1_MCFG);
@ -2281,16 +2290,16 @@ static int pic32mx_ifup(struct net_driver_s *dev)
pic32mx_putreg(regval, PIC32MX_EMAC1_SA2);
#else
regval = pic32mx_getreg(PIC32MX_EMAC1_SA0);
priv->pd_dev.d_mac.ether.ether_addr_octet[4] = (uint32_t)(regval & 0xff);
priv->pd_dev.d_mac.ether.ether_addr_octet[5] = (uint32_t)((regval >> 8) & 0xff);
priv->pd_dev.d_mac.ether.ether_addr_octet[4] = regval & 0xff;
priv->pd_dev.d_mac.ether.ether_addr_octet[5] = (regval >> 8) & 0xff;
regval = pic32mx_getreg(PIC32MX_EMAC1_SA1);
priv->pd_dev.d_mac.ether.ether_addr_octet[2] = (uint32_t)(regval & 0xff);
priv->pd_dev.d_mac.ether.ether_addr_octet[3] = (uint32_t)((regval >> 8) & 0xff);
priv->pd_dev.d_mac.ether.ether_addr_octet[2] = regval & 0xff;
priv->pd_dev.d_mac.ether.ether_addr_octet[3] = (regval >> 8) & 0xff;
regval = pic32mx_getreg(PIC32MX_EMAC1_SA2);
priv->pd_dev.d_mac.ether.ether_addr_octet[0] = (uint32_t)(regval & 0xff);
priv->pd_dev.d_mac.ether.ether_addr_octet[1] = (uint32_t)((regval >> 8) & 0xff);
priv->pd_dev.d_mac.ether.ether_addr_octet[0] = regval & 0xff;
priv->pd_dev.d_mac.ether.ether_addr_octet[1] = (regval >> 8) & 0xff;
#endif
/* Continue Ethernet Controller Initialization ****************************/
@ -2950,8 +2959,8 @@ static inline int pic32mx_phyinit(struct pic32mx_driver_s *priv)
#endif
#else
/* Set the MII/ operation mode. This usually requires access to a vendor-
* specific control register.
/* Set the MII/ operation mode. This usually requires access to a vendor
* -specific control register.
*/
#ifdef CONFIG_ETH0_PHY_DP83848C
@ -3080,8 +3089,8 @@ static inline int pic32mx_phyinit(struct pic32mx_driver_s *priv)
/* Set up the fixed PHY configuration
*
* If auto-negotiation is not supported/selected, update the PHY Duplex and
* Speed settings directly (use Control Register 0 and possibly some vendor-
* pecific registers).
* Speed settings directly (use Control Register 0 and possibly some vendor
* -pecific registers).
*/
ret = pic32mx_phymode(phyaddr, PIC32MX_MODE_DEFLT);

80
arch/misoc/src/common/misoc_net.c
View file

@ -79,7 +79,7 @@
*/
#if !defined(CONFIG_SCHED_HPWORK)
/* REVISIT: The low priority work queue would be preferred if it is available */
/* REVISIT: The low priority work queue would be preferred if available */
# error High priority work queue support is required
#endif
@ -92,7 +92,9 @@
# define CONFIG_MISOC_NET_NINTERFACES 1
#endif
/* TX poll delay = 1 seconds. CLK_TCK is the number of clock ticks per second */
/* TX poll delay = 1 seconds.
* CLK_TCK is the number of clock ticks per second
*/
#define MISOC_NET_WDDELAY (1*CLK_TCK)
@ -100,7 +102,7 @@
#define MISOC_NET_TXTIMEOUT (60*CLK_TCK)
/* This is a helper pointer for accessing the contents of the Ethernet header */
/* This is a helper pointer for accessing the contents of Ethernet header */
#define BUF ((struct eth_hdr_s *)priv->misoc_net_dev.d_buf)
@ -108,8 +110,8 @@
* Private Types
****************************************************************************/
/* The misoc_net_driver_s encapsulates all state information for a single hardware
* interface
/* The misoc_net_driver_s encapsulates all state information for a single
* hardware interface
*/
struct misoc_net_driver_s
@ -177,9 +179,11 @@ static void misoc_net_txavail_work(FAR void *arg);
static int misoc_net_txavail(FAR struct net_driver_s *dev);
#if defined(CONFIG_NET_MCASTGROUP) || defined(CONFIG_NET_ICMPv6)
static int misoc_net_addmac(FAR struct net_driver_s *dev, FAR const uint8_t *mac);
static int misoc_net_addmac(FAR struct net_driver_s *dev,
FAR const uint8_t *mac);
#ifdef CONFIG_NET_MCASTGROUP
static int misoc_net_rmmac(FAR struct net_driver_s *dev, FAR const uint8_t *mac);
static int misoc_net_rmmac(FAR struct net_driver_s *dev,
FAR const uint8_t *mac);
#endif
#ifdef CONFIG_NET_ICMPv6
static void misoc_net_ipv6multicast(FAR struct misoc_net_driver_s *priv);
@ -337,14 +341,14 @@ static int misoc_net_txpoll(FAR struct net_driver_s *dev)
misoc_net_transmit(priv);
/* Check if there is room in the device to hold another packet. If not,
* return a non-zero value to terminate the poll.
/* Check if there is room in the device to hold another packet.
* If not, return a non-zero value to terminate the poll.
*/
}
}
/* If zero is returned, the polling will continue until all connections have
* been examined.
/* If zero is returned, the polling will continue until all connections
* have been examined.
*/
return 0;
@ -388,11 +392,11 @@ static void misoc_net_receive(FAR struct misoc_net_driver_s *priv)
rxlen = ethmac_sram_writer_length_read();
/* Copy the data data from the hardware to priv->misoc_net_dev.d_buf. Set
* amount of data in priv->misoc_net_dev.d_len
/* Copy the data data from the hardware to priv->misoc_net_dev.d_buf.
* Set amount of data in priv->misoc_net_dev.d_len
*
* NOTE: These memcpy's could be avoided by simply setting the d_buf
* pointer to the rx*_buf containing the received data. Some additional
* pointer to the rx*_buf containing the received data. Some additional
* buffer management logic would also be required.
*/
@ -414,7 +418,7 @@ static void misoc_net_receive(FAR struct misoc_net_driver_s *priv)
priv->misoc_net_dev.d_len = rxlen;
#ifdef CONFIG_NET_PKT
/* When packet sockets are enabled, feed the frame into the packet tap */
/* When packet sockets are enabled, feed the frame into the tap */
pkt_input(&priv->misoc_net_dev);
#endif
@ -435,7 +439,7 @@ static void misoc_net_receive(FAR struct misoc_net_driver_s *priv)
ipv4_input(&priv->misoc_net_dev);
/* If the above function invocation resulted in data that should be
* sent out on the network, the field d_len will set to a value > 0.
* sent out on the network, d_len field will set to a value > 0.
*/
if (priv->misoc_net_dev.d_len > 0)
@ -473,7 +477,7 @@ static void misoc_net_receive(FAR struct misoc_net_driver_s *priv)
ipv6_input(&priv->misoc_net_dev);
/* If the above function invocation resulted in data that should be
* sent out on the network, the field d_len will set to a value > 0.
* sent out on the network, d_len field will set to a value > 0.
*/
if (priv->misoc_net_dev.d_len > 0)
@ -507,7 +511,7 @@ static void misoc_net_receive(FAR struct misoc_net_driver_s *priv)
NETDEV_RXARP(&priv->misoc_net_dev);
/* If the above function invocation resulted in data that should be
* sent out on the network, the field d_len will set to a value > 0.
* sent out on the network, d_len field will set to a value > 0.
*/
if (priv->misoc_net_dev.d_len > 0)
@ -589,16 +593,18 @@ static void misoc_net_interrupt_work(FAR void *arg)
net_lock();
/* Check if we received an incoming packet, if so, call misoc_net_receive() */
/* Check if we received an incoming packet,
* if so, call misoc_net_receive()
*/
if (ethmac_sram_writer_ev_pending_read() & ETHMAC_EV_SRAM_WRITER)
{
misoc_net_receive(priv);
}
/* Check if a packet transmission just completed. If so, call misoc_net_txdone.
* This may disable further Tx interrupts if there are no pending
* transmissions.
/* Check if a packet transmission just completed. If so, call
* misoc_net_txdone. This may disable further Tx interrupts if there are no
* pending transmissions.
*/
if (ethmac_sram_reader_ev_pending_read() & ETHMAC_EV_SRAM_READER)
@ -660,7 +666,8 @@ static int misoc_net_interrupt(int irq, FAR void *context, FAR void *arg)
/* Schedule to perform the interrupt processing on the worker thread. */
work_queue(HPWORK, &priv->misoc_net_irqwork, misoc_net_interrupt_work, priv, 0);
work_queue(HPWORK, &priv->misoc_net_irqwork,
misoc_net_interrupt_work, priv, 0);
return OK;
}
@ -732,7 +739,8 @@ static void misoc_net_txtimeout_expiry(int argc, wdparm_t arg, ...)
/* Schedule to perform the TX timeout processing on the worker thread. */
work_queue(HPWORK, &priv->misoc_net_irqwork, misoc_net_txtimeout_work, priv, 0);
work_queue(HPWORK, &priv->misoc_net_irqwork,
misoc_net_txtimeout_work, priv, 0);
}
/****************************************************************************
@ -803,7 +811,8 @@ static void misoc_net_poll_expiry(int argc, wdparm_t arg, ...)
/* Schedule to perform the interrupt processing on the worker thread. */
work_queue(HPWORK, &priv->misoc_net_pollwork, misoc_net_poll_work, priv, 0);
work_queue(HPWORK, &priv->misoc_net_pollwork,
misoc_net_poll_work, priv, 0);
}
/****************************************************************************
@ -841,9 +850,11 @@ static int misoc_net_ifup(FAR struct net_driver_s *dev)
dev->d_ipv6addr[6], dev->d_ipv6addr[7]);
#endif
/* Initialize PHYs, the Ethernet interface, and setup up Ethernet interrupts */
/* Initialize PHYs, Ethernet interface, and setup up Ethernet interrupts */
/* Instantiate the MAC address from priv->misoc_net_dev.d_mac.ether.ether_addr_octet */
/* Instantiate the MAC address from
* priv->misoc_net_dev.d_mac.ether.ether_addr_octet
*/
#ifdef CONFIG_NET_ICMPv6
/* Set up IPv6 multicast address filtering */
@ -942,7 +953,7 @@ static void misoc_net_txavail_work(FAR void *arg)
net_lock();
if (priv->misoc_net_bifup)
{
/* Check if there is room in the hardware to hold another outgoing packet. */
/* Check if there is room in the hardware to hold another packet. */
if (!ethmac_sram_reader_ready_read())
{
@ -988,7 +999,8 @@ static int misoc_net_txavail(FAR struct net_driver_s *dev)
{
/* Schedule to serialize the poll on the worker thread. */
work_queue(HPWORK, &priv->misoc_net_pollwork, misoc_net_txavail_work, priv, 0);
work_queue(HPWORK, &priv->misoc_net_pollwork,
misoc_net_txavail_work, priv, 0);
}
return OK;
@ -1013,7 +1025,8 @@ static int misoc_net_txavail(FAR struct net_driver_s *dev)
****************************************************************************/
#if defined(CONFIG_NET_MCASTGROUP) || defined(CONFIG_NET_ICMPv6)
static int misoc_net_addmac(FAR struct net_driver_s *dev, FAR const uint8_t *mac)
static int misoc_net_addmac(FAR struct net_driver_s *dev,
FAR const uint8_t *mac)
{
FAR struct misoc_net_driver_s *priv =
(FAR struct misoc_net_driver_s *)dev->d_private;
@ -1028,8 +1041,8 @@ static int misoc_net_addmac(FAR struct net_driver_s *dev, FAR const uint8_t *mac
* Function: misoc_net_rmmac
*
* Description:
* NuttX Callback: Remove the specified MAC address from the hardware multicast
* address filtering
* NuttX Callback: Remove the specified MAC address from the hardware
* multicast address filtering
*
* Input Parameters:
* dev - Reference to the NuttX driver state structure
@ -1043,7 +1056,8 @@ static int misoc_net_addmac(FAR struct net_driver_s *dev, FAR const uint8_t *mac
****************************************************************************/
#ifdef CONFIG_NET_MCASTGROUP
static int misoc_net_rmmac(FAR struct net_driver_s *dev, FAR const uint8_t *mac)
static int misoc_net_rmmac(FAR struct net_driver_s *dev,
FAR const uint8_t *mac)
{
FAR struct misoc_net_driver_s *priv =
(FAR struct misoc_net_driver_s *)dev->d_private;

49
arch/renesas/src/rx65n/rx65n_eth.c
View file

@ -1088,17 +1088,14 @@ static int rx65n_txpoll(struct net_driver_s *dev)
rx65n_transmit(priv);
DEBUGASSERT(dev->d_len == 0 && dev->d_buf == NULL);
/* Check if the next TX descriptor is owned by the
* Ethernet DMA or CPU.
* We cannot perform the TX poll if we are unable to accept
/* Check if the next TX descriptor is owned by the Ethernet DMA or
* CPU. We cannot perform the TX poll if we are unable to accept
* another packet fo transmission.
* In a race condition, TACT may be cleared
* BUT still not available
* because rx65n_freeframe() has not yet run.
* If rx65n_freeframe() has run,
* the buffer1 pointer (tdes2) will be nullified
* (and inflight should
* be CONFIG_RX65N_ETH_NTXDESC).
*
* In a race condition, TACT may be cleared BUT still not available
* because rx65n_freeframe() has not yet run. If rx65n_freeframe()
* has run, the buffer1 pointer (tdes2) will be nullified (and
* inflight should be CONFIG_RX65N_ETH_NTXDESC).
*/
if ((priv->txhead->tdes0 & TACT) != 0 ||
@ -1167,9 +1164,9 @@ static void rx65n_dopoll(FAR struct rx65n_ethmac_s *priv)
* another packet for transmission.
*
* In a race condition, TACT may be cleared BUT still not available
* because rx65n_freeframe() has not yet run. If rx65n_freeframe() has
* run, the buffer1 pointer (tdes2) will be nullified (and inflight
* should be < CONFIG_RX65N_ETH_NTXDESC).
* because rx65n_freeframe() has not yet run. If rx65n_freeframe()
* has run, the buffer1 pointer (tdes2) will be nullified (and
* inflight should be < CONFIG_RX65N_ETH_NTXDESC).
*/
if ((priv->txhead->tdes0 & TACT) == 0 &&
@ -1481,10 +1478,9 @@ static int rx65n_recvframe(FAR struct rx65n_ethmac_s *priv)
rxdesc = (struct eth_rxdesc_s *)rxdesc->rdes3;
}
/* We get here after all of the descriptors have been scanned or
* when rxdesc points
* to the first descriptor owned by the DMA.
* Remember where we left off.
/* We get here after all of the descriptors have been scanned or when
* rxdesc points to the first descriptor owned by the DMA. Remember
* where we left off.
*/
priv->rxhead = rxdesc;
@ -1528,7 +1524,7 @@ static void rx65n_receive(FAR struct rx65n_ethmac_s *priv)
* tap
*/
pkt_input(&priv->dev);
pkt_input(&priv->dev);
#endif
/* Check if the packet is a valid size for the network
@ -1755,8 +1751,8 @@ static void rx65n_freeframe(FAR struct rx65n_ethmac_s *priv)
priv->inflight--;
/* If all of the TX descriptors were in-flight,
* then RX interrupts may have been disabled... we
* can re-enable them now.
* then RX interrupts may have been disabled...
* we can re-enable them now.
*/
/* Need to check this and update the arguments of the
@ -2116,15 +2112,14 @@ static void rx65n_poll_work(FAR void *arg)
FAR struct rx65n_ethmac_s *priv = (FAR struct rx65n_ethmac_s *)arg;
FAR struct net_driver_s *dev = &priv->dev;
/* Check if the next TX descriptor is owned by the Ethernet DMA or CPU. We
* cannot perform the timer poll if we are unable to accept another packet
* for transmission. Hmmm.. might be bug here. Does this mean if there is
* a transmit in progress, we will miss TCP time state updates?
/* Check if the next TX descriptor is owned by the Ethernet DMA or
* CPU. We cannot perform the TX poll if we are unable to accept
* another packet for transmission.
*
* In a race condition, TACT may be cleared BUT still not available
* because rx65n_freeframe() has not yet run. If rx65n_freeframe() has
* run, the buffer1 pointer (tdes2) will be nullified (and inflight
* should be < CONFIG_RX65N_ETH_NTXDESC).
* because rx65n_freeframe() has not yet run. If rx65n_freeframe()
* has run, the buffer1 pointer (tdes2) will be nullified (and
* inflight should be < CONFIG_RX65N_ETH_NTXDESC).
*/
net_lock();

2
arch/xtensa/src/esp32/esp32_emac.c
View file

@ -1361,7 +1361,7 @@ static void emac_rx_interrupt_work(FAR void *arg)
/* When packet sockets are enabled, feed the frame into the packet tap
*/
pkt_input(&priv->dev);
pkt_input(&priv->dev);
#endif
/* We only accept IP packets of the configured type and ARP packets

22
arch/z80/src/ez80/ez80_emac.c
View file

@ -243,7 +243,9 @@ extern uintptr_t __RAM_ADDR_U_INIT_PARAM;
#define EMAC_EIN_HANDLED \
(EMAC_ISTAT_RXEVENTS | EMAC_ISTAT_TXEVENTS | EMAC_ISTAT_SYSEVENTS)
/* TX poll deley = 1 seconds. CLK_TCK is the number of clock ticks per second */
/* TX poll deley = 1 seconds.
* CLK_TCK is the number of clock ticks per second
*/
#define EMAC_WDDELAY (1*CLK_TCK)
@ -251,7 +253,7 @@ extern uintptr_t __RAM_ADDR_U_INIT_PARAM;
#define EMAC_TXTIMEOUT (60*CLK_TCK)
/* This is a helper pointer for accessing the contents of the Ethernet header */
/* This is a helper pointer for accessing the contents of Ethernet header */
#define ETHBUF ((struct eth_hdr_s *)priv->dev.d_buf)
@ -1081,7 +1083,9 @@ static int ez80emac_transmit(struct ez80emac_driver_s *priv)
txnext->pktsize = 0;
txnext->stat = 0; /* Bit 15: 0=Host (eZ80 CPU) owns, 1=EMAC owns. */
/* Copy the data to the next packet in the Tx buffer (handling wraparound) */
/* Copy the data to the next packet in the Tx buffer
* (handling wraparound)
*/
psrc = priv->dev.d_buf;
pdest = (uint8_t *)txdesc + SIZEOF_EMACSDESC;
@ -1388,9 +1392,9 @@ static int ez80emac_receive(struct ez80emac_driver_s *priv)
inp(EZ80_EMAC_BLKSLFT_H), inp(EZ80_EMAC_BLKSLFT_L));
#ifdef CONFIG_NET_PKT
/* When packet sockets are enabled, feed the frame into the packet tap */
/* When packet sockets are enabled, feed the frame into the tap */
pkt_input(&priv->dev);
pkt_input(&priv->dev);
#endif
/* We only accept IP packets of the configured type and ARP packets */
@ -1556,7 +1560,7 @@ static void ez80emac_txinterrupt_work(FAR void *arg)
txhead, txhead->np, txhead->pktsize, txhead->stat,
inp(EZ80_EMAC_TRP_H), inp(EZ80_EMAC_TRP_L), istat);
/* Handle all packets in the list that are no longer owned by the hardware */
/* Handle all packets in the list that are no longer owned by hardware */
while (txhead && (txhead->stat & EMAC_TXDESC_OWNER) == 0)
{
@ -2217,7 +2221,7 @@ static void ez80emac_txavail_work(FAR void *arg)
net_lock();
if (priv->bifup)
{
/* Check if there is room in the hardware to hold another outgoing packet. */
/* Check if there is room in the hardware to hold another packet. */
/* If so, then poll the network for new XMIT data */
@ -2623,7 +2627,9 @@ int up_netinitialize(void)
priv->txpoll = wd_create(); /* Create periodic poll timer */
priv->txtimeout = wd_create(); /* Create TX timeout timer */
/* Read the MAC address from the hardware into priv->dev.d_mac.ether.ether_addr_octet */
/* Read the MAC address from the hardware into
* priv->dev.d_mac.ether.ether_addr_octet
*/
/* Register the device with the OS so that socket IOCTLs can be performed */

3
drivers/input/ft5x06.c
View file

@ -363,7 +363,8 @@ static void ft5x06_data_worker(FAR void *arg)
#ifdef CONFIG_FT5X06_POLLMODE
/* Exit, re-starting the poll. */
wd_start(priv->polltimer, priv->delay, ft5x06_poll_timeout, 1, (wdparm_t)priv);
wd_start(priv->polltimer, priv->delay,
ft5x06_poll_timeout, 1, (wdparm_t)priv);
#else
/* Exit, re-enabling FT5x06 interrupts */

83
drivers/input/stmpe811_tsc.c
View file

@ -5,7 +5,7 @@
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* References:
* "STMPE811 S-Touch<EFBFBD> advanced resistive touchscreen controller with 8-bit
* "STMPE811 S-Touch advanced resistive touchscreen controller with 8-bit
* GPIO expander," Doc ID 14489 Rev 6, CD00186725, STMicroelectronics"
*
* Redistribution and use in source and binary forms, with or without
@ -75,14 +75,6 @@
* Pre-processor Definitions
****************************************************************************/
#define Direction_IN 0x00
#define Direction_OUT 0x01
#define Polarity_Low 0x00
#define Polarity_High 0x04
#define Type_Level 0x00
#define Type_Edge 0x02
#define IO_IT_0 0x01
#define IO_IT_1 0x02
#define IO_IT_2 0x04
@ -96,10 +88,10 @@
#define IOE_TS_IT (uint8_t)(IO_IT_0 | IO_IT_1 | IO_IT_2)
#define IOE_INMEMS_IT (uint8_t)(IO_IT_2 | IO_IT_3)
#define EDGE_FALLING 0x01
#define EDGE_RISING 0x02
#define TIMEOUT_MAX 0x3000 /*<! The value of the maximal timeout for I2C waiting loops */
#define EDGE_FALLING 0x01
#define EDGE_RISING 0x02
/* <! The value of the maximal timeout for I2C waiting loops */
#define TIMEOUT_MAX 0x3000
/****************************************************************************
* Private Types
@ -108,6 +100,7 @@
/****************************************************************************
* Private Function Prototypes
****************************************************************************/
/* Internal logic */
static void stmpe811_notify(FAR struct stmpe811_dev_s *priv);
@ -151,6 +144,7 @@ static const struct file_operations g_stmpe811fops =
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: stmpe811_notify
*
@ -177,10 +171,10 @@ static void stmpe811_notify(FAR struct stmpe811_dev_s *priv)
nxsem_post(&priv->waitsem);
}
/* If there are threads waiting on poll() for STMPE811 data to become available,
* then wake them up now. NOTE: we wake up all waiting threads because we
* do not know that they are going to do. If they all try to read the data,
* then some make end up blocking after all.
/* If there are threads waiting on poll() for STMPE811 data to become
* available, then wake them up now. NOTE: we wake up all waiting threads
* because we do not know that they are going to do. If they all try to
* read the data, then some make end up blocking after all.
*/
for (i = 0; i < CONFIG_STMPE811_NPOLLWAITERS; i++)
@ -238,15 +232,15 @@ static int stmpe811_sample(FAR struct stmpe811_dev_s *priv,
priv->id++;
}
else if (sample->contact == CONTACT_DOWN)
{
{
/* The sampling logic has detected pen-up in some condition other
* than CONTACT_MOVE. Set the next state to CONTACT_MOVE: Further
* samples collected while the pen is down will reported as movement
* events.
* than CONTACT_MOVE. Set the next state to CONTACT_MOVE: Further
* samples collected while the pen is down will reported as
* movement events.
*/
priv->sample.contact = CONTACT_MOVE;
}
}
priv->penchange = false;
ret = OK;
@ -304,7 +298,7 @@ static inline int stmpe811_waitsample(FAR struct stmpe811_dev_s *priv,
}
/* Re-acquire the semaphore that manages mutually exclusive access to
* the device structure. We may have to wait here. But we have our sample.
* the device structure. We may have to wait here. But we have our sample.
* Interrupts and pre-emption will be re-enabled while we wait.
*/
@ -432,7 +426,8 @@ static int stmpe811_close(FAR struct file *filep)
*
****************************************************************************/
static ssize_t stmpe811_read(FAR struct file *filep, FAR char *buffer, size_t len)
static ssize_t stmpe811_read(FAR struct file *filep,
FAR char *buffer, size_t len)
{
FAR struct inode *inode;
FAR struct stmpe811_dev_s *priv;
@ -483,7 +478,7 @@ static ssize_t stmpe811_read(FAR struct file *filep, FAR char *buffer, size_t le
{
ret = -EAGAIN;
goto errout;
}
}
/* Wait for sample data */
@ -755,7 +750,8 @@ static void stmpe811_timeout(int argc, wdparm_t arg1, ...)
* action should be required to protect the work queue.
*/
ret = work_queue(HPWORK, &priv->timeout, stmpe811_timeoutworker, priv, 0);
ret = work_queue(HPWORK, &priv->timeout,
stmpe811_timeoutworker, priv, 0);
if (ret != 0)
{
ierr("ERROR: Failed to queue work: %d\n", ret);
@ -811,8 +807,8 @@ static inline void stmpe811_tscinitialize(FAR struct stmpe811_dev_s *priv)
/* Select 2 nF filter capacitor */
stmpe811_putreg8(priv, STMPE811_TSC_CFG,
(TSC_CFG_AVE_CTRL_4SAMPLES | TSC_CFG_TOUCH_DELAY_500US | TSC_CFG_SETTLING_500US));
stmpe811_putreg8(priv, STMPE811_TSC_CFG, TSC_CFG_AVE_CTRL_4SAMPLES |
TSC_CFG_TOUCH_DELAY_500US | TSC_CFG_SETTLING_500US);
/* Select single point reading */
@ -926,7 +922,7 @@ int stmpe811_register(STMPE811_HANDLE handle, int minor)
/* Inidicate that the touchscreen controller was successfully initialized */
priv->inuse |= TSC_PIN_SET; /* Pins 4-7 are now in-use */
priv->flags |= STMPE811_FLAGS_TSC_INITIALIZED; /* TSC function is initialized */
priv->flags |= STMPE811_FLAGS_TSC_INITIALIZED; /* TSC function is initialized */
nxsem_post(&priv->exclsem);
return ret;
}
@ -955,23 +951,23 @@ void stmpe811_tscworker(FAR struct stmpe811_dev_s *priv, uint8_t intsta)
wd_cancel(priv->wdog);
/* Check for pen up or down from the TSC_STA ibit n the STMPE811_TSC_CTRL register. */
/* Check for pen up or down from the TSC_STA bit in STMPE811_TSC_CTRL. */
pendown = (stmpe811_getreg8(priv, STMPE811_TSC_CTRL) & TSC_CTRL_TSC_STA) != 0;
pendown = !!(stmpe811_getreg8(priv, STMPE811_TSC_CTRL) & TSC_CTRL_TSC_STA);
/* Handle the change from pen down to pen up */
if (!pendown)
{
/* The pen is up.. reset thresholding variables. FIFOs will read zero if
* there is no data available (hence the choice of (0,0))
/* The pen is up.. reset thresholding variables. FIFOs will read zero
* if there is no data available (hence the choice of (0,0))
*/
priv->threshx = 0;
priv->threshy = 0;
/* Ignore the interrupt if the pen was already up (CONTACT_NONE == pen up and
* already reported; CONTACT_UP == pen up, but not reported)
/* Ignore the interrupt if the pen was already up (CONTACT_NONE == pen
* up and already reported; CONTACT_UP == pen up, but not reported)
*/
if (priv->sample.contact == CONTACT_NONE ||
@ -980,9 +976,9 @@ void stmpe811_tscworker(FAR struct stmpe811_dev_s *priv, uint8_t intsta)
goto ignored;
}
/* A pen-down to up transition has been detected. CONTACT_UP indicates the
* initial loss of contact. The state will be changed to CONTACT_NONE
* after the loss of contact is sampled.
/* A pen-down to up transition has been detected. CONTACT_UP indicates
* the initial loss of contact. The state will be changed to
* CONTACT_NONE after the loss of contact is sampled.
*/
priv->sample.contact = CONTACT_UP;
@ -1021,9 +1017,10 @@ void stmpe811_tscworker(FAR struct stmpe811_dev_s *priv, uint8_t intsta)
goto ignored;
}
/* Perform a thresholding operation so that the results will be more stable.
* If the difference from the last sample is small, then ignore the event.
* REVISIT: Should a large change in pressure also generate a event?
/* Perform a thresholding operation so that the results will be more
* stable. If the difference from the last sample is small, then ignore
* the event. REVISIT: Should a large change in pressure also generate
* a event?
*/
xdiff = x > priv->threshx ? (x - priv->threshx) : (priv->threshx - x);
@ -1031,7 +1028,9 @@ void stmpe811_tscworker(FAR struct stmpe811_dev_s *priv, uint8_t intsta)
if (xdiff < CONFIG_STMPE811_THRESHX && ydiff < CONFIG_STMPE811_THRESHY)
{
/* Little or no change in either direction ... don't report anything. */
/* Little or no change in either direction ...
* don't report anything.
*/
goto ignored;
}

77
drivers/net/dm90x0.c
View file

@ -284,7 +284,9 @@
# define CONFIG_DM9X_MODE_AUTO 1
#endif
/* TX poll deley = 1 seconds. CLK_TCK is the number of clock ticks per second */
/* TX poll deley = 1 seconds.
* CLK_TCK is the number of clock ticks per second
*/
#define DM9X_WDDELAY (1*CLK_TCK)
@ -292,7 +294,7 @@
#define DM6X_TXTIMEOUT (60*CLK_TCK)
/* This is a helper pointer for accessing the contents of the Ethernet header */
/* This is a helper pointer for accessing the contents of Ethernet header */
#define BUF ((struct eth_hdr_s *)priv->dm_dev.d_buf)
@ -798,7 +800,8 @@ static int dm9x_transmit(FAR struct dm9x_driver_s *priv)
static int dm9x_txpoll(FAR struct net_driver_s *dev)
{
FAR struct dm9x_driver_s *priv = (FAR struct dm9x_driver_s *)dev->d_private;
FAR struct dm9x_driver_s *priv =
(FAR struct dm9x_driver_s *)dev->d_private;
/* If the polling resulted in data that should be sent out on the network,
* the field d_len is set to a value > 0.
@ -841,15 +844,15 @@ static int dm9x_txpoll(FAR struct net_driver_s *dev)
if (priv->dm_ntxpending > 1 || !priv->dm_b100m)
{
/* Returning a non-zero value will terminate the poll operation */
/* Returning a non-zero value terminate the poll operation */
return 1;
}
}
}
/* If zero is returned, the polling will continue until all connections have
* been examined.
/* If zero is returned, the polling will continue until all connections
* have been examined.
*/
return 0;
@ -920,7 +923,7 @@ static void dm9x_receive(FAR struct dm9x_driver_s *priv)
priv->dm_discard(rx.desc.rx_len);
}
/* Also check if the packet is a valid size for the network configuration */
/* Also check if the packet is a valid size for the configuration */
else if (rx.desc.rx_len < ETH_HDRLEN ||
rx.desc.rx_len > (CONFIG_NET_ETH_PKTSIZE + 2))
@ -934,18 +937,20 @@ static void dm9x_receive(FAR struct dm9x_driver_s *priv)
}
else
{
/* Good packet... Copy the packet data out of SRAM and pass it one to the network */
/* Good packet...
* Copy the packet data out of SRAM and pass it one to the network
*/
priv->dm_dev.d_len = rx.desc.rx_len;
priv->dm_read(priv->dm_dev.d_buf, rx.desc.rx_len);
#ifdef CONFIG_NET_PKT
/* When packet sockets are enabled, feed the frame into the packet tap */
/* When packet sockets are enabled, feed the frame into the tap */
pkt_input(&priv->dm_dev);
#endif
/* We only accept IP packets of the configured type and ARP packets */
/* We accept IP packets of the configured type and ARP packets */
#ifdef CONFIG_NET_IPv4
if (BUF->type == HTONS(ETHTYPE_IP))
@ -960,14 +965,14 @@ static void dm9x_receive(FAR struct dm9x_driver_s *priv)
arp_ipin(&priv->dm_dev);
ipv4_input(&priv->dm_dev);
/* If the above function invocation resulted in data that should
* be sent out on the network, the field d_len will set to a
* value > 0.
/* If the above function invocation resulted in data that
* should be sent out on the network, the field d_len will
* set to a value > 0.
*/
if (priv->dm_dev.d_len > 0)
{
/* Update the Ethernet header with the correct MAC address */
/* Update Ethernet header with the correct MAC address */
#ifdef CONFIG_NET_IPv6
if (IFF_IS_IPv4(priv->dm_dev.d_flags))
@ -999,14 +1004,14 @@ static void dm9x_receive(FAR struct dm9x_driver_s *priv)
ipv6_input(&priv->dm_dev);
/* If the above function invocation resulted in data that should
* be sent out on the network, the field d_len will set to a
* value > 0.
/* If the above function invocation resulted in data that
* should be sent out on the network, the field d_len will
* set to a value > 0.
*/
if (priv->dm_dev.d_len > 0)
{
/* Update the Ethernet header with the correct MAC address */
/* Update Ethernet header with the correct MAC address */
#ifdef CONFIG_NET_IPv4
if (IFF_IS_IPv4(priv->dm_dev.d_flags))
@ -1034,9 +1039,9 @@ static void dm9x_receive(FAR struct dm9x_driver_s *priv)
arp_arpin(&priv->dm_dev);
NETDEV_RXARP(&priv->dm_dev);
/* If the above function invocation resulted in data that should
* be sent out on the network, the field d_len will set to a
* value > 0.
/* If the above function invocation resulted in data that
* should be sent out on the network, the field d_len will set
* to a value > 0.
*/
if (priv->dm_dev.d_len > 0)
@ -1054,7 +1059,8 @@ static void dm9x_receive(FAR struct dm9x_driver_s *priv)
NETDEV_RXPACKETS(&priv->dm_dev);
priv->ncrxpackets++;
}
while ((rxbyte & 0x01) == DM9X_PKTRDY && priv->ncrxpackets < DM9X_CRXTHRES);
while ((rxbyte & 0x01) == DM9X_PKTRDY &&
priv->ncrxpackets < DM9X_CRXTHRES);
ninfo("All RX packets processed\n");
}
@ -1414,7 +1420,7 @@ static void dm9x_poll_work(FAR void *arg)
if (priv->dm_ntxpending < 1 || (priv->dm_b100m && priv->dm_ntxpending < 2))
{
/* If so, update TCP timing states and poll the network for new XMIT data */
/* Update TCP timing states and poll the network for new XMIT data */
devif_timer(&priv->dm_dev, DM9X_WDDELAY, dm9x_txpoll);
}
@ -1516,7 +1522,8 @@ static inline void dm9x_phymode(FAR struct dm9x_driver_s *priv)
static int dm9x_ifup(FAR struct net_driver_s *dev)
{
FAR struct dm9x_driver_s *priv = (FAR struct dm9x_driver_s *)dev->d_private;
FAR struct dm9x_driver_s *priv =
(FAR struct dm9x_driver_s *)dev->d_private;
uint8_t netstatus;
int i;
@ -1584,7 +1591,8 @@ static int dm9x_ifup(FAR struct net_driver_s *dev)
static int dm9x_ifdown(FAR struct net_driver_s *dev)
{
FAR struct dm9x_driver_s *priv = (FAR struct dm9x_driver_s *)dev->d_private;
FAR struct dm9x_driver_s *priv =
(FAR struct dm9x_driver_s *)dev->d_private;
irqstate_t flags;
ninfo("Stopping\n");
@ -1631,7 +1639,8 @@ static int dm9x_ifdown(FAR struct net_driver_s *dev)
static void dm9x_txavail_work(FAR void *arg)
{
FAR struct dm9x_driver_s *priv = (FAR struct dm9x_driver_s *)arg;
FAR struct dm9x_driver_s *priv =
(FAR struct dm9x_driver_s *)arg;
ninfo("Polling\n");
@ -1640,7 +1649,7 @@ static void dm9x_txavail_work(FAR void *arg)
net_lock();
if (priv->dm_bifup)
{
/* Check if there is room in the DM90x0 to hold another packet. In 100M
/* Check if there is room in the DM90x0 to hold another packet. In 100M
* mode, that can be 2 packets, otherwise it is a single packet.
*/
@ -1677,7 +1686,8 @@ static void dm9x_txavail_work(FAR void *arg)
static int dm9x_txavail(FAR struct net_driver_s *dev)
{
FAR struct dm9x_driver_s *priv = (FAR struct dm9x_driver_s *)dev->d_private;
FAR struct dm9x_driver_s *priv =
(FAR struct dm9x_driver_s *)dev->d_private;
/* Is our single work structure available? It may not be if there are
* pending interrupt actions and we will have to ignore the Tx
@ -1715,7 +1725,8 @@ static int dm9x_txavail(FAR struct net_driver_s *dev)
#ifdef CONFIG_NET_MCASTGROUP
static int dm9x_addmac(FAR struct net_driver_s *dev, FAR const uint8_t *mac)
{
FAR struct dm9x_driver_s *priv = (FAR struct dm9x_driver_s *)dev->d_private;
FAR struct dm9x_driver_s *priv =
(FAR struct dm9x_driver_s *)dev->d_private;
/* Add the MAC address to the hardware multicast routing table */
@ -1745,7 +1756,8 @@ static int dm9x_addmac(FAR struct net_driver_s *dev, FAR const uint8_t *mac)
#ifdef CONFIG_NET_MCASTGROUP
static int dm9x_rmmac(FAR struct net_driver_s *dev, FAR const uint8_t *mac)
{
FAR struct dm9x_driver_s *priv = (FAR struct dm9x_driver_s *)dev->d_private;
FAR struct dm9x_driver_s *priv =
(FAR struct dm9x_driver_s *)dev->d_private;
/* Add the MAC address to the hardware multicast routing table */
@ -1826,7 +1838,8 @@ static void dm9x_bringup(FAR struct dm9x_driver_s *priv)
putreg(DM9X_TXC, 0x00); /* Clear TX Polling */
putreg(DM9X_BPTHRES, 0x3f); /* Less 3kb, 600us */
putreg(DM9X_SMODEC, 0x00); /* Special mode */
putreg(DM9X_NETS, (DM9X_NETS_WAKEST | DM9X_NETS_TX1END | DM9X_NETS_TX2END)); /* Clear TX status */
/* Clear TX status */
putreg(DM9X_NETS, DM9X_NETS_WAKEST | DM9X_NETS_TX1END | DM9X_NETS_TX2END);
putreg(DM9X_ISR, DM9X_INT_ALL); /* Clear interrupt status */
#if defined(CONFIG_DM9X_CHECKSUM)
@ -1947,7 +1960,7 @@ int dm9x_initialize(void)
if (vid != DM9X_DAVICOMVID ||
(pid != DM9X_DM9000PID && pid != DM9X_DM9010PID))
{
nerr("ERROR: DM90x0 vendor/product ID not found at this base address\n");
nerr("ERROR: vendor/product ID not found at this base address\n");
return -ENODEV;
}

8
drivers/net/enc28j60.c
View file

@ -1387,7 +1387,7 @@ static void enc_rxerif(FAR struct enc_driver_s *priv)
static void enc_rxdispatch(FAR struct enc_driver_s *priv)
{
#ifdef CONFIG_NET_PKT
/* When packet sockets are enabled, feed the frame into the packet tap */
/* When packet sockets are enabled, feed the frame into the tap */
pkt_input(&priv->dev);
#endif
@ -1408,7 +1408,7 @@ static void enc_rxdispatch(FAR struct enc_driver_s *priv)
ipv4_input(&priv->dev);
/* If the above function invocation resulted in data that should be
* sent out on the network, the field d_len will set to a value > 0.
* sent out on the network, d_len field will set to a value > 0.
*/
if (priv->dev.d_len > 0)
@ -1446,7 +1446,7 @@ static void enc_rxdispatch(FAR struct enc_driver_s *priv)
ipv6_input(&priv->dev);
/* If the above function invocation resulted in data that should be
* sent out on the network, the field d_len will set to a value > 0.
* sent out on the network, d_len field will set to a value > 0.
*/
if (priv->dev.d_len > 0)
@ -1482,7 +1482,7 @@ static void enc_rxdispatch(FAR struct enc_driver_s *priv)
arp_arpin(&priv->dev);
/* If the above function invocation resulted in data that should be
* sent out on the network, the field d_len will set to a value > 0.
* sent out on the network, d_len field will set to a value > 0.
*/
if (priv->dev.d_len > 0)

2
drivers/net/encx24j600.c
View file

@ -1485,7 +1485,7 @@ static void enc_rxdispatch(FAR struct enc_driver_s *priv)
#ifdef CONFIG_NET_PKT
/* When packet sockets are enabled, feed the frame to the packet tap */
pkt_input(&priv->dev);
pkt_input(&priv->dev);
#endif
/* We only accept IP packets of the configured type and ARP packets */

44
drivers/net/lan91c111.c
View file

@ -83,7 +83,9 @@
# define lan91c111_dumppacket(m, b, l)
#endif
/* TX poll delay = 1 seconds. CLK_TCK is the number of clock ticks per second */
/* TX poll delay = 1 seconds.
* CLK_TCK is the number of clock ticks per second
*/
#define LAN91C111_WDDELAY (1*CLK_TCK)
@ -101,12 +103,12 @@
struct lan91c111_driver_s
{
uintptr_t base; /* Base address */
int irq; /* IRQ number */
uint16_t bank; /* Current bank */
WDOG_ID txpoll; /* TX poll timer */
struct work_s irqwork; /* For deferring interrupt work to the work queue */
struct work_s pollwork; /* For deferring poll work to the work queue */
uintptr_t base; /* Base address */
int irq; /* IRQ number */
uint16_t bank; /* Current bank */
WDOG_ID txpoll; /* TX poll timer */
struct work_s irqwork; /* For deferring interrupt work to the work queue */
struct work_s pollwork; /* For deferring poll work to the work queue */
uint8_t pktbuf[MAX_NETDEV_PKTSIZE + 4]; /* +4 due to getregs32/putregs32 */
/* This holds the information visible to the NuttX network */
@ -187,7 +189,8 @@ static uint8_t getreg8(FAR struct lan91c111_driver_s *priv, uint16_t offset)
return *(FAR volatile uint8_t *)(priv->base + offset);
}
static uint16_t getreg16(FAR struct lan91c111_driver_s *priv, uint16_t offset)
static uint16_t getreg16(FAR struct lan91c111_driver_s *priv,
uint16_t offset)
{
offset = updatebank(priv, offset);
return *(FAR volatile uint16_t *)(priv->base + offset);
@ -559,8 +562,8 @@ static int lan91c111_txpoll(FAR struct net_driver_s *dev)
}
}
/* If zero is returned, the polling will continue until all connections have
* been examined.
/* If zero is returned, the polling will continue until all connections
* have been examined.
*/
return 0;
@ -691,7 +694,7 @@ static void lan91c111_receive(FAR struct net_driver_s *dev)
NETDEV_RXPACKETS(dev);
#ifdef CONFIG_NET_PKT
/* When packet sockets are enabled, feed the frame into the packet tap */
/* When packet sockets are enabled, feed the frame into the tap */
pkt_input(dev);
#endif
@ -904,7 +907,9 @@ static void lan91c111_interrupt_work(FAR void *arg)
/* Handle interrupts according to status bit settings */
/* Check if we received an incoming packet, if so, call lan91c111_receive() */
/* Check if we received an incoming packet,
* if so, call lan91c111_receive()
*/
if (status & IM_RCV_INT)
{
@ -916,14 +921,18 @@ static void lan91c111_interrupt_work(FAR void *arg)
NETDEV_RXERRORS(dev);
}
/* Check if a packet transmission just completed. If so, call lan91c111_txdone. */
/* Check if a packet transmission just completed.
* If so, call lan91c111_txdone.
*/
if (status & IM_TX_INT)
{
lan91c111_txdone(dev);
}
/* Check if we have the phy interrupt, if so, call lan91c111_phy_notify() */
/* Check if we have the phy interrupt,
* if so, call lan91c111_phy_notify()
*/
if (status & IM_MDINT)
{
@ -1102,7 +1111,7 @@ static int lan91c111_ifup(FAR struct net_driver_s *dev)
net_lock();
/* Initialize PHYs, the Ethernet interface, and setup up Ethernet interrupts */
/* Initialize PHYs, Ethernet interface, and setup up Ethernet interrupts */
putreg16(priv, CONFIG_REG, CONFIG_DEFAULT);
putreg16(priv, CTL_REG, CTL_DEFAULT);
@ -1580,7 +1589,8 @@ int lan91c111_initialize(uintptr_t base, int irq)
macrev = getreg16(priv, REV_REG);
phyid = getphy(priv, MII_PHYID1) << 16;
phyid |= getphy(priv, MII_PHYID2);
ninfo("base: %08x irq: %d rev: %04x phy: %08x\n", base, irq, macrev, phyid);
ninfo("base: %08x irq: %d rev: %04x phy: %08x\n",
base, irq, macrev, phyid);
if ((macrev >> 4 & 0x0f) != CHIP_91111FD || phyid != PHY_LAN83C183)
{
@ -1636,7 +1646,7 @@ int lan91c111_initialize(uintptr_t base, int irq)
/* Loop, reset don't finish yet */
}
/* Read the MAC address from the hardware into dev->d_mac.ether.ether_addr_octet */
/* Read MAC address from the hardware into dev->d_mac.ether */
copyfrom16(priv, ADDR0_REG, &dev->d_mac.ether, sizeof(dev->d_mac.ether));

8
drivers/net/loopback.c
View file

@ -75,7 +75,9 @@
# error Worker thread support is required (CONFIG_SCHED_WORKQUEUE)
#endif
/* TX poll delay = 1 seconds. CLK_TCK is the number of clock ticks per second */
/* TX poll delay = 1 seconds.
* CLK_TCK is the number of clock ticks per second
*/
#define LO_WDDELAY (1*CLK_TCK)
@ -172,7 +174,7 @@ static int lo_txpoll(FAR struct net_driver_s *dev)
NETDEV_RXPACKETS(&priv->lo_dev);
#ifdef CONFIG_NET_PKT
/* When packet sockets are enabled, feed the frame into the packet tap */
/* When packet sockets are enabled, feed the frame into the tap */
pkt_input(&priv->lo_dev);
#endif
@ -521,7 +523,7 @@ int localhost_initialize(void)
priv->lo_dev.d_rmmac = lo_rmmac; /* Remove multicast MAC address */
#endif
priv->lo_dev.d_buf = g_iobuffer; /* Attach the IO buffer */
priv->lo_dev.d_private = (FAR void *)priv; /* Used to recover private state from dev */
priv->lo_dev.d_private = priv; /* Used to recover private state from dev */
/* Create a watchdog for timing polling for and timing of transmissions */

2
drivers/net/rpmsgdrv.c
View file

@ -637,7 +637,7 @@ static int net_rpmsg_drv_transfer_handler(FAR struct rpmsg_endpoint *ept,
dev->d_len = msg->length;
#ifdef CONFIG_NET_PKT
/* When packet sockets are enabled, feed the frame into the packet tap */
/* When packet sockets are enabled, feed the frame into the tap */
pkt_input(dev);
#endif

75
drivers/net/skeleton.c
View file

@ -83,23 +83,25 @@
#define ETHWORK LPWORK
/* CONFIG_skeleton_NINTERFACES determines the number of physical interfaces
/* CONFIG_SKELETON_NINTERFACES determines the number of physical interfaces
* that will be supported.
*/
#ifndef CONFIG_skeleton_NINTERFACES
# define CONFIG_skeleton_NINTERFACES 1
#ifndef CONFIG_SKELETON_NINTERFACES
# define CONFIG_SKELETON_NINTERFACES 1
#endif
/* TX poll delay = 1 seconds. CLK_TCK is the number of clock ticks per second */
/* TX poll delay = 1 seconds.
* CLK_TCK is the number of clock ticks per second
*/
#define skeleton_WDDELAY (1*CLK_TCK)
#define SKELETON_WDDELAY (1*CLK_TCK)
/* TX timeout = 1 minute */
#define skeleton_TXTIMEOUT (60*CLK_TCK)
#define SKELETON_TXTIMEOUT (60*CLK_TCK)
/* This is a helper pointer for accessing the contents of the Ethernet header */
/* This is a helper pointer for accessing the contents of Ethernet header */
#define BUF ((struct eth_hdr_s *)priv->sk_dev.d_buf)
@ -139,7 +141,7 @@ struct skel_driver_s
* descriptors in rings to implement such a pipeline. This example assumes
* much simpler hardware that simply handles one packet at a time.
*
* NOTE that if CONFIG_skeleton_NINTERFACES were greater than 1, you would
* NOTE that if CONFIG_SKELETON_NINTERFACES were greater than 1, you would
* need a minimum on one packet buffer per instance. Much better to be
* allocated dynamically in cases where more than one are needed.
*/
@ -148,7 +150,7 @@ static uint8_t g_pktbuf[MAX_NETDEV_PKTSIZE + CONFIG_NET_GUARDSIZE];
/* Driver state structure */
static struct skel_driver_s g_skel[CONFIG_skeleton_NINTERFACES];
static struct skel_driver_s g_skel[CONFIG_SKELETON_NINTERFACES];
/****************************************************************************
* Private Function Prototypes
@ -239,7 +241,7 @@ static int skel_transmit(FAR struct skel_driver_s *priv)
/* Setup the TX timeout watchdog (perhaps restarting the timer) */
wd_start(priv->sk_txtimeout, skeleton_TXTIMEOUT,
wd_start(priv->sk_txtimeout, SKELETON_TXTIMEOUT,
skel_txtimeout_expiry, 1, (wdparm_t)priv);
return OK;
}
@ -269,7 +271,8 @@ static int skel_transmit(FAR struct skel_driver_s *priv)
static int skel_txpoll(FAR struct net_driver_s *dev)
{
FAR struct skel_driver_s *priv = (FAR struct skel_driver_s *)dev->d_private;
FAR struct skel_driver_s *priv =
(FAR struct skel_driver_s *)dev->d_private;
/* If the polling resulted in data that should be sent out on the network,
* the field d_len is set to a value > 0.
@ -316,8 +319,8 @@ static int skel_txpoll(FAR struct net_driver_s *dev)
}
}
/* If zero is returned, the polling will continue until all connections have
* been examined.
/* If zero is returned, the polling will continue until all connections
* have been examined.
*/
return 0;
@ -412,7 +415,7 @@ static void skel_receive(FAR struct skel_driver_s *priv)
*/
#ifdef CONFIG_NET_PKT
/* When packet sockets are enabled, feed the frame into the packet tap */
/* When packet sockets are enabled, feed the frame into the tap */
pkt_input(&priv->sk_dev);
#endif
@ -574,7 +577,7 @@ static void skel_interrupt_work(FAR void *arg)
/* Re-enable Ethernet interrupts */
up_enable_irq(CONFIG_skeleton_IRQ);
up_enable_irq(CONFIG_SKELETON_IRQ);
}
/****************************************************************************
@ -607,7 +610,7 @@ static int skel_interrupt(int irq, FAR void *context, FAR void *arg)
* condition here.
*/
up_disable_irq(CONFIG_skeleton_IRQ);
up_disable_irq(CONFIG_SKELETON_IRQ);
/* TODO: Determine if a TX transfer just completed */
@ -693,7 +696,7 @@ static void skel_txtimeout_expiry(int argc, wdparm_t arg, ...)
* condition with interrupt work that is already queued and in progress.
*/
up_disable_irq(CONFIG_skeleton_IRQ);
up_disable_irq(CONFIG_SKELETON_IRQ);
/* Schedule to perform the TX timeout processing on the worker thread. */
@ -740,11 +743,11 @@ static void skel_poll_work(FAR void *arg)
* progress, we will missing TCP time state updates?
*/
devif_timer(&priv->sk_dev, skeleton_WDDELAY, skel_txpoll);
devif_timer(&priv->sk_dev, SKELETON_WDDELAY, skel_txpoll);
/* Setup the watchdog poll timer again */
wd_start(priv->sk_txpoll, skeleton_WDDELAY,
wd_start(priv->sk_txpoll, SKELETON_WDDELAY,
skel_poll_expiry, 1, (wdparm_t)priv);
net_unlock();
}
@ -797,7 +800,8 @@ static void skel_poll_expiry(int argc, wdparm_t arg, ...)
static int skel_ifup(FAR struct net_driver_s *dev)
{
FAR struct skel_driver_s *priv = (FAR struct skel_driver_s *)dev->d_private;
FAR struct skel_driver_s *priv =
(FAR struct skel_driver_s *)dev->d_private;
#ifdef CONFIG_NET_IPv4
ninfo("Bringing up: %d.%d.%d.%d\n",
@ -811,9 +815,9 @@ static int skel_ifup(FAR struct net_driver_s *dev)
dev->d_ipv6addr[6], dev->d_ipv6addr[7]);
#endif
/* Initialize PHYs, the Ethernet interface, and setup up Ethernet interrupts */
/* Initialize PHYs, Ethernet interface, and setup up Ethernet interrupts */
/* Instantiate the MAC address from priv->sk_dev.d_mac.ether.ether_addr_octet */
/* Instantiate MAC address from priv->sk_dev.d_mac.ether.ether_addr_octet */
#ifdef CONFIG_NET_ICMPv6
/* Set up IPv6 multicast address filtering */
@ -823,13 +827,13 @@ static int skel_ifup(FAR struct net_driver_s *dev)
/* Set and activate a timer process */
wd_start(priv->sk_txpoll, skeleton_WDDELAY,
wd_start(priv->sk_txpoll, SKELETON_WDDELAY,
skel_poll_expiry, 1, (wdparm_t)priv);
/* Enable the Ethernet interrupt */
priv->sk_bifup = true;
up_enable_irq(CONFIG_skeleton_IRQ);
up_enable_irq(CONFIG_SKELETON_IRQ);
return OK;
}
@ -852,13 +856,14 @@ static int skel_ifup(FAR struct net_driver_s *dev)
static int skel_ifdown(FAR struct net_driver_s *dev)
{
FAR struct skel_driver_s *priv = (FAR struct skel_driver_s *)dev->d_private;
FAR struct skel_driver_s *priv =
(FAR struct skel_driver_s *)dev->d_private;
irqstate_t flags;
/* Disable the Ethernet interrupt */
flags = enter_critical_section();
up_disable_irq(CONFIG_skeleton_IRQ);
up_disable_irq(CONFIG_SKELETON_IRQ);
/* Cancel the TX poll timer and TX timeout timers */
@ -910,7 +915,7 @@ static void skel_txavail_work(FAR void *arg)
if (priv->sk_bifup)
{
/* Check if there is room in the hardware to hold another outgoing packet. */
/* Check if there is room in the hardware to hold another packet. */
/* If so, then poll the network for new XMIT data */
@ -941,7 +946,8 @@ static void skel_txavail_work(FAR void *arg)
static int skel_txavail(FAR struct net_driver_s *dev)
{
FAR struct skel_driver_s *priv = (FAR struct skel_driver_s *)dev->d_private;
FAR struct skel_driver_s *priv =
(FAR struct skel_driver_s *)dev->d_private;
/* Is our single work structure available? It may not be if there are
* pending interrupt actions and we will have to ignore the Tx
@ -977,7 +983,8 @@ static int skel_txavail(FAR struct net_driver_s *dev)
#if defined(CONFIG_NET_MCASTGROUP) || defined(CONFIG_NET_ICMPv6)
static int skel_addmac(FAR struct net_driver_s *dev, FAR const uint8_t *mac)
{
FAR struct skel_driver_s *priv = (FAR struct skel_driver_s *)dev->d_private;
FAR struct skel_driver_s *priv =
(FAR struct skel_driver_s *)dev->d_private;
/* Add the MAC address to the hardware multicast routing table */
@ -1004,7 +1011,8 @@ static int skel_addmac(FAR struct net_driver_s *dev, FAR const uint8_t *mac)
#ifdef CONFIG_NET_MCASTGROUP
static int skel_rmmac(FAR struct net_driver_s *dev, FAR const uint8_t *mac)
{
FAR struct skel_driver_s *priv = (FAR struct skel_driver_s *)dev->d_private;
FAR struct skel_driver_s *priv =
(FAR struct skel_driver_s *)dev->d_private;
/* Add the MAC address to the hardware multicast routing table */
@ -1107,7 +1115,8 @@ static void skel_ipv6multicast(FAR struct skel_driver_s *priv)
static int skel_ioctl(FAR struct net_driver_s *dev, int cmd,
unsigned long arg)
{
FAR struct skel_driver_s *priv = (FAR struct skel_driver_s *)dev->d_private;
FAR struct skel_driver_s *priv =
(FAR struct skel_driver_s *)dev->d_private;
int ret;
/* Decode and dispatch the driver-specific IOCTL command */
@ -1153,14 +1162,14 @@ int skel_initialize(int intf)
/* Get the interface structure associated with this interface number. */
DEBUGASSERT(intf < CONFIG_skeleton_NINTERFACES);
DEBUGASSERT(intf < CONFIG_SKELETON_NINTERFACES);
priv = &g_skel[intf];
/* Check if a Ethernet chip is recognized at its I/O base */
/* Attach the IRQ to the driver */
if (irq_attach(CONFIG_skeleton_IRQ, skel_interrupt, priv))
if (irq_attach(CONFIG_SKELETON_IRQ, skel_interrupt, priv))
{
/* We could not attach the ISR to the interrupt */

10
drivers/net/tun.c
View file

@ -105,8 +105,8 @@
#define NET_TUN_PKTSIZE ((CONFIG_NET_TUN_PKTSIZE + CONFIG_NET_GUARDSIZE + 1) & ~1)
/* TX poll delay = 1 seconds. CLK_TCK is the number of clock ticks per
* second
/* TX poll delay = 1 seconds.
* CLK_TCK is the number of clock ticks per second
*/
#define TUN_WDDELAY (1 * CLK_TCK)
@ -572,7 +572,7 @@ static void tun_net_receive_tap(FAR struct tun_device_s *priv)
NETDEV_RXPACKETS(&priv->dev);
#ifdef CONFIG_NET_PKT
/* When packet sockets are enabled, feed the frame into the packet tap */
/* When packet sockets are enabled, feed the frame into the tap */
pkt_input(&priv->dev);
#endif
@ -684,7 +684,7 @@ static void tun_net_receive_tun(FAR struct tun_device_s *priv)
NETDEV_RXPACKETS(&priv->dev);
#ifdef CONFIG_NET_PKT
/* When packet sockets are enabled, feed the frame into the packet tap */
/* When packet sockets are enabled, feed the frame into the tap */
pkt_input(&priv->dev);
#endif
@ -721,7 +721,7 @@ static void tun_net_receive_tun(FAR struct tun_device_s *priv)
}
/* If the above function invocation resulted in data that should be
* sent out on the network, the field d_len will set to a value > 0.
* sent out on the network, d_len field will set to a value > 0.
*/
if (priv->dev.d_len > 0)

6
drivers/sensors/ak09912.c
View file

@ -84,8 +84,8 @@
#define AK09912_ASAX 0x60
/* REGISTER: CNTL1
* Enable or disable temparator measure or enable or disable Noise suppression
* filter.
* Enable or disable temparator measure or enable or disable Noise
* suppression filter.
*/
#define AK09912_CTRL1 0x30
@ -676,7 +676,7 @@ int ak09912_register(FAR const char *devpath, FAR struct i2c_master_s *i2c)
/* Initialize the AK09912 device structure */
priv = (FAR struct ak09912_dev_s *)kmm_malloc(sizeof(struct ak09912_dev_s));
priv = kmm_malloc(sizeof(struct ak09912_dev_s));
if (!priv)
{
snerr("Failed to allocate instance\n");

38
drivers/usbdev/cdcacm.c
View file

@ -177,20 +177,20 @@ static int cdcacm_requeue_rdrequest(FAR struct cdcacm_dev_s *priv,
static int cdcacm_release_rxpending(FAR struct cdcacm_dev_s *priv);
static void cdcacm_rxtimeout(int argc, wdparm_t arg1, ...);
/* Request helpers *********************************************************/
/* Request helpers **********************************************************/
static struct usbdev_req_s *cdcacm_allocreq(FAR struct usbdev_ep_s *ep,
uint16_t len);
static void cdcacm_freereq(FAR struct usbdev_ep_s *ep,
FAR struct usbdev_req_s *req);
/* Flow Control ************************************************************/
/* Flow Control *************************************************************/
#ifdef CONFIG_CDCACM_IFLOWCONTROL
static int cdcacm_serialstate(FAR struct cdcacm_dev_s *priv);
#endif
/* Configuration ***********************************************************/
/* Configuration ************************************************************/
static void cdcacm_resetconfig(FAR struct cdcacm_dev_s *priv);
static int cdcacm_epconfigure(FAR struct usbdev_ep_s *ep,
@ -200,7 +200,7 @@ static int cdcacm_epconfigure(FAR struct usbdev_ep_s *ep,
static int cdcacm_setconfig(FAR struct cdcacm_dev_s *priv,
uint8_t config);
/* Completion event handlers ***********************************************/
/* Completion event handlers ************************************************/
static void cdcacm_ep0incomplete(FAR struct usbdev_ep_s *ep,
FAR struct usbdev_req_s *req);
@ -209,7 +209,7 @@ static void cdcacm_rdcomplete(FAR struct usbdev_ep_s *ep,
static void cdcacm_wrcomplete(FAR struct usbdev_ep_s *ep,
FAR struct usbdev_req_s *req);
/* USB class device ********************************************************/
/* USB class device *********************************************************/
static int cdcacm_bind(FAR struct usbdevclass_driver_s *driver,
FAR struct usbdev_s *dev);
@ -461,7 +461,7 @@ static int cdcacm_sndpacket(FAR struct cdcacm_dev_s *priv)
*
* Description:
* A normal completion event was received by the read completion handler
* at the interrupt level (with interrupts disabled). This function handles
* at the interrupt level (with interrupts disabled). This function handles
* the USB packet and provides the received data to the uart RX buffer.
*
* Assumptions:
@ -520,7 +520,7 @@ static int cdcacm_recvpacket(FAR struct cdcacm_dev_s *priv,
* and that the actual capacity of the RX buffer is (recv->size - 1).
*/
watermark = (CONFIG_SERIAL_IFLOWCONTROL_UPPER_WATERMARK * recv->size) / 100;
watermark = CONFIG_SERIAL_IFLOWCONTROL_UPPER_WATERMARK * recv->size / 100;
DEBUGASSERT(watermark > 0 && watermark < (recv->size - 1));
#endif
@ -558,8 +558,8 @@ static int cdcacm_recvpacket(FAR struct cdcacm_dev_s *priv,
if (nbuffered >= watermark)
{
/* Let the lower level driver know that the watermark level has been
* crossed. It will probably activate RX flow control.
/* Let the lower level driver know that the watermark level has
* been crossed. It will probably activate RX flow control.
*/
if (cdcuart_rxflowcontrol(&priv->serdev, nbuffered, true))
@ -1311,7 +1311,8 @@ static void cdcacm_wrcomplete(FAR struct usbdev_ep_s *ep,
static int cdcacm_bind(FAR struct usbdevclass_driver_s *driver,
FAR struct usbdev_s *dev)
{
FAR struct cdcacm_dev_s *priv = ((FAR struct cdcacm_driver_s *)driver)->dev;
FAR struct cdcacm_dev_s *priv =
((FAR struct cdcacm_driver_s *)driver)->dev;
FAR struct cdcacm_wrreq_s *wrcontainer;
FAR struct cdcacm_rdreq_s *rdcontainer;
irqstate_t flags;
@ -1458,7 +1459,9 @@ static int cdcacm_bind(FAR struct usbdevclass_driver_s *driver,
leave_critical_section(flags);
}
/* Report if we are selfpowered (unless we are part of a composite device) */
/* Report if we are selfpowered (unless we are part of a
* composite device)
*/
#ifndef CONFIG_CDCACM_COMPOSITE
#ifdef CONFIG_USBDEV_SELFPOWERED
@ -1876,7 +1879,8 @@ static int cdcacm_setup(FAR struct usbdevclass_driver_s *driver,
if (dataout && len <= SIZEOF_CDC_LINECODING) /* REVISIT */
{
memcpy(&priv->linecoding, dataout, SIZEOF_CDC_LINECODING);
memcpy(&priv->linecoding,
dataout, SIZEOF_CDC_LINECODING);
}
/* Respond with a zero length packet */
@ -2564,8 +2568,8 @@ static int cdcuart_ioctl(FAR struct file *filep, int cmd, unsigned long arg)
* and cdcuart_attach are called called)
* 2. With enable==false while transferring data from the RX buffer
* 2. With enable==true while waiting for more incoming data
* 3. With enable==false when the port is closed (just before cdcuart_detach
* and cdcuart_shutdown are called).
* 3. With enable==false when the port is closed (just before
* cdcuart_detach and cdcuart_shutdown are called).
*
* Assumptions:
* Called from the serial upper-half driver running on the thread of
@ -3100,8 +3104,8 @@ int cdcacm_initialize(int minor, FAR void **handle)
*
* Input Parameters:
* There is one parameter, it differs in typing depending upon whether the
* CDC/ACM driver is an internal part of a composite device, or a standalone
* USB driver:
* CDC/ACM driver is an internal part of a composite device, or a
* standalone USB driver:
*
* classdev - The class object returned by cdcacm_classobject()
* handle - The opaque handle representing the class object returned by
@ -3217,7 +3221,7 @@ void cdcacm_get_composite_devdesc(struct composite_devdesc_s *dev)
dev->nconfigs = CDCACM_NCONFIGS; /* Number of configurations supported */
dev->configid = CDCACM_CONFIGID; /* The only supported configuration ID */
/* Let the construction function calculate the size of the config descriptor */
/* Let the construction function calculate the size of config descriptor */
#ifdef CONFIG_USBDEV_DUALSPEED
dev->cfgdescsize = cdcacm_mkcfgdesc(NULL, NULL, USB_SPEED_UNKNOWN, 0);

91
drivers/usbdev/cdcecm.c
View file

@ -111,7 +111,9 @@
# define CONFIG_CDCECM_NINTERFACES 1
#endif
/* TX poll delay = 1 seconds. CLK_TCK is the number of clock ticks per second */
/* TX poll delay = 1 seconds.
* CLK_TCK is the number of clock ticks per second
*/
#define CDCECM_WDDELAY (1*CLK_TCK)
@ -119,7 +121,7 @@
#define CDCECM_TXTIMEOUT (60*CLK_TCK)
/* This is a helper pointer for accessing the contents of the Ethernet header */
/* This is a helper pointer for accessing the contents of Ethernet header */
#define BUF ((struct eth_hdr_s *)self->dev.d_buf)
@ -127,8 +129,8 @@
* Private Types
****************************************************************************/
/* The cdcecm_driver_s encapsulates all state information for a single hardware
* interface
/* The cdcecm_driver_s encapsulates all state information for a single
* hardware interface
*/
struct cdcecm_driver_s
@ -143,7 +145,8 @@ struct cdcecm_driver_s
FAR struct usbdev_ep_s *epbulkout; /* Bulk OUT endpoint */
uint8_t config; /* Selected configuration number */
uint8_t pktbuf[CONFIG_NET_ETH_PKTSIZE + CONFIG_NET_GUARDSIZE];
uint8_t pktbuf[CONFIG_NET_ETH_PKTSIZE +
CONFIG_NET_GUARDSIZE];
struct usbdev_req_s *rdreq; /* Single read request */
bool rxpending; /* Packet available in rdreq */
@ -323,8 +326,8 @@ static const struct usb_devdesc_s g_devdesc =
static int cdcecm_transmit(FAR struct cdcecm_driver_s *self)
{
/* Wait until the USB device request for Ethernet frame transmissions becomes
* available.
/* Wait until the USB device request for Ethernet frame transmissions
* becomes available.
*/
while (nxsem_wait(&self->wrreq_idle) != OK)
@ -352,7 +355,8 @@ static int cdcecm_transmit(FAR struct cdcecm_driver_s *self)
* devif_poll() may be called:
*
* 1. When the preceding TX packet send is complete,
* 2. When the preceding TX packet send times out and the interface is reset
* 2. When the preceding TX packet send times out and the interface is
* reset
* 3. During normal TX polling
*
* Input Parameters:
@ -510,7 +514,7 @@ static void cdcecm_receive(FAR struct cdcecm_driver_s *self)
self->dev.d_len = self->rdreq->xfrd;
#ifdef CONFIG_NET_PKT
/* When packet sockets are enabled, feed the frame into the packet tap */
/* When packet sockets are enabled, feed the frame into the tap */
pkt_input(&self->dev);
#endif
@ -561,7 +565,7 @@ static void cdcecm_receive(FAR struct cdcecm_driver_s *self)
NETDEV_RXARP(&self->dev);
/* If the above function invocation resulted in data that should be
* sent out on the network, the field d_len will set to a value > 0.
* sent out on the network, d_len field will set to a value > 0.
*/
if (self->dev.d_len > 0)
@ -646,9 +650,9 @@ static void cdcecm_interrupt_work(FAR void *arg)
leave_critical_section(flags);
}
/* Check if a packet transmission just completed. If so, call cdcecm_txdone.
* This may disable further Tx interrupts if there are no pending
* transmissions.
/* Check if a packet transmission just completed. If so, call
* cdcecm_txdone. This may disable further Tx interrupts if there
* are no pending transmissions.
*/
if (self->txdone)
@ -772,9 +776,9 @@ static int cdcecm_ifup(FAR struct net_driver_s *dev)
dev->d_ipv6addr[6], dev->d_ipv6addr[7]);
#endif
/* Initialize PHYs, the Ethernet interface, and setup up Ethernet interrupts */
/* Initialize PHYs, Ethernet interface, and setup up Ethernet interrupts */
/* Instantiate the MAC address from priv->dev.d_mac.ether.ether_addr_octet */
/* Instantiate MAC address from priv->dev.d_mac.ether.ether_addr_octet */
#ifdef CONFIG_NET_ICMPv6
/* Set up IPv6 multicast address filtering */
@ -929,7 +933,8 @@ static int cdcecm_txavail(FAR struct net_driver_s *dev)
****************************************************************************/
#if defined(CONFIG_NET_MCASTGROUP) || defined(CONFIG_NET_ICMPv6)
static int cdcecm_addmac(FAR struct net_driver_s *dev, FAR const uint8_t *mac)
static int cdcecm_addmac(FAR struct net_driver_s *dev,
FAR const uint8_t *mac)
{
FAR struct cdcecm_driver_s *priv =
(FAR struct cdcecm_driver_s *)dev->d_private;
@ -945,8 +950,8 @@ static int cdcecm_addmac(FAR struct net_driver_s *dev, FAR const uint8_t *mac)
* Name: cdcecm_rmmac
*
* Description:
* NuttX Callback: Remove the specified MAC address from the hardware multicast
* address filtering
* NuttX Callback: Remove the specified MAC address from the hardware
* multicast address filtering
*
* Input Parameters:
* dev - Reference to the NuttX driver state structure
@ -1123,7 +1128,8 @@ static void cdcecm_rdcomplete(FAR struct usbdev_ep_s *ep,
{
DEBUGASSERT(!self->rxpending);
self->rxpending = true;
work_queue(ETHWORK, &self->irqwork, cdcecm_interrupt_work, self, 0);
work_queue(ETHWORK, &self->irqwork,
cdcecm_interrupt_work, self, 0);
}
break;
@ -1227,13 +1233,13 @@ static void cdcecm_freereq(FAR struct usbdev_ep_s *ep,
}
}
/******************************************************************************
/****************************************************************************
* Name: cdcecm_resetconfig
*
* Description:
* Mark the device as not configured and disable all endpoints.
*
******************************************************************************/
****************************************************************************/
static void cdcecm_resetconfig(FAR struct cdcecm_driver_s *self)
{
@ -1259,7 +1265,7 @@ static void cdcecm_resetconfig(FAR struct cdcecm_driver_s *self)
}
}
/******************************************************************************
/****************************************************************************
* Name: cdcecm_setconfig
*
* Set the device configuration by allocating and configuring endpoints and
@ -1300,7 +1306,8 @@ static int cdcecm_setconfig(FAR struct cdcecm_driver_s *self, uint8_t config)
self->epint->priv = self;
bool is_high_speed = (self->usbdev.speed == USB_SPEED_HIGH);
cdcecm_mkepdesc(CDCECM_EP_BULKIN_IDX, &epdesc, &self->devinfo, is_high_speed);
cdcecm_mkepdesc(CDCECM_EP_BULKIN_IDX,
&epdesc, &self->devinfo, is_high_speed);
ret = EP_CONFIGURE(self->epbulkin, &epdesc, false);
if (ret < 0)
@ -1310,7 +1317,8 @@ static int cdcecm_setconfig(FAR struct cdcecm_driver_s *self, uint8_t config)
self->epbulkin->priv = self;
cdcecm_mkepdesc(CDCECM_EP_BULKOUT_IDX, &epdesc, &self->devinfo, is_high_speed);
cdcecm_mkepdesc(CDCECM_EP_BULKOUT_IDX,
&epdesc, &self->devinfo, is_high_speed);
ret = EP_CONFIGURE(self->epbulkout, &epdesc, true);
if (ret < 0)
@ -1355,7 +1363,7 @@ error:
return ret;
}
/******************************************************************************
/****************************************************************************
* Name: cdcecm_setinterface
*
****************************************************************************/
@ -1734,7 +1742,7 @@ static int16_t cdcecm_mkcfgdesc(FAR uint8_t *desc,
return len;
}
/*******************************************************************************
/****************************************************************************
* Name: cdcecm_getdescriptor
*
* Description:
@ -1752,10 +1760,10 @@ static int16_t cdcecm_mkcfgdesc(FAR uint8_t *desc,
* The size in bytes of the requested USB Descriptor or a negated errno in
* case of failure.
*
******************************************************************************/
****************************************************************************/
static int cdcecm_getdescriptor(FAR struct cdcecm_driver_s *self, uint8_t type,
uint8_t index, FAR void *desc)
static int cdcecm_getdescriptor(FAR struct cdcecm_driver_s *self,
uint8_t type, uint8_t index, FAR void *desc)
{
uinfo("type: 0x%02hhx, index: 0x%02hhx\n", type, index);
@ -1851,7 +1859,7 @@ static int cdcecm_bind(FAR struct usbdevclass_driver_s *driver,
/* Pre-allocate read requests. The buffer size is one full packet. */
self->rdreq = cdcecm_allocreq(self->epbulkout,
CONFIG_NET_ETH_PKTSIZE + CONFIG_NET_GUARDSIZE);
CONFIG_NET_ETH_PKTSIZE + CONFIG_NET_GUARDSIZE);
if (self->rdreq == NULL)
{
uerr("Out of memory\n");
@ -1864,7 +1872,7 @@ static int cdcecm_bind(FAR struct usbdevclass_driver_s *driver,
/* Pre-allocate a single write request. Buffer size is one full packet. */
self->wrreq = cdcecm_allocreq(self->epbulkin,
CONFIG_NET_ETH_PKTSIZE + CONFIG_NET_GUARDSIZE);
CONFIG_NET_ETH_PKTSIZE + CONFIG_NET_GUARDSIZE);
if (self->wrreq == NULL)
{
uerr("Out of memory\n");
@ -2035,12 +2043,12 @@ static int cdcecm_setup(FAR struct usbdevclass_driver_s *driver,
/* SetEthernetPacketFilter is the only required CDCECM subclass
* specific request, but it is still ok to always operate in
* promiscuous mode and rely on the host to do the filtering. This
* is especially true for our case: A simulated point-to-point
* connection.
* promiscuous mode and rely on the host to do the filtering.
* This is especially true for our case:
* A simulated point-to-point connection.
*/
uinfo("ECM_SET_PACKET_FILTER. wValue: 0x%04hx, wIndex: 0x%04hx\n",
uinfo("ECM_SET_PACKET_FILTER wValue: 0x%04hx, wIndex: 0x%04hx\n",
GETUINT16(ctrl->value), GETUINT16(ctrl->index));
ret = OK;
@ -2093,7 +2101,8 @@ static void cdcecm_disconnect(FAR struct usbdevclass_driver_s *driver,
*
****************************************************************************/
static int cdcecm_classobject(int minor, FAR struct usbdev_devinfo_s *devinfo,
static int cdcecm_classobject(int minor,
FAR struct usbdev_devinfo_s *devinfo,
FAR struct usbdevclass_driver_s **classdev)
{
FAR struct cdcecm_driver_s *self;
@ -2180,8 +2189,8 @@ static int cdcecm_classobject(int minor, FAR struct usbdev_devinfo_s *devinfo,
*
* Input Parameters:
* There is one parameter, it differs in typing depending upon whether the
* CDC/ECM driver is an internal part of a composite device, or a standalone
* USB driver:
* CDC/ECM driver is an internal part of a composite device, or a
* standalone USB driver:
*
* classdev - The class object returned by cdcacm_classobject()
* handle - The opaque handle representing the class object returned by
@ -2266,8 +2275,8 @@ void cdcecm_uninitialize(FAR void *handle)
* Name: cdcecm_initialize
*
* Description:
* Register CDC/ECM USB device interface. Register the corresponding network
* driver to NuttX and bring up the network.
* Register CDC/ECM USB device interface. Register the corresponding
* network driver to NuttX and bring up the network.
*
* Input Parameters:
* minor - Device minor number.
@ -2348,7 +2357,7 @@ void cdcecm_get_composite_devdesc(struct composite_devdesc_s *dev)
dev->nconfigs = CDCECM_NCONFIGS; /* Number of configurations supported */
dev->configid = CDCECM_CONFIGID; /* The only supported configuration ID */
/* Let the construction function calculate the size of the config descriptor */
/* Let the construction function calculate the size of config descriptor */
#ifdef CONFIG_USBDEV_DUALSPEED
dev->cfgdescsize = cdcecm_mkcfgdesc(NULL, NULL, USB_SPEED_UNKNOWN, 0);

99
drivers/usbdev/rndis.c
View file

@ -101,7 +101,9 @@
#define RNDIS_BUFFER_SIZE CONFIG_NET_ETH_PKTSIZE
#define RNDIS_BUFFER_COUNT 4
/* TX poll delay = 1 seconds. CLK_TCK is the number of clock ticks per second */
/* TX poll delay = 1 seconds.
* CLK_TCK is the number of clock ticks per second
*/
#define RNDIS_WDDELAY (1*CLK_TCK)
@ -394,8 +396,8 @@ static uint8_t g_rndis_default_mac_addr[6] =
};
/* These lists give dummy responses to be returned to PC. The values are
* chosen so that Windows is happy - other operating systems don't really care
* much.
* chosen so that Windows is happy - other operating systems don't really
* care much.
*/
static const uint32_t g_rndis_supported_oids[] =
@ -474,8 +476,8 @@ static const struct rndis_oid_value_s g_rndis_oid_values[] =
* When the reception of an Ethernet packet is complete, a worker to process
* the packet is scheduled and bulk OUT endpoint is set to NAK.
*
* The processing worker passes the buffer to the network. When the network is
* done processing the packet, the buffer might contain data to be sent.
* The processing worker passes the buffer to the network. When the network
* is done processing the packet, the buffer might contain data to be sent.
* If so, the corresponding write request is queued on the bulk IN endpoint.
* The NAK state on bulk OUT endpoint is cleared to allow new packets to
* arrive. If there's no data to send, the request is returned to the list of
@ -832,7 +834,8 @@ static uint16_t rndis_fillrequest(FAR struct rndis_dev_s *priv,
{
/* Send the required headers */
FAR struct rndis_packet_msg *msg = (FAR struct rndis_packet_msg *)req->buf;
FAR struct rndis_packet_msg *msg =
(FAR struct rndis_packet_msg *)req->buf;
memset(msg, 0, RNDIS_PACKET_HDR_SIZE);
msg->msgtype = RNDIS_PACKET_MSG;
@ -959,7 +962,8 @@ static void rndis_rxdispatch(FAR void *arg)
else
#endif
{
uerr("ERROR: Unsupported packet type dropped (%02x)\n", htons(hdr->type));
uerr("ERROR: Unsupported packet type dropped (%02x)\n",
htons(hdr->type));
NETDEV_RXDROPPED(&priv->netdev);
priv->netdev.d_len = 0;
}
@ -1035,8 +1039,8 @@ static int rndis_txpoll(FAR struct net_driver_s *dev)
}
}
/* If zero is returned, the polling will continue until all connections have
* been examined.
/* If zero is returned, the polling will continue until all connections
* have been examined.
*/
return ret;
@ -1204,7 +1208,7 @@ static int rndis_txavail(FAR struct net_driver_s *dev)
return OK;
}
/************************************************************************************
/****************************************************************************
* Name: rndis_recvpacket
*
* Description:
@ -1213,7 +1217,7 @@ static int rndis_txavail(FAR struct net_driver_s *dev)
* Assumptions:
* Called from the USB interrupt handler with interrupts disabled.
*
************************************************************************************/
****************************************************************************/
static inline int rndis_recvpacket(FAR struct rndis_dev_s *priv,
FAR uint8_t *reqbuf, uint16_t reqlen)
@ -1238,7 +1242,8 @@ static inline int rndis_recvpacket(FAR struct rndis_dev_s *priv,
{
/* The packet contains a RNDIS packet message header */
FAR struct rndis_packet_msg *msg = (FAR struct rndis_packet_msg *)reqbuf;
FAR struct rndis_packet_msg *msg =
(FAR struct rndis_packet_msg *)reqbuf;
if (msg->msgtype == RNDIS_PACKET_MSG)
{
priv->current_rx_received = reqlen;
@ -1247,16 +1252,17 @@ static inline int rndis_recvpacket(FAR struct rndis_dev_s *priv,
/* According to RNDIS-over-USB send, if the message length is a
* multiple of endpoint max packet size, the host must send an
* additional single-byte zero packet. Take that in account here.
* additional single-byte zero packet. Take that in account
* here.
*/
if ((priv->current_rx_msglen % priv->epbulkout->maxpacket) == 0)
if (!(priv->current_rx_msglen % priv->epbulkout->maxpacket))
{
priv->current_rx_msglen += 1;
}
/* Data offset is defined as an offset from the beginning of the
* offset field itself
/* Data offset is defined as an offset from the beginning of
* the offset field itself
*/
priv->current_rx_datagram_offset = msg->dataoffset + 8;
@ -1279,19 +1285,22 @@ static inline int rndis_recvpacket(FAR struct rndis_dev_s *priv,
priv->current_rx_received <= priv->current_rx_datagram_size +
priv->current_rx_datagram_offset)
{
size_t index = priv->current_rx_received - priv->current_rx_datagram_offset;
size_t copysize = min(reqlen, priv->current_rx_datagram_size - index);
size_t index = priv->current_rx_received -
priv->current_rx_datagram_offset;
size_t copysize = min(reqlen,
priv->current_rx_datagram_size - index);
/* Check if the received packet exceeds request buffer */
if ((index + copysize) <= CONFIG_NET_ETH_PKTSIZE)
{
memcpy(&priv->rx_req->req->buf[RNDIS_PACKET_HDR_SIZE + index], reqbuf,
copysize);
memcpy(&priv->rx_req->req->buf[RNDIS_PACKET_HDR_SIZE + index],
reqbuf, copysize);
}
else
{
uerr("The packet exceeds request buffer (reqlen=%d) \n", reqlen);
uerr("The packet exceeds request buffer (reqlen=%d) \n",
reqlen);
}
}
priv->current_rx_received += reqlen;
@ -1342,8 +1351,9 @@ static inline int rndis_recvpacket(FAR struct rndis_dev_s *priv,
*
****************************************************************************/
static bool rndis_prepare_response(FAR struct rndis_dev_s *priv, size_t size,
FAR struct rndis_command_header *request_hdr)
static bool
rndis_prepare_response(FAR struct rndis_dev_s *priv, size_t size,
FAR struct rndis_command_header *request_hdr)
{
FAR struct rndis_response_header *hdr =
(FAR struct rndis_response_header *)priv->ctrlreq->buf;
@ -1403,7 +1413,8 @@ static int rndis_send_encapsulated_response(FAR struct rndis_dev_s *priv)
****************************************************************************/
static int rndis_handle_control_message(FAR struct rndis_dev_s *priv,
FAR uint8_t *dataout, uint16_t outlen)
FAR uint8_t *dataout,
uint16_t outlen)
{
FAR struct rndis_command_header *cmd_hdr =
(FAR struct rndis_command_header *)dataout;
@ -1453,7 +1464,8 @@ static int rndis_handle_control_message(FAR struct rndis_dev_s *priv,
resp->hdr.status = RNDIS_STATUS_NOT_SUPPORTED;
for (i = 0;
i < sizeof(g_rndis_oid_values) / sizeof(g_rndis_oid_values[0]);
i < sizeof(g_rndis_oid_values) /
sizeof(g_rndis_oid_values[0]);
i++)
{
bool match = (g_rndis_oid_values[i].objid == req->objid);
@ -1642,7 +1654,8 @@ static void rndis_rdcomplete(FAR struct usbdev_ep_s *ep,
return;
default: /* Some other error occurred */
usbtrace(TRACE_CLSERROR(USBSER_TRACEERR_RDUNEXPECTED), (uint16_t)-req->result);
usbtrace(TRACE_CLSERROR(USBSER_TRACEERR_RDUNEXPECTED),
(uint16_t)-req->result);
break;
};
@ -2074,8 +2087,9 @@ static int usbclass_bind(FAR struct usbdevclass_driver_s *driver,
/* Pre-allocate the IN interrupt endpoint */
priv->epintin = DEV_ALLOCEP(dev, USB_EPIN(priv->devinfo.epno[RNDIS_EP_INTIN_IDX]),
true, USB_EP_ATTR_XFER_INT);
priv->epintin = DEV_ALLOCEP(dev,
USB_EPIN(priv->devinfo.epno[RNDIS_EP_INTIN_IDX]),
true, USB_EP_ATTR_XFER_INT);
if (!priv->epintin)
{
usbtrace(TRACE_CLSERROR(USBSER_TRACEERR_EPINTINALLOCFAIL), 0);
@ -2098,8 +2112,9 @@ static int usbclass_bind(FAR struct usbdevclass_driver_s *driver,
/* Pre-allocate the IN bulk endpoint */
priv->epbulkin = DEV_ALLOCEP(dev, USB_EPIN(priv->devinfo.epno[RNDIS_EP_BULKIN_IDX]),
true, USB_EP_ATTR_XFER_BULK);
priv->epbulkin = DEV_ALLOCEP(dev,
USB_EPIN(priv->devinfo.epno[RNDIS_EP_BULKIN_IDX]),
true, USB_EP_ATTR_XFER_BULK);
if (!priv->epbulkin)
{
usbtrace(TRACE_CLSERROR(USBSER_TRACEERR_EPBULKINALLOCFAIL), 0);
@ -2376,8 +2391,9 @@ static int usbclass_setup(FAR struct usbdevclass_driver_s *driver,
{
case USB_REQ_GETDESCRIPTOR:
{
/* The value field specifies the descriptor type in the MS byte and the
* descriptor index in the LS byte (order is little endian)
/* The value field specifies the descriptor type in the MS byte
* and the descriptor index in the LS byte (order is little
* endian)
*/
switch (ctrl->value[1])
@ -2402,13 +2418,14 @@ static int usbclass_setup(FAR struct usbdevclass_driver_s *driver,
/* index == language code. */
ret = usbclass_mkstrdesc(ctrl->value[0],
(FAR struct usb_strdesc_s *)ctrlreq->buf);
(FAR struct usb_strdesc_s *)ctrlreq->buf);
}
break;
default:
{
usbtrace(TRACE_CLSERROR(USBSER_TRACEERR_GETUNKNOWNDESC), value);
usbtrace(TRACE_CLSERROR(USBSER_TRACEERR_GETUNKNOWNDESC),
value);
}
break;
}
@ -2435,7 +2452,8 @@ static int usbclass_setup(FAR struct usbdevclass_driver_s *driver,
break;
default:
usbtrace(TRACE_CLSERROR(USBSER_TRACEERR_UNSUPPORTEDSTDREQ), ctrl->req);
usbtrace(TRACE_CLSERROR(USBSER_TRACEERR_UNSUPPORTEDSTDREQ),
ctrl->req);
break;
}
}
@ -2445,7 +2463,8 @@ static int usbclass_setup(FAR struct usbdevclass_driver_s *driver,
case USB_REQ_TYPE_CLASS:
{
if ((ctrl->type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_INTERFACE)
if ((ctrl->type & USB_REQ_RECIPIENT_MASK) ==
USB_REQ_RECIPIENT_INTERFACE)
{
if (ctrl->req == RNDIS_SEND_ENCAPSULATED_COMMAND)
{
@ -2657,7 +2676,8 @@ static int usbclass_setconfig(FAR struct rndis_dev_s *priv, uint8_t config)
/* Configure the IN bulk endpoint */
usbclass_copy_epdesc(RNDIS_EP_BULKIN_IDX, &epdesc, &priv->devinfo, hispeed);
usbclass_copy_epdesc(RNDIS_EP_BULKIN_IDX,
&epdesc, &priv->devinfo, hispeed);
ret = EP_CONFIGURE(priv->epbulkin, &epdesc, false);
if (ret < 0)
@ -2670,7 +2690,8 @@ static int usbclass_setconfig(FAR struct rndis_dev_s *priv, uint8_t config)
/* Configure the OUT bulk endpoint */
usbclass_copy_epdesc(RNDIS_EP_BULKOUT_IDX, &epdesc, &priv->devinfo, hispeed);
usbclass_copy_epdesc(RNDIS_EP_BULKOUT_IDX,
&epdesc, &priv->devinfo, hispeed);
ret = EP_CONFIGURE(priv->epbulkout, &epdesc, true);
if (ret < 0)
@ -2728,7 +2749,7 @@ static int usbclass_classobject(int minor,
/* Allocate the structures needed */
alloc = (FAR struct rndis_alloc_s *)kmm_zalloc(sizeof(struct rndis_alloc_s));
alloc = kmm_zalloc(sizeof(struct rndis_alloc_s));
if (!alloc)
{
usbtrace(TRACE_CLSERROR(USBSER_TRACEERR_ALLOCDEVSTRUCT), 0);

39
drivers/wireless/ieee80211/bcm43xxx/bcmf_netdev.c
View file

@ -90,15 +90,17 @@
#define BCMFWORK LPWORK
/* CONFIG_IEEE80211_BROADCOM_NINTERFACES determines the number of physical interfaces
* that will be supported.
/* CONFIG_IEEE80211_BROADCOM_NINTERFACES determines the number of physical
* interfaces that will be supported.
*/
#ifndef CONFIG_IEEE80211_BROADCOM_NINTERFACES
# define CONFIG_IEEE80211_BROADCOM_NINTERFACES 1
#endif
/* TX poll delay = 1 seconds. CLK_TCK is the number of clock ticks per second */
/* TX poll delay = 1 seconds.
* CLK_TCK is the number of clock ticks per second
*/
#define BCMF_WDDELAY (1*CLK_TCK)
@ -106,7 +108,7 @@
#define BCMF_TXTIMEOUT (60*CLK_TCK)
/* This is a helper pointer for accessing the contents of the Ethernet header */
/* This is a helper pointer for accessing the contents of Ethernet header */
#define BUF ((struct eth_hdr_s *)priv->bc_dev.d_buf)
@ -166,7 +168,8 @@ int bcmf_netdev_alloc_tx_frame(FAR struct bcmf_dev_s *priv)
/* Allocate frame for TX */
priv->cur_tx_frame = bcmf_bdc_allocate_frame(priv, MAX_NETDEV_PKTSIZE, true);
priv->cur_tx_frame = bcmf_bdc_allocate_frame(priv,
MAX_NETDEV_PKTSIZE, true);
if (!priv->cur_tx_frame)
{
wlerr("ERROR: Cannot allocate TX frame\n");
@ -259,12 +262,12 @@ static void bcmf_receive(FAR struct bcmf_dev_s *priv)
}
priv->bc_dev.d_buf = frame->data;
priv->bc_dev.d_len = frame->len - (uint32_t)(frame->data - frame->base);
priv->bc_dev.d_len = frame->len - (frame->data - frame->base);
wlinfo("Got frame %p %d\n", frame, priv->bc_dev.d_len);
#ifdef CONFIG_NET_PKT
/* When packet sockets are enabled, feed the frame into the packet tap */
/* When packet sockets are enabled, feed the frame into the tap */
pkt_input(&priv->bc_dev);
#endif
@ -303,7 +306,7 @@ static void bcmf_receive(FAR struct bcmf_dev_s *priv)
ipv4_input(&priv->bc_dev);
/* If the above function invocation resulted in data that should be
* sent out on the network, the field d_len will set to a value > 0.
* sent out on the network, d_len field will set to a value > 0.
*/
if (priv->bc_dev.d_len > 0)
@ -347,7 +350,7 @@ static void bcmf_receive(FAR struct bcmf_dev_s *priv)
ipv6_input(&priv->bc_dev);
/* If the above function invocation resulted in data that should be
* sent out on the network, the field d_len will set to a value > 0.
* sent out on the network, d_len field will set to a value > 0.
*/
if (priv->bc_dev.d_len > 0)
@ -387,7 +390,7 @@ static void bcmf_receive(FAR struct bcmf_dev_s *priv)
NETDEV_RXARP(&priv->bc_dev);
/* If the above function invocation resulted in data that should be
* sent out on the network, the field d_len will set to a value > 0.
* sent out on the network, d_len field will set to a value > 0.
*/
if (priv->bc_dev.d_len > 0)
@ -479,8 +482,8 @@ static int bcmf_txpoll(FAR struct net_driver_s *dev)
bcmf_transmit(priv, priv->cur_tx_frame);
/* TODO: Check if there is room in the device to hold another packet.
* If not, return a non-zero value to terminate the poll.
/* TODO: Check if there is room in the device to hold another
* packet. If not, return a non-zero value to terminate the poll.
*/
priv->cur_tx_frame = NULL;
@ -488,8 +491,8 @@ static int bcmf_txpoll(FAR struct net_driver_s *dev)
}
}
/* If zero is returned, the polling will continue until all connections have
* been examined.
/* If zero is returned, the polling will continue until all connections
* have been examined.
*/
return 0;
@ -688,7 +691,7 @@ static int bcmf_ifup(FAR struct net_driver_s *dev)
dev->d_ipv6addr[6], dev->d_ipv6addr[7]);
#endif
/* Instantiate the MAC address from priv->bc_dev.d_mac.ether.ether_addr_octet */
/* Instantiate MAC address from priv->bc_dev.d_mac.ether.ether_addr_octet */
#ifdef CONFIG_NET_ICMPv6
/* Set up IPv6 multicast address filtering */
@ -782,7 +785,7 @@ static void bcmf_txavail_work(FAR void *arg)
if (priv->bc_bifup)
{
/* Check if there is room in the hardware to hold another outgoing packet. */
/* Check if there is room in the hardware to hold another packet. */
if (bcmf_netdev_alloc_tx_frame(priv))
{
@ -871,8 +874,8 @@ static int bcmf_addmac(FAR struct net_driver_s *dev, FAR const uint8_t *mac)
* Name: bcmf_rmmac
*
* Description:
* NuttX Callback: Remove the specified MAC address from the hardware multicast
* address filtering
* NuttX Callback: Remove the specified MAC address from the hardware
* multicast address filtering
*
* Input Parameters:
* dev - Reference to the NuttX driver state structure

79
drivers/wireless/ieee802154/xbee/xbee_mac.c
View file

@ -89,10 +89,10 @@ static void xbee_assocworker(FAR void *arg);
* Name: xbee_assoctimer
*
* Description:
* This function is used to schedule * an associatioin indication poll. When
* association first gets triggered, a watchdog timer is started. This function
* is called when it expires. The watchdog timer is scheduled again until
* the association is either successful or fails.
* This function is used to schedule * an associatioin indication poll.
* When association first gets triggered, a watchdog timer is started. This
* function is called when it expires. The watchdog timer is scheduled
* again until the association is either successful or fails.
*
* Input Parameters:
* argc - The number of available arguments
@ -123,7 +123,8 @@ static void xbee_assoctimer(int argc, wdparm_t arg, ...)
* occur until we restart the poll timeout watchdog.
*/
ret = work_queue(HPWORK, &priv->assocwork, xbee_assocworker, (FAR void *)priv, 0);
ret = work_queue(HPWORK, &priv->assocwork,
xbee_assocworker, (FAR void *)priv, 0);
UNUSED(ret);
DEBUGASSERT(ret == OK);
}
@ -132,9 +133,9 @@ static void xbee_assoctimer(int argc, wdparm_t arg, ...)
* Name: xbee_assocworker
*
* Description:
* Poll the device for the assosciation status. This function is indirectly
* scheduled rom xbee_req_associate in order to poll the device for association
* progress.
* Poll the device for the assosciation status. This function is indirectly
* scheduled rom xbee_req_associate in order to poll the device for
* association progress.
*
* Input Parameters:
* arg - The reference to the driver structure (cast to void*)
@ -163,11 +164,11 @@ static void xbee_assocworker(FAR void *arg)
* Name: xbee_reqdata_timeout
*
* Description:
* This function runs when a send request has timed out waiting for a response
* from the XBee module. This really should never happen, but if it does,
* handle it gracefully by retrying the query. Although I still think this
* should not happen, it does seem to happen. The XBee seemingly randomly drops
* the request and never sends a response.
* This function runs when a send request has timed out waiting for a
* response from the XBee module. This really should never happen, but if
* it does, handle it gracefully by retrying the query. Although I still
* think this should not happen, it does seem to happen. The XBee seemingly
* randomly drops the request and never sends a response.
*
* Parameters:
* argc - The number of available arguments
@ -263,12 +264,13 @@ int xbee_bind(XBEEHANDLE xbee, FAR struct xbee_maccb_s *cb)
* Description:
* Calculate the MAC header length given the frame meta-data. For the XBee,
* we use the header to store the entire API frame for the TX request. The
* size we need is fixed based on the address mode we are using as it changes
* which API frame we need to issue.
* size we need is fixed based on the address mode we are using as it
* changes which API frame we need to issue.
*
****************************************************************************/
int xbee_get_mhrlen(XBEEHANDLE xbee, FAR const struct ieee802154_frame_meta_s *meta)
int xbee_get_mhrlen(XBEEHANDLE xbee,
FAR const struct ieee802154_frame_meta_s *meta)
{
int ret = 9; /* Smallest possible header size */
@ -388,15 +390,17 @@ int xbee_req_data(XBEEHANDLE xbee,
xbee_send_apiframe(priv, &frame->io_data[frame->io_offset],
(frame->io_len - frame->io_offset));
/* Wait for a transmit status to be received. Does not necessarily mean success */
/* Wait for a transmit status to be received. Does not necessarily mean
* success
*/
while (nxsem_wait(&priv->txdone_sem) < 0);
/* If the transmit timeout has occurred, and there are no IOBs available,
* we may be blocking the context needed to free the IOBs. We cannot receive
* the Tx status because it requires an IOB. Therefore, if we have hit the
* timeout, and there are no IOBs, let's move on assuming the transmit was
* a success
/* If the transmit timeout has occurred, and there are no IOBs
* available, we may be blocking the context needed to free the IOBs.
* We cannot receive the Tx status because it requires an IOB.
* Therefore, if we have hit the timeout, and there are no IOBs, let's
* move on assuming the transmit was a success
*/
if (!priv->txdone && iob_navail(false) <= 0)
@ -430,8 +434,8 @@ int xbee_req_data(XBEEHANDLE xbee,
*
* NOTE: The standard specifies that the attribute value should be returned
* via the asynchronous MLME-GET.confirm primitive. However, in our
* implementation, we synchronously return the value immediately.Therefore, we
* merge the functionality of the MLME-GET.request and MLME-GET.confirm
* implementation, we synchronously return the value immediately.Therefore,
* we merge the functionality of the MLME-GET.request and MLME-GET.confirm
* primitives together.
*
****************************************************************************/
@ -494,8 +498,9 @@ int xbee_req_get(XBEEHANDLE xbee, enum ieee802154_attr_e attr,
case IEEE802154_ATTR_PHY_TX_POWER:
{
/* TODO: Convert pwrlvl and boost mode settings to int32_t dbm. This
* depends on whether device is XBee or XBee Pro to do this look-up.
/* TODO: Convert pwrlvl and boost mode settings to int32_t dbm.
* This depends on whether device is XBee or XBee Pro to do this
* look-up.
*/
xbee_query_powerlevel(priv);
@ -535,10 +540,10 @@ int xbee_req_get(XBEEHANDLE xbee, enum ieee802154_attr_e attr,
* indicated MAC PIB attribute.
*
* NOTE: The standard specifies that confirmation should be indicated via
* the asynchronous MLME-SET.confirm primitive. However, in our implementation
* we synchronously return the status from the request. Therefore, we do merge
* the functionality of the MLME-SET.request and MLME-SET.confirm primitives
* together.
* the asynchronous MLME-SET.confirm primitive. However, in our
* implementation we synchronously return the status from the request.
* Therefore, we do merge the functionality of the MLME-SET.request and
* MLME-SET.confirm primitives together.
*
****************************************************************************/
@ -578,7 +583,8 @@ int xbee_req_set(XBEEHANDLE xbee, enum ieee802154_attr_e attr,
{
if (attrval->mac.assocpermit)
{
xbee_set_coordassocflags(priv, XBEE_COORDASSOCFLAGS_ALLOWASSOC);
xbee_set_coordassocflags(priv,
XBEE_COORDASSOCFLAGS_ALLOWASSOC);
}
else
{
@ -589,8 +595,8 @@ int xbee_req_set(XBEEHANDLE xbee, enum ieee802154_attr_e attr,
case IEEE802154_ATTR_PHY_TX_POWER:
{
/* TODO: Convert int32_t dbm input to closest PM/PL settings. Need to
* know whether device is XBee or XBee Pro to do this look-up.
/* TODO: Convert int32_t dbm input to closest PM/PL settings. Need
* to know whether device is XBee or XBee Pro to do this look-up.
*/
xbee_set_powerlevel(priv, attrval->phy.txpwr);
@ -676,7 +682,8 @@ int xbee_req_start(XBEEHANDLE xbee, FAR struct ieee802154_start_req_s *req)
*
****************************************************************************/
int xbee_req_associate(XBEEHANDLE xbee, FAR struct ieee802154_assoc_req_s *req)
int xbee_req_associate(XBEEHANDLE xbee,
FAR struct ieee802154_assoc_req_s *req)
{
FAR struct xbee_priv_s *priv = (FAR struct xbee_priv_s *)xbee;
@ -710,8 +717,8 @@ int xbee_req_associate(XBEEHANDLE xbee, FAR struct ieee802154_assoc_req_s *req)
* that the MLME performs a reset operation.
*
* Input Parameters:
* xbee - Handle to the XBee instance
* resetattr - Whether or not to reset the MAC PIB attributes to defaults
* xbee - Handle to the XBee instance
* resetattr - Whether or not to reset the MAC PIB attributes to defaults
*
****************************************************************************/

8
drivers/wireless/spirit/drivers/spirit_netdev.c
View file

@ -215,7 +215,9 @@
#define SPIRIT_RXFIFO_ALMOSTFULL (3 * SPIRIT_MAX_FIFO_LEN / 4)
#define SPIRIT_TXFIFO_ALMOSTEMPTY (1 * SPIRIT_MAX_FIFO_LEN / 4)
/* TX poll delay = 1 seconds. CLK_TCK is the number of clock ticks per second */
/* TX poll delay = 1 seconds.
* CLK_TCK is the number of clock ticks per second
*/
#define SPIRIT_WDDELAY (1*CLK_TCK)
@ -580,7 +582,7 @@ static void spirit_set_ipaddress(FAR struct net_driver_s *dev)
{
FAR struct netdev_varaddr_s *addr;
/* Get a convenient pointer to the PktRadio variable length address struct */
/* Get a convenient pointer to the variable length address struct */
addr = (FAR struct netdev_varaddr_s *)&dev->d_mac.radio;
@ -2861,7 +2863,7 @@ int spirit_netdev_initialize(FAR struct spi_dev_s *spi,
priv->radio.r_dev.d_buf = g_iobuffer.rb_buf;
#endif
/* Register the device with the OS so that socket IOCTLs can be performed. */
/* Register the device with the OS so that IOCTLs can be performed. */
ret = netdev_register(dev, NET_LL_PKTRADIO);
if (ret < 0)

12
include/nuttx/net/gmii.h
View file

@ -79,7 +79,7 @@
#define GMII_KSZ90x1_LINKMD 18 /* LinkMD(c) cable diagnostic */
#define GMII_KSZ90x1_PMAPCS 19 /* Digital PMA/PCS status */
#define GMII_KSZ90x1_RXERR 21 /* RXER counter */
#define GMII_KSZ90x1_ICS 27 /* Interrupt control/status */
#define GMII_KSZ90X1_ICS 27 /* Interrupt control/status */
#define GMII_KSZ90x1_DBGCTRL1 28 /* Digital debug control 1 */
#define GMII_KSZ90x1_PHYCTRL 31 /* PHY control */
@ -89,8 +89,8 @@
#define GMII_KSZ90x1_SSR 257 /* Strap status */
#define GMII_KSZ90x1_OMSOR 258 /* Operation mode strap override */
#define GMII_KSZ90x1_OMSSR 259 /* Operation mode strap status */
#define GMII_KSZ90x1_RCCPSR 260 /* RGMII clock and control pad skew */
#define GMII_KSZ90x1_RRDPSR 261 /* RGMII RX data pad skew */
#define GMII_KSZ90X1_RCCPSR 260 /* RGMII clock and control pad skew */
#define GMII_KSZ90X1_RRDPSR 261 /* RGMII RX data pad skew */
#define GMII_KSZ90x1_ATR 263 /* Analog test register */
/* MII register bit settings *****************************************************************/
@ -233,6 +233,7 @@
#define GMII_ESTATUS_1000BASEXFULL MII_ESTATUS_1000BASEXFULL
/* 1000BASE-T Control Register */
/* Bits 0-7: Reserved */
#define GMII_1000BTCR_1000BASETHALF (1 << 8) /* Bit 8: 1000Base-T half duplex able */
#define GMII_1000BTCR_1000BASETFULL (1 << 9) /* Bit 9: 1000Base-T full duplex able */
@ -267,6 +268,7 @@
#define GMII_ERCR_WRITE (1 << 15) /* Bit 15: 1=Write extended register */
/* Extend Register - Data Write Register (16-bit data value) */
/* Extend Register - Data Read Register (16-bit data value) */
/* Micrel KSZ9021/31 Vendor Specific Register Bit Definitions ********************************/
@ -278,9 +280,9 @@
#define GMII_KSZ90x1_INT_PREN (1 << 13) /* Page received interrupt enable */
#define GMII_KSZ90x1_INT_PDFEN (1 << 12) /* Parallel detect fault interrupt enable */
#define GMII_KSZ90x1_INT_LPAEN (1 << 11) /* Link partner acknowledge interrupt enable */
#define GMII_KSZ90x1_INT_LDEN (1 << 10) /* Link down fault interrupt enable */
#define GMII_KSZ90X1_INT_LDEN (1 << 10) /* Link down fault interrupt enable */
#define GMII_KSZ90x1_INT_RFEN (1 << 9) /* Remote fault interrupt enable */
#define GMII_KSZ90x1_INT_LUEN (1 << 8) /* Link up interrupt enable */
#define GMII_KSZ90X1_INT_LUEN (1 << 8) /* Link up interrupt enable */
#define GMII_KSZ90x1_INT_J (1 << 7) /* Jabber interrupt */
#define GMII_KSZ90x1_INT_RE (1 << 6) /* Receive error interrupt */

8
include/nuttx/net/mld.h
View file

@ -222,8 +222,8 @@
* Address Compatibility Mode for a specific multicast
* address. When an MLDv1 report is received for that
* multicast address, routers set their Older Version
* Host Present Timer to the Older Version Host Present
* Timeout.
* Host Present Timer to the Older Version Host
* Present Timeout.
*/
#define MLD_ROBUSTNESS (2)
@ -247,7 +247,8 @@
****************************************************************************/
/* Multicast Listener Queries are sent by multicast routers in Querier State
* to query the multicast listening state of neighboring interfaces (RFC 3810).
* to query the multicast listening state of neighboring interfaces
* (RFC 3810).
*
* There are three variants of the Query message:
*
@ -315,6 +316,7 @@ struct mld_mcast_listen_report_v1_s
};
/* Version 2 Multicast Listener Report (RFC 3810). */
/* This is the form of the address record used in the listener report */
struct mld_mcast_addrec_v2_s

8
net/devif/devif_loopback.c
View file

@ -88,9 +88,9 @@ static bool is_loopback(FAR struct net_driver_s *dev)
*
* Description:
* This function should be called before sending out a packet. The function
* checks the destination address of the packet to see whether the target of
* packet is ourself and then consume the packet directly by calling input
* process functions.
* checks the destination address of the packet to see whether the target
* of packet is ourself and then consume the packet directly by calling
* input process functions.
*
* Returned Value:
* Zero is returned if the packet don't loop back to ourself, otherwise
@ -115,7 +115,7 @@ int devif_loopback(FAR struct net_driver_s *dev)
NETDEV_RXPACKETS(dev);
#ifdef CONFIG_NET_PKT
/* When packet sockets are enabled, feed the frame into the packet tap */
/* When packet sockets are enabled, feed the frame into the tap */
pkt_input(dev);
#endif

46
net/igmp/igmp_input.c
View file

@ -19,21 +19,21 @@
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of CITEL Technologies Ltd nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
* 3. Neither the name of CITEL Technologies Ltd nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY CITEL TECHNOLOGIES AND CONTRIBUTORS ``AS IS''
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL CITEL TECHNOLOGIES OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
* ARE DISCLAIMED. IN NO EVENT SHALL CITEL TECHNOLOGIES OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
@ -121,7 +121,8 @@ void igmp_input(struct net_driver_s *dev)
uint16_t iphdrlen;
unsigned int ticks;
ninfo("IGMP message: %04x%04x\n", ipv4->destipaddr[1], ipv4->destipaddr[0]);
ninfo("IGMP message: %04x%04x\n",
ipv4->destipaddr[1], ipv4->destipaddr[0]);
/* Get the IP header length (accounting for possible options). */
@ -166,10 +167,11 @@ void igmp_input(struct net_driver_s *dev)
{
case IGMP_MEMBERSHIP_QUERY:
/* RFC 2236, 2.2. ax Response Time
* "The Max Response Time field is meaningful only in Membership Query
* messages, and specifies the maximum allowed time before sending a
* responding report in units of 1/10 second. In all other messages,
* it is set to zero by the sender and ignored by receivers.
* "The Max Response Time field is meaningful only in Membership
* Query messages, and specifies the maximum allowed time before
* sending a responding report in units of 1/10 second. In all
* other messages, it is set to zero by the sender and ignored by
* receivers.
*/
/* Check if the query was sent to all systems */
@ -210,13 +212,13 @@ void igmp_input(struct net_driver_s *dev)
IGMP_STATINCR(g_netstats.igmp.query_received);
for (member = (FAR struct igmp_group_s *)dev->d_igmp_grplist.head;
member;
member = member->next)
member = (FAR struct igmp_group_s *)dev->d_igmp_grplist.head;
for (; member; member = member->next)
{
/* Skip over the all systems group entry */
if (!net_ipv4addr_cmp(member->grpaddr, g_ipv4_allsystems))
if (!net_ipv4addr_cmp(member->grpaddr,
g_ipv4_allsystems))
{
ticks = net_dsec2tick((int)igmp->maxresp);
if (IS_IDLEMEMBER(member->flags) ||
@ -232,8 +234,8 @@ void igmp_input(struct net_driver_s *dev)
{
ninfo("Group-specific multicast query\n");
/* We first need to re-lookup the group since we used dest last time.
* Use the incoming IPaddress!
/* We first need to re-lookup the group since we used dest
* last time. Use the incoming IPaddress!
*/
IGMP_STATINCR(g_netstats.igmp.ucast_query);

32
net/igmp/igmp_leave.c
View file

@ -19,21 +19,21 @@
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of CITEL Technologies Ltd nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
* 3. Neither the name of CITEL Technologies Ltd nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY CITEL TECHNOLOGIES AND CONTRIBUTORS ``AS IS''
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL CITEL TECHNOLOGIES OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
* ARE DISCLAIMED. IN NO EVENT SHALL CITEL TECHNOLOGIES OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
@ -138,10 +138,10 @@ int igmp_leavegroup(struct net_driver_s *dev,
ninfo("Leaving group: %p\n", group);
if (group)
{
/* Cancel the timer and discard any queued Membership Reports. Canceling
* the timer will prevent any new Membership Reports from being sent;
* clearing the flags will discard any pending Membership Reports that
* could interfere with the Leave Group.
/* Cancel the timer and discard any queued Membership Reports.
* Canceling the timer will prevent any new Membership Reports from
* being sent; clearing the flags will discard any pending Membership
* Reports that could interfere with the Leave Group.
*/
wd_cancel(group->wdog);
@ -168,7 +168,7 @@ int igmp_leavegroup(struct net_driver_s *dev,
igmp_grpfree(dev, group);
/* And remove the group address from the ethernet drivers MAC filter set */
/* And remove the group address from the drivers MAC filter set */
igmp_removemcastmac(dev, (FAR in_addr_t *)&grpaddr->s_addr);
return OK;

20
net/mld/mld_initialize.c
View file

@ -14,21 +14,21 @@
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of CITEL Technologies Ltd nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
* 3. Neither the name of CITEL Technologies Ltd nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY CITEL TECHNOLOGIES AND CONTRIBUTORS ``AS IS''
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL CITEL TECHNOLOGIES OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* ARE DISCLAIMED. IN NO EVENT SHALL CITEL TECHNOLOGIES OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
* SUBSTITUTE GOODS HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/

22
net/mld/mld_leave.c
View file

@ -13,21 +13,21 @@
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of CITEL Technologies Ltd nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
* 3. Neither the name of CITEL Technologies Ltd nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY CITEL TECHNOLOGIES AND CONTRIBUTORS ``AS IS''
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL CITEL TECHNOLOGIES OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
* ARE DISCLAIMED. IN NO EVENT SHALL CITEL TECHNOLOGIES OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/

25
net/mld/mld_timer.c
View file

@ -13,21 +13,21 @@
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of CITEL Technologies Ltd nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
* 3. Neither the name of CITEL Technologies Ltd nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY CITEL TECHNOLOGIES AND CONTRIBUTORS ``AS IS''
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL CITEL TECHNOLOGIES OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
* ARE DISCLAIMED. IN NO EVENT SHALL CITEL TECHNOLOGIES OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
@ -491,7 +491,8 @@ void mld_start_polltimer(FAR struct mld_group_s *group, clock_t ticks)
mldinfo("ticks: %lu\n", (unsigned long)ticks);
ret = wd_start(group->polldog, ticks, mld_polldog_timout, 1, (wdparm_t)group);
ret = wd_start(group->polldog, ticks,
mld_polldog_timout, 1, (wdparm_t)group);
DEBUGASSERT(ret == OK);
UNUSED(ret);

64
net/sixlowpan/sixlowpan_input.c
View file

@ -265,8 +265,8 @@ static uint16_t sixlowpan_uncompress_ipv6proto(FAR uint8_t *fptr,
* INPUT_PARTIAL Frame processed successful, packet incomplete
* INPUT_COMPLETE Frame processed successful, packet complete
*
* Otherwise a negated errno value is returned to indicate the nature of the
* failure.
* Otherwise a negated errno value is returned to indicate the nature of
* the failure.
*
* Assumptions:
* Network is locked
@ -274,7 +274,8 @@ static uint16_t sixlowpan_uncompress_ipv6proto(FAR uint8_t *fptr,
****************************************************************************/
static int sixlowpan_frame_process(FAR struct radio_driver_s *radio,
FAR const void *metadata, FAR struct iob_s *iob)
FAR const void *metadata,
FAR struct iob_s *iob)
{
FAR struct sixlowpan_reassbuf_s *reass;
struct netdev_varaddr_s fragsrc;
@ -323,8 +324,8 @@ static int sixlowpan_frame_process(FAR struct radio_driver_s *radio,
{
/* Set up for the reassembly */
fragsize = GETUINT16(fragptr, SIXLOWPAN_FRAG_DISPATCH_SIZE) & 0x07ff;
fragtag = GETUINT16(fragptr, SIXLOWPAN_FRAG_TAG);
fragsize = GETUINT16(fragptr, SIXLOWPAN_FRAG_DISPATCH_SIZE) & 0x07ff;
fragtag = GETUINT16(fragptr, SIXLOWPAN_FRAG_TAG);
g_frame_hdrlen += SIXLOWPAN_FRAG1_HDR_LEN;
ninfo("FRAG1: fragsize=%d fragtag=%d fragoffset=%d\n",
@ -381,9 +382,9 @@ static int sixlowpan_frame_process(FAR struct radio_driver_s *radio,
{
/* Get offset, tag, size. Offset is in units of 8 bytes. */
fragoffset = fragptr[SIXLOWPAN_FRAG_OFFSET];
fragtag = GETUINT16(fragptr, SIXLOWPAN_FRAG_TAG);
fragsize = GETUINT16(fragptr, SIXLOWPAN_FRAG_DISPATCH_SIZE) & 0x07ff;
fragoffset = fragptr[SIXLOWPAN_FRAG_OFFSET];
fragtag = GETUINT16(fragptr, SIXLOWPAN_FRAG_TAG);
fragsize = GETUINT16(fragptr, SIXLOWPAN_FRAG_DISPATCH_SIZE) & 0x07ff;
g_frame_hdrlen += SIXLOWPAN_FRAGN_HDR_LEN;
/* Extract the source address from the 'metadata'. */
@ -395,7 +396,9 @@ static int sixlowpan_frame_process(FAR struct radio_driver_s *radio,
return ret;
}
/* Find the existing reassembly buffer with the same tag and source address */
/* Find the existing reassembly buffer
* with the same tag and source address
*/
reass = sixlowpan_reass_find(fragtag, &fragsrc);
if (reass == NULL)
@ -409,7 +412,7 @@ static int sixlowpan_frame_process(FAR struct radio_driver_s *radio,
{
/* The packet is a fragment but its size does not match. */
nwarn("WARNING: Dropping 6LoWPAN packet. Bad fragsize: %u vs &u\n",
nwarn("WARNING: Dropping 6LoWPAN packet. Bad fragsize: %u vs &u\n",
fragsize, reass->rb_pktlen);
ret = -EPERM;
goto errout_with_reass;
@ -453,7 +456,8 @@ static int sixlowpan_frame_process(FAR struct radio_driver_s *radio,
SIXLOWPAN_DISPATCH_IPHC)
{
ninfo("IPHC Dispatch\n");
sixlowpan_uncompresshdr_hc06(radio, metadata, fragsize, iob, fptr, bptr);
sixlowpan_uncompresshdr_hc06(radio, metadata,
fragsize, iob, fptr, bptr);
}
else
#endif /* CONFIG_NET_6LOWPAN_COMPRESSION_HC06 */
@ -462,7 +466,8 @@ static int sixlowpan_frame_process(FAR struct radio_driver_s *radio,
if (hc1[SIXLOWPAN_HC1_DISPATCH] == SIXLOWPAN_DISPATCH_HC1)
{
ninfo("HC1 Dispatch\n");
sixlowpan_uncompresshdr_hc1(radio, metadata, fragsize, iob, fptr, bptr);
sixlowpan_uncompresshdr_hc1(radio, metadata,
fragsize, iob, fptr, bptr);
}
else
#endif /* CONFIG_NET_6LOWPAN_COMPRESSION_HC1 */
@ -525,7 +530,7 @@ static int sixlowpan_frame_process(FAR struct radio_driver_s *radio,
paysize = iob->io_len - g_frame_hdrlen;
if (paysize > CONFIG_NET_6LOWPAN_PKTSIZE)
{
nwarn("WARNING: Packet dropped due to payload (%u) > packet buffer (%u)\n",
nwarn("Packet dropped due to payload (%u) > packet buffer (%u)\n",
paysize, CONFIG_NET_6LOWPAN_PKTSIZE);
ret = -ENOSPC;
goto errout_with_reass;
@ -597,7 +602,8 @@ errout_with_reass:
* Name: sixlowpan_dispatch
*
* Description:
* Inject the packet in d_buf into the network for normal packet processing.
* Inject the packet in d_buf into the network for normal packet
* processing.
*
* Input Parameters:
* radio - The IEEE802.15.4 MAC network driver interface.
@ -617,7 +623,7 @@ static int sixlowpan_dispatch(FAR struct radio_driver_s *radio)
radio->r_dev.d_len);
#ifdef CONFIG_NET_PKT
/* When packet sockets are enabled, feed the frame into the packet tap */
/* When packet sockets are enabled, feed the frame into the tap */
ninfo("Packet tap\n");
pkt_input(&radio->r_dev);
@ -669,11 +675,12 @@ static int sixlowpan_dispatch(FAR struct radio_driver_s *radio)
* - The io_flink field points to the next frame in the list (if enable)
* - The last frame in the list will have io_flink == NULL.
*
* An non-NULL d_buf of size CONFIG_NET_6LOWPAN_PKTSIZE + CONFIG_NET_GUARDSIZE
* must also be provided. The frame will be decompressed and placed in
* the d_buf. Fragmented packets will also be reassembled in the d_buf as
* they are received (meaning for the driver, that two packet buffers are
* required: One for reassembly of RX packets and one used for TX polling).
* An non-NULL d_buf of size CONFIG_NET_6LOWPAN_PKTSIZE +
* CONFIG_NET_GUARDSIZE must also be provided. The frame will be
* decompressed and placed in the d_buf. Fragmented packets will also be
* reassembled in the d_buf as they are received (meaning for the driver,
* that two packet buffers are required: One for reassembly of RX packets
* and one used for TX polling).
*
* After each frame is processed into d_buf, the IOB is deallocated. If
* reassembly is incomplete, the partially reassembled packet must be
@ -723,8 +730,9 @@ int sixlowpan_input(FAR struct radio_driver_s *radio,
DEBUGASSERT(radio != NULL && framelist != NULL);
/* Sixlowpan modifies the d_buf to process fragments using reassembly buffers.
* Save the value of d_buf on entry and set it back before returning
/* Sixlowpan modifies the d_buf to process fragments using reassembly
* buffers. Save the value of d_buf on entry and set it back before
* returning
*/
d_buf_backup = radio->r_dev.d_buf;
@ -796,7 +804,8 @@ int sixlowpan_input(FAR struct radio_driver_s *radio,
&destmac);
if (ret < 0)
{
nerr("ERROR: Failed to get dest MAC address: %d\n", ret);
nerr("ERROR: Failed to get dest MAC address: %d\n",
ret);
goto drop;
}
@ -812,8 +821,9 @@ int sixlowpan_input(FAR struct radio_driver_s *radio,
FAR struct tcp_hdr_s *tcp = TCPBUF(&radio->r_dev);
uint16_t tcplen;
/* The TCP header length is encoded in the top 4 bits
* of the tcpoffset field (in units of 32-bit words).
/* The TCP header length is encoded in the top 4
* bits of the tcpoffset field (in units of 32-bit
* words).
*/
tcplen = ((uint16_t)tcp->tcpoffset >> 4) << 2;
@ -855,8 +865,8 @@ int sixlowpan_input(FAR struct radio_driver_s *radio,
buffer = radio->r_dev.d_buf + hdrlen;
buflen = radio->r_dev.d_len - hdrlen;
ret = sixlowpan_queue_frames(radio, ipv6hdr, buffer, buflen,
&destmac);
ret = sixlowpan_queue_frames(radio, ipv6hdr, buffer,
buflen, &destmac);
drop:
radio->r_dev.d_len = 0;

2
sched/wdog/wd_start.c
View file

@ -60,7 +60,7 @@
*
* Description:
* Check if the timer for the watchdog at the head of list is ready to
* run. If so, remove the watchdog from the list and execute it.
* run. If so, remove the watchdog from the list and execute it.
*
* Input Parameters:
* None