From f5d180bbdf2d855129909024ba691baf4518fe58 Mon Sep 17 00:00:00 2001
From: zhuyanlin <zhuyanlin1@xiaomi.com>
Date: Fri, 14 Jan 2022 16:52:11 +0800
Subject: [PATCH] xtensa: spit up_irq_disable and up_irq_save INTLEVEL MARCO

For up_irq_disable, use XCHAL_EXCM_LEVEL
For up_irq_save,  use XCHAL_IRQ_LEVEL.
Then we can use svcall in enter_crritical_section.

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
---
 arch/xtensa/include/irq.h         | 3 ++-
 arch/xtensa/include/xtensa/core.h | 5 +++++
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/arch/xtensa/include/irq.h b/arch/xtensa/include/irq.h
index d6808af5b4b..cf99de03d4a 100644
--- a/arch/xtensa/include/irq.h
+++ b/arch/xtensa/include/irq.h
@@ -37,6 +37,7 @@
 #include <arch/types.h>
 #include <arch/chip/tie.h>
 #include <arch/chip/core-isa.h>
+#include <arch/xtensa/core.h>
 
 #include <arch/xtensa/xtensa_specregs.h>
 #include <arch/xtensa/xtensa_corebits.h>
@@ -233,7 +234,7 @@ static inline uint32_t up_irq_save(void)
 
   __asm__ __volatile__
   (
-    "rsil %0, %1" : "=r"(ps) : "i"(XCHAL_EXCM_LEVEL)
+    "rsil %0, %1" : "=r"(ps) : "i"(XCHAL_IRQ_LEVEL)
   );
 
   /* Return the previous PS value so that it can be restored with
diff --git a/arch/xtensa/include/xtensa/core.h b/arch/xtensa/include/xtensa/core.h
index 6efab57b3f0..1385abddb20 100644
--- a/arch/xtensa/include/xtensa/core.h
+++ b/arch/xtensa/include/xtensa/core.h
@@ -90,6 +90,11 @@
 /* Interrupts ***************************************************************/
 
 /* Indexing macros: */
+#ifndef XCHAL_SYSCALL_LEVEL
+#  define XCHAL_IRQ_LEVEL  XCHAL_EXCM_LEVEL
+#else
+#  define XCHAL_IRQ_LEVEL  XCHAL_SYSCALL_LEVEL
+#endif
 
 #define _XCHAL_INTLEVEL_MASK(n)         XCHAL_INTLEVEL ## n ## _MASK
 #define XCHAL_INTLEVEL_MASK(n)          _XCHAL_INTLEVEL_MASK(n) /* n = 0 .. 15 */