From f5cf35784e5a13ea66376deffcffa9cd9a388c86 Mon Sep 17 00:00:00 2001 From: Huang Qi Date: Wed, 13 Apr 2022 16:25:18 +0800 Subject: [PATCH] arch/risc-v: Correct format of 32-bit insn in misaligned handler FIx: Format specifies type 'unsigned long' but the argument has type 'uint32_t' (aka 'unsigned int') Signed-off-by: Huang Qi --- arch/risc-v/src/common/riscv_misaligned.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/risc-v/src/common/riscv_misaligned.c b/arch/risc-v/src/common/riscv_misaligned.c index 4358dfe64f4..3c3f8431eb0 100644 --- a/arch/risc-v/src/common/riscv_misaligned.c +++ b/arch/risc-v/src/common/riscv_misaligned.c @@ -447,7 +447,7 @@ static bool decode_insn(uintptr_t *regs, riscv_insn_ctx_t *ctx) case INSN_FSD: _alert("Misaligned float instruction not support yet\n"); default: - _alert("Uncompressed: %lx\n", insn.insn); + _alert("Uncompressed: %x\n", insn.insn); return false; }