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rv32im: fix typo.

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Change-Id: I805a179c3cf56518b85f80c8ba8c52bf60929d19
Signed-off-by: zhongan <zhongan@xiaomi.com>
This commit is contained in:
zhongan 2020-11-17 13:42:13 +08:00
parent 587bb341d8
commit f5bd0a06f0
1 changed files with 2 additions and 2 deletions
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arch/risc-v/src/rv32im/riscv_schedulesigaction.c
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@ -32,8 +32,8 @@
#include <nuttx/arch.h>
#include "sched/sched.h"
#include "up_internal.h"
#include "up_arch.h"
#include "riscv_internal.h"
#include "riscv_arch.h"
#ifndef CONFIG_DISABLE_SIGNALS