diff --git a/arch/arm/src/stm32/chip/stm32_adc.h b/arch/arm/src/stm32/chip/stm32_adc.h index ea9579c3918..3a59ba25a88 100644 --- a/arch/arm/src/stm32/chip/stm32_adc.h +++ b/arch/arm/src/stm32/chip/stm32_adc.h @@ -308,24 +308,37 @@ /* Bits 12-15: Reserved */ # define ADC_CR2_JEXTSEL_SHIFT (16) /* Bits 16-19: External event select for injected group */ # define ADC_CR2_JEXTSEL_MASK (0x0F << ADC_CR2_JEXTSEL_SHIFT) -# define ADC_CR2_JEXTSEL_T1CC4 (0x0 << ADC_CR2_JEXTSEL_SHIFT) /* 0000: Timer 1 CC4 event. For STM32L15XX: TIM9_CC1 event */ -# define ADC_CR2_JEXTSEL_T1TRGO (0x01 << ADC_CR2_JEXTSEL_SHIFT) /* 0001: Timer 1 TRGO event. For STM32L15XX: TIM9_TRGO event */ -# define ADC_CR2_JEXTSEL_T2CC1 (0x02 << ADC_CR2_JEXTSEL_SHIFT) /* 0010: Timer 2 CC1 event. For STM32L15XX: TIM2_TRGO event */ -# define ADC_CR2_JEXTSEL_T2TRGO (0x03 << ADC_CR2_JEXTSEL_SHIFT) /* 0011: Timer 2 TRGO event. For STM32L15XX: TIM2_CC1 event */ -# define ADC_CR2_JEXTSEL_T3CC2 (0x04 << ADC_CR2_JEXTSEL_SHIFT) /* 0100: Timer 3 CC2 event. For STM32L15XX: TIM3_CC4 event */ -# define ADC_CR2_JEXTSEL_T3CC4 (0x05 << ADC_CR2_JEXTSEL_SHIFT) /* 0101: Timer 3 CC4 event. For STM32L15XX: TIM4_TRGO event */ -# define ADC_CR2_JEXTSEL_T4CC1 (0x06 << ADC_CR2_JEXTSEL_SHIFT) /* 0110: Timer 4 CC1 event. For STM32L15XX: TIM4_CC1 event */ -# define ADC_CR2_JEXTSEL_T4CC2 (0x07 << ADC_CR2_JEXTSEL_SHIFT) /* 0111: Timer 4 CC2 event. For STM32L15XX: TIM4_CC2 event */ -# define ADC_CR2_JEXTSEL_T4CC3 (0x08 << ADC_CR2_JEXTSEL_SHIFT) /* 1000: Timer 4 CC3 event. For STM32L15XX: TIM4_CC3 event */ -# define ADC_CR2_JEXTSEL_T4TRGO (0x09 << ADC_CR2_JEXTSEL_SHIFT) /* 1001: Timer 4 TRGO event. For STM32L15XX: TIM10_CC1 event */ -# define ADC_CR2_JEXTSEL_T5CC4 (0x0A << ADC_CR2_JEXTSEL_SHIFT) /* 1010: Timer 5 CC4 event. For STM32L15XX: TIM7_TRGO event */ -# ifndef CONFIG_STM32_STM32L15XX -# define ADC_CR2_JEXTSEL_T5TRGO (0x0B << ADC_CR2_JEXTSEL_SHIFT) /* 1011: Timer 5 TRGO event. */ -# define ADC_CR2_JEXTSEL_T8CC2 (0x0C << ADC_CR2_JEXTSEL_SHIFT) /* 1100: Timer 8 CC2 event. */ -# define ADC_CR2_JEXTSEL_T8CC3 (0x0D << ADC_CR2_JEXTSEL_SHIFT) /* 1101: Timer 8 CC3 event. */ -# define ADC_CR2_JEXTSEL_T8CC4 (0x0E << ADC_CR2_JEXTSEL_SHIFT) /* 1110: Timer 8 CC4 event. */ +# ifdef CONFIG_STM32_STM32L15XX +# define ADC_CR2_JEXTSEL_T9CC1 (0x00 << ADC_CR2_JEXTSEL_SHIFT) /* 0000: Timer 9 CC1 event */ +# define ADC_CR2_JEXTSEL_T9TRGO (0x01 << ADC_CR2_JEXTSEL_SHIFT) /* 0001: Timer 9 TRGO event */ +# define ADC_CR2_JEXTSEL_T2TRGO (0x02 << ADC_CR2_JEXTSEL_SHIFT) /* 0010: Timer 2 TRGO event*/ +# define ADC_CR2_JEXTSEL_T2CC1 (0x03 << ADC_CR2_JEXTSEL_SHIFT) /* 0011: Timer 2 CC1 event */ +# define ADC_CR2_JEXTSEL_T3CC4 (0x04 << ADC_CR2_JEXTSEL_SHIFT) /* 0100: Timer 3 CC4 event */ +# define ADC_CR2_JEXTSEL_T4TRGO (0x05 << ADC_CR2_JEXTSEL_SHIFT) /* 0101: Timer 4 TRGO event */ +# define ADC_CR2_JEXTSEL_T4CC1 (0x06 << ADC_CR2_JEXTSEL_SHIFT) /* 0110: Timer 4 CC1 event */ +# define ADC_CR2_JEXTSEL_T4CC2 (0x07 << ADC_CR2_JEXTSEL_SHIFT) /* 0111: Timer 4 CC2 event */ +# define ADC_CR2_JEXTSEL_T4CC3 (0x08 << ADC_CR2_JEXTSEL_SHIFT) /* 1000: Timer 4 CC3 event */ +# define ADC_CR2_JEXTSEL_T10CC1 (0x09 << ADC_CR2_JEXTSEL_SHIFT) /* 1001: Timer 10 CC1 event */ +# define ADC_CR2_JEXTSEL_T7TRGO (0x0A << ADC_CR2_JEXTSEL_SHIFT) /* 1010: Timer 7 TRGO event */ +# define ADC_CR2_JEXTSEL_EXTI15 (0x0F << ADC_CR2_JEXTSEL_SHIFT) /* 1111: EXTI line 15 */ +# else +# define ADC_CR2_JEXTSEL_T1CC4 (0x00 << ADC_CR2_JEXTSEL_SHIFT) /* 0000: Timer 1 CC4 event */ +# define ADC_CR2_JEXTSEL_T1TRGO (0x01 << ADC_CR2_JEXTSEL_SHIFT) /* 0001: Timer 1 TRGO event */ +# define ADC_CR2_JEXTSEL_T2CC1 (0x02 << ADC_CR2_JEXTSEL_SHIFT) /* 0010: Timer 2 CC1 event */ +# define ADC_CR2_JEXTSEL_T2TRGO (0x03 << ADC_CR2_JEXTSEL_SHIFT) /* 0011: Timer 2 TRGO event */ +# define ADC_CR2_JEXTSEL_T3CC2 (0x04 << ADC_CR2_JEXTSEL_SHIFT) /* 0100: Timer 3 CC2 event */ +# define ADC_CR2_JEXTSEL_T3CC4 (0x05 << ADC_CR2_JEXTSEL_SHIFT) /* 0101: Timer 3 CC4 event */ +# define ADC_CR2_JEXTSEL_T4CC1 (0x06 << ADC_CR2_JEXTSEL_SHIFT) /* 0110: Timer 4 CC1 event */ +# define ADC_CR2_JEXTSEL_T4CC2 (0x07 << ADC_CR2_JEXTSEL_SHIFT) /* 0111: Timer 4 CC2 event */ +# define ADC_CR2_JEXTSEL_T4CC3 (0x08 << ADC_CR2_JEXTSEL_SHIFT) /* 1000: Timer 4 CC3 event */ +# define ADC_CR2_JEXTSEL_T4TRGO (0x09 << ADC_CR2_JEXTSEL_SHIFT) /* 1001: Timer 4 TRGO event */ +# define ADC_CR2_JEXTSEL_T5CC4 (0x0A << ADC_CR2_JEXTSEL_SHIFT) /* 1010: Timer 5 CC4 event */ +# define ADC_CR2_JEXTSEL_T5TRGO (0x0B << ADC_CR2_JEXTSEL_SHIFT) /* 1011: Timer 5 TRGO event */ +# define ADC_CR2_JEXTSEL_T8CC2 (0x0C << ADC_CR2_JEXTSEL_SHIFT) /* 1100: Timer 8 CC2 event */ +# define ADC_CR2_JEXTSEL_T8CC3 (0x0D << ADC_CR2_JEXTSEL_SHIFT) /* 1101: Timer 8 CC3 event */ +# define ADC_CR2_JEXTSEL_T8CC4 (0x0E << ADC_CR2_JEXTSEL_SHIFT) /* 1110: Timer 8 CC4 event */ +# define ADC_CR2_JEXTSEL_EXTI15 (0x0F << ADC_CR2_JEXTSEL_SHIFT) /* 1111: EXTI line 15 */ # endif -# define ADC_CR2_JEXTSEL_EXTI (0x0F << ADC_CR2_JEXTSEL_SHIFT) /* 1111: EXTI line15 */ # define ADC_CR2_JEXTEN_SHIFT (20) /* Bits 20-21: External trigger enable for injected channels */ # define ADC_CR2_JEXTEN_MASK (3 << ADC_CR2_JEXTEN_SHIFT) @@ -338,24 +351,37 @@ /* Bit 23: Reserved, must be kept at reset value. */ # define ADC_CR2_EXTSEL_SHIFT (24) /* Bits 24-27: External Event Select for regular group */ # define ADC_CR2_EXTSEL_MASK (0x0F << ADC_CR2_EXTSEL_SHIFT) -# define ADC_CR2_EXTSEL_T1CC1 (0x0 << ADC_CR2_EXTSEL_SHIFT) /* 0000: Timer 1 CC1 event. For STM32L15XX: TIM9_CC2 event */ -# define ADC_CR2_EXTSEL_T1CC2 (0x01 << ADC_CR2_EXTSEL_SHIFT) /* 0001: Timer 1 CC2 event. For STM32L15XX: TIM9_TRGO event */ -# define ADC_CR2_EXTSEL_T1CC3 (0x02 << ADC_CR2_EXTSEL_SHIFT) /* 0010: Timer 1 CC3 event. For STM32L15XX: TIM2_CC3 event */ -# define ADC_CR2_EXTSEL_T2CC2 (0x03 << ADC_CR2_EXTSEL_SHIFT) /* 0011: Timer 2 CC2 event. For STM32L15XX: TIM2_CC2 event */ -# define ADC_CR2_EXTSEL_T2CC3 (0x04 << ADC_CR2_EXTSEL_SHIFT) /* 0100: Timer 2 CC3 event. For STM32L15XX: TIM3_TRGO event */ -# define ADC_CR2_EXTSEL_T2CC4 (0x05 << ADC_CR2_EXTSEL_SHIFT) /* 0101: Timer 2 CC4 event. For STM32L15XX: TIM4_CC4 event */ -# define ADC_CR2_EXTSEL_T2TRGO (0x06 << ADC_CR2_EXTSEL_SHIFT) /* 0110: Timer 2 TRGO event. For STM32L15XX: TIM2_TRGO event */ -# define ADC_CR2_EXTSEL_T3CC1 (0x07 << ADC_CR2_EXTSEL_SHIFT) /* 0111: Timer 3 CC1 event. For STM32L15XX: TIM3_CC1 event */ -# define ADC_CR2_EXTSEL_T3TRGO (0x08 << ADC_CR2_EXTSEL_SHIFT) /* 1000: Timer 3 TRGO event. For STM32L15XX: TIM3_CC3 event */ -# define ADC_CR2_EXTSEL_T4CC4 (0x09 << ADC_CR2_EXTSEL_SHIFT) /* 1001: Timer 4 CC4 event. For STM32L15XX: TIM4_TRGO event */ -# define ADC_CR2_EXTSEL_T5CC1 (0x0A << ADC_CR2_EXTSEL_SHIFT) /* 1010: Timer 5 CC1 event. For STM32L15XX: TIM6_TRGO event */ -# ifndef CONFIG_STM32_STM32L15XX +# ifdef CONFIG_STM32_STM32L15XX +# define ADC_CR2_EXTSEL_T9CC2 (0x00 << ADC_CR2_EXTSEL_SHIFT) /* 0000: Timer 9 CC2 event */ +# define ADC_CR2_EXTSEL_T9TRGO (0x01 << ADC_CR2_EXTSEL_SHIFT) /* 0001: Timer 9 TRGO event */ +# define ADC_CR2_EXTSEL_T2CC3 (0x02 << ADC_CR2_EXTSEL_SHIFT) /* 0010: Timer 2 CC3 event */ +# define ADC_CR2_EXTSEL_T2CC2 (0x03 << ADC_CR2_EXTSEL_SHIFT) /* 0011: Timer 2 CC2 event */ +# define ADC_CR2_EXTSEL_T3TRGO (0x04 << ADC_CR2_EXTSEL_SHIFT) /* 0100: Timer 3 TRGO event */ +# define ADC_CR2_EXTSEL_T4CC4 (0x05 << ADC_CR2_EXTSEL_SHIFT) /* 0101: Timer 4 CC4 event */ +# define ADC_CR2_EXTSEL_T2TRGO (0x06 << ADC_CR2_EXTSEL_SHIFT) /* 0110: Timer 2 TRGO event */ +# define ADC_CR2_EXTSEL_T3CC1 (0x07 << ADC_CR2_EXTSEL_SHIFT) /* 0111: Timer 3 CC1 event */ +# define ADC_CR2_EXTSEL_T3CC3 (0x08 << ADC_CR2_EXTSEL_SHIFT) /* 1000: Timer 3 CC3 event */ +# define ADC_CR2_EXTSEL_T4TRGO (0x09 << ADC_CR2_EXTSEL_SHIFT) /* 1001: Timer 4 TRGO event */ +# define ADC_CR2_EXTSEL_T6TRGO (0x0A << ADC_CR2_EXTSEL_SHIFT) /* 1010: Timer 6 TRGO event */ +# define ADC_CR2_EXTSEL_EXTI11 (0x0F << ADC_CR2_EXTSEL_SHIFT) /* 1111: EXTI line 11 */ +# else +# define ADC_CR2_EXTSEL_T1CC1 (0x0 << ADC_CR2_EXTSEL_SHIFT) /* 0000: Timer 1 CC1 event */ +# define ADC_CR2_EXTSEL_T1CC2 (0x01 << ADC_CR2_EXTSEL_SHIFT) /* 0001: Timer 1 CC2 event */ +# define ADC_CR2_EXTSEL_T1CC3 (0x02 << ADC_CR2_EXTSEL_SHIFT) /* 0010: Timer 1 CC3 event */ +# define ADC_CR2_EXTSEL_T2CC2 (0x03 << ADC_CR2_EXTSEL_SHIFT) /* 0011: Timer 2 CC2 event */ +# define ADC_CR2_EXTSEL_T2CC3 (0x04 << ADC_CR2_EXTSEL_SHIFT) /* 0100: Timer 2 CC3 event */ +# define ADC_CR2_EXTSEL_T2CC4 (0x05 << ADC_CR2_EXTSEL_SHIFT) /* 0101: Timer 2 CC4 event */ +# define ADC_CR2_EXTSEL_T2TRGO (0x06 << ADC_CR2_EXTSEL_SHIFT) /* 0110: Timer 2 TRGO event */ +# define ADC_CR2_EXTSEL_T3CC1 (0x07 << ADC_CR2_EXTSEL_SHIFT) /* 0111: Timer 3 CC1 event */ +# define ADC_CR2_EXTSEL_T3TRGO (0x08 << ADC_CR2_EXTSEL_SHIFT) /* 1000: Timer 3 TRGO event */ +# define ADC_CR2_EXTSEL_T4CC4 (0x09 << ADC_CR2_EXTSEL_SHIFT) /* 1001: Timer 4 CC4 event */ +# define ADC_CR2_EXTSEL_T5CC1 (0x0A << ADC_CR2_EXTSEL_SHIFT) /* 1010: Timer 5 CC1 event */ # define ADC_CR2_EXTSEL_T5CC2 (0x0B << ADC_CR2_EXTSEL_SHIFT) /* 1011: Timer 5 CC2 event */ # define ADC_CR2_EXTSEL_T5CC3 (0x0C << ADC_CR2_EXTSEL_SHIFT) /* 1100: Timer 5 CC3 event */ # define ADC_CR2_EXTSEL_T8CC1 (0x0D << ADC_CR2_EXTSEL_SHIFT) /* 1101: Timer 8 CC1 event */ # define ADC_CR2_EXTSEL_T8TRGO (0x0E << ADC_CR2_EXTSEL_SHIFT) /* 1110: Timer 8 TRGO event */ +# define ADC_CR2_EXTSEL_EXTI11 (0x0F << ADC_CR2_EXTSEL_SHIFT) /* 1111: EXTI line 11 */ # endif -# define ADC_CR2_EXTSEL_EXTI (0x0F << ADC_CR2_EXTSEL_SHIFT) /* 1111: EXTI line11 */ # define ADC_CR2_EXTEN_SHIFT (28) /* Bits 28-29: External trigger enable for regular channels */ # define ADC_CR2_EXTEN_MASK (3 << ADC_CR2_EXTEN_SHIFT) @@ -375,7 +401,7 @@ # define ADC_CR2_JEXTSEL_T2CC1 (3 << ADC_CR2_JEXTSEL_SHIFT) /* 011: Timer 2 CC1 event */ # define ADC_CR2_JEXTSEL_T3CC4 (4 << ADC_CR2_JEXTSEL_SHIFT) /* 100: Timer 3 CC4 event */ # define ADC_CR2_JEXTSEL_T4TRGO (5 << ADC_CR2_JEXTSEL_SHIFT) /* 101: Timer 4 TRGO event */ -# define ADC_CR2_JEXTSEL_EXTI15 (6 << ADC_CR2_JEXTSEL_SHIFT) /* 110: EXTI line15 */ +# define ADC_CR2_JEXTSEL_EXTI15 (6 << ADC_CR2_JEXTSEL_SHIFT) /* 110: EXTI line 15 */ # define ADC_CR2_JEXTSEL_SWSTART (7 << ADC_CR2_JEXTSEL_SHIFT) /* 111: JSWSTART */ # define ADC_CR2_JEXTTRIG (1 << 15) /* Bit 15: External Trigger Conversion mode for injected channels */ @@ -387,7 +413,7 @@ # define ADC_CR2_EXTSEL_T2CC2 (3 << ADC_CR2_EXTSEL_SHIFT) /* 011: Timer 2 CC2 event */ # define ADC_CR2_EXTSEL_T3TRGO (4 << ADC_CR2_EXTSEL_SHIFT) /* 100: Timer 3 TRGO event */ # define ADC_CR2_EXTSEL_T4CC4 (5 << ADC_CR2_EXTSEL_SHIFT) /* 101: Timer 4 CC4 event */ -# define ADC_CR2_EXTSEL_EXTI11 (6 << ADC_CR2_EXTSEL_SHIFT) /* 110: EXTI line11 */ +# define ADC_CR2_EXTSEL_EXTI11 (6 << ADC_CR2_EXTSEL_SHIFT) /* 110: EXTI line 11 */ # define ADC_CR2_EXTSEL_SWSTART (7 << ADC_CR2_EXTSEL_SHIFT) /* 111: SWSTART */ # define ADC_CR2_EXTTRIG (1 << 20) /* Bit 20: External Trigger Conversion mode for regular channels */ @@ -585,6 +611,9 @@ # define ADC_SQR1_L_SHIFT (20) /* Bits 23-20: Regular channel sequence length */ # define ADC_SQR1_L_MASK (0x0f << ADC_SQR1_L_SHIFT) # define ADC_SQR1_RESERVED (0xff000000) +# define ADC_SQR1_FIRST (13) +# define ADC_SQR1_LAST (16) +# define ADC_SQR1_SQ_OFFSET (0) #else # define ADC_SQR1_SQ25_SHIFT (0) /* Bits 4-0: 25th conversion in regular sequence */ # define ADC_SQR1_SQ25_MASK (0x1f << ADC_SQR1_SQ25_SHIFT) @@ -597,6 +626,9 @@ # define ADC_SQR1_L_SHIFT (20) /* Bits 24-20: Regular channel sequence length */ # define ADC_SQR1_L_MASK (0x1f << ADC_SQR1_L_SHIFT) # define ADC_SQR1_RESERVED (0xff000000) +# define ADC_SQR1_FIRST (25) +# define ADC_SQR1_LAST (28) +# define ADC_SQR1_SQ_OFFSET (0) #endif /* ADC regular sequence register 2 */ @@ -615,6 +647,9 @@ # define ADC_SQR2_SQ12_SHIFT (25) /* Bits 29-25: 12th conversion in regular sequence */ # define ADC_SQR2_SQ12_MASK (0x1f << ADC_SQR2_SQ12_SHIFT) # define ADC_SQR2_RESERVED (0xc0000000) +# define ADC_SQR2_FIRST (7) +# define ADC_SQR2_LAST (12) +# define ADC_SQR2_SQ_OFFSET (0) #else # define ADC_SQR2_SQ19_SHIFT (0) /* Bits 4-0: 19th conversion in regular sequence */ # define ADC_SQR2_SQ19_MASK (0x1f << ADC_SQR2_SQ19_SHIFT) @@ -629,6 +664,9 @@ # define ADC_SQR2_SQ24_SHIFT (25) /* Bits 29-25: 24th conversion in regular sequence */ # define ADC_SQR2_SQ24_MASK (0x1f << ADC_SQR2_SQ24_SHIFT) # define ADC_SQR2_RESERVED (0xc0000000) +# define ADC_SQR2_FIRST (19) +# define ADC_SQR2_LAST (24) +# define ADC_SQR2_SQ_OFFSET (0) #endif /* ADC regular sequence register 3 */ @@ -647,6 +685,9 @@ # define ADC_SQR3_SQ6_SHIFT (25) /* Bits 29-25: 6th conversion in regular sequence */ # define ADC_SQR3_SQ6_MASK (0x1f << ADC_SQR3_SQ6_SHIFT) # define ADC_SQR3_RESERVED (0xc0000000) +# define ADC_SQR3_FIRST (1) +# define ADC_SQR3_LAST (6) +# define ADC_SQR3_SQ_OFFSET (0) #else # define ADC_SQR3_SQ13_SHIFT (0) /* Bits 4-0: 13th conversion in regular sequence */ # define ADC_SQR3_SQ13_MASK (0x1f << ADC_SQR3_SQ13_SHIFT) @@ -661,6 +702,9 @@ # define ADC_SQR3_SQ18_SHIFT (25) /* Bits 29-25: 18th conversion in regular sequence */ # define ADC_SQR3_SQ18_MASK (0x1f << ADC_SQR3_SQ18_SHIFT) # define ADC_SQR3_RESERVED (0xc0000000) +# define ADC_SQR3_FIRST (13) +# define ADC_SQR3_LAST (18) +# define ADC_SQR3_SQ_OFFSET (0) #endif /* ADC regular sequence register 4 */ @@ -679,6 +723,9 @@ # define ADC_SQR4_SQ12_SHIFT (25) /* Bits 29-25: 12th conversion in regular sequence */ # define ADC_SQR4_SQ12_MASK (0x1f << ADC_SQR4_SQ12_SHIFT) # define ADC_SQR4_RESERVED (0xc0000000) +# define ADC_SQR4_FIRST (7) +# define ADC_SQR4_LAST (12) +# define ADC_SQR4_SQ_OFFSET (0) #endif /* ADC regular sequence register 5 */ @@ -697,8 +744,15 @@ # define ADC_SQR5_SQ6_SHIFT (25) /* Bits 29-25: 6th conversion in regular sequence */ # define ADC_SQR5_SQ6_MASK (0x1f << ADC_SQR5_SQ6_SHIFT) # define ADC_SQR5_RESERVED (0xc0000000) +# define ADC_SQR5_FIRST (1) +# define ADC_SQR5_LAST (6) +# define ADC_SQR5_SQ_OFFSET (0) #endif +/* Offset between SQ bits */ + +#define ADC_SQ_OFFSET (5) + /* ADC injected sequence register */ #define ADC_JSQR_JSQ1_SHIFT (0) /* Bits 4-0: 1st conversion in injected sequence */ @@ -714,15 +768,15 @@ /* ADC injected data register 1-4 */ -#define ADC_JDR_SHIFT (0) /* Bits 15-0: Injected data */ -#define ADC_JDR_MASK (0xffff << ADC_JDR_SHIFT) +#define ADC_JDR_JDATA_SHIFT (0) /* Bits 15-0: Injected data */ +#define ADC_JDR_JDATA_MASK (0xffff << ADC_JDR_JDATA_SHIFT) /* ADC regular data register */ -#define ADC_DR_DATA_SHIFT (0) /* Bits 15-0 Regular data */ -#define ADC_DR_DATA_MASK (0xffff << ADC_DR_DATA_SHIFT) +#define ADC_DR_RDATA_SHIFT (0) /* Bits 15-0 Regular data */ +#define ADC_DR_RDATA_MASK (0xffff << ADC_DR_RDATA_SHIFT) -#ifndef CONFIG_STM32_STM32L15XX +#ifdef CONFIG_STM32_STM32F10XX # define ADC_DR_ADC2DATA_SHIFT (16) /* Bits 31-16: ADC2 data */ # define ADC_DR_ADC2DATA_MASK (0xffff << ADC_DR_ADC2DATA_SHIFT) #endif @@ -784,7 +838,7 @@ /* Bits 5-7: Reserved, must be kept at reset value. */ # define ADC_CCR_DELAY_SHIFT (8) /* Bits 8-11: Delay between 2 sampling phases */ # define ADC_CCR_DELAY_MASK (15 << ADC_CCR_DELAY_SHIFT) -# define ADC_CCR_DELAY(n) (((5)-5) << ADC_CCR_DELAY_SHIFT) /* n * TADCCLK, n=5-20 */ +# define ADC_CCR_DELAY(n) (((n)-5) << ADC_CCR_DELAY_SHIFT) /* n * TADCCLK, n=5-20 */ /* Bit 12 Reserved, must be kept at reset value. */ # define ADC_CCR_DDS (1 << 13) /* Bit 13: DMA disable selection (for multi-ADC mode) */ diff --git a/arch/arm/src/stm32/chip/stm32f30xxx_adc.h b/arch/arm/src/stm32/chip/stm32f30xxx_adc.h index 638acf74863..5763260eb9c 100644 --- a/arch/arm/src/stm32/chip/stm32f30xxx_adc.h +++ b/arch/arm/src/stm32/chip/stm32f30xxx_adc.h @@ -210,7 +210,7 @@ #define STM32_ADC34_CDR (STM32_ADC34_BASE+STM32_ADC_CDR_OFFSET) /* Register Bitfield Definitions ********************************************************************/ -/* ADC interrupt and status register (ISR) and ADC interrupt enable register (IER) */ +/* ADC interrupt and status register (ISR) and ADC interrupt enable register (IER) */ #define ADC_INT_ARDY (1 << 0) /* Bit 0: ADC ready */ #define ADC_INT_EOSMP (1 << 1) /* Bit 1: End of sampling flag */ @@ -242,7 +242,8 @@ /* ADC configuration register */ -#define ADC_CFGR_DMACFG (1 << 1) /* Bit 0: Direct memory access configuration */ +#define ADC_CFGR_DMAEN (1 << 0) /* Bit 0: Direct memory access enable */ +#define ADC_CFGR_DMACFG (1 << 1) /* Bit 1: Direct memory access configuration */ #define ADC_CFGR_RES_SHIFT (3) /* Bits 3-4: Data resolution */ #define ADC_CFGR_RES_MASK (3 << ADC_CFGR_RES_SHIFT) # define ADC_CFGR_RES_12BIT (0 << ADC_CFGR_RES_SHIFT) /* 15 ADCCLK clyes */ @@ -252,7 +253,34 @@ #define ADC_CFGR_ALIGN (1 << 5) /* Bit 5: Data Alignment */ #define ADC_CFGR_EXTSEL_SHIFT (6) /* Bits 6-9: External Event Select for regular group */ #define ADC_CFGR_EXTSEL_MASK (15 << ADC_CFGR_EXTSEL_SHIFT) -# define ADC_CFGR_EXTSEL(event) ((event) << ADC_CFGR_EXTSEL_SHIFT) /* Event = 0..15 */ +# define ADC12_CFGR_EXTSEL_T1CC1 (0 << ADC_CFGR_EXTSEL_SHIFT) +# define ADC12_CFGR_EXTSEL_T1CC2 (1 << ADC_CFGR_EXTSEL_SHIFT) +# define ADC12_CFGR_EXTSEL_T1CC3 (2 << ADC_CFGR_EXTSEL_SHIFT) +# define ADC12_CFGR_EXTSEL_T2CC2 (3 << ADC_CFGR_EXTSEL_SHIFT) +# define ADC12_CFGR_EXTSEL_T3TRGO (4 << ADC_CFGR_EXTSEL_SHIFT) +# define ADC12_CFGR_EXTSEL_T4CC4 (5 << ADC_CFGR_EXTSEL_SHIFT) +# define ADC12_CFGR_EXTSEL_EXTI11 (6 << ADC_CFGR_EXTSEL_SHIFT) /* 0110: EXTI line 11 */ +# define ADC12_CFGR_EXTSEL_T8TRGO (7 << ADC_CFGR_EXTSEL_SHIFT) +# define ADC12_CFGR_EXTSEL_T1TRGO (9 << ADC_CFGR_EXTSEL_SHIFT) +# define ADC12_CFGR_EXTSEL_T2TRGO (11 << ADC_CFGR_EXTSEL_SHIFT) +# define ADC12_CFGR_EXTSEL_T4TRGO (12 << ADC_CFGR_EXTSEL_SHIFT) +# define ADC12_CFGR_EXTSEL_T6TRGO (13 << ADC_CFGR_EXTSEL_SHIFT) +# define ADC12_CFGR_EXTSEL_T15TRGO (14 << ADC_CFGR_EXTSEL_SHIFT) +# define ADC12_CFGR_EXTSEL_T3CC4 (15 << ADC_CFGR_EXTSEL_SHIFT) +# define ADC34_CFGR_EXTSEL_T3CC1 (0 << ADC_CFGR_EXTSEL_SHIFT) +# define ADC34_CFGR_EXTSEL_T2CC3 (1 << ADC_CFGR_EXTSEL_SHIFT) +# define ADC34_CFGR_EXTSEL_T1CC3 (2 << ADC_CFGR_EXTSEL_SHIFT) +# define ADC34_CFGR_EXTSEL_T8CC1 (3 << ADC_CFGR_EXTSEL_SHIFT) +# define ADC34_CFGR_EXTSEL_T8TRGO (4 << ADC_CFGR_EXTSEL_SHIFT) +# define ADC34_CFGR_EXTSEL_T20TRGO (5 << ADC_CFGR_EXTSEL_SHIFT) +# define ADC34_CFGR_EXTSEL_T4CC1 (6 << ADC_CFGR_EXTSEL_SHIFT) +# define ADC34_CFGR_EXTSEL_T2TRGO (7 << ADC_CFGR_EXTSEL_SHIFT) +# define ADC34_CFGR_EXTSEL_T1TRGO (9 << ADC_CFGR_EXTSEL_SHIFT) +# define ADC34_CFGR_EXTSEL_T3TRGO (11 << ADC_CFGR_EXTSEL_SHIFT) +# define ADC34_CFGR_EXTSEL_T4TRGO (12 << ADC_CFGR_EXTSEL_SHIFT) +# define ADC34_CFGR_EXTSEL_T7TRGO (13 << ADC_CFGR_EXTSEL_SHIFT) +# define ADC34_CFGR_EXTSEL_T15TRGO (14 << ADC_CFGR_EXTSEL_SHIFT) +# define ADC34_CFGR_EXTSEL_T2CC1 (15 << ADC_CFGR_EXTSEL_SHIFT) #define ADC_CFGR_EXTEN_SHIFT (10) /* Bits 10-11: External trigger/polarity selection regular channels */ #define ADC_CFGR_EXTEN_MASK (3 << ADC_CFGR_EXTEN_SHIFT) # define ADC_CFGR_EXTEN_NONE (0 << ADC_CFGR_EXTEN_SHIFT) /* Trigger detection disabled */ @@ -285,7 +313,7 @@ #define ADC_SMPR_19p5 4 /* 100: 19.5 cycles */ #define ADC_SMPR_61p5 5 /* 101: 61.5 cycles */ #define ADC_SMPR_181p5 6 /* 110: 181.5 cycles */ -#define ADC_SMPR_2601p5 7 /* 111: 601.5 cycles */ +#define ADC_SMPR_601p5 7 /* 111: 601.5 cycles */ #define ADC_SMPR1_SMP1_SHIFT (3) /* Bits 5-3: Channel 1 Sample time selection */ #define ADC_SMPR1_SMP1_MASK (7 << ADC_SMPR1_SMP1_SHIFT) @@ -348,6 +376,10 @@ #define ADC_TR3_HT_SHIFT (16) /* Bits 16-23: Analog watchdog 3 higher threshold */ #define ADC_TR3_HT_MASK (0xff << ADC_TR3_HT_SHIFT) +/* Offset between SQ bits */ + +#define ADC_SQ_OFFSET (6) + /* ADC regular sequence register 1 */ #define ADC_SQR1_L_SHIFT (0) /* Bits 0-3: Regular channel sequence length */ @@ -360,6 +392,10 @@ #define ADC_SQR1_SQ3_MASK (0x1f << ADC_SQR1_SQ3_SHIFT) #define ADC_SQR1_SQ4_SHIFT (24) /* Bits 24-28: 4th conversion in regular sequence */ #define ADC_SQR1_SQ4_MASK (0x1f << ADC_SQR1_SQ4_SHIFT) +#define ADC_SQR1_RESERVED (0xe0820830) +#define ADC_SQR1_FIRST (1) +#define ADC_SQR1_LAST (4) +#define ADC_SQR1_SQ_OFFSET (1*ADC_SQ_OFFSET) /* ADC regular sequence register 2 */ @@ -372,7 +408,11 @@ #define ADC_SQR2_SQ8_SHIFT (18) /* Bits 18-22: 8th conversion in regular sequence */ #define ADC_SQR2_SQ8_MASK (0x1f << ADC_SQR2_SQ8_SHIFT) #define ADC_SQR2_SQ9_SHIFT (24) /* Bits 24-28: 9th conversion in regular sequence */ -#define ADC_SQR2_SQ9_MASK (0x1f << ADC_SQR2_SQ9_SHIFT ) +#define ADC_SQR2_SQ9_MASK (0x1f << ADC_SQR2_SQ9_SHIFT) +#define ADC_SQR2_RESERVED (0xe0820820) +#define ADC_SQR2_FIRST (5) +#define ADC_SQR2_LAST (9) +#define ADC_SQR2_SQ_OFFSET (0) /* ADC regular sequence register 3 */ @@ -385,18 +425,27 @@ #define ADC_SQR3_SQ13_SHIFT (18) /* Bits 18-22: 13th conversion in regular sequence */ #define ADC_SQR3_SQ13_MASK (0x1f << ADC_SQR3_SQ13_SHIFT) #define ADC_SQR3_SQ14_SHIFT (24) /* Bits 24-28: 14th conversion in regular sequence */ -#define ADC_SQR3_SQ14_MASK (0x1f << ADC_SQR3_SQ14_SHIFT ) +#define ADC_SQR3_SQ14_MASK (0x1f << ADC_SQR3_SQ14_SHIFT) +#define ADC_SQR3_RESERVED (0xe0820820) +#define ADC_SQR3_FIRST (10) +#define ADC_SQR3_LAST (14) +#define ADC_SQR3_SQ_OFFSET (0) /* ADC regular sequence register 4 */ -#define ADC_SQR4_SQ15_SHIFT (0) /* Bits 4-0: 14th conversion in regular sequence */ +#define ADC_SQR4_SQ15_SHIFT (0) /* Bits 4-0: 15th conversion in regular sequence */ #define ADC_SQR4_SQ15_MASK (0x1f << ADC_SQR4_SQ15_SHIFT) -#define ADC_SQR4_SQ16_SHIFT (6) /* Bits 6-10: 15th conversion in regular sequence */ +#define ADC_SQR4_SQ16_SHIFT (6) /* Bits 6-10: 16th conversion in regular sequence */ #define ADC_SQR4_SQ16_MASK (0x1f << ADC_SQR4_SQ16_SHIFT) +#define ADC_SQR4_RESERVED (0xfffff820) +#define ADC_SQR4_FIRST (15) +#define ADC_SQR4_LAST (16) +#define ADC_SQR4_SQ_OFFSET (0) /* ADC regular data register */ -#define ADC_DR_MASK (0xffff) +#define ADC_DR_RDATA_SHIFT (0) +#define ADC_DR_RDATA_MASK (0xffff << ADC_DR_RDATA_SHIFT) /* ADC injected sequence register */ @@ -405,7 +454,34 @@ # define ADC_JSQR_JL(n) (((n)-1) << ADC_JSQR_JL_SHIFT) /* n=1..4 */ #define ADC_JSQR_JEXTSEL_SHIFT (2) /* Bits 2-5: External Trigger Selection for injected group */ #define ADC_JSQR_JEXTSEL_MASK (15 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC_JSQR_JEXTSEL(event) ((event) << ADC_JSQR_JEXTSEL_SHIFT) /* Event = 0..15 */ +# define ADC12_JSQR_JEXTSEL_T1TRGO (0 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_T1CC4 (1 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_T2TRGO (2 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_T2CC1 (3 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_T3CC4 (4 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_T4TRGO (5 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_T20TRGO (6 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_T8CC4 (7 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_T8TRGO (9 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_T3CC3 (11 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_T3TRGO (12 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_T3CC1 (13 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_T6TRGO (14 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_T15TRGO (15 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_T1TRGO (0 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_T1CC4 (1 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_T4CC3 (2 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_T8CC2 (3 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_T8CC4 (4 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_T20TRGO (5 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_T4CC4 (6 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_T4TRGO (7 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_T8TRGO (9 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_T1CC3 (11 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_T3TRGO (12 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_T2TRGO (13 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_T7TRGO (14 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_T15TRGO (15 << ADC_JSQR_JEXTSEL_SHIFT) # define ADC_JSQR_JEXTEN_SHIFT (6) /* Bits 6-7: External trigger selection for injected greoup */ # define ADC_JSQR_JEXTEN_MASK (3 << ADC_JSQR_JEXTEN_SHIFT) # define ADC_JSQR_JEXTEN_NONE (0 << ADC_JSQR_JEXTEN_SHIFT) /* 00: Trigger detection disabled */ @@ -437,96 +513,97 @@ /* ADC injected data register 1, 2, 3, and 4 */ -#define ADC_JDR_MASK (0xffff) +#define ADC_JDR_JDATA_SHIFT (0) +#define ADC_JDR_JDATA_MASK (0xffff << ADC_JDR_JDATA_SHIFT) /* ADC analog watchdog 2 configuration register */ -#define ADC_AWD2CR_CH_SHIFT (1) /* Bits 1-18: Analog watchdog 2 channel selection */ -#define ADC_AWD2CR_CH_MASK (0x3ffff << ADC_AWD2CR_CH_SHIFT) -# define ADC_AWD2CR_CH(n) (1 << (n)) /* Channel n=1..18 */ +#define ADC_AWD2CR_CH_SHIFT (1) /* Bits 1-18: Analog watchdog 2 channel selection */ +#define ADC_AWD2CR_CH_MASK (0x3ffff << ADC_AWD2CR_CH_SHIFT) +# define ADC_AWD2CR_CH(n) (1 << (n)) /* Channel n=1..18 */ /* ADC analog watchdog 3 configuration register */ -#define ADC_AWD3CR_CH_SHIFT (1) /* Bits 1-18: Analog watchdog 2 channel selection */ -#define ADC_AWD3CR_CH_MASK (0x3ffff << ADC_AWD3CR_CH_SHIFT) -# define ADC_AWD3CR_CH(n) (1 << (n)) /* Channel n=1..18 */ +#define ADC_AWD3CR_CH_SHIFT (1) /* Bits 1-18: Analog watchdog 2 channel selection */ +#define ADC_AWD3CR_CH_MASK (0x3ffff << ADC_AWD3CR_CH_SHIFT) +# define ADC_AWD3CR_CH(n) (1 << (n)) /* Channel n=1..18 */ /* ADC differential mode selection register 2 */ #define ADC_DIFSEL_ -#define ADC_DIFSEL_CH_SHIFT (1) /* Bits 1-18: Analog watchdog 2 channel selection */ -#define ADC_DIFSEL_CH_MASK (0x3ffff << ADC_DIFSEL_CH_SHIFT) -# define ADC_DIFSEL_CH(n) (1 << (n)) /* Channel n=1..18 */ +#define ADC_DIFSEL_CH_SHIFT (1) /* Bits 1-18: Analog watchdog 2 channel selection */ +#define ADC_DIFSEL_CH_MASK (0x3ffff << ADC_DIFSEL_CH_SHIFT) +# define ADC_DIFSEL_CH(n) (1 << (n)) /* Channel n=1..18 */ /* ADC calibration factors */ -#define ADC_CALFACT_S_SHIFT (0) /* Bits 0-6: Calibration factors in single-ended mode */ -#define ADC_CALFACT_S_MASK (0x7f << ADC_CALFACT_S_SHIFT) -#define ADC_CALFACT_D_SHIFT (16) /* Bits 16-22: Calibration Factors indifferential mode */ -#define ADC_CALFACT_D_MASK (0x7f << ADC_CALFACT_D_SHIFT) +#define ADC_CALFACT_S_SHIFT (0) /* Bits 0-6: Calibration factors in single-ended mode */ +#define ADC_CALFACT_S_MASK (0x7f << ADC_CALFACT_S_SHIFT) +#define ADC_CALFACT_D_SHIFT (16) /* Bits 16-22: Calibration Factors indifferential mode */ +#define ADC_CALFACT_D_MASK (0x7f << ADC_CALFACT_D_SHIFT) /* Common status register */ -#define ADC_CSR_ADRDY_MST (1 << 0) /* Bit 0: Master ADC ready */ -#define ADC_CSR_EOSMP_MST (1 << 1) /* Bit 1: End of Sampling phase flag (master ADC) */ -#define ADC_CSR_EOC_MST (1 << 2) /* Bit 2: End of regular conversion (master ADC) */ -#define ADC_CSR_EOS_MST (1 << 3) /* Bit 3: End of regular sequence flag (master ADC) */ -#define ADC_CSR_OVR_MST (1 << 4) /* Bit 4: Overrun flag (master ADC) */ -#define ADC_CSR_JEOC_MST (1 << 5) /* Bit 5: End of injected conversion flag (master ADC) */ -#define ADC_CSR_JEOS_MST (1 << 6) /* Bit 6: End of injected sequence flag (master ADC) */ -#define ADC_CSR_AWD1_MST (1 << 7) /* Bit 7: Analog watchdog 1 flag (master ADC) */ -#define ADC_CSR_AWD2_MST (1 << 8) /* Bit 8: Analog watchdog 2 flag (master ADC) */ -#define ADC_CSR_AWD3_MST (1 << 9) /* Bit 9: Analog watchdog 3 flag (master ADC) */ -#define ADC_CSR_JQOVF_MST (1 << 10) /* Bit 10: Injected Context Queue Overflow flag (master ADC) */ -#define ADC_CSR_ADRDY_SLV (1 << 16) /* Bit 16: Slave ADC ready */ -#define ADC_CSR_EOSMP_SLV (1 << 17) /* Bit 17: End of Sampling phase flag (slave ADC) */ -#define ADC_CSR_EOC_SLV (1 << 18) /* Bit 18: End of regular conversion (slave ADC) */ -#define ADC_CSR_EOS_SLV (1 << 19) /* Bit 19: End of regular sequence flag (slave ADC) */ -#define ADC_CSR_OVR_SLV (1 << 20) /* Bit 20: Overrun flag (slave ADC) */ -#define ADC_CSR_JEOC_SLV (1 << 21) /* Bit 21: End of injected conversion flag (slave ADC) */ -#define ADC_CSR_JEOS_SLV (1 << 22) /* Bit 22: End of injected sequence flag (slave ADC) */ -#define ADC_CSR_AWD1_SLV (1 << 23) /* Bit 23: Analog watchdog 1 flag (slave ADC) */ -#define ADC_CSR_AWD2_SLV (1 << 24) /* Bit 24: Analog watchdog 2 flag (slave ADC) */ -#define ADC_CSR_AWD3_SLV (1 << 25) /* Bit 25: Analog watchdog 3 flag (slave ADC) */ -#define ADC_CSR_JQOVF_SLV (1 << 26) /* Bit 26: Injected Context Queue Overflow flag (slave ADC) */ +#define ADC_CSR_ADRDY_MST (1 << 0) /* Bit 0: Master ADC ready */ +#define ADC_CSR_EOSMP_MST (1 << 1) /* Bit 1: End of Sampling phase flag (master ADC) */ +#define ADC_CSR_EOC_MST (1 << 2) /* Bit 2: End of regular conversion (master ADC) */ +#define ADC_CSR_EOS_MST (1 << 3) /* Bit 3: End of regular sequence flag (master ADC) */ +#define ADC_CSR_OVR_MST (1 << 4) /* Bit 4: Overrun flag (master ADC) */ +#define ADC_CSR_JEOC_MST (1 << 5) /* Bit 5: End of injected conversion flag (master ADC) */ +#define ADC_CSR_JEOS_MST (1 << 6) /* Bit 6: End of injected sequence flag (master ADC) */ +#define ADC_CSR_AWD1_MST (1 << 7) /* Bit 7: Analog watchdog 1 flag (master ADC) */ +#define ADC_CSR_AWD2_MST (1 << 8) /* Bit 8: Analog watchdog 2 flag (master ADC) */ +#define ADC_CSR_AWD3_MST (1 << 9) /* Bit 9: Analog watchdog 3 flag (master ADC) */ +#define ADC_CSR_JQOVF_MST (1 << 10) /* Bit 10: Injected Context Queue Overflow flag (master ADC) */ +#define ADC_CSR_ADRDY_SLV (1 << 16) /* Bit 16: Slave ADC ready */ +#define ADC_CSR_EOSMP_SLV (1 << 17) /* Bit 17: End of Sampling phase flag (slave ADC) */ +#define ADC_CSR_EOC_SLV (1 << 18) /* Bit 18: End of regular conversion (slave ADC) */ +#define ADC_CSR_EOS_SLV (1 << 19) /* Bit 19: End of regular sequence flag (slave ADC) */ +#define ADC_CSR_OVR_SLV (1 << 20) /* Bit 20: Overrun flag (slave ADC) */ +#define ADC_CSR_JEOC_SLV (1 << 21) /* Bit 21: End of injected conversion flag (slave ADC) */ +#define ADC_CSR_JEOS_SLV (1 << 22) /* Bit 22: End of injected sequence flag (slave ADC) */ +#define ADC_CSR_AWD1_SLV (1 << 23) /* Bit 23: Analog watchdog 1 flag (slave ADC) */ +#define ADC_CSR_AWD2_SLV (1 << 24) /* Bit 24: Analog watchdog 2 flag (slave ADC) */ +#define ADC_CSR_AWD3_SLV (1 << 25) /* Bit 25: Analog watchdog 3 flag (slave ADC) */ +#define ADC_CSR_JQOVF_SLV (1 << 26) /* Bit 26: Injected Context Queue Overflow flag (slave ADC) */ /* Common control register */ -#define ADC_CCR_DUAL_SHIFT (0) /* Bits 0-4: Dual ADC mode selection */ -#define ADC_CCR_DUAL_MASK (31 << ADC_CCR_DUAL_SHIFT) -# define ADC_CCR_DUAL_IND (0 << ADC_CCR_DUAL_SHIFT) /* Independent mode */ -# define ADC_CCR_DUAL_DUAL (1 << ADC_CCR_DUAL_SHIFT) /* Dual mode, master/slave ADCs together */ -# define ADC_CCR_DUAL_SIMINJ (1 << ADC_CCR_DUAL_SHIFT) /* Combined regular sim. + injected sim. */ -# define ADC_CCR_DUAL_SIMALT (2 << ADC_CCR_DUAL_SHIFT) /* Combined regular sim. + alternate trigger */ -# define ADC_CCR_DUAL_INJECTED (5 << ADC_CCR_DUAL_SHIFT) /* Injected simultaneous mode only */ -# define ADC_CCR_DUAL_SIM (6 << ADC_CCR_DUAL_SHIFT) /* Regular simultaneous mode only */ -# define ADC_CCR_DUAL_INTERLEAVE (7 << ADC_CCR_DUAL_SHIFT) /* Interleaved mode only */ -# define ADC_CCR_DUAL_ALT (9 << ADC_CCR_DUAL_SHIFT) /* Alternate trigger mode only */ -#define ADC_CCR_DELAY_SHIFT (8) /* Bits 8-11: Delay between 2 sampling phases */ -#define ADC_CCR_DELAY_MASK (15 << ADC_CCR_DELAY_SHIFT) -# define ADC_CCR_DELAY(n) (((n)-1) << ADC_CCR_DELAY_SHIFT) /* n * TADCCLK, 1-13 */ -#define ADC_CCR_DMACFG (1 << 13) /* Bit 13: DMA configuration (for dual ADC mode) */ -#define ADC_CCR_MDMA_SHIFT (14) /* Bits 14-15: Direct memory access mode for dual ADC mode */ -#define ADC_CCR_MDMA_MASK (3 << ADC_CCR_MDMA_SHIFT) -# define ADC_CCR_MDMA_DISABLE (0 << ADC_CCR_MDMA_SHIFT) /* MDMA mode disabled */ -# define ADC_CCR_MDMA_ 10_12 (2 << ADC_CCR_MDMA_SHIFT) /* MDMA mode enabled (12 / 10-bit) */ -# define ADC_CCR_MDMA_6_8 (3 << ADC_CCR_MDMA_SHIFT) /* MDMA mode enabled (8 / 6-bit) */ -#define ADC_CCR_CKMODE_SHIFT (16) /* Bits 16-17: ADC clock mode */ -#define ADC_CCR_CKMODE_MASK (15 << ADC_CCR_CKMODE_SHIFT) -# define ADC_CCR_CKMODE_ASYCH (0 << ADC_CCR_CKMODE_SHIFT) /* Asynchronous clock mode */ -# define ADC_CCR_CKMODE_SYNCH_DIV1 (1 << ADC_CCR_CKMODE_SHIFT) /* Synchronous clock mode divided by 1 */ -# define ADC_CCR_CKMODE_SYNCH_DIV2 (2 << ADC_CCR_CKMODE_SHIFT) /* Synchronous clock mode divided by 2 */ -# define ADC_CCR_CKMODE_SYNCH_DIV4 (3 << ADC_CCR_CKMODE_SHIFT) /* Synchronous clock mode divided by 4 */ -#define ADC_CCR_VREFEN (1 << 22) /* Bit 22: VREFINT enable */ -#define ADC_CCR_TSEN (1 << 23) /* Bit 23: Temperature sensor enable */ -#define ADC_CCR_VBATEN (1 << 24) /* Bit 22: VBAT enable */ +#define ADC_CCR_DUAL_SHIFT (0) /* Bits 0-4: Dual ADC mode selection */ +#define ADC_CCR_DUAL_MASK (31 << ADC_CCR_DUAL_SHIFT) +# define ADC_CCR_DUAL_IND (0 << ADC_CCR_DUAL_SHIFT) /* Independent mode */ +# define ADC_CCR_DUAL_DUAL (1 << ADC_CCR_DUAL_SHIFT) /* Dual mode, master/slave ADCs together */ +# define ADC_CCR_DUAL_SIMINJ (1 << ADC_CCR_DUAL_SHIFT) /* Combined regular sim. + injected sim. */ +# define ADC_CCR_DUAL_SIMALT (2 << ADC_CCR_DUAL_SHIFT) /* Combined regular sim. + alternate trigger */ +# define ADC_CCR_DUAL_INJECTED (5 << ADC_CCR_DUAL_SHIFT) /* Injected simultaneous mode only */ +# define ADC_CCR_DUAL_SIM (6 << ADC_CCR_DUAL_SHIFT) /* Regular simultaneous mode only */ +# define ADC_CCR_DUAL_INTERLEAVE (7 << ADC_CCR_DUAL_SHIFT) /* Interleaved mode only */ +# define ADC_CCR_DUAL_ALT (9 << ADC_CCR_DUAL_SHIFT) /* Alternate trigger mode only */ +#define ADC_CCR_DELAY_SHIFT (8) /* Bits 8-11: Delay between 2 sampling phases */ +#define ADC_CCR_DELAY_MASK (15 << ADC_CCR_DELAY_SHIFT) +# define ADC_CCR_DELAY(n) (((n)-1) << ADC_CCR_DELAY_SHIFT) /* n * TADCCLK, 1-13 */ +#define ADC_CCR_DMACFG (1 << 13) /* Bit 13: DMA configuration (for dual ADC mode) */ +#define ADC_CCR_MDMA_SHIFT (14) /* Bits 14-15: Direct memory access mode for dual ADC mode */ +#define ADC_CCR_MDMA_MASK (3 << ADC_CCR_MDMA_SHIFT) +# define ADC_CCR_MDMA_DISABLED (0 << ADC_CCR_MDMA_SHIFT) /* MDMA mode disabled */ +# define ADC_CCR_MDMA_10_12 (2 << ADC_CCR_MDMA_SHIFT) /* MDMA mode enabled (12 / 10-bit) */ +# define ADC_CCR_MDMA_6_8 (3 << ADC_CCR_MDMA_SHIFT) /* MDMA mode enabled (8 / 6-bit) */ +#define ADC_CCR_CKMODE_SHIFT (16) /* Bits 16-17: ADC clock mode */ +#define ADC_CCR_CKMODE_MASK (15 << ADC_CCR_CKMODE_SHIFT) +# define ADC_CCR_CKMODE_ASYNCH (0 << ADC_CCR_CKMODE_SHIFT) /* Asynchronous clock mode */ +# define ADC_CCR_CKMODE_SYNCH_DIV1 (1 << ADC_CCR_CKMODE_SHIFT) /* Synchronous clock mode divided by 1 */ +# define ADC_CCR_CKMODE_SYNCH_DIV2 (2 << ADC_CCR_CKMODE_SHIFT) /* Synchronous clock mode divided by 2 */ +# define ADC_CCR_CKMODE_SYNCH_DIV4 (3 << ADC_CCR_CKMODE_SHIFT) /* Synchronous clock mode divided by 4 */ +#define ADC_CCR_VREFEN (1 << 22) /* Bit 22: VREFINT enable */ +#define ADC_CCR_TSEN (1 << 23) /* Bit 23: Temperature sensor enable */ +#define ADC_CCR_VBATEN (1 << 24) /* Bit 22: VBAT enable */ /* Common regular data register for dual mode */ -#define ADC_CDR_RDATA_MST_SHIFT (0) /* Bits 0-15: Regular data of the master ADC */ -#define ADC_CDR_RDATA_MST_MASK (0xffff << ADC_CDR_RDATA_MST_SHIFT) -#define ADC_CDR_RDATA_SLV_SHIFT (16) /* Bits 16-31: Regular data of the slave ADC */ -#define ADC_CDR_RDATA_SLV_MASK (0xffff << ADC_CDR_RDATA_SLV_SHIFT) +#define ADC_CDR_RDATA_MST_SHIFT (0) /* Bits 0-15: Regular data of the master ADC */ +#define ADC_CDR_RDATA_MST_MASK (0xffff << ADC_CDR_RDATA_MST_SHIFT) +#define ADC_CDR_RDATA_SLV_SHIFT (16) /* Bits 16-31: Regular data of the slave ADC */ +#define ADC_CDR_RDATA_SLV_MASK (0xffff << ADC_CDR_RDATA_SLV_SHIFT) /**************************************************************************************************** * Public Types diff --git a/arch/arm/src/stm32/chip/stm32f30xxx_pinmap.h b/arch/arm/src/stm32/chip/stm32f30xxx_pinmap.h index a12151fd8f9..38ae3f0c368 100644 --- a/arch/arm/src/stm32/chip/stm32f30xxx_pinmap.h +++ b/arch/arm/src/stm32/chip/stm32f30xxx_pinmap.h @@ -68,6 +68,59 @@ * pins in this file. */ +/* ADC */ + +#define GPIO_ADC1_IN1 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN0) +#define GPIO_ADC1_IN2 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN1) +#define GPIO_ADC1_IN3 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN2) +#define GPIO_ADC1_IN4 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN3) +#define GPIO_ADC1_IN5 (GPIO_ANALOG|GPIO_PORTF|GPIO_PIN4) +#define GPIO_ADC1_IN11 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN0) +#define GPIO_ADC1_IN12 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN1) +#define GPIO_ADC1_IN13 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN13) + +#define GPIO_ADC2_IN1 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN4) +#define GPIO_ADC2_IN2 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN5) +#define GPIO_ADC2_IN3 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN6) +#define GPIO_ADC2_IN4 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN7) +#define GPIO_ADC2_IN5 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN4) +#define GPIO_ADC2_IN11 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN5) +#define GPIO_ADC2_IN12 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN2) +#define GPIO_ADC2_IN13 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN12) +#define GPIO_ADC2_IN14 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN14) +#define GPIO_ADC2_IN15 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN15) + +#define GPIO_ADC12_IN6 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN0) +#define GPIO_ADC12_IN7 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN1) +#define GPIO_ADC12_IN8 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN2) +#define GPIO_ADC12_IN9 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN3) +#define GPIO_ADC12_IN10 (GPIO_ANALOG|GPIO_PORTF|GPIO_PIN2) + +#define GPIO_ADC3_IN1 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN1) +#define GPIO_ADC3_IN2 (GPIO_ANALOG|GPIO_PORTE|GPIO_PIN9) +#define GPIO_ADC3_IN3 (GPIO_ANALOG|GPIO_PORTE|GPIO_PIN13) +#define GPIO_ADC3_IN5 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN13) +#define GPIO_ADC3_IN12 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN0) +#define GPIO_ADC3_IN13 (GPIO_ANALOG|GPIO_PORTE|GPIO_PIN7) +#define GPIO_ADC3_IN14 (GPIO_ANALOG|GPIO_PORTE|GPIO_PIN10) +#define GPIO_ADC3_IN15 (GPIO_ANALOG|GPIO_PORTE|GPIO_PIN11) +#define GPIO_ADC3_IN16 (GPIO_ANALOG|GPIO_PORTE|GPIO_PIN12) + +#define GPIO_ADC4_IN1 (GPIO_ANALOG|GPIO_PORTE|GPIO_PIN14) +#define GPIO_ADC4_IN2 (GPIO_ANALOG|GPIO_PORTE|GPIO_PIN15) +#define GPIO_ADC4_IN3 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN12) +#define GPIO_ADC4_IN4 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN14) +#define GPIO_ADC4_IN5 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN15) +#define GPIO_ADC4_IN12 (GPIO_ANALOG|GPIO_PORTD|GPIO_PIN8) +#define GPIO_ADC4_IN13 (GPIO_ANALOG|GPIO_PORTD|GPIO_PIN9) + +#define GPIO_ADC34_IN6 (GPIO_ANALOG|GPIO_PORTE|GPIO_PIN8) +#define GPIO_ADC34_IN7 (GPIO_ANALOG|GPIO_PORTD|GPIO_PIN10) +#define GPIO_ADC34_IN8 (GPIO_ANALOG|GPIO_PORTD|GPIO_PIN11) +#define GPIO_ADC34_IN9 (GPIO_ANALOG|GPIO_PORTD|GPIO_PIN12) +#define GPIO_ADC34_IN10 (GPIO_ANALOG|GPIO_PORTD|GPIO_PIN13) +#define GPIO_ADC34_IN11 (GPIO_ANALOG|GPIO_PORTD|GPIO_PIN14) + /* CAN */ #define GPIO_CAN_RX_1 (GPIO_ALT|GPIO_AF7|GPIO_SPEED_25MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN0) @@ -603,4 +656,3 @@ #define GPIO_PF10_EVENT_OUT (GPIO_ALT|GPIO_AF1|GPIO_PORTF|GPIO_PIN10) #endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F30XXX_PINMAP_H */ - diff --git a/arch/arm/src/stm32/stm32_adc.c b/arch/arm/src/stm32/stm32_adc.c index a2ad492f0da..514e707cf30 100644 --- a/arch/arm/src/stm32/stm32_adc.c +++ b/arch/arm/src/stm32/stm32_adc.c @@ -2,8 +2,10 @@ * arch/arm/src/stm32/stm32_adc.c * * Copyright (C) 2011, 2013, 2015 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * Diego Sanchez + * Copyright (C) 2015 Omni Hoverboards Inc. All rights reserved. + * Authors: Gregory Nutt + * Diego Sanchez + * Paul Alexander Patience * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -71,12 +73,13 @@ /* Some ADC peripheral must be enabled */ #if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || \ - defined(CONFIG_STM32_ADC3) + defined(CONFIG_STM32_ADC3) || defined(CONFIG_STM32_ADC4) /* This implementation is for the STM32 F1, F2, F4 and STM32L15XX only */ #if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F20XX) || \ - defined(CONFIG_STM32_STM32F40XX) || defined(CONFIG_STM32_STM32L15XX) + defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F40XX) || \ + defined(CONFIG_STM32_STM32L15XX) /* At the moment there is no proper implementation for timers external * trigger in STM32L15XX May be added latter @@ -89,21 +92,80 @@ /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ +/* RCC reset ****************************************************************/ + +#if defined(CONFIG_STM32_STM32F10XX) +# define STM32_RCC_RSTR STM32_RCC_APB2RSTR +# define RCC_RSTR_ADC1RST RCC_APB2RSTR_ADC1RST +# define RCC_RSTR_ADC2RST RCC_APB2RSTR_ADC2RST +# define RCC_RSTR_ADC3RST RCC_APB2RSTR_ADC3RST +# define RCC_RSTR_ADC4RST RCC_APB2RSTR_ADC4RST +#elif defined(CONFIG_STM32_STM32F30XX) +# define STM32_RCC_RSTR STM32_RCC_AHBRSTR +# define RCC_RSTR_ADC1RST RCC_AHBRSTR_ADC12RST +# define RCC_RSTR_ADC2RST RCC_AHBRSTR_ADC12RST +# define RCC_RSTR_ADC3RST RCC_AHBRSTR_ADC34RST +# define RCC_RSTR_ADC4RST RCC_AHBRSTR_ADC34RST +#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX) +# define STM32_RCC_RSTR STM32_RCC_APB2RSTR +# define RCC_RSTR_ADC1RST RCC_APB2RSTR_ADCRST +# define RCC_RSTR_ADC2RST RCC_APB2RSTR_ADCRST +# define RCC_RSTR_ADC3RST RCC_APB2RSTR_ADCRST +# define RCC_RSTR_ADC4RST RCC_APB2RSTR_ADCRST +#elif defined(CONFIG_STM32_STM32L15XX) +# define STM32_RCC_RSTR STM32_RCC_APB2RSTR +# define RCC_RSTR_ADC1RST RCC_APB2RSTR_ADC1RST +#endif + /* ADC interrupts ***********************************************************/ -#ifdef CONFIG_STM32_STM32F10XX -# define ADC_SR_ALLINTS (ADC_SR_AWD | ADC_SR_EOC | ADC_SR_JEOC) +#ifdef CONFIG_STM32_STM32F30XX +# define STM32_ADC_DMAREG_OFFSET STM32_ADC_CFGR_OFFSET +# define ADC_DMAREG_DMA ADC_CFGR_DMAEN +# define STM32_ADC_EXTREG_OFFSET STM32_ADC_CFGR_OFFSET +# define ADC_EXTREG_EXTSEL_MASK ADC_CFGR_EXTSEL_MASK +# define ADC_EXTREG_EXTEN_MASK ADC_CFGR_EXTEN_MASK +# define ADC_EXTREG_EXTEN_DEFAULT ADC_CFGR_EXTEN_RISING +# define ADC_ISR_EOC ADC_INT_EOC +# define ADC_IER_EOC ADC_INT_EOC +# define ADC_ISR_AWD ADC_INT_AWD1 +# define ADC_IER_AWD ADC_INT_AWD1 +# define ADC_ISR_JEOC ADC_INT_JEOC +# define ADC_IER_JEOC ADC_INT_JEOC +# define ADC_ISR_OVR ADC_INT_OVR +# define ADC_IER_OVR ADC_INT_OVR #else -# define ADC_SR_ALLINTS (ADC_SR_AWD | ADC_SR_EOC | ADC_SR_JEOC | \ - ADC_SR_OVR) +# define STM32_ADC_DMAREG_OFFSET STM32_ADC_CR2_OFFSET +# define ADC_DMAREG_DMA ADC_CR2_DMA +# define STM32_ADC_EXTREG_OFFSET STM32_ADC_CR2_OFFSET +# define ADC_EXTREG_EXTSEL_MASK ADC_CR2_EXTSEL_MASK +# define STM32_ADC_ISR_OFFSET STM32_ADC_SR_OFFSET +# define STM32_ADC_IER_OFFSET STM32_ADC_CR1_OFFSET +# define ADC_ISR_EOC ADC_SR_EOC +# define ADC_IER_EOC ADC_CR1_EOCIE +# define ADC_ISR_AWD ADC_SR_AWD +# define ADC_IER_AWD ADC_CR1_AWDIE +# define ADC_ISR_JEOC ADC_SR_JEOC +# define ADC_IER_JEOC ADC_CR1_JEOCIE +# ifdef CONFIG_STM32_STM32F10XX +# define ADC_EXTREG_EXTEN_MASK ADC_CR2_EXTTRIG +# define ADC_EXTREG_EXTEN_NONE 0 +# define ADC_EXTREG_EXTEN_DEFAULT ADC_CR2_EXTTRIG +# define ADC_ISR_OVR 0 +# define ADC_IER_OVR 0 +# else +# define ADC_EXTREG_EXTEN_MASK ADC_CR2_EXTEN_MASK +# define ADC_EXTREG_EXTEN_NONE ADC_CR2_EXTEN_NONE +# define ADC_EXTREG_EXTEN_DEFAULT ADC_CR2_EXTEN_RISING +# define ADC_ISR_OVR ADC_SR_OVR +# define ADC_IER_OVR ADC_CR1_OVRIE +# endif #endif -#ifdef CONFIG_STM32_STM32F10XX -# define ADC_CR1_ALLINTS (ADC_CR1_AWDIE | ADC_CR1_EOCIE | ADC_CR1_JEOCIE) -#else -# define ADC_CR1_ALLINTS (ADC_CR1_AWDIE | ADC_CR1_EOCIE | ADC_CR1_JEOCIE | \ - ADC_CR1_OVRIE) -#endif +#define ADC_ISR_ALLINTS (ADC_ISR_EOC | ADC_ISR_AWD | ADC_ISR_JEOC | \ + ADC_ISR_OVR) +#define ADC_IER_ALLINTS (ADC_IER_EOC | ADC_IER_AWD | ADC_IER_JEOC | \ + ADC_IER_OVR) /* ADC Channels/DMA ********************************************************/ /* The maximum number of channels that can be sampled. If DMA support is @@ -122,17 +184,70 @@ /* DMA channels and interface values differ for the F1 and F4 families */ -#if defined(CONFIG_STM32_STM32L15XX) -# define ADC_CHANNELS_NUMBER 32 -# define ADC_DEFAULT_SAMPLE 0x7 -#endif - -/* This can be refined or defined in Kconfig */ - -#ifndef CONFIG_ADC_TOTAL_CHANNELS -# define ADC_MAX_CHANNELS ADC_MAX_SAMPLES -#else -# define ADC_MAX_CHANNELS CONFIG_ADC_TOTAL_CHANNELS +#if defined(CONFIG_STM32_STM32F10XX) +# define ADC_SMPR_DEFAULT ADC_SMPR_55p5 +# define ADC_SMPR1_DEFAULT ((ADC_SMPR_DEFAULT << ADC_SMPR1_SMP10_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP11_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP12_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP13_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP14_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP15_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP16_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP17_SHIFT)) +# define ADC_SMPR2_DEFAULT ((ADC_SMPR_DEFAULT << ADC_SMPR2_SMP0_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP1_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP2_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP3_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP4_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP5_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP6_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP7_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP8_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP9_SHIFT)) +#elif defined(CONFIG_STM32_STM32F30XX) +# define ADC_SMPR_DEFAULT ADC_SMPR_61p5 +# define ADC_SMPR1_DEFAULT ((ADC_SMPR_DEFAULT << ADC_SMPR1_SMP1_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP2_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP3_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP4_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP5_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP6_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP7_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP8_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP9_SHIFT)) +# define ADC_SMPR2_DEFAULT ((ADC_SMPR_DEFAULT << ADC_SMPR2_SMP10_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP11_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP12_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP13_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP14_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP15_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP16_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP17_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP18_SHIFT)) +#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX) +# define ADC_SMPR_DEFAULT ADC_SMPR_112 +# define ADC_SMPR1_DEFAULT ((ADC_SMPR_DEFAULT << ADC_SMPR1_SMP10_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP11_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP12_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP13_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP14_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP15_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP16_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP17_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP18_SHIFT)) +# define ADC_SMPR2_DEFAULT ((ADC_SMPR_DEFAULT << ADC_SMPR2_SMP0_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP1_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP2_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP3_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP4_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP5_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP6_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP7_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP8_SHIFT) | \ + (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP9_SHIFT)) +#elif defined(CONFIG_STM32_STM32L15XX) +# define ADC_CHANNELS_NUMBER 32 +# define ADC_SMPR_DEFAULT ADC_SMPR_384 #endif /**************************************************************************** @@ -149,10 +264,10 @@ struct stm32_dev_s uint8_t intf; /* ADC interface number */ uint8_t current; /* Current ADC channel being converted */ #ifdef ADC_HAVE_DMA - uint8_t dmachan; /* DMA channel needed by this ADC */ - bool hasdma; /* True: This channel supports DMA */ + uint8_t dmachan; /* DMA channel needed by this ADC */ + bool hasdma; /* True: This channel supports DMA */ #endif -#if defined(CONFIG_STM32_STM32L15XX) +#ifdef CONFIG_STM32_STM32L15XX /* Sample time selection. These bits must be written only when ADON=0 */ uint8_t sample_rate[ADC_CHANNELS_NUMBER]; @@ -161,7 +276,7 @@ struct stm32_dev_s uint8_t trigger; /* Timer trigger channel: 0=CC1, 1=CC2, 2=CC3, * 3=CC4, 4=TRGO */ #endif - xcpt_t isr; /* Interrupt handler for this ADC block */ + xcpt_t isr; /* Interrupt handler for this ADC block */ uint32_t base; /* Base address of registers unique to this ADC * block */ #ifdef ADC_HAVE_TIMER @@ -189,31 +304,48 @@ struct stm32_dev_s /* ADC Register access */ -static uint32_t adc_getreg(struct stm32_dev_s *priv, int offset); -static void adc_putreg(struct stm32_dev_s *priv, int offset, uint32_t value); +#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || \ + defined(CONFIG_STM32_STM32F40XX) || defined(CONFIG_STM32_STM32L15XX) +static void stm32_modifyreg32(unsigned int addr, uint32_t clrbits, + uint32_t setbits); +#endif +static uint32_t adc_getreg(FAR struct stm32_dev_s *priv, int offset); +static void adc_putreg(FAR struct stm32_dev_s *priv, int offset, + uint32_t value); +static void adc_modifyreg(FAR struct stm32_dev_s *priv, int offset, + uint32_t clrbits, uint32_t setbits); #ifdef ADC_HAVE_TIMER -static uint16_t tim_getreg(struct stm32_dev_s *priv, int offset); -static void tim_putreg(struct stm32_dev_s *priv, int offset, uint16_t value); -static void adc_tim_dumpregs(struct stm32_dev_s *priv, FAR const char *msg); +static uint16_t tim_getreg(FAR struct stm32_dev_s *priv, int offset); +static void tim_putreg(FAR struct stm32_dev_s *priv, int offset, + uint16_t value); +static void tim_modifyreg(FAR struct stm32_dev_s *priv, int offset, + uint16_t clrbits, uint16_t setbits); +static void tim_dumpregs(FAR struct stm32_dev_s *priv, + FAR const char *msg); #endif -static void adc_rccreset(struct stm32_dev_s *priv, bool reset); +static void adc_rccreset(FAR struct stm32_dev_s *priv, bool reset); /* ADC Interrupt Handler */ static int adc_interrupt(FAR struct adc_dev_s *dev); -#if defined(CONFIG_STM32_STM32F10XX) && (defined(CONFIG_STM32_ADC1) || \ - defined(CONFIG_STM32_ADC2)) -static int adc12_interrupt(int irq, void *context); +#ifdef CONFIG_STM32_STM32L15XX +static int adc1_interrupt(int irq, FAR void *context); #endif -#if defined(CONFIG_STM32_STM32F10XX) && defined (CONFIG_STM32_ADC3) -static int adc3_interrupt(int irq, void *context); +#if (defined(CONFIG_STM32_STM32F10XX) || \ + defined(CONFIG_STM32_STM32F30XX)) && \ + (defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2)) +static int adc12_interrupt(int irq, FAR void *context); +#endif +#if (defined(CONFIG_STM32_STM32F10XX) || \ + defined(CONFIG_STM32_STM32F30XX)) && defined(CONFIG_STM32_ADC3) +static int adc3_interrupt(int irq, FAR void *context); +#endif +#if defined(CONFIG_STM32_STM32F30XX) && defined(CONFIG_STM32_ADC4) +static int adc4_interrupt(int irq, FAR void *context); #endif #if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX) -static int adc123_interrupt(int irq, void *context); -#endif -#ifdef CONFIG_STM32_STM32L15XX -static int adc_stm32l_interrupt(int irq, void *context); +static int adc123_interrupt(int irq, FAR void *context); #endif /* ADC Driver Methods */ @@ -224,24 +356,26 @@ static void adc_shutdown(FAR struct adc_dev_s *dev); static void adc_rxint(FAR struct adc_dev_s *dev, bool enable); static int adc_ioctl(FAR struct adc_dev_s *dev, int cmd, unsigned long arg); static void adc_enable(FAR struct stm32_dev_s *priv, bool enable); -static int adc_set_ch(FAR struct adc_dev_s *dev, uint8_t ch); -static int adc_set_ch_idx(FAR struct adc_dev_s *dev, uint8_t idx); + +static uint32_t adc_sqrbits(FAR struct stm32_dev_s *priv, int first, int last, + int offset); +static int adc_set_ch(FAR struct adc_dev_s *dev, uint8_t ch); + #ifdef CONFIG_STM32_STM32L15XX - static void adc_power_down_idle(FAR struct stm32_dev_s *priv, - bool pdi_high); - static void adc_power_down_delay(FAR struct stm32_dev_s *priv, - bool pdd_high); - static void adc_dels_after_conversion(FAR struct stm32_dev_s *priv, - uint32_t delay); - static void adc_select_ch_bank(FAR struct stm32_dev_s *priv, - bool chb_selected); - static int adc_ioc_change_ints(FAR struct adc_dev_s *dev, int cmd, - bool arg); +static void adc_power_down_idle(FAR struct stm32_dev_s *priv, + bool pdi_high); +static void adc_power_down_delay(FAR struct stm32_dev_s *priv, + bool pdd_high); +static void adc_dels_after_conversion(FAR struct stm32_dev_s *priv, + uint32_t delay); +static void adc_select_ch_bank(FAR struct stm32_dev_s *priv, + bool chb_selected); +static int adc_ioc_change_ints(FAR struct adc_dev_s *dev, int cmd, + bool arg); +#if STM32_CFGR_PLLSRC != 0 || STM32_SYSCLK_SW != RCC_CFGR_SW_HSI +static void adc_enable_hsi(bool enable); +static void adc_reset_hsi_disable(FAR struct adc_dev_s *dev); #endif -#if defined(CONFIG_STM32_STM32L15XX) && ((STM32_CFGR_PLLSRC != 0) || \ - (STM32_SYSCLK_SW != RCC_CFGR_SW_HSI)) - static void adc_enable_hsi(bool enable); - static void adc_reset_hsi_disable(FAR struct adc_dev_s *dev); #endif #ifdef ADC_HAVE_TIMER @@ -249,11 +383,13 @@ static void adc_timstart(FAR struct stm32_dev_s *priv, bool enable); static int adc_timinit(FAR struct stm32_dev_s *priv); #endif -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX) || \ - defined(CONFIG_STM32_STM32L15XX) -static void adc_startconv(FAR struct stm32_dev_s *priv, bool enable); +#ifdef ADC_HAVE_DMA +static void adc_dmaconvcallback(DMA_HANDLE handle, uint8_t isr, + FAR void *arg); #endif +static void adc_startconv(FAR struct stm32_dev_s *priv, bool enable); + /**************************************************************************** * Private Data ****************************************************************************/ @@ -262,8 +398,8 @@ static void adc_startconv(FAR struct stm32_dev_s *priv, bool enable); static const struct adc_ops_s g_adcops = { -#if defined(CONFIG_STM32_STM32L15XX) && ((STM32_CFGR_PLLSRC != 0) || \ - (STM32_SYSCLK_SW != RCC_CFGR_SW_HSI)) +#if defined(CONFIG_STM32_STM32L15XX) && \ + (STM32_CFGR_PLLSRC != 0 || STM32_SYSCLK_SW != RCC_CFGR_SW_HSI) .ao_reset = adc_reset_hsi_disable, #else .ao_reset = adc_reset, @@ -279,23 +415,18 @@ static const struct adc_ops_s g_adcops = #ifdef CONFIG_STM32_ADC1 static struct stm32_dev_s g_adcpriv1 = { -#ifdef CONFIG_STM32_STM32F10XX +#if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX) .irq = STM32_IRQ_ADC12, .isr = adc12_interrupt, #elif defined(CONFIG_STM32_STM32L15XX) .irq = STM32_IRQ_ADC1, - .isr = adc_stm32l_interrupt, + .isr = adc1_interrupt, #else .irq = STM32_IRQ_ADC, .isr = adc123_interrupt, #endif .intf = 1, -#ifndef CONFIG_STM32_STM32L15XX .base = STM32_ADC1_BASE, -#else - .base = STM32_ADC_BASE, -#endif - #ifdef ADC1_HAVE_TIMER .trigger = CONFIG_STM32_ADC1_TIMTRIG, .tbase = ADC1_TIMER_BASE, @@ -321,7 +452,7 @@ static struct adc_dev_s g_adcdev1 = #ifdef CONFIG_STM32_ADC2 static struct stm32_dev_s g_adcpriv2 = { -#ifdef CONFIG_STM32_STM32F10XX +#if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX) .irq = STM32_IRQ_ADC12, .isr = adc12_interrupt, #else @@ -355,7 +486,7 @@ static struct adc_dev_s g_adcdev2 = #ifdef CONFIG_STM32_ADC3 static struct stm32_dev_s g_adcpriv3 = { -#ifdef CONFIG_STM32_STM32F10XX +#if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX) .irq = STM32_IRQ_ADC3, .isr = adc3_interrupt, #else @@ -387,7 +518,30 @@ static struct adc_dev_s g_adcdev3 = /* ADC4 state */ #ifdef CONFIG_STM32_ADC4 -# error Missing ADC4 implementation +static struct stm32_dev_s g_adcpriv4 = +{ + .irq = STM32_IRQ_ADC4, + .isr = adc4_interrupt, + .intf = 4, + .base = STM32_ADC4_BASE, +#ifdef ADC4_HAVE_TIMER + .trigger = CONFIG_STM32_ADC4_TIMTRIG, + .tbase = ADC4_TIMER_BASE, + .extsel = ADC4_EXTSEL_VALUE, + .pclck = ADC4_TIMER_PCLK_FREQUENCY, + .freq = CONFIG_STM32_ADC4_SAMPLE_FREQUENCY, +#endif +#ifdef ADC4_HAVE_DMA + .dmachan = ADC4_DMA_CHAN, + .hasdma = true, +#endif +}; + +static struct adc_dev_s g_adcdev4 = +{ + .ad_ops = &g_adcops, + .ad_priv = &g_adcpriv4, +}; #endif /**************************************************************************** @@ -395,23 +549,29 @@ static struct adc_dev_s g_adcdev3 = ****************************************************************************/ /**************************************************************************** - * Name: adc_getreg + * Name: stm32_modifyreg32 * * Description: - * Read the value of an ADC register. + * Modify the value of a 32-bit register (not atomic). * * Input Parameters: - * priv - A reference to the ADC block status - * offset - The offset to the register to read + * addr - The address of the register + * clrbits - The bits to clear + * setbits - The bits to set * * Returned Value: + * None * ****************************************************************************/ -static uint32_t adc_getreg(struct stm32_dev_s *priv, int offset) +#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || \ + defined(CONFIG_STM32_STM32F40XX) || defined(CONFIG_STM32_STM32L15XX) +static void stm32_modifyreg32(unsigned int addr, uint32_t clrbits, + uint32_t setbits) { - return getreg32(priv->base + offset); + putreg32((getreg32(addr) & ~clrbits) | setbits, addr); } +#endif /**************************************************************************** * Name: adc_getreg @@ -420,18 +580,64 @@ static uint32_t adc_getreg(struct stm32_dev_s *priv, int offset) * Read the value of an ADC register. * * Input Parameters: - * priv - A reference to the ADC block status + * priv - A reference to the ADC block status * offset - The offset to the register to read * * Returned Value: + * The current contents of the specified register * ****************************************************************************/ -static void adc_putreg(struct stm32_dev_s *priv, int offset, uint32_t value) +static uint32_t adc_getreg(FAR struct stm32_dev_s *priv, int offset) +{ + return getreg32(priv->base + offset); +} + +/**************************************************************************** + * Name: adc_putreg + * + * Description: + * Write a value to an ADC register. + * + * Input Parameters: + * priv - A reference to the ADC block status + * offset - The offset to the register to write to + * value - The value to write to the register + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void adc_putreg(FAR struct stm32_dev_s *priv, int offset, + uint32_t value) { putreg32(value, priv->base + offset); } +/**************************************************************************** + * Name: adc_modifyreg + * + * Description: + * Modify the value of an ADC register (not atomic). + * + * Input Parameters: + * priv - A reference to the ADC block status + * offset - The offset to the register to modify + * clrbits - The bits to clear + * setbits - The bits to set + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void adc_modifyreg(FAR struct stm32_dev_s *priv, int offset, + uint32_t clrbits, uint32_t setbits) +{ + adc_putreg(priv, offset, (adc_getreg(priv, offset) & ~clrbits) | setbits); +} + /**************************************************************************** * Name: tim_getreg * @@ -439,7 +645,7 @@ static void adc_putreg(struct stm32_dev_s *priv, int offset, uint32_t value) * Read the value of an ADC timer register. * * Input Parameters: - * priv - A reference to the ADC block status + * priv - A reference to the ADC block status * offset - The offset to the register to read * * Returned Value: @@ -448,7 +654,7 @@ static void adc_putreg(struct stm32_dev_s *priv, int offset, uint32_t value) ****************************************************************************/ #ifdef ADC_HAVE_TIMER -static uint16_t tim_getreg(struct stm32_dev_s *priv, int offset) +static uint16_t tim_getreg(FAR struct stm32_dev_s *priv, int offset) { return getreg16(priv->tbase + offset); } @@ -458,11 +664,12 @@ static uint16_t tim_getreg(struct stm32_dev_s *priv, int offset) * Name: tim_putreg * * Description: - * Read the value of an ADC timer register. + * Write a value to an ADC timer register. * * Input Parameters: - * priv - A reference to the ADC block status - * offset - The offset to the register to read + * priv - A reference to the ADC block status + * offset - The offset to the register to write to + * value - The value to write to the register * * Returned Value: * None @@ -470,14 +677,40 @@ static uint16_t tim_getreg(struct stm32_dev_s *priv, int offset) ****************************************************************************/ #ifdef ADC_HAVE_TIMER -static void tim_putreg(struct stm32_dev_s *priv, int offset, uint16_t value) +static void tim_putreg(FAR struct stm32_dev_s *priv, int offset, + uint16_t value) { putreg16(value, priv->tbase + offset); } #endif /**************************************************************************** - * Name: adc_tim_dumpregs + * Name: tim_modifyreg + * + * Description: + * Modify the value of an ADC timer register (not atomic). + * + * Input Parameters: + * priv - A reference to the ADC block status + * offset - The offset to the register to modify + * clrbits - The bits to clear + * setbits - The bits to set + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef ADC_HAVE_TIMER +static void tim_modifyreg(FAR struct stm32_dev_s *priv, int offset, + uint16_t clrbits, uint16_t setbits) +{ + tim_putreg(priv, offset, (tim_getreg(priv, offset) & ~clrbits) | setbits); +} +#endif + +/**************************************************************************** + * Name: tim_dumpregs * * Description: * Dump all timer registers. @@ -491,9 +724,8 @@ static void tim_putreg(struct stm32_dev_s *priv, int offset, uint16_t value) ****************************************************************************/ #ifdef ADC_HAVE_TIMER -static void adc_tim_dumpregs(struct stm32_dev_s *priv, FAR const char *msg) +static void tim_dumpregs(FAR struct stm32_dev_s *priv, FAR const char *msg) { -#if defined(CONFIG_DEBUG_ANALOG) && defined(CONFIG_DEBUG_VERBOSE) avdbg("%s:\n", msg); avdbg(" CR1: %04x CR2: %04x SMCR: %04x DIER: %04x\n", tim_getreg(priv, STM32_GTIM_CR1_OFFSET), @@ -514,7 +746,7 @@ static void adc_tim_dumpregs(struct stm32_dev_s *priv, FAR const char *msg) tim_getreg(priv, STM32_GTIM_CCR2_OFFSET), tim_getreg(priv, STM32_GTIM_CCR3_OFFSET), tim_getreg(priv, STM32_GTIM_CCR4_OFFSET)); -# ifndef CONFIG_STM32_STM32L15XX +#ifndef CONFIG_STM32_STM32L15XX if (priv->tbase == STM32_TIM1_BASE || priv->tbase == STM32_TIM8_BASE) { avdbg(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n", @@ -529,7 +761,6 @@ static void adc_tim_dumpregs(struct stm32_dev_s *priv, FAR const char *msg) tim_getreg(priv, STM32_GTIM_DCR_OFFSET), tim_getreg(priv, STM32_GTIM_DMAR_OFFSET)); } -# endif #endif } #endif @@ -549,28 +780,22 @@ static void adc_tim_dumpregs(struct stm32_dev_s *priv, FAR const char *msg) ****************************************************************************/ #ifdef ADC_HAVE_TIMER -static void adc_timstart(struct stm32_dev_s *priv, bool enable) +static void adc_timstart(FAR struct stm32_dev_s *priv, bool enable) { - uint16_t regval; - - avdbg("enable: %d\n", enable); - regval = tim_getreg(priv, STM32_GTIM_CR1_OFFSET); + avdbg("enable: %d\n", enable ? 1 : 0); if (enable) { /* Start the counter */ - regval |= ATIM_CR1_CEN; + tim_modifyreg(priv, STM32_GTIM_CR1_OFFSET, 0, GTIM_CR1_CEN); } - else { /* Disable the counter */ - regval &= ~ATIM_CR1_CEN; + tim_modifyreg(priv, STM32_GTIM_CR1_OFFSET, GTIM_CR1_CEN, 0); } - - tim_putreg(priv, STM32_GTIM_CR1_OFFSET, regval); } #endif @@ -578,8 +803,8 @@ static void adc_timstart(struct stm32_dev_s *priv, bool enable) * Name: adc_timinit * * Description: - * Initialize the timer that drivers the ADC sampling for this channel using - * the pre-calculated timer divider definitions. + * Initialize the timer that drivers the ADC sampling for this channel + * using the pre-calculated timer divider definitions. * * Input Parameters: * priv - A reference to the ADC block status @@ -597,6 +822,8 @@ static int adc_timinit(FAR struct stm32_dev_s *priv) uint32_t regval; uint32_t timclk; + uint16_t clrbits = 0; + uint16_t setbits = 0; uint16_t cr1; uint16_t cr2; uint16_t ccmr1; @@ -607,45 +834,30 @@ static int adc_timinit(FAR struct stm32_dev_s *priv) uint16_t ccer; uint16_t egr; - avdbg("Initializing timers extsel = 0x%08X\n", priv->extsel); - /* If the timer base address is zero, then this ADC was not configured to * use a timer. */ - regval = adc_getreg(priv, STM32_ADC_CR2_OFFSET); - -#ifdef CONFIG_STM32_STM32F10XX - if (!priv->tbase) + if (priv->tbase == 0) { - /* Configure the ADC to use the selected timer and timer channel as - * the trigger EXTTRIG: External Trigger Conversion mode for regular - * channels DISABLE - */ - - regval &= ~ADC_CR2_EXTTRIG; - adc_putreg(priv, STM32_ADC_CR2_OFFSET, regval); - return OK; + return ERROR; } - else - { - regval |= ADC_CR2_EXTTRIG; - } -#endif /* EXTSEL selection: These bits select the external event used to trigger * the start of conversion of a regular group. NOTE: * * - The position with of the EXTSEL field varies from one STM32 MCU * to another. - * - The width of the EXTSEL field varies from one STM3 MCU to another. + * - The width of the EXTSEL field varies from one STM32 MCU to another. * - The value in priv->extsel is already shifted into the correct bit * position. */ - regval &= ~ADC_CR2_EXTSEL_MASK; - regval |= priv->extsel; - adc_putreg(priv, STM32_ADC_CR2_OFFSET, regval); + avdbg("Initializing timers extsel = 0x%08x\n", priv->extsel); + + adc_modifyreg(priv, STM32_ADC_EXTREG_OFFSET, + ADC_EXTREG_EXTEN_MASK | ADC_EXTREG_EXTSEL_MASK, + ADC_EXTREG_EXTEN_DEFAULT | priv->extsel); /* Configure the timer channel to drive the ADC */ @@ -700,28 +912,24 @@ static int adc_timinit(FAR struct stm32_dev_s *priv) reload = 65535; } - /* Set up the timer CR1 register */ - - cr1 = tim_getreg(priv, STM32_GTIM_CR1_OFFSET); - /* Disable the timer until we get it configured */ adc_timstart(priv, false); - /* Select the Counter Mode == count up: + /* Set up the timer CR1 register. + * + * Select the Counter Mode == count up: * * ATIM_CR1_EDGE: The counter counts up or down depending on the * direction bit(DIR). * ATIM_CR1_DIR: 0: count up, 1: count down + * + * Set the clock division to zero for all */ - cr1 &= ~(ATIM_CR1_DIR | ATIM_CR1_CMS_MASK); - cr1 |= ATIM_CR1_EDGE; - - /* Set the clock division to zero for all */ - - cr1 &= ~GTIM_CR1_CKD_MASK; - tim_putreg(priv, STM32_GTIM_CR1_OFFSET, cr1); + clrbits = GTIM_CR1_DIR | GTIM_CR1_CMS_MASK | GTIM_CR1_CKD_MASK; + setbits = GTIM_CR1_EDGE; + tim_modifyreg(priv, STM32_GTIM_CR1_OFFSET, clrbits, setbits); /* Set the reload and prescaler values */ @@ -740,14 +948,14 @@ static int adc_timinit(FAR struct stm32_dev_s *priv) /* TIMx event generation: Bit 0 UG: Update generation */ - tim_putreg(priv, STM32_GTIM_EGR_OFFSET, ATIM_EGR_UG); + tim_putreg(priv, STM32_GTIM_EGR_OFFSET, GTIM_EGR_UG); /* Handle channel specific setup */ ocmode1 = 0; ocmode2 = 0; - switch (priv->trigger) + switch (priv->trigger) { case 0: /* TimerX CC1 event */ { @@ -760,7 +968,9 @@ static int adc_timinit(FAR struct stm32_dev_s *priv) egr = ATIM_EGR_CC1G; - /* Set the duty cycle by writing to the CCR register for this channel */ + /* Set the duty cycle by writing to the CCR register for this + * channel + */ tim_putreg(priv, STM32_GTIM_CCR1_OFFSET, (uint16_t)(reload >> 1)); } @@ -777,7 +987,9 @@ static int adc_timinit(FAR struct stm32_dev_s *priv) egr = ATIM_EGR_CC2G; - /* Set the duty cycle by writing to the CCR register for this channel */ + /* Set the duty cycle by writing to the CCR register for this + * channel + */ tim_putreg(priv, STM32_GTIM_CCR2_OFFSET, (uint16_t)(reload >> 1)); } @@ -794,7 +1006,9 @@ static int adc_timinit(FAR struct stm32_dev_s *priv) egr = ATIM_EGR_CC3G; - /* Set the duty cycle by writing to the CCR register for this channel */ + /* Set the duty cycle by writing to the CCR register for this + * channel + */ tim_putreg(priv, STM32_GTIM_CCR3_OFFSET, (uint16_t)(reload >> 1)); } @@ -811,7 +1025,9 @@ static int adc_timinit(FAR struct stm32_dev_s *priv) egr = ATIM_EGR_CC4G; - /* Set the duty cycle by writing to the CCR register for this channel */ + /* Set the duty cycle by writing to the CCR register for this + * channel + */ tim_putreg(priv, STM32_GTIM_CCR4_OFFSET, (uint16_t)(reload >> 1)); } @@ -825,7 +1041,9 @@ static int adc_timinit(FAR struct stm32_dev_s *priv) ccenable = 0; egr = GTIM_EGR_TG; - /* Set the duty cycle by writing to the CCR register for this channel */ + /* Set the duty cycle by writing to the CCR register for this + * channel + */ tim_putreg(priv, STM32_GTIM_CCR4_OFFSET, (uint16_t)(reload >> 1)); } @@ -848,7 +1066,9 @@ static int adc_timinit(FAR struct stm32_dev_s *priv) ccmr1 = tim_getreg(priv, STM32_GTIM_CCMR1_OFFSET); ccmr2 = tim_getreg(priv, STM32_GTIM_CCMR2_OFFSET); - /* Reset the Output Compare Mode Bits and set the select output compare mode */ + /* Reset the Output Compare Mode Bits and set the select output compare + * mode + */ ccmr1 &= ~(ATIM_CCMR1_CC1S_MASK | ATIM_CCMR1_OC1M_MASK | ATIM_CCMR1_OC1PE | ATIM_CCMR1_CC2S_MASK | ATIM_CCMR1_OC2M_MASK | ATIM_CCMR1_OC2PE); @@ -857,41 +1077,54 @@ static int adc_timinit(FAR struct stm32_dev_s *priv) ccmr1 |= ocmode1; ccmr2 |= ocmode2; - /* Reset the output polarity level of all channels (selects high polarity) */ + /* Reset the output polarity level of all channels (selects high + * polarity) + */ - ccer &= ~(ATIM_CCER_CC1P | ATIM_CCER_CC2P | ATIM_CCER_CC3P | ATIM_CCER_CC4P); + ccer &= ~(ATIM_CCER_CC1P | ATIM_CCER_CC2P | + ATIM_CCER_CC3P | ATIM_CCER_CC4P); /* Enable the output state of the selected channel (only) */ - ccer &= ~(ATIM_CCER_CC1E | ATIM_CCER_CC2E | ATIM_CCER_CC3E | ATIM_CCER_CC4E); + ccer &= ~(ATIM_CCER_CC1E | ATIM_CCER_CC2E | + ATIM_CCER_CC3E | ATIM_CCER_CC4E); ccer |= ccenable; #ifndef CONFIG_STM32_STM32L15XX - if (priv->tbase == STM32_TIM1_BASE || priv->tbase == STM32_TIM8_BASE) - { - /* Reset output N polarity level, output N state, output compare state, - * output compare N idle state. - */ + if (priv->tbase == STM32_TIM1_BASE || priv->tbase == STM32_TIM8_BASE) + { + /* Reset output N polarity level, output N state, output compare state, + * output compare N idle state. + */ -# if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX) - ccer &= ~(ATIM_CCER_CC1NE | ATIM_CCER_CC1NP | ATIM_CCER_CC2NE | ATIM_CCER_CC2NP | - ATIM_CCER_CC3NE | ATIM_CCER_CC3NP | ATIM_CCER_CC4NP); +# if defined(CONFIG_STM32_STM32F20XX) || \ + defined(CONFIG_STM32_STM32F30XX) || \ + defined(CONFIG_STM32_STM32F40XX) + ccer &= ~(ATIM_CCER_CC1NE | ATIM_CCER_CC1NP | + ATIM_CCER_CC2NE | ATIM_CCER_CC2NP | + ATIM_CCER_CC3NE | ATIM_CCER_CC3NP | + ATIM_CCER_CC4NP); # else - ccer &= ~(ATIM_CCER_CC1NE | ATIM_CCER_CC1NP | ATIM_CCER_CC2NE | ATIM_CCER_CC2NP | - ATIM_CCER_CC3NE | ATIM_CCER_CC3NP); + ccer &= ~(ATIM_CCER_CC1NE | ATIM_CCER_CC1NP | + ATIM_CCER_CC2NE | ATIM_CCER_CC2NP | + ATIM_CCER_CC3NE | ATIM_CCER_CC3NP); # endif - /* Reset the output compare and output compare N IDLE State */ + /* Reset the output compare and output compare N IDLE State */ - cr2 &= ~(ATIM_CR2_OIS1 | ATIM_CR2_OIS1N | ATIM_CR2_OIS2 | ATIM_CR2_OIS2N | - ATIM_CR2_OIS3 | ATIM_CR2_OIS3N | ATIM_CR2_OIS4); - } -# if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX) - else - { - ccer &= ~(GTIM_CCER_CC1NP | GTIM_CCER_CC2NP | GTIM_CCER_CC3NP); - } + cr2 &= ~(ATIM_CR2_OIS1 | ATIM_CR2_OIS1N | + ATIM_CR2_OIS2 | ATIM_CR2_OIS2N | + ATIM_CR2_OIS3 | ATIM_CR2_OIS3N | + ATIM_CR2_OIS4); + } +# if defined(CONFIG_STM32_STM32F20XX) || \ + defined(CONFIG_STM32_STM32F30XX) || \ + defined(CONFIG_STM32_STM32F40XX) + else + { + ccer &= ~(GTIM_CCER_CC1NP | GTIM_CCER_CC2NP | GTIM_CCER_CC3NP); + } # endif #else @@ -905,8 +1138,11 @@ static int adc_timinit(FAR struct stm32_dev_s *priv) /* Reset output N polarity level, output N state, output compare state, * output compare N idle state. */ - ccer &= ~(ATIM_CCER_CC1NE | ATIM_CCER_CC1NP | ATIM_CCER_CC2NE | ATIM_CCER_CC2NP | - ATIM_CCER_CC3NE | ATIM_CCER_CC3NP | ATIM_CCER_CC4NP); + + ccer &= ~(ATIM_CCER_CC1NE | ATIM_CCER_CC1NP | + ATIM_CCER_CC2NE | ATIM_CCER_CC2NP | + ATIM_CCER_CC3NE | ATIM_CCER_CC3NP | + ATIM_CCER_CC4NP); } #endif @@ -920,17 +1156,13 @@ static int adc_timinit(FAR struct stm32_dev_s *priv) /* Set the ARR Preload Bit */ - cr1 = tim_getreg(priv, STM32_GTIM_CR1_OFFSET); - cr1 |= GTIM_CR1_ARPE; - tim_putreg(priv, STM32_GTIM_CR1_OFFSET, cr1); + tim_modifyreg(priv, STM32_GTIM_CR1_OFFSET, 0, GTIM_CR1_ARPE); - /* Enable the timer counter - * All but the CEN bit with the default config in CR1 - */ + /* Enable the timer counter */ adc_timstart(priv, true); - adc_tim_dumpregs(priv, "After starting Timers"); + tim_dumpregs(priv, "After starting timers"); return OK; } @@ -940,7 +1172,7 @@ static int adc_timinit(FAR struct stm32_dev_s *priv) * Name: adc_startconv * * Description: - * Start (or stop) the ADC conversion process in DMA mode + * Start (or stop) the ADC conversion process * * Input Parameters: * priv - A reference to the ADC block status @@ -950,46 +1182,74 @@ static int adc_timinit(FAR struct stm32_dev_s *priv) * ****************************************************************************/ -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX) || \ - defined(CONFIG_STM32_STM32L15XX) -static void adc_startconv(struct stm32_dev_s *priv, bool enable) +#if defined(CONFIG_STM32_STM32F10XX) +static void adc_startconv(FAR struct stm32_dev_s *priv, bool enable) +{ + avdbg("enable: %d\n", enable ? 1 : 0); + + if (!enable) + { + /* Clear ADON to stop the conversion and put the ADC in the + * power down state. + */ + + adc_enable(priv, false); + } + + /* If the ADC is already on, set ADON again to start the conversion. + * Otherwise, set ADON once to wake up the ADC from the power down state. + */ + + adc_enable(priv, true); +} +#elif defined(CONFIG_STM32_STM32F30XX) +static void adc_startconv(FAR struct stm32_dev_s *priv, bool enable) { uint32_t regval; - avdbg("enable: %d\n", enable); - - regval = adc_getreg(priv, STM32_ADC_CR2_OFFSET); + avdbg("enable: %d\n", enable ? 1 : 0); if (enable) { -#ifdef CONFIG_ADC_CONTINUOUS + /* Start the conversion of regular channels */ - /* Set continuous mode */ - - regval |= ADC_CR2_CONT; - -#endif - - /* Start conversion of regular channels */ - - regval |= ADC_CR2_SWSTART; + adc_modifyreg(priv, STM32_ADC_CR_OFFSET, 0, ADC_CR_ADSTART); } else { -#ifdef CONFIG_ADC_CONTINUOUS + regval = adc_getreg(priv, STM32_ADC_CR_OFFSET); - /* Disable the continuous conversion */ + /* Is a conversion ongoing? */ - regval &= ~ADC_CR2_CONT; + if ((regval & ADC_CR_ADSTART) != 0) + { + /* Stop the conversion */ -#endif + adc_putreg(priv, STM32_ADC_CR_OFFSET, regval | ADC_CR_ADSTP); - /* Disable the conversion of regular channels */ + /* Wait for the conversion to stop */ - regval &= ~ADC_CR2_SWSTART; + while ((adc_getreg(priv, STM32_ADC_CR_OFFSET) & ADC_CR_ADSTP) != 0); + } } +} +#else +static void adc_startconv(FAR struct stm32_dev_s *priv, bool enable) +{ + avdbg("enable: %d\n", enable ? 1 : 0); - adc_putreg(priv, STM32_ADC_CR2_OFFSET, regval); + if (enable) + { + /* Start the conversion of regular channels */ + + adc_modifyreg(priv, STM32_ADC_CR2_OFFSET, 0, ADC_CR2_SWSTART); + } + else + { + /* Stop the conversion */ + + adc_modifyreg(priv, STM32_ADC_CR2_OFFSET, ADC_CR2_SWSTART, 0); + } } #endif @@ -1008,73 +1268,59 @@ static void adc_startconv(struct stm32_dev_s *priv, bool enable) * ****************************************************************************/ -static void adc_rccreset(struct stm32_dev_s *priv, bool reset) +static void adc_rccreset(FAR struct stm32_dev_s *priv, bool reset) { - irqstate_t flags; - uint32_t regval; uint32_t adcbit; - /* Pick the appropriate bit in the APB2 reset register */ - -#ifdef CONFIG_STM32_STM32F10XX - /* For the STM32 F1, there is an individual bit to reset each ADC. */ + /* Pick the appropriate bit in the APB2 reset register. + * For the STM32 F1, there is an individual bit to reset each ADC, + * but for the STM32 F2/F4, there is one common reset for all ADCs. + * THIS will probably cause some problems! + */ switch (priv->intf) { #ifdef CONFIG_STM32_ADC1 case 1: - adcbit = RCC_APB2RSTR_ADC1RST; + adcbit = RCC_RSTR_ADC1RST; break; #endif #ifdef CONFIG_STM32_ADC2 case 2: - adcbit = RCC_APB2RSTR_ADC2RST; + adcbit = RCC_RSTR_ADC2RST; break; #endif #ifdef CONFIG_STM32_ADC3 case 3: - adcbit = RCC_APB2RSTR_ADC3RST; + adcbit = RCC_RSTR_ADC3RST; + break; +#endif +#ifdef CONFIG_STM32_ADC4 + case 4: + adcbit = RCC_RSTR_ADC4RST; break; #endif default: return; } -#elif defined(CONFIG_STM32_STM32L15XX) - adcbit = RCC_APB2RSTR_ADC1RST; - -#else - /* For the STM32 F4, there is one common reset for all ADC block. - * THIS will probably cause some problems! + /* Set or clear the selected bit in the APB2 reset register. + * modifyreg32() disables interrupts. Disabling interrupts is necessary + * because the APB2RTSR register is used by several different drivers. */ - adcbit = RCC_APB2RSTR_ADCRST; -#endif - - /* Disable interrupts. This is necessary because the APB2RTSR register - * is used by several different drivers. - */ - - flags = irqsave(); - - /* Set or clear the selected bit in the APB2 reset register */ - - regval = getreg32(STM32_RCC_APB2RSTR); if (reset) { - /* Enable ADC reset state */ + /* Enable ADC reset state */ - regval |= adcbit; + modifyreg32(STM32_RCC_RSTR, 0, adcbit); } else { /* Release ADC from reset state */ - regval &= ~adcbit; + modifyreg32(STM32_RCC_RSTR, adcbit, 0); } - - putreg32(regval, STM32_RCC_APB2RSTR); - irqrestore(flags); } /**************************************************************************** @@ -1096,13 +1342,13 @@ static void adc_rccreset(struct stm32_dev_s *priv, bool reset) #ifdef CONFIG_STM32_STM32L15XX static void adc_power_down_idle(FAR struct stm32_dev_s *priv, bool pdi_high) { - uint32_t regval = 0; + uint32_t regval; - avdbg("PDI: %d\n", (pdi_high ? 1 : 0)); + avdbg("PDI: %d\n", pdi_high ? 1 : 0); regval = adc_getreg(priv, STM32_ADC_CR1_OFFSET); - if (!(STM32_ADC1_CR2 & ADC_CR2_ADON)) + if ((STM32_ADC1_CR2 & ADC_CR2_ADON) == 0) { if (pdi_high) { @@ -1137,13 +1383,13 @@ static void adc_power_down_idle(FAR struct stm32_dev_s *priv, bool pdi_high) #ifdef CONFIG_STM32_STM32L15XX static void adc_power_down_delay(FAR struct stm32_dev_s *priv, bool pdd_high) { - uint32_t regval = 0; + uint32_t regval; - avdbg("PDD: %d\n", (pdd_high ? 1 : 0)); + avdbg("PDD: %d\n", pdd_high ? 1 : 0); regval = adc_getreg(priv, STM32_ADC_CR1_OFFSET); - if (!(STM32_ADC1_CR2 & ADC_CR2_ADON)) + if ((STM32_ADC1_CR2 & ADC_CR2_ADON) == 0) { if (pdd_high) { @@ -1179,14 +1425,9 @@ static void adc_power_down_delay(FAR struct stm32_dev_s *priv, bool pdd_high) static void adc_dels_after_conversion(FAR struct stm32_dev_s *priv, uint32_t delay) { - uint32_t regval; + avdbg("Delay selected: 0x%08x\n", delay); - avdbg("Delay selected: 0x%08X\n", delay); - - regval = adc_getreg(priv, STM32_ADC_CR2_OFFSET); - regval &= ~ADC_CR2_DELS_MASK; - regval |= delay; - adc_putreg(priv, STM32_ADC_CR2_OFFSET, regval); + adc_modifyreg(priv, STM32_ADC_CR2_OFFSET, ADC_CR2_DELS_MASK, delay); } #endif @@ -1207,24 +1448,19 @@ static void adc_dels_after_conversion(FAR struct stm32_dev_s *priv, ****************************************************************************/ #ifdef CONFIG_STM32_STM32L15XX -static void adc_select_ch_bank(FAR struct stm32_dev_s *priv, bool chb_selected) +static void adc_select_ch_bank(FAR struct stm32_dev_s *priv, + bool chb_selected) { - uint32_t regval; - - avdbg("Bank of channels selected: %c\n", (chb_selected ? 'B' : 'A')); - - regval = adc_getreg(priv, STM32_ADC_CR2_OFFSET); + avdbg("Bank of channels selected: %c\n", chb_selected ? 'B' : 'A'); if (chb_selected) { - regval |= ADC_CR2_CFG; + adc_modifyreg(priv, STM32_ADC_CR2_OFFSET, 0, ADC_CR2_CFG); } else { - regval &= ~ADC_CR2_CFG; + adc_modifyreg(priv, STM32_ADC_CR2_OFFSET, ADC_CR2_CFG, 0); } - - adc_putreg(priv, STM32_ADC_CR2_OFFSET, regval); } #endif @@ -1244,42 +1480,61 @@ static void adc_select_ch_bank(FAR struct stm32_dev_s *priv, bool chb_selected) * ****************************************************************************/ +#ifdef CONFIG_STM32_STM32F30XX static void adc_enable(FAR struct stm32_dev_s *priv, bool enable) { uint32_t regval; - avdbg("enable: %d\n", (enable ? 1 : 0)); + avdbg("enable: %d\n", enable ? 1 : 0); - /* Not all STM32 parts prove the SR ADONS bit */ + regval = adc_getreg(priv, STM32_ADC_CR_OFFSET); -#ifdef ADC_SR_ADONS - regval = adc_getreg(priv, STM32_ADC_SR_OFFSET); - - if (!(regval & ADC_SR_ADONS) && enable) - { - regval = adc_getreg(priv, STM32_ADC_CR2_OFFSET); - regval |= ADC_CR2_ADON; - } - else if ((regval & ADC_SR_ADONS) && !enable) - { - regval = adc_getreg(priv, STM32_ADC_CR2_OFFSET); - regval &= ~ADC_CR2_ADON; - } - -#else - regval = adc_getreg(priv, STM32_ADC_CR2_OFFSET); if (enable) { - regval |= ADC_CR2_ADON; + /* Enable the ADC */ + + adc_putreg(priv, STM32_ADC_CR_OFFSET, regval | ADC_CR_ADEN); + + /* Wait for the ADC to be ready */ + + while ((adc_getreg(priv, STM32_ADC_ISR_OFFSET) & ADC_INT_ARDY) == 0); } - else + else if ((regval & ADC_CR_ADEN) != 0 && (regval & ADC_CR_ADDIS) == 0) { - regval &= ~ADC_CR2_ADON; + /* Stop ongoing conversions */ + + adc_startconv(priv, false); + + /* Disable the ADC */ + + adc_putreg(priv, STM32_ADC_CR_OFFSET, regval | ADC_CR_ADDIS); + + /* Wait for the ADC to be disabled */ + + while ((adc_getreg(priv, STM32_ADC_CR_OFFSET) & ADC_CR_ADEN) != 0); } +} +#else +static void adc_enable(FAR struct stm32_dev_s *priv, bool enable) +{ +#ifdef ADC_SR_ADONS + bool enabled = (adc_getreg(priv, STM32_ADC_SR_OFFSET) & ADC_SR_ADONS) != 0; +#else + bool enabled = false; #endif - adc_putreg(priv, STM32_ADC_CR2_OFFSET, regval); + avdbg("enable: %d\n", enable ? 1 : 0); + + if (!enabled && enable) + { + adc_modifyreg(priv, STM32_ADC_CR2_OFFSET, 0, ADC_CR2_ADON); + } + else if (enabled && !enable) + { + adc_modifyreg(priv, STM32_ADC_CR2_OFFSET, ADC_CR2_ADON, 0); + } } +#endif /**************************************************************************** * Name: adc_write_sample_time_registers @@ -1299,7 +1554,8 @@ static void adc_write_sample_time_registers(FAR struct adc_dev_s *dev) { FAR struct stm32_dev_s *priv = (FAR struct stm32_dev_s *)dev->ad_priv; uint32_t value = 0; - uint8_t i, shift; + uint8_t i; + uint8_t shift; /* Sampling time individually for each channel * 000: 4 cycles @@ -1367,11 +1623,10 @@ static void adc_write_sample_time_registers(FAR struct adc_dev_s *dev) ****************************************************************************/ #ifdef ADC_HAVE_DMA -static void adc_dmaconvcallback(DMA_HANDLE handle, uint8_t isr, void *arg) +static void adc_dmaconvcallback(DMA_HANDLE handle, uint8_t isr, FAR void *arg) { - FAR struct adc_dev_s *dev = (FAR struct adc_dev_s *)arg; - FAR struct stm32_dev_s *priv = dev->ad_priv; - uint32_t regval; + FAR struct adc_dev_s *dev = (FAR struct adc_dev_s *)arg; + FAR struct stm32_dev_s *priv = (FAR struct stm32_dev_s *)dev->ad_priv; int i; for (i = 0; i < priv->nchannels; i++) @@ -1388,12 +1643,8 @@ static void adc_dmaconvcallback(DMA_HANDLE handle, uint8_t isr, void *arg) /* Restart DMA for the next conversion series */ - regval = adc_getreg(priv, STM32_ADC_CR2_OFFSET); - regval &= ~ADC_CR2_DMA; - adc_putreg(priv, STM32_ADC_CR2_OFFSET, regval); - - regval |= ADC_CR2_DMA; - adc_putreg(priv, STM32_ADC_CR2_OFFSET, regval); + adc_modifyreg(priv, STM32_ADC_DMAREG_OFFSET, ADC_DMAREG_DMA, 0); + adc_modifyreg(priv, STM32_ADC_DMAREG_OFFSET, 0, ADC_DMAREG_DMA); } #endif @@ -1414,21 +1665,32 @@ static void adc_reset(FAR struct adc_dev_s *dev) { FAR struct stm32_dev_s *priv = (FAR struct stm32_dev_s *)dev->ad_priv; irqstate_t flags; - uint32_t regval; + uint32_t clrbits; + uint32_t setbits; #ifdef ADC_HAVE_TIMER int ret; #endif - allvdbg("intf: ADC%d\n", priv->intf); + allvdbg("intf: %d\n", priv->intf); flags = irqsave(); - /* In STM32L15XX family HSI used as an independent clock-source for the ADC */ +#if defined(CONFIG_STM32_STM32L15XX) && \ + (STM32_CFGR_PLLSRC != 0 || STM32_SYSCLK_SW != RCC_CFGR_SW_HSI) -#if defined(CONFIG_STM32_STM32L15XX) && ((STM32_CFGR_PLLSRC != 0) || \ - (STM32_SYSCLK_SW != RCC_CFGR_SW_HSI)) + /* The STM32L15XX family uses HSI as an independent clock-source + * for the ADC + */ adc_enable_hsi(true); +#endif + +#ifdef CONFIG_STM32_STM32F30XX + + /* Turn off the ADC so we can write the RCC bits */ + + adc_enable(priv, false); + #endif /* Enable ADC reset state */ @@ -1439,7 +1701,39 @@ static void adc_reset(FAR struct adc_dev_s *dev) adc_rccreset(priv, false); - /* Initialize the ADC data structures */ +#ifdef CONFIG_STM32_STM32F30XX + + /* Set voltage regular enable to intermediate state */ + + adc_modifyreg(priv, STM32_ADC_CR_OFFSET, ADC_CR_ADVREGEN_MASK, + ADC_CR_ADVREGEN_INTER); + + /* Enable the ADC voltage regulator */ + + adc_modifyreg(priv, STM32_ADC_CR_OFFSET, ADC_CR_ADVREGEN_MASK, + ADC_CR_ADVREGEN_ENABLED); + + /* Wait for the ADC voltage regulator to startup */ + + up_udelay(10); + +#if 0 /* Doesn't work */ + + /* Calibrate the ADC */ + + adc_modifyreg(priv, STM32_ADC_CR_OFFSET, ADC_CR_ADCALDIF, AD_CR_ADCAL); + + /* Wait for the calibration to complete */ + + while ((adc_getreg(priv, STM32_ADC_CR_OFFSET) & ADC_CR_ADCAL) != 0); + +#endif + + /* Initialize the watchdog 1 threshold register */ + + adc_putreg(priv, STM32_ADC_TR1_OFFSET, 0x0fff0000); + +#else /* Initialize the watchdog high threshold register */ @@ -1449,67 +1743,105 @@ static void adc_reset(FAR struct adc_dev_s *dev) adc_putreg(priv, STM32_ADC_LTR_OFFSET, 0x00000000); - /* Initialize the same sample time for each ADC 55.5 cycles - * +#endif + + /* Initialize the same sample time for each ADC. * During sample cycles channel selection bits must remain unchanged. - * For F-family only - * - * 000: 1.5 cycles - * 001: 7.5 cycles - * 010: 13.5 cycles - * 011: 28.5 cycles - * 100: 41.5 cycles - * 101: 55.5 cycles - * 110: 71.5 cycles - * 111: 239.5 cycles */ -#ifndef CONFIG_STM32_STM32L15XX - adc_putreg(priv, STM32_ADC_SMPR1_OFFSET, 0x00b6db6d); - adc_putreg(priv, STM32_ADC_SMPR2_OFFSET, 0x00b6db6d); -#else +#ifdef CONFIG_STM32_STM32L15XX adc_write_sample_time_registers(dev); +#else + adc_putreg(priv, STM32_ADC_SMPR1_OFFSET, ADC_SMPR1_DEFAULT); + adc_putreg(priv, STM32_ADC_SMPR2_OFFSET, ADC_SMPR2_DEFAULT); #endif - /* ADC CR1 Configuration */ +#ifdef CONFIG_STM32_STM32F30XX - regval = adc_getreg(priv, STM32_ADC_CR1_OFFSET); + /* Enable the analog watchdog */ - /* Set mode configuration (Independent mode) */ + clrbits = ADC_CFGR_AWD1CH_MASK; + setbits = ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL | + (priv->chanlist[0] << ADC_CFGR_AWD1CH_SHIFT); -#ifdef CONFIG_STM32_STM32F10XX - regval |= ADC_CR1_IND; -#endif + /* Set the resolution of the conversion */ - /* Initialize the Analog watchdog enable */ - - regval |= ADC_CR1_AWDEN; - regval |= (priv->chanlist[0] << ADC_CR1_AWDCH_SHIFT); - - /* Enable interrupt flags */ - - regval |= ADC_CR1_ALLINTS; + clrbits |= ADC_CFGR_RES_MASK; + setbits |= ADC_CFGR_RES_12BIT; #ifdef ADC_HAVE_DMA if (priv->hasdma) { - regval |= ADC_CR1_SCAN; + /* Set DMA one shot mode */ + + clrbits |= ADC_CFGR_DMACFG; + + /* Enable DMA */ + + setbits |= ADC_CFGR_DMAEN; } #endif -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX) || \ - defined(CONFIG_STM32_STM32L15XX) + /* Disable continuous mode and set align to right */ - /* Enable or disable Overrun interrupt */ + clrbits |= ADC_CFGR_CONT | ADC_CFGR_ALIGN; - regval &= ~ADC_CR1_OVRIE; + /* Disable external trigger for regular channels */ + + clrbits |= ADC_CFGR_EXTEN_MASK; + setbits |= ADC_CFGR_EXTEN_NONE; + + /* Set CFGR configuration */ + + adc_modifyreg(priv, STM32_ADC_CFGR_OFFSET, clrbits, setbits); + + /* Enable interrupt flags, but disable overrun interrupt */ + + clrbits = ADC_IER_OVR; + setbits = ADC_IER_ALLINTS & ~ADC_IER_OVR; + + /* Set IER configuration */ + + adc_modifyreg(priv, STM32_ADC_IER_OFFSET, clrbits, setbits); + +#else + + /* Enable the analog watchdog */ + + clrbits = ADC_CR1_AWDCH_MASK; + setbits = ADC_CR1_AWDEN | (priv->chanlist[0] << ADC_CR1_AWDCH_SHIFT); + +#ifdef CONFIG_STM32_STM32F10XX + + /* Set independent mode */ + + clrbits |= ADC_CR1_DUALMOD_MASK; + setbits |= ADC_CR1_IND; + +#else /* Set the resolution of the conversion */ - regval |= ADC_CR1_RES_12BIT; + clrbits |= ADC_CR1_RES_MASK; + setbits |= ADC_CR1_RES_12BIT; + #endif - adc_putreg(priv, STM32_ADC_CR1_OFFSET, regval); +#ifdef ADC_HAVE_DMA + if (priv->hasdma) + { + setbits |= ADC_CR1_SCAN; + } +#endif + + /* Enable interrupt flags, but disable overrun interrupt */ + + clrbits |= ADC_IER_OVR; + setbits |= ADC_IER_ALLINTS & ~ADC_IER_OVR; + + /* Set CR1 configuration */ + + adc_modifyreg(priv, STM32_ADC_CR1_OFFSET, clrbits, setbits); #ifdef CONFIG_STM32_STM32L15XX @@ -1517,9 +1849,6 @@ static void adc_reset(FAR struct adc_dev_s *dev) adc_power_down_idle(priv, false); adc_power_down_delay(priv, false); -#endif - -#ifdef CONFIG_STM32_STM32L15XX /* Select the bank of channels A */ @@ -1528,85 +1857,70 @@ static void adc_reset(FAR struct adc_dev_s *dev) /* Delay until the converted data has been read */ adc_dels_after_conversion(priv, ADC_CR2_DELS_TILLRD); + #endif - /* ADC CR2 Configuration */ + /* Disable continuous mode and set align to right */ - regval = adc_getreg(priv, STM32_ADC_CR2_OFFSET); + clrbits = ADC_CR2_CONT | ADC_CR2_ALIGN; + setbits = 0; - /* Clear CONT, continuous mode disable */ + /* Disable external trigger for regular channels */ - regval &= ~ADC_CR2_CONT; - - /* Set ALIGN (Right = 0) */ - - regval &= ~ADC_CR2_ALIGN; - -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX) || \ - defined(CONFIG_STM32_STM32L15XX) - /* External trigger enable for regular channels */ - - regval |= ADC_CR2_EXTEN_NONE; -#endif + clrbits |= ADC_EXTREG_EXTEN_MASK; + setbits |= ADC_EXTREG_EXTEN_NONE; #ifdef ADC_HAVE_DMA if (priv->hasdma) { - regval |= ADC_CR2_DMA; + setbits |= ADC_CR2_DMA; } #endif - adc_putreg(priv, STM32_ADC_CR2_OFFSET, regval); + /* Set CR2 configuration */ + + adc_modifyreg(priv, STM32_ADC_CR2_OFFSET, clrbits, setbits); + +#endif /* Configuration of the channel conversions */ -#if ADC_MAX_SAMPLES == 1 - /* Select on first indexed channel for backward compatibility. */ - - adc_set_ch_idx(dev, 0); -#else adc_set_ch(dev, 0); -#endif /* ADC CCR configuration */ -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX) - regval = getreg32(STM32_ADC_CCR); - regval &= ~(ADC_CCR_MULTI_MASK | ADC_CCR_DELAY_MASK | ADC_CCR_DDS | - ADC_CCR_DMA_MASK | ADC_CCR_ADCPRE_MASK | ADC_CCR_VBATE | - ADC_CCR_TSVREFE); - regval |= (ADC_CCR_MULTI_NONE | ADC_CCR_DMA_DISABLED | - ADC_CCR_ADCPRE_DIV2); - putreg32(regval, STM32_ADC_CCR); +#if defined(CONFIG_STM32_STM32F30XX) + clrbits = ADC_CCR_DUAL_MASK | ADC_CCR_DELAY_MASK | ADC_CCR_DMACFG | + ADC_CCR_MDMA_MASK | ADC_CCR_CKMODE_MASK | ADC_CCR_VREFEN | + ADC_CCR_TSEN | ADC_CCR_VBATEN; + setbits = ADC_CCR_DUAL_IND | ADC_CCR_DELAY(0) | ADC_CCR_MDMA_DISABLED | + ADC_CCR_CKMODE_ASYNCH; -#elif defined(CONFIG_STM32_STM32L15XX) - regval = getreg32(STM32_ADC_CCR); - regval &= ~(ADC_CCR_ADCPRE_MASK | ADC_CCR_TSVREFE); - regval |= ADC_CCR_ADCPRE_DIV2; - putreg32(regval, STM32_ADC_CCR); -#endif - - /* Set the number of conversions */ - -#ifdef ADC_HAVE_DMA - if (priv->hasdma) + if (priv->base == STM32_ADC1_BASE || priv->base == STM32_ADC2_BASE) { - DEBUGASSERT(priv->nchannels <= ADC_MAX_CHANNELS_DMA); + stm32_modifyreg32(STM32_ADC12_CCR, clrbits, setbits); } else -#endif { - DEBUGASSERT(priv->nchannels <= ADC_MAX_CHANNELS_NODMA); + stm32_modifyreg32(STM32_ADC34_CCR, clrbits, setbits); } +#elif defined(CONFIG_STM32_STM32F20XX) || \ + defined(CONFIG_STM32_STM32F40XX) || \ + defined(CONFIG_STM32_STM32L15XX) + clrbits = ADC_CCR_ADCPRE_MASK | ADC_CCR_TSVREFE; + setbits = ADC_CCR_ADCPRE_DIV2; - regval |= (((uint32_t)priv->nchannels - 1) << ADC_SQR1_L_SHIFT); - adc_putreg(priv, STM32_ADC_SQR1_OFFSET, regval); +#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX) + clrbits |= ADC_CCR_MULTI_MASK | ADC_CCR_DELAY_MASK | ADC_CCR_DDS | + ADC_CCR_DMA_MASK | ADC_CCR_VBATE; + setbits |= ADC_CCR_MULTI_NONE | ADC_CCR_DMA_DISABLED; +#endif - /* Set the channel index of the first conversion */ - - priv->current = 0; + stm32_modifyreg32(STM32_ADC_CCR, clrbits, setbits); +#endif #ifdef ADC_HAVE_DMA + /* Enable DMA */ if (priv->hasdma) @@ -1636,52 +1950,72 @@ static void adc_reset(FAR struct adc_dev_s *dev) stm32_dmastart(priv->dma, adc_dmaconvcallback, dev, false); } + #endif - /* Set ADON to wake up the ADC from Power Down state. */ + /* Set ADON to wake up the ADC from the power down state */ adc_enable(priv, true); #ifdef ADC_HAVE_TIMER - ret = adc_timinit(priv); - if (ret != OK) + if (priv->tbase != 0) { - adbg("Error initializing the timers\n"); + ret = adc_timinit(priv); + if (ret < 0) + { + adbg("adc_timinit failed: %d\n", ret); + } } -#elif !defined(CONFIG_ADC_NO_STARTUP_CONV) - -#ifdef CONFIG_STM32_STM32F10XX - /* Set ADON (Again) to start the conversion. Only if Timers are not - * configured as triggers - */ - - adc_enable(priv, true); -#else - adc_startconv(priv, true); -#endif /* CONFIG_STM32_STM32F10XX */ - -#endif /* ADC_HAVE_TIMER */ +#ifndef CONFIG_ADC_NO_STARTUP_CONV + else +#endif +#endif +#ifndef CONFIG_ADC_NO_STARTUP_CONV + { + adc_startconv(priv, true); + } +#endif irqrestore(flags); +#ifdef CONFIG_STM32_STM32F30XX + avdbg("ISR: 0x%08x CR: 0x%08x CFGR: 0x%08x\n", + adc_getreg(priv, STM32_ADC_ISR_OFFSET), + adc_getreg(priv, STM32_ADC_CR_OFFSET), + adc_getreg(priv, STM32_ADC_CFGR_OFFSET)); +#else avdbg("SR: 0x%08x CR1: 0x%08x CR2: 0x%08x\n", adc_getreg(priv, STM32_ADC_SR_OFFSET), adc_getreg(priv, STM32_ADC_CR1_OFFSET), adc_getreg(priv, STM32_ADC_CR2_OFFSET)); +#endif + avdbg("SQR1: 0x%08x SQR2: 0x%08x SQR3: 0x%08x\n", adc_getreg(priv, STM32_ADC_SQR1_OFFSET), adc_getreg(priv, STM32_ADC_SQR2_OFFSET), adc_getreg(priv, STM32_ADC_SQR3_OFFSET)); -#ifdef CONFIG_STM32_STM32L15XX + +#if defined(CONFIG_STM32_STM32F30XX) + avdbg("SQR4: 0x%08x\n", adc_getreg(priv, STM32_ADC_SQR4_OFFSET)); +#elif defined(CONFIG_STM32_STM32L15XX) avdbg("SQR4: 0x%08x SQR5: 0x%08x\n", - adc_getreg(priv, STM32_ADC_SQR4_OFFSET), + adc_getreg(priv, STM32_ADC_SQR4_OFFSET) adc_getreg(priv, STM32_ADC_SQR5_OFFSET)); #endif -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX) || \ - defined(CONFIG_STM32_STM32L15XX) - avdbg("CCR: 0x%08x\n", - getreg32(STM32_ADC_CCR)); +#if defined(CONFIG_STM32_STM32F30XX) + if (priv->base == STM32_ADC1_BASE || priv->base == STM32_ADC2_BASE) + { + avdbg("CCR: 0x%08x\n", getreg32(STM32_ADC12_CCR)); + } + else + { + avdbg("CCR: 0x%08x\n", getreg32(STM32_ADC34_CCR)); + } +#elif defined(CONFIG_STM32_STM32F20XX) || \ + defined(CONFIG_STM32_STM32F40XX) || \ + defined(CONFIG_STM32_STM32L15XX) + avdbg("CCR: 0x%08x\n", getreg32(STM32_ADC_CCR)); #endif } @@ -1700,8 +2034,8 @@ static void adc_reset(FAR struct adc_dev_s *dev) * ****************************************************************************/ -#if defined(CONFIG_STM32_STM32L15XX) && ((STM32_CFGR_PLLSRC != 0) || \ - (STM32_SYSCLK_SW != RCC_CFGR_SW_HSI)) +#if defined(CONFIG_STM32_STM32L15XX) && \ + (STM32_CFGR_PLLSRC != 0 || STM32_SYSCLK_SW != RCC_CFGR_SW_HSI) static void adc_reset_hsi_disable(FAR struct adc_dev_s *dev) { adc_reset(dev); @@ -1715,8 +2049,8 @@ static void adc_reset_hsi_disable(FAR struct adc_dev_s *dev) * Description: * Configure the ADC. This method is called the first time that the ADC * device is opened. This will occur when the port is first opened. - * This setup includes configuring and attaching ADC interrupts. Interrupts - * are all disabled upon return. + * This setup includes configuring and attaching ADC interrupts. + * Interrupts are all disabled upon return. * * Input Parameters: * @@ -1732,18 +2066,21 @@ static int adc_setup(FAR struct adc_dev_s *dev) /* Attach the ADC interrupt */ ret = irq_attach(priv->irq, priv->isr); - if (ret == OK) + if (ret < 0) { - /* Make sure that the ADC device is in the powered up, reset state */ - - adc_reset(dev); - - /* Enable the ADC interrupt */ - - avdbg("Enable the ADC interrupt: irq=%d\n", priv->irq); - up_enable_irq(priv->irq); + avdbg("irq_attach failed: %d\n", ret); + return ret; } + /* Make sure that the ADC device is in the powered up, reset state */ + + adc_reset(dev); + + /* Enable the ADC interrupt */ + + avdbg("Enable the ADC interrupt: irq=%d\n", priv->irq); + up_enable_irq(priv->irq); + return ret; } @@ -1764,11 +2101,10 @@ static void adc_shutdown(FAR struct adc_dev_s *dev) { FAR struct stm32_dev_s *priv = (FAR struct stm32_dev_s *)dev->ad_priv; -#ifdef CONFIG_STM32_STM32L15XX adc_enable(priv, false); -# if (STM32_CFGR_PLLSRC != 0) || (STM32_SYSCLK_SW != RCC_CFGR_SW_HSI) - adc_enable_hsi(false); -# endif +#if defined(CONFIG_STM32_STM32L15XX) && \ + (STM32_CFGR_PLLSRC != 0 || STM32_SYSCLK_SW != RCC_CFGR_SW_HSI) + adc_enable_hsi(false); #endif /* Disable ADC interrupts and detach the ADC interrupt handler */ @@ -1796,40 +2132,21 @@ static void adc_shutdown(FAR struct adc_dev_s *dev) static void adc_rxint(FAR struct adc_dev_s *dev, bool enable) { FAR struct stm32_dev_s *priv = (FAR struct stm32_dev_s *)dev->ad_priv; - uint32_t regval; - avdbg("intf: %d enable: %d\n", priv->intf, enable); + avdbg("intf: %d enable: %d\n", priv->intf, enable ? 1 : 0); - regval = adc_getreg(priv, STM32_ADC_CR1_OFFSET); - -#ifndef CONFIG_STM32_HAVE_ONLY_EOCIE if (enable) { /* Enable the end-of-conversion ADC and analog watchdog interrupts */ - regval |= ADC_CR1_ALLINTS; + adc_modifyreg(priv, STM32_ADC_IER_OFFSET, 0, ADC_IER_ALLINTS); } -#else - if (enable) - { - - /* Clear all interrupts */ - - regval &= ~ADC_CR1_ALLINTS; - - /* Enable the end-of-conversion ADC interrupt */ - - regval |= ADC_CR1_EOCIE; - } -#endif else { /* Disable all ADC interrupts */ - regval &= ~ADC_CR1_ALLINTS; + adc_modifyreg(priv, STM32_ADC_IER_OFFSET, ADC_IER_ALLINTS, 0); } - - adc_putreg(priv, STM32_ADC_CR1_OFFSET, regval); } /**************************************************************************** @@ -1840,8 +2157,10 @@ static void adc_rxint(FAR struct adc_dev_s *dev, bool enable) * * Input Parameters: * dev - pointer to device structure used by the driver - * enable - true: Temperature sensor and V REFINT channel enabled (ch 16 and 17) - * false: Temperature sensor and V REFINT channel disabled (ch 16 and 17) + * enable - true: Temperature sensor and V REFINT channel enabled + * (ch 16 and 17) + * false: Temperature sensor and V REFINT channel disabled + * (ch 16 and 17) * * Returned Value: * None. @@ -1849,23 +2168,19 @@ static void adc_rxint(FAR struct adc_dev_s *dev, bool enable) ****************************************************************************/ #ifdef CONFIG_STM32_STM32L15XX -static void adc_ioc_enable_tvref_register(FAR struct adc_dev_s *dev, bool enable) +static void adc_ioc_enable_tvref_register(FAR struct adc_dev_s *dev, + bool enable) { - uint32_t regval; - - regval = getreg32(STM32_ADC_CCR); - if (enable) { - regval |= ADC_CCR_TSVREFE; + stm32_modifyreg32(STM32_ADC_CCR, 0, ADC_CCR_TSVREFE); } else { - regval &= ~ADC_CCR_TSVREFE; + stm32_modifyreg32(STM32_ADC_CCR, ADC_CCR_TSVREFE, 0); } - putreg32(regval, STM32_ADC_CCR); - allvdbg("STM32_ADC_CCR value: 0x%08X\n", getreg32(STM32_ADC_CCR)); + avdbg("STM32_ADC_CCR value: 0x%08x\n", getreg32(STM32_ADC_CCR)); } #endif @@ -1923,7 +2238,7 @@ static int adc_ioc_change_sleep_between_opers(FAR struct adc_dev_s *dev, * Name: adc_ioc_enable_awd_int * * Description: - * Turns ON/OFF ADC analog watch-dog interrupt. + * Turns ON/OFF ADC analog watchdog interrupt. * * Input Parameters: * dev - pointer to device structure used by the driver @@ -1937,19 +2252,14 @@ static int adc_ioc_change_sleep_between_opers(FAR struct adc_dev_s *dev, #ifdef CONFIG_STM32_STM32L15XX static void adc_ioc_enable_awd_int(FAR struct stm32_dev_s *priv, bool enable) { - uint32_t regval = 0; - - regval = adc_getreg(priv, STM32_ADC_CR1_OFFSET); if (enable) { - regval |= ADC_CR1_AWDIE; + adc_modifyreg(priv, STM32_ADC_IER_OFFSET, 0, ADC_IER_AWD); } else { - regval &= ~ADC_CR1_AWDIE; + adc_modifyreg(priv, STM32_ADC_IER_OFFSET, ADC_IER_AWD, 0); } - - adc_putreg(priv, STM32_ADC_CR1_OFFSET, regval); } #endif @@ -1971,19 +2281,14 @@ static void adc_ioc_enable_awd_int(FAR struct stm32_dev_s *priv, bool enable) #ifdef CONFIG_STM32_STM32L15XX static void adc_ioc_enable_eoc_int(FAR struct stm32_dev_s *priv, bool enable) { - uint32_t regval = 0; - - regval = adc_getreg(priv, STM32_ADC_CR1_OFFSET); if (enable) { - regval |= ADC_CR1_EOCIE; + adc_modifyreg(priv, STM32_ADC_IER_OFFSET, 0, ADC_IER_EOC); } else { - regval &= ~ADC_CR1_EOCIE; + adc_modifyreg(priv, STM32_ADC_IER_OFFSET, ADC_IER_EOC, 0); } - - adc_putreg(priv, STM32_ADC_CR1_OFFSET, regval); } #endif @@ -2005,19 +2310,14 @@ static void adc_ioc_enable_eoc_int(FAR struct stm32_dev_s *priv, bool enable) #ifdef CONFIG_STM32_STM32L15XX static void adc_ioc_enable_jeoc_int(FAR struct stm32_dev_s *priv, bool enable) { - uint32_t regval = 0; - - regval = adc_getreg(priv, STM32_ADC_CR1_OFFSET); if (enable) { - regval |= ADC_CR1_JEOCIE; + adc_modifyreg(priv, STM32_ADC_IER_OFFSET, 0, ADC_IER_JEOC); } else { - regval &= ~ADC_CR1_JEOCIE; + adc_modifyreg(priv, STM32_ADC_IER_OFFSET, ADC_IER_JEOC, 0); } - - adc_putreg(priv, STM32_ADC_CR1_OFFSET, regval); } #endif @@ -2039,19 +2339,14 @@ static void adc_ioc_enable_jeoc_int(FAR struct stm32_dev_s *priv, bool enable) #ifdef CONFIG_STM32_STM32L15XX static void adc_ioc_enable_ovr_int(FAR struct stm32_dev_s *priv, bool enable) { - uint32_t regval = 0; - - regval = adc_getreg(priv, STM32_ADC_CR1_OFFSET); if (enable) { - regval |= ADC_CR1_OVRIE; + adc_modifyreg(priv, STM32_ADC_IER_OFFSET, 0, ADC_IER_OVR); } else { - regval &= ~ADC_CR1_OVRIE; + adc_modifyreg(priv, STM32_ADC_IER_OFFSET, ADC_IER_OVR, 0); } - - adc_putreg(priv, STM32_ADC_CR1_OFFSET, regval); } #endif @@ -2127,12 +2422,11 @@ static int adc_ioc_change_ints(FAR struct adc_dev_s *dev, int cmd, bool arg) #ifdef CONFIG_STM32_STM32L15XX static int adc_ioc_wait_rcnr_zeroed(FAR struct stm32_dev_s *priv) { - int i = 0; - uint32_t regval = 0; + int i; for (i = 0; i < 30000; i++) { - if (!((regval = adc_getreg(priv, STM32_ADC_SR_OFFSET)) & ADC_SR_RCNR)) + if ((adc_getreg(priv, STM32_ADC_SR_OFFSET) & ADC_SR_RCNR) == 0) { return OK; } @@ -2156,68 +2450,44 @@ static int adc_ioc_wait_rcnr_zeroed(FAR struct stm32_dev_s *priv) * ****************************************************************************/ -#if defined(CONFIG_STM32_STM32L15XX) && ((STM32_CFGR_PLLSRC != 0) || \ - (STM32_SYSCLK_SW != RCC_CFGR_SW_HSI)) +#if defined(CONFIG_STM32_STM32L15XX) && \ + (STM32_CFGR_PLLSRC != 0 || STM32_SYSCLK_SW != RCC_CFGR_SW_HSI) static void adc_enable_hsi(bool enable) { - uint32_t regval = 0; - if (enable) { - regval = getreg32(STM32_RCC_CR); - regval |= RCC_CR_HSION; - putreg32(regval, STM32_RCC_CR); /* Enable the HSI */ + /* Enable the HSI */ + + stm32_modifyreg32(STM32_RCC_CR, 0, RCC_CR_HSION); while ((getreg32(STM32_RCC_CR) & RCC_CR_HSIRDY) == 0); } else { - regval = getreg32(STM32_RCC_CR); - regval &= ~RCC_CR_HSION; - putreg32(regval, STM32_RCC_CR); /* Disable the HSI */ + /* Disable the HSI */ + + stm32_modifyreg32(STM32_RCC_CR, RCC_CR_HSION, 0); } } #endif /**************************************************************************** - * Name: adc_set_ch_idx - * - * Description: - * Set single channel for adc conversion. Channel selected from - * configured channel list by index. - * - * Input Parameters: - * dev - pointer to device structure used by the driver - * idx - channel index in configured channel list - * - * Returned Value: - * int - errno - * + * Name: adc_sqrbits ****************************************************************************/ -static int adc_set_ch_idx(FAR struct adc_dev_s *dev, uint8_t idx) +static uint32_t adc_sqrbits(FAR struct stm32_dev_s *priv, int first, int last, + int offset) { - FAR struct stm32_dev_s *priv = (FAR struct stm32_dev_s *)dev->ad_priv; - int32_t regval; + uint32_t bits = 0; + int i; - if (idx < priv->cchannels) + for (i = first - 1; + i < priv->nchannels && i < last; + i++, offset += ADC_SQ_OFFSET) { -#ifdef CONFIG_STM32_STM32L15XX - regval = adc_getreg(priv, STM32_ADC_SQR5_OFFSET) & ADC_SQR3_RESERVED; -#else - regval = adc_getreg(priv, STM32_ADC_SQR3_OFFSET) & ADC_SQR3_RESERVED; -#endif - regval |= (uint32_t)priv->chanlist[idx]; -#ifdef CONFIG_STM32_STM32L15XX - adc_putreg(priv, STM32_ADC_SQR5_OFFSET, regval); -#else - adc_putreg(priv, STM32_ADC_SQR3_OFFSET, regval); -#endif - return 0; - } - else - { - return -ENODEV; + bits |= (uint32_t)priv->chanlist[i] << offset; } + + return bits; } /**************************************************************************** @@ -2238,105 +2508,48 @@ static int adc_set_ch_idx(FAR struct adc_dev_s *dev, uint8_t idx) static int adc_set_ch(FAR struct adc_dev_s *dev, uint8_t ch) { FAR struct stm32_dev_s *priv = (FAR struct stm32_dev_s *)dev->ad_priv; - uint32_t regval; - int i, ret = 0; + uint32_t bits; + int i; if (ch == 0) { - int offset; - -#ifdef CONFIG_STM32_STM32L15XX + priv->current = 0; priv->nchannels = priv->cchannels; - regval = adc_getreg(priv, STM32_ADC_SQR5_OFFSET) & ADC_SQR5_RESERVED; - for (i = 0, offset = 0; i < priv->nchannels && i < 6; i++, offset += 5) - { - regval |= (uint32_t)priv->chanlist[i] << offset; - } - - adc_putreg(priv, STM32_ADC_SQR5_OFFSET, regval); - - regval = adc_getreg(priv, STM32_ADC_SQR4_OFFSET) & ADC_SQR4_RESERVED; - for (i = 6, offset = 0; i < priv->nchannels && i < 12; i++, offset += 5) - { - regval |= (uint32_t)priv->chanlist[i] << offset; - } - - adc_putreg(priv, STM32_ADC_SQR4_OFFSET, regval); - - regval = adc_getreg(priv, STM32_ADC_SQR3_OFFSET) & ADC_SQR3_RESERVED; - for (i = 12, offset = 0; i < priv->nchannels && i < 18; i++, offset += 5) - { - regval |= (uint32_t)priv->chanlist[i] << offset; - } - - adc_putreg(priv, STM32_ADC_SQR3_OFFSET, regval); - - regval = adc_getreg(priv, STM32_ADC_SQR2_OFFSET) & ADC_SQR2_RESERVED; - for (i = 18, offset = 0; i < priv->nchannels && i < 24; i++, offset += 5) - { - regval |= (uint32_t)priv->chanlist[i] << offset; - } - - adc_putreg(priv, STM32_ADC_SQR2_OFFSET, regval); - - regval = adc_getreg(priv, STM32_ADC_SQR1_OFFSET) & ADC_SQR1_RESERVED; - for (i = 24, offset = 0; i < priv->nchannels && i < 28; i++, offset += 5) - { - regval |= (uint32_t)priv->chanlist[i] << offset; - } - -#else - priv->nchannels = priv->cchannels; - regval = adc_getreg(priv, STM32_ADC_SQR3_OFFSET) & ADC_SQR3_RESERVED; - for (i = 0, offset = 0; i < priv->nchannels && i < 6; i++, offset += 5) - { - regval |= (uint32_t)priv->chanlist[i] << offset; - } - - adc_putreg(priv, STM32_ADC_SQR3_OFFSET, regval); - - regval = adc_getreg(priv, STM32_ADC_SQR2_OFFSET) & ADC_SQR2_RESERVED; - for (i = 6, offset = 0; i < priv->nchannels && i < 12; i++, offset += 5) - { - regval |= (uint32_t)priv->chanlist[i] << offset; - } - - adc_putreg(priv, STM32_ADC_SQR2_OFFSET, regval); - - regval = adc_getreg(priv, STM32_ADC_SQR1_OFFSET) & ADC_SQR1_RESERVED; - for (i = 12, offset = 0; i < priv->nchannels && i < 16; i++, offset += 5) - { - regval |= (uint32_t)priv->chanlist[i] << offset; - } -#endif } else { - ch = ch - 1; - for (i = 0; i < priv->cchannels; i++) + for (i = 0; i < priv->cchannels && priv->chanlist[i] != ch - 1; i++); + + if (i >= priv->cchannels) { - if ((uint32_t)priv->chanlist[i] == ch) - { - ret = adc_set_ch_idx(dev, i); - if (ret < 0) - { - break; - } - - regval = adc_getreg(priv, STM32_ADC_SQR1_OFFSET) & ADC_SQR1_RESERVED; - regval &= ~(ADC_SQR1_L_MASK); - adc_putreg(priv, STM32_ADC_SQR1_OFFSET, regval); - - priv->current = i; - priv->nchannels = 1; - return ret; - } + return -ENODEV; } - ret = -ENODEV; + priv->current = i; + priv->nchannels = 1; } - return ret; +#ifdef STM32_ADC_SQR5_OFFSET + bits = adc_sqrbits(priv, ADC_SQR5_FIRST, ADC_SQR5_LAST, ADC_SQR5_SQ_OFFSET); + adc_modifyreg(priv, STM32_ADC_SQR5_OFFSET, ~ADC_SQR5_RESERVED, bits); +#endif + +#ifdef STM32_ADC_SQR4_OFFSET + bits = adc_sqrbits(priv, ADC_SQR4_FIRST, ADC_SQR4_LAST, ADC_SQR4_SQ_OFFSET); + adc_modifyreg(priv, STM32_ADC_SQR4_OFFSET, ~ADC_SQR4_RESERVED, bits); +#endif + + bits = adc_sqrbits(priv, ADC_SQR3_FIRST, ADC_SQR3_LAST, ADC_SQR3_SQ_OFFSET); + adc_modifyreg(priv, STM32_ADC_SQR3_OFFSET, ~ADC_SQR3_RESERVED, bits); + + bits = adc_sqrbits(priv, ADC_SQR2_FIRST, ADC_SQR2_LAST, ADC_SQR2_SQ_OFFSET); + adc_modifyreg(priv, STM32_ADC_SQR2_OFFSET, ~ADC_SQR2_RESERVED, bits); + + bits = ((uint32_t)priv->nchannels - 1) << ADC_SQR1_L_SHIFT | + adc_sqrbits(priv, ADC_SQR1_FIRST, ADC_SQR1_LAST, ADC_SQR1_SQ_OFFSET); + adc_modifyreg(priv, STM32_ADC_SQR1_OFFSET, ~ADC_SQR1_RESERVED, bits); + + return OK; } /**************************************************************************** @@ -2356,16 +2569,14 @@ static int adc_set_ch(FAR struct adc_dev_s *dev, uint8_t ch) static int adc_ioctl(FAR struct adc_dev_s *dev, int cmd, unsigned long arg) { - FAR struct stm32_dev_s * priv = (FAR struct stm32_dev_s *)dev->ad_priv; + FAR struct stm32_dev_s *priv = (FAR struct stm32_dev_s *)dev->ad_priv; int ret = OK; switch (cmd) { -#ifdef ADC_HAVE_DMA case ANIOC_TRIGGER: adc_startconv(priv, true); break; -#endif #ifdef CONFIG_STM32_STM32L15XX case IO_ENABLE_TEMPER_VOLT_CH: @@ -2413,10 +2624,10 @@ static int adc_ioctl(FAR struct adc_dev_s *dev, int cmd, unsigned long arg) } adc_startconv(priv, true); - break; } + break; -#if (STM32_CFGR_PLLSRC != 0 || STM32_SYSCLK_SW != RCC_CFGR_SW_HSI) +#if STM32_CFGR_PLLSRC != 0 || STM32_SYSCLK_SW != RCC_CFGR_SW_HSI case IO_STOP_ADC: adc_enable(priv, false); adc_enable_hsi(false); @@ -2432,9 +2643,9 @@ static int adc_ioctl(FAR struct adc_dev_s *dev, int cmd, unsigned long arg) default: adbg("ERROR: Unknown cmd: %d\n", cmd); ret = -ENOTTY; + break; } - UNUSED(priv); return ret; } @@ -2453,37 +2664,40 @@ static int adc_ioctl(FAR struct adc_dev_s *dev, int cmd, unsigned long arg) static int adc_interrupt(FAR struct adc_dev_s *dev) { FAR struct stm32_dev_s *priv = (FAR struct stm32_dev_s *)dev->ad_priv; - uint32_t adcsr; - int32_t value; + uint32_t regval; + uint32_t pending; + int32_t data; + + regval = adc_getreg(priv, STM32_ADC_ISR_OFFSET); + pending = regval & ADC_ISR_ALLINTS; + if (pending == 0) + { + return OK; + } /* Identifies the interruption AWD, OVR or EOC */ - adcsr = adc_getreg(priv, STM32_ADC_SR_OFFSET); - if ((adcsr & ADC_SR_AWD) != 0) + if ((regval & ADC_ISR_AWD) != 0) { alldbg("WARNING: Analog Watchdog, Value converted out of range!\n"); } -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX) || \ - defined(CONFIG_STM32_STM32L15XX) - if ((adcsr & ADC_SR_OVR) != 0) + if ((regval & ADC_ISR_OVR) != 0) { alldbg("WARNING: Overrun has occurred!\n"); } -#endif /* EOC: End of conversion */ - if ((adcsr & ADC_SR_EOC) != 0) + if ((regval & ADC_ISR_EOC) != 0) { /* Read the converted value and clear EOC bit * (It is cleared by reading the ADC_DR) */ - value = adc_getreg(priv, STM32_ADC_DR_OFFSET); - value &= ADC_DR_DATA_MASK; + data = adc_getreg(priv, STM32_ADC_DR_OFFSET) & ADC_DR_RDATA_MASK; - /* Give the ADC data to the ADC driver. adc_receive accepts 3 + /* Give the ADC data to the ADC driver. adc_receive() accepts 3 * parameters: * * 1) The first is the ADC device instance for this ADC block. @@ -2491,7 +2705,7 @@ static int adc_interrupt(FAR struct adc_dev_s *dev) * 3) The third is the converted data for the channel. */ - adc_receive(dev, priv->chanlist[priv->current], value); + adc_receive(dev, priv->chanlist[priv->current], data); /* Set the channel number of the next channel that will complete * conversion. @@ -2507,92 +2721,13 @@ static int adc_interrupt(FAR struct adc_dev_s *dev) } } + regval &= ~pending; + adc_putreg(priv, STM32_ADC_ISR_OFFSET, regval); return OK; } /**************************************************************************** - * Name: adc12_interrupt - * - * Description: - * ADC12 interrupt handler for the STM32 F1 family. - * - * Input Parameters: - * - * Returned Value: - * - ****************************************************************************/ - -#if defined(CONFIG_STM32_STM32F10XX) && (defined(CONFIG_STM32_ADC1) || \ - defined(CONFIG_STM32_ADC2)) -static int adc12_interrupt(int irq, void *context) -{ - uint32_t regval; - uint32_t pending; - - /* Check for pending ADC1 interrupts */ - -#ifdef CONFIG_STM32_ADC1 - regval = getreg32(STM32_ADC1_SR); - pending = regval & ADC_SR_ALLINTS; - if (pending != 0) - { - adc_interrupt(&g_adcdev1); - regval &= ~pending; - putreg32(regval, STM32_ADC1_SR); - } -#endif - - /* Check for pending ADC2 interrupts */ - -#ifdef CONFIG_STM32_ADC2 - regval = getreg32(STM32_ADC2_SR); - pending = regval & ADC_SR_ALLINTS; - if (pending != 0) - { - adc_interrupt(&g_adcdev2); - regval &= ~pending; - putreg32(regval, STM32_ADC2_SR); - } -#endif - return OK; -} -#endif - -/**************************************************************************** - * Name: adc3_interrupt - * - * Description: - * ADC1/2 interrupt handler for the STM32 F1 family. - * - * Input Parameters: - * - * Returned Value: - * - ****************************************************************************/ - -#if defined (CONFIG_STM32_STM32F10XX) && defined (CONFIG_STM32_ADC3) -static int adc3_interrupt(int irq, void *context) -{ - uint32_t regval; - uint32_t pending; - - /* Check for pending ADC3 interrupts */ - - regval = getreg32(STM32_ADC3_SR); - pending = regval & ADC_SR_ALLINTS; - if (pending != 0) - { - adc_interrupt(&g_adcdev3); - regval &= ~pending; - putreg32(regval, STM32_ADC3_SR); - } - - return OK; -} -#endif - -/**************************************************************************** - * Name: adc123_interrupt + * Name: adc1_interrupt * * Description: * ADC interrupt handler for the STM32 L15XX family. @@ -2606,24 +2741,82 @@ static int adc3_interrupt(int irq, void *context) ****************************************************************************/ #ifdef CONFIG_STM32_STM32L15XX -static int adc_stm32l_interrupt(int irq, void *context) +static int adc1_interrupt(int irq, FAR void *context) { - uint32_t regval; - uint32_t pending; + adc_interrupt(&g_adcdev1); - /* STM32L15XX-family has the only ADC. For the sake of the simplicity the ADC1 - * name is used everywhere - */ + return OK; +} +#endif +/**************************************************************************** + * Name: adc12_interrupt + * + * Description: + * ADC1/2 interrupt handler for the STM32 F1/F3 families. + * + * Input Parameters: + * + * Returned Value: + * + ****************************************************************************/ + +#if (defined(CONFIG_STM32_STM32F10XX) || \ + defined(CONFIG_STM32_STM32F30XX)) && \ + (defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2)) +static int adc12_interrupt(int irq, FAR void *context) +{ #ifdef CONFIG_STM32_ADC1 - regval = getreg32(STM32_ADC1_SR); - pending = regval & ADC_SR_ALLINTS; - if (pending != 0) - { - adc_interrupt(&g_adcdev1); - regval &= ~pending; - putreg32(regval, STM32_ADC1_SR); - } + adc_interrupt(&g_adcdev1); +#endif + +#ifdef CONFIG_STM32_ADC2 + adc_interrupt(&g_adcdev2); +#endif + + return OK; +} +#endif + +/**************************************************************************** + * Name: adc3_interrupt + * + * Description: + * ADC3 interrupt handler for the STM32 F1 family. + * + * Input Parameters: + * + * Returned Value: + * + ****************************************************************************/ + +#if (defined(CONFIG_STM32_STM32F10XX) || \ + defined(CONFIG_STM32_STM32F30XX)) && defined(CONFIG_STM32_ADC3) +static int adc3_interrupt(int irq, FAR void *context) +{ + adc_interrupt(&g_adcdev3); + + return OK; +} +#endif + +/**************************************************************************** + * Name: adc4_interrupt + * + * Description: + * ADC4 interrupt handler for the STM32 F3 family. + * + * Input Parameters: + * + * Returned Value: + * + ****************************************************************************/ + +#if defined(CONFIG_STM32_STM32F30XX) && defined(CONFIG_STM32_ADC4) +static int adc4_interrupt(int irq, FAR void *context) +{ +#ifdef CONFIG_STM32_ADC4 + adc_interrupt(&g_adcdev4); #endif return OK; @@ -2634,7 +2827,7 @@ static int adc_stm32l_interrupt(int irq, void *context) * Name: adc123_interrupt * * Description: - * ADC1/2/3 interrupt handler for the STM32 F4 family. + * ADC1/2/3 interrupt handler for the STM32 F2/F4 families. * * Input Parameters: * @@ -2643,49 +2836,20 @@ static int adc_stm32l_interrupt(int irq, void *context) ****************************************************************************/ #if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX) -static int adc123_interrupt(int irq, void *context) +static int adc123_interrupt(int irq, FAR void *context) { - uint32_t regval; - uint32_t pending; - - /* Check for pending ADC1 interrupts */ - #ifdef CONFIG_STM32_ADC1 - regval = getreg32(STM32_ADC1_SR); - pending = regval & ADC_SR_ALLINTS; - if (pending != 0) - { - adc_interrupt(&g_adcdev1); - regval &= ~pending; - putreg32(regval, STM32_ADC1_SR); - } + adc_interrupt(&g_adcdev1); #endif - /* Check for pending ADC2 interrupts */ - #ifdef CONFIG_STM32_ADC2 - regval = getreg32(STM32_ADC2_SR); - pending = regval & ADC_SR_ALLINTS; - if (pending != 0) - { - adc_interrupt(&g_adcdev2); - regval &= ~pending; - putreg32(regval, STM32_ADC2_SR); - } + adc_interrupt(&g_adcdev2); #endif - /* Check for pending ADC3 interrupts */ - #ifdef CONFIG_STM32_ADC3 - regval = getreg32(STM32_ADC3_SR); - pending = regval & ADC_SR_ALLINTS; - if (pending != 0) - { - adc_interrupt(&g_adcdev3); - regval &= ~pending; - putreg32(regval, STM32_ADC3_SR); - } + adc_interrupt(&g_adcdev3); #endif + return OK; } #endif @@ -2697,21 +2861,21 @@ static int adc123_interrupt(int irq, void *context) /**************************************************************************** * Name: adc_change_sample_time * - * Description : Changes sample times for specified channels. This method - * doesn't make any register writing. So, it's only stores the information. - * Values provided by user will be written in registers only on the next adc - * peripheral start, as it was told to do in manual. However, before very first - * start, user can call this method and override default values either - * for every channels or for only some predefined by user channel(s) + * Description: + * Changes sample times for specified channels. This method + * doesn't make any register writing. So, it's only stores the information. + * Values provided by user will be written in registers only on the next + * ADC peripheral start, as it was told to do in manual. However, before + * very first start, user can call this method and override default values + * either for every channels or for only some predefined by user channel(s) * * Input Parameters: - * * priv - pointer to the adc device structure * pdi_high - true: The ADC is powered down when waiting for a start event * false: The ADC is powered up when waiting for a start event * * Returned Value: - * None. + * None * ****************************************************************************/ @@ -2773,65 +2937,58 @@ void stm32_adcchange_sample_time(FAR struct adc_dev_s *dev, * ****************************************************************************/ -struct adc_dev_s *stm32_adcinitialize(int intf, const uint8_t *chanlist, +struct adc_dev_s *stm32_adcinitialize(int intf, FAR const uint8_t *chanlist, int cchannels) { FAR struct adc_dev_s *dev; FAR struct stm32_dev_s *priv; - allvdbg("intf: %d cchannels: %d\n", intf, cchannels); + avdbg("intf: %d cchannels: %d\n", intf, cchannels); -#ifdef CONFIG_STM32_ADC1 - if (intf == 1) + switch (intf) { - allvdbg("ADC1 Selected\n"); - dev = &g_adcdev1; - } - else +#ifdef CONFIG_STM32_ADC1 + case 1: + avdbg("ADC1 selected\n"); + dev = &g_adcdev1; + break; #endif #ifdef CONFIG_STM32_ADC2 - if (intf == 2) - { - avdbg("ADC2 Selected\n"); - dev = &g_adcdev2; - } - else + case 2: + avdbg("ADC2 selected\n"); + dev = &g_adcdev2; + break; #endif #ifdef CONFIG_STM32_ADC3 - if (intf == 3) - { - avdbg("ADC3 Selected\n"); - dev = &g_adcdev3; - } - else + case 3: + avdbg("ADC3 selected\n"); + dev = &g_adcdev3; + break; #endif - { - adbg("No ADC interface defined\n"); - return NULL; +#ifdef CONFIG_STM32_ADC4 + case 4: + avdbg("ADC4 selected\n"); + dev = &g_adcdev4; + break; +#endif + default: + adbg("No ADC interface defined\n"); + return NULL; } /* Configure the selected ADC */ - priv = dev->ad_priv; + priv = (FAR struct stm32_dev_s *)dev->ad_priv; #if defined(CONFIG_STM32_STM32L15XX) /* Assign default values for the sample time table */ - memset(priv->sample_rate, ADC_DEFAULT_SAMPLE, ADC_CHANNELS_NUMBER); + memset(priv->sample_rate, ADC_SMPR_DEFAULT, ADC_CHANNELS_NUMBER); #endif -#ifdef ADC_HAVE_DMA - if (priv->hasdma) - { - DEBUGASSERT(priv->nchannels <= ADC_MAX_CHANNELS_DMA); - } - else -#endif - { - DEBUGASSERT(priv->nchannels <= ADC_MAX_CHANNELS_NODMA); - } + DEBUGASSERT(cchannels <= ADC_MAX_SAMPLES); priv->cchannels = cchannels; @@ -2840,6 +2997,11 @@ struct adc_dev_s *stm32_adcinitialize(int intf, const uint8_t *chanlist, return dev; } -#endif /* CONFIG_STM32_STM32F10XX || CONFIG_STM32_STM32F20XX || CONFIG_STM32_STM32F40XX */ -#endif /* CONFIG_STM32_ADC || CONFIG_STM32_ADC2 || CONFIG_STM32_ADC3 */ +#endif /* CONFIG_STM32_STM32F10XX || CONFIG_STM32_STM32F20XX || + * CONFIG_STM32_STM32F30XX || CONFIG_STM32_STM32F40XX || + * CONFIG_STM32_STM32L15XX + */ +#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 || + * CONFIG_STM32_ADC3 || CONFIG_STM32_ADC4 + */ #endif /* CONFIG_ADC */ diff --git a/arch/arm/src/stm32/stm32_adc.h b/arch/arm/src/stm32/stm32_adc.h index 5a4534b275a..3f354f28f3f 100644 --- a/arch/arm/src/stm32/stm32_adc.h +++ b/arch/arm/src/stm32/stm32_adc.h @@ -2,7 +2,9 @@ * arch/arm/src/stm32/stm32_adc.h * * Copyright (C) 2009, 2011, 2015 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Copyright (C) 2015 Omni Hoverboards Inc. All rights reserved. + * Authors: Gregory Nutt + * Paul Alexander Patience * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -62,33 +64,48 @@ * to be used for that purpose. */ -/* For the STM32 F1 line, timers 1-4 may be used. For STM32 F4 line, timers 1-5 and - * 8 may be used. For the STM32L15XX line, timers 2-4, 6, 7, 9, 10 may be used +/* For the STM32 F1 line, timers 1-4 may be used. + * For the STM32 F3 line, timers 1-4, 6-8, 15, 20 may be used. + * For the STM32 F2/F4 lines, timers 1-5 and 8 may be used. + * For the STM32L15XX line, timers 2-4, 6, 7, 9, 10 may be used. */ -#ifndef CONFIG_STM32_TIM1 +#ifdef CONFIG_STM32_STM32L15XX # undef CONFIG_STM32_TIM1_ADC # undef CONFIG_STM32_TIM1_ADC1 # undef CONFIG_STM32_TIM1_ADC2 # undef CONFIG_STM32_TIM1_ADC3 +# undef CONFIG_STM32_TIM1_ADC4 +#else +# ifndef CONFIG_STM32_TIM1 +# undef CONFIG_STM32_TIM1_ADC +# undef CONFIG_STM32_TIM1_ADC1 +# undef CONFIG_STM32_TIM1_ADC2 +# undef CONFIG_STM32_TIM1_ADC3 +# undef CONFIG_STM32_TIM1_ADC4 +# endif #endif + #ifndef CONFIG_STM32_TIM2 # undef CONFIG_STM32_TIM2_ADC # undef CONFIG_STM32_TIM2_ADC1 # undef CONFIG_STM32_TIM2_ADC2 # undef CONFIG_STM32_TIM2_ADC3 +# undef CONFIG_STM32_TIM2_ADC4 #endif #ifndef CONFIG_STM32_TIM3 # undef CONFIG_STM32_TIM3_ADC # undef CONFIG_STM32_TIM3_ADC1 # undef CONFIG_STM32_TIM3_ADC2 # undef CONFIG_STM32_TIM3_ADC3 +# undef CONFIG_STM32_TIM3_ADC4 #endif #ifndef CONFIG_STM32_TIM4 # undef CONFIG_STM32_TIM4_ADC # undef CONFIG_STM32_TIM4_ADC1 # undef CONFIG_STM32_TIM4_ADC2 # undef CONFIG_STM32_TIM4_ADC3 +# undef CONFIG_STM32_TIM4_ADC4 #endif #if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX) @@ -97,23 +114,31 @@ # undef CONFIG_STM32_TIM5_ADC1 # undef CONFIG_STM32_TIM5_ADC2 # undef CONFIG_STM32_TIM5_ADC3 +# undef CONFIG_STM32_TIM5_ADC4 # endif -# ifndef CONFIG_STM32_TIM8 -# undef CONFIG_STM32_TIM8_ADC -# undef CONFIG_STM32_TIM8_ADC1 -# undef CONFIG_STM32_TIM8_ADC2 -# undef CONFIG_STM32_TIM8_ADC3 -# endif -# #else # undef CONFIG_STM32_TIM5_ADC # undef CONFIG_STM32_TIM5_ADC1 # undef CONFIG_STM32_TIM5_ADC2 # undef CONFIG_STM32_TIM5_ADC3 +# undef CONFIG_STM32_TIM5_ADC4 +#endif + +#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || \ + defined(CONFIG_STM32_STM32F40XX) +# ifndef CONFIG_STM32_TIM8 +# undef CONFIG_STM32_TIM8_ADC +# undef CONFIG_STM32_TIM8_ADC1 +# undef CONFIG_STM32_TIM8_ADC2 +# undef CONFIG_STM32_TIM8_ADC3 +# undef CONFIG_STM32_TIM8_ADC4 +# endif +#else # undef CONFIG_STM32_TIM8_ADC # undef CONFIG_STM32_TIM8_ADC1 # undef CONFIG_STM32_TIM8_ADC2 # undef CONFIG_STM32_TIM8_ADC3 +# undef CONFIG_STM32_TIM8_ADC4 #endif /* Timers 6, 7, 9, 10 used by STM32L15XX family devices. Though there is only ADC @@ -121,50 +146,60 @@ * See definition of the STM32_NADC */ -#if defined(CONFIG_STM32_STM32L15XX) +#if defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F30XX) # ifndef CONFIG_STM32_TIM6 # undef CONFIG_STM32_TIM6_ADC # undef CONFIG_STM32_TIM6_ADC1 # undef CONFIG_STM32_TIM6_ADC2 # undef CONFIG_STM32_TIM6_ADC3 +# undef CONFIG_STM32_TIM6_ADC4 # endif # ifndef CONFIG_STM32_TIM7 # undef CONFIG_STM32_TIM7_ADC # undef CONFIG_STM32_TIM7_ADC1 # undef CONFIG_STM32_TIM7_ADC2 # undef CONFIG_STM32_TIM7_ADC3 +# undef CONFIG_STM32_TIM7_ADC4 # endif +#else +# undef CONFIG_STM32_TIM6_ADC +# undef CONFIG_STM32_TIM6_ADC1 +# undef CONFIG_STM32_TIM6_ADC2 +# undef CONFIG_STM32_TIM6_ADC3 +# undef CONFIG_STM32_TIM6_ADC4 +# undef CONFIG_STM32_TIM7_ADC +# undef CONFIG_STM32_TIM7_ADC1 +# undef CONFIG_STM32_TIM7_ADC2 +# undef CONFIG_STM32_TIM7_ADC3 +# undef CONFIG_STM32_TIM7_ADC4 +#endif + +#if defined(CONFIG_STM32_STM32L15XX) # ifndef CONFIG_STM32_TIM9 # undef CONFIG_STM32_TIM9_ADC # undef CONFIG_STM32_TIM9_ADC1 # undef CONFIG_STM32_TIM9_ADC2 # undef CONFIG_STM32_TIM9_ADC3 +# undef CONFIG_STM32_TIM9_ADC4 # endif # ifndef CONFIG_STM32_TIM10 # undef CONFIG_STM32_TIM10_ADC # undef CONFIG_STM32_TIM10_ADC1 # undef CONFIG_STM32_TIM10_ADC2 # undef CONFIG_STM32_TIM10_ADC3 +# undef CONFIG_STM32_TIM10_ADC4 # endif -# #else -# undef CONFIG_STM32_TIM6_ADC -# undef CONFIG_STM32_TIM6_ADC1 -# undef CONFIG_STM32_TIM6_ADC2 -# undef CONFIG_STM32_TIM6_ADC3 -# undef CONFIG_STM32_TIM7_ADC -# undef CONFIG_STM32_TIM7_ADC1 -# undef CONFIG_STM32_TIM7_ADC2 -# undef CONFIG_STM32_TIM7_ADC3 # undef CONFIG_STM32_TIM9_ADC # undef CONFIG_STM32_TIM9_ADC1 # undef CONFIG_STM32_TIM9_ADC2 # undef CONFIG_STM32_TIM9_ADC3 +# undef CONFIG_STM32_TIM9_ADC4 # undef CONFIG_STM32_TIM10_ADC # undef CONFIG_STM32_TIM10_ADC1 # undef CONFIG_STM32_TIM10_ADC2 # undef CONFIG_STM32_TIM10_ADC3 -# +# undef CONFIG_STM32_TIM10_ADC4 #endif /* Timers 6, 7, and 10-14 are not used with the ADC by any supported family @@ -174,20 +209,56 @@ #undef CONFIG_STM32_TIM11_ADC1 #undef CONFIG_STM32_TIM11_ADC2 #undef CONFIG_STM32_TIM11_ADC3 +#undef CONFIG_STM32_TIM11_ADC4 #undef CONFIG_STM32_TIM12_ADC #undef CONFIG_STM32_TIM12_ADC1 #undef CONFIG_STM32_TIM12_ADC2 #undef CONFIG_STM32_TIM12_ADC3 +#undef CONFIG_STM32_TIM12_ADC4 #undef CONFIG_STM32_TIM13_ADC #undef CONFIG_STM32_TIM13_ADC1 #undef CONFIG_STM32_TIM13_ADC2 #undef CONFIG_STM32_TIM13_ADC3 +#undef CONFIG_STM32_TIM13_ADC4 #undef CONFIG_STM32_TIM14_ADC #undef CONFIG_STM32_TIM14_ADC1 #undef CONFIG_STM32_TIM14_ADC2 #undef CONFIG_STM32_TIM14_ADC3 +#undef CONFIG_STM32_TIM14_ADC4 -/* Up to 3 ADC interfaces are supported */ +#ifdef CONFIG_STM32_STM32F30XX +# ifndef CONFIG_STM32_TIM15 +# undef CONFIG_STM32_TIM15_ADC +# undef CONFIG_STM32_TIM15_ADC1 +# undef CONFIG_STM32_TIM15_ADC2 +# undef CONFIG_STM32_TIM15_ADC3 +# undef CONFIG_STM32_TIM15_ADC4 +# endif +# ifndef CONFIG_STM32_TIM20 +# undef CONFIG_STM32_TIM20_ADC +# undef CONFIG_STM32_TIM20_ADC1 +# undef CONFIG_STM32_TIM20_ADC2 +# undef CONFIG_STM32_TIM20_ADC3 +# undef CONFIG_STM32_TIM20_ADC4 +# endif +#else +# undef CONFIG_STM32_TIM15_ADC +# undef CONFIG_STM32_TIM15_ADC1 +# undef CONFIG_STM32_TIM15_ADC2 +# undef CONFIG_STM32_TIM15_ADC3 +# undef CONFIG_STM32_TIM15_ADC4 +# undef CONFIG_STM32_TIM20_ADC +# undef CONFIG_STM32_TIM20_ADC1 +# undef CONFIG_STM32_TIM20_ADC2 +# undef CONFIG_STM32_TIM20_ADC3 +# undef CONFIG_STM32_TIM20_ADC4 +#endif + +/* Up to 4 ADC interfaces are supported */ + +#if STM32_NADC < 4 +# undef CONFIG_STM32_ADC4 +#endif #if STM32_NADC < 3 # undef CONFIG_STM32_ADC3 @@ -202,17 +273,17 @@ #endif #if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || \ - defined(CONFIG_STM32_ADC3) + defined(CONFIG_STM32_ADC3) || defined(CONFIG_STM32_ADC4) /* DMA support */ #undef ADC_HAVE_DMA #if defined(CONFIG_STM32_ADC1_DMA) || defined(CONFIG_STM32_ADC2_DMA) || \ defined(CONFIG_STM32_ADC3_DMA) || defined(CONFIG_STM32_ADC4_DMA) -# if defined(CONFIG_STM32_STM32F40XX) || defined(CONFIG_STM32_STM32F40XX) -# define ADC_HAVE_DMA 1 +# if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX) +# define ADC_HAVE_DMA 1 # else -# warning DMA is only supported for the STM32 F2/F4 family +# warning "DMA is only supported for the STM32 F2/F3/F4 families" # undef CONFIG_STM32_ADC1_DMA # undef CONFIG_STM32_ADC2_DMA # undef CONFIG_STM32_ADC3_DMA @@ -291,6 +362,10 @@ # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM10_BASE # define ADC1_TIMER_PCLK_FREQUENCY STM32_APB2_TIM10_CLKIN +#elif defined(CONFIG_STM32_TIM15_ADC1) +# define ADC1_HAVE_TIMER 1 +# define ADC1_TIMER_BASE STM32_TIM15_BASE +# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB2_TIM15_CLKIN #else # undef ADC1_HAVE_TIMER #endif @@ -325,10 +400,18 @@ # define ADC2_HAVE_TIMER 1 # define ADC2_TIMER_BASE STM32_TIM5_BASE # define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM5_CLKIN +#elif defined(CONFIG_STM32_TIM6_ADC2) +# define ADC2_HAVE_TIMER 1 +# define ADC2_TIMER_BASE STM32_TIM6_BASE +# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM6_CLKIN #elif defined(CONFIG_STM32_TIM8_ADC2) # define ADC2_HAVE_TIMER 1 # define ADC2_TIMER_BASE STM32_TIM8_BASE # define ADC2_TIMER_PCLK_FREQUENCY STM32_APB2_TIM8_CLKIN +#elif defined(CONFIG_STM32_TIM15_ADC2) +# define ADC2_HAVE_TIMER 1 +# define ADC2_TIMER_BASE STM32_TIM15_BASE +# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB2_TIM15_CLKIN #else # undef ADC2_HAVE_TIMER #endif @@ -363,10 +446,22 @@ # define ADC3_HAVE_TIMER 1 # define ADC3_TIMER_BASE STM32_TIM5_BASE # define ADC3_TIMER_PCLK_FREQUENCY STM32_APB1_TIM5_CLKIN +#elif defined(CONFIG_STM32_TIM7_ADC3) +# define ADC3_HAVE_TIMER 1 +# define ADC3_TIMER_BASE STM32_TIM7_BASE +# define ADC3_TIMER_PCLK_FREQUENCY STM32_APB1_TIM7_CLKIN #elif defined(CONFIG_STM32_TIM8_ADC3) # define ADC3_HAVE_TIMER 1 # define ADC3_TIMER_BASE STM32_TIM8_BASE # define ADC3_TIMER_PCLK_FREQUENCY STM32_APB2_TIM8_CLKIN +#elif defined(CONFIG_STM32_TIM15_ADC3) +# define ADC3_HAVE_TIMER 1 +# define ADC3_TIMER_BASE STM32_TIM15_BASE +# define ADC3_TIMER_PCLK_FREQUENCY STM32_APB2_TIM15_CLKIN +#elif defined(CONFIG_STM32_TIM20_ADC3) +# define ADC3_HAVE_TIMER 1 +# define ADC3_TIMER_BASE STM32_TIM20_BASE +# define ADC3_TIMER_PCLK_FREQUENCY STM32_APB2_TIM20_CLKIN #else # undef ADC3_HAVE_TIMER #endif @@ -381,7 +476,58 @@ # endif #endif -#if defined(ADC1_HAVE_TIMER) || defined(ADC2_HAVE_TIMER) || defined(ADC3_HAVE_TIMER) +#if defined(CONFIG_STM32_TIM1_ADC4) +# define ADC4_HAVE_TIMER 1 +# define ADC4_TIMER_BASE STM32_TIM1_BASE +# define ADC4_TIMER_PCLK_FREQUENCY STM32_APB2_TIM1_CLKIN +#elif defined(CONFIG_STM32_TIM2_ADC4) +# define ADC4_HAVE_TIMER 1 +# define ADC4_TIMER_BASE STM32_TIM2_BASE +# define ADC4_TIMER_PCLK_FREQUENCY STM32_APB1_TIM2_CLKIN +#elif defined(CONFIG_STM32_TIM3_ADC4) +# define ADC4_HAVE_TIMER 1 +# define ADC4_TIMER_BASE STM32_TIM3_BASE +# define ADC4_TIMER_PCLK_FREQUENCY STM32_APB1_TIM3_CLKIN +#elif defined(CONFIG_STM32_TIM4_ADC4) +# define ADC4_HAVE_TIMER 1 +# define ADC4_TIMER_BASE STM32_TIM4_BASE +# define ADC4_TIMER_PCLK_FREQUENCY STM32_APB1_TIM4_CLKIN +#elif defined(CONFIG_STM32_TIM5_ADC4) +# define ADC4_HAVE_TIMER 1 +# define ADC4_TIMER_BASE STM32_TIM5_BASE +# define ADC4_TIMER_PCLK_FREQUENCY STM32_APB1_TIM5_CLKIN +#elif defined(CONFIG_STM32_TIM7_ADC4) +# define ADC4_HAVE_TIMER 1 +# define ADC4_TIMER_BASE STM32_TIM7_BASE +# define ADC4_TIMER_PCLK_FREQUENCY STM32_APB1_TIM7_CLKIN +#elif defined(CONFIG_STM32_TIM8_ADC4) +# define ADC4_HAVE_TIMER 1 +# define ADC4_TIMER_BASE STM32_TIM8_BASE +# define ADC4_TIMER_PCLK_FREQUENCY STM32_APB2_TIM8_CLKIN +#elif defined(CONFIG_STM32_TIM15_ADC4) +# define ADC4_HAVE_TIMER 1 +# define ADC4_TIMER_BASE STM32_TIM15_BASE +# define ADC4_TIMER_PCLK_FREQUENCY STM32_APB2_TIM15_CLKIN +#elif defined(CONFIG_STM32_TIM20_ADC4) +# define ADC4_HAVE_TIMER 1 +# define ADC4_TIMER_BASE STM32_TIM20_BASE +# define ADC4_TIMER_PCLK_FREQUENCY STM32_APB2_TIM20_CLKIN +#else +# undef ADC4_HAVE_TIMER +#endif + +#ifdef ADC4_HAVE_TIMER +# ifndef CONFIG_STM32_ADC4_SAMPLE_FREQUENCY +# error "CONFIG_STM32_ADC4_SAMPLE_FREQUENCY not defined" +# endif +# ifndef CONFIG_STM32_ADC4_TIMTRIG +# error "CONFIG_STM32_ADC4_TIMTRIG not defined" +# warning "Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO" +# endif +#endif + +#if defined(ADC1_HAVE_TIMER) || defined(ADC2_HAVE_TIMER) || \ + defined(ADC3_HAVE_TIMER) || defined(ADC4_HAVE_TIMER) # define ADC_HAVE_TIMER 1 # if defined(CONFIG_STM32_STM32F10XX) && !defined(CONFIG_STM32_FORCEPOWER) # warning "CONFIG_STM32_FORCEPOWER must be defined to enable the timer(s)" @@ -401,143 +547,641 @@ * for other 3 ADC's */ +#ifdef CONFIG_STM32_STM32F30XX +# define ADC1_EXTSEL_T1CC1 ADC12_CFGR_EXTSEL_T1CC1 +# define ADC1_EXTSEL_T1CC2 ADC12_CFGR_EXTSEL_T1CC2 +# define ADC1_EXTSEL_T1CC3 ADC12_CFGR_EXTSEL_T1CC3 +# define ADC1_EXTSEL_T1CC4 ADC12_CFGR_EXTSEL_T1CC4 +# define ADC1_EXTSEL_T1TRGO ADC12_CFGR_EXTSEL_T1TRGO +# define ADC2_EXTSEL_T1CC1 ADC12_CFGR_EXTSEL_T1CC1 +# define ADC2_EXTSEL_T1CC2 ADC12_CFGR_EXTSEL_T1CC2 +# define ADC2_EXTSEL_T1CC3 ADC12_CFGR_EXTSEL_T1CC3 +# define ADC2_EXTSEL_T1CC4 ADC12_CFGR_EXTSEL_T1CC4 +# define ADC2_EXTSEL_T1TRGO ADC12_CFGR_EXTSEL_T1TRGO +# define ADC3_EXTSEL_T1CC1 ADC34_CFGR_EXTSEL_T1CC1 +# define ADC3_EXTSEL_T1CC2 ADC34_CFGR_EXTSEL_T1CC2 +# define ADC3_EXTSEL_T1CC3 ADC34_CFGR_EXTSEL_T1CC3 +# define ADC3_EXTSEL_T1CC4 ADC34_CFGR_EXTSEL_T1CC4 +# define ADC3_EXTSEL_T1TRGO ADC34_CFGR_EXTSEL_T1TRGO +# define ADC4_EXTSEL_T1CC1 ADC34_CFGR_EXTSEL_T1CC1 +# define ADC4_EXTSEL_T1CC2 ADC34_CFGR_EXTSEL_T1CC2 +# define ADC4_EXTSEL_T1CC3 ADC34_CFGR_EXTSEL_T1CC3 +# define ADC4_EXTSEL_T1CC4 ADC34_CFGR_EXTSEL_T1CC4 +# define ADC4_EXTSEL_T1TRGO ADC34_CFGR_EXTSEL_T1TRGO +# define ADC1_EXTSEL_T2CC1 ADC12_CFGR_EXTSEL_T2CC1 +# define ADC1_EXTSEL_T2CC2 ADC12_CFGR_EXTSEL_T2CC2 +# define ADC1_EXTSEL_T2CC3 ADC12_CFGR_EXTSEL_T2CC3 +# define ADC1_EXTSEL_T2CC4 ADC12_CFGR_EXTSEL_T2CC4 +# define ADC1_EXTSEL_T2TRGO ADC12_CFGR_EXTSEL_T2TRGO +# define ADC2_EXTSEL_T2CC1 ADC12_CFGR_EXTSEL_T2CC1 +# define ADC2_EXTSEL_T2CC2 ADC12_CFGR_EXTSEL_T2CC2 +# define ADC2_EXTSEL_T2CC3 ADC12_CFGR_EXTSEL_T2CC3 +# define ADC2_EXTSEL_T2CC4 ADC12_CFGR_EXTSEL_T2CC4 +# define ADC2_EXTSEL_T2TRGO ADC12_CFGR_EXTSEL_T2TRGO +# define ADC3_EXTSEL_T2CC1 ADC34_CFGR_EXTSEL_T2CC1 +# define ADC3_EXTSEL_T2CC2 ADC34_CFGR_EXTSEL_T2CC2 +# define ADC3_EXTSEL_T2CC3 ADC34_CFGR_EXTSEL_T2CC3 +# define ADC3_EXTSEL_T2CC4 ADC34_CFGR_EXTSEL_T2CC4 +# define ADC3_EXTSEL_T2TRGO ADC34_CFGR_EXTSEL_T2TRGO +# define ADC4_EXTSEL_T2CC1 ADC34_CFGR_EXTSEL_T2CC1 +# define ADC4_EXTSEL_T2CC2 ADC34_CFGR_EXTSEL_T2CC2 +# define ADC4_EXTSEL_T2CC3 ADC34_CFGR_EXTSEL_T2CC3 +# define ADC4_EXTSEL_T2CC4 ADC34_CFGR_EXTSEL_T2CC4 +# define ADC4_EXTSEL_T2TRGO ADC34_CFGR_EXTSEL_T2TRGO +# define ADC1_EXTSEL_T3CC1 ADC12_CFGR_EXTSEL_T3CC1 +# define ADC1_EXTSEL_T3CC2 ADC12_CFGR_EXTSEL_T3CC2 +# define ADC1_EXTSEL_T3CC3 ADC12_CFGR_EXTSEL_T3CC3 +# define ADC1_EXTSEL_T3CC4 ADC12_CFGR_EXTSEL_T3CC4 +# define ADC1_EXTSEL_T3TRGO ADC12_CFGR_EXTSEL_T3TRGO +# define ADC2_EXTSEL_T3CC1 ADC12_CFGR_EXTSEL_T3CC1 +# define ADC2_EXTSEL_T3CC2 ADC12_CFGR_EXTSEL_T3CC2 +# define ADC2_EXTSEL_T3CC3 ADC12_CFGR_EXTSEL_T3CC3 +# define ADC2_EXTSEL_T3CC4 ADC12_CFGR_EXTSEL_T3CC4 +# define ADC2_EXTSEL_T3TRGO ADC12_CFGR_EXTSEL_T3TRGO +# define ADC3_EXTSEL_T3CC1 ADC34_CFGR_EXTSEL_T3CC1 +# define ADC3_EXTSEL_T3CC2 ADC34_CFGR_EXTSEL_T3CC2 +# define ADC3_EXTSEL_T3CC3 ADC34_CFGR_EXTSEL_T3CC3 +# define ADC3_EXTSEL_T3CC4 ADC34_CFGR_EXTSEL_T3CC4 +# define ADC3_EXTSEL_T3TRGO ADC34_CFGR_EXTSEL_T3TRGO +# define ADC4_EXTSEL_T3CC1 ADC34_CFGR_EXTSEL_T3CC1 +# define ADC4_EXTSEL_T3CC2 ADC34_CFGR_EXTSEL_T3CC2 +# define ADC4_EXTSEL_T3CC3 ADC34_CFGR_EXTSEL_T3CC3 +# define ADC4_EXTSEL_T3CC4 ADC34_CFGR_EXTSEL_T3CC4 +# define ADC4_EXTSEL_T3TRGO ADC34_CFGR_EXTSEL_T3TRGO +# define ADC1_EXTSEL_T4CC1 ADC12_CFGR_EXTSEL_T4CC1 +# define ADC1_EXTSEL_T4CC2 ADC12_CFGR_EXTSEL_T4CC2 +# define ADC1_EXTSEL_T4CC3 ADC12_CFGR_EXTSEL_T4CC3 +# define ADC1_EXTSEL_T4CC4 ADC12_CFGR_EXTSEL_T4CC4 +# define ADC1_EXTSEL_T4TRGO ADC12_CFGR_EXTSEL_T4TRGO +# define ADC2_EXTSEL_T4CC1 ADC12_CFGR_EXTSEL_T4CC1 +# define ADC2_EXTSEL_T4CC2 ADC12_CFGR_EXTSEL_T4CC2 +# define ADC2_EXTSEL_T4CC3 ADC12_CFGR_EXTSEL_T4CC3 +# define ADC2_EXTSEL_T4CC4 ADC12_CFGR_EXTSEL_T4CC4 +# define ADC2_EXTSEL_T4TRGO ADC12_CFGR_EXTSEL_T4TRGO +# define ADC3_EXTSEL_T4CC1 ADC34_CFGR_EXTSEL_T4CC1 +# define ADC3_EXTSEL_T4CC2 ADC34_CFGR_EXTSEL_T4CC2 +# define ADC3_EXTSEL_T4CC3 ADC34_CFGR_EXTSEL_T4CC3 +# define ADC3_EXTSEL_T4CC4 ADC34_CFGR_EXTSEL_T4CC4 +# define ADC3_EXTSEL_T4TRGO ADC34_CFGR_EXTSEL_T4TRGO +# define ADC4_EXTSEL_T4CC1 ADC34_CFGR_EXTSEL_T4CC1 +# define ADC4_EXTSEL_T4CC2 ADC34_CFGR_EXTSEL_T4CC2 +# define ADC4_EXTSEL_T4CC3 ADC34_CFGR_EXTSEL_T4CC3 +# define ADC4_EXTSEL_T4CC4 ADC34_CFGR_EXTSEL_T4CC4 +# define ADC4_EXTSEL_T4TRGO ADC34_CFGR_EXTSEL_T4TRGO +# define ADC1_EXTSEL_T5CC1 ADC12_CFGR_EXTSEL_T5CC1 +# define ADC1_EXTSEL_T5CC2 ADC12_CFGR_EXTSEL_T5CC2 +# define ADC1_EXTSEL_T5CC3 ADC12_CFGR_EXTSEL_T5CC3 +# define ADC1_EXTSEL_T5CC4 ADC12_CFGR_EXTSEL_T5CC4 +# define ADC1_EXTSEL_T5TRGO ADC12_CFGR_EXTSEL_T5TRGO +# define ADC2_EXTSEL_T5CC1 ADC12_CFGR_EXTSEL_T5CC1 +# define ADC2_EXTSEL_T5CC2 ADC12_CFGR_EXTSEL_T5CC2 +# define ADC2_EXTSEL_T5CC3 ADC12_CFGR_EXTSEL_T5CC3 +# define ADC2_EXTSEL_T5CC4 ADC12_CFGR_EXTSEL_T5CC4 +# define ADC2_EXTSEL_T5TRGO ADC12_CFGR_EXTSEL_T5TRGO +# define ADC3_EXTSEL_T5CC1 ADC34_CFGR_EXTSEL_T5CC1 +# define ADC3_EXTSEL_T5CC2 ADC34_CFGR_EXTSEL_T5CC2 +# define ADC3_EXTSEL_T5CC3 ADC34_CFGR_EXTSEL_T5CC3 +# define ADC3_EXTSEL_T5CC4 ADC34_CFGR_EXTSEL_T5CC4 +# define ADC3_EXTSEL_T5TRGO ADC34_CFGR_EXTSEL_T5TRGO +# define ADC4_EXTSEL_T5CC1 ADC34_CFGR_EXTSEL_T5CC1 +# define ADC4_EXTSEL_T5CC2 ADC34_CFGR_EXTSEL_T5CC2 +# define ADC4_EXTSEL_T5CC3 ADC34_CFGR_EXTSEL_T5CC3 +# define ADC4_EXTSEL_T5CC4 ADC34_CFGR_EXTSEL_T5CC4 +# define ADC4_EXTSEL_T5TRGO ADC34_CFGR_EXTSEL_T5TRGO +# define ADC1_EXTSEL_T6CC1 ADC12_CFGR_EXTSEL_T6CC1 +# define ADC1_EXTSEL_T6CC2 ADC12_CFGR_EXTSEL_T6CC2 +# define ADC1_EXTSEL_T6CC3 ADC12_CFGR_EXTSEL_T6CC3 +# define ADC1_EXTSEL_T6CC4 ADC12_CFGR_EXTSEL_T6CC4 +# define ADC1_EXTSEL_T6TRGO ADC12_CFGR_EXTSEL_T6TRGO +# define ADC2_EXTSEL_T6CC1 ADC12_CFGR_EXTSEL_T6CC1 +# define ADC2_EXTSEL_T6CC2 ADC12_CFGR_EXTSEL_T6CC2 +# define ADC2_EXTSEL_T6CC3 ADC12_CFGR_EXTSEL_T6CC3 +# define ADC2_EXTSEL_T6CC4 ADC12_CFGR_EXTSEL_T6CC4 +# define ADC2_EXTSEL_T6TRGO ADC12_CFGR_EXTSEL_T6TRGO +# define ADC3_EXTSEL_T6CC1 ADC34_CFGR_EXTSEL_T6CC1 +# define ADC3_EXTSEL_T6CC2 ADC34_CFGR_EXTSEL_T6CC2 +# define ADC3_EXTSEL_T6CC3 ADC34_CFGR_EXTSEL_T6CC3 +# define ADC3_EXTSEL_T6CC4 ADC34_CFGR_EXTSEL_T6CC4 +# define ADC3_EXTSEL_T6TRGO ADC34_CFGR_EXTSEL_T6TRGO +# define ADC4_EXTSEL_T6CC1 ADC34_CFGR_EXTSEL_T6CC1 +# define ADC4_EXTSEL_T6CC2 ADC34_CFGR_EXTSEL_T6CC2 +# define ADC4_EXTSEL_T6CC3 ADC34_CFGR_EXTSEL_T6CC3 +# define ADC4_EXTSEL_T6CC4 ADC34_CFGR_EXTSEL_T6CC4 +# define ADC4_EXTSEL_T6TRGO ADC34_CFGR_EXTSEL_T6TRGO +# define ADC1_EXTSEL_T7CC1 ADC12_CFGR_EXTSEL_T7CC1 +# define ADC1_EXTSEL_T7CC2 ADC12_CFGR_EXTSEL_T7CC2 +# define ADC1_EXTSEL_T7CC3 ADC12_CFGR_EXTSEL_T7CC3 +# define ADC1_EXTSEL_T7CC4 ADC12_CFGR_EXTSEL_T7CC4 +# define ADC1_EXTSEL_T7TRGO ADC12_CFGR_EXTSEL_T7TRGO +# define ADC2_EXTSEL_T7CC1 ADC12_CFGR_EXTSEL_T7CC1 +# define ADC2_EXTSEL_T7CC2 ADC12_CFGR_EXTSEL_T7CC2 +# define ADC2_EXTSEL_T7CC3 ADC12_CFGR_EXTSEL_T7CC3 +# define ADC2_EXTSEL_T7CC4 ADC12_CFGR_EXTSEL_T7CC4 +# define ADC2_EXTSEL_T7TRGO ADC12_CFGR_EXTSEL_T7TRGO +# define ADC3_EXTSEL_T7CC1 ADC34_CFGR_EXTSEL_T7CC1 +# define ADC3_EXTSEL_T7CC2 ADC34_CFGR_EXTSEL_T7CC2 +# define ADC3_EXTSEL_T7CC3 ADC34_CFGR_EXTSEL_T7CC3 +# define ADC3_EXTSEL_T7CC4 ADC34_CFGR_EXTSEL_T7CC4 +# define ADC3_EXTSEL_T7TRGO ADC34_CFGR_EXTSEL_T7TRGO +# define ADC4_EXTSEL_T7CC1 ADC34_CFGR_EXTSEL_T7CC1 +# define ADC4_EXTSEL_T7CC2 ADC34_CFGR_EXTSEL_T7CC2 +# define ADC4_EXTSEL_T7CC3 ADC34_CFGR_EXTSEL_T7CC3 +# define ADC4_EXTSEL_T7CC4 ADC34_CFGR_EXTSEL_T7CC4 +# define ADC4_EXTSEL_T7TRGO ADC34_CFGR_EXTSEL_T7TRGO +# define ADC1_EXTSEL_T8CC1 ADC12_CFGR_EXTSEL_T8CC1 +# define ADC1_EXTSEL_T8CC2 ADC12_CFGR_EXTSEL_T8CC2 +# define ADC1_EXTSEL_T8CC3 ADC12_CFGR_EXTSEL_T8CC3 +# define ADC1_EXTSEL_T8CC4 ADC12_CFGR_EXTSEL_T8CC4 +# define ADC1_EXTSEL_T8TRGO ADC12_CFGR_EXTSEL_T8TRGO +# define ADC2_EXTSEL_T8CC1 ADC12_CFGR_EXTSEL_T8CC1 +# define ADC2_EXTSEL_T8CC2 ADC12_CFGR_EXTSEL_T8CC2 +# define ADC2_EXTSEL_T8CC3 ADC12_CFGR_EXTSEL_T8CC3 +# define ADC2_EXTSEL_T8CC4 ADC12_CFGR_EXTSEL_T8CC4 +# define ADC2_EXTSEL_T8TRGO ADC12_CFGR_EXTSEL_T8TRGO +# define ADC3_EXTSEL_T8CC1 ADC34_CFGR_EXTSEL_T8CC1 +# define ADC3_EXTSEL_T8CC2 ADC34_CFGR_EXTSEL_T8CC2 +# define ADC3_EXTSEL_T8CC3 ADC34_CFGR_EXTSEL_T8CC3 +# define ADC3_EXTSEL_T8CC4 ADC34_CFGR_EXTSEL_T8CC4 +# define ADC3_EXTSEL_T8TRGO ADC34_CFGR_EXTSEL_T8TRGO +# define ADC4_EXTSEL_T8CC1 ADC34_CFGR_EXTSEL_T8CC1 +# define ADC4_EXTSEL_T8CC2 ADC34_CFGR_EXTSEL_T8CC2 +# define ADC4_EXTSEL_T8CC3 ADC34_CFGR_EXTSEL_T8CC3 +# define ADC4_EXTSEL_T8CC4 ADC34_CFGR_EXTSEL_T8CC4 +# define ADC4_EXTSEL_T8TRGO ADC34_CFGR_EXTSEL_T8TRGO +# define ADC1_EXTSEL_T9CC1 ADC12_CFGR_EXTSEL_T9CC1 +# define ADC1_EXTSEL_T9CC2 ADC12_CFGR_EXTSEL_T9CC2 +# define ADC1_EXTSEL_T9CC3 ADC12_CFGR_EXTSEL_T9CC3 +# define ADC1_EXTSEL_T9CC4 ADC12_CFGR_EXTSEL_T9CC4 +# define ADC1_EXTSEL_T9TRGO ADC12_CFGR_EXTSEL_T9TRGO +# define ADC2_EXTSEL_T9CC1 ADC12_CFGR_EXTSEL_T9CC1 +# define ADC2_EXTSEL_T9CC2 ADC12_CFGR_EXTSEL_T9CC2 +# define ADC2_EXTSEL_T9CC3 ADC12_CFGR_EXTSEL_T9CC3 +# define ADC2_EXTSEL_T9CC4 ADC12_CFGR_EXTSEL_T9CC4 +# define ADC2_EXTSEL_T9TRGO ADC12_CFGR_EXTSEL_T9TRGO +# define ADC3_EXTSEL_T9CC1 ADC34_CFGR_EXTSEL_T9CC1 +# define ADC3_EXTSEL_T9CC2 ADC34_CFGR_EXTSEL_T9CC2 +# define ADC3_EXTSEL_T9CC3 ADC34_CFGR_EXTSEL_T9CC3 +# define ADC3_EXTSEL_T9CC4 ADC34_CFGR_EXTSEL_T9CC4 +# define ADC3_EXTSEL_T9TRGO ADC34_CFGR_EXTSEL_T9TRGO +# define ADC4_EXTSEL_T9CC1 ADC34_CFGR_EXTSEL_T9CC1 +# define ADC4_EXTSEL_T9CC2 ADC34_CFGR_EXTSEL_T9CC2 +# define ADC4_EXTSEL_T9CC3 ADC34_CFGR_EXTSEL_T9CC3 +# define ADC4_EXTSEL_T9CC4 ADC34_CFGR_EXTSEL_T9CC4 +# define ADC4_EXTSEL_T9TRGO ADC34_CFGR_EXTSEL_T9TRGO +# define ADC1_EXTSEL_T10CC1 ADC12_CFGR_EXTSEL_T10CC1 +# define ADC1_EXTSEL_T10CC2 ADC12_CFGR_EXTSEL_T10CC2 +# define ADC1_EXTSEL_T10CC3 ADC12_CFGR_EXTSEL_T10CC3 +# define ADC1_EXTSEL_T10CC4 ADC12_CFGR_EXTSEL_T10CC4 +# define ADC1_EXTSEL_T10TRGO ADC12_CFGR_EXTSEL_T10TRGO +# define ADC2_EXTSEL_T10CC1 ADC12_CFGR_EXTSEL_T10CC1 +# define ADC2_EXTSEL_T10CC2 ADC12_CFGR_EXTSEL_T10CC2 +# define ADC2_EXTSEL_T10CC3 ADC12_CFGR_EXTSEL_T10CC3 +# define ADC2_EXTSEL_T10CC4 ADC12_CFGR_EXTSEL_T10CC4 +# define ADC2_EXTSEL_T10TRGO ADC12_CFGR_EXTSEL_T10TRGO +# define ADC3_EXTSEL_T10CC1 ADC34_CFGR_EXTSEL_T10CC1 +# define ADC3_EXTSEL_T10CC2 ADC34_CFGR_EXTSEL_T10CC2 +# define ADC3_EXTSEL_T10CC3 ADC34_CFGR_EXTSEL_T10CC3 +# define ADC3_EXTSEL_T10CC4 ADC34_CFGR_EXTSEL_T10CC4 +# define ADC3_EXTSEL_T10TRGO ADC34_CFGR_EXTSEL_T10TRGO +# define ADC4_EXTSEL_T10CC1 ADC34_CFGR_EXTSEL_T10CC1 +# define ADC4_EXTSEL_T10CC2 ADC34_CFGR_EXTSEL_T10CC2 +# define ADC4_EXTSEL_T10CC3 ADC34_CFGR_EXTSEL_T10CC3 +# define ADC4_EXTSEL_T10CC4 ADC34_CFGR_EXTSEL_T10CC4 +# define ADC4_EXTSEL_T10TRGO ADC34_CFGR_EXTSEL_T10TRGO +# define ADC1_EXTSEL_T15CC1 ADC12_CFGR_EXTSEL_T15CC1 +# define ADC1_EXTSEL_T15CC2 ADC12_CFGR_EXTSEL_T15CC2 +# define ADC1_EXTSEL_T15CC3 ADC12_CFGR_EXTSEL_T15CC3 +# define ADC1_EXTSEL_T15CC4 ADC12_CFGR_EXTSEL_T15CC4 +# define ADC1_EXTSEL_T15TRGO ADC12_CFGR_EXTSEL_T15TRGO +# define ADC2_EXTSEL_T15CC1 ADC12_CFGR_EXTSEL_T15CC1 +# define ADC2_EXTSEL_T15CC2 ADC12_CFGR_EXTSEL_T15CC2 +# define ADC2_EXTSEL_T15CC3 ADC12_CFGR_EXTSEL_T15CC3 +# define ADC2_EXTSEL_T15CC4 ADC12_CFGR_EXTSEL_T15CC4 +# define ADC2_EXTSEL_T15TRGO ADC12_CFGR_EXTSEL_T15TRGO +# define ADC3_EXTSEL_T15CC1 ADC34_CFGR_EXTSEL_T15CC1 +# define ADC3_EXTSEL_T15CC2 ADC34_CFGR_EXTSEL_T15CC2 +# define ADC3_EXTSEL_T15CC3 ADC34_CFGR_EXTSEL_T15CC3 +# define ADC3_EXTSEL_T15CC4 ADC34_CFGR_EXTSEL_T15CC4 +# define ADC3_EXTSEL_T15TRGO ADC34_CFGR_EXTSEL_T15TRGO +# define ADC4_EXTSEL_T15CC1 ADC34_CFGR_EXTSEL_T15CC1 +# define ADC4_EXTSEL_T15CC2 ADC34_CFGR_EXTSEL_T15CC2 +# define ADC4_EXTSEL_T15CC3 ADC34_CFGR_EXTSEL_T15CC3 +# define ADC4_EXTSEL_T15CC4 ADC34_CFGR_EXTSEL_T15CC4 +# define ADC4_EXTSEL_T15TRGO ADC34_CFGR_EXTSEL_T15TRGO +# define ADC1_EXTSEL_T20CC1 ADC12_CFGR_EXTSEL_T20CC1 +# define ADC1_EXTSEL_T20CC2 ADC12_CFGR_EXTSEL_T20CC2 +# define ADC1_EXTSEL_T20CC3 ADC12_CFGR_EXTSEL_T20CC3 +# define ADC1_EXTSEL_T20CC4 ADC12_CFGR_EXTSEL_T20CC4 +# define ADC1_EXTSEL_T20TRGO ADC12_CFGR_EXTSEL_T20TRGO +# define ADC2_EXTSEL_T20CC1 ADC12_CFGR_EXTSEL_T20CC1 +# define ADC2_EXTSEL_T20CC2 ADC12_CFGR_EXTSEL_T20CC2 +# define ADC2_EXTSEL_T20CC3 ADC12_CFGR_EXTSEL_T20CC3 +# define ADC2_EXTSEL_T20CC4 ADC12_CFGR_EXTSEL_T20CC4 +# define ADC2_EXTSEL_T20TRGO ADC12_CFGR_EXTSEL_T20TRGO +# define ADC3_EXTSEL_T20CC1 ADC34_CFGR_EXTSEL_T20CC1 +# define ADC3_EXTSEL_T20CC2 ADC34_CFGR_EXTSEL_T20CC2 +# define ADC3_EXTSEL_T20CC3 ADC34_CFGR_EXTSEL_T20CC3 +# define ADC3_EXTSEL_T20CC4 ADC34_CFGR_EXTSEL_T20CC4 +# define ADC3_EXTSEL_T20TRGO ADC34_CFGR_EXTSEL_T20TRGO +# define ADC4_EXTSEL_T20CC1 ADC34_CFGR_EXTSEL_T20CC1 +# define ADC4_EXTSEL_T20CC2 ADC34_CFGR_EXTSEL_T20CC2 +# define ADC4_EXTSEL_T20CC3 ADC34_CFGR_EXTSEL_T20CC3 +# define ADC4_EXTSEL_T20CC4 ADC34_CFGR_EXTSEL_T20CC4 +# define ADC4_EXTSEL_T20TRGO ADC34_CFGR_EXTSEL_T20TRGO +#else +# define ADC1_EXTSEL_T1CC1 ADC_CR2_EXTSEL_T1CC1 +# define ADC1_EXTSEL_T1CC2 ADC_CR2_EXTSEL_T1CC2 +# define ADC1_EXTSEL_T1CC3 ADC_CR2_EXTSEL_T1CC3 +# define ADC1_EXTSEL_T1CC4 ADC_CR2_EXTSEL_T1CC4 +# define ADC1_EXTSEL_T1TRGO ADC_CR2_EXTSEL_T1TRGO +# define ADC2_EXTSEL_T1CC1 ADC_CR2_EXTSEL_T1CC1 +# define ADC2_EXTSEL_T1CC2 ADC_CR2_EXTSEL_T1CC2 +# define ADC2_EXTSEL_T1CC3 ADC_CR2_EXTSEL_T1CC3 +# define ADC2_EXTSEL_T1CC4 ADC_CR2_EXTSEL_T1CC4 +# define ADC2_EXTSEL_T1TRGO ADC_CR2_EXTSEL_T1TRGO +# define ADC3_EXTSEL_T1CC1 ADC_CR2_EXTSEL_T1CC1 +# define ADC3_EXTSEL_T1CC2 ADC_CR2_EXTSEL_T1CC2 +# define ADC3_EXTSEL_T1CC3 ADC_CR2_EXTSEL_T1CC3 +# define ADC3_EXTSEL_T1CC4 ADC_CR2_EXTSEL_T1CC4 +# define ADC3_EXTSEL_T1TRGO ADC_CR2_EXTSEL_T1TRGO +# define ADC4_EXTSEL_T1CC1 ADC_CR2_EXTSEL_T1CC1 +# define ADC4_EXTSEL_T1CC2 ADC_CR2_EXTSEL_T1CC2 +# define ADC4_EXTSEL_T1CC3 ADC_CR2_EXTSEL_T1CC3 +# define ADC4_EXTSEL_T1CC4 ADC_CR2_EXTSEL_T1CC4 +# define ADC4_EXTSEL_T1TRGO ADC_CR2_EXTSEL_T1TRGO +# define ADC1_EXTSEL_T2CC1 ADC_CR2_EXTSEL_T2CC1 +# define ADC1_EXTSEL_T2CC2 ADC_CR2_EXTSEL_T2CC2 +# define ADC1_EXTSEL_T2CC3 ADC_CR2_EXTSEL_T2CC3 +# define ADC1_EXTSEL_T2CC4 ADC_CR2_EXTSEL_T2CC4 +# define ADC1_EXTSEL_T2TRGO ADC_CR2_EXTSEL_T2TRGO +# define ADC2_EXTSEL_T2CC1 ADC_CR2_EXTSEL_T2CC1 +# define ADC2_EXTSEL_T2CC2 ADC_CR2_EXTSEL_T2CC2 +# define ADC2_EXTSEL_T2CC3 ADC_CR2_EXTSEL_T2CC3 +# define ADC2_EXTSEL_T2CC4 ADC_CR2_EXTSEL_T2CC4 +# define ADC2_EXTSEL_T2TRGO ADC_CR2_EXTSEL_T2TRGO +# define ADC3_EXTSEL_T2CC1 ADC_CR2_EXTSEL_T2CC1 +# define ADC3_EXTSEL_T2CC2 ADC_CR2_EXTSEL_T2CC2 +# define ADC3_EXTSEL_T2CC3 ADC_CR2_EXTSEL_T2CC3 +# define ADC3_EXTSEL_T2CC4 ADC_CR2_EXTSEL_T2CC4 +# define ADC3_EXTSEL_T2TRGO ADC_CR2_EXTSEL_T2TRGO +# define ADC4_EXTSEL_T2CC1 ADC_CR2_EXTSEL_T2CC1 +# define ADC4_EXTSEL_T2CC2 ADC_CR2_EXTSEL_T2CC2 +# define ADC4_EXTSEL_T2CC3 ADC_CR2_EXTSEL_T2CC3 +# define ADC4_EXTSEL_T2CC4 ADC_CR2_EXTSEL_T2CC4 +# define ADC4_EXTSEL_T2TRGO ADC_CR2_EXTSEL_T2TRGO +# define ADC1_EXTSEL_T3CC1 ADC_CR2_EXTSEL_T3CC1 +# define ADC1_EXTSEL_T3CC2 ADC_CR2_EXTSEL_T3CC2 +# define ADC1_EXTSEL_T3CC3 ADC_CR2_EXTSEL_T3CC3 +# define ADC1_EXTSEL_T3CC4 ADC_CR2_EXTSEL_T3CC4 +# define ADC1_EXTSEL_T3TRGO ADC_CR2_EXTSEL_T3TRGO +# define ADC2_EXTSEL_T3CC1 ADC_CR2_EXTSEL_T3CC1 +# define ADC2_EXTSEL_T3CC2 ADC_CR2_EXTSEL_T3CC2 +# define ADC2_EXTSEL_T3CC3 ADC_CR2_EXTSEL_T3CC3 +# define ADC2_EXTSEL_T3CC4 ADC_CR2_EXTSEL_T3CC4 +# define ADC2_EXTSEL_T3TRGO ADC_CR2_EXTSEL_T3TRGO +# define ADC3_EXTSEL_T3CC1 ADC_CR2_EXTSEL_T3CC1 +# define ADC3_EXTSEL_T3CC2 ADC_CR2_EXTSEL_T3CC2 +# define ADC3_EXTSEL_T3CC3 ADC_CR2_EXTSEL_T3CC3 +# define ADC3_EXTSEL_T3CC4 ADC_CR2_EXTSEL_T3CC4 +# define ADC3_EXTSEL_T3TRGO ADC_CR2_EXTSEL_T3TRGO +# define ADC4_EXTSEL_T3CC1 ADC_CR2_EXTSEL_T3CC1 +# define ADC4_EXTSEL_T3CC2 ADC_CR2_EXTSEL_T3CC2 +# define ADC4_EXTSEL_T3CC3 ADC_CR2_EXTSEL_T3CC3 +# define ADC4_EXTSEL_T3CC4 ADC_CR2_EXTSEL_T3CC4 +# define ADC4_EXTSEL_T3TRGO ADC_CR2_EXTSEL_T3TRGO +# define ADC1_EXTSEL_T4CC1 ADC_CR2_EXTSEL_T4CC1 +# define ADC1_EXTSEL_T4CC2 ADC_CR2_EXTSEL_T4CC2 +# define ADC1_EXTSEL_T4CC3 ADC_CR2_EXTSEL_T4CC3 +# define ADC1_EXTSEL_T4CC4 ADC_CR2_EXTSEL_T4CC4 +# define ADC1_EXTSEL_T4TRGO ADC_CR2_EXTSEL_T4TRGO +# define ADC2_EXTSEL_T4CC1 ADC_CR2_EXTSEL_T4CC1 +# define ADC2_EXTSEL_T4CC2 ADC_CR2_EXTSEL_T4CC2 +# define ADC2_EXTSEL_T4CC3 ADC_CR2_EXTSEL_T4CC3 +# define ADC2_EXTSEL_T4CC4 ADC_CR2_EXTSEL_T4CC4 +# define ADC2_EXTSEL_T4TRGO ADC_CR2_EXTSEL_T4TRGO +# define ADC3_EXTSEL_T4CC1 ADC_CR2_EXTSEL_T4CC1 +# define ADC3_EXTSEL_T4CC2 ADC_CR2_EXTSEL_T4CC2 +# define ADC3_EXTSEL_T4CC3 ADC_CR2_EXTSEL_T4CC3 +# define ADC3_EXTSEL_T4CC4 ADC_CR2_EXTSEL_T4CC4 +# define ADC3_EXTSEL_T4TRGO ADC_CR2_EXTSEL_T4TRGO +# define ADC4_EXTSEL_T4CC1 ADC_CR2_EXTSEL_T4CC1 +# define ADC4_EXTSEL_T4CC2 ADC_CR2_EXTSEL_T4CC2 +# define ADC4_EXTSEL_T4CC3 ADC_CR2_EXTSEL_T4CC3 +# define ADC4_EXTSEL_T4CC4 ADC_CR2_EXTSEL_T4CC4 +# define ADC4_EXTSEL_T4TRGO ADC_CR2_EXTSEL_T4TRGO +# define ADC1_EXTSEL_T5CC1 ADC_CR2_EXTSEL_T5CC1 +# define ADC1_EXTSEL_T5CC2 ADC_CR2_EXTSEL_T5CC2 +# define ADC1_EXTSEL_T5CC3 ADC_CR2_EXTSEL_T5CC3 +# define ADC1_EXTSEL_T5CC4 ADC_CR2_EXTSEL_T5CC4 +# define ADC1_EXTSEL_T5TRGO ADC_CR2_EXTSEL_T5TRGO +# define ADC2_EXTSEL_T5CC1 ADC_CR2_EXTSEL_T5CC1 +# define ADC2_EXTSEL_T5CC2 ADC_CR2_EXTSEL_T5CC2 +# define ADC2_EXTSEL_T5CC3 ADC_CR2_EXTSEL_T5CC3 +# define ADC2_EXTSEL_T5CC4 ADC_CR2_EXTSEL_T5CC4 +# define ADC2_EXTSEL_T5TRGO ADC_CR2_EXTSEL_T5TRGO +# define ADC3_EXTSEL_T5CC1 ADC_CR2_EXTSEL_T5CC1 +# define ADC3_EXTSEL_T5CC2 ADC_CR2_EXTSEL_T5CC2 +# define ADC3_EXTSEL_T5CC3 ADC_CR2_EXTSEL_T5CC3 +# define ADC3_EXTSEL_T5CC4 ADC_CR2_EXTSEL_T5CC4 +# define ADC3_EXTSEL_T5TRGO ADC_CR2_EXTSEL_T5TRGO +# define ADC4_EXTSEL_T5CC1 ADC_CR2_EXTSEL_T5CC1 +# define ADC4_EXTSEL_T5CC2 ADC_CR2_EXTSEL_T5CC2 +# define ADC4_EXTSEL_T5CC3 ADC_CR2_EXTSEL_T5CC3 +# define ADC4_EXTSEL_T5CC4 ADC_CR2_EXTSEL_T5CC4 +# define ADC4_EXTSEL_T5TRGO ADC_CR2_EXTSEL_T5TRGO +# define ADC1_EXTSEL_T6CC1 ADC_CR2_EXTSEL_T6CC1 +# define ADC1_EXTSEL_T6CC2 ADC_CR2_EXTSEL_T6CC2 +# define ADC1_EXTSEL_T6CC3 ADC_CR2_EXTSEL_T6CC3 +# define ADC1_EXTSEL_T6CC4 ADC_CR2_EXTSEL_T6CC4 +# define ADC1_EXTSEL_T6TRGO ADC_CR2_EXTSEL_T6TRGO +# define ADC2_EXTSEL_T6CC1 ADC_CR2_EXTSEL_T6CC1 +# define ADC2_EXTSEL_T6CC2 ADC_CR2_EXTSEL_T6CC2 +# define ADC2_EXTSEL_T6CC3 ADC_CR2_EXTSEL_T6CC3 +# define ADC2_EXTSEL_T6CC4 ADC_CR2_EXTSEL_T6CC4 +# define ADC2_EXTSEL_T6TRGO ADC_CR2_EXTSEL_T6TRGO +# define ADC3_EXTSEL_T6CC1 ADC_CR2_EXTSEL_T6CC1 +# define ADC3_EXTSEL_T6CC2 ADC_CR2_EXTSEL_T6CC2 +# define ADC3_EXTSEL_T6CC3 ADC_CR2_EXTSEL_T6CC3 +# define ADC3_EXTSEL_T6CC4 ADC_CR2_EXTSEL_T6CC4 +# define ADC3_EXTSEL_T6TRGO ADC_CR2_EXTSEL_T6TRGO +# define ADC4_EXTSEL_T6CC1 ADC_CR2_EXTSEL_T6CC1 +# define ADC4_EXTSEL_T6CC2 ADC_CR2_EXTSEL_T6CC2 +# define ADC4_EXTSEL_T6CC3 ADC_CR2_EXTSEL_T6CC3 +# define ADC4_EXTSEL_T6CC4 ADC_CR2_EXTSEL_T6CC4 +# define ADC4_EXTSEL_T6TRGO ADC_CR2_EXTSEL_T6TRGO +# define ADC1_EXTSEL_T7CC1 ADC_CR2_EXTSEL_T7CC1 +# define ADC1_EXTSEL_T7CC2 ADC_CR2_EXTSEL_T7CC2 +# define ADC1_EXTSEL_T7CC3 ADC_CR2_EXTSEL_T7CC3 +# define ADC1_EXTSEL_T7CC4 ADC_CR2_EXTSEL_T7CC4 +# define ADC1_EXTSEL_T7TRGO ADC_CR2_EXTSEL_T7TRGO +# define ADC2_EXTSEL_T7CC1 ADC_CR2_EXTSEL_T7CC1 +# define ADC2_EXTSEL_T7CC2 ADC_CR2_EXTSEL_T7CC2 +# define ADC2_EXTSEL_T7CC3 ADC_CR2_EXTSEL_T7CC3 +# define ADC2_EXTSEL_T7CC4 ADC_CR2_EXTSEL_T7CC4 +# define ADC2_EXTSEL_T7TRGO ADC_CR2_EXTSEL_T7TRGO +# define ADC3_EXTSEL_T7CC1 ADC_CR2_EXTSEL_T7CC1 +# define ADC3_EXTSEL_T7CC2 ADC_CR2_EXTSEL_T7CC2 +# define ADC3_EXTSEL_T7CC3 ADC_CR2_EXTSEL_T7CC3 +# define ADC3_EXTSEL_T7CC4 ADC_CR2_EXTSEL_T7CC4 +# define ADC3_EXTSEL_T7TRGO ADC_CR2_EXTSEL_T7TRGO +# define ADC4_EXTSEL_T7CC1 ADC_CR2_EXTSEL_T7CC1 +# define ADC4_EXTSEL_T7CC2 ADC_CR2_EXTSEL_T7CC2 +# define ADC4_EXTSEL_T7CC3 ADC_CR2_EXTSEL_T7CC3 +# define ADC4_EXTSEL_T7CC4 ADC_CR2_EXTSEL_T7CC4 +# define ADC4_EXTSEL_T7TRGO ADC_CR2_EXTSEL_T7TRGO +# define ADC1_EXTSEL_T8CC1 ADC_CR2_EXTSEL_T8CC1 +# define ADC1_EXTSEL_T8CC2 ADC_CR2_EXTSEL_T8CC2 +# define ADC1_EXTSEL_T8CC3 ADC_CR2_EXTSEL_T8CC3 +# define ADC1_EXTSEL_T8CC4 ADC_CR2_EXTSEL_T8CC4 +# define ADC1_EXTSEL_T8TRGO ADC_CR2_EXTSEL_T8TRGO +# define ADC2_EXTSEL_T8CC1 ADC_CR2_EXTSEL_T8CC1 +# define ADC2_EXTSEL_T8CC2 ADC_CR2_EXTSEL_T8CC2 +# define ADC2_EXTSEL_T8CC3 ADC_CR2_EXTSEL_T8CC3 +# define ADC2_EXTSEL_T8CC4 ADC_CR2_EXTSEL_T8CC4 +# define ADC2_EXTSEL_T8TRGO ADC_CR2_EXTSEL_T8TRGO +# define ADC3_EXTSEL_T8CC1 ADC_CR2_EXTSEL_T8CC1 +# define ADC3_EXTSEL_T8CC2 ADC_CR2_EXTSEL_T8CC2 +# define ADC3_EXTSEL_T8CC3 ADC_CR2_EXTSEL_T8CC3 +# define ADC3_EXTSEL_T8CC4 ADC_CR2_EXTSEL_T8CC4 +# define ADC3_EXTSEL_T8TRGO ADC_CR2_EXTSEL_T8TRGO +# define ADC4_EXTSEL_T8CC1 ADC_CR2_EXTSEL_T8CC1 +# define ADC4_EXTSEL_T8CC2 ADC_CR2_EXTSEL_T8CC2 +# define ADC4_EXTSEL_T8CC3 ADC_CR2_EXTSEL_T8CC3 +# define ADC4_EXTSEL_T8CC4 ADC_CR2_EXTSEL_T8CC4 +# define ADC4_EXTSEL_T8TRGO ADC_CR2_EXTSEL_T8TRGO +# define ADC1_EXTSEL_T9CC1 ADC_CR2_EXTSEL_T9CC1 +# define ADC1_EXTSEL_T9CC2 ADC_CR2_EXTSEL_T9CC2 +# define ADC1_EXTSEL_T9CC3 ADC_CR2_EXTSEL_T9CC3 +# define ADC1_EXTSEL_T9CC4 ADC_CR2_EXTSEL_T9CC4 +# define ADC1_EXTSEL_T9TRGO ADC_CR2_EXTSEL_T9TRGO +# define ADC2_EXTSEL_T9CC1 ADC_CR2_EXTSEL_T9CC1 +# define ADC2_EXTSEL_T9CC2 ADC_CR2_EXTSEL_T9CC2 +# define ADC2_EXTSEL_T9CC3 ADC_CR2_EXTSEL_T9CC3 +# define ADC2_EXTSEL_T9CC4 ADC_CR2_EXTSEL_T9CC4 +# define ADC2_EXTSEL_T9TRGO ADC_CR2_EXTSEL_T9TRGO +# define ADC3_EXTSEL_T9CC1 ADC_CR2_EXTSEL_T9CC1 +# define ADC3_EXTSEL_T9CC2 ADC_CR2_EXTSEL_T9CC2 +# define ADC3_EXTSEL_T9CC3 ADC_CR2_EXTSEL_T9CC3 +# define ADC3_EXTSEL_T9CC4 ADC_CR2_EXTSEL_T9CC4 +# define ADC3_EXTSEL_T9TRGO ADC_CR2_EXTSEL_T9TRGO +# define ADC4_EXTSEL_T9CC1 ADC_CR2_EXTSEL_T9CC1 +# define ADC4_EXTSEL_T9CC2 ADC_CR2_EXTSEL_T9CC2 +# define ADC4_EXTSEL_T9CC3 ADC_CR2_EXTSEL_T9CC3 +# define ADC4_EXTSEL_T9CC4 ADC_CR2_EXTSEL_T9CC4 +# define ADC4_EXTSEL_T9TRGO ADC_CR2_EXTSEL_T9TRGO +# define ADC1_EXTSEL_T10CC1 ADC_CR2_EXTSEL_T10CC1 +# define ADC1_EXTSEL_T10CC2 ADC_CR2_EXTSEL_T10CC2 +# define ADC1_EXTSEL_T10CC3 ADC_CR2_EXTSEL_T10CC3 +# define ADC1_EXTSEL_T10CC4 ADC_CR2_EXTSEL_T10CC4 +# define ADC1_EXTSEL_T10TRGO ADC_CR2_EXTSEL_T10TRGO +# define ADC2_EXTSEL_T10CC1 ADC_CR2_EXTSEL_T10CC1 +# define ADC2_EXTSEL_T10CC2 ADC_CR2_EXTSEL_T10CC2 +# define ADC2_EXTSEL_T10CC3 ADC_CR2_EXTSEL_T10CC3 +# define ADC2_EXTSEL_T10CC4 ADC_CR2_EXTSEL_T10CC4 +# define ADC2_EXTSEL_T10TRGO ADC_CR2_EXTSEL_T10TRGO +# define ADC3_EXTSEL_T10CC1 ADC_CR2_EXTSEL_T10CC1 +# define ADC3_EXTSEL_T10CC2 ADC_CR2_EXTSEL_T10CC2 +# define ADC3_EXTSEL_T10CC3 ADC_CR2_EXTSEL_T10CC3 +# define ADC3_EXTSEL_T10CC4 ADC_CR2_EXTSEL_T10CC4 +# define ADC3_EXTSEL_T10TRGO ADC_CR2_EXTSEL_T10TRGO +# define ADC4_EXTSEL_T10CC1 ADC_CR2_EXTSEL_T10CC1 +# define ADC4_EXTSEL_T10CC2 ADC_CR2_EXTSEL_T10CC2 +# define ADC4_EXTSEL_T10CC3 ADC_CR2_EXTSEL_T10CC3 +# define ADC4_EXTSEL_T10CC4 ADC_CR2_EXTSEL_T10CC4 +# define ADC4_EXTSEL_T10TRGO ADC_CR2_EXTSEL_T10TRGO +# define ADC1_EXTSEL_T15CC1 ADC_CR2_EXTSEL_T15CC1 +# define ADC1_EXTSEL_T15CC2 ADC_CR2_EXTSEL_T15CC2 +# define ADC1_EXTSEL_T15CC3 ADC_CR2_EXTSEL_T15CC3 +# define ADC1_EXTSEL_T15CC4 ADC_CR2_EXTSEL_T15CC4 +# define ADC1_EXTSEL_T15TRGO ADC_CR2_EXTSEL_T15TRGO +# define ADC2_EXTSEL_T15CC1 ADC_CR2_EXTSEL_T15CC1 +# define ADC2_EXTSEL_T15CC2 ADC_CR2_EXTSEL_T15CC2 +# define ADC2_EXTSEL_T15CC3 ADC_CR2_EXTSEL_T15CC3 +# define ADC2_EXTSEL_T15CC4 ADC_CR2_EXTSEL_T15CC4 +# define ADC2_EXTSEL_T15TRGO ADC_CR2_EXTSEL_T15TRGO +# define ADC3_EXTSEL_T15CC1 ADC_CR2_EXTSEL_T15CC1 +# define ADC3_EXTSEL_T15CC2 ADC_CR2_EXTSEL_T15CC2 +# define ADC3_EXTSEL_T15CC3 ADC_CR2_EXTSEL_T15CC3 +# define ADC3_EXTSEL_T15CC4 ADC_CR2_EXTSEL_T15CC4 +# define ADC3_EXTSEL_T15TRGO ADC_CR2_EXTSEL_T15TRGO +# define ADC4_EXTSEL_T15CC1 ADC_CR2_EXTSEL_T15CC1 +# define ADC4_EXTSEL_T15CC2 ADC_CR2_EXTSEL_T15CC2 +# define ADC4_EXTSEL_T15CC3 ADC_CR2_EXTSEL_T15CC3 +# define ADC4_EXTSEL_T15CC4 ADC_CR2_EXTSEL_T15CC4 +# define ADC4_EXTSEL_T15TRGO ADC_CR2_EXTSEL_T15TRGO +# define ADC1_EXTSEL_T20CC1 ADC_CR2_EXTSEL_T20CC1 +# define ADC1_EXTSEL_T20CC2 ADC_CR2_EXTSEL_T20CC2 +# define ADC1_EXTSEL_T20CC3 ADC_CR2_EXTSEL_T20CC3 +# define ADC1_EXTSEL_T20CC4 ADC_CR2_EXTSEL_T20CC4 +# define ADC1_EXTSEL_T20TRGO ADC_CR2_EXTSEL_T20TRGO +# define ADC2_EXTSEL_T20CC1 ADC_CR2_EXTSEL_T20CC1 +# define ADC2_EXTSEL_T20CC2 ADC_CR2_EXTSEL_T20CC2 +# define ADC2_EXTSEL_T20CC3 ADC_CR2_EXTSEL_T20CC3 +# define ADC2_EXTSEL_T20CC4 ADC_CR2_EXTSEL_T20CC4 +# define ADC2_EXTSEL_T20TRGO ADC_CR2_EXTSEL_T20TRGO +# define ADC3_EXTSEL_T20CC1 ADC_CR2_EXTSEL_T20CC1 +# define ADC3_EXTSEL_T20CC2 ADC_CR2_EXTSEL_T20CC2 +# define ADC3_EXTSEL_T20CC3 ADC_CR2_EXTSEL_T20CC3 +# define ADC3_EXTSEL_T20CC4 ADC_CR2_EXTSEL_T20CC4 +# define ADC3_EXTSEL_T20TRGO ADC_CR2_EXTSEL_T20TRGO +# define ADC4_EXTSEL_T20CC1 ADC_CR2_EXTSEL_T20CC1 +# define ADC4_EXTSEL_T20CC2 ADC_CR2_EXTSEL_T20CC2 +# define ADC4_EXTSEL_T20CC3 ADC_CR2_EXTSEL_T20CC3 +# define ADC4_EXTSEL_T20CC4 ADC_CR2_EXTSEL_T20CC4 +# define ADC4_EXTSEL_T20TRGO ADC_CR2_EXTSEL_T20TRGO +#endif + #if defined(CONFIG_STM32_TIM1_ADC1) # if CONFIG_STM32_ADC1_TIMTRIG == 0 -# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T1CC1 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T1CC1 # elif CONFIG_STM32_ADC1_TIMTRIG == 1 -# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T1CC2 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T1CC2 # elif CONFIG_STM32_ADC1_TIMTRIG == 2 -# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T1CC3 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T1CC3 # elif CONFIG_STM32_ADC1_TIMTRIG == 3 -# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T1CC4 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T1CC4 # elif CONFIG_STM32_ADC1_TIMTRIG == 4 -# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T1TRGO +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T1TRGO # else # error "CONFIG_STM32_ADC1_TIMTRIG is out of range" # endif #elif defined(CONFIG_STM32_TIM2_ADC1) # if CONFIG_STM32_ADC1_TIMTRIG == 0 -# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T2CC1 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T2CC1 # elif CONFIG_STM32_ADC1_TIMTRIG == 1 -# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T2CC2 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T2CC2 # elif CONFIG_STM32_ADC1_TIMTRIG == 2 -# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T2CC3 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T2CC3 # elif CONFIG_STM32_ADC1_TIMTRIG == 3 -# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T2CC4 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T2CC4 # elif CONFIG_STM32_ADC1_TIMTRIG == 4 -# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T2TRGO +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T2TRGO # else # error "CONFIG_STM32_ADC1_TIMTRIG is out of range" # endif #elif defined(CONFIG_STM32_TIM3_ADC1) # if CONFIG_STM32_ADC1_TIMTRIG == 0 -# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T3CC1 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T3CC1 # elif CONFIG_STM32_ADC1_TIMTRIG == 1 -# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T3CC2 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T3CC2 # elif CONFIG_STM32_ADC1_TIMTRIG == 2 -# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T3CC3 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T3CC3 # elif CONFIG_STM32_ADC1_TIMTRIG == 3 -# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T3CC4 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T3CC4 # elif CONFIG_STM32_ADC1_TIMTRIG == 4 -# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T3TRGO +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T3TRGO # else # error "CONFIG_STM32_ADC1_TIMTRIG is out of range" # endif #elif defined(CONFIG_STM32_TIM4_ADC1) # if CONFIG_STM32_ADC1_TIMTRIG == 0 -# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T4CC1 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T4CC1 # elif CONFIG_STM32_ADC1_TIMTRIG == 1 -# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T4CC2 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T4CC2 # elif CONFIG_STM32_ADC1_TIMTRIG == 2 -# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T4CC3 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T4CC3 # elif CONFIG_STM32_ADC1_TIMTRIG == 3 -# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T4CC4 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T4CC4 # elif CONFIG_STM32_ADC1_TIMTRIG == 4 -# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T4TRGO +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T4TRGO # else # error "CONFIG_STM32_ADC1_TIMTRIG is out of range" # endif #elif defined(CONFIG_STM32_TIM5_ADC1) # if CONFIG_STM32_ADC1_TIMTRIG == 0 -# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T5CC1 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T5CC1 # elif CONFIG_STM32_ADC1_TIMTRIG == 1 -# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T5CC2 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T5CC2 # elif CONFIG_STM32_ADC1_TIMTRIG == 2 -# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T5CC3 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T5CC3 # elif CONFIG_STM32_ADC1_TIMTRIG == 3 -# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T5CC4 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T5CC4 # elif CONFIG_STM32_ADC1_TIMTRIG == 4 -# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T5TRGO +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T5TRGO # else # error "CONFIG_STM32_ADC1_TIMTRIG is out of range" # endif #elif defined(CONFIG_STM32_TIM6_ADC1) # if CONFIG_STM32_ADC1_TIMTRIG == 0 -# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T5CC1 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T6CC1 # elif CONFIG_STM32_ADC1_TIMTRIG == 1 -# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T5CC2 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T6CC2 # elif CONFIG_STM32_ADC1_TIMTRIG == 2 -# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T5CC3 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T6CC3 # elif CONFIG_STM32_ADC1_TIMTRIG == 3 -# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T5CC4 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T6CC4 # elif CONFIG_STM32_ADC1_TIMTRIG == 4 -# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T5TRGO +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T6TRGO # else # error "CONFIG_STM32_ADC1_TIMTRIG is out of range" # endif #elif defined(CONFIG_STM32_TIM7_ADC1) # if CONFIG_STM32_ADC1_TIMTRIG == 0 -# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T5CC1 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T7CC1 # elif CONFIG_STM32_ADC1_TIMTRIG == 1 -# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T5CC2 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T7CC2 # elif CONFIG_STM32_ADC1_TIMTRIG == 2 -# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T5CC3 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T7CC3 # elif CONFIG_STM32_ADC1_TIMTRIG == 3 -# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T5CC4 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T7CC4 # elif CONFIG_STM32_ADC1_TIMTRIG == 4 -# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T5TRGO +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T7TRGO # else # error "CONFIG_STM32_ADC1_TIMTRIG is out of range" # endif #elif defined(CONFIG_STM32_TIM8_ADC1) # if CONFIG_STM32_ADC1_TIMTRIG == 0 -# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T8CC1 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T8CC1 # elif CONFIG_STM32_ADC1_TIMTRIG == 1 -# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T8CC2 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T8CC2 # elif CONFIG_STM32_ADC1_TIMTRIG == 2 -# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T8CC3 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T8CC3 # elif CONFIG_STM32_ADC1_TIMTRIG == 3 -# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T8CC4 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T8CC4 # elif CONFIG_STM32_ADC1_TIMTRIG == 4 -# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T8TRGO +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T8TRGO # else # error "CONFIG_STM32_ADC1_TIMTRIG is out of range" # endif #elif defined(CONFIG_STM32_TIM9_ADC1) # if CONFIG_STM32_ADC1_TIMTRIG == 0 -# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T8CC1 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T9CC1 # elif CONFIG_STM32_ADC1_TIMTRIG == 1 -# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T8CC2 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T9CC2 # elif CONFIG_STM32_ADC1_TIMTRIG == 2 -# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T8CC3 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T9CC3 # elif CONFIG_STM32_ADC1_TIMTRIG == 3 -# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T8CC4 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T9CC4 # elif CONFIG_STM32_ADC1_TIMTRIG == 4 -# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T8TRGO +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T9TRGO # else # error "CONFIG_STM32_ADC1_TIMTRIG is out of range" # endif #elif defined(CONFIG_STM32_TIM10_ADC1) # if CONFIG_STM32_ADC1_TIMTRIG == 0 -# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T8CC1 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T10CC1 # elif CONFIG_STM32_ADC1_TIMTRIG == 1 -# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T8CC2 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T10CC2 # elif CONFIG_STM32_ADC1_TIMTRIG == 2 -# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T8CC3 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T10CC3 # elif CONFIG_STM32_ADC1_TIMTRIG == 3 -# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T8CC4 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T10CC4 # elif CONFIG_STM32_ADC1_TIMTRIG == 4 -# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T8TRGO +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T10TRGO +# else +# error "CONFIG_STM32_ADC1_TIMTRIG is out of range" +# endif +#elif defined(CONFIG_STM32_TIM15_ADC1) +# if CONFIG_STM32_ADC1_TIMTRIG == 0 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T15CC1 +# elif CONFIG_STM32_ADC1_TIMTRIG == 1 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T15CC2 +# elif CONFIG_STM32_ADC1_TIMTRIG == 2 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T15CC3 +# elif CONFIG_STM32_ADC1_TIMTRIG == 3 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T15CC4 +# elif CONFIG_STM32_ADC1_TIMTRIG == 4 +# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T15TRGO # else # error "CONFIG_STM32_ADC1_TIMTRIG is out of range" # endif @@ -545,85 +1189,113 @@ #if defined(CONFIG_STM32_TIM1_ADC2) # if CONFIG_STM32_ADC2_TIMTRIG == 0 -# define ADC2_EXTSEL_VALUE ADC_CR2_EXTSEL_T1CC1 +# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T1CC1 # elif CONFIG_STM32_ADC2_TIMTRIG == 1 -# define ADC2_EXTSEL_VALUE ADC_CR2_EXTSEL_T1CC2 +# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T1CC2 # elif CONFIG_STM32_ADC2_TIMTRIG == 2 -# define ADC2_EXTSEL_VALUE ADC_CR2_EXTSEL_T1CC3 +# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T1CC3 # elif CONFIG_STM32_ADC2_TIMTRIG == 3 -# define ADC2_EXTSEL_VALUE ADC_CR2_EXTSEL_T1CC4 +# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T1CC4 # elif CONFIG_STM32_ADC2_TIMTRIG == 4 -# define ADC2_EXTSEL_VALUE ADC_CR2_EXTSEL_T1TRGO +# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T1TRGO # else # error "CONFIG_STM32_ADC2_TIMTRIG is out of range" # endif #elif defined(CONFIG_STM32_TIM2_ADC2) # if CONFIG_STM32_ADC2_TIMTRIG == 0 -# define ADC2_EXTSEL_VALUE ADC_CR2_EXTSEL_T2CC1 +# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T2CC1 # elif CONFIG_STM32_ADC2_TIMTRIG == 1 -# define ADC2_EXTSEL_VALUE ADC_CR2_EXTSEL_T2CC2 +# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T2CC2 # elif CONFIG_STM32_ADC2_TIMTRIG == 2 -# define ADC2_EXTSEL_VALUE ADC_CR2_EXTSEL_T2CC3 +# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T2CC3 # elif CONFIG_STM32_ADC2_TIMTRIG == 3 -# define ADC2_EXTSEL_VALUE ADC_CR2_EXTSEL_T2CC4 +# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T2CC4 # elif CONFIG_STM32_ADC2_TIMTRIG == 4 -# define ADC2_EXTSEL_VALUE ADC_CR2_EXTSEL_T2TRGO +# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T2TRGO # else # error "CONFIG_STM32_ADC2_TIMTRIG is out of range" # endif #elif defined(CONFIG_STM32_TIM3_ADC2) # if CONFIG_STM32_ADC2_TIMTRIG == 0 -# define ADC2_EXTSEL_VALUE ADC_CR2_EXTSEL_T3CC1 +# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T3CC1 # elif CONFIG_STM32_ADC2_TIMTRIG == 1 -# define ADC2_EXTSEL_VALUE ADC_CR2_EXTSEL_T3CC2 +# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T3CC2 # elif CONFIG_STM32_ADC2_TIMTRIG == 2 -# define ADC2_EXTSEL_VALUE ADC_CR2_EXTSEL_T3CC3 +# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T3CC3 # elif CONFIG_STM32_ADC2_TIMTRIG == 3 -# define ADC2_EXTSEL_VALUE ADC_CR2_EXTSEL_T3CC4 +# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T3CC4 # elif CONFIG_STM32_ADC2_TIMTRIG == 4 -# define ADC2_EXTSEL_VALUE ADC_CR2_EXTSEL_T3TRGO +# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T3TRGO # else # error "CONFIG_STM32_ADC2_TIMTRIG is out of range" # endif #elif defined(CONFIG_STM32_TIM4_ADC2) # if CONFIG_STM32_ADC2_TIMTRIG == 0 -# define ADC2_EXTSEL_VALUE ADC_CR2_EXTSEL_T4CC1 +# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T4CC1 # elif CONFIG_STM32_ADC2_TIMTRIG == 1 -# define ADC2_EXTSEL_VALUE ADC_CR2_EXTSEL_T4CC2 +# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T4CC2 # elif CONFIG_STM32_ADC2_TIMTRIG == 2 -# define ADC2_EXTSEL_VALUE ADC_CR2_EXTSEL_T4CC3 +# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T4CC3 # elif CONFIG_STM32_ADC2_TIMTRIG == 3 -# define ADC2_EXTSEL_VALUE ADC_CR2_EXTSEL_T4CC4 +# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T4CC4 # elif CONFIG_STM32_ADC2_TIMTRIG == 4 -# define ADC2_EXTSEL_VALUE ADC_CR2_EXTSEL_T4TRGO +# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T4TRGO # else # error "CONFIG_STM32_ADC2_TIMTRIG is out of range" # endif #elif defined(CONFIG_STM32_TIM5_ADC2) # if CONFIG_STM32_ADC2_TIMTRIG == 0 -# define ADC2_EXTSEL_VALUE ADC_CR2_EXTSEL_T5CC1 +# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T5CC1 # elif CONFIG_STM32_ADC2_TIMTRIG == 1 -# define ADC2_EXTSEL_VALUE ADC_CR2_EXTSEL_T5CC2 +# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T5CC2 # elif CONFIG_STM32_ADC2_TIMTRIG == 2 -# define ADC2_EXTSEL_VALUE ADC_CR2_EXTSEL_T5CC3 +# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T5CC3 # elif CONFIG_STM32_ADC2_TIMTRIG == 3 -# define ADC2_EXTSEL_VALUE ADC_CR2_EXTSEL_T5CC4 +# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T5CC4 # elif CONFIG_STM32_ADC2_TIMTRIG == 4 -# define ADC2_EXTSEL_VALUE ADC_CR2_EXTSEL_T5TRGO +# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T5TRGO +# else +# error "CONFIG_STM32_ADC2_TIMTRIG is out of range" +# endif +#elif defined(CONFIG_STM32_TIM6_ADC2) +# if CONFIG_STM32_ADC2_TIMTRIG == 0 +# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T6CC1 +# elif CONFIG_STM32_ADC2_TIMTRIG == 1 +# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T6CC2 +# elif CONFIG_STM32_ADC2_TIMTRIG == 2 +# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T6CC3 +# elif CONFIG_STM32_ADC2_TIMTRIG == 3 +# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T6CC4 +# elif CONFIG_STM32_ADC2_TIMTRIG == 4 +# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T6TRGO # else # error "CONFIG_STM32_ADC2_TIMTRIG is out of range" # endif #elif defined(CONFIG_STM32_TIM8_ADC2) # if CONFIG_STM32_ADC2_TIMTRIG == 0 -# define ADC2_EXTSEL_VALUE ADC_CR2_EXTSEL_T8CC1 +# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T8CC1 # elif CONFIG_STM32_ADC2_TIMTRIG == 1 -# define ADC2_EXTSEL_VALUE ADC_CR2_EXTSEL_T8CC2 +# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T8CC2 # elif CONFIG_STM32_ADC2_TIMTRIG == 2 -# define ADC2_EXTSEL_VALUE ADC_CR2_EXTSEL_T8CC3 +# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T8CC3 # elif CONFIG_STM32_ADC2_TIMTRIG == 3 -# define ADC2_EXTSEL_VALUE ADC_CR2_EXTSEL_T8CC4 +# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T8CC4 # elif CONFIG_STM32_ADC2_TIMTRIG == 4 -# define ADC2_EXTSEL_VALUE ADC_CR2_EXTSEL_T8TRGO +# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T8TRGO +# else +# error "CONFIG_STM32_ADC2_TIMTRIG is out of range" +# endif +#elif defined(CONFIG_STM32_TIM15_ADC2) +# if CONFIG_STM32_ADC2_TIMTRIG == 0 +# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T15CC1 +# elif CONFIG_STM32_ADC2_TIMTRIG == 1 +# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T15CC2 +# elif CONFIG_STM32_ADC2_TIMTRIG == 2 +# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T15CC3 +# elif CONFIG_STM32_ADC2_TIMTRIG == 3 +# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T15CC4 +# elif CONFIG_STM32_ADC2_TIMTRIG == 4 +# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T15TRGO # else # error "CONFIG_STM32_ADC2_TIMTRIG is out of range" # endif @@ -631,88 +1303,258 @@ #if defined(CONFIG_STM32_TIM1_ADC3) # if CONFIG_STM32_ADC3_TIMTRIG == 0 -# define ADC3_EXTSEL_VALUE ADC_CR2_EXTSEL_T1CC1 +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T1CC1 # elif CONFIG_STM32_ADC3_TIMTRIG == 1 -# define ADC3_EXTSEL_VALUE ADC_CR2_EXTSEL_T1CC2 +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T1CC2 # elif CONFIG_STM32_ADC3_TIMTRIG == 2 -# define ADC3_EXTSEL_VALUE ADC_CR2_EXTSEL_T1CC3 +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T1CC3 # elif CONFIG_STM32_ADC3_TIMTRIG == 3 -# define ADC3_EXTSEL_VALUE ADC_CR2_EXTSEL_T1CC4 +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T1CC4 # elif CONFIG_STM32_ADC3_TIMTRIG == 4 -# define ADC3_EXTSEL_VALUE ADC_CR2_EXTSEL_T1TRGO +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T1TRGO # else # error "CONFIG_STM32_ADC3_TIMTRIG is out of range" # endif #elif defined(CONFIG_STM32_TIM2_ADC3) # if CONFIG_STM32_ADC3_TIMTRIG == 0 -# define ADC3_EXTSEL_VALUE ADC_CR2_EXTSEL_T2CC1 +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T2CC1 # elif CONFIG_STM32_ADC3_TIMTRIG == 1 -# define ADC3_EXTSEL_VALUE ADC_CR2_EXTSEL_T2CC2 +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T2CC2 # elif CONFIG_STM32_ADC3_TIMTRIG == 2 -# define ADC3_EXTSEL_VALUE ADC_CR2_EXTSEL_T2CC3 +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T2CC3 # elif CONFIG_STM32_ADC3_TIMTRIG == 3 -# define ADC3_EXTSEL_VALUE ADC_CR2_EXTSEL_T2CC4 +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T2CC4 # elif CONFIG_STM32_ADC3_TIMTRIG == 4 -# define ADC3_EXTSEL_VALUE ADC_CR2_EXTSEL_T2TRGO +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T2TRGO # else # error "CONFIG_STM32_ADC3_TIMTRIG is out of range" # endif #elif defined(CONFIG_STM32_TIM3_ADC3) # if CONFIG_STM32_ADC3_TIMTRIG == 0 -# define ADC3_EXTSEL_VALUE ADC_CR2_EXTSEL_T3CC1 +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T3CC1 # elif CONFIG_STM32_ADC3_TIMTRIG == 1 -# define ADC3_EXTSEL_VALUE ADC_CR2_EXTSEL_T3CC2 +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T3CC2 # elif CONFIG_STM32_ADC3_TIMTRIG == 2 -# define ADC3_EXTSEL_VALUE ADC_CR2_EXTSEL_T3CC3 +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T3CC3 # elif CONFIG_STM32_ADC3_TIMTRIG == 3 -# define ADC3_EXTSEL_VALUE ADC_CR2_EXTSEL_T3CC4 +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T3CC4 # elif CONFIG_STM32_ADC3_TIMTRIG == 4 -# define ADC3_EXTSEL_VALUE ADC_CR2_EXTSEL_T3TRGO +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T3TRGO # else # error "CONFIG_STM32_ADC3_TIMTRIG is out of range" # endif #elif defined(CONFIG_STM32_TIM4_ADC3) # if CONFIG_STM32_ADC3_TIMTRIG == 0 -# define ADC3_EXTSEL_VALUE ADC_CR2_EXTSEL_T4CC1 +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T4CC1 # elif CONFIG_STM32_ADC3_TIMTRIG == 1 -# define ADC3_EXTSEL_VALUE ADC_CR2_EXTSEL_T4CC2 +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T4CC2 # elif CONFIG_STM32_ADC3_TIMTRIG == 2 -# define ADC3_EXTSEL_VALUE ADC_CR2_EXTSEL_T4CC3 +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T4CC3 # elif CONFIG_STM32_ADC3_TIMTRIG == 3 -# define ADC3_EXTSEL_VALUE ADC_CR2_EXTSEL_T4CC4 +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T4CC4 # elif CONFIG_STM32_ADC3_TIMTRIG == 4 -# define ADC3_EXTSEL_VALUE ADC_CR2_EXTSEL_T4TRGO +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T4TRGO # else # error "CONFIG_STM32_ADC3_TIMTRIG is out of range" # endif #elif defined(CONFIG_STM32_TIM5_ADC3) # if CONFIG_STM32_ADC3_TIMTRIG == 0 -# define ADC3_EXTSEL_VALUE ADC_CR2_EXTSEL_T5CC1 +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T5CC1 # elif CONFIG_STM32_ADC3_TIMTRIG == 1 -# define ADC3_EXTSEL_VALUE ADC_CR2_EXTSEL_T5CC2 +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T5CC2 # elif CONFIG_STM32_ADC3_TIMTRIG == 2 -# define ADC3_EXTSEL_VALUE ADC_CR2_EXTSEL_T5CC3 +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T5CC3 # elif CONFIG_STM32_ADC3_TIMTRIG == 3 -# define ADC3_EXTSEL_VALUE ADC_CR2_EXTSEL_T5CC4 +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T5CC4 # elif CONFIG_STM32_ADC3_TIMTRIG == 4 -# define ADC3_EXTSEL_VALUE ADC_CR2_EXTSEL_T5TRGO +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T5TRGO +# else +# error "CONFIG_STM32_ADC3_TIMTRIG is out of range" +# endif +#elif defined(CONFIG_STM32_TIM7_ADC3) +# if CONFIG_STM32_ADC3_TIMTRIG == 0 +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T7CC1 +# elif CONFIG_STM32_ADC3_TIMTRIG == 1 +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T7CC2 +# elif CONFIG_STM32_ADC3_TIMTRIG == 2 +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T7CC3 +# elif CONFIG_STM32_ADC3_TIMTRIG == 3 +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T7CC4 +# elif CONFIG_STM32_ADC3_TIMTRIG == 4 +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T7TRGO # else # error "CONFIG_STM32_ADC3_TIMTRIG is out of range" # endif #elif defined(CONFIG_STM32_TIM8_ADC3) # if CONFIG_STM32_ADC3_TIMTRIG == 0 -# define ADC3_EXTSEL_VALUE ADC_CR2_EXTSEL_T8CC1 +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T8CC1 # elif CONFIG_STM32_ADC3_TIMTRIG == 1 -# define ADC3_EXTSEL_VALUE ADC_CR2_EXTSEL_T8CC2 +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T8CC2 # elif CONFIG_STM32_ADC3_TIMTRIG == 2 -# define ADC3_EXTSEL_VALUE ADC_CR2_EXTSEL_T8CC3 +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T8CC3 # elif CONFIG_STM32_ADC3_TIMTRIG == 3 -# define ADC3_EXTSEL_VALUE ADC_CR2_EXTSEL_T8CC4 +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T8CC4 # elif CONFIG_STM32_ADC3_TIMTRIG == 4 -# define ADC3_EXTSEL_VALUE ADC_CR2_EXTSEL_T8TRGO +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T8TRGO # else # error "CONFIG_STM32_ADC3_TIMTRIG is out of range" # endif +#elif defined(CONFIG_STM32_TIM15_ADC3) +# if CONFIG_STM32_ADC3_TIMTRIG == 0 +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T15CC1 +# elif CONFIG_STM32_ADC3_TIMTRIG == 1 +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T15CC2 +# elif CONFIG_STM32_ADC3_TIMTRIG == 2 +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T15CC3 +# elif CONFIG_STM32_ADC3_TIMTRIG == 3 +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T15CC4 +# elif CONFIG_STM32_ADC3_TIMTRIG == 4 +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T15TRGO +# else +# error "CONFIG_STM32_ADC3_TIMTRIG is out of range" +# endif +#elif defined(CONFIG_STM32_TIM20_ADC3) +# if CONFIG_STM32_ADC3_TIMTRIG == 0 +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T20CC1 +# elif CONFIG_STM32_ADC3_TIMTRIG == 1 +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T20CC2 +# elif CONFIG_STM32_ADC3_TIMTRIG == 2 +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T20CC3 +# elif CONFIG_STM32_ADC3_TIMTRIG == 3 +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T20CC4 +# elif CONFIG_STM32_ADC3_TIMTRIG == 4 +# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T20TRGO +# else +# error "CONFIG_STM32_ADC3_TIMTRIG is out of range" +# endif +#endif + +#if defined(CONFIG_STM32_TIM1_ADC4) +# if CONFIG_STM32_ADC4_TIMTRIG == 0 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T1CC1 +# elif CONFIG_STM32_ADC4_TIMTRIG == 1 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T1CC2 +# elif CONFIG_STM32_ADC4_TIMTRIG == 2 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T1CC3 +# elif CONFIG_STM32_ADC4_TIMTRIG == 3 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T1CC4 +# elif CONFIG_STM32_ADC4_TIMTRIG == 4 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T1TRGO +# else +# error "CONFIG_STM32_ADC4_TIMTRIG is out of range" +# endif +#elif defined(CONFIG_STM32_TIM2_ADC4) +# if CONFIG_STM32_ADC4_TIMTRIG == 0 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T2CC1 +# elif CONFIG_STM32_ADC4_TIMTRIG == 1 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T2CC2 +# elif CONFIG_STM32_ADC4_TIMTRIG == 2 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T2CC3 +# elif CONFIG_STM32_ADC4_TIMTRIG == 3 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T2CC4 +# elif CONFIG_STM32_ADC4_TIMTRIG == 4 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T2TRGO +# else +# error "CONFIG_STM32_ADC4_TIMTRIG is out of range" +# endif +#elif defined(CONFIG_STM32_TIM3_ADC4) +# if CONFIG_STM32_ADC4_TIMTRIG == 0 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T3CC1 +# elif CONFIG_STM32_ADC4_TIMTRIG == 1 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T3CC2 +# elif CONFIG_STM32_ADC4_TIMTRIG == 2 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T3CC3 +# elif CONFIG_STM32_ADC4_TIMTRIG == 3 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T3CC4 +# elif CONFIG_STM32_ADC4_TIMTRIG == 4 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T3TRGO +# else +# error "CONFIG_STM32_ADC4_TIMTRIG is out of range" +# endif +#elif defined(CONFIG_STM32_TIM4_ADC4) +# if CONFIG_STM32_ADC4_TIMTRIG == 0 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T4CC1 +# elif CONFIG_STM32_ADC4_TIMTRIG == 1 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T4CC2 +# elif CONFIG_STM32_ADC4_TIMTRIG == 2 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T4CC3 +# elif CONFIG_STM32_ADC4_TIMTRIG == 3 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T4CC4 +# elif CONFIG_STM32_ADC4_TIMTRIG == 4 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T4TRGO +# else +# error "CONFIG_STM32_ADC4_TIMTRIG is out of range" +# endif +#elif defined(CONFIG_STM32_TIM5_ADC4) +# if CONFIG_STM32_ADC4_TIMTRIG == 0 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T5CC1 +# elif CONFIG_STM32_ADC4_TIMTRIG == 1 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T5CC2 +# elif CONFIG_STM32_ADC4_TIMTRIG == 2 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T5CC3 +# elif CONFIG_STM32_ADC4_TIMTRIG == 3 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T5CC4 +# elif CONFIG_STM32_ADC4_TIMTRIG == 4 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T5TRGO +# else +# error "CONFIG_STM32_ADC4_TIMTRIG is out of range" +# endif +#elif defined(CONFIG_STM32_TIM7_ADC4) +# if CONFIG_STM32_ADC4_TIMTRIG == 0 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T7CC1 +# elif CONFIG_STM32_ADC4_TIMTRIG == 1 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T7CC2 +# elif CONFIG_STM32_ADC4_TIMTRIG == 2 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T7CC3 +# elif CONFIG_STM32_ADC4_TIMTRIG == 3 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T7CC4 +# elif CONFIG_STM32_ADC4_TIMTRIG == 4 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T7TRGO +# else +# error "CONFIG_STM32_ADC4_TIMTRIG is out of range" +# endif +#elif defined(CONFIG_STM32_TIM8_ADC4) +# if CONFIG_STM32_ADC4_TIMTRIG == 0 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T8CC1 +# elif CONFIG_STM32_ADC4_TIMTRIG == 1 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T8CC2 +# elif CONFIG_STM32_ADC4_TIMTRIG == 2 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T8CC3 +# elif CONFIG_STM32_ADC4_TIMTRIG == 3 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T8CC4 +# elif CONFIG_STM32_ADC4_TIMTRIG == 4 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T8TRGO +# else +# error "CONFIG_STM32_ADC4_TIMTRIG is out of range" +# endif +#elif defined(CONFIG_STM32_TIM15_ADC4) +# if CONFIG_STM32_ADC4_TIMTRIG == 0 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T15CC1 +# elif CONFIG_STM32_ADC4_TIMTRIG == 1 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T15CC2 +# elif CONFIG_STM32_ADC4_TIMTRIG == 2 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T15CC3 +# elif CONFIG_STM32_ADC4_TIMTRIG == 3 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T15CC4 +# elif CONFIG_STM32_ADC4_TIMTRIG == 4 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T15TRGO +# else +# error "CONFIG_STM32_ADC4_TIMTRIG is out of range" +# endif +#elif defined(CONFIG_STM32_TIM20_ADC4) +# if CONFIG_STM32_ADC4_TIMTRIG == 0 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T20CC1 +# elif CONFIG_STM32_ADC4_TIMTRIG == 1 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T20CC2 +# elif CONFIG_STM32_ADC4_TIMTRIG == 2 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T20CC3 +# elif CONFIG_STM32_ADC4_TIMTRIG == 3 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T20CC4 +# elif CONFIG_STM32_ADC4_TIMTRIG == 4 +# define ADC4_EXTSEL_VALUE ADC4_EXTSEL_T20TRGO +# else +# error "CONFIG_STM32_ADC4_TIMTRIG is out of range" +# endif #endif /************************************************************************************ @@ -740,7 +1582,7 @@ typedef enum ADC_IO_CMDS typedef struct adc_channel_s { - uint8_t channel : 5; + uint8_t channel:5; /* Sampling time individually for each channel * 000: 4 cycles @@ -753,19 +1595,20 @@ typedef struct adc_channel_s * 111: 384 cycles - selected for all channels */ - uint8_t sample_time : 3; + uint8_t sample_time:3; } adc_channel_t; /* This structure will be used while setting channels to specified by the * "channel-sample time" pairs' values */ -struct adc_sample_time_s { - adc_channel_t *channel; /* array of channels */ - uint8_t channels_nbr:5; /* number of channels in array */ - bool all_same:1; /* All 32 channels will get the +struct adc_sample_time_s +{ + adc_channel_t *channel; /* Array of channels */ + uint8_t channels_nbr:5; /* Number of channels in array */ + bool all_same:1; /* All 32 channels will get the * same value of the sample time */ - uint8_t all_ch_sample_time:3; /* Sample time for all 32 channels */ + uint8_t all_ch_sample_time:3; /* Sample time for all 32 channels */ }; #endif @@ -814,5 +1657,7 @@ void stm32_adcchange_sample_time(FAR struct adc_dev_s *dev, #endif #endif /* __ASSEMBLY__ */ -#endif /* CONFIG_STM32_ADC || CONFIG_STM32_ADC2 || CONFIG_STM32_ADC3 */ +#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 || + * CONFIG_STM32_ADC3 || CONFIG_STM32_ADC4 + */ #endif /* __ARCH_ARM_SRC_STM32_STM32_ADC_H */