From f1ff5abddf846cc70c8f8ddc752169339ea531cd Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Fri, 29 May 2026 16:28:52 +0200 Subject: [PATCH] !arm/stm32wb: standardize public API/type prefix to stm32_ BREAKING CHANGE: Public STM32WB interfaces were renamed from stm32wb_* forms to canonical stm32_* forms across arch and board headers/sources. Public type names in STM32WB timer/dma/freerun/oneshot/GPIO/EXTI and related API-facing declarations were normalized to stm32_* equivalents. The STM32WB root family header was renamed from stm32wb.h to stm32.h; all STM32WB arch/board includes were updated accordingly. Signed-off-by: raiden00pl --- arch/arm/src/stm32wb/{stm32wb.h => stm32.h} | 2 +- arch/arm/src/stm32wb/stm32wb_allocateheap.c | 6 +- arch/arm/src/stm32wb/stm32wb_blehci.c | 62 +- arch/arm/src/stm32wb/stm32wb_blehci.h | 4 +- arch/arm/src/stm32wb/stm32wb_dma.c | 196 +++--- arch/arm/src/stm32wb/stm32wb_dma.h | 60 +- arch/arm/src/stm32wb/stm32wb_dumpgpio.c | 4 +- arch/arm/src/stm32wb/stm32wb_exti.h | 12 +- arch/arm/src/stm32wb/stm32wb_exti_alarm.c | 10 +- arch/arm/src/stm32wb/stm32wb_exti_gpio.c | 40 +- arch/arm/src/stm32wb/stm32wb_exti_pwr.c | 10 +- arch/arm/src/stm32wb/stm32wb_exti_wakeup.c | 10 +- arch/arm/src/stm32wb/stm32wb_flash.c | 16 +- arch/arm/src/stm32wb/stm32wb_flash.h | 8 +- arch/arm/src/stm32wb/stm32wb_freerun.c | 32 +- arch/arm/src/stm32wb/stm32wb_freerun.h | 26 +- arch/arm/src/stm32wb/stm32wb_gpio.c | 28 +- arch/arm/src/stm32wb/stm32wb_gpio.h | 36 +- arch/arm/src/stm32wb/stm32wb_i2c.c | 516 ++++++++-------- arch/arm/src/stm32wb/stm32wb_i2c.h | 10 +- arch/arm/src/stm32wb/stm32wb_idle.c | 6 +- arch/arm/src/stm32wb/stm32wb_ipcc.c | 8 +- arch/arm/src/stm32wb/stm32wb_ipcc.h | 36 +- arch/arm/src/stm32wb/stm32wb_irq.c | 38 +- arch/arm/src/stm32wb/stm32wb_lowputc.c | 20 +- arch/arm/src/stm32wb/stm32wb_lowputc.h | 4 +- arch/arm/src/stm32wb/stm32wb_mbox.c | 330 +++++----- arch/arm/src/stm32wb/stm32wb_mbox.h | 32 +- arch/arm/src/stm32wb/stm32wb_mbox_list.h | 36 +- arch/arm/src/stm32wb/stm32wb_mbox_shci.h | 2 +- arch/arm/src/stm32wb/stm32wb_mpuinit.c | 8 +- arch/arm/src/stm32wb/stm32wb_mpuinit.h | 12 +- arch/arm/src/stm32wb/stm32wb_oneshot.c | 42 +- arch/arm/src/stm32wb/stm32wb_oneshot.h | 28 +- .../src/stm32wb/stm32wb_oneshot_lowerhalf.c | 78 +-- arch/arm/src/stm32wb/stm32wb_pm.h | 20 +- arch/arm/src/stm32wb/stm32wb_pmlpr.c | 4 +- arch/arm/src/stm32wb/stm32wb_pmsleep.c | 4 +- arch/arm/src/stm32wb/stm32wb_pmstandby.c | 4 +- arch/arm/src/stm32wb/stm32wb_pmstop.c | 8 +- arch/arm/src/stm32wb/stm32wb_pwr.c | 26 +- arch/arm/src/stm32wb/stm32wb_pwr.h | 8 +- arch/arm/src/stm32wb/stm32wb_rcc.c | 40 +- arch/arm/src/stm32wb/stm32wb_rcc.h | 42 +- arch/arm/src/stm32wb/stm32wb_rcc_hsi48.c | 8 +- arch/arm/src/stm32wb/stm32wb_rcc_lse.c | 10 +- arch/arm/src/stm32wb/stm32wb_rcc_lsi.c | 8 +- arch/arm/src/stm32wb/stm32wb_rtc.c | 90 +-- arch/arm/src/stm32wb/stm32wb_rtc.h | 42 +- arch/arm/src/stm32wb/stm32wb_rtc_lowerhalf.c | 152 ++--- arch/arm/src/stm32wb/stm32wb_serial.c | 574 +++++++++--------- arch/arm/src/stm32wb/stm32wb_spi.c | 166 ++--- arch/arm/src/stm32wb/stm32wb_spi.h | 40 +- arch/arm/src/stm32wb/stm32wb_start.c | 12 +- arch/arm/src/stm32wb/stm32wb_start.h | 4 +- arch/arm/src/stm32wb/stm32wb_tickless.c | 94 +-- arch/arm/src/stm32wb/stm32wb_tim.c | 436 ++++++------- arch/arm/src/stm32wb/stm32wb_tim.h | 60 +- arch/arm/src/stm32wb/stm32wb_tim_lowerhalf.c | 84 +-- arch/arm/src/stm32wb/stm32wb_timerisr.c | 6 +- arch/arm/src/stm32wb/stm32wb_uart.h | 4 +- arch/arm/src/stm32wb/stm32wb_uid.c | 2 +- arch/arm/src/stm32wb/stm32wb_uid.h | 2 +- arch/arm/src/stm32wb/stm32wb_userspace.c | 6 +- arch/arm/src/stm32wb/stm32wb_userspace.h | 4 +- arch/arm/src/stm32wb/stm32wb_waste.c | 2 +- arch/arm/src/stm32wb/stm32wb_waste.h | 4 +- .../arm/stm32wb/flipperzero/include/board.h | 4 +- .../arm/stm32wb/flipperzero/src/flipperzero.h | 4 +- .../arm/stm32wb/flipperzero/src/stm32_boot.c | 16 +- .../flipperzero/src/stm32_lcd_st7565.c | 54 +- .../arm/stm32wb/flipperzero/src/stm32_spi.c | 28 +- .../arm/stm32wb/nucleo-wb55rg/include/board.h | 4 +- .../nucleo-wb55rg/src/stm32_autoleds.c | 20 +- .../stm32wb/nucleo-wb55rg/src/stm32_boot.c | 12 +- .../nucleo-wb55rg/src/stm32_userleds.c | 32 +- 76 files changed, 1954 insertions(+), 1954 deletions(-) rename arch/arm/src/stm32wb/{stm32wb.h => stm32.h} (98%) diff --git a/arch/arm/src/stm32wb/stm32wb.h b/arch/arm/src/stm32wb/stm32.h similarity index 98% rename from arch/arm/src/stm32wb/stm32wb.h rename to arch/arm/src/stm32wb/stm32.h index 25327d74d90..539f3eb9ea4 100644 --- a/arch/arm/src/stm32wb/stm32wb.h +++ b/arch/arm/src/stm32wb/stm32.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32wb/stm32wb.h + * arch/arm/src/stm32wb/stm32.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32wb/stm32wb_allocateheap.c b/arch/arm/src/stm32wb/stm32wb_allocateheap.c index fb2f6dc9451..d22ff6b51de 100644 --- a/arch/arm/src/stm32wb/stm32wb_allocateheap.c +++ b/arch/arm/src/stm32wb/stm32wb_allocateheap.c @@ -201,7 +201,7 @@ void up_allocate_heap(void **heap_start, size_t *heap_size) /* Allow user-mode access to the user heap memory */ - stm32wb_mpu_uheap((uintptr_t)ubase, usize); + stm32_mpu_uheap((uintptr_t)ubase, usize); #else /* Return the heap settings */ @@ -289,7 +289,7 @@ void arm_addregion(void) /* Allow user-mode access to the SRAM2a heap */ - stm32wb_mpu_uheap((uintptr_t)SRAM2A_START, SRAM2A_END - SRAM2A_START); + stm32_mpu_uheap((uintptr_t)SRAM2A_START, SRAM2A_END - SRAM2A_START); #endif @@ -309,7 +309,7 @@ void arm_addregion(void) /* Allow user-mode access to the SRAM2b heap */ - stm32wb_mpu_uheap((uintptr_t)SRAM2B_START, SRAM2B_END - SRAM2B_START); + stm32_mpu_uheap((uintptr_t)SRAM2B_START, SRAM2B_END - SRAM2B_START); #endif diff --git a/arch/arm/src/stm32wb/stm32wb_blehci.c b/arch/arm/src/stm32wb/stm32wb_blehci.c index 3b41a7bee2c..7b69d9b314f 100644 --- a/arch/arm/src/stm32wb/stm32wb_blehci.c +++ b/arch/arm/src/stm32wb/stm32wb_blehci.c @@ -106,14 +106,14 @@ * Private Function Prototypes ****************************************************************************/ -static int stm32wb_blehci_driveropen(struct bt_driver_s *btdev); -static int stm32wb_blehci_driversend(struct bt_driver_s *btdev, +static int stm32_blehci_driveropen(struct bt_driver_s *btdev); +static int stm32_blehci_driversend(struct bt_driver_s *btdev, enum bt_buf_type_e type, void *data, size_t len); -static int stm32wb_blehci_rxevt(struct stm32wb_mbox_evt_s *evt); -static void stm32wb_blehci_bleinit(void); -static int stm32wb_blehci_driverinitialize(void); -static void stm32wb_blehci_drvinitworker(void *arg); +static int stm32_blehci_rxevt(struct stm32_mbox_evt_s *evt); +static void stm32_blehci_bleinit(void); +static int stm32_blehci_driverinitialize(void); +static void stm32_blehci_drvinitworker(void *arg); /**************************************************************************** * Private Data @@ -122,8 +122,8 @@ static void stm32wb_blehci_drvinitworker(void *arg); static struct bt_driver_s g_blehci_driver = { .head_reserve = 0, - .open = stm32wb_blehci_driveropen, - .send = stm32wb_blehci_driversend + .open = stm32_blehci_driveropen, + .send = stm32_blehci_driversend }; static mutex_t g_lock = NXMUTEX_INITIALIZER; @@ -134,19 +134,19 @@ struct work_s g_drv_init_work; ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_blehci_driveropen + * Name: stm32_blehci_driveropen ****************************************************************************/ -static int stm32wb_blehci_driveropen(struct bt_driver_s *btdev) +static int stm32_blehci_driveropen(struct bt_driver_s *btdev) { return 0; } /**************************************************************************** - * Name: stm32wb_blehci_driversend + * Name: stm32_blehci_driversend ****************************************************************************/ -static int stm32wb_blehci_driversend(struct bt_driver_s *btdev, +static int stm32_blehci_driversend(struct bt_driver_s *btdev, enum bt_buf_type_e type, void *data, size_t len) { @@ -177,11 +177,11 @@ static int stm32wb_blehci_driversend(struct bt_driver_s *btdev, if (type == BT_CMD) { - ret = stm32wb_mbox_blecmd(data, len); + ret = stm32_mbox_blecmd(data, len); } else { - ret = stm32wb_mbox_bleacl(data, len); + ret = stm32_mbox_bleacl(data, len); } nxmutex_unlock(&g_lock); @@ -191,10 +191,10 @@ static int stm32wb_blehci_driversend(struct bt_driver_s *btdev, } /**************************************************************************** - * Name: stm32wb_blehci_rxevt + * Name: stm32_blehci_rxevt ****************************************************************************/ -static int stm32wb_blehci_rxevt(struct stm32wb_mbox_evt_s *evt) +static int stm32_blehci_rxevt(struct stm32_mbox_evt_s *evt) { size_t len; @@ -259,7 +259,7 @@ static int stm32wb_blehci_rxevt(struct stm32wb_mbox_evt_s *evt) if (evt->evt_hdr.evt == STM32_SHCI_ASYNC_EVT && *(uint16_t *)(&evt->evt_hdr + 1) == STM32_SHCI_ASYNC_EVT_C2RDY) { - stm32wb_blehci_bleinit(); + stm32_blehci_bleinit(); } break; @@ -276,7 +276,7 @@ static int stm32wb_blehci_rxevt(struct stm32wb_mbox_evt_s *evt) /* Make driver initialisation in low priority work queue */ work_queue(LPWORK, &g_drv_init_work, - stm32wb_blehci_drvinitworker, NULL, 0); + stm32_blehci_drvinitworker, NULL, 0); } break; @@ -288,14 +288,14 @@ static int stm32wb_blehci_rxevt(struct stm32wb_mbox_evt_s *evt) } /**************************************************************************** - * Name: stm32wb_blehci_bleinit + * Name: stm32_blehci_bleinit ****************************************************************************/ -static void stm32wb_blehci_bleinit(void) +static void stm32_blehci_bleinit(void) { /* Prepare BLE configuration */ - struct stm32wb_shci_ble_init_cfg_s params = + struct stm32_shci_ble_init_cfg_s params = { .ble_buf = NULL, .ble_buf_size = 0, @@ -323,14 +323,14 @@ static void stm32wb_blehci_bleinit(void) /* Initialise BLE */ - stm32wb_mbox_bleinit(¶ms); + stm32_mbox_bleinit(¶ms); } /**************************************************************************** - * Name: stm32wb_blehci_driverinitialize + * Name: stm32_blehci_driverinitialize ****************************************************************************/ -static int stm32wb_blehci_driverinitialize(void) +static int stm32_blehci_driverinitialize(void) { int ret = 0; @@ -345,12 +345,12 @@ static int stm32wb_blehci_driverinitialize(void) } /**************************************************************************** - * Name: stm32wb_blehci_drvinitworker + * Name: stm32_blehci_drvinitworker ****************************************************************************/ -static void stm32wb_blehci_drvinitworker(void *arg) +static void stm32_blehci_drvinitworker(void *arg) { - stm32wb_blehci_driverinitialize(); + stm32_blehci_driverinitialize(); } /**************************************************************************** @@ -358,7 +358,7 @@ static void stm32wb_blehci_drvinitworker(void *arg) ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_blehci_initialize + * Name: stm32_blehci_initialize * * Description: * Initialize and register BLE HCI driver which interfaces a BLE host @@ -367,15 +367,15 @@ static void stm32wb_blehci_drvinitworker(void *arg) * ****************************************************************************/ -void stm32wb_blehci_initialize(void) +void stm32_blehci_initialize(void) { /* Initialize mbox internal data structures and set * event receive handler. */ - stm32wb_mboxinitialize(stm32wb_blehci_rxevt); + stm32_mboxinitialize(stm32_blehci_rxevt); /* Enable communication hardware and boot up CPU2 */ - stm32wb_mboxenable(); + stm32_mboxenable(); } diff --git a/arch/arm/src/stm32wb/stm32wb_blehci.h b/arch/arm/src/stm32wb/stm32wb_blehci.h index a8d5f6229d5..01b93c012d5 100644 --- a/arch/arm/src/stm32wb/stm32wb_blehci.h +++ b/arch/arm/src/stm32wb/stm32wb_blehci.h @@ -50,7 +50,7 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_blehci_initialize + * Name: stm32_blehci_initialize * * Description: * Initialize and register BLE HCI driver which interfaces a BLE host @@ -59,7 +59,7 @@ extern "C" * ****************************************************************************/ -void stm32wb_blehci_initialize(void); +void stm32_blehci_initialize(void); #undef EXTERN #if defined(__cplusplus) diff --git a/arch/arm/src/stm32wb/stm32wb_dma.c b/arch/arm/src/stm32wb/stm32wb_dma.c index 9789c80b45c..d8674fd279c 100644 --- a/arch/arm/src/stm32wb/stm32wb_dma.c +++ b/arch/arm/src/stm32wb/stm32wb_dma.c @@ -75,20 +75,20 @@ /* This structure described one DMAMUX device */ -struct stm32wb_dmamux_s +struct stm32_dmamux_s { uint8_t id; /* DMAMUX id */ uint8_t nchan; /* DMAMUX channels */ uint32_t base; /* DMAMUX base address */ }; -typedef const struct stm32wb_dmamux_s *DMA_MUX; +typedef const struct stm32_dmamux_s *DMA_MUX; /* This structure describes one DMA controller */ -struct stm32wb_dma_s +struct stm32_dma_s { - uint8_t first; /* Offset in stm32wb_dmach_s array */ + uint8_t first; /* Offset in stm32_dmach_s array */ uint8_t nchan; /* Number of channels */ uint8_t dmamux_offset; /* DMAMUX channel offset */ uint32_t base; /* Base address */ @@ -97,7 +97,7 @@ struct stm32wb_dma_s /* This structure describes one DMA channel (DMA1, DMA2) */ -struct stm32wb_dmach_s +struct stm32_dmach_s { bool used; /* Channel in use */ uint8_t dmamux_req; /* Configured DMAMUX input request */ @@ -110,11 +110,11 @@ struct stm32wb_dmach_s void *arg; /* Argument passed to callback function */ }; -typedef struct stm32wb_dmach_s *DMA_CHANNEL; +typedef struct stm32_dmach_s *DMA_CHANNEL; /* DMA operations */ -struct stm32wb_dma_ops_s +struct stm32_dma_ops_s { /* Disable the DMA transfer */ @@ -145,12 +145,12 @@ struct stm32wb_dma_ops_s #ifdef CONFIG_DEBUG_DMA_INFO /* Sample the DMA registers */ - void (*dma_sample)(DMA_HANDLE handle, struct stm32wb_dmaregs_s *regs); + void (*dma_sample)(DMA_HANDLE handle, struct stm32_dmaregs_s *regs); /* Dump the DMA registers */ void (*dma_dump)(DMA_HANDLE handle, - const struct stm32wb_dmaregs_s *regs, + const struct stm32_dmaregs_s *regs, const char *msg); #endif }; @@ -160,19 +160,19 @@ struct stm32wb_dma_ops_s ****************************************************************************/ #if defined(CONFIG_STM32WB_DMA1) || defined(CONFIG_STM32WB_DMA2) -static void stm32wb_dma12_disable(DMA_CHANNEL dmachan); -static int stm32wb_dma12_interrupt(int irq, void *context, void *arg); -static void stm32wb_dma12_setup(DMA_HANDLE handle, uint32_t paddr, +static void stm32_dma12_disable(DMA_CHANNEL dmachan); +static int stm32_dma12_interrupt(int irq, void *context, void *arg); +static void stm32_dma12_setup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, size_t ntransfers, uint32_t ccr); -static void stm32wb_dma12_start(DMA_HANDLE handle, dma_callback_t callback, +static void stm32_dma12_start(DMA_HANDLE handle, dma_callback_t callback, void *arg, bool half); -static size_t stm32wb_dma12_residual(DMA_HANDLE handle); +static size_t stm32_dma12_residual(DMA_HANDLE handle); #ifdef CONFIG_DEBUG_DMA_INFO -static void stm32wb_dma12_sample(DMA_HANDLE handle, - struct stm32wb_dmaregs_s *regs); -static void stm32wb_dma12_dump(DMA_HANDLE handle, - const struct stm32wb_dmaregs_s *regs, +static void stm32_dma12_sample(DMA_HANDLE handle, + struct stm32_dmaregs_s *regs); +static void stm32_dma12_dump(DMA_HANDLE handle, + const struct stm32_dmaregs_s *regs, const char *msg); #endif #endif @@ -187,14 +187,14 @@ static void dmachan_putreg(DMA_CHANNEL dmachan, uint32_t offset, static void dmamux_putreg(DMA_MUX dmamux, uint32_t offset, uint32_t value); #ifdef CONFIG_DEBUG_DMA_INFO static uint32_t dmamux_getreg(DMA_MUX dmamux, uint32_t offset); -static void stm32wb_dmamux_sample(DMA_MUX dmamux, uint8_t chan, - struct stm32wb_dmaregs_s *regs); -static void stm32wb_dmamux_dump(DMA_MUX dmamux, uint8_t channel, - const struct stm32wb_dmaregs_s *regs); +static void stm32_dmamux_sample(DMA_MUX dmamux, uint8_t chan, + struct stm32_dmaregs_s *regs); +static void stm32_dmamux_dump(DMA_MUX dmamux, uint8_t channel, + const struct stm32_dmaregs_s *regs); #endif -static DMA_CHANNEL stm32wb_dma_channel_get(uint8_t channel, +static DMA_CHANNEL stm32_dma_channel_get(uint8_t channel, uint8_t controller); -static void stm32wb_gdma_limits_get(uint8_t controller, uint8_t *first, +static void stm32_gdma_limits_get(uint8_t controller, uint8_t *first, uint8_t *last); /**************************************************************************** @@ -203,20 +203,20 @@ static void stm32wb_gdma_limits_get(uint8_t controller, uint8_t *first, /* Operations specific to DMA controller */ -static const struct stm32wb_dma_ops_s g_dma_ops[DMA_CONTROLLERS] = +static const struct stm32_dma_ops_s g_dma_ops[DMA_CONTROLLERS] = { #ifdef CONFIG_STM32WB_DMA1 /* 0 - DMA1 */ { - .dma_disable = stm32wb_dma12_disable, - .dma_interrupt = stm32wb_dma12_interrupt, - .dma_setup = stm32wb_dma12_setup, - .dma_start = stm32wb_dma12_start, - .dma_residual = stm32wb_dma12_residual, + .dma_disable = stm32_dma12_disable, + .dma_interrupt = stm32_dma12_interrupt, + .dma_setup = stm32_dma12_setup, + .dma_start = stm32_dma12_start, + .dma_residual = stm32_dma12_residual, #ifdef CONFIG_DEBUG_DMA_INFO - .dma_sample = stm32wb_dma12_sample, - .dma_dump = stm32wb_dma12_dump, + .dma_sample = stm32_dma12_sample, + .dma_dump = stm32_dma12_dump, #endif }, #else @@ -229,14 +229,14 @@ static const struct stm32wb_dma_ops_s g_dma_ops[DMA_CONTROLLERS] = /* 1 - DMA2 */ { - .dma_disable = stm32wb_dma12_disable, - .dma_interrupt = stm32wb_dma12_interrupt, - .dma_setup = stm32wb_dma12_setup, - .dma_start = stm32wb_dma12_start, - .dma_residual = stm32wb_dma12_residual, + .dma_disable = stm32_dma12_disable, + .dma_interrupt = stm32_dma12_interrupt, + .dma_setup = stm32_dma12_setup, + .dma_start = stm32_dma12_start, + .dma_residual = stm32_dma12_residual, #ifdef CONFIG_DEBUG_DMA_INFO - .dma_sample = stm32wb_dma12_sample, - .dma_dump = stm32wb_dma12_dump, + .dma_sample = stm32_dma12_sample, + .dma_dump = stm32_dma12_dump, #endif } #else @@ -248,7 +248,7 @@ static const struct stm32wb_dma_ops_s g_dma_ops[DMA_CONTROLLERS] = /* This array describes the state of DMAMUX controller */ -static const struct stm32wb_dmamux_s g_dmamux[DMAMUX_NUM] = +static const struct stm32_dmamux_s g_dmamux[DMAMUX_NUM] = { { .id = 1, @@ -259,7 +259,7 @@ static const struct stm32wb_dmamux_s g_dmamux[DMAMUX_NUM] = /* This array describes the state of each controller */ -static const struct stm32wb_dma_s g_dma[DMA_NCHANNELS] = +static const struct stm32_dma_s g_dma[DMA_NCHANNELS] = { /* 0 - DMA1 */ @@ -284,7 +284,7 @@ static const struct stm32wb_dma_s g_dma[DMA_NCHANNELS] = /* This array describes the state of each DMA channel. */ -static struct stm32wb_dmach_s g_dmach[DMA_NCHANNELS] = +static struct stm32_dmach_s g_dmach[DMA_NCHANNELS] = { #ifdef CONFIG_STM32WB_DMA1 /* DMA1 */ @@ -517,7 +517,7 @@ static uint32_t dmamux_getreg(DMA_MUX dmamux, uint32_t offset) #endif /**************************************************************************** - * Name: stm32wb_dma_channel_get + * Name: stm32_dma_channel_get * * Description: * Get the g_dmach table entry associated with a given DMA controller @@ -525,7 +525,7 @@ static uint32_t dmamux_getreg(DMA_MUX dmamux, uint32_t offset) * ****************************************************************************/ -static DMA_CHANNEL stm32wb_dma_channel_get(uint8_t channel, +static DMA_CHANNEL stm32_dma_channel_get(uint8_t channel, uint8_t controller) { uint8_t first = 0; @@ -533,7 +533,7 @@ static DMA_CHANNEL stm32wb_dma_channel_get(uint8_t channel, /* Get limits for g_dma array */ - stm32wb_gdma_limits_get(controller, &first, &nchan); + stm32_gdma_limits_get(controller, &first, &nchan); DEBUGASSERT(channel <= nchan); @@ -541,14 +541,14 @@ static DMA_CHANNEL stm32wb_dma_channel_get(uint8_t channel, } /**************************************************************************** - * Name: stm32wb_gdma_limits_get + * Name: stm32_gdma_limits_get * * Description: * Get g_dma array limits for a given DMA controller. * ****************************************************************************/ -static void stm32wb_gdma_limits_get(uint8_t controller, uint8_t *first, +static void stm32_gdma_limits_get(uint8_t controller, uint8_t *first, uint8_t *nchan) { DEBUGASSERT(first != NULL); @@ -567,14 +567,14 @@ static void stm32wb_gdma_limits_get(uint8_t controller, uint8_t *first, #if defined(CONFIG_STM32WB_DMA1) || defined(CONFIG_STM32WB_DMA2) /**************************************************************************** - * Name: stm32wb_dma12_disable + * Name: stm32_dma12_disable * * Description: * Disable DMA channel (DMA1/DMA2) * ****************************************************************************/ -static void stm32wb_dma12_disable(DMA_CHANNEL dmachan) +static void stm32_dma12_disable(DMA_CHANNEL dmachan) { uint32_t regval; @@ -597,14 +597,14 @@ static void stm32wb_dma12_disable(DMA_CHANNEL dmachan) } /**************************************************************************** - * Name: stm32wb_dma12_interrupt + * Name: stm32_dma12_interrupt * * Description: * DMA channel interrupt handler * ****************************************************************************/ -static int stm32wb_dma12_interrupt(int irq, void *context, void *arg) +static int stm32_dma12_interrupt(int irq, void *context, void *arg) { DMA_CHANNEL dmachan; uint32_t isr; @@ -643,7 +643,7 @@ static int stm32wb_dma12_interrupt(int irq, void *context, void *arg) /* Get the channel structure from the stream and controller numbers */ - dmachan = stm32wb_dma_channel_get(channel, controller); + dmachan = stm32_dma_channel_get(channel, controller); /* Get the interrupt status (for this channel only) */ @@ -666,14 +666,14 @@ static int stm32wb_dma12_interrupt(int irq, void *context, void *arg) } /**************************************************************************** - * Name: stm32wb_dma12_setup + * Name: stm32_dma12_setup * * Description: * Configure DMA before using * ****************************************************************************/ -static void stm32wb_dma12_setup(DMA_HANDLE handle, uint32_t paddr, +static void stm32_dma12_setup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, size_t ntransfers, uint32_t ccr) { @@ -738,13 +738,13 @@ static void stm32wb_dma12_setup(DMA_HANDLE handle, uint32_t paddr, } /**************************************************************************** - * Name: stm32wb_dma12_start + * Name: stm32_dma12_start * * Description: * Start the standard DMA transfer ****************************************************************************/ -static void stm32wb_dma12_start(DMA_HANDLE handle, dma_callback_t callback, +static void stm32_dma12_start(DMA_HANDLE handle, dma_callback_t callback, void *arg, bool half) { DMA_CHANNEL dmachan = (DMA_CHANNEL)handle; @@ -800,10 +800,10 @@ static void stm32wb_dma12_start(DMA_HANDLE handle, dma_callback_t callback, } /**************************************************************************** - * Name: stm32wb_dma12_residual + * Name: stm32_dma12_residual ****************************************************************************/ -static size_t stm32wb_dma12_residual(DMA_HANDLE handle) +static size_t stm32_dma12_residual(DMA_HANDLE handle) { DMA_CHANNEL dmachan = (DMA_CHANNEL)handle; @@ -813,11 +813,11 @@ static size_t stm32wb_dma12_residual(DMA_HANDLE handle) } /**************************************************************************** - * Name: stm32wb_dma12_sample + * Name: stm32_dma12_sample ****************************************************************************/ #ifdef CONFIG_DEBUG_DMA_INFO -void stm32wb_dma12_sample(DMA_HANDLE handle, struct stm32wb_dmaregs_s *regs) +void stm32_dma12_sample(DMA_HANDLE handle, struct stm32_dmaregs_s *regs) { DMA_CHANNEL dmachan = (DMA_CHANNEL)handle; irqstate_t flags; @@ -830,7 +830,7 @@ void stm32wb_dma12_sample(DMA_HANDLE handle, struct stm32wb_dmaregs_s *regs) regs->cpar = dmachan_getreg(dmachan, STM32_DMACHAN_CPAR_OFFSET); regs->cmar = dmachan_getreg(dmachan, STM32_DMACHAN_CMAR_OFFSET); - stm32wb_dmamux_sample(g_dma[dmachan->ctrl].dmamux, + stm32_dmamux_sample(g_dma[dmachan->ctrl].dmamux, dmachan->chan + g_dma[dmachan->ctrl].dmamux_offset, regs); @@ -839,12 +839,12 @@ void stm32wb_dma12_sample(DMA_HANDLE handle, struct stm32wb_dmaregs_s *regs) #endif /**************************************************************************** - * Name: stm32wb_dma12_dump + * Name: stm32_dma12_dump ****************************************************************************/ #ifdef CONFIG_DEBUG_DMA_INFO -static void stm32wb_dma12_dump(DMA_HANDLE handle, - const struct stm32wb_dmaregs_s *regs, +static void stm32_dma12_dump(DMA_HANDLE handle, + const struct stm32_dmaregs_s *regs, const char *msg) { DMA_CHANNEL dmachan = (DMA_CHANNEL)handle; @@ -872,7 +872,7 @@ static void stm32wb_dma12_dump(DMA_HANDLE handle, dmachan->base + STM32_DMACHAN_CMAR_OFFSET, regs->cmar); - stm32wb_dmamux_dump(g_dma[dmachan->ctrl].dmamux, + stm32_dmamux_dump(g_dma[dmachan->ctrl].dmamux, dmachan->chan + g_dma[dmachan->ctrl].dmamux_offset, regs); } @@ -881,12 +881,12 @@ static void stm32wb_dma12_dump(DMA_HANDLE handle, #endif /* CONFIG_STM32WB_DMA1 || CONFIG_STM32WB_DMA2 */ /**************************************************************************** - * Name: stm32wb_dmamux_sample + * Name: stm32_dmamux_sample ****************************************************************************/ #ifdef CONFIG_DEBUG_DMA_INFO -static void stm32wb_dmamux_sample(DMA_MUX dmamux, uint8_t chan, - struct stm32wb_dmaregs_s *regs) +static void stm32_dmamux_sample(DMA_MUX dmamux, uint8_t chan, + struct stm32_dmaregs_s *regs) { regs->dmamux.ccr = dmamux_getreg(dmamux, STM32_DMAMUX_CXCR_OFFSET(chan)); regs->dmamux.csr = dmamux_getreg(dmamux, STM32_DMAMUX_CSR_OFFSET); @@ -899,12 +899,12 @@ static void stm32wb_dmamux_sample(DMA_MUX dmamux, uint8_t chan, #endif /**************************************************************************** - * Name: stm32wb_dmamux_dump + * Name: stm32_dmamux_dump ****************************************************************************/ #ifdef CONFIG_DEBUG_DMA_INFO -static void stm32wb_dmamux_dump(DMA_MUX dmamux, uint8_t channel, - const struct stm32wb_dmaregs_s *regs) +static void stm32_dmamux_dump(DMA_MUX dmamux, uint8_t channel, + const struct stm32_dmaregs_s *regs) { dmainfo("DMAMUX%d CH=%d\n", dmamux->id, channel); dmainfo(" CCR[%08x]: %08x\n", @@ -980,7 +980,7 @@ void weak_function arm_dma_initialize(void) } /**************************************************************************** - * Name: stm32wb_dmachannel + * Name: stm32_dmachannel * * Description: * Allocate a DMA channel. This function gives the caller mutually @@ -1004,7 +1004,7 @@ void weak_function arm_dma_initialize(void) * ****************************************************************************/ -DMA_HANDLE stm32wb_dmachannel(unsigned int dmamap) +DMA_HANDLE stm32_dmachannel(unsigned int dmamap) { DMA_CHANNEL dmachan; uint8_t dmamux_req; @@ -1026,7 +1026,7 @@ DMA_HANDLE stm32wb_dmachannel(unsigned int dmamap) /* Get g_dma array limits for given controller */ - stm32wb_gdma_limits_get(controller, &first, &nchan); + stm32_gdma_limits_get(controller, &first, &nchan); /* Find available channel for given controller */ @@ -1070,13 +1070,13 @@ DMA_HANDLE stm32wb_dmachannel(unsigned int dmamap) } /**************************************************************************** - * Name: stm32wb_dmafree + * Name: stm32_dmafree * * Description: * Release a DMA channel and unmap DMAMUX if required. * * NOTE: The 'handle' used in this argument must NEVER be used again - * until stm32wb_dmachannel() is called again to re-gain access to the + * until stm32_dmachannel() is called again to re-gain access to the * channel. * * Returned Value: @@ -1088,7 +1088,7 @@ DMA_HANDLE stm32wb_dmachannel(unsigned int dmamap) * ****************************************************************************/ -void stm32wb_dmafree(DMA_HANDLE handle) +void stm32_dmafree(DMA_HANDLE handle) { DMA_CHANNEL dmachan = (DMA_CHANNEL)handle; uint8_t controller; @@ -1114,14 +1114,14 @@ void stm32wb_dmafree(DMA_HANDLE handle) } /**************************************************************************** - * Name: stm32wb_dmasetup + * Name: stm32_dmasetup * * Description: * Configure DMA before using * ****************************************************************************/ -void stm32wb_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, +void stm32_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, size_t ntransfers, uint32_t ccr) { DMA_CHANNEL dmachan = (DMA_CHANNEL)handle; @@ -1138,18 +1138,18 @@ void stm32wb_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, } /**************************************************************************** - * Name: stm32wb_dmastart + * Name: stm32_dmastart * * Description: * Start the DMA transfer * * Assumptions: - * - DMA handle allocated by stm32wb_dmachannel() + * - DMA handle allocated by stm32_dmachannel() * - No DMA in progress * ****************************************************************************/ -void stm32wb_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg, +void stm32_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg, bool half) { DMA_CHANNEL dmachan = (DMA_CHANNEL)handle; @@ -1187,19 +1187,19 @@ void stm32wb_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg, } /**************************************************************************** - * Name: stm32wb_dmastop + * Name: stm32_dmastop * * Description: - * Cancel the DMA. After stm32wb_dmastop() is called, the DMA channel is - * reset and stm32wb_dmasetup() must be called before stm32wb_dmastart() + * Cancel the DMA. After stm32_dmastop() is called, the DMA channel is + * reset and stm32_dmasetup() must be called before stm32_dmastart() * can be called again * * Assumptions: - * - DMA handle allocated by stm32wb_dmachannel() + * - DMA handle allocated by stm32_dmachannel() * ****************************************************************************/ -void stm32wb_dmastop(DMA_HANDLE handle) +void stm32_dmastop(DMA_HANDLE handle) { DMA_CHANNEL dmachan = (DMA_CHANNEL)handle; DMA_MUX dmamux; @@ -1228,17 +1228,17 @@ void stm32wb_dmastop(DMA_HANDLE handle) } /**************************************************************************** - * Name: stm32wb_dmaresidual + * Name: stm32_dmaresidual * * Description: * Read the DMA bytes-remaining register. * * Assumptions: - * - DMA handle allocated by stm32wb_dmachannel() + * - DMA handle allocated by stm32_dmachannel() * ****************************************************************************/ -size_t stm32wb_dmaresidual(DMA_HANDLE handle) +size_t stm32_dmaresidual(DMA_HANDLE handle) { DMA_CHANNEL dmachan = (DMA_CHANNEL)handle; uint8_t controller; @@ -1254,7 +1254,7 @@ size_t stm32wb_dmaresidual(DMA_HANDLE handle) } /**************************************************************************** - * Name: stm32wb_dmacapable + * Name: stm32_dmacapable * * Description: * Check if the DMA controller can transfer data to/from given memory @@ -1271,7 +1271,7 @@ size_t stm32wb_dmaresidual(DMA_HANDLE handle) ****************************************************************************/ #ifdef CONFIG_STM32WB_DMACAPABLE -bool stm32wb_dmacapable(uint32_t maddr, uint32_t count, uint32_t ccr) +bool stm32_dmacapable(uint32_t maddr, uint32_t count, uint32_t ccr) { unsigned int msize_shift; uint32_t transfer_size; @@ -1347,18 +1347,18 @@ bool stm32wb_dmacapable(uint32_t maddr, uint32_t count, uint32_t ccr) #endif /**************************************************************************** - * Name: stm32wb_dmasample + * Name: stm32_dmasample * * Description: * Sample DMA register contents * * Assumptions: - * - DMA handle allocated by stm32wb_dmachannel() + * - DMA handle allocated by stm32_dmachannel() * ****************************************************************************/ #ifdef CONFIG_DEBUG_DMA_INFO -void stm32wb_dmasample(DMA_HANDLE handle, struct stm32wb_dmaregs_s *regs) +void stm32_dmasample(DMA_HANDLE handle, struct stm32_dmaregs_s *regs) { DMA_CHANNEL dmachan = (DMA_CHANNEL)handle; uint8_t controller; @@ -1375,18 +1375,18 @@ void stm32wb_dmasample(DMA_HANDLE handle, struct stm32wb_dmaregs_s *regs) #endif /**************************************************************************** - * Name: stm32wb_dmadump + * Name: stm32_dmadump * * Description: * Dump previously sampled DMA register contents * * Assumptions: - * - DMA handle allocated by stm32wb_dmachannel() + * - DMA handle allocated by stm32_dmachannel() * ****************************************************************************/ #ifdef CONFIG_DEBUG_DMA_INFO -void stm32wb_dmadump(DMA_HANDLE handle, const struct stm32wb_dmaregs_s *regs, +void stm32_dmadump(DMA_HANDLE handle, const struct stm32_dmaregs_s *regs, const char *msg) { DMA_CHANNEL dmachan = (DMA_CHANNEL)handle; diff --git a/arch/arm/src/stm32wb/stm32wb_dma.h b/arch/arm/src/stm32wb/stm32wb_dma.h index 6caff116906..baf212c4dbd 100644 --- a/arch/arm/src/stm32wb/stm32wb_dma.h +++ b/arch/arm/src/stm32wb/stm32wb_dma.h @@ -71,7 +71,7 @@ typedef void *DMA_HANDLE; typedef void (*dma_callback_t)(DMA_HANDLE handle, uint8_t status, void *arg); #ifdef CONFIG_DEBUG_DMA_INFO -struct stm32wb_dmaregs_s +struct stm32_dmaregs_s { uint32_t isr; /* Interrupt Status Register; each channel gets 4 bits */ uint32_t ccr; /* Channel Configuration Register; determines functionality */ @@ -139,18 +139,18 @@ extern "C" * ****************************************************************************/ -DMA_HANDLE stm32wb_dmachannel(unsigned int dmamap); +DMA_HANDLE stm32_dmachannel(unsigned int dmamap); /**************************************************************************** - * Name: stm32wb_dmafree + * Name: stm32_dmafree * * Description: * Release a DMA channel. If another thread is waiting for this DMA - * channel in a call to stm32wb_dmachannel, then this function will + * channel in a call to stm32_dmachannel, then this function will * re-assign the DMA channel to that thread and wake it up. * * NOTE: The 'handle' used in this argument must NEVER be used again - * until stm32wb_dmachannel() is called again to re-gain access to + * until stm32_dmachannel() is called again to re-gain access to * the channel. * * Returned Value: @@ -162,64 +162,64 @@ DMA_HANDLE stm32wb_dmachannel(unsigned int dmamap); * ****************************************************************************/ -void stm32wb_dmafree(DMA_HANDLE handle); +void stm32_dmafree(DMA_HANDLE handle); /**************************************************************************** - * Name: stm32wb_dmasetup + * Name: stm32_dmasetup * * Description: * Configure DMA before using * ****************************************************************************/ -void stm32wb_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, +void stm32_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, size_t ntransfers, uint32_t ccr); /**************************************************************************** - * Name: stm32wb_dmastart + * Name: stm32_dmastart * * Description: * Start the DMA transfer * * Assumptions: - * - DMA handle allocated by stm32wb_dmachannel() + * - DMA handle allocated by stm32_dmachannel() * - No DMA in progress * ****************************************************************************/ -void stm32wb_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg, +void stm32_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg, bool half); /**************************************************************************** - * Name: stm32wb_dmastop + * Name: stm32_dmastop * * Description: - * Cancel the DMA. After stm32wb_dmastop() is called, the DMA channel is - * reset and stm32wb_dmasetup() must be called before stm32wb_dmastart() + * Cancel the DMA. After stm32_dmastop() is called, the DMA channel is + * reset and stm32_dmasetup() must be called before stm32_dmastart() * can be called again * * Assumptions: - * - DMA handle allocated by stm32wb_dmachannel() + * - DMA handle allocated by stm32_dmachannel() * ****************************************************************************/ -void stm32wb_dmastop(DMA_HANDLE handle); +void stm32_dmastop(DMA_HANDLE handle); /**************************************************************************** - * Name: stm32wb_dmaresidual + * Name: stm32_dmaresidual * * Description: * Returns the number of bytes remaining to be transferred * * Assumptions: - * - DMA handle allocated by stm32wb_dmachannel() + * - DMA handle allocated by stm32_dmachannel() * ****************************************************************************/ -size_t stm32wb_dmaresidual(DMA_HANDLE handle); +size_t stm32_dmaresidual(DMA_HANDLE handle); /**************************************************************************** - * Name: stm32wb_dmacapable + * Name: stm32_dmacapable * * Description: * Check if the DMA controller can transfer data to/from given memory @@ -234,44 +234,44 @@ size_t stm32wb_dmaresidual(DMA_HANDLE handle); ****************************************************************************/ #ifdef CONFIG_STM32WB_DMACAPABLE -bool stm32wb_dmacapable(uintptr_t maddr, uint32_t count, uint32_t ccr); +bool stm32_dmacapable(uintptr_t maddr, uint32_t count, uint32_t ccr); #else -# define stm32wb_dmacapable(maddr, count, ccr) (true) +# define stm32_dmacapable(maddr, count, ccr) (true) #endif /**************************************************************************** - * Name: stm32wb_dmasample + * Name: stm32_dmasample * * Description: * Sample DMA register contents * * Assumptions: - * - DMA handle allocated by stm32wb_dmachannel() + * - DMA handle allocated by stm32_dmachannel() * ****************************************************************************/ #ifdef CONFIG_DEBUG_DMA_INFO -void stm32wb_dmasample(DMA_HANDLE handle, struct stm32wb_dmaregs_s *regs); +void stm32_dmasample(DMA_HANDLE handle, struct stm32_dmaregs_s *regs); #else -# define stm32wb_dmasample(handle,regs) ((void)0) +# define stm32_dmasample(handle,regs) ((void)0) #endif /**************************************************************************** - * Name: stm32wb_dmadump + * Name: stm32_dmadump * * Description: * Dump previously sampled DMA register contents * * Assumptions: - * - DMA handle allocated by stm32wb_dmachannel() + * - DMA handle allocated by stm32_dmachannel() * ****************************************************************************/ #ifdef CONFIG_DEBUG_DMA_INFO -void stm32wb_dmadump(DMA_HANDLE handle, const struct stm32wb_dmaregs_s *regs, +void stm32_dmadump(DMA_HANDLE handle, const struct stm32_dmaregs_s *regs, const char *msg); #else -# define stm32wb_dmadump(handle,regs,msg) ((void)0) +# define stm32_dmadump(handle,regs,msg) ((void)0) #endif #undef EXTERN diff --git a/arch/arm/src/stm32wb/stm32wb_dumpgpio.c b/arch/arm/src/stm32wb/stm32wb_dumpgpio.c index 3a45d0e54c7..2b33764174a 100644 --- a/arch/arm/src/stm32wb/stm32wb_dumpgpio.c +++ b/arch/arm/src/stm32wb/stm32wb_dumpgpio.c @@ -66,14 +66,14 @@ static const char g_portchar[STM32_NPORTS] = ****************************************************************************/ /**************************************************************************** - * Function: stm32wb_dumpgpio + * Function: stm32_dumpgpio * * Description: * Dump all GPIO registers associated with the provided base address * ****************************************************************************/ -int stm32wb_dumpgpio(uint32_t pinset, const char *msg) +int stm32_dumpgpio(uint32_t pinset, const char *msg) { irqstate_t flags; uint32_t base; diff --git a/arch/arm/src/stm32wb/stm32wb_exti.h b/arch/arm/src/stm32wb/stm32wb_exti.h index 40494223991..9e0b370fbe4 100644 --- a/arch/arm/src/stm32wb/stm32wb_exti.h +++ b/arch/arm/src/stm32wb/stm32wb_exti.h @@ -54,7 +54,7 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_gpiosetevent + * Name: stm32_gpiosetevent * * Description: * Sets/clears GPIO based event and interrupt triggers. @@ -73,11 +73,11 @@ extern "C" * ****************************************************************************/ -int stm32wb_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, +int stm32_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, bool event, xcpt_t func, void *arg); /**************************************************************************** - * Name: stm32wb_exti_alarm + * Name: stm32_exti_alarm * * Description: * Sets/clears EXTI alarm interrupt. @@ -95,12 +95,12 @@ int stm32wb_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, ****************************************************************************/ #ifdef CONFIG_RTC_ALARM -int stm32wb_exti_alarm(bool risingedge, bool fallingedge, bool event, +int stm32_exti_alarm(bool risingedge, bool fallingedge, bool event, xcpt_t func, void *arg); #endif /**************************************************************************** - * Name: stm32wb_exti_wakeup + * Name: stm32_exti_wakeup * * Description: * Sets/clears EXTI wakeup interrupt. @@ -118,7 +118,7 @@ int stm32wb_exti_alarm(bool risingedge, bool fallingedge, bool event, ****************************************************************************/ #ifdef CONFIG_RTC_PERIODIC -int stm32wb_exti_wakeup(bool risingedge, bool fallingedge, bool event, +int stm32_exti_wakeup(bool risingedge, bool fallingedge, bool event, xcpt_t func, void *arg); #endif diff --git a/arch/arm/src/stm32wb/stm32wb_exti_alarm.c b/arch/arm/src/stm32wb/stm32wb_exti_alarm.c index 8a4b9cf1538..cff98eaeb93 100644 --- a/arch/arm/src/stm32wb/stm32wb_exti_alarm.c +++ b/arch/arm/src/stm32wb/stm32wb_exti_alarm.c @@ -51,14 +51,14 @@ static void *g_callback_arg; ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_exti_alarm_isr + * Name: stm32_exti_alarm_isr * * Description: * EXTI ALARM interrupt service routine/dispatcher * ****************************************************************************/ -static int stm32wb_exti_alarm_isr(int irq, void *context, void *arg) +static int stm32_exti_alarm_isr(int irq, void *context, void *arg) { int ret = OK; @@ -81,7 +81,7 @@ static int stm32wb_exti_alarm_isr(int irq, void *context, void *arg) ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_exti_alarm + * Name: stm32_exti_alarm * * Description: * Sets/clears EXTI alarm interrupt. @@ -97,7 +97,7 @@ static int stm32wb_exti_alarm_isr(int irq, void *context, void *arg) * ****************************************************************************/ -int stm32wb_exti_alarm(bool risingedge, bool fallingedge, bool event, +int stm32_exti_alarm(bool risingedge, bool fallingedge, bool event, xcpt_t func, void *arg) { g_alarm_callback = func; @@ -107,7 +107,7 @@ int stm32wb_exti_alarm(bool risingedge, bool fallingedge, bool event, if (func) { - irq_attach(STM32_IRQ_RTCALRM, stm32wb_exti_alarm_isr, NULL); + irq_attach(STM32_IRQ_RTCALRM, stm32_exti_alarm_isr, NULL); up_enable_irq(STM32_IRQ_RTCALRM); } else diff --git a/arch/arm/src/stm32wb/stm32wb_exti_gpio.c b/arch/arm/src/stm32wb/stm32wb_exti_gpio.c index 6d5afe56e69..6e6597b60ca 100644 --- a/arch/arm/src/stm32wb/stm32wb_exti_gpio.c +++ b/arch/arm/src/stm32wb/stm32wb_exti_gpio.c @@ -65,7 +65,7 @@ static struct gpio_callback_s g_gpio_handlers[16]; * Interrupt Service Routines - Dispatchers ****************************************************************************/ -static int stm32wb_exti0_isr(int irq, void *context, void *arg) +static int stm32_exti0_isr(int irq, void *context, void *arg) { int ret = OK; @@ -86,7 +86,7 @@ static int stm32wb_exti0_isr(int irq, void *context, void *arg) return ret; } -static int stm32wb_exti1_isr(int irq, void *context, void *arg) +static int stm32_exti1_isr(int irq, void *context, void *arg) { int ret = OK; @@ -107,7 +107,7 @@ static int stm32wb_exti1_isr(int irq, void *context, void *arg) return ret; } -static int stm32wb_exti2_isr(int irq, void *context, void *arg) +static int stm32_exti2_isr(int irq, void *context, void *arg) { int ret = OK; @@ -128,7 +128,7 @@ static int stm32wb_exti2_isr(int irq, void *context, void *arg) return ret; } -static int stm32wb_exti3_isr(int irq, void *context, void *arg) +static int stm32_exti3_isr(int irq, void *context, void *arg) { int ret = OK; @@ -149,7 +149,7 @@ static int stm32wb_exti3_isr(int irq, void *context, void *arg) return ret; } -static int stm32wb_exti4_isr(int irq, void *context, void *arg) +static int stm32_exti4_isr(int irq, void *context, void *arg) { int ret = OK; @@ -170,7 +170,7 @@ static int stm32wb_exti4_isr(int irq, void *context, void *arg) return ret; } -static int stm32wb_exti_multiisr(int irq, void *context, void *arg, +static int stm32_exti_multiisr(int irq, void *context, void *arg, int first, int last) { uint32_t pr; @@ -214,14 +214,14 @@ static int stm32wb_exti_multiisr(int irq, void *context, void *arg, return ret; } -static int stm32wb_exti95_isr(int irq, void *context, void *arg) +static int stm32_exti95_isr(int irq, void *context, void *arg) { - return stm32wb_exti_multiisr(irq, context, arg, 5, 9); + return stm32_exti_multiisr(irq, context, arg, 5, 9); } -static int stm32wb_exti1510_isr(int irq, void *context, void *arg) +static int stm32_exti1510_isr(int irq, void *context, void *arg) { - return stm32wb_exti_multiisr(irq, context, arg, 10, 15); + return stm32_exti_multiisr(irq, context, arg, 10, 15); } /**************************************************************************** @@ -229,7 +229,7 @@ static int stm32wb_exti1510_isr(int irq, void *context, void *arg) ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_gpiosetevent + * Name: stm32_gpiosetevent * * Description: * Sets/clears GPIO based event and interrupt triggers. @@ -251,7 +251,7 @@ static int stm32wb_exti1510_isr(int irq, void *context, void *arg) * ****************************************************************************/ -int stm32wb_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, +int stm32_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, bool event, xcpt_t func, void *arg) { struct gpio_callback_s *shared_cbs; @@ -271,37 +271,37 @@ int stm32wb_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, switch (pin) { case 0: - handler = stm32wb_exti0_isr; + handler = stm32_exti0_isr; break; case 1: - handler = stm32wb_exti1_isr; + handler = stm32_exti1_isr; break; case 2: - handler = stm32wb_exti2_isr; + handler = stm32_exti2_isr; break; case 3: - handler = stm32wb_exti3_isr; + handler = stm32_exti3_isr; break; default: - handler = stm32wb_exti4_isr; + handler = stm32_exti4_isr; break; } } else if (pin < 10) { irq = STM32_IRQ_EXTI95; - handler = stm32wb_exti95_isr; + handler = stm32_exti95_isr; shared_cbs = &g_gpio_handlers[5]; nshared = 5; } else { irq = STM32_IRQ_EXTI1510; - handler = stm32wb_exti1510_isr; + handler = stm32_exti1510_isr; shared_cbs = &g_gpio_handlers[10]; nshared = 6; } @@ -347,7 +347,7 @@ int stm32wb_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, pinset |= GPIO_EXTI; } - stm32wb_configgpio(pinset); + stm32_configgpio(pinset); /* Configure rising/falling edges */ diff --git a/arch/arm/src/stm32wb/stm32wb_exti_pwr.c b/arch/arm/src/stm32wb/stm32wb_exti_pwr.c index 8caaed92019..0cc045d27ca 100644 --- a/arch/arm/src/stm32wb/stm32wb_exti_pwr.c +++ b/arch/arm/src/stm32wb/stm32wb_exti_pwr.c @@ -56,14 +56,14 @@ static void *g_callback_arg; ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_exti_pvd_isr + * Name: stm32_exti_pvd_isr * * Description: * EXTI PVD interrupt service routine/dispatcher * ****************************************************************************/ -static int stm32wb_exti_pvd_isr(int irq, void *context, void *arg) +static int stm32_exti_pvd_isr(int irq, void *context, void *arg) { int ret = OK; @@ -86,7 +86,7 @@ static int stm32wb_exti_pvd_isr(int irq, void *context, void *arg) ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_exti_pvd + * Name: stm32_exti_pvd * * Description: * Sets/clears EXTI PVD interrupt. @@ -102,7 +102,7 @@ static int stm32wb_exti_pvd_isr(int irq, void *context, void *arg) * ****************************************************************************/ -int stm32wb_exti_pvd(bool risingedge, bool fallingedge, bool event, +int stm32_exti_pvd(bool risingedge, bool fallingedge, bool event, xcpt_t func, void *arg) { /* Get the previous GPIO IRQ handler; Save the new IRQ handler. */ @@ -114,7 +114,7 @@ int stm32wb_exti_pvd(bool risingedge, bool fallingedge, bool event, if (func) { - irq_attach(STM32_IRQ_PVD, stm32wb_exti_pvd_isr, NULL); + irq_attach(STM32_IRQ_PVD, stm32_exti_pvd_isr, NULL); up_enable_irq(STM32_IRQ_PVD); } else diff --git a/arch/arm/src/stm32wb/stm32wb_exti_wakeup.c b/arch/arm/src/stm32wb/stm32wb_exti_wakeup.c index 0e44b3f4dcc..32fba5d71e9 100644 --- a/arch/arm/src/stm32wb/stm32wb_exti_wakeup.c +++ b/arch/arm/src/stm32wb/stm32wb_exti_wakeup.c @@ -51,14 +51,14 @@ static void *g_callback_arg; ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_exti_wakeup_isr + * Name: stm32_exti_wakeup_isr * * Description: * EXTI periodic WAKEUP interrupt service routine/dispatcher * ****************************************************************************/ -static int stm32wb_exti_wakeup_isr(int irq, void *context, void *arg) +static int stm32_exti_wakeup_isr(int irq, void *context, void *arg) { int ret = OK; @@ -81,7 +81,7 @@ static int stm32wb_exti_wakeup_isr(int irq, void *context, void *arg) ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_exti_wakeup + * Name: stm32_exti_wakeup * * Description: * Sets/clears EXTI wakeup interrupt. @@ -97,7 +97,7 @@ static int stm32wb_exti_wakeup_isr(int irq, void *context, void *arg) * ****************************************************************************/ -int stm32wb_exti_wakeup(bool risingedge, bool fallingedge, bool event, +int stm32_exti_wakeup(bool risingedge, bool fallingedge, bool event, xcpt_t func, void *arg) { g_wakeup_callback = func; @@ -107,7 +107,7 @@ int stm32wb_exti_wakeup(bool risingedge, bool fallingedge, bool event, if (func) { - irq_attach(STM32_IRQ_RTC_WKUP, stm32wb_exti_wakeup_isr, NULL); + irq_attach(STM32_IRQ_RTC_WKUP, stm32_exti_wakeup_isr, NULL); up_enable_irq(STM32_IRQ_RTC_WKUP); } else diff --git a/arch/arm/src/stm32wb/stm32wb_flash.c b/arch/arm/src/stm32wb/stm32wb_flash.c index 346a1355940..4d6432f6af5 100644 --- a/arch/arm/src/stm32wb/stm32wb_flash.c +++ b/arch/arm/src/stm32wb/stm32wb_flash.c @@ -93,7 +93,7 @@ static void flash_unlock(void) { while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY) { - stm32wb_waste(); + stm32_waste(); } if (getreg32(STM32_FLASH_CR) & FLASH_CR_LOCK) @@ -143,7 +143,7 @@ static inline void flash_erase(size_t page) while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY) { - stm32wb_waste(); + stm32_waste(); } modifyreg32(STM32_FLASH_CR, FLASH_CR_PAGE_ERASE, 0); @@ -153,7 +153,7 @@ static inline void flash_erase(size_t page) * Public Functions ****************************************************************************/ -int stm32wb_flash_unlock(void) +int stm32_flash_unlock(void) { int ret; @@ -169,7 +169,7 @@ int stm32wb_flash_unlock(void) return ret; } -int stm32wb_flash_lock(void) +int stm32_flash_lock(void) { int ret; @@ -186,7 +186,7 @@ int stm32wb_flash_lock(void) } /**************************************************************************** - * Name: stm32wb_flash_user_optbytes + * Name: stm32_flash_user_optbytes * * Description: * Modify the contents of the user option bytes (USR OPT) on the flash. @@ -202,7 +202,7 @@ int stm32wb_flash_lock(void) * ****************************************************************************/ -uint32_t stm32wb_flash_user_optbytes(uint32_t clrbits, uint32_t setbits) +uint32_t stm32_flash_user_optbytes(uint32_t clrbits, uint32_t setbits) { uint32_t regval; int ret; @@ -240,7 +240,7 @@ uint32_t stm32wb_flash_user_optbytes(uint32_t clrbits, uint32_t setbits) while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY) { - stm32wb_waste(); + stm32_waste(); } flash_optbytes_lock(); @@ -453,7 +453,7 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t buflen) while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY) { - stm32wb_waste(); + stm32_waste(); } /* Verify */ diff --git a/arch/arm/src/stm32wb/stm32wb_flash.h b/arch/arm/src/stm32wb/stm32wb_flash.h index 36077d8b0f8..704b3106fe8 100644 --- a/arch/arm/src/stm32wb/stm32wb_flash.h +++ b/arch/arm/src/stm32wb/stm32wb_flash.h @@ -35,11 +35,11 @@ * Public Function Prototypes ****************************************************************************/ -int stm32wb_flash_lock(void); -int stm32wb_flash_unlock(void); +int stm32_flash_lock(void); +int stm32_flash_unlock(void); /**************************************************************************** - * Name: stm32wb_flash_user_optbytes + * Name: stm32_flash_user_optbytes * * Description: * Modify the contents of the user option bytes (USR OPT) on the flash. @@ -55,6 +55,6 @@ int stm32wb_flash_unlock(void); * ****************************************************************************/ -uint32_t stm32wb_flash_user_optbytes(uint32_t clrbits, uint32_t setbits); +uint32_t stm32_flash_user_optbytes(uint32_t clrbits, uint32_t setbits); #endif /* __ARCH_ARM_SRC_STM32WB_STM32WB_FLASH_H */ diff --git a/arch/arm/src/stm32wb/stm32wb_freerun.c b/arch/arm/src/stm32wb/stm32wb_freerun.c index bd56695e121..570f3b3f2f1 100644 --- a/arch/arm/src/stm32wb/stm32wb_freerun.c +++ b/arch/arm/src/stm32wb/stm32wb_freerun.c @@ -44,7 +44,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_freerun_handler + * Name: stm32_freerun_handler * * Description: * Timer interrupt callback. When the freerun timer counter overflows, @@ -62,9 +62,9 @@ ****************************************************************************/ #ifndef CONFIG_CLOCK_TIMEKEEPING -static int stm32wb_freerun_handler(int irq, void *context, void *arg) +static int stm32_freerun_handler(int irq, void *context, void *arg) { - struct stm32wb_freerun_s *freerun = (struct stm32wb_freerun_s *)arg; + struct stm32_freerun_s *freerun = (struct stm32_freerun_s *)arg; DEBUGASSERT(freerun != NULL && freerun->overflow < UINT32_MAX); freerun->overflow++; @@ -79,7 +79,7 @@ static int stm32wb_freerun_handler(int irq, void *context, void *arg) ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_freerun_initialize + * Name: stm32_freerun_initialize * * Description: * Initialize the freerun timer wrapper @@ -97,7 +97,7 @@ static int stm32wb_freerun_handler(int irq, void *context, void *arg) * ****************************************************************************/ -int stm32wb_freerun_initialize(struct stm32wb_freerun_s *freerun, int chan, +int stm32_freerun_initialize(struct stm32_freerun_s *freerun, int chan, uint16_t resolution) { uint32_t frequency; @@ -110,7 +110,7 @@ int stm32wb_freerun_initialize(struct stm32wb_freerun_s *freerun, int chan, frequency = USEC_PER_SEC / (uint32_t)resolution; freerun->frequency = frequency; - freerun->tch = stm32wb_tim_init(chan); + freerun->tch = stm32_tim_init(chan); if (!freerun->tch) { tmrerr("ERROR: Failed to allocate TIM%d\n", chan); @@ -135,7 +135,7 @@ int stm32wb_freerun_initialize(struct stm32wb_freerun_s *freerun, int chan, /* Set up to receive the callback when the counter overflow occurs */ - STM32_TIM_SETISR(freerun->tch, stm32wb_freerun_handler, freerun, 0); + STM32_TIM_SETISR(freerun->tch, stm32_freerun_handler, freerun, 0); #endif /* Set timer period */ @@ -156,7 +156,7 @@ int stm32wb_freerun_initialize(struct stm32wb_freerun_s *freerun, int chan, } /**************************************************************************** - * Name: stm32wb_freerun_counter + * Name: stm32_freerun_counter * * Description: * Read the counter register of the free-running timer. @@ -164,7 +164,7 @@ int stm32wb_freerun_initialize(struct stm32wb_freerun_s *freerun, int chan, * Input Parameters: * freerun Caller allocated instance of the freerun state structure. This * structure must have been previously initialized via a call to - * stm32wb_freerun_initialize(); + * stm32_freerun_initialize(); * ts The location in which to return the time from the free-running * timer. * @@ -176,7 +176,7 @@ int stm32wb_freerun_initialize(struct stm32wb_freerun_s *freerun, int chan, #ifndef CONFIG_CLOCK_TIMEKEEPING -int stm32wb_freerun_counter(struct stm32wb_freerun_s *freerun, +int stm32_freerun_counter(struct stm32_freerun_s *freerun, struct timespec *ts) { uint64_t usec; @@ -190,7 +190,7 @@ int stm32wb_freerun_counter(struct stm32wb_freerun_s *freerun, DEBUGASSERT(freerun && freerun->tch && ts); /* Temporarily disable the overflow counter. NOTE that we have to be - * careful here because stm32wb_tc_getpending() will reset the pending + * careful here because stm32_tc_getpending() will reset the pending * interrupt status. If we do not handle the overflow here then, it will * be lost. */ @@ -253,7 +253,7 @@ int stm32wb_freerun_counter(struct stm32wb_freerun_s *freerun, #else /* CONFIG_CLOCK_TIMEKEEPING */ -int stm32wb_freerun_counter(struct stm32wb_freerun_s *freerun, +int stm32_freerun_counter(struct stm32_freerun_s *freerun, uint64_t *counter) { *counter = STM32_TIM_GETCOUNTER(freerun->tch); @@ -263,7 +263,7 @@ int stm32wb_freerun_counter(struct stm32wb_freerun_s *freerun, #endif /* CONFIG_CLOCK_TIMEKEEPING */ /**************************************************************************** - * Name: stm32wb_freerun_uninitialize + * Name: stm32_freerun_uninitialize * * Description: * Stop the free-running timer and release all resources that it uses. @@ -271,7 +271,7 @@ int stm32wb_freerun_counter(struct stm32wb_freerun_s *freerun, * Input Parameters: * freerun Caller allocated instance of the freerun state structure. This * structure must have been previously initialized via a call to - * stm32wb_freerun_initialize(); + * stm32_freerun_initialize(); * * Returned Value: * Zero (OK) is returned on success; a negated errno value is returned @@ -279,7 +279,7 @@ int stm32wb_freerun_counter(struct stm32wb_freerun_s *freerun, * ****************************************************************************/ -int stm32wb_freerun_uninitialize(struct stm32wb_freerun_s *freerun) +int stm32_freerun_uninitialize(struct stm32_freerun_s *freerun) { DEBUGASSERT(freerun && freerun->tch); @@ -291,7 +291,7 @@ int stm32wb_freerun_uninitialize(struct stm32wb_freerun_s *freerun) /* Free the timer */ - stm32wb_tim_deinit(freerun->tch); + stm32_tim_deinit(freerun->tch); freerun->tch = NULL; return OK; diff --git a/arch/arm/src/stm32wb/stm32wb_freerun.h b/arch/arm/src/stm32wb/stm32wb_freerun.h index ef95f59c32e..9f1a86dc817 100644 --- a/arch/arm/src/stm32wb/stm32wb_freerun.h +++ b/arch/arm/src/stm32wb/stm32wb_freerun.h @@ -42,17 +42,17 @@ ****************************************************************************/ /* The freerun client must allocate an instance of this structure and called - * stm32wb_freerun_initialize() before using the freerun facilities. The + * stm32_freerun_initialize() before using the freerun facilities. The * client should not access the contents of this structure directly since * the contents are subject to change. */ -struct stm32wb_freerun_s +struct stm32_freerun_s { uint8_t chan; /* The timer/counter in use */ uint8_t width; /* Width of timer (16- or 32-bits) */ - struct stm32wb_tim_dev_s *tch; /* Pointer returned by - * stm32wb_tim_init() */ + struct stm32_tim_dev_s *tch; /* Pointer returned by + * stm32_tim_init() */ uint32_t frequency; #ifndef CONFIG_CLOCK_TIMEKEEPING @@ -82,7 +82,7 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_freerun_initialize + * Name: stm32_freerun_initialize * * Description: * Initialize the freerun timer wrapper @@ -100,11 +100,11 @@ extern "C" * ****************************************************************************/ -int stm32wb_freerun_initialize(struct stm32wb_freerun_s *freerun, int chan, +int stm32_freerun_initialize(struct stm32_freerun_s *freerun, int chan, uint16_t resolution); /**************************************************************************** - * Name: stm32wb_freerun_counter + * Name: stm32_freerun_counter * * Description: * Read the counter register of the free-running timer. @@ -112,7 +112,7 @@ int stm32wb_freerun_initialize(struct stm32wb_freerun_s *freerun, int chan, * Input Parameters: * freerun Caller allocated instance of the freerun state structure. This * structure must have been previously initialized via a call to - * stm32wb_freerun_initialize(); + * stm32_freerun_initialize(); * ts The location in which to return the time remaining on the * oneshot timer. * @@ -124,18 +124,18 @@ int stm32wb_freerun_initialize(struct stm32wb_freerun_s *freerun, int chan, #ifndef CONFIG_CLOCK_TIMEKEEPING -int stm32wb_freerun_counter(struct stm32wb_freerun_s *freerun, +int stm32_freerun_counter(struct stm32_freerun_s *freerun, struct timespec *ts); #else /* CONFIG_CLOCK_TIMEKEEPING */ -int stm32wb_freerun_counter(struct stm32_freerun_s *freerun, +int stm32_freerun_counter(struct stm32_freerun_s *freerun, uint64_t *counter); #endif /* CONFIG_CLOCK_TIMEKEEPING */ /**************************************************************************** - * Name: stm32wb_freerun_uninitialize + * Name: stm32_freerun_uninitialize * * Description: * Stop the free-running timer and release all resources that it uses. @@ -143,7 +143,7 @@ int stm32wb_freerun_counter(struct stm32_freerun_s *freerun, * Input Parameters: * freerun Caller allocated instance of the freerun state structure. This * structure must have been previously initialized via a call to - * stm32wb_freerun_initialize(); + * stm32_freerun_initialize(); * * Returned Value: * Zero (OK) is returned on success; a negated errno value is returned @@ -151,7 +151,7 @@ int stm32wb_freerun_counter(struct stm32_freerun_s *freerun, * ****************************************************************************/ -int stm32wb_freerun_uninitialize(struct stm32wb_freerun_s *freerun); +int stm32_freerun_uninitialize(struct stm32_freerun_s *freerun); #undef EXTERN #ifdef __cplusplus diff --git a/arch/arm/src/stm32wb/stm32wb_gpio.c b/arch/arm/src/stm32wb/stm32wb_gpio.c index 433df3cea15..a38e7398b74 100644 --- a/arch/arm/src/stm32wb/stm32wb_gpio.c +++ b/arch/arm/src/stm32wb/stm32wb_gpio.c @@ -71,13 +71,13 @@ const uint32_t g_gpiobase[STM32_NPORTS] = ****************************************************************************/ /**************************************************************************** - * Function: stm32wb_gpioinit + * Function: stm32_gpioinit * * Description: * Based on configuration within the .config file, it does: * - Remaps positions of alternative functions. * - * Typically called from stm32wb_start(). + * Typically called from stm32_start(). * * Assumptions: * This function is called early in the initialization sequence so that @@ -85,17 +85,17 @@ const uint32_t g_gpiobase[STM32_NPORTS] = * ****************************************************************************/ -void stm32wb_gpioinit(void) +void stm32_gpioinit(void) { } /**************************************************************************** - * Name: stm32wb_configgpio + * Name: stm32_configgpio * * Description: * Configure a GPIO pin based on bit-encoded description of the pin. * Once it is configured as Alternative (GPIO_ALT|GPIO_CNF_AFPP|...) - * function, it must be unconfigured with stm32wb_unconfiggpio() with + * function, it must be unconfigured with stm32_unconfiggpio() with * the same cfgset first before it can be set to non-alternative function. * * Returned Value: @@ -106,7 +106,7 @@ void stm32wb_gpioinit(void) * To-Do: Auto Power Enable ****************************************************************************/ -int stm32wb_configgpio(uint32_t cfgset) +int stm32_configgpio(uint32_t cfgset) { uintptr_t base; uint32_t regval; @@ -147,7 +147,7 @@ int stm32wb_configgpio(uint32_t cfgset) /* Set the initial output value */ - stm32wb_gpiowrite(cfgset, (cfgset & GPIO_OUTPUT_SET) != 0); + stm32_gpiowrite(cfgset, (cfgset & GPIO_OUTPUT_SET) != 0); pinmode = GPIO_MODER_OUTPUT; break; @@ -305,7 +305,7 @@ int stm32wb_configgpio(uint32_t cfgset) } /**************************************************************************** - * Name: stm32wb_unconfiggpio + * Name: stm32_unconfiggpio * * Description: * Unconfigure a GPIO pin based on bit-encoded description of the pin, set @@ -325,7 +325,7 @@ int stm32wb_configgpio(uint32_t cfgset) * To-Do: Auto Power Disable ****************************************************************************/ -int stm32wb_unconfiggpio(uint32_t cfgset) +int stm32_unconfiggpio(uint32_t cfgset) { /* Reuse port and pin number and set it to default HiZ INPUT */ @@ -334,18 +334,18 @@ int stm32wb_unconfiggpio(uint32_t cfgset) /* To-Do: Mark its unuse for automatic power saving options */ - return stm32wb_configgpio(cfgset); + return stm32_configgpio(cfgset); } /**************************************************************************** - * Name: stm32wb_gpiowrite + * Name: stm32_gpiowrite * * Description: * Write one or zero to the selected GPIO pin * ****************************************************************************/ -void stm32wb_gpiowrite(uint32_t pinset, bool value) +void stm32_gpiowrite(uint32_t pinset, bool value) { uint32_t base; uint32_t bit; @@ -379,14 +379,14 @@ void stm32wb_gpiowrite(uint32_t pinset, bool value) } /**************************************************************************** - * Name: stm32wb_gpioread + * Name: stm32_gpioread * * Description: * Read one or zero from the selected GPIO pin * ****************************************************************************/ -bool stm32wb_gpioread(uint32_t pinset) +bool stm32_gpioread(uint32_t pinset) { uint32_t base; unsigned int port; diff --git a/arch/arm/src/stm32wb/stm32wb_gpio.h b/arch/arm/src/stm32wb/stm32wb_gpio.h index e407a28a564..1103b50cbc2 100644 --- a/arch/arm/src/stm32wb/stm32wb_gpio.h +++ b/arch/arm/src/stm32wb/stm32wb_gpio.h @@ -52,7 +52,7 @@ # define STM32_NPORTS 4 #endif -/* Bit-encoded input to stm32wb_configgpio() */ +/* Bit-encoded input to stm32_configgpio() */ /* Each port bit of the general-purpose I/O (GPIO) ports can be individually * configured by software in several modes: @@ -257,12 +257,12 @@ EXTERN const uint32_t g_gpiobase[STM32_NPORTS]; ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_configgpio + * Name: stm32_configgpio * * Description: * Configure a GPIO pin based on bit-encoded description of the pin. * Once it is configured as Alternative (GPIO_ALT|GPIO_CNF_AFPP|...) - * function, it must be unconfigured with stm32wb_unconfiggpio() with + * function, it must be unconfigured with stm32_unconfiggpio() with * the same cfgset first before it can be set to non-alternative function. * * Returned Value: @@ -271,10 +271,10 @@ EXTERN const uint32_t g_gpiobase[STM32_NPORTS]; * ****************************************************************************/ -int stm32wb_configgpio(uint32_t cfgset); +int stm32_configgpio(uint32_t cfgset); /**************************************************************************** - * Name: stm32wb_unconfiggpio + * Name: stm32_unconfiggpio * * Description: * Unconfigure a GPIO pin based on bit-encoded description of the pin, set @@ -293,30 +293,30 @@ int stm32wb_configgpio(uint32_t cfgset); * ****************************************************************************/ -int stm32wb_unconfiggpio(uint32_t cfgset); +int stm32_unconfiggpio(uint32_t cfgset); /**************************************************************************** - * Name: stm32wb_gpiowrite + * Name: stm32_gpiowrite * * Description: * Write one or zero to the selected GPIO pin * ****************************************************************************/ -void stm32wb_gpiowrite(uint32_t pinset, bool value); +void stm32_gpiowrite(uint32_t pinset, bool value); /**************************************************************************** - * Name: stm32wb_gpioread + * Name: stm32_gpioread * * Description: * Read one or zero from the selected GPIO pin * ****************************************************************************/ -bool stm32wb_gpioread(uint32_t pinset); +bool stm32_gpioread(uint32_t pinset); /**************************************************************************** - * Name: stm32wb_gpiosetevent + * Name: stm32_gpiosetevent * * Description: * Sets/clears GPIO based event and interrupt triggers. @@ -335,11 +335,11 @@ bool stm32wb_gpioread(uint32_t pinset); * ****************************************************************************/ -int stm32wb_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, +int stm32_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, bool event, xcpt_t func, void *arg); /**************************************************************************** - * Function: stm32wb_dumpgpio + * Function: stm32_dumpgpio * * Description: * Dump all GPIO registers associated with the provided base address @@ -347,23 +347,23 @@ int stm32wb_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, ****************************************************************************/ #ifdef CONFIG_DEBUG_FEATURES -int stm32wb_dumpgpio(uint32_t pinset, const char *msg); +int stm32_dumpgpio(uint32_t pinset, const char *msg); #else -# define stm32wb_dumpgpio(p,m) +# define stm32_dumpgpio(p,m) #endif /**************************************************************************** - * Function: stm32wb_gpioinit + * Function: stm32_gpioinit * * Description: * Based on configuration within the .config file, it does: * - Remaps positions of alternative functions. * - * Typically called from stm32wb_start(). + * Typically called from stm32_start(). * ****************************************************************************/ -void stm32wb_gpioinit(void); +void stm32_gpioinit(void); #undef EXTERN #if defined(__cplusplus) diff --git a/arch/arm/src/stm32wb/stm32wb_i2c.c b/arch/arm/src/stm32wb/stm32wb_i2c.c index 182d588027a..85d42440330 100644 --- a/arch/arm/src/stm32wb/stm32wb_i2c.c +++ b/arch/arm/src/stm32wb/stm32wb_i2c.c @@ -245,10 +245,10 @@ */ #ifndef CONFIG_I2C_TRACE -# define stm32wb_i2c_tracereset(p) -# define stm32wb_i2c_tracenew(p,s) -# define stm32wb_i2c_traceevent(p,e,a) -# define stm32wb_i2c_tracedump(p) +# define stm32_i2c_tracereset(p) +# define stm32_i2c_tracenew(p,s) +# define stm32_i2c_traceevent(p,e,a) +# define stm32_i2c_tracedump(p) #endif #ifndef CONFIG_I2C_NTRACE @@ -261,7 +261,7 @@ /* Interrupt state */ -enum stm32wb_intstate_e +enum stm32_intstate_e { INTSTATE_IDLE = 0, /* No I2C activity */ INTSTATE_WAITING, /* Waiting for completion of interrupt activity */ @@ -270,7 +270,7 @@ enum stm32wb_intstate_e /* Trace events */ -enum stm32wb_trace_e +enum stm32_trace_e { I2CEVENT_NONE = 0, I2CEVENT_STATE_ERROR, @@ -293,18 +293,18 @@ enum stm32wb_trace_e /* Trace data */ -struct stm32wb_trace_s +struct stm32_trace_s { uint32_t status; /* I2C 32-bit SR2|SR1 status */ uint32_t count; /* Interrupt count when status change */ - enum stm32wb_intstate_e event; /* Last event that occurred with this status */ + enum stm32_intstate_e event; /* Last event that occurred with status */ uint32_t parm; /* Parameter associated with the event */ clock_t time; /* First of event or first status */ }; /* I2C Device hardware configuration */ -struct stm32wb_i2c_config_s +struct stm32_i2c_config_s { uint32_t base; /* I2C base address */ uint32_t clk_bit; /* Clock enable bit */ @@ -319,18 +319,18 @@ struct stm32wb_i2c_config_s /* I2C Device Private Data */ -struct stm32wb_i2c_priv_s +struct stm32_i2c_priv_s { /* Port configuration */ - const struct stm32wb_i2c_config_s *config; + const struct stm32_i2c_config_s *config; int refs; /* Reference count */ mutex_t lock; /* Mutual exclusion mutex */ #ifndef CONFIG_I2C_POLLED sem_t sem_isr; /* Interrupt wait semaphore */ #endif - volatile uint8_t intstate; /* Interrupt handshake (see enum stm32wb_intstate_e) */ + volatile uint8_t intstate; /* Interrupt handshake (see enum stm32_intstate_e) */ uint8_t msgc; /* Message count */ struct i2c_msg_s *msgv; /* Message list */ @@ -348,7 +348,7 @@ struct stm32wb_i2c_priv_s /* The actual trace data */ - struct stm32wb_trace_s trace[CONFIG_I2C_NTRACE]; + struct stm32_trace_s trace[CONFIG_I2C_NTRACE]; #endif uint32_t status; /* End of transfer SR2|SR1 status */ @@ -360,10 +360,10 @@ struct stm32wb_i2c_priv_s /* I2C Device, Instance */ -struct stm32wb_i2c_inst_s +struct stm32_i2c_inst_s { - const struct i2c_ops_s *ops; /* Standard I2C operations */ - struct stm32wb_i2c_priv_s *priv; /* Common driver private data structure */ + const struct i2c_ops_s *ops; /* Standard I2C operations */ + struct stm32_i2c_priv_s *priv; /* Common driver private data structure */ }; /**************************************************************************** @@ -371,57 +371,57 @@ struct stm32wb_i2c_inst_s ****************************************************************************/ static inline -uint16_t stm32wb_i2c_getreg(struct stm32wb_i2c_priv_s *priv, +uint16_t stm32_i2c_getreg(struct stm32_i2c_priv_s *priv, uint8_t offset); static inline -void stm32wb_i2c_putreg(struct stm32wb_i2c_priv_s *priv, +void stm32_i2c_putreg(struct stm32_i2c_priv_s *priv, uint8_t offset, uint16_t value); static inline -void stm32wb_i2c_putreg32(struct stm32wb_i2c_priv_s *priv, +void stm32_i2c_putreg32(struct stm32_i2c_priv_s *priv, uint8_t offset, uint32_t value); static inline -void stm32wb_i2c_modifyreg32(struct stm32wb_i2c_priv_s *priv, +void stm32_i2c_modifyreg32(struct stm32_i2c_priv_s *priv, uint8_t offset, uint32_t clearbits, uint32_t setbits); #ifdef CONFIG_STM32WB_I2C_DYNTIMEO -static uint32_t stm32wb_i2c_toticks(int msgc, struct i2c_msg_s *msgs); +static uint32_t stm32_i2c_toticks(int msgc, struct i2c_msg_s *msgs); #endif /* CONFIG_STM32WB_I2C_DYNTIMEO */ static inline -int stm32wb_i2c_sem_waitdone(struct stm32wb_i2c_priv_s *priv); +int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv); static inline -void stm32wb_i2c_sem_waitstop(struct stm32wb_i2c_priv_s *priv); +void stm32_i2c_sem_waitstop(struct stm32_i2c_priv_s *priv); #ifdef CONFIG_I2C_TRACE -static void stm32wb_i2c_tracereset(struct stm32wb_i2c_priv_s *priv); -static void stm32wb_i2c_tracenew(struct stm32wb_i2c_priv_s *priv, +static void stm32_i2c_tracereset(struct stm32_i2c_priv_s *priv); +static void stm32_i2c_tracenew(struct stm32_i2c_priv_s *priv, uint32_t status); static void -stm32wb_i2c_traceevent(struct stm32wb_i2c_priv_s *priv, - enum stm32wb_trace_e event, uint32_t parm); -static void stm32wb_i2c_tracedump(struct stm32wb_i2c_priv_s *priv); +stm32_i2c_traceevent(struct stm32_i2c_priv_s *priv, + enum stm32_trace_e event, uint32_t parm); +static void stm32_i2c_tracedump(struct stm32_i2c_priv_s *priv); #endif /* CONFIG_I2C_TRACE */ -static void stm32wb_i2c_setclock(struct stm32wb_i2c_priv_s *priv, +static void stm32_i2c_setclock(struct stm32_i2c_priv_s *priv, uint32_t frequency); static inline -void stm32wb_i2c_sendstart(struct stm32wb_i2c_priv_s *priv); -static inline void stm32wb_i2c_sendstop(struct stm32wb_i2c_priv_s *priv); +void stm32_i2c_sendstart(struct stm32_i2c_priv_s *priv); +static inline void stm32_i2c_sendstop(struct stm32_i2c_priv_s *priv); static inline -uint32_t stm32wb_i2c_getstatus(struct stm32wb_i2c_priv_s *priv); -static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv); +uint32_t stm32_i2c_getstatus(struct stm32_i2c_priv_s *priv); +static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv); #ifndef CONFIG_I2C_POLLED -static int stm32wb_i2c_isr(int irq, void *context, void *arg); +static int stm32_i2c_isr(int irq, void *context, void *arg); #endif -static int stm32wb_i2c_init(struct stm32wb_i2c_priv_s *priv); -static int stm32wb_i2c_deinit(struct stm32wb_i2c_priv_s *priv); +static int stm32_i2c_init(struct stm32_i2c_priv_s *priv); +static int stm32_i2c_deinit(struct stm32_i2c_priv_s *priv); -static int stm32wb_i2c_process(struct i2c_master_s *dev, +static int stm32_i2c_process(struct i2c_master_s *dev, struct i2c_msg_s *msgs, int count); -static int stm32wb_i2c_transfer(struct i2c_master_s *dev, +static int stm32_i2c_transfer(struct i2c_master_s *dev, struct i2c_msg_s *msgs, int count); #ifdef CONFIG_I2C_RESET -static int stm32wb_i2c_reset(struct i2c_master_s *dev); +static int stm32_i2c_reset(struct i2c_master_s *dev); #endif #ifdef CONFIG_PM -static int stm32wb_i2c_pm_prepare(struct pm_callback_s *cb, int domain, +static int stm32_i2c_pm_prepare(struct pm_callback_s *cb, int domain, enum pm_state_e pmstate); #endif @@ -430,7 +430,7 @@ static int stm32wb_i2c_pm_prepare(struct pm_callback_s *cb, int domain, ****************************************************************************/ #ifdef CONFIG_STM32WB_I2C1 -static const struct stm32wb_i2c_config_s stm32wb_i2c1_config = +static const struct stm32_i2c_config_s stm32_i2c1_config = { .base = STM32_I2C1_BASE, .clk_bit = RCC_APB1ENR1_I2C1EN, @@ -443,9 +443,9 @@ static const struct stm32wb_i2c_config_s stm32wb_i2c1_config = #endif }; -static struct stm32wb_i2c_priv_s stm32wb_i2c1_priv = +static struct stm32_i2c_priv_s stm32_i2c1_priv = { - .config = &stm32wb_i2c1_config, + .config = &stm32_i2c1_config, .refs = 0, .lock = NXMUTEX_INITIALIZER, #ifndef CONFIG_I2C_POLLED @@ -460,13 +460,13 @@ static struct stm32wb_i2c_priv_s stm32wb_i2c1_priv = .flags = 0, .status = 0, #ifdef CONFIG_PM - .pm_cb.prepare = stm32wb_i2c_pm_prepare, + .pm_cb.prepare = stm32_i2c_pm_prepare, #endif }; #endif #ifdef CONFIG_STM32WB_I2C3 -static const struct stm32wb_i2c_config_s stm32wb_i2c3_config = +static const struct stm32_i2c_config_s stm32_i2c3_config = { .base = STM32_I2C3_BASE, .clk_bit = RCC_APB1ENR1_I2C3EN, @@ -479,9 +479,9 @@ static const struct stm32wb_i2c_config_s stm32wb_i2c3_config = #endif }; -static struct stm32wb_i2c_priv_s stm32wb_i2c3_priv = +static struct stm32_i2c_priv_s stm32_i2c3_priv = { - .config = &stm32wb_i2c3_config, + .config = &stm32_i2c3_config, .refs = 0, .lock = NXMUTEX_INITIALIZER, #ifndef CONFIG_I2C_POLLED @@ -496,18 +496,18 @@ static struct stm32wb_i2c_priv_s stm32wb_i2c3_priv = .flags = 0, .status = 0, #ifdef CONFIG_PM - .pm_cb.prepare = stm32wb_i2c_pm_prepare, + .pm_cb.prepare = stm32_i2c_pm_prepare, #endif }; #endif /* Device Structures, Instantiation */ -static const struct i2c_ops_s stm32wb_i2c_ops = +static const struct i2c_ops_s stm32_i2c_ops = { - .transfer = stm32wb_i2c_transfer, + .transfer = stm32_i2c_transfer, #ifdef CONFIG_I2C_RESET - .reset = stm32wb_i2c_reset + .reset = stm32_i2c_reset #endif }; @@ -516,7 +516,7 @@ static const struct i2c_ops_s stm32wb_i2c_ops = ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_i2c_getreg + * Name: stm32_i2c_getreg * * Description: * Get a 16-bit register value by offset @@ -524,14 +524,14 @@ static const struct i2c_ops_s stm32wb_i2c_ops = ****************************************************************************/ static inline -uint16_t stm32wb_i2c_getreg(struct stm32wb_i2c_priv_s *priv, +uint16_t stm32_i2c_getreg(struct stm32_i2c_priv_s *priv, uint8_t offset) { return getreg16(priv->config->base + offset); } /**************************************************************************** - * Name: stm32wb_i2c_getreg32 + * Name: stm32_i2c_getreg32 * * Description: * Get a 32-bit register value by offset @@ -539,42 +539,42 @@ uint16_t stm32wb_i2c_getreg(struct stm32wb_i2c_priv_s *priv, ****************************************************************************/ static inline -uint32_t stm32wb_i2c_getreg32(struct stm32wb_i2c_priv_s *priv, +uint32_t stm32_i2c_getreg32(struct stm32_i2c_priv_s *priv, uint8_t offset) { return getreg32(priv->config->base + offset); } /**************************************************************************** - * Name: stm32wb_i2c_putreg + * Name: stm32_i2c_putreg * * Description: * Put a 16-bit register value by offset * ****************************************************************************/ -static inline void stm32wb_i2c_putreg(struct stm32wb_i2c_priv_s *priv, +static inline void stm32_i2c_putreg(struct stm32_i2c_priv_s *priv, uint8_t offset, uint16_t value) { putreg16(value, priv->config->base + offset); } /**************************************************************************** - * Name: stm32wb_i2c_putreg32 + * Name: stm32_i2c_putreg32 * * Description: * Put a 32-bit register value by offset * ****************************************************************************/ -static inline void stm32wb_i2c_putreg32(struct stm32wb_i2c_priv_s *priv, +static inline void stm32_i2c_putreg32(struct stm32_i2c_priv_s *priv, uint8_t offset, uint32_t value) { putreg32(value, priv->config->base + offset); } /**************************************************************************** - * Name: stm32wb_i2c_modifyreg32 + * Name: stm32_i2c_modifyreg32 * * Description: * Modify a 32-bit register value by offset @@ -582,7 +582,7 @@ static inline void stm32wb_i2c_putreg32(struct stm32wb_i2c_priv_s *priv, ****************************************************************************/ static inline -void stm32wb_i2c_modifyreg32(struct stm32wb_i2c_priv_s *priv, +void stm32_i2c_modifyreg32(struct stm32_i2c_priv_s *priv, uint8_t offset, uint32_t clearbits, uint32_t setbits) { @@ -590,7 +590,7 @@ void stm32wb_i2c_modifyreg32(struct stm32wb_i2c_priv_s *priv, } /**************************************************************************** - * Name: stm32wb_i2c_toticks + * Name: stm32_i2c_toticks * * Description: * Return a micro-second delay based on the number of bytes left to be @@ -599,7 +599,7 @@ void stm32wb_i2c_modifyreg32(struct stm32wb_i2c_priv_s *priv, ****************************************************************************/ #ifdef CONFIG_STM32WB_I2C_DYNTIMEO -static uint32_t stm32wb_i2c_toticks(int msgc, struct i2c_msg_s *msgs) +static uint32_t stm32_i2c_toticks(int msgc, struct i2c_msg_s *msgs) { size_t bytecount = 0; int i; @@ -620,7 +620,7 @@ static uint32_t stm32wb_i2c_toticks(int msgc, struct i2c_msg_s *msgs) #endif /**************************************************************************** - * Name: stm32wb_i2c_enableinterrupts + * Name: stm32_i2c_enableinterrupts * * Description: * Enable I2C interrupts @@ -629,15 +629,15 @@ static uint32_t stm32wb_i2c_toticks(int msgc, struct i2c_msg_s *msgs) #ifndef CONFIG_I2C_POLLED static inline -void stm32wb_i2c_enableinterrupts(struct stm32wb_i2c_priv_s *priv) +void stm32_i2c_enableinterrupts(struct stm32_i2c_priv_s *priv) { - stm32wb_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, 0, + stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, 0, (I2C_CR1_TXRX | I2C_CR1_NACKIE)); } #endif /**************************************************************************** - * Name: stm32wb_i2c_sem_waitdone + * Name: stm32_i2c_sem_waitdone * * Description: * Wait for a transfer to complete @@ -649,7 +649,7 @@ void stm32wb_i2c_enableinterrupts(struct stm32wb_i2c_priv_s *priv) #ifndef CONFIG_I2C_POLLED static inline -int stm32wb_i2c_sem_waitdone(struct stm32wb_i2c_priv_s *priv) +int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv) { irqstate_t flags; int ret; @@ -659,11 +659,11 @@ int stm32wb_i2c_sem_waitdone(struct stm32wb_i2c_priv_s *priv) /* Enable I2C interrupts */ /* The TXIE and RXIE interrupts are enabled initially in - * stm32wb_i2c_process. The remainder of the interrupts, including + * stm32_i2c_process. The remainder of the interrupts, including * error-related, are enabled here. */ - stm32wb_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, 0, + stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, 0, (I2C_CR1_ALLINTS & ~I2C_CR1_TXRX)); /* Signal the interrupt handler that we are waiting */ @@ -675,7 +675,7 @@ int stm32wb_i2c_sem_waitdone(struct stm32wb_i2c_priv_s *priv) #ifdef CONFIG_STM32WB_I2C_DYNTIMEO ret = nxsem_tickwait_uninterruptible(&priv->sem_isr, - stm32wb_i2c_toticks(priv->msgc, priv->msgv)); + stm32_i2c_toticks(priv->msgc, priv->msgv)); #else ret = nxsem_tickwait_uninterruptible(&priv->sem_isr, CONFIG_STM32WB_I2CTIMEOTICKS); @@ -701,14 +701,14 @@ int stm32wb_i2c_sem_waitdone(struct stm32wb_i2c_priv_s *priv) /* Disable I2C interrupts */ - stm32wb_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, I2C_CR1_ALLINTS, 0); + stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, I2C_CR1_ALLINTS, 0); leave_critical_section(flags); return ret; } #else static inline -int stm32wb_i2c_sem_waitdone(struct stm32wb_i2c_priv_s *priv) +int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv) { clock_t timeout; clock_t start; @@ -718,7 +718,7 @@ int stm32wb_i2c_sem_waitdone(struct stm32wb_i2c_priv_s *priv) /* Get the timeout value */ #ifdef CONFIG_STM32WB_I2C_DYNTIMEO - timeout = stm32wb_i2c_toticks(priv->msgc, priv->msgv); + timeout = stm32_i2c_toticks(priv->msgc, priv->msgv); #else timeout = CONFIG_STM32WB_I2CTIMEOTICKS; #endif @@ -741,7 +741,7 @@ int stm32wb_i2c_sem_waitdone(struct stm32wb_i2c_priv_s *priv) * reports that it is done. */ - stm32wb_i2c_isr_process(priv); + stm32_i2c_isr_process(priv); } /* Loop until the transfer is complete. */ @@ -760,92 +760,92 @@ int stm32wb_i2c_sem_waitdone(struct stm32wb_i2c_priv_s *priv) #endif /**************************************************************************** - * Name: stm32wb_i2c_set_7bit_address + * Name: stm32_i2c_set_7bit_address * * Description: * ****************************************************************************/ static inline void -stm32wb_i2c_set_7bit_address(struct stm32wb_i2c_priv_s *priv) +stm32_i2c_set_7bit_address(struct stm32_i2c_priv_s *priv) { - stm32wb_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_SADD7_MASK, + stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_SADD7_MASK, (priv->msgv->addr << I2C_CR2_SADD7_SHIFT) & I2C_CR2_SADD7_MASK); } /**************************************************************************** - * Name: stm32wb_i2c_set_bytes_to_transfer + * Name: stm32_i2c_set_bytes_to_transfer * * Description: * ****************************************************************************/ static inline void -stm32wb_i2c_set_bytes_to_transfer(struct stm32wb_i2c_priv_s *priv, +stm32_i2c_set_bytes_to_transfer(struct stm32_i2c_priv_s *priv, uint8_t n_bytes) { - stm32wb_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_NBYTES_MASK, + stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_NBYTES_MASK, (n_bytes << I2C_CR2_NBYTES_SHIFT)); } /**************************************************************************** - * Name: stm32wb_i2c_set_write_transfer_dir + * Name: stm32_i2c_set_write_transfer_dir * * Description: * ****************************************************************************/ static inline void -stm32wb_i2c_set_write_transfer_dir(struct stm32wb_i2c_priv_s *priv) +stm32_i2c_set_write_transfer_dir(struct stm32_i2c_priv_s *priv) { - stm32wb_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_RD_WRN, 0); + stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_RD_WRN, 0); } /**************************************************************************** - * Name: stm32wb_i2c_set_read_transfer_dir + * Name: stm32_i2c_set_read_transfer_dir * * Description: * ****************************************************************************/ static inline void -stm32wb_i2c_set_read_transfer_dir(struct stm32wb_i2c_priv_s *priv) +stm32_i2c_set_read_transfer_dir(struct stm32_i2c_priv_s *priv) { - stm32wb_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, + stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_RD_WRN); } /**************************************************************************** - * Name: stm32wb_i2c_enable_reload + * Name: stm32_i2c_enable_reload * * Description: * ****************************************************************************/ static inline void -stm32wb_i2c_enable_reload(struct stm32wb_i2c_priv_s *priv) +stm32_i2c_enable_reload(struct stm32_i2c_priv_s *priv) { - stm32wb_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, + stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_RELOAD); } /**************************************************************************** - * Name: stm32wb_i2c_disable_reload + * Name: stm32_i2c_disable_reload * * Description: * ****************************************************************************/ static inline void -stm32wb_i2c_disable_reload(struct stm32wb_i2c_priv_s *priv) +stm32_i2c_disable_reload(struct stm32_i2c_priv_s *priv) { - stm32wb_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, + stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_RELOAD, 0); } /**************************************************************************** - * Name: stm32wb_i2c_sem_waitstop + * Name: stm32_i2c_sem_waitstop * * Description: * Wait for a STOP to complete @@ -853,7 +853,7 @@ stm32wb_i2c_disable_reload(struct stm32wb_i2c_priv_s *priv) ****************************************************************************/ static inline -void stm32wb_i2c_sem_waitstop(struct stm32wb_i2c_priv_s *priv) +void stm32_i2c_sem_waitstop(struct stm32_i2c_priv_s *priv) { clock_t start; clock_t elapsed; @@ -880,7 +880,7 @@ void stm32wb_i2c_sem_waitstop(struct stm32wb_i2c_priv_s *priv) /* Check for STOP condition */ - cr = stm32wb_i2c_getreg32(priv, STM32_I2C_CR2_OFFSET); + cr = stm32_i2c_getreg32(priv, STM32_I2C_CR2_OFFSET); if ((cr & I2C_CR2_STOP) == 0) { return; @@ -888,7 +888,7 @@ void stm32wb_i2c_sem_waitstop(struct stm32wb_i2c_priv_s *priv) /* Check for timeout error */ - sr = stm32wb_i2c_getreg(priv, STM32_I2C_ISR_OFFSET); + sr = stm32_i2c_getreg(priv, STM32_I2C_ISR_OFFSET); if ((sr & I2C_INT_TIMEOUT) != 0) { i2cerr("ERROR: waiting for a STOP isr timeout, elapsed: %lu\n", @@ -909,7 +909,7 @@ void stm32wb_i2c_sem_waitstop(struct stm32wb_i2c_priv_s *priv) } /**************************************************************************** - * Name: stm32wb_i2c_trace* + * Name: stm32_i2c_trace* * * Description: * I2C trace instrumentation @@ -917,9 +917,9 @@ void stm32wb_i2c_sem_waitstop(struct stm32wb_i2c_priv_s *priv) ****************************************************************************/ #ifdef CONFIG_I2C_TRACE -static void stm32wb_i2c_traceclear(struct stm32wb_i2c_priv_s *priv) +static void stm32_i2c_traceclear(struct stm32_i2c_priv_s *priv) { - struct stm32wb_trace_s *trace = &priv->trace[priv->tndx]; + struct stm32_trace_s *trace = &priv->trace[priv->tndx]; trace->status = 0; /* I2C 32-bit status */ trace->count = 0; /* Interrupt count when status change */ @@ -928,19 +928,19 @@ static void stm32wb_i2c_traceclear(struct stm32wb_i2c_priv_s *priv) trace->time = 0; /* Time of first status or event */ } -static void stm32wb_i2c_tracereset(struct stm32wb_i2c_priv_s *priv) +static void stm32_i2c_tracereset(struct stm32_i2c_priv_s *priv) { /* Reset the trace info for a new data collection */ priv->tndx = 0; priv->start_time = clock_systime_ticks(); - stm32wb_i2c_traceclear(priv); + stm32_i2c_traceclear(priv); } -static void stm32wb_i2c_tracenew(struct stm32wb_i2c_priv_s *priv, +static void stm32_i2c_tracenew(struct stm32_i2c_priv_s *priv, uint32_t status) { - struct stm32wb_trace_s *trace = &priv->trace[priv->tndx]; + struct stm32_trace_s *trace = &priv->trace[priv->tndx]; /* Is the current entry uninitialized? Has the status changed? */ @@ -966,7 +966,7 @@ static void stm32wb_i2c_tracenew(struct stm32wb_i2c_priv_s *priv, /* Initialize the new trace entry */ - stm32wb_i2c_traceclear(priv); + stm32_i2c_traceclear(priv); trace->status = status; trace->count = 1; trace->time = clock_systime_ticks(); @@ -979,10 +979,10 @@ static void stm32wb_i2c_tracenew(struct stm32wb_i2c_priv_s *priv, } } -static void stm32wb_i2c_traceevent(struct stm32wb_i2c_priv_s *priv, - enum stm32wb_trace_e event, uint32_t parm) +static void stm32_i2c_traceevent(struct stm32_i2c_priv_s *priv, + enum stm32_trace_e event, uint32_t parm) { - struct stm32wb_trace_s *trace; + struct stm32_trace_s *trace; if (event != I2CEVENT_NONE) { @@ -1002,13 +1002,13 @@ static void stm32wb_i2c_traceevent(struct stm32wb_i2c_priv_s *priv, } priv->tndx++; - stm32wb_i2c_traceclear(priv); + stm32_i2c_traceclear(priv); } } -static void stm32wb_i2c_tracedump(struct stm32wb_i2c_priv_s *priv) +static void stm32_i2c_tracedump(struct stm32_i2c_priv_s *priv) { - struct stm32wb_trace_s *trace; + struct stm32_trace_s *trace; int i; syslog(LOG_DEBUG, "Elapsed time: %d\n", @@ -1026,7 +1026,7 @@ static void stm32wb_i2c_tracedump(struct stm32wb_i2c_priv_s *priv) #endif /* CONFIG_I2C_TRACE */ /**************************************************************************** - * Name: stm32wb_i2c_setclock + * Name: stm32_i2c_setclock * * Description: * @@ -1066,7 +1066,7 @@ static void stm32wb_i2c_tracedump(struct stm32wb_i2c_priv_s *priv) * ****************************************************************************/ -static void stm32wb_i2c_setclock(struct stm32wb_i2c_priv_s *priv, +static void stm32_i2c_setclock(struct stm32_i2c_priv_s *priv, uint32_t frequency) { uint32_t pe; @@ -1076,10 +1076,10 @@ static void stm32wb_i2c_setclock(struct stm32wb_i2c_priv_s *priv, { /* I2C peripheral must be disabled to update clocking configuration */ - pe = stm32wb_i2c_getreg32(priv, STM32_I2C_CR1_OFFSET) & I2C_CR1_PE; + pe = stm32_i2c_getreg32(priv, STM32_I2C_CR1_OFFSET) & I2C_CR1_PE; if (pe) { - stm32wb_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, + stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, I2C_CR1_PE, 0); } @@ -1128,11 +1128,11 @@ static void stm32wb_i2c_setclock(struct stm32wb_i2c_priv_s *priv, } #endif - stm32wb_i2c_putreg32(priv, STM32_I2C_TIMINGR_OFFSET, timingr); + stm32_i2c_putreg32(priv, STM32_I2C_TIMINGR_OFFSET, timingr); if (pe) { - stm32wb_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, + stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, 0, I2C_CR1_PE); } @@ -1141,7 +1141,7 @@ static void stm32wb_i2c_setclock(struct stm32wb_i2c_priv_s *priv, } /**************************************************************************** - * Name: stm32wb_i2c_sendstart + * Name: stm32_i2c_sendstart * * Description: * Send the START condition / force Master mode @@ -1168,7 +1168,7 @@ static void stm32wb_i2c_setclock(struct stm32wb_i2c_priv_s *priv, ****************************************************************************/ static inline -void stm32wb_i2c_sendstart(struct stm32wb_i2c_priv_s *priv) +void stm32_i2c_sendstart(struct stm32_i2c_priv_s *priv) { bool next_norestart = false; @@ -1230,13 +1230,13 @@ void stm32wb_i2c_sendstart(struct stm32wb_i2c_priv_s *priv) { i2cinfo("RELOAD enabled: dcnt = %i msgc = %i\n", priv->dcnt, priv->msgc); - stm32wb_i2c_enable_reload(priv); + stm32_i2c_enable_reload(priv); } else { i2cinfo("RELOAD disable: dcnt = %i msgc = %i\n", priv->dcnt, priv->msgc); - stm32wb_i2c_disable_reload(priv); + stm32_i2c_disable_reload(priv); } /* Set the number of bytes to transfer (I2C_CR2->NBYTES) to the number of @@ -1246,18 +1246,18 @@ void stm32wb_i2c_sendstart(struct stm32wb_i2c_priv_s *priv) if (priv->dcnt > 255) { - stm32wb_i2c_set_bytes_to_transfer(priv, 255); + stm32_i2c_set_bytes_to_transfer(priv, 255); } else { - stm32wb_i2c_set_bytes_to_transfer(priv, priv->dcnt); + stm32_i2c_set_bytes_to_transfer(priv, priv->dcnt); } /* Set the (7 bit) address. * 10 bit addressing is not yet supported. */ - stm32wb_i2c_set_7bit_address(priv); + stm32_i2c_set_7bit_address(priv); /* The flag of the current message is used to determine the direction of * transfer required for the current message. @@ -1265,11 +1265,11 @@ void stm32wb_i2c_sendstart(struct stm32wb_i2c_priv_s *priv) if (priv->flags & I2C_M_READ) { - stm32wb_i2c_set_read_transfer_dir(priv); + stm32_i2c_set_read_transfer_dir(priv); } else { - stm32wb_i2c_set_write_transfer_dir(priv); + stm32_i2c_set_write_transfer_dir(priv); } /* Set the I2C_CR2->START bit to 1 to instruct the hardware to send the @@ -1279,11 +1279,11 @@ void stm32wb_i2c_sendstart(struct stm32wb_i2c_priv_s *priv) i2cinfo("Sending START: dcnt=%i msgc=%i flags=0x%04x\n", priv->dcnt, priv->msgc, priv->flags); - stm32wb_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_START); + stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_START); } /**************************************************************************** - * Name: stm32wb_i2c_sendstop + * Name: stm32_i2c_sendstop * * Description: * Send the STOP conditions @@ -1295,17 +1295,17 @@ void stm32wb_i2c_sendstart(struct stm32wb_i2c_priv_s *priv) ****************************************************************************/ static inline -void stm32wb_i2c_sendstop(struct stm32wb_i2c_priv_s *priv) +void stm32_i2c_sendstop(struct stm32_i2c_priv_s *priv) { i2cinfo("Sending STOP\n"); - stm32wb_i2c_traceevent(priv, I2CEVENT_WRITE_STOP, 0); + stm32_i2c_traceevent(priv, I2CEVENT_WRITE_STOP, 0); - stm32wb_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, + stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_STOP); } /**************************************************************************** - * Name: stm32wb_i2c_getstatus + * Name: stm32_i2c_getstatus * * Description: * Get 32-bit status (SR1 and SR2 combined) @@ -1313,13 +1313,13 @@ void stm32wb_i2c_sendstop(struct stm32wb_i2c_priv_s *priv) ****************************************************************************/ static inline -uint32_t stm32wb_i2c_getstatus(struct stm32wb_i2c_priv_s *priv) +uint32_t stm32_i2c_getstatus(struct stm32_i2c_priv_s *priv) { return getreg32(priv->config->base + STM32_I2C_ISR_OFFSET); } /**************************************************************************** - * Name: stm32wb_i2c_clearinterrupts + * Name: stm32_i2c_clearinterrupts * * Description: * Clear all interrupts @@ -1327,14 +1327,14 @@ uint32_t stm32wb_i2c_getstatus(struct stm32wb_i2c_priv_s *priv) ****************************************************************************/ static inline -void stm32wb_i2c_clearinterrupts(struct stm32wb_i2c_priv_s *priv) +void stm32_i2c_clearinterrupts(struct stm32_i2c_priv_s *priv) { - stm32wb_i2c_modifyreg32(priv, STM32_I2C_ICR_OFFSET, + stm32_i2c_modifyreg32(priv, STM32_I2C_ICR_OFFSET, 0, I2C_ICR_CLEARMASK); } /**************************************************************************** - * Name: stm32wb_i2c_isr_process + * Name: stm32_i2c_isr_process * * Description: * Common interrupt service routine (ISR) that handles I2C protocol logic. @@ -1342,22 +1342,22 @@ void stm32wb_i2c_clearinterrupts(struct stm32wb_i2c_priv_s *priv) * * This ISR is activated and deactivated by: * - * stm32wb_i2c_process + * stm32_i2c_process * and - * stm32wb_i2c_waitdone + * stm32_i2c_waitdone * * Input Parameters: * priv - The private struct of the I2C driver. * ****************************************************************************/ -static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) +static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv) { uint32_t status; /* Get state of the I2C controller */ - status = stm32wb_i2c_getreg32(priv, STM32_I2C_ISR_OFFSET); + status = stm32_i2c_getreg32(priv, STM32_I2C_ISR_OFFSET); i2cinfo("ENTER: status = 0x%08" PRIx32 "\n", status); @@ -1367,8 +1367,8 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) /* If this is a new transmission set up the trace table accordingly */ - stm32wb_i2c_tracenew(priv, status); - stm32wb_i2c_traceevent(priv, I2CEVENT_ISR_CALL, 0); + stm32_i2c_tracenew(priv, status); + stm32_i2c_traceevent(priv, I2CEVENT_ISR_CALL, 0); /* ------------------- Start of I2C protocol handling ------------------ */ @@ -1410,7 +1410,7 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) i2cinfo("NACK: Address invalid: dcnt=%i " "msgc=%i status=0x%08" PRIx32 "\n", priv->dcnt, priv->msgc, status); - stm32wb_i2c_traceevent(priv, I2CEVENT_ADDRESS_NACKED, + stm32_i2c_traceevent(priv, I2CEVENT_ADDRESS_NACKED, priv->msgv->addr); } else @@ -1420,7 +1420,7 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) i2cinfo("NACK: NACK received: dcnt=%i " "msgc=%i status=0x%08" PRIx32 "\n", priv->dcnt, priv->msgc, status); - stm32wb_i2c_traceevent(priv, I2CEVENT_ADDRESS_NACKED, + stm32_i2c_traceevent(priv, I2CEVENT_ADDRESS_NACKED, priv->msgv->addr); } @@ -1474,7 +1474,7 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) { /* TXIS interrupt occurred, address valid, ready to transmit */ - stm32wb_i2c_traceevent(priv, I2CEVENT_WRITE, 0); + stm32_i2c_traceevent(priv, I2CEVENT_WRITE, 0); i2cinfo("TXIS: ENTER dcnt = %i msgc = %i status 0x%08" PRIx32 "\n", priv->dcnt, priv->msgc, status); @@ -1487,7 +1487,7 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) if (priv->astart == true) { i2cinfo("TXIS: Address Valid\n"); - stm32wb_i2c_traceevent(priv, I2CEVENT_ADDRESS_ACKED, + stm32_i2c_traceevent(priv, I2CEVENT_ADDRESS_ACKED, priv->msgv->addr); priv->astart = false; } @@ -1498,7 +1498,7 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) { /* Prepare to transmit the current byte */ - stm32wb_i2c_traceevent(priv, I2CEVENT_WRITE_TO_DR, priv->dcnt); + stm32_i2c_traceevent(priv, I2CEVENT_WRITE_TO_DR, priv->dcnt); i2cinfo("TXIS: Write Data 0x%02x\n", *priv->ptr); /* Decrement byte counter */ @@ -1520,13 +1520,13 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) if (priv->msgc == 1) { - stm32wb_i2c_disable_reload(priv); + stm32_i2c_disable_reload(priv); } } /* Transmit current byte */ - stm32wb_i2c_putreg(priv, STM32_I2C_TXDR_OFFSET, *priv->ptr); + stm32_i2c_putreg(priv, STM32_I2C_TXDR_OFFSET, *priv->ptr); /* Advance to next byte */ @@ -1539,7 +1539,7 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) i2cerr("ERROR: TXIS Unsupported state detected, dcnt=%i, " "status 0x%08" PRIx32 "\n", priv->dcnt, status); - stm32wb_i2c_traceevent(priv, I2CEVENT_WRITE_ERROR, 0); + stm32_i2c_traceevent(priv, I2CEVENT_WRITE_ERROR, 0); } i2cinfo("TXIS: EXIT dcnt = %i msgc = %i status 0x%08" PRIx32 "\n", @@ -1582,7 +1582,7 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) * (RXNE is set) then the driver can read from the data register. */ - stm32wb_i2c_traceevent(priv, I2CEVENT_READ, 0); + stm32_i2c_traceevent(priv, I2CEVENT_READ, 0); i2cinfo("RXNE: ENTER dcnt = %i msgc = %i status 0x%08" PRIx32 "\n", priv->dcnt, priv->msgc, status); @@ -1590,7 +1590,7 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) if (priv->dcnt > 0) { - stm32wb_i2c_traceevent(priv, I2CEVENT_RCVBYTE, priv->dcnt); + stm32_i2c_traceevent(priv, I2CEVENT_RCVBYTE, priv->dcnt); /* No interrupts or context switches may occur in the following * sequence. Otherwise, additional bytes may be received. @@ -1601,7 +1601,7 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) #endif /* Receive a byte */ - *priv->ptr = stm32wb_i2c_getreg(priv, STM32_I2C_RXDR_OFFSET); + *priv->ptr = stm32_i2c_getreg(priv, STM32_I2C_RXDR_OFFSET); i2cinfo("RXNE: Read Data 0x%02x\n", *priv->ptr); @@ -1621,8 +1621,8 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) { /* Unsupported state */ - stm32wb_i2c_traceevent(priv, I2CEVENT_READ_ERROR, 0); - status = stm32wb_i2c_getreg(priv, STM32_I2C_ISR_OFFSET); + stm32_i2c_traceevent(priv, I2CEVENT_READ_ERROR, 0); + status = stm32_i2c_getreg(priv, STM32_I2C_ISR_OFFSET); i2cerr("ERROR: RXNE Unsupported state detected, dcnt=%i, " "status 0x%08" PRIx32 "\n", priv->dcnt, status); @@ -1688,7 +1688,7 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) { i2cinfo("TC: RESTART: dcnt=%i, msgc=%i\n", priv->dcnt, priv->msgc); - stm32wb_i2c_traceevent(priv, I2CEVENT_TC_NO_RESTART, priv->msgc); + stm32_i2c_traceevent(priv, I2CEVENT_TC_NO_RESTART, priv->msgc); /* Issue a START condition. * @@ -1702,7 +1702,7 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) priv->msgv++; - stm32wb_i2c_sendstart(priv); + stm32_i2c_sendstart(priv); } else { @@ -1715,9 +1715,9 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) i2cinfo("TC: STOP: dcnt=%i msgc=%i\n", priv->dcnt, priv->msgc); - stm32wb_i2c_traceevent(priv, I2CEVENT_STOP, priv->dcnt); + stm32_i2c_traceevent(priv, I2CEVENT_STOP, priv->dcnt); - stm32wb_i2c_sendstop(priv); + stm32_i2c_sendstop(priv); /* Set signals that will terminate ISR and wake waiting thread */ @@ -1796,7 +1796,7 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) i2cinfo("TCR: DISABLE RELOAD: dcnt = %i msgc = %i\n", priv->dcnt, priv->msgc); - stm32wb_i2c_disable_reload(priv); + stm32_i2c_disable_reload(priv); } /* Update NBYTES with length of current message */ @@ -1804,7 +1804,7 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) i2cinfo("TCR: NEXT MSG dcnt = %i msgc = %i\n", priv->dcnt, priv->msgc); - stm32wb_i2c_set_bytes_to_transfer(priv, priv->dcnt); + stm32_i2c_set_bytes_to_transfer(priv, priv->dcnt); } else { @@ -1829,9 +1829,9 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) * the transfer. */ - stm32wb_i2c_enable_reload(priv); + stm32_i2c_enable_reload(priv); - stm32wb_i2c_set_bytes_to_transfer(priv, 255); + stm32_i2c_set_bytes_to_transfer(priv, 255); } else { @@ -1848,9 +1848,9 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) i2cinfo("TCR: DISABLE RELOAD: NBYTES = dcnt = %i msgc = %i\n", priv->dcnt, priv->msgc); - stm32wb_i2c_disable_reload(priv); + stm32_i2c_disable_reload(priv); - stm32wb_i2c_set_bytes_to_transfer(priv, priv->dcnt); + stm32_i2c_set_bytes_to_transfer(priv, priv->dcnt); } i2cinfo("TCR: EXIT dcnt = %i msgc = %i status 0x%08" PRIx32 "\n", @@ -1866,10 +1866,10 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) else if (priv->dcnt == -1 && priv->msgc == 0) { - status = stm32wb_i2c_getreg(priv, STM32_I2C_ISR_OFFSET); + status = stm32_i2c_getreg(priv, STM32_I2C_ISR_OFFSET); i2cwarn("WARNING: EMPTY CALL: Stopping ISR: status 0x%08" PRIx32 "\n", status); - stm32wb_i2c_traceevent(priv, I2CEVENT_ISR_EMPTY_CALL, 0); + stm32_i2c_traceevent(priv, I2CEVENT_ISR_EMPTY_CALL, 0); } /* Error handler @@ -1885,11 +1885,11 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) else { #ifdef CONFIG_I2C_POLLED - stm32wb_i2c_traceevent(priv, I2CEVENT_POLL_DEV_NOT_RDY, 0); + stm32_i2c_traceevent(priv, I2CEVENT_POLL_DEV_NOT_RDY, 0); #else /* Read rest of the state */ - status = stm32wb_i2c_getreg(priv, STM32_I2C_ISR_OFFSET); + status = stm32_i2c_getreg(priv, STM32_I2C_ISR_OFFSET); i2cerr("ERROR: Invalid state detected, status 0x%08" PRIx32 "\n", status); @@ -1898,7 +1898,7 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) priv->dcnt = -1; priv->msgc = 0; - stm32wb_i2c_traceevent(priv, I2CEVENT_STATE_ERROR, 0); + stm32_i2c_traceevent(priv, I2CEVENT_STATE_ERROR, 0); #endif } @@ -1907,7 +1907,7 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) /* Message Handling * * Transmission of the whole message chain has been completed. We have to - * terminate the ISR and wake up stm32wb_i2c_process() that is waiting for + * terminate the ISR and wake up stm32_i2c_process() that is waiting for * the ISR cycle to handle the sending/receiving of the messages. */ @@ -1915,7 +1915,7 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) { i2cinfo("MSG: Shutting down I2C ISR\n"); - stm32wb_i2c_traceevent(priv, I2CEVENT_ISR_SHUTDOWN, 0); + stm32_i2c_traceevent(priv, I2CEVENT_ISR_SHUTDOWN, 0); /* Clear pointer to message content to reflect we are done * with the current transaction. @@ -1927,7 +1927,7 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) priv->intstate = INTSTATE_DONE; #else - status = stm32wb_i2c_getreg32(priv, STM32_I2C_ISR_OFFSET); + status = stm32_i2c_getreg32(priv, STM32_I2C_ISR_OFFSET); /* Update private state to capture NACK which is used in combination * with the astart flag to report the type of NACK received (address @@ -1941,7 +1941,7 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) /* Clear all interrupts */ - stm32wb_i2c_modifyreg32(priv, STM32_I2C_ICR_OFFSET, + stm32_i2c_modifyreg32(priv, STM32_I2C_ICR_OFFSET, 0, I2C_ICR_CLEARMASK); /* If a thread is waiting then inform it transfer is complete */ @@ -1954,14 +1954,14 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) #endif } - status = stm32wb_i2c_getreg32(priv, STM32_I2C_ISR_OFFSET); + status = stm32_i2c_getreg32(priv, STM32_I2C_ISR_OFFSET); i2cinfo("EXIT: status = 0x%08" PRIx32 "\n", status); return OK; } /**************************************************************************** - * Name: stm32wb_i2c_isr + * Name: stm32_i2c_isr * * Description: * Common I2C interrupt service routine @@ -1969,24 +1969,24 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) ****************************************************************************/ #ifndef CONFIG_I2C_POLLED -static int stm32wb_i2c_isr(int irq, void *context, void *arg) +static int stm32_i2c_isr(int irq, void *context, void *arg) { - struct stm32wb_i2c_priv_s *priv = (struct stm32wb_i2c_priv_s *)arg; + struct stm32_i2c_priv_s *priv = (struct stm32_i2c_priv_s *)arg; DEBUGASSERT(priv != NULL); - return stm32wb_i2c_isr_process(priv); + return stm32_i2c_isr_process(priv); } #endif /**************************************************************************** - * Name: stm32wb_i2c_init + * Name: stm32_i2c_init * * Description: * Setup the I2C hardware, ready for operation with defaults * ****************************************************************************/ -static int stm32wb_i2c_init(struct stm32wb_i2c_priv_s *priv) +static int stm32_i2c_init(struct stm32_i2c_priv_s *priv) { /* Power-up and configure GPIOs */ @@ -1998,22 +1998,22 @@ static int stm32wb_i2c_init(struct stm32wb_i2c_priv_s *priv) /* Configure pins */ - if (stm32wb_configgpio(priv->config->scl_pin) < 0) + if (stm32_configgpio(priv->config->scl_pin) < 0) { return ERROR; } - if (stm32wb_configgpio(priv->config->sda_pin) < 0) + if (stm32_configgpio(priv->config->sda_pin) < 0) { - stm32wb_unconfiggpio(priv->config->scl_pin); + stm32_unconfiggpio(priv->config->scl_pin); return ERROR; } #ifndef CONFIG_I2C_POLLED /* Attach error and event interrupts to the ISRs */ - irq_attach(priv->config->ev_irq, stm32wb_i2c_isr, priv); - irq_attach(priv->config->er_irq, stm32wb_i2c_isr, priv); + irq_attach(priv->config->ev_irq, stm32_i2c_isr, priv); + irq_attach(priv->config->er_irq, stm32_i2c_isr, priv); up_enable_irq(priv->config->ev_irq); up_enable_irq(priv->config->er_irq); #endif @@ -2026,33 +2026,33 @@ static int stm32wb_i2c_init(struct stm32wb_i2c_priv_s *priv) /* Force a frequency update */ priv->frequency = 0; - stm32wb_i2c_setclock(priv, 100000); + stm32_i2c_setclock(priv, 100000); /* Enable I2C peripheral */ - stm32wb_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, 0, I2C_CR1_PE); + stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, 0, I2C_CR1_PE); return OK; } /**************************************************************************** - * Name: stm32wb_i2c_deinit + * Name: stm32_i2c_deinit * * Description: * Shutdown the I2C hardware * ****************************************************************************/ -static int stm32wb_i2c_deinit(struct stm32wb_i2c_priv_s *priv) +static int stm32_i2c_deinit(struct stm32_i2c_priv_s *priv) { /* Disable I2C */ - stm32wb_i2c_putreg32(priv, STM32_I2C_CR1_OFFSET, 0); + stm32_i2c_putreg32(priv, STM32_I2C_CR1_OFFSET, 0); /* Unconfigure GPIO pins */ - stm32wb_unconfiggpio(priv->config->scl_pin); - stm32wb_unconfiggpio(priv->config->sda_pin); + stm32_unconfiggpio(priv->config->scl_pin); + stm32_unconfiggpio(priv->config->sda_pin); #ifndef CONFIG_I2C_POLLED @@ -2072,7 +2072,7 @@ static int stm32wb_i2c_deinit(struct stm32wb_i2c_priv_s *priv) } /**************************************************************************** - * Name: stm32wb_i2c_process + * Name: stm32_i2c_process * * Description: * Common I2C transfer logic @@ -2082,11 +2082,11 @@ static int stm32wb_i2c_deinit(struct stm32wb_i2c_priv_s *priv) * ****************************************************************************/ -static int stm32wb_i2c_process(struct i2c_master_s *dev, +static int stm32_i2c_process(struct i2c_master_s *dev, struct i2c_msg_s *msgs, int count) { - struct stm32wb_i2c_inst_s *inst = (struct stm32wb_i2c_inst_s *)dev; - struct stm32wb_i2c_priv_s *priv = inst->priv; + struct stm32_i2c_inst_s *inst = (struct stm32_i2c_inst_s *)dev; + struct stm32_i2c_priv_s *priv = inst->priv; uint32_t status = 0; uint32_t cr1; uint32_t cr2; @@ -2097,11 +2097,11 @@ static int stm32wb_i2c_process(struct i2c_master_s *dev, /* Wait for any STOP in progress */ - stm32wb_i2c_sem_waitstop(priv); + stm32_i2c_sem_waitstop(priv); /* Clear any pending error interrupts */ - stm32wb_i2c_clearinterrupts(priv); + stm32_i2c_clearinterrupts(priv); /* Old transfers are done */ @@ -2110,14 +2110,14 @@ static int stm32wb_i2c_process(struct i2c_master_s *dev, /* Reset I2C trace logic */ - stm32wb_i2c_tracereset(priv); + stm32_i2c_tracereset(priv); /* Set I2C clock frequency (on change it toggles I2C_CR1_PE !) */ - stm32wb_i2c_setclock(priv, msgs->frequency); + stm32_i2c_setclock(priv, msgs->frequency); /* Trigger start condition, then the process moves into the ISR. I2C - * interrupts will be enabled within stm32wb_i2c_waitdone(). + * interrupts will be enabled within stm32_i2c_waitdone(). */ priv->status = 0; @@ -2126,17 +2126,17 @@ static int stm32wb_i2c_process(struct i2c_master_s *dev, /* Enable transmit and receive interrupts here so when we send the start * condition below the ISR will fire if the data was sent and some * response from the slave received. All other interrupts relevant to - * our needs are enabled in stm32wb_i2c_sem_waitdone() below. + * our needs are enabled in stm32_i2c_sem_waitdone() below. */ - stm32wb_i2c_enableinterrupts(priv); + stm32_i2c_enableinterrupts(priv); #endif /* Trigger START condition generation, which also sends the slave address * with read/write flag and the data in the first message */ - stm32wb_i2c_sendstart(priv); + stm32_i2c_sendstart(priv); /* Wait for the ISR to tell us that the transfer is complete by attempting * to grab the semaphore that is initially locked by the ISR. If the ISR @@ -2144,10 +2144,10 @@ static int stm32wb_i2c_process(struct i2c_master_s *dev, * the timeout period waitdone returns error and we report a timeout. */ - waitrc = stm32wb_i2c_sem_waitdone(priv); + waitrc = stm32_i2c_sem_waitdone(priv); - cr1 = stm32wb_i2c_getreg32(priv, STM32_I2C_CR1_OFFSET); - cr2 = stm32wb_i2c_getreg32(priv, STM32_I2C_CR2_OFFSET); + cr1 = stm32_i2c_getreg32(priv, STM32_I2C_CR1_OFFSET); + cr2 = stm32_i2c_getreg32(priv, STM32_I2C_CR2_OFFSET); #if !defined(CONFIG_DEBUG_I2C) UNUSED(cr1); UNUSED(cr2); @@ -2161,7 +2161,7 @@ static int stm32wb_i2c_process(struct i2c_master_s *dev, * like a NACK, so we reset the status field to include that information. */ - status = stm32wb_i2c_getstatus(priv); + status = stm32_i2c_getstatus(priv); /* The priv->status field can hold additional information like a NACK * event so we include that information. @@ -2266,7 +2266,7 @@ static int stm32wb_i2c_process(struct i2c_master_s *dev, /* This is not an error, but should not happen. The BUSY signal can be * present if devices on the bus are in an odd state and need to be reset. * NOTE: - * We will only see this busy indication if stm32wb_i2c_sem_waitdone() + * We will only see this busy indication if stm32_i2c_sem_waitdone() * fails above; Otherwise it is cleared. */ @@ -2276,7 +2276,7 @@ static int stm32wb_i2c_process(struct i2c_master_s *dev, * * This is a status condition rather than an error. * - * We will only see this busy indication if stm32wb_i2c_sem_waitdone() + * We will only see this busy indication if stm32_i2c_sem_waitdone() * fails above; Otherwise it is cleared by the hardware when the ISR * wraps up the transfer with a STOP condition. */ @@ -2284,7 +2284,7 @@ static int stm32wb_i2c_process(struct i2c_master_s *dev, clock_t start = clock_systime_ticks(); clock_t timeout = USEC2TICK(USEC_PER_SEC / priv->frequency) + 1; - status = stm32wb_i2c_getstatus(priv); + status = stm32_i2c_getstatus(priv); while (status & I2C_ISR_BUSY) { @@ -2295,27 +2295,27 @@ static int stm32wb_i2c_process(struct i2c_master_s *dev, break; } - status = stm32wb_i2c_getstatus(priv); + status = stm32_i2c_getstatus(priv); } } /* Dump the trace result */ - stm32wb_i2c_tracedump(priv); + stm32_i2c_tracedump(priv); nxmutex_unlock(&priv->lock); return -errval; } /**************************************************************************** - * Name: stm32wb_i2c_transfer + * Name: stm32_i2c_transfer * * Description: * Generic I2C transfer function * ****************************************************************************/ -static int stm32wb_i2c_transfer(struct i2c_master_s *dev, +static int stm32_i2c_transfer(struct i2c_master_s *dev, struct i2c_msg_s *msgs, int count) { @@ -2323,17 +2323,17 @@ static int stm32wb_i2c_transfer(struct i2c_master_s *dev, /* Ensure that address or flags don't change meanwhile */ - ret = nxmutex_lock(&((struct stm32wb_i2c_inst_s *)dev)->priv->lock); + ret = nxmutex_lock(&((struct stm32_i2c_inst_s *)dev)->priv->lock); if (ret >= 0) { - ret = stm32wb_i2c_process(dev, msgs, count); + ret = stm32_i2c_process(dev, msgs, count); } return ret; } /**************************************************************************** - * Name: stm32wb_i2c_reset + * Name: stm32_i2c_reset * * Description: * Reset an I2C bus @@ -2341,9 +2341,9 @@ static int stm32wb_i2c_transfer(struct i2c_master_s *dev, ****************************************************************************/ #ifdef CONFIG_I2C_RESET -static int stm32wb_i2c_reset(struct i2c_master_s * dev) +static int stm32_i2c_reset(struct i2c_master_s * dev) { - struct stm32wb_i2c_priv_s *priv; + struct stm32_i2c_priv_s *priv; unsigned int clock_count; unsigned int stretch_count; uint32_t scl_gpio; @@ -2355,7 +2355,7 @@ static int stm32wb_i2c_reset(struct i2c_master_s * dev) /* Get I2C private structure */ - priv = ((struct stm32wb_i2c_inst_s *)dev)->priv; + priv = ((struct stm32_i2c_inst_s *)dev)->priv; /* Our caller must own a ref */ @@ -2377,24 +2377,24 @@ static int stm32wb_i2c_reset(struct i2c_master_s * dev) /* De-init the port */ - stm32wb_i2c_deinit(priv); + stm32_i2c_deinit(priv); /* Use GPIO configuration to un-wedge the bus */ scl_gpio = MKI2C_OUTPUT(priv->config->scl_pin); sda_gpio = MKI2C_OUTPUT(priv->config->sda_pin); - stm32wb_configgpio(sda_gpio); - stm32wb_configgpio(scl_gpio); + stm32_configgpio(sda_gpio); + stm32_configgpio(scl_gpio); /* Let SDA go high */ - stm32wb_gpiowrite(sda_gpio, 1); + stm32_gpiowrite(sda_gpio, 1); /* Clock the bus until any slaves currently driving it let it go. */ clock_count = 0; - while (!stm32wb_gpioread(sda_gpio)) + while (!stm32_gpioread(sda_gpio)) { /* Give up if we have tried too hard */ @@ -2409,7 +2409,7 @@ static int stm32wb_i2c_reset(struct i2c_master_s * dev) */ stretch_count = 0; - while (!stm32wb_gpioread(scl_gpio)) + while (!stm32_gpioread(scl_gpio)) { /* Give up if we have tried too hard */ @@ -2423,12 +2423,12 @@ static int stm32wb_i2c_reset(struct i2c_master_s * dev) /* Drive SCL low */ - stm32wb_gpiowrite(scl_gpio, 0); + stm32_gpiowrite(scl_gpio, 0); up_udelay(10); /* Drive SCL high again */ - stm32wb_gpiowrite(scl_gpio, 1); + stm32_gpiowrite(scl_gpio, 1); up_udelay(10); } @@ -2436,27 +2436,27 @@ static int stm32wb_i2c_reset(struct i2c_master_s * dev) * state machines. */ - stm32wb_gpiowrite(sda_gpio, 0); + stm32_gpiowrite(sda_gpio, 0); up_udelay(10); - stm32wb_gpiowrite(scl_gpio, 0); + stm32_gpiowrite(scl_gpio, 0); up_udelay(10); - stm32wb_gpiowrite(scl_gpio, 1); + stm32_gpiowrite(scl_gpio, 1); up_udelay(10); - stm32wb_gpiowrite(sda_gpio, 1); + stm32_gpiowrite(sda_gpio, 1); up_udelay(10); /* Revert the GPIO configuration. */ - stm32wb_unconfiggpio(sda_gpio); - stm32wb_unconfiggpio(scl_gpio); + stm32_unconfiggpio(sda_gpio); + stm32_unconfiggpio(scl_gpio); /* Re-init the port */ - stm32wb_i2c_init(priv); + stm32_i2c_init(priv); /* Restore the frequency */ - stm32wb_i2c_setclock(priv, frequency); + stm32_i2c_setclock(priv, frequency); ret = OK; out: @@ -2469,7 +2469,7 @@ out: #endif /* CONFIG_I2C_RESET */ /**************************************************************************** - * Name: stm32wb_i2c_pm_prepare + * Name: stm32_i2c_pm_prepare * * Description: * Request the driver to prepare for a new power state. This is a @@ -2498,12 +2498,12 @@ out: ****************************************************************************/ #ifdef CONFIG_PM -static int stm32wb_i2c_pm_prepare(struct pm_callback_s *cb, int domain, +static int stm32_i2c_pm_prepare(struct pm_callback_s *cb, int domain, enum pm_state_e pmstate) { - struct stm32wb_i2c_priv_s *priv = - (struct stm32wb_i2c_priv_s *)((char *)cb - - offsetof(struct stm32wb_i2c_priv_s, pm_cb)); + struct stm32_i2c_priv_s *priv = + (struct stm32_i2c_priv_s *)((char *)cb - + offsetof(struct stm32_i2c_priv_s, pm_cb)); /* Logic to prepare for a reduced power state goes here. */ @@ -2545,17 +2545,17 @@ static int stm32wb_i2c_pm_prepare(struct pm_callback_s *cb, int domain, ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_i2cbus_initialize + * Name: stm32_i2cbus_initialize * * Description: * Initialize one I2C bus * ****************************************************************************/ -struct i2c_master_s *stm32wb_i2cbus_initialize(int port) +struct i2c_master_s *stm32_i2cbus_initialize(int port) { - struct stm32wb_i2c_priv_s *priv = NULL; /* private data of device with multiple instances */ - struct stm32wb_i2c_inst_s *inst = NULL; /* device, single instance */ + struct stm32_i2c_priv_s *priv = NULL; /* private data of device with multiple instances */ + struct stm32_i2c_inst_s *inst = NULL; /* device, single instance */ /* Get I2C private structure */ @@ -2563,12 +2563,12 @@ struct i2c_master_s *stm32wb_i2cbus_initialize(int port) { #ifdef CONFIG_STM32WB_I2C1 case 1: - priv = (struct stm32wb_i2c_priv_s *)&stm32wb_i2c1_priv; + priv = (struct stm32_i2c_priv_s *)&stm32_i2c1_priv; break; #endif #ifdef CONFIG_STM32WB_I2C3 case 3: - priv = (struct stm32wb_i2c_priv_s *)&stm32wb_i2c3_priv; + priv = (struct stm32_i2c_priv_s *)&stm32_i2c3_priv; break; #endif default: @@ -2577,14 +2577,14 @@ struct i2c_master_s *stm32wb_i2cbus_initialize(int port) /* Allocate instance */ - if (!(inst = kmm_malloc(sizeof(struct stm32wb_i2c_inst_s)))) + if (!(inst = kmm_malloc(sizeof(struct stm32_i2c_inst_s)))) { return NULL; } /* Initialize instance */ - inst->ops = &stm32wb_i2c_ops; + inst->ops = &stm32_i2c_ops; inst->priv = priv; /* Init private data for the first time, increment refs count, @@ -2594,7 +2594,7 @@ struct i2c_master_s *stm32wb_i2cbus_initialize(int port) nxmutex_lock(&priv->lock); if (priv->refs++ == 0) { - stm32wb_i2c_init(priv); + stm32_i2c_init(priv); #ifdef CONFIG_PM /* Register to receive power management callbacks */ @@ -2608,19 +2608,19 @@ struct i2c_master_s *stm32wb_i2cbus_initialize(int port) } /**************************************************************************** - * Name: stm32wb_i2cbus_uninitialize + * Name: stm32_i2cbus_uninitialize * * Description: * Uninitialize an I2C bus * ****************************************************************************/ -int stm32wb_i2cbus_uninitialize(struct i2c_master_s *dev) +int stm32_i2cbus_uninitialize(struct i2c_master_s *dev) { - struct stm32wb_i2c_priv_s *priv; + struct stm32_i2c_priv_s *priv; DEBUGASSERT(dev); - priv = ((struct stm32wb_i2c_inst_s *)dev)->priv; + priv = ((struct stm32_i2c_inst_s *)dev)->priv; /* Decrement refs and check for underflow */ @@ -2645,7 +2645,7 @@ int stm32wb_i2cbus_uninitialize(struct i2c_master_s *dev) /* Disable power and other HW resource (GPIO's) */ - stm32wb_i2c_deinit(priv); + stm32_i2c_deinit(priv); nxmutex_unlock(&priv->lock); kmm_free(dev); diff --git a/arch/arm/src/stm32wb/stm32wb_i2c.h b/arch/arm/src/stm32wb/stm32wb_i2c.h index 3c9ea624557..adb5a001e6e 100644 --- a/arch/arm/src/stm32wb/stm32wb_i2c.h +++ b/arch/arm/src/stm32wb/stm32wb_i2c.h @@ -53,7 +53,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_i2cbus_initialize + * Name: stm32_i2cbus_initialize * * Description: * Initialize the selected I2C port. And return a unique instance of struct @@ -69,16 +69,16 @@ * ****************************************************************************/ -struct i2c_master_s *stm32wb_i2cbus_initialize(int port); +struct i2c_master_s *stm32_i2cbus_initialize(int port); /**************************************************************************** - * Name: stm32wb_i2cbus_uninitialize + * Name: stm32_i2cbus_uninitialize * * Description: * De-initialize the selected I2C port, and power down the device. * * Input Parameters: - * Device structure as returned by the stm32wb_i2cbus_initialize() + * Device structure as returned by the stm32_i2cbus_initialize() * * Returned Value: * OK on success, ERROR when internal reference count mismatch or dev @@ -86,6 +86,6 @@ struct i2c_master_s *stm32wb_i2cbus_initialize(int port); * ****************************************************************************/ -int stm32wb_i2cbus_uninitialize(struct i2c_master_s *dev); +int stm32_i2cbus_uninitialize(struct i2c_master_s *dev); #endif /* __ARCH_ARM_SRC_STM32WB_STM32WB_I2C_H */ diff --git a/arch/arm/src/stm32wb/stm32wb_idle.c b/arch/arm/src/stm32wb/stm32wb_idle.c index 977ff297093..0a0e6d1ad06 100644 --- a/arch/arm/src/stm32wb/stm32wb_idle.c +++ b/arch/arm/src/stm32wb/stm32wb_idle.c @@ -119,12 +119,12 @@ static void up_idlepm(void) /* Enter STOP mode */ BEGIN_IDLE(); - stm32wb_pmstop(true); + stm32_pmstop(true); END_IDLE(); /* Set correct clock again after returning from STOP */ - stm32wb_clockenable(); + stm32_clockenable(); /* Inform of all drivers of the new state */ @@ -137,7 +137,7 @@ static void up_idlepm(void) break; case PM_SLEEP: - stm32wb_pmstandby(); + stm32_pmstandby(); break; default: diff --git a/arch/arm/src/stm32wb/stm32wb_ipcc.c b/arch/arm/src/stm32wb/stm32wb_ipcc.c index 795ec398c46..c9b889aec9a 100644 --- a/arch/arm/src/stm32wb/stm32wb_ipcc.c +++ b/arch/arm/src/stm32wb/stm32wb_ipcc.c @@ -40,14 +40,14 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_ipccreset + * Name: stm32_ipccreset * * Description: * Reset the IPCC registers to default state * ****************************************************************************/ -void stm32wb_ipccreset(void) +void stm32_ipccreset(void) { uint32_t regval; @@ -77,14 +77,14 @@ void stm32wb_ipccreset(void) } /**************************************************************************** - * Name: stm32wb_ipccenable + * Name: stm32_ipccenable * * Description: * Enable the IPCC and start CPU2 * ****************************************************************************/ -void stm32wb_ipccenable(void) +void stm32_ipccenable(void) { uint32_t regval; diff --git a/arch/arm/src/stm32wb/stm32wb_ipcc.h b/arch/arm/src/stm32wb/stm32wb_ipcc.h index b130c899662..679c4cd6728 100644 --- a/arch/arm/src/stm32wb/stm32wb_ipcc.h +++ b/arch/arm/src/stm32wb/stm32wb_ipcc.h @@ -55,77 +55,77 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_ipccreset + * Name: stm32_ipccreset * * Description: * Reset the IPCC registers to default state * ****************************************************************************/ -void stm32wb_ipccreset(void); +void stm32_ipccreset(void); /**************************************************************************** - * Name: stm32wb_ipccenable + * Name: stm32_ipccenable * * Description: * Enable the IPCC and start CPU2 * ****************************************************************************/ -void stm32wb_ipccenable(void); +void stm32_ipccenable(void); /**************************************************************************** * Inline Functions ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_ipcc_rxactive + * Name: stm32_ipcc_rxactive * * Description: * Check channel receive active flag. * ****************************************************************************/ -static inline bool stm32wb_ipcc_rxactive(uint8_t chan) +static inline bool stm32_ipcc_rxactive(uint8_t chan) { return (getreg32(STM32_IPCC_C2TOC1SR) & IPCC_C2TOC1SR_BIT(chan)) != 0; } /**************************************************************************** - * Name: stm32wb_ipcc_txactive + * Name: stm32_ipcc_txactive * * Description: * Check channel transmit active flag. * ****************************************************************************/ -static inline bool stm32wb_ipcc_txactive(uint8_t chan) +static inline bool stm32_ipcc_txactive(uint8_t chan) { return (getreg32(STM32_IPCC_C1TOC2SR) & IPCC_C1TOC2SR_BIT(chan)) != 0; } /**************************************************************************** - * Name: stm32wb_ipcc_settxactive + * Name: stm32_ipcc_settxactive * * Description: * Set channel transmit active flag. * ****************************************************************************/ -static inline void stm32wb_ipcc_settxactive(uint8_t chan) +static inline void stm32_ipcc_settxactive(uint8_t chan) { putreg32(IPCC_C1SCR_SET_BIT(chan), STM32_IPCC_C1SCR); } /**************************************************************************** - * Name: stm32wb_ipcc_masktxf + * Name: stm32_ipcc_masktxf * * Description: * Mask channel transmit free interrupt. * ****************************************************************************/ -static inline void stm32wb_ipcc_masktxf(uint8_t chan) +static inline void stm32_ipcc_masktxf(uint8_t chan) { uint32_t regval = getreg32(STM32_IPCC_C1MR); regval |= IPCC_C1MR_FM_BIT(chan); @@ -133,14 +133,14 @@ static inline void stm32wb_ipcc_masktxf(uint8_t chan) } /**************************************************************************** - * Name: stm32wb_ipcc_unmasktxf + * Name: stm32_ipcc_unmasktxf * * Description: * Unmask channel transmit free interrupt. * ****************************************************************************/ -static inline void stm32wb_ipcc_unmasktxf(uint8_t chan) +static inline void stm32_ipcc_unmasktxf(uint8_t chan) { uint32_t regval = getreg32(STM32_IPCC_C1MR); regval &= ~IPCC_C1MR_FM_BIT(chan); @@ -148,14 +148,14 @@ static inline void stm32wb_ipcc_unmasktxf(uint8_t chan) } /**************************************************************************** - * Name: stm32wb_ipcc_maskrxo + * Name: stm32_ipcc_maskrxo * * Description: * Mask channel receive occupied interrupt. * ****************************************************************************/ -static inline void stm32wb_ipcc_maskrxo(uint8_t chan) +static inline void stm32_ipcc_maskrxo(uint8_t chan) { uint32_t regval = getreg32(STM32_IPCC_C1MR); regval |= IPCC_C1MR_OM_BIT(chan); @@ -163,14 +163,14 @@ static inline void stm32wb_ipcc_maskrxo(uint8_t chan) } /**************************************************************************** - * Name: stm32wb_ipcc_maskrxo + * Name: stm32_ipcc_maskrxo * * Description: * Unmask channel receive occupied interrupt. * ****************************************************************************/ -static inline void stm32wb_ipcc_unmaskrxo(uint8_t chan) +static inline void stm32_ipcc_unmaskrxo(uint8_t chan) { uint32_t regval = getreg32(STM32_IPCC_C1MR); regval &= ~IPCC_C1MR_OM_BIT(chan); diff --git a/arch/arm/src/stm32wb/stm32wb_irq.c b/arch/arm/src/stm32wb/stm32wb_irq.c index f87503a7802..d03886cee30 100644 --- a/arch/arm/src/stm32wb/stm32wb_irq.c +++ b/arch/arm/src/stm32wb/stm32wb_irq.c @@ -65,7 +65,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_dumpnvic + * Name: stm32_dumpnvic * * Description: * Dump some interesting NVIC registers @@ -73,7 +73,7 @@ ****************************************************************************/ #if defined(CONFIG_DEBUG_IRQ_INFO) -static void stm32wb_dumpnvic(const char *msg, int irq) +static void stm32_dumpnvic(const char *msg, int irq) { irqstate_t flags; @@ -129,11 +129,11 @@ static void stm32wb_dumpnvic(const char *msg, int irq) leave_critical_section(flags); } #else -# define stm32wb_dumpnvic(msg, irq) +# define stm32_dumpnvic(msg, irq) #endif /**************************************************************************** - * Name: stm32wb_nmi, stm32wb_pendsv,stm32wb_pendsv, stm32wb_reserved + * Name: stm32_nmi, stm32_pendsv,stm32_pendsv, stm32_reserved * * Description: * Handlers for various exceptions. None are handled and all are fatal @@ -143,7 +143,7 @@ static void stm32wb_dumpnvic(const char *msg, int irq) ****************************************************************************/ #ifdef CONFIG_DEBUG_FEATURES -static int stm32wb_nmi(int irq, void *context, void *arg) +static int stm32_nmi(int irq, void *context, void *arg) { up_irq_save(); _err("PANIC!!! NMI received\n"); @@ -151,7 +151,7 @@ static int stm32wb_nmi(int irq, void *context, void *arg) return 0; } -static int stm32wb_pendsv(int irq, void *context, void *arg) +static int stm32_pendsv(int irq, void *context, void *arg) { up_irq_save(); _err("PANIC!!! PendSV received\n"); @@ -159,7 +159,7 @@ static int stm32wb_pendsv(int irq, void *context, void *arg) return 0; } -static int stm32wb_reserved(int irq, void *context, void *arg) +static int stm32_reserved(int irq, void *context, void *arg) { up_irq_save(); _err("PANIC!!! Reserved interrupt\n"); @@ -169,7 +169,7 @@ static int stm32wb_reserved(int irq, void *context, void *arg) #endif /**************************************************************************** - * Name: stm32wb_prioritize_syscall + * Name: stm32_prioritize_syscall * * Description: * Set the priority of an exception. This function may be needed @@ -177,7 +177,7 @@ static int stm32wb_reserved(int irq, void *context, void *arg) * ****************************************************************************/ -static inline void stm32wb_prioritize_syscall(int priority) +static inline void stm32_prioritize_syscall(int priority) { uint32_t regval; @@ -190,7 +190,7 @@ static inline void stm32wb_prioritize_syscall(int priority) } /**************************************************************************** - * Name: stm32wb_irqinfo + * Name: stm32_irqinfo * * Description: * Given an IRQ number, provide the register and bit setting to enable or @@ -198,7 +198,7 @@ static inline void stm32wb_prioritize_syscall(int priority) * ****************************************************************************/ -static int stm32wb_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit, +static int stm32_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit, uintptr_t offset) { int n; @@ -328,7 +328,7 @@ void up_irqinitialize(void) /* up_prioritize_irq(STM32_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */ #endif - stm32wb_prioritize_syscall(NVIC_SYSH_SVCALL_PRIORITY); + stm32_prioritize_syscall(NVIC_SYSH_SVCALL_PRIORITY); /* If the MPU is enabled, then attach and enable the Memory Management * Fault handler. @@ -342,19 +342,19 @@ void up_irqinitialize(void) /* Attach all other processor exceptions (except reset and sys tick) */ #ifdef CONFIG_DEBUG_FEATURES - irq_attach(STM32_IRQ_NMI, stm32wb_nmi, NULL); + irq_attach(STM32_IRQ_NMI, stm32_nmi, NULL); #ifndef CONFIG_ARM_MPU irq_attach(STM32_IRQ_MEMFAULT, arm_memfault, NULL); #endif irq_attach(STM32_IRQ_BUSFAULT, arm_busfault, NULL); irq_attach(STM32_IRQ_USAGEFAULT, arm_usagefault, NULL); - irq_attach(STM32_IRQ_PENDSV, stm32wb_pendsv, NULL); + irq_attach(STM32_IRQ_PENDSV, stm32_pendsv, NULL); arm_enable_dbgmonitor(); irq_attach(STM32_IRQ_DBGMONITOR, arm_dbgmonitor, NULL); - irq_attach(STM32_IRQ_RESERVED, stm32wb_reserved, NULL); + irq_attach(STM32_IRQ_RESERVED, stm32_reserved, NULL); #endif - stm32wb_dumpnvic("initial", NR_IRQS); + stm32_dumpnvic("initial", NR_IRQS); #ifndef CONFIG_SUPPRESS_INTERRUPTS @@ -379,7 +379,7 @@ void up_disable_irq(int irq) uint32_t regval; uint32_t bit; - if (stm32wb_irqinfo(irq, ®addr, &bit, NVIC_CLRENA_OFFSET) == 0) + if (stm32_irqinfo(irq, ®addr, &bit, NVIC_CLRENA_OFFSET) == 0) { /* Modify the appropriate bit in the register to disable the interrupt. * For normal interrupts, we need to set the bit in the associated @@ -414,7 +414,7 @@ void up_enable_irq(int irq) uint32_t regval; uint32_t bit; - if (stm32wb_irqinfo(irq, ®addr, &bit, NVIC_ENA_OFFSET) == 0) + if (stm32_irqinfo(irq, ®addr, &bit, NVIC_ENA_OFFSET) == 0) { /* Modify the appropriate bit in the register to enable the interrupt. * For normal interrupts, we need to set the bit in the associated @@ -491,7 +491,7 @@ int up_prioritize_irq(int irq, int priority) regval |= (priority << shift); putreg32(regval, regaddr); - stm32wb_dumpnvic("prioritize", irq); + stm32_dumpnvic("prioritize", irq); return OK; } #endif diff --git a/arch/arm/src/stm32wb/stm32wb_lowputc.c b/arch/arm/src/stm32wb/stm32wb_lowputc.c index c8807a1f5bf..9175c37cffd 100644 --- a/arch/arm/src/stm32wb/stm32wb_lowputc.c +++ b/arch/arm/src/stm32wb/stm32wb_lowputc.c @@ -32,7 +32,7 @@ #include "arm_internal.h" #include "chip.h" -#include "stm32wb.h" +#include "stm32.h" #include "stm32wb_rcc.h" #include "stm32wb_gpio.h" #include "stm32wb_uart.h" @@ -214,7 +214,7 @@ void arm_lowputc(char ch) while ((getreg32(STM32_CONSOLE_BASE + STM32_USART_ISR_OFFSET) & USART_ISR_TXE) == 0); #ifdef STM32_CONSOLE_RS485_DIR - stm32wb_gpiowrite(STM32_CONSOLE_RS485_DIR, + stm32_gpiowrite(STM32_CONSOLE_RS485_DIR, STM32_CONSOLE_RS485_DIR_POLARITY); #endif @@ -225,7 +225,7 @@ void arm_lowputc(char ch) #ifdef STM32_CONSOLE_RS485_DIR while ((getreg32(STM32_CONSOLE_BASE + STM32_USART_ISR_OFFSET) & USART_ISR_TC) == 0); - stm32wb_gpiowrite(STM32_CONSOLE_RS485_DIR, + stm32_gpiowrite(STM32_CONSOLE_RS485_DIR, !STM32_CONSOLE_RS485_DIR_POLARITY); #endif @@ -233,7 +233,7 @@ void arm_lowputc(char ch) } /**************************************************************************** - * Name: stm32wb_lowsetup + * Name: stm32_lowsetup * * Description: * This performs basic initialization of the USART used for the serial @@ -242,7 +242,7 @@ void arm_lowputc(char ch) * ****************************************************************************/ -void stm32wb_lowsetup(void) +void stm32_lowsetup(void) { #if defined(HAVE_UART) #if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG) @@ -258,19 +258,19 @@ void stm32wb_lowsetup(void) /* Enable the console USART and configure GPIO pins needed for rx/tx. * * NOTE: Clocking for selected U[S]ARTs was already provided in - * stm32wb_rcc.c + * stm32_rcc.c */ #ifdef STM32_CONSOLE_TX - stm32wb_configgpio(STM32_CONSOLE_TX); + stm32_configgpio(STM32_CONSOLE_TX); #endif #ifdef STM32_CONSOLE_RX - stm32wb_configgpio(STM32_CONSOLE_RX); + stm32_configgpio(STM32_CONSOLE_RX); #endif #ifdef STM32_CONSOLE_RS485_DIR - stm32wb_configgpio(STM32_CONSOLE_RS485_DIR); - stm32wb_gpiowrite(STM32_CONSOLE_RS485_DIR, + stm32_configgpio(STM32_CONSOLE_RS485_DIR); + stm32_gpiowrite(STM32_CONSOLE_RS485_DIR, !STM32_CONSOLE_RS485_DIR_POLARITY); #endif diff --git a/arch/arm/src/stm32wb/stm32wb_lowputc.h b/arch/arm/src/stm32wb/stm32wb_lowputc.h index 8a8ca85b338..bd55c77c74f 100644 --- a/arch/arm/src/stm32wb/stm32wb_lowputc.h +++ b/arch/arm/src/stm32wb/stm32wb_lowputc.h @@ -47,7 +47,7 @@ extern "C" #endif /**************************************************************************** - * Name: stm32wb_lowsetup + * Name: stm32_lowsetup * * Description: * Called at the very beginning of _start. @@ -55,7 +55,7 @@ extern "C" * ****************************************************************************/ -void stm32wb_lowsetup(void); +void stm32_lowsetup(void); #undef EXTERN #if defined(__cplusplus) diff --git a/arch/arm/src/stm32wb/stm32wb_mbox.c b/arch/arm/src/stm32wb/stm32wb_mbox.c index 232e03af6f7..f92be7547f5 100644 --- a/arch/arm/src/stm32wb/stm32wb_mbox.c +++ b/arch/arm/src/stm32wb/stm32wb_mbox.c @@ -48,14 +48,14 @@ /* Mailbox shared buffer fields */ -#define stm32wb_mbox_shared \ - (*(struct stm32wb_mbox_shared_buffer_s *)STM32_MBOX_SHARED_BASE) +#define stm32_mbox_shared \ + (*(struct stm32_mbox_shared_buffer_s *)STM32_MBOX_SHARED_BASE) -#define stm32wb_mbox_ref_table (stm32wb_mbox_shared.ref_table) -#define stm32wb_mbox_di_table (stm32wb_mbox_shared.dev_info_table) -#define stm32wb_mbox_sys_table (stm32wb_mbox_shared.sys_table) -#define stm32wb_mbox_mm_table (stm32wb_mbox_shared.mm_table) -#define stm32wb_mbox_ble_table (stm32wb_mbox_shared.ble_table) +#define stm32_mbox_ref_table (stm32_mbox_shared.ref_table) +#define stm32_mbox_di_table (stm32_mbox_shared.dev_info_table) +#define stm32_mbox_sys_table (stm32_mbox_shared.sys_table) +#define stm32_mbox_mm_table (stm32_mbox_shared.mm_table) +#define stm32_mbox_ble_table (stm32_mbox_shared.ble_table) /* Mailbox buffer sizes */ @@ -72,19 +72,19 @@ /* Mailbox shared buffer structures */ -begin_packed_struct struct stm32wb_mbox_safe_boot_info_table_s +begin_packed_struct struct stm32_mbox_safe_boot_info_table_s { uint32_t version; } end_packed_struct; -begin_packed_struct struct stm32wb_mbox_fus_info_table_s +begin_packed_struct struct stm32_mbox_fus_info_table_s { uint32_t version; uint32_t memory_size; uint32_t fus_info; } end_packed_struct; -begin_packed_struct struct stm32wb_mbox_wireless_fw_info_table_s +begin_packed_struct struct stm32_mbox_wireless_fw_info_table_s { uint32_t version; uint32_t memory_size; @@ -92,14 +92,14 @@ begin_packed_struct struct stm32wb_mbox_wireless_fw_info_table_s uint32_t reserved; } end_packed_struct; -begin_packed_struct struct stm32wb_mbox_device_info_table_s +begin_packed_struct struct stm32_mbox_device_info_table_s { - struct stm32wb_mbox_safe_boot_info_table_s safe_boot_info_table; - struct stm32wb_mbox_fus_info_table_s fus_info_table; - struct stm32wb_mbox_wireless_fw_info_table_s wireless_fw_info_table; + struct stm32_mbox_safe_boot_info_table_s safe_boot_info_table; + struct stm32_mbox_fus_info_table_s fus_info_table; + struct stm32_mbox_wireless_fw_info_table_s wireless_fw_info_table; } end_packed_struct; -begin_packed_struct struct stm32wb_mbox_ble_table_s +begin_packed_struct struct stm32_mbox_ble_table_s { void *cmd_buffer; void *cs_buffer; @@ -107,13 +107,13 @@ begin_packed_struct struct stm32wb_mbox_ble_table_s void *acl_buffer; } end_packed_struct; -begin_packed_struct struct stm32wb_mbox_sys_table_s +begin_packed_struct struct stm32_mbox_sys_table_s { void *cmd_buffer; void *evt_queue; } end_packed_struct; -begin_packed_struct struct stm32wb_mbox_mem_manager_table_s +begin_packed_struct struct stm32_mbox_mem_manager_table_s { void *ble_spare_buffer; void *sys_spare_buffer; @@ -124,13 +124,13 @@ begin_packed_struct struct stm32wb_mbox_mem_manager_table_s uint32_t traces_evtpool_size; } end_packed_struct; -begin_packed_struct struct stm32wb_mbox_ref_table_s +begin_packed_struct struct stm32_mbox_ref_table_s { - struct stm32wb_mbox_device_info_table_s *dev_info_table; - struct stm32wb_mbox_ble_table_s *ble_table; + struct stm32_mbox_device_info_table_s *dev_info_table; + struct stm32_mbox_ble_table_s *ble_table; void *thread_table; - struct stm32wb_mbox_sys_table_s *sys_table; - struct stm32wb_mbox_mem_manager_table_s *mm_table; + struct stm32_mbox_sys_table_s *sys_table; + struct stm32_mbox_mem_manager_table_s *mm_table; void *traces_table; void *mac_802_15_4_table; void *zigbee_table; @@ -140,20 +140,20 @@ begin_packed_struct struct stm32wb_mbox_ref_table_s /* Mailbox shared buffer memory layout structure */ -struct stm32wb_mbox_shared_buffer_s +struct stm32_mbox_shared_buffer_s { - aligned_data(4) struct stm32wb_mbox_ref_table_s ref_table; + aligned_data(4) struct stm32_mbox_ref_table_s ref_table; - aligned_data(4) struct stm32wb_mbox_device_info_table_s dev_info_table; - aligned_data(4) struct stm32wb_mbox_ble_table_s ble_table; - aligned_data(4) struct stm32wb_mbox_sys_table_s sys_table; - aligned_data(4) struct stm32wb_mbox_mem_manager_table_s mm_table; + aligned_data(4) struct stm32_mbox_device_info_table_s dev_info_table; + aligned_data(4) struct stm32_mbox_ble_table_s ble_table; + aligned_data(4) struct stm32_mbox_sys_table_s sys_table; + aligned_data(4) struct stm32_mbox_mem_manager_table_s mm_table; - aligned_data(4) stm32wb_mbox_list_t evtfree_buffer; + aligned_data(4) stm32_mbox_list_t evtfree_buffer; #ifdef CONFIG_STM32WB_BLE - aligned_data(4) stm32wb_mbox_list_t ble_evt_queue; + aligned_data(4) stm32_mbox_list_t ble_evt_queue; #endif - aligned_data(4) stm32wb_mbox_list_t sys_evt_queue; + aligned_data(4) stm32_mbox_list_t sys_evt_queue; #ifdef CONFIG_STM32WB_BLE aligned_data(4) uint8_t ble_cs_buffer[STM32_MBOX_CS_BUF_SIZE]; @@ -170,11 +170,11 @@ struct stm32wb_mbox_shared_buffer_s /* Mailbox channel data type */ -struct stm32wb_mbox_channel_s +struct stm32_mbox_channel_s { uint8_t ch_num; - stm32wb_mbox_list_t cmd_buf_queue; - struct stm32wb_mbox_cmd_s *cmd_buf; + stm32_mbox_list_t cmd_buf_queue; + struct stm32_mbox_cmd_s *cmd_buf; bool ack_ready; }; @@ -182,18 +182,18 @@ struct stm32wb_mbox_channel_s * Private Function prototypes ****************************************************************************/ -static void stm32wb_ipcc_rxoisr(int irq, uint32_t *regs, void *arg); -static void stm32wb_ipcc_txfisr(int irq, uint32_t *regs, void *arg); +static void stm32_ipcc_rxoisr(int irq, uint32_t *regs, void *arg); +static void stm32_ipcc_txfisr(int irq, uint32_t *regs, void *arg); -static void stm32wb_mbox_rxworker(void *arg); -static void stm32wb_mbox_txworker(void *arg); +static void stm32_mbox_rxworker(void *arg); +static void stm32_mbox_txworker(void *arg); -static void stm32wb_mbox_eventfree(stm32wb_mbox_list_t *evt); -static void stm32wb_mbox_acksyscmd(void); +static void stm32_mbox_eventfree(stm32_mbox_list_t *evt); +static void stm32_mbox_acksyscmd(void); -static int stm32wb_mbox_txdata(struct stm32wb_mbox_channel_s *chan, +static int stm32_mbox_txdata(struct stm32_mbox_channel_s *chan, uint8_t type, void *data, size_t len); -static bool stm32wb_mbox_txnext(struct stm32wb_mbox_channel_s *chan); +static bool stm32_mbox_txnext(struct stm32_mbox_channel_s *chan); /**************************************************************************** * Private Data @@ -202,26 +202,26 @@ static bool stm32wb_mbox_txnext(struct stm32wb_mbox_channel_s *chan); static struct work_s g_rx_evt_work; static struct work_s g_tx_cmd_work; -static stm32wb_mbox_list_t g_rx_evt_queue; -static stm32wb_mbox_list_t g_tx_evtfree_queue; +static stm32_mbox_list_t g_rx_evt_queue; +static stm32_mbox_list_t g_tx_evtfree_queue; static uint8_t g_free_buffers[CONFIG_STM32WB_MBOX_TX_CMD_QUEUE_LEN] [STM32_MBOX_CMDPKT_BUF_SIZE]; -static stm32wb_mbox_list_t g_free_buffers_pool; +static stm32_mbox_list_t g_free_buffers_pool; -static struct stm32wb_mbox_channel_s g_syscmd_channel; +static struct stm32_mbox_channel_s g_syscmd_channel; #ifdef CONFIG_STM32WB_BLE -static struct stm32wb_mbox_channel_s g_blecmd_channel; -static struct stm32wb_mbox_channel_s g_bleacl_channel; +static struct stm32_mbox_channel_s g_blecmd_channel; +static struct stm32_mbox_channel_s g_bleacl_channel; #endif -static stm32wb_mbox_evt_handler_t receive_evt_handler; +static stm32_mbox_evt_handler_t receive_evt_handler; /**************************************************************************** * Private Functions ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_ipcc_rxoisr + * Name: stm32_ipcc_rxoisr * * Description: * RX channel occupied interrupt handler (communication data posted @@ -229,15 +229,15 @@ static stm32wb_mbox_evt_handler_t receive_evt_handler; * ****************************************************************************/ -static void stm32wb_ipcc_rxoisr(int irq, uint32_t *regs, void *arg) +static void stm32_ipcc_rxoisr(int irq, uint32_t *regs, void *arg) { uint32_t clrmask = 0; /* Pull events from system channel into processing queue */ - if (stm32wb_ipcc_rxactive(STM32_MBOX_SYSEVT_CHANNEL)) + if (stm32_ipcc_rxactive(STM32_MBOX_SYSEVT_CHANNEL)) { - stm32wb_mbox_list_moveall(&stm32wb_mbox_shared.sys_evt_queue, + stm32_mbox_list_moveall(&stm32_mbox_shared.sys_evt_queue, &g_rx_evt_queue); clrmask |= IPCC_C1SCR_CLR_BIT(STM32_MBOX_SYSEVT_CHANNEL); @@ -247,9 +247,9 @@ static void stm32wb_ipcc_rxoisr(int irq, uint32_t *regs, void *arg) /* Pull events from BLE channel into processing queue */ - if (stm32wb_ipcc_rxactive(STM32_MBOX_BLEEVT_CHANNEL)) + if (stm32_ipcc_rxactive(STM32_MBOX_BLEEVT_CHANNEL)) { - stm32wb_mbox_list_moveall(&stm32wb_mbox_shared.ble_evt_queue, + stm32_mbox_list_moveall(&stm32_mbox_shared.ble_evt_queue, &g_rx_evt_queue); clrmask |= IPCC_C1SCR_CLR_BIT(STM32_MBOX_BLEEVT_CHANNEL); @@ -260,7 +260,7 @@ static void stm32wb_ipcc_rxoisr(int irq, uint32_t *regs, void *arg) if (work_available(&g_rx_evt_work)) { - work_queue(HPWORK, &g_rx_evt_work, stm32wb_mbox_rxworker, NULL, 0); + work_queue(HPWORK, &g_rx_evt_work, stm32_mbox_rxworker, NULL, 0); } /* Clear active statuses */ @@ -269,7 +269,7 @@ static void stm32wb_ipcc_rxoisr(int irq, uint32_t *regs, void *arg) } /**************************************************************************** - * Name: stm32wb_ipcc_txfisr + * Name: stm32_ipcc_txfisr * * Description: * TX channel free interrupt handler (communication data retrieved @@ -277,7 +277,7 @@ static void stm32wb_ipcc_rxoisr(int irq, uint32_t *regs, void *arg) * ****************************************************************************/ -static void stm32wb_ipcc_txfisr(int irq, uint32_t *regs, void *arg) +static void stm32_ipcc_txfisr(int irq, uint32_t *regs, void *arg) { uint32_t c1mr = getreg32(STM32_IPCC_C1MR); uint32_t txfsrc; @@ -296,14 +296,14 @@ static void stm32wb_ipcc_txfisr(int irq, uint32_t *regs, void *arg) { /* Move all released events (if any) into transmission mailbox */ - if (!stm32wb_mbox_list_is_empty(&g_tx_evtfree_queue)) + if (!stm32_mbox_list_is_empty(&g_tx_evtfree_queue)) { - stm32wb_mbox_list_moveall(&g_tx_evtfree_queue, - &stm32wb_mbox_shared.evtfree_buffer); + stm32_mbox_list_moveall(&g_tx_evtfree_queue, + &stm32_mbox_shared.evtfree_buffer); /* Start release channel transmission */ - stm32wb_ipcc_settxactive(STM32_MBOX_EVT_RELEASE_CHANNEL); + stm32_ipcc_settxactive(STM32_MBOX_EVT_RELEASE_CHANNEL); } } @@ -327,7 +327,7 @@ static void stm32wb_ipcc_txfisr(int irq, uint32_t *regs, void *arg) if (work_available(&g_tx_cmd_work)) { - work_queue(HPWORK, &g_tx_cmd_work, stm32wb_mbox_txworker, NULL, 0); + work_queue(HPWORK, &g_tx_cmd_work, stm32_mbox_txworker, NULL, 0); } } @@ -337,10 +337,10 @@ static void stm32wb_ipcc_txfisr(int irq, uint32_t *regs, void *arg) } /**************************************************************************** - * Name: stm32wb_mbox_txworker + * Name: stm32_mbox_txworker ****************************************************************************/ -static void stm32wb_mbox_txworker(void *arg) +static void stm32_mbox_txworker(void *arg) { bool handled; @@ -350,28 +350,28 @@ static void stm32wb_mbox_txworker(void *arg) { handled = false; - if (!stm32wb_ipcc_txactive(STM32_MBOX_SYSCMD_CHANNEL)) + if (!stm32_ipcc_txactive(STM32_MBOX_SYSCMD_CHANNEL)) { /* Process ack response before send new command */ if (g_syscmd_channel.ack_ready) { - stm32wb_mbox_acksyscmd(); + stm32_mbox_acksyscmd(); g_syscmd_channel.ack_ready = false; } - handled = stm32wb_mbox_txnext(&g_syscmd_channel); + handled = stm32_mbox_txnext(&g_syscmd_channel); } #ifdef CONFIG_STM32WB_BLE - if (!stm32wb_ipcc_txactive(STM32_MBOX_BLECMD_CHANNEL)) + if (!stm32_ipcc_txactive(STM32_MBOX_BLECMD_CHANNEL)) { - handled |= stm32wb_mbox_txnext(&g_blecmd_channel); + handled |= stm32_mbox_txnext(&g_blecmd_channel); } - if (!stm32wb_ipcc_txactive(STM32_MBOX_BLEACL_CHANNEL)) + if (!stm32_ipcc_txactive(STM32_MBOX_BLEACL_CHANNEL)) { - handled |= stm32wb_mbox_txnext(&g_bleacl_channel); + handled |= stm32_mbox_txnext(&g_bleacl_channel); } #endif } @@ -379,12 +379,12 @@ static void stm32wb_mbox_txworker(void *arg) } /**************************************************************************** - * Name: stm32wb_mbox_rxworker + * Name: stm32_mbox_rxworker ****************************************************************************/ -static void stm32wb_mbox_rxworker(void *arg) +static void stm32_mbox_rxworker(void *arg) { - stm32wb_mbox_list_t *evt; + stm32_mbox_list_t *evt; irqstate_t flags; while (1) @@ -393,7 +393,7 @@ static void stm32wb_mbox_rxworker(void *arg) /* Pull an event from the queue */ - evt = stm32wb_mbox_list_remove_head(&g_rx_evt_queue); + evt = stm32_mbox_list_remove_head(&g_rx_evt_queue); leave_critical_section(flags); @@ -404,18 +404,18 @@ static void stm32wb_mbox_rxworker(void *arg) /* Pass event to a callback function without a list header */ - receive_evt_handler((struct stm32wb_mbox_evt_s *)(evt + 1)); + receive_evt_handler((struct stm32_mbox_evt_s *)(evt + 1)); /* Free completed event. Released event needs to return to CPU2 * via release channel. */ - stm32wb_mbox_eventfree((stm32wb_mbox_list_t *)evt); + stm32_mbox_eventfree((stm32_mbox_list_t *)evt); } } /**************************************************************************** - * Name: stm32wb_mbox_txdata + * Name: stm32_mbox_txdata * * Description: * Send data over specified mailbox channel if possible. If the @@ -423,11 +423,11 @@ static void stm32wb_mbox_rxworker(void *arg) * ****************************************************************************/ -static int stm32wb_mbox_txdata(struct stm32wb_mbox_channel_s *chan, +static int stm32_mbox_txdata(struct stm32_mbox_channel_s *chan, uint8_t type, void *data, size_t len) { irqstate_t flags; - struct stm32wb_mbox_cmd_s *pkt_buf; + struct stm32_mbox_cmd_s *pkt_buf; flags = enter_critical_section(); @@ -435,8 +435,8 @@ static int stm32wb_mbox_txdata(struct stm32wb_mbox_channel_s *chan, * none of other waiting commands and none of unprocessed ack responses. */ - if (stm32wb_mbox_list_is_empty(&chan->cmd_buf_queue) && - !stm32wb_ipcc_txactive(chan->ch_num) && !chan->ack_ready) + if (stm32_mbox_list_is_empty(&chan->cmd_buf_queue) && + !stm32_ipcc_txactive(chan->ch_num) && !chan->ack_ready) { /* Channel is ready, copy command into transmission buffer */ @@ -446,8 +446,8 @@ static int stm32wb_mbox_txdata(struct stm32wb_mbox_channel_s *chan, { /* Otherwise get temp buffer for command */ - pkt_buf = (struct stm32wb_mbox_cmd_s *) - stm32wb_mbox_list_remove_head(&g_free_buffers_pool); + pkt_buf = (struct stm32_mbox_cmd_s *) + stm32_mbox_list_remove_head(&g_free_buffers_pool); } leave_critical_section(flags); @@ -464,9 +464,9 @@ static int stm32wb_mbox_txdata(struct stm32wb_mbox_channel_s *chan, { /* Command is ready in mailbox buffer, start transmission now */ - stm32wb_ipcc_settxactive(chan->ch_num); + stm32_ipcc_settxactive(chan->ch_num); - if (!stm32wb_mbox_list_is_empty(&chan->cmd_buf_queue) || + if (!stm32_mbox_list_is_empty(&chan->cmd_buf_queue) || chan->ch_num == STM32_MBOX_SYSCMD_CHANNEL) { /* There are more commands awaiting, so unmask interrupt to get @@ -474,7 +474,7 @@ static int stm32wb_mbox_txdata(struct stm32wb_mbox_channel_s *chan, * And the system channel needs to check ack on completion. */ - stm32wb_ipcc_unmasktxf(chan->ch_num); + stm32_ipcc_unmasktxf(chan->ch_num); } } else @@ -482,31 +482,31 @@ static int stm32wb_mbox_txdata(struct stm32wb_mbox_channel_s *chan, /* Command is in temp buffer, push it into queue */ flags = enter_critical_section(); - stm32wb_mbox_list_add_tail(&chan->cmd_buf_queue, &pkt_buf->list_hdr); + stm32_mbox_list_add_tail(&chan->cmd_buf_queue, &pkt_buf->list_hdr); leave_critical_section(flags); /* Unmask interrupt to get notified when channel gets free */ - stm32wb_ipcc_unmasktxf(chan->ch_num); + stm32_ipcc_unmasktxf(chan->ch_num); } return OK; } /**************************************************************************** - * Name: stm32wb_mbox_txnext + * Name: stm32_mbox_txnext * * Description: * Send next command from the queue. * ****************************************************************************/ -static bool stm32wb_mbox_txnext(struct stm32wb_mbox_channel_s *chan) +static bool stm32_mbox_txnext(struct stm32_mbox_channel_s *chan) { - struct stm32wb_mbox_cmd_s *pkt_buf; + struct stm32_mbox_cmd_s *pkt_buf; - pkt_buf = (struct stm32wb_mbox_cmd_s *) - stm32wb_mbox_list_remove_head(&chan->cmd_buf_queue); + pkt_buf = (struct stm32_mbox_cmd_s *) + stm32_mbox_list_remove_head(&chan->cmd_buf_queue); if (pkt_buf != NULL) { @@ -525,32 +525,32 @@ static bool stm32wb_mbox_txnext(struct stm32wb_mbox_channel_s *chan) /* Start transmission */ - stm32wb_ipcc_settxactive(chan->ch_num); + stm32_ipcc_settxactive(chan->ch_num); - if (!stm32wb_mbox_list_is_empty(&chan->cmd_buf_queue)) + if (!stm32_mbox_list_is_empty(&chan->cmd_buf_queue)) { /* Unmask TXF interrupt to get notified when completed */ - stm32wb_ipcc_unmasktxf(chan->ch_num); + stm32_ipcc_unmasktxf(chan->ch_num); } /* Put back to pool the freed command buffer */ - stm32wb_mbox_list_add_tail(&g_free_buffers_pool, &pkt_buf->list_hdr); + stm32_mbox_list_add_tail(&g_free_buffers_pool, &pkt_buf->list_hdr); } return pkt_buf != NULL; } /**************************************************************************** - * Name: stm32wb_mbox_eventfree + * Name: stm32_mbox_eventfree * * Description: * Free handled mailbox event. * ****************************************************************************/ -static void stm32wb_mbox_eventfree(stm32wb_mbox_list_t *evt) +static void stm32_mbox_eventfree(stm32_mbox_list_t *evt) { irqstate_t flags; @@ -558,48 +558,48 @@ static void stm32wb_mbox_eventfree(stm32wb_mbox_list_t *evt) /* Collect releasing events in the global list */ - stm32wb_mbox_list_add_tail(&g_tx_evtfree_queue, evt); + stm32_mbox_list_add_tail(&g_tx_evtfree_queue, evt); /* Check if release channel is ready to process now */ - if (!stm32wb_ipcc_txactive(STM32_MBOX_EVT_RELEASE_CHANNEL)) + if (!stm32_ipcc_txactive(STM32_MBOX_EVT_RELEASE_CHANNEL)) { /* Move all collected events into transmission queue */ - stm32wb_mbox_list_moveall(&g_tx_evtfree_queue, - &stm32wb_mbox_shared.evtfree_buffer); + stm32_mbox_list_moveall(&g_tx_evtfree_queue, + &stm32_mbox_shared.evtfree_buffer); /* Start transmission */ - stm32wb_ipcc_settxactive(STM32_MBOX_EVT_RELEASE_CHANNEL); + stm32_ipcc_settxactive(STM32_MBOX_EVT_RELEASE_CHANNEL); } else { /* Unmask interrupt to get notified when channel gets free */ - stm32wb_ipcc_unmasktxf(STM32_MBOX_EVT_RELEASE_CHANNEL); + stm32_ipcc_unmasktxf(STM32_MBOX_EVT_RELEASE_CHANNEL); } leave_critical_section(flags); } /**************************************************************************** - * Name: stm32wb_mbox_acksyscmd + * Name: stm32_mbox_acksyscmd * * Description: * Send ACK response event for completed system command. * ****************************************************************************/ -static void stm32wb_mbox_acksyscmd(void) +static void stm32_mbox_acksyscmd(void) { - struct stm32wb_mbox_evt_s *evt; + struct stm32_mbox_evt_s *evt; /* System command ACK response is placed at the same address as the * processed command but without a list header. */ - evt = (struct stm32wb_mbox_evt_s *)(&g_syscmd_channel.cmd_buf); + evt = (struct stm32_mbox_evt_s *)(&g_syscmd_channel.cmd_buf); evt->type = STM32_MBOX_SYSACK; receive_evt_handler(evt); @@ -610,7 +610,7 @@ static void stm32wb_mbox_acksyscmd(void) ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_mboxinitialize + * Name: stm32_mboxinitialize * * Description: * Initialize mailbox driver memory. @@ -620,79 +620,79 @@ static void stm32wb_mbox_acksyscmd(void) * ****************************************************************************/ -void stm32wb_mboxinitialize(stm32wb_mbox_evt_handler_t evt_handler) +void stm32_mboxinitialize(stm32_mbox_evt_handler_t evt_handler) { int i; /* Init mailbox shared data */ - stm32wb_mbox_list_initialize(&stm32wb_mbox_shared.sys_evt_queue); - stm32wb_mbox_list_initialize(&stm32wb_mbox_shared.evtfree_buffer); + stm32_mbox_list_initialize(&stm32_mbox_shared.sys_evt_queue); + stm32_mbox_list_initialize(&stm32_mbox_shared.evtfree_buffer); #ifdef CONFIG_STM32WB_BLE - stm32wb_mbox_list_initialize(&stm32wb_mbox_shared.ble_evt_queue); + stm32_mbox_list_initialize(&stm32_mbox_shared.ble_evt_queue); #endif - stm32wb_mbox_ref_table.dev_info_table = &stm32wb_mbox_di_table; - stm32wb_mbox_ref_table.ble_table = &stm32wb_mbox_ble_table; - stm32wb_mbox_ref_table.sys_table = &stm32wb_mbox_sys_table; - stm32wb_mbox_ref_table.mm_table = &stm32wb_mbox_mm_table; + stm32_mbox_ref_table.dev_info_table = &stm32_mbox_di_table; + stm32_mbox_ref_table.ble_table = &stm32_mbox_ble_table; + stm32_mbox_ref_table.sys_table = &stm32_mbox_sys_table; + stm32_mbox_ref_table.mm_table = &stm32_mbox_mm_table; - stm32wb_mbox_sys_table.cmd_buffer = &stm32wb_mbox_shared.sys_cmd_buffer; - stm32wb_mbox_sys_table.evt_queue = &stm32wb_mbox_shared.sys_evt_queue; + stm32_mbox_sys_table.cmd_buffer = &stm32_mbox_shared.sys_cmd_buffer; + stm32_mbox_sys_table.evt_queue = &stm32_mbox_shared.sys_evt_queue; - stm32wb_mbox_mm_table.evtpool_buffer = &stm32wb_mbox_shared + stm32_mbox_mm_table.evtpool_buffer = &stm32_mbox_shared .evtpool_buffer; - stm32wb_mbox_mm_table.evtpool_size = sizeof(stm32wb_mbox_shared + stm32_mbox_mm_table.evtpool_size = sizeof(stm32_mbox_shared .evtpool_buffer); - stm32wb_mbox_mm_table.evtfree_buffer = &stm32wb_mbox_shared + stm32_mbox_mm_table.evtfree_buffer = &stm32_mbox_shared .evtfree_buffer; - stm32wb_mbox_mm_table.sys_spare_buffer = &stm32wb_mbox_shared + stm32_mbox_mm_table.sys_spare_buffer = &stm32_mbox_shared .sys_spare_buffer; #ifdef CONFIG_STM32WB_BLE - stm32wb_mbox_mm_table.ble_spare_buffer = &stm32wb_mbox_shared + stm32_mbox_mm_table.ble_spare_buffer = &stm32_mbox_shared .ble_spare_buffer; #endif #ifdef CONFIG_STM32WB_BLE - stm32wb_mbox_ble_table.cmd_buffer = &stm32wb_mbox_shared.ble_cmd_buffer; - stm32wb_mbox_ble_table.acl_buffer = &stm32wb_mbox_shared.ble_acl_buffer; - stm32wb_mbox_ble_table.cs_buffer = &stm32wb_mbox_shared.ble_cs_buffer; - stm32wb_mbox_ble_table.evt_queue = &stm32wb_mbox_shared.ble_evt_queue; + stm32_mbox_ble_table.cmd_buffer = &stm32_mbox_shared.ble_cmd_buffer; + stm32_mbox_ble_table.acl_buffer = &stm32_mbox_shared.ble_acl_buffer; + stm32_mbox_ble_table.cs_buffer = &stm32_mbox_shared.ble_cs_buffer; + stm32_mbox_ble_table.evt_queue = &stm32_mbox_shared.ble_evt_queue; #endif /* Init system channel data */ g_syscmd_channel.ch_num = STM32_MBOX_SYSCMD_CHANNEL; - g_syscmd_channel.cmd_buf = (struct stm32wb_mbox_cmd_s *) - stm32wb_mbox_shared.sys_cmd_buffer; - stm32wb_mbox_list_initialize(&g_syscmd_channel.cmd_buf_queue); + g_syscmd_channel.cmd_buf = (struct stm32_mbox_cmd_s *) + stm32_mbox_shared.sys_cmd_buffer; + stm32_mbox_list_initialize(&g_syscmd_channel.cmd_buf_queue); #ifdef CONFIG_STM32WB_BLE /* Init BLE command channel data */ g_blecmd_channel.ch_num = STM32_MBOX_BLECMD_CHANNEL; - g_blecmd_channel.cmd_buf = (struct stm32wb_mbox_cmd_s *) - stm32wb_mbox_shared.ble_cmd_buffer; - stm32wb_mbox_list_initialize(&g_blecmd_channel.cmd_buf_queue); + g_blecmd_channel.cmd_buf = (struct stm32_mbox_cmd_s *) + stm32_mbox_shared.ble_cmd_buffer; + stm32_mbox_list_initialize(&g_blecmd_channel.cmd_buf_queue); /* Init BLE ACL channel data */ g_bleacl_channel.ch_num = STM32_MBOX_BLEACL_CHANNEL; - g_bleacl_channel.cmd_buf = (struct stm32wb_mbox_cmd_s *) - stm32wb_mbox_shared.ble_acl_buffer; - stm32wb_mbox_list_initialize(&g_bleacl_channel.cmd_buf_queue); + g_bleacl_channel.cmd_buf = (struct stm32_mbox_cmd_s *) + stm32_mbox_shared.ble_acl_buffer; + stm32_mbox_list_initialize(&g_bleacl_channel.cmd_buf_queue); #endif /* Init local (not shared) queues */ - stm32wb_mbox_list_initialize(&g_rx_evt_queue); - stm32wb_mbox_list_initialize(&g_tx_evtfree_queue); + stm32_mbox_list_initialize(&g_rx_evt_queue); + stm32_mbox_list_initialize(&g_tx_evtfree_queue); - stm32wb_mbox_list_initialize(&g_free_buffers_pool); + stm32_mbox_list_initialize(&g_free_buffers_pool); for (i = 0; i < CONFIG_STM32WB_MBOX_TX_CMD_QUEUE_LEN; i++) { - stm32wb_mbox_list_add_tail(&g_free_buffers_pool, - (stm32wb_mbox_list_t *)g_free_buffers[i]); + stm32_mbox_list_add_tail(&g_free_buffers_pool, + (stm32_mbox_list_t *)g_free_buffers[i]); } /* Set event receive function */ @@ -701,7 +701,7 @@ void stm32wb_mboxinitialize(stm32wb_mbox_evt_handler_t evt_handler) } /**************************************************************************** - * Name: stm32wb_mboxenable + * Name: stm32_mboxenable * * Description: * Enable mailbox hardware and start communication. The CPU2 responses @@ -709,16 +709,16 @@ void stm32wb_mboxinitialize(stm32wb_mbox_evt_handler_t evt_handler) * ****************************************************************************/ -void stm32wb_mboxenable(void) +void stm32_mboxenable(void) { uint32_t regval; /* Setup RXO and TXF interrupts */ - irq_attach(STM32_IRQ_IPCCRX, (xcpt_t)stm32wb_ipcc_rxoisr, NULL); + irq_attach(STM32_IRQ_IPCCRX, (xcpt_t)stm32_ipcc_rxoisr, NULL); up_enable_irq(STM32_IRQ_IPCCRX); - irq_attach(STM32_IRQ_IPCCTX, (xcpt_t)stm32wb_ipcc_txfisr, NULL); + irq_attach(STM32_IRQ_IPCCTX, (xcpt_t)stm32_ipcc_txfisr, NULL); up_enable_irq(STM32_IRQ_IPCCTX); regval = getreg32(STM32_IPCC_C1CR); @@ -729,15 +729,15 @@ void stm32wb_mboxenable(void) * to receive C2READY event via system channel. */ - stm32wb_ipcc_unmaskrxo(STM32_MBOX_SYSEVT_CHANNEL); + stm32_ipcc_unmaskrxo(STM32_MBOX_SYSEVT_CHANNEL); /* Enable IPCC hardware and boot up CPU2 */ - stm32wb_ipccenable(); + stm32_ipccenable(); } /**************************************************************************** - * Name: stm32wb_mbox_syscmd + * Name: stm32_mbox_syscmd * * Description: * Send command over mailbox system channel. Command data must be @@ -745,15 +745,15 @@ void stm32wb_mboxenable(void) * ****************************************************************************/ -int stm32wb_mbox_syscmd(void *data, size_t len) +int stm32_mbox_syscmd(void *data, size_t len) { - return stm32wb_mbox_txdata(&g_syscmd_channel, STM32_MBOX_SYSCMD, + return stm32_mbox_txdata(&g_syscmd_channel, STM32_MBOX_SYSCMD, data, len); } #ifdef CONFIG_STM32WB_BLE /**************************************************************************** - * Name: stm32wb_mbox_blecmd + * Name: stm32_mbox_blecmd * * Description: * Send command over mailbox BLE channel. Command data must be @@ -761,14 +761,14 @@ int stm32wb_mbox_syscmd(void *data, size_t len) * ****************************************************************************/ -int stm32wb_mbox_blecmd(void *data, size_t len) +int stm32_mbox_blecmd(void *data, size_t len) { - return stm32wb_mbox_txdata(&g_blecmd_channel, STM32_MBOX_HCICMD, + return stm32_mbox_txdata(&g_blecmd_channel, STM32_MBOX_HCICMD, data, len); } /**************************************************************************** - * Name: stm32wb_mbox_bleacl + * Name: stm32_mbox_bleacl * * Description: * Send BLE ACL data over mailbox BLE ACL channel. Data must be @@ -776,27 +776,27 @@ int stm32wb_mbox_blecmd(void *data, size_t len) * ****************************************************************************/ -int stm32wb_mbox_bleacl(void *data, size_t len) +int stm32_mbox_bleacl(void *data, size_t len) { - return stm32wb_mbox_txdata(&g_bleacl_channel, STM32_MBOX_HCIACL, + return stm32_mbox_txdata(&g_bleacl_channel, STM32_MBOX_HCIACL, data, len); } /**************************************************************************** - * Name: stm32wb_mbox_bleinit + * Name: stm32_mbox_bleinit * * Description: * Initialize and start BLE subsystem with provided configuration params. * ****************************************************************************/ -void stm32wb_mbox_bleinit(struct stm32wb_shci_ble_init_cfg_s *params) +void stm32_mbox_bleinit(struct stm32_shci_ble_init_cfg_s *params) { struct bt_hci_cmd_hdr_s *cmd; /* Just borrow a temporary free buffer for command data */ - cmd = (struct bt_hci_cmd_hdr_s *)stm32wb_mbox_shared.sys_spare_buffer; + cmd = (struct bt_hci_cmd_hdr_s *)stm32_mbox_shared.sys_spare_buffer; /* Prepare command data */ @@ -806,10 +806,10 @@ void stm32wb_mbox_bleinit(struct stm32wb_shci_ble_init_cfg_s *params) /* Send BLE init command to CPU2 */ - stm32wb_mbox_syscmd(cmd, sizeof(*cmd) + sizeof(*params)); + stm32_mbox_syscmd(cmd, sizeof(*cmd) + sizeof(*params)); /* Unmask BLE event channel RXO interrupt */ - stm32wb_ipcc_unmaskrxo(STM32_MBOX_BLEEVT_CHANNEL); + stm32_ipcc_unmaskrxo(STM32_MBOX_BLEEVT_CHANNEL); } #endif /* CONFIG_STM32WB_BLE */ diff --git a/arch/arm/src/stm32wb/stm32wb_mbox.h b/arch/arm/src/stm32wb/stm32wb_mbox.h index 6d5f9cc7932..2d7ea4b437c 100644 --- a/arch/arm/src/stm32wb/stm32wb_mbox.h +++ b/arch/arm/src/stm32wb/stm32wb_mbox.h @@ -77,7 +77,7 @@ /* Mailbox data transfer packets */ -begin_packed_struct struct stm32wb_mbox_evt_s +begin_packed_struct struct stm32_mbox_evt_s { uint8_t type; union @@ -87,9 +87,9 @@ begin_packed_struct struct stm32wb_mbox_evt_s }; } end_packed_struct; -begin_packed_struct struct stm32wb_mbox_cmd_s +begin_packed_struct struct stm32_mbox_cmd_s { - stm32wb_mbox_list_t list_hdr; + stm32_mbox_list_t list_hdr; uint8_t type; union { @@ -100,14 +100,14 @@ begin_packed_struct struct stm32wb_mbox_cmd_s /* Mailbox receive event handler type */ -typedef int (*stm32wb_mbox_evt_handler_t)(struct stm32wb_mbox_evt_s *); +typedef int (*stm32_mbox_evt_handler_t)(struct stm32_mbox_evt_s *); /**************************************************************************** * Public Function Prototypes ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_mboxinitialize + * Name: stm32_mboxinitialize * * Description: * Initialize mailbox driver memory. @@ -117,10 +117,10 @@ typedef int (*stm32wb_mbox_evt_handler_t)(struct stm32wb_mbox_evt_s *); * ****************************************************************************/ -void stm32wb_mboxinitialize(stm32wb_mbox_evt_handler_t evt_handler); +void stm32_mboxinitialize(stm32_mbox_evt_handler_t evt_handler); /**************************************************************************** - * Name: stm32wb_mboxenable + * Name: stm32_mboxenable * * Description: * Enable mailbox hardware and start communication. The CPU2 responses @@ -128,10 +128,10 @@ void stm32wb_mboxinitialize(stm32wb_mbox_evt_handler_t evt_handler); * ****************************************************************************/ -void stm32wb_mboxenable(void); +void stm32_mboxenable(void); /**************************************************************************** - * Name: stm32wb_mbox_syscmd + * Name: stm32_mbox_syscmd * * Description: * Send command over mailbox system channel. Command data must be @@ -139,10 +139,10 @@ void stm32wb_mboxenable(void); * ****************************************************************************/ -int stm32wb_mbox_syscmd(void *data, size_t len); +int stm32_mbox_syscmd(void *data, size_t len); /**************************************************************************** - * Name: stm32wb_mbox_blecmd + * Name: stm32_mbox_blecmd * * Description: * Send command over mailbox BLE channel. Command data must be @@ -150,10 +150,10 @@ int stm32wb_mbox_syscmd(void *data, size_t len); * ****************************************************************************/ -int stm32wb_mbox_blecmd(void *data, size_t len); +int stm32_mbox_blecmd(void *data, size_t len); /**************************************************************************** - * Name: stm32wb_mbox_bleacl + * Name: stm32_mbox_bleacl * * Description: * Send BLE ACL data over mailbox BLE ACL channel. Data must be @@ -161,16 +161,16 @@ int stm32wb_mbox_blecmd(void *data, size_t len); * ****************************************************************************/ -int stm32wb_mbox_bleacl(void *data, size_t len); +int stm32_mbox_bleacl(void *data, size_t len); /**************************************************************************** - * Name: stm32wb_mbox_bleinit + * Name: stm32_mbox_bleinit * * Description: * Initialize and start BLE subsystem with provided configuration params. * ****************************************************************************/ -void stm32wb_mbox_bleinit(struct stm32wb_shci_ble_init_cfg_s *params); +void stm32_mbox_bleinit(struct stm32_shci_ble_init_cfg_s *params); #endif /* __ARCH_ARM_SRC_STM32WB_STM32WB_MBOX_H */ diff --git a/arch/arm/src/stm32wb/stm32wb_mbox_list.h b/arch/arm/src/stm32wb/stm32wb_mbox_list.h index 4208da7fbec..80b3838155d 100644 --- a/arch/arm/src/stm32wb/stm32wb_mbox_list.h +++ b/arch/arm/src/stm32wb/stm32wb_mbox_list.h @@ -38,42 +38,42 @@ * a new list_moveall function. */ -begin_packed_struct struct stm32wb_mbox_list_s +begin_packed_struct struct stm32_mbox_list_s { - struct stm32wb_mbox_list_s *next; - struct stm32wb_mbox_list_s *prev; + struct stm32_mbox_list_s *next; + struct stm32_mbox_list_s *prev; } end_packed_struct; -typedef struct stm32wb_mbox_list_s stm32wb_mbox_list_t; +typedef struct stm32_mbox_list_s stm32_mbox_list_t; /**************************************************************************** * Inline Functions ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_mbox_list_initialize + * Name: stm32_mbox_list_initialize * * Description: * Initialize internal fields. * ****************************************************************************/ -static inline void stm32wb_mbox_list_initialize(stm32wb_mbox_list_t *list) +static inline void stm32_mbox_list_initialize(stm32_mbox_list_t *list) { list->prev = list; list->next = list; } /**************************************************************************** - * Name: stm32wb_mbox_list_add_tail + * Name: stm32_mbox_list_add_tail * * Description: * Add new node at the end of the list. * ****************************************************************************/ -static inline void stm32wb_mbox_list_add_tail(stm32wb_mbox_list_t *list, - stm32wb_mbox_list_t *item) +static inline void stm32_mbox_list_add_tail(stm32_mbox_list_t *list, + stm32_mbox_list_t *item) { item->prev = list->prev; item->next = list; @@ -82,19 +82,19 @@ static inline void stm32wb_mbox_list_add_tail(stm32wb_mbox_list_t *list, } /**************************************************************************** - * Name: stm32wb_mbox_list_remove_head + * Name: stm32_mbox_list_remove_head * * Description: * Remove and return first node from the list head (if any). * ****************************************************************************/ -static inline stm32wb_mbox_list_t * -stm32wb_mbox_list_remove_head(stm32wb_mbox_list_t *list) +static inline stm32_mbox_list_t * +stm32_mbox_list_remove_head(stm32_mbox_list_t *list) { if (list->next != list) { - stm32wb_mbox_list_t *item = list->next; + stm32_mbox_list_t *item = list->next; item->next->prev = item->prev; item->prev->next = item->next; item->prev = NULL; @@ -108,20 +108,20 @@ stm32wb_mbox_list_remove_head(stm32wb_mbox_list_t *list) } /**************************************************************************** - * Name: stm32wb_mbox_list_is_empty + * Name: stm32_mbox_list_is_empty * * Description: * Check if the list is empty. * ****************************************************************************/ -static inline bool stm32wb_mbox_list_is_empty(stm32wb_mbox_list_t *list) +static inline bool stm32_mbox_list_is_empty(stm32_mbox_list_t *list) { return (list->next == list); } /**************************************************************************** - * Name: stm32wb_mbox_list_moveall + * Name: stm32_mbox_list_moveall * * Description: * Remove all nodes from source list and add them to the end of the @@ -129,8 +129,8 @@ static inline bool stm32wb_mbox_list_is_empty(stm32wb_mbox_list_t *list) * ****************************************************************************/ -static inline void stm32wb_mbox_list_moveall(stm32wb_mbox_list_t *src, - stm32wb_mbox_list_t *dst) +static inline void stm32_mbox_list_moveall(stm32_mbox_list_t *src, + stm32_mbox_list_t *dst) { if (src->next != src) { diff --git a/arch/arm/src/stm32wb/stm32wb_mbox_shci.h b/arch/arm/src/stm32wb/stm32wb_mbox_shci.h index 442dee86f15..e1eeffeb066 100644 --- a/arch/arm/src/stm32wb/stm32wb_mbox_shci.h +++ b/arch/arm/src/stm32wb/stm32wb_mbox_shci.h @@ -119,7 +119,7 @@ /* STM32_SHCI_BLE_INIT command params */ -begin_packed_struct struct stm32wb_shci_ble_init_cfg_s +begin_packed_struct struct stm32_shci_ble_init_cfg_s { void *ble_buf; /* Not used, must be NULL. */ uint32_t ble_buf_size; /* Not used, must be 0. */ diff --git a/arch/arm/src/stm32wb/stm32wb_mpuinit.c b/arch/arm/src/stm32wb/stm32wb_mpuinit.c index b9d878aadd0..acc1576a646 100644 --- a/arch/arm/src/stm32wb/stm32wb_mpuinit.c +++ b/arch/arm/src/stm32wb/stm32wb_mpuinit.c @@ -41,7 +41,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_mpuinitialize + * Name: stm32_mpuinitialize * * Description: * Configure the MPU to permit user-space access to only restricted SAM3U @@ -49,7 +49,7 @@ * ****************************************************************************/ -void stm32wb_mpuinitialize(void) +void stm32_mpuinitialize(void) { uintptr_t datastart = MIN(USERSPACE->us_datastart, USERSPACE->us_bssstart); uintptr_t dataend = MAX(USERSPACE->us_dataend, USERSPACE->us_bssend); @@ -74,7 +74,7 @@ void stm32wb_mpuinitialize(void) } /**************************************************************************** - * Name: stm32wb_mpu_uheap + * Name: stm32_mpu_uheap * * Description: * Map the user-heap region. @@ -83,7 +83,7 @@ void stm32wb_mpuinitialize(void) * ****************************************************************************/ -void stm32wb_mpu_uheap(uintptr_t start, size_t size) +void stm32_mpu_uheap(uintptr_t start, size_t size) { mpu_user_intsram(start, size); } diff --git a/arch/arm/src/stm32wb/stm32wb_mpuinit.h b/arch/arm/src/stm32wb/stm32wb_mpuinit.h index 1cc8d755c37..18ac01dea38 100644 --- a/arch/arm/src/stm32wb/stm32wb_mpuinit.h +++ b/arch/arm/src/stm32wb/stm32wb_mpuinit.h @@ -34,7 +34,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_mpuinitialize + * Name: stm32_mpuinitialize * * Description: * Configure the MPU to permit user-space access to only unrestricted MCU @@ -43,13 +43,13 @@ ****************************************************************************/ #ifdef CONFIG_BUILD_PROTECTED -void stm32wb_mpuinitialize(void); +void stm32_mpuinitialize(void); #else -# define stm32wb_mpuinitialize() +# define stm32_mpuinitialize() #endif /**************************************************************************** - * Name: stm32wb_mpu_uheap + * Name: stm32_mpu_uheap * * Description: * Map the user heap region. @@ -57,9 +57,9 @@ void stm32wb_mpuinitialize(void); ****************************************************************************/ #ifdef CONFIG_BUILD_PROTECTED -void stm32wb_mpu_uheap(uintptr_t start, size_t size); +void stm32_mpu_uheap(uintptr_t start, size_t size); #else -# define stm32wb_mpu_uheap(start,size) +# define stm32_mpu_uheap(start,size) #endif #endif /* __ARCH_ARM_SRC_STM32WB_STM32WB_MPUINIT_H */ diff --git a/arch/arm/src/stm32wb/stm32wb_oneshot.c b/arch/arm/src/stm32wb/stm32wb_oneshot.c index bd8ffa00d19..9666c714bda 100644 --- a/arch/arm/src/stm32wb/stm32wb_oneshot.c +++ b/arch/arm/src/stm32wb/stm32wb_oneshot.c @@ -45,20 +45,20 @@ * Private Function Prototypes ****************************************************************************/ -static int stm32wb_oneshot_handler(int irq, void *context, void *arg); +static int stm32_oneshot_handler(int irq, void *context, void *arg); /**************************************************************************** * Private Data ****************************************************************************/ -static struct stm32wb_oneshot_s *g_oneshot[CONFIG_STM32WB_ONESHOT_MAXTIMERS]; +static struct stm32_oneshot_s *g_oneshot[CONFIG_STM32WB_ONESHOT_MAXTIMERS]; /**************************************************************************** * Private Functions ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_oneshot_handler + * Name: stm32_oneshot_handler * * Description: * Common timer interrupt callback. When any oneshot timer interrupt @@ -73,9 +73,9 @@ static struct stm32wb_oneshot_s *g_oneshot[CONFIG_STM32WB_ONESHOT_MAXTIMERS]; * ****************************************************************************/ -static int stm32wb_oneshot_handler(int irq, void *context, void *arg) +static int stm32_oneshot_handler(int irq, void *context, void *arg) { - struct stm32wb_oneshot_s *oneshot = (struct stm32wb_oneshot_s *)arg; + struct stm32_oneshot_s *oneshot = (struct stm32_oneshot_s *)arg; oneshot_handler_t oneshot_handler; void *oneshot_arg; @@ -107,7 +107,7 @@ static int stm32wb_oneshot_handler(int irq, void *context, void *arg) } /**************************************************************************** - * Name: stm32wb_allocate_handler + * Name: stm32_allocate_handler * * Description: * Allocate a timer callback handler for the oneshot instance. @@ -121,7 +121,7 @@ static int stm32wb_oneshot_handler(int irq, void *context, void *arg) * ****************************************************************************/ -static inline int stm32wb_allocate_handler(struct stm32wb_oneshot_s *oneshot) +static inline int stm32_allocate_handler(struct stm32_oneshot_s *oneshot) { #if CONFIG_STM32WB_ONESHOT_MAXTIMERS > 1 int ret = -EBUSY; @@ -162,7 +162,7 @@ static inline int stm32wb_allocate_handler(struct stm32wb_oneshot_s *oneshot) ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_oneshot_initialize + * Name: stm32_oneshot_initialize * * Description: * Initialize the oneshot timer wrapper @@ -180,7 +180,7 @@ static inline int stm32wb_allocate_handler(struct stm32wb_oneshot_s *oneshot) * ****************************************************************************/ -int stm32wb_oneshot_initialize(struct stm32wb_oneshot_s *oneshot, +int stm32_oneshot_initialize(struct stm32_oneshot_s *oneshot, int chan, uint16_t resolution) { uint32_t frequency; @@ -193,7 +193,7 @@ int stm32wb_oneshot_initialize(struct stm32wb_oneshot_s *oneshot, frequency = USEC_PER_SEC / (uint32_t)resolution; oneshot->frequency = frequency; - oneshot->tch = stm32wb_tim_init(chan); + oneshot->tch = stm32_tim_init(chan); if (!oneshot->tch) { tmrerr("ERROR: Failed to allocate TIM%d\n", chan); @@ -211,18 +211,18 @@ int stm32wb_oneshot_initialize(struct stm32wb_oneshot_s *oneshot, /* Assign a callback handler to the oneshot */ - return stm32wb_allocate_handler(oneshot); + return stm32_allocate_handler(oneshot); } /**************************************************************************** - * Name: stm32wb_oneshot_max_delay + * Name: stm32_oneshot_max_delay * * Description: * Determine the maximum delay of the one-shot timer (in microseconds) * ****************************************************************************/ -int stm32wb_oneshot_max_delay(struct stm32wb_oneshot_s *oneshot, +int stm32_oneshot_max_delay(struct stm32_oneshot_s *oneshot, uint64_t *usec) { DEBUGASSERT(oneshot != NULL && usec != NULL); @@ -233,7 +233,7 @@ int stm32wb_oneshot_max_delay(struct stm32wb_oneshot_s *oneshot, } /**************************************************************************** - * Name: stm32wb_oneshot_start + * Name: stm32_oneshot_start * * Description: * Start the oneshot timer @@ -241,7 +241,7 @@ int stm32wb_oneshot_max_delay(struct stm32wb_oneshot_s *oneshot, * Input Parameters: * oneshot Caller allocated instance of the oneshot state structure. This * structure must have been previously initialized via a call to - * stm32wb_oneshot_initialize(); + * stm32_oneshot_initialize(); * handler The function to call when when the oneshot timer expires. * arg An opaque argument that will accompany the callback. * ts Provides the duration of the one shot timer. @@ -252,7 +252,7 @@ int stm32wb_oneshot_max_delay(struct stm32wb_oneshot_s *oneshot, * ****************************************************************************/ -int stm32wb_oneshot_start(struct stm32wb_oneshot_s *oneshot, +int stm32_oneshot_start(struct stm32_oneshot_s *oneshot, oneshot_handler_t handler, void *arg, const struct timespec *ts) { @@ -273,7 +273,7 @@ int stm32wb_oneshot_start(struct stm32wb_oneshot_s *oneshot, /* Yes.. then cancel it */ tmrinfo("Already running... cancelling\n"); - stm32wb_oneshot_cancel(oneshot, NULL); + stm32_oneshot_cancel(oneshot, NULL); } /* Save the new handler and its argument */ @@ -301,7 +301,7 @@ int stm32wb_oneshot_start(struct stm32wb_oneshot_s *oneshot, /* Set up to receive the callback when the interrupt occurs */ - STM32_TIM_SETISR(oneshot->tch, stm32wb_oneshot_handler, oneshot, 0); + STM32_TIM_SETISR(oneshot->tch, stm32_oneshot_handler, oneshot, 0); /* Set timer period */ @@ -325,7 +325,7 @@ int stm32wb_oneshot_start(struct stm32wb_oneshot_s *oneshot, } /**************************************************************************** - * Name: stm32wb_oneshot_cancel + * Name: stm32_oneshot_cancel * * Description: * Cancel the oneshot timer and return the time remaining on the timer. @@ -336,7 +336,7 @@ int stm32wb_oneshot_start(struct stm32wb_oneshot_s *oneshot, * Input Parameters: * oneshot Caller allocated instance of the oneshot state structure. This * structure must have been previously initialized via a call to - * stm32wb_oneshot_initialize(); + * stm32_oneshot_initialize(); * ts The location in which to return the time remaining on the * oneshot timer. A time of zero is returned if the timer is * not running. ts may be zero in which case the time remaining @@ -349,7 +349,7 @@ int stm32wb_oneshot_start(struct stm32wb_oneshot_s *oneshot, * ****************************************************************************/ -int stm32wb_oneshot_cancel(struct stm32wb_oneshot_s *oneshot, +int stm32_oneshot_cancel(struct stm32_oneshot_s *oneshot, struct timespec *ts) { irqstate_t flags; diff --git a/arch/arm/src/stm32wb/stm32wb_oneshot.h b/arch/arm/src/stm32wb/stm32wb_oneshot.h index 37d45ac8ed2..d84e8f15b1c 100644 --- a/arch/arm/src/stm32wb/stm32wb_oneshot.h +++ b/arch/arm/src/stm32wb/stm32wb_oneshot.h @@ -67,20 +67,20 @@ typedef void (*oneshot_handler_t)(void *arg); /* The oneshot client must allocate an instance of this structure and called - * stm32wb_oneshot_initialize() before using the oneshot facilities. The + * stm32_oneshot_initialize() before using the oneshot facilities. The * client should not access the contents of this structure directly since * the contents are subject to change. */ -struct stm32wb_oneshot_s +struct stm32_oneshot_s { uint8_t chan; /* The timer/counter in use */ #if CONFIG_STM32WB_ONESHOT_MAXTIMERS > 1 uint8_t cbndx; /* Timer callback handler index */ #endif volatile bool running; /* True: the timer is running */ - struct stm32wb_tim_dev_s *tch; /* Pointer returned by - * stm32wb_tim_init() */ + struct stm32_tim_dev_s *tch; /* Pointer returned by + * stm32_tim_init() */ volatile oneshot_handler_t handler; /* Oneshot expiration callback */ volatile void *arg; /* The argument that will accompany * the callback */ @@ -106,7 +106,7 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_oneshot_initialize + * Name: stm32_oneshot_initialize * * Description: * Initialize the oneshot timer wrapper @@ -124,22 +124,22 @@ extern "C" * ****************************************************************************/ -int stm32wb_oneshot_initialize(struct stm32wb_oneshot_s *oneshot, int chan, +int stm32_oneshot_initialize(struct stm32_oneshot_s *oneshot, int chan, uint16_t resolution); /**************************************************************************** - * Name: stm32wb_oneshot_max_delay + * Name: stm32_oneshot_max_delay * * Description: * Determine the maximum delay of the one-shot timer (in microseconds) * ****************************************************************************/ -int stm32wb_oneshot_max_delay(struct stm32wb_oneshot_s *oneshot, +int stm32_oneshot_max_delay(struct stm32_oneshot_s *oneshot, uint64_t *usec); /**************************************************************************** - * Name: stm32wb_oneshot_start + * Name: stm32_oneshot_start * * Description: * Start the oneshot timer @@ -147,7 +147,7 @@ int stm32wb_oneshot_max_delay(struct stm32wb_oneshot_s *oneshot, * Input Parameters: * oneshot Caller allocated instance of the oneshot state structure. This * structure must have been previously initialized via a call to - * stm32wb_oneshot_initialize(); + * stm32_oneshot_initialize(); * handler The function to call when when the oneshot timer expires. * arg An opaque argument that will accompany the callback. * ts Provides the duration of the one shot timer. @@ -158,12 +158,12 @@ int stm32wb_oneshot_max_delay(struct stm32wb_oneshot_s *oneshot, * ****************************************************************************/ -int stm32wb_oneshot_start(struct stm32wb_oneshot_s *oneshot, +int stm32_oneshot_start(struct stm32_oneshot_s *oneshot, oneshot_handler_t handler, void *arg, const struct timespec *ts); /**************************************************************************** - * Name: stm32wb_oneshot_cancel + * Name: stm32_oneshot_cancel * * Description: * Cancel the oneshot timer and return the time remaining on the timer. @@ -174,7 +174,7 @@ int stm32wb_oneshot_start(struct stm32wb_oneshot_s *oneshot, * Input Parameters: * oneshot Caller allocated instance of the oneshot state structure. This * structure must have been previously initialized via a call to - * stm32wb_oneshot_initialize(); + * stm32_oneshot_initialize(); * ts The location in which to return the time remaining on the * oneshot timer. A time of zero is returned if the timer is * not running. @@ -186,7 +186,7 @@ int stm32wb_oneshot_start(struct stm32wb_oneshot_s *oneshot, * ****************************************************************************/ -int stm32wb_oneshot_cancel(struct stm32wb_oneshot_s *oneshot, +int stm32_oneshot_cancel(struct stm32_oneshot_s *oneshot, struct timespec *ts); #undef EXTERN diff --git a/arch/arm/src/stm32wb/stm32wb_oneshot_lowerhalf.c b/arch/arm/src/stm32wb/stm32wb_oneshot_lowerhalf.c index 4c1b7030377..d98270362c4 100644 --- a/arch/arm/src/stm32wb/stm32wb_oneshot_lowerhalf.c +++ b/arch/arm/src/stm32wb/stm32wb_oneshot_lowerhalf.c @@ -45,32 +45,32 @@ * driver */ -struct stm32wb_oneshot_lowerhalf_s +struct stm32_oneshot_lowerhalf_s { /* This is the part of the lower half driver that is visible to the upper- * half client of the driver. This must be the first thing in this * structure so that pointers to struct oneshot_lowerhalf_s are cast - * compatible to struct stm32wb_oneshot_lowerhalf_s and vice versa. + * compatible to struct stm32_oneshot_lowerhalf_s and vice versa. */ struct oneshot_lowerhalf_s lh; /* Common lower-half driver fields */ /* Private lower half data follows */ - struct stm32wb_oneshot_s oneshot; /* STM32-specific oneshot state */ + struct stm32_oneshot_s oneshot; /* STM32-specific oneshot state */ }; /**************************************************************************** * Private Function Prototypes ****************************************************************************/ -static void stm32wb_oneshot_handler(void *arg); +static void stm32_oneshot_handler(void *arg); -static int stm32wb_max_delay(struct oneshot_lowerhalf_s *lower, +static int stm32_max_delay(struct oneshot_lowerhalf_s *lower, struct timespec *ts); -static int stm32wb_start(struct oneshot_lowerhalf_s *lower, +static int stm32_start(struct oneshot_lowerhalf_s *lower, const struct timespec *ts); -static int stm32wb_cancel(struct oneshot_lowerhalf_s *lower, +static int stm32_cancel(struct oneshot_lowerhalf_s *lower, struct timespec *ts); /**************************************************************************** @@ -81,9 +81,9 @@ static int stm32wb_cancel(struct oneshot_lowerhalf_s *lower, static const struct oneshot_operations_s g_oneshot_ops = { - .max_delay = stm32wb_max_delay, - .start = stm32wb_start, - .cancel = stm32wb_cancel, + .max_delay = stm32_max_delay, + .start = stm32_start, + .cancel = stm32_cancel, }; /**************************************************************************** @@ -91,13 +91,13 @@ static const struct oneshot_operations_s g_oneshot_ops = ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_oneshot_handler + * Name: stm32_oneshot_handler * * Description: * Timer expiration handler * * Input Parameters: - * arg - Should be the same argument provided when stm32wb_oneshot_start() + * arg - Should be the same argument provided when stm32_oneshot_start() * was called. * * Returned Value: @@ -105,22 +105,22 @@ static const struct oneshot_operations_s g_oneshot_ops = * ****************************************************************************/ -static void stm32wb_oneshot_handler(void *arg) +static void stm32_oneshot_handler(void *arg) { - struct stm32wb_oneshot_lowerhalf_s *priv = - (struct stm32wb_oneshot_lowerhalf_s *)arg; + struct stm32_oneshot_lowerhalf_s *priv = + (struct stm32_oneshot_lowerhalf_s *)arg; DEBUGASSERT(priv != NULL); /* Perhaps the callback was nullified in a race condition with - * stm32wb_cancel? + * stm32_cancel? */ oneshot_process_callback(&priv->lh); } /**************************************************************************** - * Name: stm32wb_max_delay + * Name: stm32_max_delay * * Description: * Determine the maximum delay of the one-shot timer (in microseconds) @@ -137,16 +137,16 @@ static void stm32wb_oneshot_handler(void *arg) * ****************************************************************************/ -static int stm32wb_max_delay(struct oneshot_lowerhalf_s *lower, +static int stm32_max_delay(struct oneshot_lowerhalf_s *lower, struct timespec *ts) { - struct stm32wb_oneshot_lowerhalf_s *priv = - (struct stm32wb_oneshot_lowerhalf_s *)lower; + struct stm32_oneshot_lowerhalf_s *priv = + (struct stm32_oneshot_lowerhalf_s *)lower; uint64_t usecs; int ret; DEBUGASSERT(priv != NULL && ts != NULL); - ret = stm32wb_oneshot_max_delay(&priv->oneshot, &usecs); + ret = stm32_oneshot_max_delay(&priv->oneshot, &usecs); if (ret >= 0) { uint64_t sec = usecs / 1000000; @@ -160,7 +160,7 @@ static int stm32wb_max_delay(struct oneshot_lowerhalf_s *lower, } /**************************************************************************** - * Name: stm32wb_start + * Name: stm32_start * * Description: * Start the oneshot timer @@ -179,11 +179,11 @@ static int stm32wb_max_delay(struct oneshot_lowerhalf_s *lower, * ****************************************************************************/ -static int stm32wb_start(struct oneshot_lowerhalf_s *lower, +static int stm32_start(struct oneshot_lowerhalf_s *lower, const struct timespec *ts) { - struct stm32wb_oneshot_lowerhalf_s *priv = - (struct stm32wb_oneshot_lowerhalf_s *)lower; + struct stm32_oneshot_lowerhalf_s *priv = + (struct stm32_oneshot_lowerhalf_s *)lower; irqstate_t flags; int ret; @@ -192,20 +192,20 @@ static int stm32wb_start(struct oneshot_lowerhalf_s *lower, /* Save the callback information and start the timer */ flags = enter_critical_section(); - ret = stm32wb_oneshot_start(&priv->oneshot, - stm32wb_oneshot_handler, priv, ts); + ret = stm32_oneshot_start(&priv->oneshot, + stm32_oneshot_handler, priv, ts); leave_critical_section(flags); if (ret < 0) { - tmrerr("ERROR: stm32wb_oneshot_start failed: %d\n", flags); + tmrerr("ERROR: stm32_oneshot_start failed: %d\n", flags); } return ret; } /**************************************************************************** - * Name: stm32wb_cancel + * Name: stm32_cancel * * Description: * Cancel the oneshot timer and return the time remaining on the timer. @@ -228,11 +228,11 @@ static int stm32wb_start(struct oneshot_lowerhalf_s *lower, * ****************************************************************************/ -static int stm32wb_cancel(struct oneshot_lowerhalf_s *lower, +static int stm32_cancel(struct oneshot_lowerhalf_s *lower, struct timespec *ts) { - struct stm32wb_oneshot_lowerhalf_s *priv = - (struct stm32wb_oneshot_lowerhalf_s *)lower; + struct stm32_oneshot_lowerhalf_s *priv = + (struct stm32_oneshot_lowerhalf_s *)lower; irqstate_t flags; int ret; @@ -241,12 +241,12 @@ static int stm32wb_cancel(struct oneshot_lowerhalf_s *lower, /* Cancel the timer */ flags = enter_critical_section(); - ret = stm32wb_oneshot_cancel(&priv->oneshot, ts); + ret = stm32_oneshot_cancel(&priv->oneshot, ts); leave_critical_section(flags); if (ret < 0) { - tmrerr("ERROR: stm32wb_oneshot_cancel failed: %d\n", flags); + tmrerr("ERROR: stm32_oneshot_cancel failed: %d\n", flags); } return ret; @@ -277,13 +277,13 @@ static int stm32wb_cancel(struct oneshot_lowerhalf_s *lower, struct oneshot_lowerhalf_s *oneshot_initialize(int chan, uint16_t resolution) { - struct stm32wb_oneshot_lowerhalf_s *priv; + struct stm32_oneshot_lowerhalf_s *priv; int ret; /* Allocate an instance of the lower half driver */ - priv = (struct stm32wb_oneshot_lowerhalf_s *) - kmm_zalloc(sizeof(struct stm32wb_oneshot_lowerhalf_s)); + priv = (struct stm32_oneshot_lowerhalf_s *) + kmm_zalloc(sizeof(struct stm32_oneshot_lowerhalf_s)); if (priv == NULL) { @@ -297,10 +297,10 @@ struct oneshot_lowerhalf_s *oneshot_initialize(int chan, uint16_t resolution) /* Initialize the contained STM32 oneshot timer */ - ret = stm32wb_oneshot_initialize(&priv->oneshot, chan, resolution); + ret = stm32_oneshot_initialize(&priv->oneshot, chan, resolution); if (ret < 0) { - tmrerr("ERROR: stm32wb_oneshot_initialize failed: %d\n", ret); + tmrerr("ERROR: stm32_oneshot_initialize failed: %d\n", ret); kmm_free(priv); return NULL; } diff --git a/arch/arm/src/stm32wb/stm32wb_pm.h b/arch/arm/src/stm32wb/stm32wb_pm.h index 3876288bc1a..9da094f711e 100644 --- a/arch/arm/src/stm32wb/stm32wb_pm.h +++ b/arch/arm/src/stm32wb/stm32wb_pm.h @@ -48,7 +48,7 @@ extern "C" #endif /**************************************************************************** - * Name: stm32wb_pmstop + * Name: stm32_pmstop * * Description: * Enter STOP mode. @@ -66,10 +66,10 @@ extern "C" * ****************************************************************************/ -int stm32wb_pmstop(bool lpds); +int stm32_pmstop(bool lpds); /**************************************************************************** - * Name: stm32wb_pmstop2 + * Name: stm32_pmstop2 * * Description: * Enter STOP2 mode. @@ -84,10 +84,10 @@ int stm32wb_pmstop(bool lpds); * ****************************************************************************/ -int stm32wb_pmstop2(void); +int stm32_pmstop2(void); /**************************************************************************** - * Name: stm32wb_pmstandby + * Name: stm32_pmstandby * * Description: * Enter STANDBY mode. @@ -103,10 +103,10 @@ int stm32wb_pmstop2(void); * ****************************************************************************/ -int stm32wb_pmstandby(void); +int stm32_pmstandby(void); /**************************************************************************** - * Name: stm32wb_pmsleep + * Name: stm32_pmsleep * * Description: * Enter SLEEP mode. @@ -122,10 +122,10 @@ int stm32wb_pmstandby(void); * ****************************************************************************/ -void stm32wb_pmsleep(bool sleeponexit); +void stm32_pmsleep(bool sleeponexit); /**************************************************************************** - * Name: stm32wb_pmlpr + * Name: stm32_pmlpr * * Description: * Enter Low-Power Run (LPR) mode. @@ -140,7 +140,7 @@ void stm32wb_pmsleep(bool sleeponexit); * ****************************************************************************/ -int stm32wb_pmlpr(void); +int stm32_pmlpr(void); #undef EXTERN #ifdef __cplusplus diff --git a/arch/arm/src/stm32wb/stm32wb_pmlpr.c b/arch/arm/src/stm32wb/stm32wb_pmlpr.c index fa601b27961..a86617edbfa 100644 --- a/arch/arm/src/stm32wb/stm32wb_pmlpr.c +++ b/arch/arm/src/stm32wb/stm32wb_pmlpr.c @@ -39,7 +39,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_pmlpr + * Name: stm32_pmlpr * * Description: * Enter Low-Power Run (LPR) mode. @@ -54,7 +54,7 @@ * ****************************************************************************/ -int stm32wb_pmlpr(void) +int stm32_pmlpr(void) { uint32_t regval; diff --git a/arch/arm/src/stm32wb/stm32wb_pmsleep.c b/arch/arm/src/stm32wb/stm32wb_pmsleep.c index b9b64dd940c..8a2b0d62967 100644 --- a/arch/arm/src/stm32wb/stm32wb_pmsleep.c +++ b/arch/arm/src/stm32wb/stm32wb_pmsleep.c @@ -37,7 +37,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_pmsleep + * Name: stm32_pmsleep * * Description: * Enter SLEEP mode. @@ -53,7 +53,7 @@ * ****************************************************************************/ -void stm32wb_pmsleep(bool sleeponexit) +void stm32_pmsleep(bool sleeponexit) { uint32_t regval; diff --git a/arch/arm/src/stm32wb/stm32wb_pmstandby.c b/arch/arm/src/stm32wb/stm32wb_pmstandby.c index 657f4bf6779..09b81ae0236 100644 --- a/arch/arm/src/stm32wb/stm32wb_pmstandby.c +++ b/arch/arm/src/stm32wb/stm32wb_pmstandby.c @@ -37,7 +37,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_pmstandby + * Name: stm32_pmstandby * * Description: * Enter STANDBY mode. @@ -53,7 +53,7 @@ * ****************************************************************************/ -int stm32wb_pmstandby(void) +int stm32_pmstandby(void) { uint32_t regval; diff --git a/arch/arm/src/stm32wb/stm32wb_pmstop.c b/arch/arm/src/stm32wb/stm32wb_pmstop.c index 1cbd80f0e23..31a53a91602 100644 --- a/arch/arm/src/stm32wb/stm32wb_pmstop.c +++ b/arch/arm/src/stm32wb/stm32wb_pmstop.c @@ -72,7 +72,7 @@ static int do_stop(void) ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_pmstop + * Name: stm32_pmstop * * Description: * Enter STOP mode. @@ -90,7 +90,7 @@ static int do_stop(void) * ****************************************************************************/ -int stm32wb_pmstop(bool lpds) +int stm32_pmstop(bool lpds) { uint32_t regval; @@ -114,7 +114,7 @@ int stm32wb_pmstop(bool lpds) } /**************************************************************************** - * Name: stm32wb_pmstop2 + * Name: stm32_pmstop2 * * Description: * Enter STOP2 mode. @@ -129,7 +129,7 @@ int stm32wb_pmstop(bool lpds) * ****************************************************************************/ -int stm32wb_pmstop2(void) +int stm32_pmstop2(void) { uint32_t regval; diff --git a/arch/arm/src/stm32wb/stm32wb_pwr.c b/arch/arm/src/stm32wb/stm32wb_pwr.c index 62fe1b7be84..7e7338b9e1e 100644 --- a/arch/arm/src/stm32wb/stm32wb_pwr.c +++ b/arch/arm/src/stm32wb/stm32wb_pwr.c @@ -39,17 +39,17 @@ * Private Functions ****************************************************************************/ -static inline uint16_t stm32wb_pwr_getreg(uint8_t offset) +static inline uint16_t stm32_pwr_getreg(uint8_t offset) { return (uint16_t)getreg32(STM32_PWR_BASE + (uint32_t)offset); } -static inline void stm32wb_pwr_putreg(uint8_t offset, uint16_t value) +static inline void stm32_pwr_putreg(uint8_t offset, uint16_t value) { putreg32((uint32_t)value, STM32_PWR_BASE + (uint32_t)offset); } -static inline void stm32wb_pwr_modifyreg(uint8_t offset, uint16_t clearbits, +static inline void stm32_pwr_modifyreg(uint8_t offset, uint16_t clearbits, uint16_t setbits) { modifyreg32(STM32_PWR_BASE + (uint32_t)offset, @@ -61,7 +61,7 @@ static inline void stm32wb_pwr_modifyreg(uint8_t offset, uint16_t clearbits, ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_pwr_enablebkp + * Name: stm32_pwr_enablebkp * * Description: * Enables access to the backup domain (RTC registers and backup @@ -75,14 +75,14 @@ static inline void stm32wb_pwr_modifyreg(uint8_t offset, uint16_t clearbits, * ****************************************************************************/ -bool stm32wb_pwr_enablebkp(bool writable) +bool stm32_pwr_enablebkp(bool writable) { uint16_t regval; bool waswritable; /* Get the current state of the STM32WB PWR control register 1 */ - regval = stm32wb_pwr_getreg(STM32_PWR_CR1_OFFSET); + regval = stm32_pwr_getreg(STM32_PWR_CR1_OFFSET); waswritable = ((regval & PWR_CR1_DBP) != 0); /* Enable or disable the ability to write */ @@ -92,14 +92,14 @@ bool stm32wb_pwr_enablebkp(bool writable) /* Disable backup domain access */ regval &= ~PWR_CR1_DBP; - stm32wb_pwr_putreg(STM32_PWR_CR1_OFFSET, regval); + stm32_pwr_putreg(STM32_PWR_CR1_OFFSET, regval); } else if (!waswritable && writable) { /* Enable backup domain access */ regval |= PWR_CR1_DBP; - stm32wb_pwr_putreg(STM32_PWR_CR1_OFFSET, regval); + stm32_pwr_putreg(STM32_PWR_CR1_OFFSET, regval); /* Enable does not happen right away */ @@ -110,7 +110,7 @@ bool stm32wb_pwr_enablebkp(bool writable) } /**************************************************************************** - * Name: stm32wb_pwr_enableusv + * Name: stm32_pwr_enableusv * * Description: * Enables or disables the USB Supply Valid monitoring. Setting this bit @@ -125,14 +125,14 @@ bool stm32wb_pwr_enablebkp(bool writable) * ****************************************************************************/ -bool stm32wb_pwr_enableusv(bool set) +bool stm32_pwr_enableusv(bool set) { uint32_t regval; bool was_set; /* Get the current state of the STM32WB PWR control register 2 */ - regval = stm32wb_pwr_getreg(STM32_PWR_CR2_OFFSET); + regval = stm32_pwr_getreg(STM32_PWR_CR2_OFFSET); was_set = ((regval & PWR_CR2_USV) != 0); /* Enable or disable the ability to write */ @@ -142,14 +142,14 @@ bool stm32wb_pwr_enableusv(bool set) /* Disable the Vddusb monitoring */ regval &= ~PWR_CR2_USV; - stm32wb_pwr_putreg(STM32_PWR_CR2_OFFSET, regval); + stm32_pwr_putreg(STM32_PWR_CR2_OFFSET, regval); } else if (!was_set && set) { /* Enable the Vddusb monitoring */ regval |= PWR_CR2_USV; - stm32wb_pwr_putreg(STM32_PWR_CR2_OFFSET, regval); + stm32_pwr_putreg(STM32_PWR_CR2_OFFSET, regval); } return was_set; diff --git a/arch/arm/src/stm32wb/stm32wb_pwr.h b/arch/arm/src/stm32wb/stm32wb_pwr.h index e9dea014de0..9f2e517dc7c 100644 --- a/arch/arm/src/stm32wb/stm32wb_pwr.h +++ b/arch/arm/src/stm32wb/stm32wb_pwr.h @@ -54,7 +54,7 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_pwr_enablebkp + * Name: stm32_pwr_enablebkp * * Description: * Enables access to the backup domain (RTC registers, RTC backup data @@ -68,10 +68,10 @@ extern "C" * ****************************************************************************/ -bool stm32wb_pwr_enablebkp(bool writable); +bool stm32_pwr_enablebkp(bool writable); /**************************************************************************** - * Name: stm32wb_pwr_enableusv + * Name: stm32_pwr_enableusv * * Description: * Enables or disables the USB Supply Valid monitoring. Setting this bit @@ -86,7 +86,7 @@ bool stm32wb_pwr_enablebkp(bool writable); * ****************************************************************************/ -bool stm32wb_pwr_enableusv(bool set); +bool stm32_pwr_enableusv(bool set); /**************************************************************************** * Name: stm32_pwr_setvos diff --git a/arch/arm/src/stm32wb/stm32wb_rcc.c b/arch/arm/src/stm32wb/stm32wb_rcc.c index e731a9448e5..5a7bb4f22ba 100644 --- a/arch/arm/src/stm32wb/stm32wb_rcc.c +++ b/arch/arm/src/stm32wb/stm32wb_rcc.c @@ -504,7 +504,7 @@ static inline void rcc_enableccip(void) } /**************************************************************************** - * Name: stm32wb_stdclockconfig + * Name: stm32_stdclockconfig * * Description: * Called to change to new clock based on settings in board.h @@ -514,7 +514,7 @@ static inline void rcc_enableccip(void) ****************************************************************************/ #ifndef CONFIG_ARCH_BOARD_STM32WB_CUSTOM_CLOCKCONFIG -static void stm32wb_stdclockconfig(void) +static void stm32_stdclockconfig(void) { uint32_t regval; volatile int32_t timeout; @@ -604,7 +604,7 @@ static void stm32wb_stdclockconfig(void) } #else -# error stm32wb_stdclockconfig(), must have one of STM32_BOARD_USEHSI, STM32_BOARD_USEMSI, STM32_BOARD_USEHSE defined +# error stm32_stdclockconfig(), must have one of STM32_BOARD_USEHSI, STM32_BOARD_USEMSI, STM32_BOARD_USEHSE defined #endif @@ -789,7 +789,7 @@ static void stm32wb_stdclockconfig(void) #if defined(CONFIG_STM32WB_IWDG) || defined(CONFIG_STM32WB_RTC_LSICLOCK) /* Low speed internal clock source LSI */ - stm32wb_rcc_enable_lsi(); + stm32_rcc_enable_lsi(); #endif #if defined(STM32_USE_LSE) @@ -805,7 +805,7 @@ static void stm32wb_stdclockconfig(void) * this for automatically trimming MSI, etc. */ - stm32wb_rcc_enable_lse(); + stm32_rcc_enable_lse(); # if defined(STM32_BOARD_USEMSI) /* Now that LSE is up, auto trim the MSI */ @@ -846,7 +846,7 @@ static inline void rcc_enableperipherals(void) #ifdef STM32_USE_HSI48 /* Enable HSI48 clocking to support USB transfers or RNG */ - stm32wb_enable_hsi48(STM32_HSI48_SYNCSRC); + stm32_enable_hsi48(STM32_HSI48_SYNCSRC); #endif } @@ -878,7 +878,7 @@ static inline void rcc_resetbkp(void) /* Check if the RTC is already configured */ - init_stat = stm32wb_rtc_is_initialized(); + init_stat = stm32_rtc_is_initialized(); if (!init_stat) { uint32_t bkregs[STM32_RTC_BKCOUNT]; @@ -895,7 +895,7 @@ static inline void rcc_resetbkp(void) * backup data registers and backup SRAM). */ - stm32wb_pwr_enablebkp(true); + stm32_pwr_enablebkp(true); /* We might be changing RTCSEL - to ensure such changes work, we must * reset the backup domain (having backed up the RTC_MAGIC token) @@ -914,7 +914,7 @@ static inline void rcc_resetbkp(void) } } - stm32wb_pwr_enablebkp(false); + stm32_pwr_enablebkp(false); } } #else @@ -922,7 +922,7 @@ static inline void rcc_resetbkp(void) #endif /**************************************************************************** - * Name: stm32wb_clockconfig + * Name: stm32_clockconfig * * Description: * Called to establish the clock settings based on the values in board.h. @@ -932,7 +932,7 @@ static inline void rcc_resetbkp(void) * * If CONFIG_ARCH_BOARD_STM32WB_CUSTOM_CLOCKCONFIG is defined, then * clocking will be enabled by an externally provided, board-specific - * function called stm32wb_board_clockconfig(). + * function called stm32_board_clockconfig(). * * Input Parameters: * None @@ -942,7 +942,7 @@ static inline void rcc_resetbkp(void) * ****************************************************************************/ -void stm32wb_clockconfig(void) +void stm32_clockconfig(void) { /* Make sure that we are starting in the reset state */ @@ -956,7 +956,7 @@ void stm32wb_clockconfig(void) /* Invoke Board Custom Clock Configuration */ - stm32wb_board_clockconfig(); + stm32_board_clockconfig(); #else @@ -964,7 +964,7 @@ void stm32wb_clockconfig(void) * board.h */ - stm32wb_stdclockconfig(); + stm32_stdclockconfig(); #endif @@ -974,7 +974,7 @@ void stm32wb_clockconfig(void) } /**************************************************************************** - * Name: stm32wb_clockenable + * Name: stm32_clockenable * * Description: * Re-enable the clock and restore the clock settings based on settings in @@ -984,12 +984,12 @@ void stm32wb_clockconfig(void) * re-enable/re-start the PLL * * This functional performs a subset of the operations performed by - * stm32wb_clockconfig(): It does not reset any devices, and it does not + * stm32_clockconfig(): It does not reset any devices, and it does not * reset the currently enabled peripheral clocks. * * If CONFIG_ARCH_BOARD_STM32WB_CUSTOM_CLOCKCONFIG is defined, then * clocking will be enabled by an externally provided, board-specific - * function called stm32wb_board_clockconfig(). + * function called stm32_board_clockconfig(). * * Input Parameters: * None @@ -1000,13 +1000,13 @@ void stm32wb_clockconfig(void) ****************************************************************************/ #ifdef CONFIG_PM -void stm32wb_clockenable(void) +void stm32_clockenable(void) { #if defined(CONFIG_ARCH_BOARD_STM32WB_CUSTOM_CLOCKCONFIG) /* Invoke Board Custom Clock Configuration */ - stm32wb_board_clockconfig(); + stm32_board_clockconfig(); #else @@ -1014,7 +1014,7 @@ void stm32wb_clockenable(void) * board.h */ - stm32wb_stdclockconfig(); + stm32_stdclockconfig(); #endif } diff --git a/arch/arm/src/stm32wb/stm32wb_rcc.h b/arch/arm/src/stm32wb/stm32wb_rcc.h index e6e675a3534..a8cd788caeb 100644 --- a/arch/arm/src/stm32wb/stm32wb_rcc.h +++ b/arch/arm/src/stm32wb/stm32wb_rcc.h @@ -68,7 +68,7 @@ typedef enum crs_syncsrc_e crs_syncsrc_t; ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_mcoconfig + * Name: stm32_mcoconfig * * Description: * Selects the clock source to output and clock divider on MC pin @@ -84,7 +84,7 @@ typedef enum crs_syncsrc_e crs_syncsrc_t; * ****************************************************************************/ -static inline void stm32wb_mcoconfig(uint32_t source, uint32_t divider) +static inline void stm32_mcoconfig(uint32_t source, uint32_t divider) { uint32_t regval; @@ -107,7 +107,7 @@ static inline void stm32wb_mcoconfig(uint32_t source, uint32_t divider) ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_clockconfig + * Name: stm32_clockconfig * * Description: * Called to establish the clock settings based on the values in board.h. @@ -117,7 +117,7 @@ static inline void stm32wb_mcoconfig(uint32_t source, uint32_t divider) * * If CONFIG_ARCH_BOARD_STM32WB_CUSTOM_CLOCKCONFIG is defined, then * clocking will be enabled by an externally provided, board-specific - * function called stm32wb_board_clockconfig(). + * function called stm32_board_clockconfig(). * * Input Parameters: * None @@ -127,10 +127,10 @@ static inline void stm32wb_mcoconfig(uint32_t source, uint32_t divider) * ****************************************************************************/ -void stm32wb_clockconfig(void); +void stm32_clockconfig(void); /**************************************************************************** - * Name: stm32wb_board_clockconfig + * Name: stm32_board_clockconfig * * Description: * Any STM32WB board may replace the "standard" board clock configuration @@ -139,11 +139,11 @@ void stm32wb_clockconfig(void); ****************************************************************************/ #ifdef CONFIG_ARCH_BOARD_STM32WB_CUSTOM_CLOCKCONFIG -void stm32wb_board_clockconfig(void); +void stm32_board_clockconfig(void); #endif /**************************************************************************** - * Name: stm32wb_clockenable + * Name: stm32_clockenable * * Description: * Re-enable the clock and restore the clock settings based on settings in @@ -153,12 +153,12 @@ void stm32wb_board_clockconfig(void); * re-start the PLL * * This functional performs a subset of the operations performed by - * stm32wb_clockconfig(): It does not reset any devices, and it does not + * stm32_clockconfig(): It does not reset any devices, and it does not * reset the currently enabled peripheral clocks. * * If CONFIG_ARCH_BOARD_STM32WB_CUSTOM_CLOCKCONFIG is defined, then * clocking will be enabled by an externally provided, board-specific - * function called stm32wb_board_clockconfig(). + * function called stm32_board_clockconfig(). * * Input Parameters: * None @@ -169,11 +169,11 @@ void stm32wb_board_clockconfig(void); ****************************************************************************/ #ifdef CONFIG_PM -void stm32wb_clockenable(void); +void stm32_clockenable(void); #endif /**************************************************************************** - * Name: stm32wb_rcc_enable_lse + * Name: stm32_rcc_enable_lse * * Description: * Enable the External Low-Speed (LSE) Oscillator. @@ -186,30 +186,30 @@ void stm32wb_clockenable(void); * ****************************************************************************/ -void stm32wb_rcc_enable_lse(void); +void stm32_rcc_enable_lse(void); /**************************************************************************** - * Name: stm32wb_rcc_enable_lsi + * Name: stm32_rcc_enable_lsi * * Description: * Enable the Internal Low-Speed (LSI) RC Oscillator. * ****************************************************************************/ -void stm32wb_rcc_enable_lsi(void); +void stm32_rcc_enable_lsi(void); /**************************************************************************** - * Name: stm32wb_rcc_disable_lsi + * Name: stm32_rcc_disable_lsi * * Description: * Disable the Internal Low-Speed (LSI) RC Oscillator. * ****************************************************************************/ -void stm32wb_rcc_disable_lsi(void); +void stm32_rcc_disable_lsi(void); /**************************************************************************** - * Name: stm32wb_rcc_enable_hsi48 + * Name: stm32_rcc_enable_hsi48 * * Description: * HSI48 clock signal is generated from an internal 48 MHz RC oscillator @@ -235,10 +235,10 @@ void stm32wb_rcc_disable_lsi(void); * ****************************************************************************/ -void stm32wb_rcc_enable_hsi48(crs_syncsrc_t syncsrc); +void stm32_rcc_enable_hsi48(crs_syncsrc_t syncsrc); /**************************************************************************** - * Name: stm32wb_rcc_disable_hsi48 + * Name: stm32_rcc_disable_hsi48 * * Description: * Disable the HSI48 clock. @@ -251,7 +251,7 @@ void stm32wb_rcc_enable_hsi48(crs_syncsrc_t syncsrc); * ****************************************************************************/ -void stm32wb_rcc_disable_hsi48(void); +void stm32_rcc_disable_hsi48(void); #undef EXTERN #if defined(__cplusplus) diff --git a/arch/arm/src/stm32wb/stm32wb_rcc_hsi48.c b/arch/arm/src/stm32wb/stm32wb_rcc_hsi48.c index abdb78b4b44..c3276e6d236 100644 --- a/arch/arm/src/stm32wb/stm32wb_rcc_hsi48.c +++ b/arch/arm/src/stm32wb/stm32wb_rcc_hsi48.c @@ -35,7 +35,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_rcc_enable_hsi48 + * Name: stm32_rcc_enable_hsi48 * * Description: * HSI48 clock signal is generated from an internal 48 MHz RC oscillator @@ -61,7 +61,7 @@ * ****************************************************************************/ -void stm32wb_rcc_enable_hsi48(crs_syncsrc_t syncsrc) +void stm32_rcc_enable_hsi48(crs_syncsrc_t syncsrc) { uint32_t regval; @@ -130,7 +130,7 @@ void stm32wb_rcc_enable_hsi48(crs_syncsrc_t syncsrc) } /**************************************************************************** - * Name: stm32wb_rcc_disable_hsi48 + * Name: stm32_rcc_disable_hsi48 * * Description: * Disable the HSI48 clock. @@ -143,7 +143,7 @@ void stm32wb_rcc_enable_hsi48(crs_syncsrc_t syncsrc) * ****************************************************************************/ -void stm32wb_rcc_disable_hsi48(void) +void stm32_rcc_disable_hsi48(void) { uint32_t regval; diff --git a/arch/arm/src/stm32wb/stm32wb_rcc_lse.c b/arch/arm/src/stm32wb/stm32wb_rcc_lse.c index e032a1a1c6d..1e56d0e3cd8 100644 --- a/arch/arm/src/stm32wb/stm32wb_rcc_lse.c +++ b/arch/arm/src/stm32wb/stm32wb_rcc_lse.c @@ -54,14 +54,14 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_rcc_enable_lse + * Name: stm32_rcc_enable_lse * * Description: * Enable the External Low-Speed (LSE) oscillator. * ****************************************************************************/ -void stm32wb_rcc_enable_lse(void) +void stm32_rcc_enable_lse(void) { bool writable; uint32_t regval; @@ -78,7 +78,7 @@ void stm32wb_rcc_enable_lse(void) * in the PWR CR register before to configuring the LSE. */ - writable = stm32wb_pwr_enablebkp(true); + writable = stm32_pwr_enablebkp(true); /* Enable the External Low-Speed (LSE) oscillator by setting the * LSEON bit the RCC BDCR register. @@ -100,7 +100,7 @@ void stm32wb_rcc_enable_lse(void) while (((regval = getreg32(STM32_RCC_BDCR)) & RCC_BDCR_LSERDY) == 0) { - stm32wb_waste(); + stm32_waste(); } #if defined(CONFIG_STM32WB_RTC_LSECLOCK_RUN_DRV_CAPABILITY) && \ @@ -121,6 +121,6 @@ void stm32wb_rcc_enable_lse(void) /* Disable backup domain access if it was disabled on entry */ - stm32wb_pwr_enablebkp(writable); + stm32_pwr_enablebkp(writable); } } diff --git a/arch/arm/src/stm32wb/stm32wb_rcc_lsi.c b/arch/arm/src/stm32wb/stm32wb_rcc_lsi.c index 9fa23cfc73a..7dcdc39a50b 100644 --- a/arch/arm/src/stm32wb/stm32wb_rcc_lsi.c +++ b/arch/arm/src/stm32wb/stm32wb_rcc_lsi.c @@ -34,14 +34,14 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_rcc_enable_lsi + * Name: stm32_rcc_enable_lsi * * Description: * Enable the Internal Low-Speed (LSI) RC Oscillator. * ****************************************************************************/ -void stm32wb_rcc_enable_lsi(void) +void stm32_rcc_enable_lsi(void) { /* Enable the Internal Low-Speed (LSI) RC Oscillator by setting the LSION * bit the RCC CSR register. @@ -55,14 +55,14 @@ void stm32wb_rcc_enable_lsi(void) } /**************************************************************************** - * Name: stm32wb_rcc_disable_lsi + * Name: stm32_rcc_disable_lsi * * Description: * Disable the Internal Low-Speed (LSI) RC Oscillator. * ****************************************************************************/ -void stm32wb_rcc_disable_lsi(void) +void stm32_rcc_disable_lsi(void) { /* Enable the Internal Low-Speed (LSI) RC Oscillator by setting the LSION * bit the RCC CSR register. diff --git a/arch/arm/src/stm32wb/stm32wb_rtc.c b/arch/arm/src/stm32wb/stm32wb_rtc.c index 78c793ef038..2b849fd12c2 100644 --- a/arch/arm/src/stm32wb/stm32wb_rtc.c +++ b/arch/arm/src/stm32wb/stm32wb_rtc.c @@ -199,7 +199,7 @@ static void rtc_wprunlock(void) { /* Enable write access to the backup domain. */ - stm32wb_pwr_enablebkp(true); + stm32_pwr_enablebkp(true); /* The following steps are required to unlock the write protection on * all the RTC registers (except for RTC_ISR[13:8], RTC_TAFCR, and @@ -237,7 +237,7 @@ static inline void rtc_wprlock(void) /* Disable write access to the backup domain. */ - stm32wb_pwr_enablebkp(false); + stm32_pwr_enablebkp(false); } /**************************************************************************** @@ -436,7 +436,7 @@ static void rtc_resume(void) } /**************************************************************************** - * Name: stm32wb_rtc_alarm_handler + * Name: stm32_rtc_alarm_handler * * Description: * RTC ALARM interrupt service routine through the EXTI line @@ -451,7 +451,7 @@ static void rtc_resume(void) ****************************************************************************/ #ifdef CONFIG_RTC_ALARM -static int stm32wb_rtc_alarm_handler(int irq, void *context, +static int stm32_rtc_alarm_handler(int irq, void *context, void *rtc_handler_arg) { struct alm_cbinfo_s *cbinfo; @@ -465,7 +465,7 @@ static int stm32wb_rtc_alarm_handler(int irq, void *context, * backup data registers and backup SRAM). */ - stm32wb_pwr_enablebkp(true); + stm32_pwr_enablebkp(true); /* Check for EXTI from Alarm A or B and handle according */ @@ -531,7 +531,7 @@ static int stm32wb_rtc_alarm_handler(int irq, void *context, * data registers and backup SRAM). */ - stm32wb_pwr_enablebkp(false); + stm32_pwr_enablebkp(false); return ret; } @@ -737,14 +737,14 @@ static inline void rtc_enable_alarm(void) * 3. Configure the RTC to generate RTC alarms (Alarm A or Alarm B). */ - stm32wb_exti_alarm(true, false, true, stm32wb_rtc_alarm_handler, NULL); + stm32_exti_alarm(true, false, true, stm32_rtc_alarm_handler, NULL); g_alarm_enabled = true; } } #endif /**************************************************************************** - * Name: stm32wb_rtc_getalarmdatetime + * Name: stm32_rtc_getalarmdatetime * * Description: * Get the current date and time for a RTC alarm. @@ -759,7 +759,7 @@ static inline void rtc_enable_alarm(void) ****************************************************************************/ #ifdef CONFIG_RTC_ALARM -static int stm32wb_rtc_getalarmdatetime(rtc_alarmreg_t reg, +static int stm32_rtc_getalarmdatetime(rtc_alarmreg_t reg, struct tm *tp) { uint32_t data; @@ -800,7 +800,7 @@ static int stm32wb_rtc_getalarmdatetime(rtc_alarmreg_t reg, ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_rtc_is_initialized + * Name: stm32_rtc_is_initialized * * Description: * Returns 'true' if the RTC has been initialized @@ -816,7 +816,7 @@ static int stm32wb_rtc_getalarmdatetime(rtc_alarmreg_t reg, * ****************************************************************************/ -bool stm32wb_rtc_is_initialized(void) +bool stm32_rtc_is_initialized(void) { uint32_t regval; @@ -851,14 +851,14 @@ int up_rtc_initialize(void) * backed, we don't need or want to re-initialize on each reset. */ - init_stat = stm32wb_rtc_is_initialized(); + init_stat = stm32_rtc_is_initialized(); if (!init_stat) { /* Enable write access to the backup domain (RTC registers, RTC * backup data registers and backup SRAM). */ - stm32wb_pwr_enablebkp(true); + stm32_pwr_enablebkp(true); #if defined(CONFIG_STM32WB_RTC_HSECLOCK) modifyreg32(STM32_RCC_BDCR, RCC_BDCR_RTCSEL_MASK, @@ -893,7 +893,7 @@ int up_rtc_initialize(void) * RTC backup data registers and backup SRAM). */ - stm32wb_pwr_enablebkp(false); + stm32_pwr_enablebkp(false); rtc_dumpregs("After Failed Initialization"); @@ -960,7 +960,7 @@ int up_rtc_initialize(void) * RTC backup data registers and backup SRAM). */ - stm32wb_pwr_enablebkp(false); + stm32_pwr_enablebkp(false); } } else @@ -969,7 +969,7 @@ int up_rtc_initialize(void) * backup data registers and backup SRAM). */ - stm32wb_pwr_enablebkp(true); + stm32_pwr_enablebkp(true); /* Write protection for RTC registers does not need to be disabled. */ @@ -979,7 +979,7 @@ int up_rtc_initialize(void) * data registers and backup SRAM). */ - stm32wb_pwr_enablebkp(false); + stm32_pwr_enablebkp(false); } g_rtc_enabled = true; @@ -989,7 +989,7 @@ int up_rtc_initialize(void) } /**************************************************************************** - * Name: stm32wb_rtc_getdatetime_with_subseconds + * Name: stm32_rtc_getdatetime_with_subseconds * * Description: * Get the current date and time from the date/time RTC. This interface @@ -1009,7 +1009,7 @@ int up_rtc_initialize(void) * ****************************************************************************/ -int stm32wb_rtc_getdatetime_with_subseconds(struct tm *tp, +int stm32_rtc_getdatetime_with_subseconds(struct tm *tp, long *nsec) { #ifdef CONFIG_STM32WB_HAVE_RTC_SUBSECONDS @@ -1140,7 +1140,7 @@ int stm32wb_rtc_getdatetime_with_subseconds(struct tm *tp, int up_rtc_getdatetime(struct tm *tp) { - return stm32wb_rtc_getdatetime_with_subseconds(tp, NULL); + return stm32_rtc_getdatetime_with_subseconds(tp, NULL); } /**************************************************************************** @@ -1174,12 +1174,12 @@ int up_rtc_getdatetime(struct tm *tp) # endif int up_rtc_getdatetime_with_subseconds(struct tm *tp, long *nsec) { - return stm32wb_rtc_getdatetime_with_subseconds(tp, nsec); + return stm32_rtc_getdatetime_with_subseconds(tp, nsec); } #endif /**************************************************************************** - * Name: stm32wb_rtc_setdatetime + * Name: stm32_rtc_setdatetime * * Description: * Set the RTC to the provided time. RTC implementations which provide @@ -1194,7 +1194,7 @@ int up_rtc_getdatetime_with_subseconds(struct tm *tp, long *nsec) * ****************************************************************************/ -int stm32wb_rtc_setdatetime(const struct tm *tp) +int stm32_rtc_setdatetime(const struct tm *tp) { uint32_t tr; uint32_t dr; @@ -1257,9 +1257,9 @@ int stm32wb_rtc_setdatetime(const struct tm *tp) if (getreg32(RTC_MAGIC_REG) != RTC_MAGIC_TIME_SET) { - stm32wb_pwr_enablebkp(true); + stm32_pwr_enablebkp(true); putreg32(RTC_MAGIC_TIME_SET, RTC_MAGIC_REG); - stm32wb_pwr_enablebkp(false); + stm32_pwr_enablebkp(false); } /* Re-enable the write protection for RTC registers */ @@ -1270,7 +1270,7 @@ int stm32wb_rtc_setdatetime(const struct tm *tp) } /**************************************************************************** - * Name: stm32wb_rtc_havesettime + * Name: stm32_rtc_havesettime * * Description: * Check if RTC time has been set. @@ -1280,7 +1280,7 @@ int stm32wb_rtc_setdatetime(const struct tm *tp) * ****************************************************************************/ -bool stm32wb_rtc_havesettime(void) +bool stm32_rtc_havesettime(void) { return getreg32(RTC_MAGIC_REG) == RTC_MAGIC_TIME_SET; } @@ -1309,11 +1309,11 @@ int up_rtc_settime(const struct timespec *tp) */ gmtime_r(&tp->tv_sec, &newtime); - return stm32wb_rtc_setdatetime(&newtime); + return stm32_rtc_setdatetime(&newtime); } /**************************************************************************** - * Name: stm32wb_rtc_setalarm + * Name: stm32_rtc_setalarm * * Description: * Set an alarm to an absolute time using associated hardware. @@ -1327,7 +1327,7 @@ int up_rtc_settime(const struct timespec *tp) ****************************************************************************/ #ifdef CONFIG_RTC_ALARM -int stm32wb_rtc_setalarm(struct alm_setalarm_s *alminfo) +int stm32_rtc_setalarm(struct alm_setalarm_s *alminfo) { struct alm_cbinfo_s *cbinfo; rtc_alarmreg_t alarmreg; @@ -1402,7 +1402,7 @@ int stm32wb_rtc_setalarm(struct alm_setalarm_s *alminfo) #endif /**************************************************************************** - * Name: stm32wb_rtc_cancelalarm + * Name: stm32_rtc_cancelalarm * * Description: * Cancel an alarm. @@ -1416,7 +1416,7 @@ int stm32wb_rtc_setalarm(struct alm_setalarm_s *alminfo) ****************************************************************************/ #ifdef CONFIG_RTC_ALARM -int stm32wb_rtc_cancelalarm(enum alm_id_e alarmid) +int stm32_rtc_cancelalarm(enum alm_id_e alarmid) { int ret = -EINVAL; @@ -1502,7 +1502,7 @@ errout_with_wprunlock: #endif /**************************************************************************** - * Name: stm32wb_rtc_rdalarm + * Name: stm32_rtc_rdalarm * * Description: * Query an alarm configured in hardware. @@ -1516,7 +1516,7 @@ errout_with_wprunlock: ****************************************************************************/ #ifdef CONFIG_RTC_ALARM -int stm32wb_rtc_rdalarm(struct alm_rdalarm_s *alminfo) +int stm32_rtc_rdalarm(struct alm_rdalarm_s *alminfo) { rtc_alarmreg_t alarmreg; int ret = -EINVAL; @@ -1529,7 +1529,7 @@ int stm32wb_rtc_rdalarm(struct alm_rdalarm_s *alminfo) case RTC_ALARMA: { alarmreg = STM32_RTC_ALRMAR; - ret = stm32wb_rtc_getalarmdatetime(alarmreg, + ret = stm32_rtc_getalarmdatetime(alarmreg, (struct tm *)alminfo->ar_time); } break; @@ -1538,7 +1538,7 @@ int stm32wb_rtc_rdalarm(struct alm_rdalarm_s *alminfo) case RTC_ALARMB: { alarmreg = STM32_RTC_ALRMBR; - ret = stm32wb_rtc_getalarmdatetime(alarmreg, + ret = stm32_rtc_getalarmdatetime(alarmreg, (struct tm *)alminfo->ar_time); } break; @@ -1554,7 +1554,7 @@ int stm32wb_rtc_rdalarm(struct alm_rdalarm_s *alminfo) #endif /**************************************************************************** - * Name: stm32wb_rtc_wakeup_handler + * Name: stm32_rtc_wakeup_handler * * Description: * RTC WAKEUP interrupt service routine through the EXTI line @@ -1568,17 +1568,17 @@ int stm32wb_rtc_rdalarm(struct alm_rdalarm_s *alminfo) ****************************************************************************/ #ifdef CONFIG_RTC_PERIODIC -static int stm32wb_rtc_wakeup_handler(int irq, void *context, void *arg) +static int stm32_rtc_wakeup_handler(int irq, void *context, void *arg) { uint32_t regval = 0; - stm32wb_pwr_enablebkp(true); + stm32_pwr_enablebkp(true); regval = getreg32(STM32_RTC_ISR); regval &= ~RTC_ISR_WUTF; putreg32(regval, STM32_RTC_ISR); - stm32wb_pwr_enablebkp(false); + stm32_pwr_enablebkp(false); if (g_wakeupcb != NULL) { @@ -1602,7 +1602,7 @@ static inline void rtc_enable_wakeup(void) { if (!g_wakeup_enabled) { - stm32wb_exti_wakeup(true, false, true, stm32wb_rtc_wakeup_handler, + stm32_exti_wakeup(true, false, true, stm32_rtc_wakeup_handler, NULL); g_wakeup_enabled = true; } @@ -1630,7 +1630,7 @@ static inline void rtc_set_wcksel(unsigned int wucksel) #endif /**************************************************************************** - * Name: stm32wb_rtc_setperiodic + * Name: stm32_rtc_setperiodic * * Description: * Set a periodic RTC wakeup @@ -1645,7 +1645,7 @@ static inline void rtc_set_wcksel(unsigned int wucksel) ****************************************************************************/ #ifdef CONFIG_RTC_PERIODIC -int stm32wb_rtc_setperiodic(const struct timespec *period, +int stm32_rtc_setperiodic(const struct timespec *period, wakeupcb_t callback) { unsigned int wutr_val; @@ -1774,7 +1774,7 @@ int stm32wb_rtc_setperiodic(const struct timespec *period, #endif /**************************************************************************** - * Name: stm32wb_rtc_cancelperiodic + * Name: stm32_rtc_cancelperiodic * * Description: * Cancel a periodic wakeup @@ -1787,7 +1787,7 @@ int stm32wb_rtc_setperiodic(const struct timespec *period, ****************************************************************************/ #ifdef CONFIG_RTC_PERIODIC -int stm32wb_rtc_cancelperiodic(void) +int stm32_rtc_cancelperiodic(void) { int ret = OK; int timeout = 0; diff --git a/arch/arm/src/stm32wb/stm32wb_rtc.h b/arch/arm/src/stm32wb/stm32wb_rtc.h index b83811499da..65a8edf5387 100644 --- a/arch/arm/src/stm32wb/stm32wb_rtc.h +++ b/arch/arm/src/stm32wb/stm32wb_rtc.h @@ -120,7 +120,7 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_rtc_is_initialized + * Name: stm32_rtc_is_initialized * * Description: * Returns 'true' if the RTC has been initialized @@ -135,10 +135,10 @@ extern "C" * ****************************************************************************/ -bool stm32wb_rtc_is_initialized(void); +bool stm32_rtc_is_initialized(void); /**************************************************************************** - * Name: stm32wb_rtc_getdatetime_with_subseconds + * Name: stm32_rtc_getdatetime_with_subseconds * * Description: * Get the current date and time from the date/time RTC. This interface @@ -159,11 +159,11 @@ bool stm32wb_rtc_is_initialized(void); ****************************************************************************/ #ifdef CONFIG_STM32WB_HAVE_RTC_SUBSECONDS -int stm32wb_rtc_getdatetime_with_subseconds(struct tm *tp, long *nsec); +int stm32_rtc_getdatetime_with_subseconds(struct tm *tp, long *nsec); #endif /**************************************************************************** - * Name: stm32wb_rtc_setdatetime + * Name: stm32_rtc_setdatetime * * Description: * Set the RTC to the provided time. RTC implementations which provide @@ -180,11 +180,11 @@ int stm32wb_rtc_getdatetime_with_subseconds(struct tm *tp, long *nsec); #ifdef CONFIG_RTC_DATETIME struct tm; -int stm32wb_rtc_setdatetime(const struct tm *tp); +int stm32_rtc_setdatetime(const struct tm *tp); #endif /**************************************************************************** - * Name: stm32wb_rtc_havesettime + * Name: stm32_rtc_havesettime * * Description: * Check if RTC time has been set. @@ -194,11 +194,11 @@ int stm32wb_rtc_setdatetime(const struct tm *tp); * ****************************************************************************/ -bool stm32wb_rtc_havesettime(void); +bool stm32_rtc_havesettime(void); #ifdef CONFIG_RTC_ALARM /**************************************************************************** - * Name: stm32wb_rtc_setalarm + * Name: stm32_rtc_setalarm * * Description: * Set an alarm to an absolute time using associated hardware. @@ -211,10 +211,10 @@ bool stm32wb_rtc_havesettime(void); * ****************************************************************************/ -int stm32wb_rtc_setalarm(struct alm_setalarm_s *alminfo); +int stm32_rtc_setalarm(struct alm_setalarm_s *alminfo); /**************************************************************************** - * Name: stm32wb_rtc_rdalarm + * Name: stm32_rtc_rdalarm * * Description: * Query an alarm configured in hardware. @@ -227,10 +227,10 @@ int stm32wb_rtc_setalarm(struct alm_setalarm_s *alminfo); * ****************************************************************************/ -int stm32wb_rtc_rdalarm(struct alm_rdalarm_s *alminfo); +int stm32_rtc_rdalarm(struct alm_rdalarm_s *alminfo); /**************************************************************************** - * Name: stm32wb_rtc_cancelalarm + * Name: stm32_rtc_cancelalarm * * Description: * Cancel an alarm. @@ -243,13 +243,13 @@ int stm32wb_rtc_rdalarm(struct alm_rdalarm_s *alminfo); * ****************************************************************************/ -int stm32wb_rtc_cancelalarm(enum alm_id_e alarmid); +int stm32_rtc_cancelalarm(enum alm_id_e alarmid); #endif /* CONFIG_RTC_ALARM */ #ifdef CONFIG_RTC_PERIODIC /**************************************************************************** - * Name: stm32wb_rtc_setperiodic + * Name: stm32_rtc_setperiodic * * Description: * Set a periodic RTC wakeup @@ -263,11 +263,11 @@ int stm32wb_rtc_cancelalarm(enum alm_id_e alarmid); * ****************************************************************************/ -int stm32wb_rtc_setperiodic(const struct timespec *period, +int stm32_rtc_setperiodic(const struct timespec *period, wakeupcb_t callback); /**************************************************************************** - * Name: stm32wb_rtc_cancelperiodic + * Name: stm32_rtc_cancelperiodic * * Description: * Cancel a periodic wakeup @@ -279,11 +279,11 @@ int stm32wb_rtc_setperiodic(const struct timespec *period, * ****************************************************************************/ -int stm32wb_rtc_cancelperiodic(void); +int stm32_rtc_cancelperiodic(void); #endif /* CONFIG_RTC_PERIODIC */ /**************************************************************************** - * Name: stm32wb_rtc_lowerhalf + * Name: stm32_rtc_lowerhalf * * Description: * Instantiate the RTC lower half driver for the STM32WB. General usage: @@ -292,7 +292,7 @@ int stm32wb_rtc_cancelperiodic(void); * #include "stm32wb_rtc.h> * * struct rtc_lowerhalf_s *lower; - * lower = stm32wb_rtc_lowerhalf(); + * lower = stm32_rtc_lowerhalf(); * rtc_initialize(0, lower); * * Input Parameters: @@ -306,7 +306,7 @@ int stm32wb_rtc_cancelperiodic(void); #ifdef CONFIG_RTC_DRIVER struct rtc_lowerhalf_s; -struct rtc_lowerhalf_s *stm32wb_rtc_lowerhalf(void); +struct rtc_lowerhalf_s *stm32_rtc_lowerhalf(void); #endif #undef EXTERN diff --git a/arch/arm/src/stm32wb/stm32wb_rtc_lowerhalf.c b/arch/arm/src/stm32wb/stm32wb_rtc_lowerhalf.c index 16fc6ea8558..fca4009e4bf 100644 --- a/arch/arm/src/stm32wb/stm32wb_rtc_lowerhalf.c +++ b/arch/arm/src/stm32wb/stm32wb_rtc_lowerhalf.c @@ -52,7 +52,7 @@ ****************************************************************************/ #ifdef CONFIG_RTC_ALARM -struct stm32wb_cbinfo_s +struct stm32_cbinfo_s { volatile rtc_alarm_callback_t cb; /* Callback when the alarm expires */ volatile void *priv; /* Private argument for callback */ @@ -64,7 +64,7 @@ struct stm32wb_cbinfo_s * with struct rtc_lowerhalf_s. */ -struct stm32wb_lowerhalf_s +struct stm32_lowerhalf_s { /* This is the contained reference to the read-only, lower-half * operations vtable (which may lie in FLASH or ROM) @@ -81,7 +81,7 @@ struct stm32wb_lowerhalf_s #ifdef CONFIG_RTC_ALARM /* Alarm callback information */ - struct stm32wb_cbinfo_s cbinfo[STM32_NALARMS]; + struct stm32_cbinfo_s cbinfo[STM32_NALARMS]; #endif #ifdef CONFIG_RTC_PERIODIC @@ -97,29 +97,29 @@ struct stm32wb_lowerhalf_s /* Prototypes for static methods in struct rtc_ops_s */ -static int stm32wb_rdtime(struct rtc_lowerhalf_s *lower, +static int stm32_rdtime(struct rtc_lowerhalf_s *lower, struct rtc_time *rtctime); -static int stm32wb_settime(struct rtc_lowerhalf_s *lower, +static int stm32_settime(struct rtc_lowerhalf_s *lower, const struct rtc_time *rtctime); -static bool stm32wb_havesettime(struct rtc_lowerhalf_s *lower); +static bool stm32_havesettime(struct rtc_lowerhalf_s *lower); #ifdef CONFIG_RTC_ALARM -static int stm32wb_setalarm(struct rtc_lowerhalf_s *lower, +static int stm32_setalarm(struct rtc_lowerhalf_s *lower, const struct lower_setalarm_s *alarminfo); static int -stm32wb_setrelative(struct rtc_lowerhalf_s *lower, +stm32_setrelative(struct rtc_lowerhalf_s *lower, const struct lower_setrelative_s *alarminfo); -static int stm32wb_cancelalarm(struct rtc_lowerhalf_s *lower, int alarmid); -static int stm32wb_rdalarm(struct rtc_lowerhalf_s *lower, +static int stm32_cancelalarm(struct rtc_lowerhalf_s *lower, int alarmid); +static int stm32_rdalarm(struct rtc_lowerhalf_s *lower, struct lower_rdalarm_s *alarminfo); #endif #ifdef CONFIG_RTC_PERIODIC static int -stm32wb_setperiodic(struct rtc_lowerhalf_s *lower, +stm32_setperiodic(struct rtc_lowerhalf_s *lower, const struct lower_setperiodic_s *alarminfo); static int -stm32wb_cancelperiodic(struct rtc_lowerhalf_s *lower, int id); +stm32_cancelperiodic(struct rtc_lowerhalf_s *lower, int id); #endif /**************************************************************************** @@ -130,24 +130,24 @@ stm32wb_cancelperiodic(struct rtc_lowerhalf_s *lower, int id); static const struct rtc_ops_s g_rtc_ops = { - .rdtime = stm32wb_rdtime, - .settime = stm32wb_settime, - .havesettime = stm32wb_havesettime, + .rdtime = stm32_rdtime, + .settime = stm32_settime, + .havesettime = stm32_havesettime, #ifdef CONFIG_RTC_ALARM - .setalarm = stm32wb_setalarm, - .setrelative = stm32wb_setrelative, - .cancelalarm = stm32wb_cancelalarm, - .rdalarm = stm32wb_rdalarm, + .setalarm = stm32_setalarm, + .setrelative = stm32_setrelative, + .cancelalarm = stm32_cancelalarm, + .rdalarm = stm32_rdalarm, #endif #ifdef CONFIG_RTC_PERIODIC - .setperiodic = stm32wb_setperiodic, - .cancelperiodic = stm32wb_cancelperiodic, + .setperiodic = stm32_setperiodic, + .cancelperiodic = stm32_cancelperiodic, #endif }; /* STM32WB RTC device state */ -static struct stm32wb_lowerhalf_s g_rtc_lowerhalf = +static struct stm32_lowerhalf_s g_rtc_lowerhalf = { .ops = &g_rtc_ops, .devlock = NXMUTEX_INITIALIZER, @@ -158,7 +158,7 @@ static struct stm32wb_lowerhalf_s g_rtc_lowerhalf = ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_alarm_callback + * Name: stm32_alarm_callback * * Description: * This is the function that is called from the RTC driver when the alarm @@ -173,17 +173,17 @@ static struct stm32wb_lowerhalf_s g_rtc_lowerhalf = ****************************************************************************/ #ifdef CONFIG_RTC_ALARM -static void stm32wb_alarm_callback(void *arg, unsigned int alarmid) +static void stm32_alarm_callback(void *arg, unsigned int alarmid) { - struct stm32wb_lowerhalf_s *lower; - struct stm32wb_cbinfo_s *cbinfo; + struct stm32_lowerhalf_s *lower; + struct stm32_cbinfo_s *cbinfo; rtc_alarm_callback_t cb; void *priv; DEBUGASSERT(arg != NULL); DEBUGASSERT(alarmid == RTC_ALARMA || alarmid == RTC_ALARMB); - lower = (struct stm32wb_lowerhalf_s *)arg; + lower = (struct stm32_lowerhalf_s *)arg; cbinfo = &lower->cbinfo[alarmid]; /* Sample and clear the callback information to minimize the window in @@ -206,7 +206,7 @@ static void stm32wb_alarm_callback(void *arg, unsigned int alarmid) #endif /* CONFIG_RTC_ALARM */ /**************************************************************************** - * Name: stm32wb_rdtime + * Name: stm32_rdtime * * Description: * Implements the rdtime() method of the RTC driver interface @@ -221,13 +221,13 @@ static void stm32wb_alarm_callback(void *arg, unsigned int alarmid) * ****************************************************************************/ -static int stm32wb_rdtime(struct rtc_lowerhalf_s *lower, +static int stm32_rdtime(struct rtc_lowerhalf_s *lower, struct rtc_time *rtctime) { - struct stm32wb_lowerhalf_s *priv; + struct stm32_lowerhalf_s *priv; int ret; - priv = (struct stm32wb_lowerhalf_s *)lower; + priv = (struct stm32_lowerhalf_s *)lower; ret = nxmutex_lock(&priv->devlock); if (ret < 0) @@ -246,7 +246,7 @@ static int stm32wb_rdtime(struct rtc_lowerhalf_s *lower, } /**************************************************************************** - * Name: stm32wb_settime + * Name: stm32_settime * * Description: * Implements the settime() method of the RTC driver interface @@ -261,13 +261,13 @@ static int stm32wb_rdtime(struct rtc_lowerhalf_s *lower, * ****************************************************************************/ -static int stm32wb_settime(struct rtc_lowerhalf_s *lower, +static int stm32_settime(struct rtc_lowerhalf_s *lower, const struct rtc_time *rtctime) { - struct stm32wb_lowerhalf_s *priv; + struct stm32_lowerhalf_s *priv; int ret; - priv = (struct stm32wb_lowerhalf_s *)lower; + priv = (struct stm32_lowerhalf_s *)lower; ret = nxmutex_lock(&priv->devlock); if (ret < 0) @@ -279,14 +279,14 @@ static int stm32wb_settime(struct rtc_lowerhalf_s *lower, * compatible with struct tm. */ - ret = stm32wb_rtc_setdatetime((const struct tm *)rtctime); + ret = stm32_rtc_setdatetime((const struct tm *)rtctime); nxmutex_unlock(&priv->devlock); return ret; } /**************************************************************************** - * Name: stm32wb_havesettime + * Name: stm32_havesettime * * Description: * Implements the havesettime() method of the RTC driver interface @@ -299,13 +299,13 @@ static int stm32wb_settime(struct rtc_lowerhalf_s *lower, * ****************************************************************************/ -static bool stm32wb_havesettime(struct rtc_lowerhalf_s *lower) +static bool stm32_havesettime(struct rtc_lowerhalf_s *lower) { - return stm32wb_rtc_havesettime(); + return stm32_rtc_havesettime(); } /**************************************************************************** - * Name: stm32wb_setalarm + * Name: stm32_setalarm * * Description: * Set a new alarm. This function implements the setalarm() method of the @@ -322,11 +322,11 @@ static bool stm32wb_havesettime(struct rtc_lowerhalf_s *lower) ****************************************************************************/ #ifdef CONFIG_RTC_ALARM -static int stm32wb_setalarm(struct rtc_lowerhalf_s *lower, +static int stm32_setalarm(struct rtc_lowerhalf_s *lower, const struct lower_setalarm_s *alarminfo) { - struct stm32wb_lowerhalf_s *priv; - struct stm32wb_cbinfo_s *cbinfo; + struct stm32_lowerhalf_s *priv; + struct stm32_cbinfo_s *cbinfo; struct alm_setalarm_s lowerinfo; int ret; @@ -334,7 +334,7 @@ static int stm32wb_setalarm(struct rtc_lowerhalf_s *lower, DEBUGASSERT(lower != NULL && alarminfo != NULL); DEBUGASSERT(alarminfo->id == RTC_ALARMA || alarminfo->id == RTC_ALARMB); - priv = (struct stm32wb_lowerhalf_s *)lower; + priv = (struct stm32_lowerhalf_s *)lower; ret = nxmutex_lock(&priv->devlock); if (ret < 0) @@ -355,13 +355,13 @@ static int stm32wb_setalarm(struct rtc_lowerhalf_s *lower, /* Set the alarm */ lowerinfo.as_id = alarminfo->id; - lowerinfo.as_cb = stm32wb_alarm_callback; + lowerinfo.as_cb = stm32_alarm_callback; lowerinfo.as_arg = priv; memcpy(&lowerinfo.as_time, &alarminfo->time, sizeof(struct tm)); /* And set the alarm */ - ret = stm32wb_rtc_setalarm(&lowerinfo); + ret = stm32_rtc_setalarm(&lowerinfo); if (ret < 0) { cbinfo->cb = NULL; @@ -375,7 +375,7 @@ static int stm32wb_setalarm(struct rtc_lowerhalf_s *lower, #endif /**************************************************************************** - * Name: stm32wb_setrelative + * Name: stm32_setrelative * * Description: * Set a new alarm relative to the current time. This function implements @@ -393,7 +393,7 @@ static int stm32wb_setalarm(struct rtc_lowerhalf_s *lower, #ifdef CONFIG_RTC_ALARM static int -stm32wb_setrelative(struct rtc_lowerhalf_s *lower, +stm32_setrelative(struct rtc_lowerhalf_s *lower, const struct lower_setrelative_s *alarminfo) { struct lower_setalarm_s setalarm; @@ -439,7 +439,7 @@ stm32wb_setrelative(struct rtc_lowerhalf_s *lower, setalarm.cb = alarminfo->cb; setalarm.priv = alarminfo->priv; - ret = stm32wb_setalarm(lower, &setalarm); + ret = stm32_setalarm(lower, &setalarm); } leave_critical_section(flags); @@ -450,7 +450,7 @@ stm32wb_setrelative(struct rtc_lowerhalf_s *lower, #endif /**************************************************************************** - * Name: stm32wb_cancelalarm + * Name: stm32_cancelalarm * * Description: * Cancel the current alarm. This function implements the cancelalarm() @@ -467,15 +467,15 @@ stm32wb_setrelative(struct rtc_lowerhalf_s *lower, ****************************************************************************/ #ifdef CONFIG_RTC_ALARM -static int stm32wb_cancelalarm(struct rtc_lowerhalf_s *lower, int alarmid) +static int stm32_cancelalarm(struct rtc_lowerhalf_s *lower, int alarmid) { - struct stm32wb_lowerhalf_s *priv; - struct stm32wb_cbinfo_s *cbinfo; + struct stm32_lowerhalf_s *priv; + struct stm32_cbinfo_s *cbinfo; int ret; DEBUGASSERT(lower != NULL); DEBUGASSERT(alarmid == RTC_ALARMA || alarmid == RTC_ALARMB); - priv = (struct stm32wb_lowerhalf_s *)lower; + priv = (struct stm32_lowerhalf_s *)lower; ret = nxmutex_lock(&priv->devlock); if (ret < 0) @@ -496,7 +496,7 @@ static int stm32wb_cancelalarm(struct rtc_lowerhalf_s *lower, int alarmid) /* Then cancel the alarm */ - ret = stm32wb_rtc_cancelalarm((enum alm_id_e)alarmid); + ret = stm32_rtc_cancelalarm((enum alm_id_e)alarmid); } nxmutex_unlock(&priv->devlock); @@ -505,7 +505,7 @@ static int stm32wb_cancelalarm(struct rtc_lowerhalf_s *lower, int alarmid) #endif /**************************************************************************** - * Name: stm32wb_rdalarm + * Name: stm32_rdalarm * * Description: * Query the RTC alarm. @@ -521,7 +521,7 @@ static int stm32wb_cancelalarm(struct rtc_lowerhalf_s *lower, int alarmid) ****************************************************************************/ #ifdef CONFIG_RTC_ALARM -static int stm32wb_rdalarm(struct rtc_lowerhalf_s *lower, +static int stm32_rdalarm(struct rtc_lowerhalf_s *lower, struct lower_rdalarm_s *alarminfo) { struct alm_rdalarm_s lowerinfo; @@ -542,7 +542,7 @@ static int stm32wb_rdalarm(struct rtc_lowerhalf_s *lower, lowerinfo.ar_id = alarminfo->id; lowerinfo.ar_time = alarminfo->time; - ret = stm32wb_rtc_rdalarm(&lowerinfo); + ret = stm32_rtc_rdalarm(&lowerinfo); leave_critical_section(flags); } @@ -552,7 +552,7 @@ static int stm32wb_rdalarm(struct rtc_lowerhalf_s *lower, #endif /**************************************************************************** - * Name: stm32wb_periodic_callback + * Name: stm32_periodic_callback * * Description: * This is the function that is called from the RTC driver when the @@ -568,14 +568,14 @@ static int stm32wb_rdalarm(struct rtc_lowerhalf_s *lower, ****************************************************************************/ #ifdef CONFIG_RTC_PERIODIC -static int stm32wb_periodic_callback(void) +static int stm32_periodic_callback(void) { - struct stm32wb_lowerhalf_s *lower; + struct stm32_lowerhalf_s *lower; struct lower_setperiodic_s *cbinfo; rtc_wakeup_callback_t cb; void *priv; - lower = (struct stm32wb_lowerhalf_s *)&g_rtc_lowerhalf; + lower = (struct stm32_lowerhalf_s *)&g_rtc_lowerhalf; cbinfo = &lower->periodic; cb = (rtc_wakeup_callback_t)cbinfo->cb; @@ -593,7 +593,7 @@ static int stm32wb_periodic_callback(void) #endif /* CONFIG_RTC_PERIODIC */ /**************************************************************************** - * Name: stm32wb_setperiodic + * Name: stm32_setperiodic * * Description: * Set a new periodic wakeup relative to the current time, with a given @@ -612,14 +612,14 @@ static int stm32wb_periodic_callback(void) #ifdef CONFIG_RTC_PERIODIC static int -stm32wb_setperiodic(struct rtc_lowerhalf_s *lower, +stm32_setperiodic(struct rtc_lowerhalf_s *lower, const struct lower_setperiodic_s *alarminfo) { - struct stm32wb_lowerhalf_s *priv; + struct stm32_lowerhalf_s *priv; int ret; DEBUGASSERT(lower != NULL && alarminfo != NULL); - priv = (struct stm32wb_lowerhalf_s *)lower; + priv = (struct stm32_lowerhalf_s *)lower; ret = nxmutex_lock(&priv->devlock); if (ret < 0) @@ -628,8 +628,8 @@ stm32wb_setperiodic(struct rtc_lowerhalf_s *lower, } memcpy(&priv->periodic, alarminfo, sizeof(struct lower_setperiodic_s)); - ret = stm32wb_rtc_setperiodic(&alarminfo->period, - stm32wb_periodic_callback); + ret = stm32_rtc_setperiodic(&alarminfo->period, + stm32_periodic_callback); nxmutex_unlock(&priv->devlock); return ret; @@ -637,7 +637,7 @@ stm32wb_setperiodic(struct rtc_lowerhalf_s *lower, #endif /**************************************************************************** - * Name: stm32wb_cancelperiodic + * Name: stm32_cancelperiodic * * Description: * Cancel the current periodic wakeup activity. This function implements @@ -653,13 +653,13 @@ stm32wb_setperiodic(struct rtc_lowerhalf_s *lower, ****************************************************************************/ #ifdef CONFIG_RTC_PERIODIC -static int stm32wb_cancelperiodic(struct rtc_lowerhalf_s *lower, int id) +static int stm32_cancelperiodic(struct rtc_lowerhalf_s *lower, int id) { - struct stm32wb_lowerhalf_s *priv; + struct stm32_lowerhalf_s *priv; int ret; DEBUGASSERT(lower != NULL); - priv = (struct stm32wb_lowerhalf_s *)lower; + priv = (struct stm32_lowerhalf_s *)lower; DEBUGASSERT(id == 0); @@ -669,7 +669,7 @@ static int stm32wb_cancelperiodic(struct rtc_lowerhalf_s *lower, int id) return ret; } - ret = stm32wb_rtc_cancelperiodic(); + ret = stm32_rtc_cancelperiodic(); nxmutex_unlock(&priv->devlock); return ret; @@ -681,7 +681,7 @@ static int stm32wb_cancelperiodic(struct rtc_lowerhalf_s *lower, int id) ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_rtc_lowerhalf + * Name: stm32_rtc_lowerhalf * * Description: * Instantiate the RTC lower half driver for the STM32. General usage: @@ -690,7 +690,7 @@ static int stm32wb_cancelperiodic(struct rtc_lowerhalf_s *lower, int id) * #include "stm32wb_rtc.h> * * struct rtc_lowerhalf_s *lower; - * lower = stm32wb_rtc_lowerhalf(); + * lower = stm32_rtc_lowerhalf(); * rtc_initialize(0, lower); * * Input Parameters: @@ -702,7 +702,7 @@ static int stm32wb_cancelperiodic(struct rtc_lowerhalf_s *lower, int id) * ****************************************************************************/ -struct rtc_lowerhalf_s *stm32wb_rtc_lowerhalf(void) +struct rtc_lowerhalf_s *stm32_rtc_lowerhalf(void) { return (struct rtc_lowerhalf_s *)&g_rtc_lowerhalf; } diff --git a/arch/arm/src/stm32wb/stm32wb_serial.c b/arch/arm/src/stm32wb/stm32wb_serial.c index 5289b289fa7..78bd2aaef33 100644 --- a/arch/arm/src/stm32wb/stm32wb_serial.c +++ b/arch/arm/src/stm32wb/stm32wb_serial.c @@ -138,7 +138,7 @@ * register. It must not collide with USART_CR1_USED_INTS or USART_CR3_EIE * 2) USART_CR3_EIE is also carried in the up_dev_s ie member. * - * See stm32wb_serial_restoreusartint where the masking is done. + * See stm32_serial_restoreusartint where the masking is done. */ #ifdef CONFIG_STM32WB_SERIALBRK_BSDCOMPAT @@ -153,7 +153,7 @@ * Private Types ****************************************************************************/ -struct stm32wb_serial_s +struct stm32_serial_s { struct uart_dev_s dev; /* Generic UART device */ uint16_t ie; /* Saved interrupt mask bits value */ @@ -239,51 +239,51 @@ struct stm32wb_serial_s ****************************************************************************/ #ifndef CONFIG_SUPPRESS_UART_CONFIG -static void stm32wb_serial_setformat(struct uart_dev_s *dev); +static void stm32_serial_setformat(struct uart_dev_s *dev); #endif -static int stm32wb_serial_setup(struct uart_dev_s *dev); -static void stm32wb_serial_shutdown(struct uart_dev_s *dev); -static int stm32wb_serial_attach(struct uart_dev_s *dev); -static void stm32wb_serial_detach(struct uart_dev_s *dev); +static int stm32_serial_setup(struct uart_dev_s *dev); +static void stm32_serial_shutdown(struct uart_dev_s *dev); +static int stm32_serial_attach(struct uart_dev_s *dev); +static void stm32_serial_detach(struct uart_dev_s *dev); static int up_interrupt(int irq, void *context, void *arg); -static int stm32wb_serial_ioctl(struct file *filep, int cmd, +static int stm32_serial_ioctl(struct file *filep, int cmd, unsigned long arg); #ifndef SERIAL_HAVE_ONLY_DMA -static int stm32wb_serial_receive(struct uart_dev_s *dev, +static int stm32_serial_receive(struct uart_dev_s *dev, unsigned int *status); -static void stm32wb_serial_rxint(struct uart_dev_s *dev, bool enable); -static bool stm32wb_serial_rxavailable(struct uart_dev_s *dev); +static void stm32_serial_rxint(struct uart_dev_s *dev, bool enable); +static bool stm32_serial_rxavailable(struct uart_dev_s *dev); #endif #ifdef CONFIG_SERIAL_IFLOWCONTROL -static bool stm32wb_serial_rxflowcontrol(struct uart_dev_s *dev, +static bool stm32_serial_rxflowcontrol(struct uart_dev_s *dev, unsigned int nbuffered, bool upper); #endif -static void stm32wb_serial_send(struct uart_dev_s *dev, int ch); -static void stm32wb_serial_txint(struct uart_dev_s *dev, bool enable); -static bool stm32wb_serial_txready(struct uart_dev_s *dev); +static void stm32_serial_send(struct uart_dev_s *dev, int ch); +static void stm32_serial_txint(struct uart_dev_s *dev, bool enable); +static bool stm32_serial_txready(struct uart_dev_s *dev); #ifdef SERIAL_HAVE_RXDMA -static int stm32wb_serial_dmasetup(struct uart_dev_s *dev); -static void stm32wb_serial_dmashutdown(struct uart_dev_s *dev); -static int stm32wb_serial_dmareceive(struct uart_dev_s *dev, +static int stm32_serial_dmasetup(struct uart_dev_s *dev); +static void stm32_serial_dmashutdown(struct uart_dev_s *dev); +static int stm32_serial_dmareceive(struct uart_dev_s *dev, unsigned int *status); -static void stm32wb_serial_dmareenable(struct stm32wb_serial_s *priv); +static void stm32_serial_dmareenable(struct stm32_serial_s *priv); #ifdef CONFIG_SERIAL_IFLOWCONTROL -static bool stm32wb_serial_dmaiflowrestart(struct stm32wb_serial_s *priv); +static bool stm32_serial_dmaiflowrestart(struct stm32_serial_s *priv); #endif -static void stm32wb_serial_dmarxint(struct uart_dev_s *dev, bool enable); -static bool stm32wb_serial_dmarxavailable(struct uart_dev_s *dev); +static void stm32_serial_dmarxint(struct uart_dev_s *dev, bool enable); +static bool stm32_serial_dmarxavailable(struct uart_dev_s *dev); -static void stm32wb_serial_dmarxcallback(DMA_HANDLE handle, uint8_t status, +static void stm32_serial_dmarxcallback(DMA_HANDLE handle, uint8_t status, void *arg); #endif #ifdef CONFIG_PM -static void stm32wb_serial_setsuspend(struct uart_dev_s *dev, bool suspend); -static void stm32wb_serial_pm_setsuspend(bool suspend); -static void stm32wb_serial_pmnotify(struct pm_callback_s *cb, +static void stm32_serial_setsuspend(struct uart_dev_s *dev, bool suspend); +static void stm32_serial_pm_setsuspend(bool suspend); +static void stm32_serial_pmnotify(struct pm_callback_s *cb, int domain, enum pm_state_e pmstate); -static int stm32wb_serial_pmprepare(struct pm_callback_s *cb, +static int stm32_serial_pmprepare(struct pm_callback_s *cb, int domain, enum pm_state_e pmstate); #endif @@ -294,42 +294,42 @@ static int stm32wb_serial_pmprepare(struct pm_callback_s *cb, #ifndef SERIAL_HAVE_ONLY_DMA static const struct uart_ops_s g_uart_ops = { - .setup = stm32wb_serial_setup, - .shutdown = stm32wb_serial_shutdown, - .attach = stm32wb_serial_attach, - .detach = stm32wb_serial_detach, - .ioctl = stm32wb_serial_ioctl, - .receive = stm32wb_serial_receive, - .rxint = stm32wb_serial_rxint, - .rxavailable = stm32wb_serial_rxavailable, + .setup = stm32_serial_setup, + .shutdown = stm32_serial_shutdown, + .attach = stm32_serial_attach, + .detach = stm32_serial_detach, + .ioctl = stm32_serial_ioctl, + .receive = stm32_serial_receive, + .rxint = stm32_serial_rxint, + .rxavailable = stm32_serial_rxavailable, #ifdef CONFIG_SERIAL_IFLOWCONTROL - .rxflowcontrol = stm32wb_serial_rxflowcontrol, + .rxflowcontrol = stm32_serial_rxflowcontrol, #endif - .send = stm32wb_serial_send, - .txint = stm32wb_serial_txint, - .txready = stm32wb_serial_txready, - .txempty = stm32wb_serial_txready, + .send = stm32_serial_send, + .txint = stm32_serial_txint, + .txready = stm32_serial_txready, + .txempty = stm32_serial_txready, }; #endif #ifdef SERIAL_HAVE_RXDMA static const struct uart_ops_s g_uart_dma_ops = { - .setup = stm32wb_serial_dmasetup, - .shutdown = stm32wb_serial_dmashutdown, - .attach = stm32wb_serial_attach, - .detach = stm32wb_serial_detach, - .ioctl = stm32wb_serial_ioctl, - .receive = stm32wb_serial_dmareceive, - .rxint = stm32wb_serial_dmarxint, - .rxavailable = stm32wb_serial_dmarxavailable, + .setup = stm32_serial_dmasetup, + .shutdown = stm32_serial_dmashutdown, + .attach = stm32_serial_attach, + .detach = stm32_serial_detach, + .ioctl = stm32_serial_ioctl, + .receive = stm32_serial_dmareceive, + .rxint = stm32_serial_dmarxint, + .rxavailable = stm32_serial_dmarxavailable, #ifdef CONFIG_SERIAL_IFLOWCONTROL - .rxflowcontrol = stm32wb_serial_rxflowcontrol, + .rxflowcontrol = stm32_serial_rxflowcontrol, #endif - .send = stm32wb_serial_send, - .txint = stm32wb_serial_txint, - .txready = stm32wb_serial_txready, - .txempty = stm32wb_serial_txready, + .send = stm32_serial_send, + .txint = stm32_serial_txint, + .txready = stm32_serial_txready, + .txempty = stm32_serial_txready, }; #endif @@ -354,7 +354,7 @@ static char g_usart1rxfifo[RXDMA_BUFFER_SIZE]; /* This describes the state of the STM32WB LPUART1 port. */ #ifdef CONFIG_STM32WB_LPUART1_SERIALDRIVER -static struct stm32wb_serial_s g_lpuart1priv = +static struct stm32_serial_s g_lpuart1priv = { .dev = { @@ -416,7 +416,7 @@ static struct stm32wb_serial_s g_lpuart1priv = /* This describes the state of the STM32WB USART1 port. */ #ifdef CONFIG_STM32WB_USART1_SERIALDRIVER -static struct stm32wb_serial_s g_usart1priv = +static struct stm32_serial_s g_usart1priv = { .dev = { @@ -477,7 +477,7 @@ static struct stm32wb_serial_s g_usart1priv = /* This table lets us iterate over the configured USARTs */ -static struct stm32wb_serial_s * +static struct stm32_serial_s * const g_uart_devs[STM32_NLPUART + STM32_NUSART] = { #ifdef CONFIG_STM32WB_LPUART1_SERIALDRIVER @@ -495,8 +495,8 @@ static struct bool serial_suspended; } g_serialpm = { - .pm_cb.notify = stm32wb_serial_pmnotify, - .pm_cb.prepare = stm32wb_serial_pmprepare, + .pm_cb.notify = stm32_serial_pmnotify, + .pm_cb.prepare = stm32_serial_pmprepare, .serial_suspended = false }; #endif @@ -506,31 +506,31 @@ static struct ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_serial_getreg + * Name: stm32_serial_getreg ****************************************************************************/ static inline -uint32_t stm32wb_serial_getreg(struct stm32wb_serial_s *priv, int offset) +uint32_t stm32_serial_getreg(struct stm32_serial_s *priv, int offset) { return getreg32(priv->usartbase + offset); } /**************************************************************************** - * Name: stm32wb_serial_putreg + * Name: stm32_serial_putreg ****************************************************************************/ -static inline void stm32wb_serial_putreg(struct stm32wb_serial_s *priv, +static inline void stm32_serial_putreg(struct stm32_serial_s *priv, int offset, uint32_t value) { putreg32(value, priv->usartbase + offset); } /**************************************************************************** - * Name: stm32wb_serial_setusartint + * Name: stm32_serial_setusartint ****************************************************************************/ static inline -void stm32wb_serial_setusartint(struct stm32wb_serial_s *priv, uint16_t ie) +void stm32_serial_setusartint(struct stm32_serial_s *priv, uint16_t ie) { uint32_t cr; @@ -542,38 +542,38 @@ void stm32wb_serial_setusartint(struct stm32wb_serial_s *priv, uint16_t ie) * enable/usage table above) */ - cr = stm32wb_serial_getreg(priv, STM32_USART_CR1_OFFSET); + cr = stm32_serial_getreg(priv, STM32_USART_CR1_OFFSET); cr &= ~(USART_CR1_USED_INTS); cr |= (ie & (USART_CR1_USED_INTS)); - stm32wb_serial_putreg(priv, STM32_USART_CR1_OFFSET, cr); + stm32_serial_putreg(priv, STM32_USART_CR1_OFFSET, cr); - cr = stm32wb_serial_getreg(priv, STM32_USART_CR3_OFFSET); + cr = stm32_serial_getreg(priv, STM32_USART_CR3_OFFSET); cr &= ~USART_CR3_EIE; cr |= (ie & USART_CR3_EIE); - stm32wb_serial_putreg(priv, STM32_USART_CR3_OFFSET, cr); + stm32_serial_putreg(priv, STM32_USART_CR3_OFFSET, cr); } /**************************************************************************** * Name: up_restoreusartint ****************************************************************************/ -static void stm32wb_serial_restoreusartint(struct stm32wb_serial_s *priv, +static void stm32_serial_restoreusartint(struct stm32_serial_s *priv, uint16_t ie) { irqstate_t flags; flags = spin_lock_irqsave(&priv->lock); - stm32wb_serial_setusartint(priv, ie); + stm32_serial_setusartint(priv, ie); spin_unlock_irqrestore(&priv->lock, flags); } /**************************************************************************** - * Name: stm32wb_serial_disableusartint + * Name: stm32_serial_disableusartint ****************************************************************************/ -static void stm32wb_serial_disableusartint(struct stm32wb_serial_s *priv, +static void stm32_serial_disableusartint(struct stm32_serial_s *priv, uint16_t *ie) { irqstate_t flags; @@ -610,8 +610,8 @@ static void stm32wb_serial_disableusartint(struct stm32wb_serial_s *priv, * USART_CR3_CTSIE USART_ISR_CTS CTS flag (not used) */ - cr1 = stm32wb_serial_getreg(priv, STM32_USART_CR1_OFFSET); - cr3 = stm32wb_serial_getreg(priv, STM32_USART_CR3_OFFSET); + cr1 = stm32_serial_getreg(priv, STM32_USART_CR1_OFFSET); + cr3 = stm32_serial_getreg(priv, STM32_USART_CR3_OFFSET); /* Return the current interrupt mask value for the used interrupts. * Notice that this depends on the fact that none of the used interrupt @@ -624,13 +624,13 @@ static void stm32wb_serial_disableusartint(struct stm32wb_serial_s *priv, /* Disable all interrupts */ - stm32wb_serial_setusartint(priv, 0); + stm32_serial_setusartint(priv, 0); spin_unlock_irqrestore(&priv->lock, flags); } /**************************************************************************** - * Name: stm32wb_serial_dmanextrx + * Name: stm32_serial_dmanextrx * * Description: * Returns the index into the RX FIFO where the DMA will place the next @@ -639,18 +639,18 @@ static void stm32wb_serial_disableusartint(struct stm32wb_serial_s *priv, ****************************************************************************/ #ifdef SERIAL_HAVE_RXDMA -static int stm32wb_serial_dmanextrx(struct stm32wb_serial_s *priv) +static int stm32_serial_dmanextrx(struct stm32_serial_s *priv) { size_t dmaresidual; - dmaresidual = stm32wb_dmaresidual(priv->rxdma); + dmaresidual = stm32_dmaresidual(priv->rxdma); return (RXDMA_BUFFER_SIZE - (int)dmaresidual); } #endif /**************************************************************************** - * Name: stm32wb_serial_setbaud_usart + * Name: stm32_serial_setbaud_usart * * Description: * Set the serial line baud rate (USART only). @@ -658,7 +658,7 @@ static int stm32wb_serial_dmanextrx(struct stm32wb_serial_s *priv) ****************************************************************************/ #ifndef CONFIG_SUPPRESS_UART_CONFIG -static void stm32wb_serial_setbaud_usart(struct stm32wb_serial_s *priv) +static void stm32_serial_setbaud_usart(struct stm32_serial_s *priv) { /* This first implementation is for U[S]ARTs that support oversampling * by 8 in additional to the standard oversampling by 16. @@ -686,8 +686,8 @@ static void stm32wb_serial_setbaud_usart(struct stm32wb_serial_s *priv) /* Use oversamply by 8 only if the divisor is small. But what is small? */ - cr1 = stm32wb_serial_getreg(priv, STM32_USART_CR1_OFFSET); - brr = stm32wb_serial_getreg(priv, STM32_USART_BRR_OFFSET); + cr1 = stm32_serial_getreg(priv, STM32_USART_CR1_OFFSET); + brr = stm32_serial_getreg(priv, STM32_USART_BRR_OFFSET); brr &= ~(USART_BRR_MANT_MASK | USART_BRR_FRAC_MASK); if (usartdiv8 > 100) @@ -713,13 +713,13 @@ static void stm32wb_serial_setbaud_usart(struct stm32wb_serial_s *priv) cr1 |= USART_CR1_OVER8; } - stm32wb_serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1); - stm32wb_serial_putreg(priv, STM32_USART_BRR_OFFSET, brr); + stm32_serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1); + stm32_serial_putreg(priv, STM32_USART_BRR_OFFSET, brr); } #endif /**************************************************************************** - * Name: stm32wb_serial_setbaud_lpuart + * Name: stm32_serial_setbaud_lpuart * * Description: * Set the serial line baud rate (LPUART only). @@ -728,7 +728,7 @@ static void stm32wb_serial_setbaud_usart(struct stm32wb_serial_s *priv) #ifndef CONFIG_SUPPRESS_UART_CONFIG #ifdef CONFIG_STM32WB_LPUART1_SERIALDRIVER -static void stm32wb_serial_setbaud_lpuart(struct stm32wb_serial_s *priv) +static void stm32_serial_setbaud_lpuart(struct stm32_serial_s *priv) { uint32_t brr; @@ -750,13 +750,13 @@ static void stm32wb_serial_setbaud_lpuart(struct stm32wb_serial_s *priv) brr = LPUART_BRR_MIN; } - stm32wb_serial_putreg(priv, STM32_USART_BRR_OFFSET, brr); + stm32_serial_putreg(priv, STM32_USART_BRR_OFFSET, brr); } #endif #endif /**************************************************************************** - * Name: stm32wb_serial_setformat + * Name: stm32_serial_setformat * * Description: * Set the serial line format and speed. @@ -764,9 +764,9 @@ static void stm32wb_serial_setbaud_lpuart(struct stm32wb_serial_s *priv) ****************************************************************************/ #ifndef CONFIG_SUPPRESS_UART_CONFIG -static void stm32wb_serial_setformat(struct uart_dev_s *dev) +static void stm32_serial_setformat(struct uart_dev_s *dev) { - struct stm32wb_serial_s *priv = (struct stm32wb_serial_s *)dev->priv; + struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; uint32_t regval; /* Set baud rate */ @@ -774,17 +774,17 @@ static void stm32wb_serial_setformat(struct uart_dev_s *dev) #ifdef CONFIG_STM32WB_LPUART1_SERIALDRIVER if (priv->usartbase == STM32_LPUART1_BASE) { - stm32wb_serial_setbaud_lpuart(priv); + stm32_serial_setbaud_lpuart(priv); } else #endif { - stm32wb_serial_setbaud_usart(priv); + stm32_serial_setbaud_usart(priv); } /* Configure parity mode */ - regval = stm32wb_serial_getreg(priv, STM32_USART_CR1_OFFSET); + regval = stm32_serial_getreg(priv, STM32_USART_CR1_OFFSET); regval &= ~(USART_CR1_PCE | USART_CR1_PS | USART_CR1_M0 | USART_CR1_M1); if (priv->parity == 1) /* Odd parity */ @@ -822,11 +822,11 @@ static void stm32wb_serial_setformat(struct uart_dev_s *dev) * 1 start, 8 data (no parity), n stop. */ - stm32wb_serial_putreg(priv, STM32_USART_CR1_OFFSET, regval); + stm32_serial_putreg(priv, STM32_USART_CR1_OFFSET, regval); /* Configure STOP bits */ - regval = stm32wb_serial_getreg(priv, STM32_USART_CR2_OFFSET); + regval = stm32_serial_getreg(priv, STM32_USART_CR2_OFFSET); regval &= ~(USART_CR2_STOP_MASK); if (priv->stopbits2) @@ -834,11 +834,11 @@ static void stm32wb_serial_setformat(struct uart_dev_s *dev) regval |= USART_CR2_STOP2; } - stm32wb_serial_putreg(priv, STM32_USART_CR2_OFFSET, regval); + stm32_serial_putreg(priv, STM32_USART_CR2_OFFSET, regval); /* Configure hardware flow control */ - regval = stm32wb_serial_getreg(priv, STM32_USART_CR3_OFFSET); + regval = stm32_serial_getreg(priv, STM32_USART_CR3_OFFSET); regval &= ~(USART_CR3_CTSE | USART_CR3_RTSE); #if defined(CONFIG_SERIAL_IFLOWCONTROL) && !defined(CONFIG_STM32WB_FLOWCONTROL_BROKEN) @@ -855,12 +855,12 @@ static void stm32wb_serial_setformat(struct uart_dev_s *dev) } #endif - stm32wb_serial_putreg(priv, STM32_USART_CR3_OFFSET, regval); + stm32_serial_putreg(priv, STM32_USART_CR3_OFFSET, regval); } #endif /* CONFIG_SUPPRESS_UART_CONFIG */ /**************************************************************************** - * Name: stm32wb_serial_setsuspend + * Name: stm32_serial_setsuspend * * Description: * Suspend or resume serial peripheral. @@ -868,9 +868,9 @@ static void stm32wb_serial_setformat(struct uart_dev_s *dev) ****************************************************************************/ #ifdef CONFIG_PM -static void stm32wb_serial_setsuspend(struct uart_dev_s *dev, bool suspend) +static void stm32_serial_setsuspend(struct uart_dev_s *dev, bool suspend) { - struct stm32wb_serial_s *priv = (struct stm32wb_serial_s *)dev->priv; + struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; #ifdef SERIAL_HAVE_RXDMA bool dmarestored = false; #endif @@ -889,18 +889,18 @@ static void stm32wb_serial_setsuspend(struct uart_dev_s *dev, bool suspend) { /* Force RTS high to prevent further Rx. */ - stm32wb_configgpio((priv->rts_gpio & ~GPIO_MODE_MASK) + stm32_configgpio((priv->rts_gpio & ~GPIO_MODE_MASK) | (GPIO_OUTPUT | GPIO_OUTPUT_SET)); } #endif /* Disable interrupts to prevent Tx. */ - stm32wb_serial_disableusartint(priv, &priv->suspended_ie); + stm32_serial_disableusartint(priv, &priv->suspended_ie); /* Wait last Tx to complete. */ - while ((stm32wb_serial_getreg(priv, STM32_USART_ISR_OFFSET) & + while ((stm32_serial_getreg(priv, STM32_USART_ISR_OFFSET) & USART_ISR_TC) == 0); #ifdef SERIAL_HAVE_RXDMA @@ -918,7 +918,7 @@ static void stm32wb_serial_setsuspend(struct uart_dev_s *dev, bool suspend) { /* Suspend Rx DMA. */ - stm32wb_dmastop(priv->rxdma); + stm32_dmastop(priv->rxdma); priv->rxdmasusp = true; } } @@ -932,7 +932,7 @@ static void stm32wb_serial_setsuspend(struct uart_dev_s *dev, bool suspend) #ifdef CONFIG_SERIAL_IFLOWCONTROL if (priv->iflow) { - stm32wb_serial_dmaiflowrestart(priv); + stm32_serial_dmaiflowrestart(priv); } else #endif @@ -942,7 +942,7 @@ static void stm32wb_serial_setsuspend(struct uart_dev_s *dev, bool suspend) * to DMA buffer before suspending). */ - stm32wb_serial_dmareenable(priv); + stm32_serial_dmareenable(priv); priv->rxdmasusp = false; } @@ -952,14 +952,14 @@ static void stm32wb_serial_setsuspend(struct uart_dev_s *dev, bool suspend) /* Re-enable interrupts to resume Tx. */ - stm32wb_serial_restoreusartint(priv, priv->suspended_ie); + stm32_serial_restoreusartint(priv, priv->suspended_ie); #ifdef CONFIG_SERIAL_IFLOWCONTROL if (priv->iflow) { /* Restore peripheral RTS control. */ - stm32wb_configgpio(priv->rts_gpio); + stm32_configgpio(priv->rts_gpio); } #endif } @@ -977,7 +977,7 @@ static void stm32wb_serial_setsuspend(struct uart_dev_s *dev, bool suspend) if (priv->rxdma != NULL) { - stm32wb_serial_dmarxcallback(priv->rxdma, 0, priv); + stm32_serial_dmarxcallback(priv->rxdma, 0, priv); } leave_critical_section(flags); @@ -987,7 +987,7 @@ static void stm32wb_serial_setsuspend(struct uart_dev_s *dev, bool suspend) #endif /**************************************************************************** - * Name: stm32wb_serial_pm_setsuspend + * Name: stm32_serial_pm_setsuspend * * Description: * Suspend or resume serial peripherals for/from deep-sleep/stop modes. @@ -995,7 +995,7 @@ static void stm32wb_serial_setsuspend(struct uart_dev_s *dev, bool suspend) ****************************************************************************/ #ifdef CONFIG_PM -static void stm32wb_serial_pm_setsuspend(bool suspend) +static void stm32_serial_pm_setsuspend(bool suspend) { int n; @@ -1010,18 +1010,18 @@ static void stm32wb_serial_pm_setsuspend(bool suspend) for (n = 0; n < STM32_NLPUART + STM32_NUSART; n++) { - struct stm32wb_serial_s *priv = g_uart_devs[n]; + struct stm32_serial_s *priv = g_uart_devs[n]; if (priv != NULL && priv->initialized != NULL) { - stm32wb_serial_setsuspend(&priv->dev, suspend); + stm32_serial_setsuspend(&priv->dev, suspend); } } } #endif /**************************************************************************** - * Name: stm32wb_serial_setapbclock + * Name: stm32_serial_setapbclock * * Description: * Enable or disable APB clock for the USART peripheral @@ -1032,9 +1032,9 @@ static void stm32wb_serial_pm_setsuspend(bool suspend) * ****************************************************************************/ -static void stm32wb_serial_setapbclock(struct uart_dev_s *dev, bool on) +static void stm32_serial_setapbclock(struct uart_dev_s *dev, bool on) { - struct stm32wb_serial_s *priv = (struct stm32wb_serial_s *)dev->priv; + struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; uint32_t rcc_en; uint32_t regaddr; @@ -1071,7 +1071,7 @@ static void stm32wb_serial_setapbclock(struct uart_dev_s *dev, bool on) } /**************************************************************************** - * Name: stm32wb_serial_setup + * Name: stm32_serial_setup * * Description: * Configure the USART baud, bits, parity, etc. This method is called the @@ -1079,37 +1079,37 @@ static void stm32wb_serial_setapbclock(struct uart_dev_s *dev, bool on) * ****************************************************************************/ -static int stm32wb_serial_setup(struct uart_dev_s *dev) +static int stm32_serial_setup(struct uart_dev_s *dev) { - struct stm32wb_serial_s *priv = (struct stm32wb_serial_s *)dev->priv; + struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; #ifndef CONFIG_SUPPRESS_UART_CONFIG uint32_t regval; /* Note: The logic here depends on the fact that that the USART module - * was enabled in stm32wb_lowsetup(). + * was enabled in stm32_lowsetup(). */ /* Enable USART APB1/2 clock */ - stm32wb_serial_setapbclock(dev, true); + stm32_serial_setapbclock(dev, true); /* Configure pins for USART use */ if (priv->tx_gpio != 0) { - stm32wb_configgpio(priv->tx_gpio); + stm32_configgpio(priv->tx_gpio); } if (priv->rx_gpio != 0) { - stm32wb_configgpio(priv->rx_gpio); + stm32_configgpio(priv->rx_gpio); } #ifdef CONFIG_SERIAL_OFLOWCONTROL if (priv->cts_gpio != 0) { - stm32wb_configgpio(priv->cts_gpio); + stm32_configgpio(priv->cts_gpio); } #endif @@ -1123,15 +1123,15 @@ static int stm32wb_serial_setup(struct uart_dev_s *dev) config = (config & ~GPIO_MODE_MASK) | GPIO_OUTPUT; #endif - stm32wb_configgpio(config); + stm32_configgpio(config); } #endif #ifdef HAVE_RS485 if (priv->rs485_dir_gpio != 0) { - stm32wb_configgpio(priv->rs485_dir_gpio); - stm32wb_gpiowrite(priv->rs485_dir_gpio, !priv->rs485_dir_polarity); + stm32_configgpio(priv->rs485_dir_gpio); + stm32_gpiowrite(priv->rs485_dir_gpio, !priv->rs485_dir_polarity); } #endif @@ -1139,7 +1139,7 @@ static int stm32wb_serial_setup(struct uart_dev_s *dev) /* Clear STOP, CLKEN, CPOL, CPHA, LBCL, and interrupt enable bits */ - regval = stm32wb_serial_getreg(priv, STM32_USART_CR2_OFFSET); + regval = stm32_serial_getreg(priv, STM32_USART_CR2_OFFSET); regval &= ~(USART_CR2_STOP_MASK | USART_CR2_CLKEN | USART_CR2_CPOL | USART_CR2_CPHA | USART_CR2_LBCL | USART_CR2_LBDIE); @@ -1150,36 +1150,36 @@ static int stm32wb_serial_setup(struct uart_dev_s *dev) regval |= USART_CR2_STOP2; } - stm32wb_serial_putreg(priv, STM32_USART_CR2_OFFSET, regval); + stm32_serial_putreg(priv, STM32_USART_CR2_OFFSET, regval); /* Configure CR1 */ /* Clear TE, REm and all interrupt enable bits */ - regval = stm32wb_serial_getreg(priv, STM32_USART_CR1_OFFSET); + regval = stm32_serial_getreg(priv, STM32_USART_CR1_OFFSET); regval &= ~(USART_CR1_TE | USART_CR1_RE | USART_CR1_ALLINTS); - stm32wb_serial_putreg(priv, STM32_USART_CR1_OFFSET, regval); + stm32_serial_putreg(priv, STM32_USART_CR1_OFFSET, regval); /* Configure CR3 */ /* Clear CTSE, RTSE, and all interrupt enable bits */ - regval = stm32wb_serial_getreg(priv, STM32_USART_CR3_OFFSET); + regval = stm32_serial_getreg(priv, STM32_USART_CR3_OFFSET); regval &= ~(USART_CR3_CTSIE | USART_CR3_CTSE | USART_CR3_RTSE | USART_CR3_EIE); - stm32wb_serial_putreg(priv, STM32_USART_CR3_OFFSET, regval); + stm32_serial_putreg(priv, STM32_USART_CR3_OFFSET, regval); /* Configure the USART line format and speed. */ - stm32wb_serial_setformat(dev); + stm32_serial_setformat(dev); /* Enable Rx, Tx, and the USART */ - regval = stm32wb_serial_getreg(priv, STM32_USART_CR1_OFFSET); + regval = stm32_serial_getreg(priv, STM32_USART_CR1_OFFSET); regval |= (USART_CR1_UE | USART_CR1_TE | USART_CR1_RE); - stm32wb_serial_putreg(priv, STM32_USART_CR1_OFFSET, regval); + stm32_serial_putreg(priv, STM32_USART_CR1_OFFSET, regval); #endif /* CONFIG_SUPPRESS_UART_CONFIG */ @@ -1195,7 +1195,7 @@ static int stm32wb_serial_setup(struct uart_dev_s *dev) } /**************************************************************************** - * Name: stm32wb_serial_dmasetup + * Name: stm32_serial_dmasetup * * Description: * Configure the USART baud, bits, parity, etc. This method is called the @@ -1204,9 +1204,9 @@ static int stm32wb_serial_setup(struct uart_dev_s *dev) ****************************************************************************/ #ifdef SERIAL_HAVE_RXDMA -static int stm32wb_serial_dmasetup(struct uart_dev_s *dev) +static int stm32_serial_dmasetup(struct uart_dev_s *dev) { - struct stm32wb_serial_s *priv = (struct stm32wb_serial_s *)dev->priv; + struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; int result; uint32_t regval; @@ -1214,7 +1214,7 @@ static int stm32wb_serial_dmasetup(struct uart_dev_s *dev) if (!dev->isconsole) { - result = stm32wb_serial_setup(dev); + result = stm32_serial_setup(dev); if (result != OK) { return result; @@ -1223,14 +1223,14 @@ static int stm32wb_serial_dmasetup(struct uart_dev_s *dev) /* Acquire the DMA channel. This should always succeed. */ - priv->rxdma = stm32wb_dmachannel(priv->rxdma_channel); + priv->rxdma = stm32_dmachannel(priv->rxdma_channel); #ifdef CONFIG_SERIAL_IFLOWCONTROL if (priv->iflow) { /* Configure for non-circular DMA reception into the RX FIFO */ - stm32wb_dmasetup(priv->rxdma, + stm32_dmasetup(priv->rxdma, priv->usartbase + STM32_USART_RDR_OFFSET, (uint32_t)priv->rxfifo, RXDMA_BUFFER_SIZE, @@ -1241,7 +1241,7 @@ static int stm32wb_serial_dmasetup(struct uart_dev_s *dev) { /* Configure for circular DMA reception into the RX FIFO */ - stm32wb_dmasetup(priv->rxdma, + stm32_dmasetup(priv->rxdma, priv->usartbase + STM32_USART_RDR_OFFSET, (uint32_t)priv->rxfifo, RXDMA_BUFFER_SIZE, @@ -1256,9 +1256,9 @@ static int stm32wb_serial_dmasetup(struct uart_dev_s *dev) /* Enable receive DMA for the UART */ - regval = stm32wb_serial_getreg(priv, STM32_USART_CR3_OFFSET); + regval = stm32_serial_getreg(priv, STM32_USART_CR3_OFFSET); regval |= USART_CR3_DMAR; - stm32wb_serial_putreg(priv, STM32_USART_CR3_OFFSET, regval); + stm32_serial_putreg(priv, STM32_USART_CR3_OFFSET, regval); #ifdef CONFIG_SERIAL_IFLOWCONTROL if (priv->iflow) @@ -1268,7 +1268,7 @@ static int stm32wb_serial_dmasetup(struct uart_dev_s *dev) * in and DMA transfer is stopped. */ - stm32wb_dmastart(priv->rxdma, stm32wb_serial_dmarxcallback, priv, + stm32_dmastart(priv->rxdma, stm32_serial_dmarxcallback, priv, false); } else @@ -1279,7 +1279,7 @@ static int stm32wb_serial_dmasetup(struct uart_dev_s *dev) * worth of time to claim bytes before they are overwritten. */ - stm32wb_dmastart(priv->rxdma, stm32wb_serial_dmarxcallback, priv, + stm32_dmastart(priv->rxdma, stm32_serial_dmarxcallback, priv, true); } @@ -1288,7 +1288,7 @@ static int stm32wb_serial_dmasetup(struct uart_dev_s *dev) #endif /**************************************************************************** - * Name: stm32wb_serial_shutdown + * Name: stm32_serial_shutdown * * Description: * Disable the USART. This method is called when the serial @@ -1296,9 +1296,9 @@ static int stm32wb_serial_dmasetup(struct uart_dev_s *dev) * ****************************************************************************/ -static void stm32wb_serial_shutdown(struct uart_dev_s *dev) +static void stm32_serial_shutdown(struct uart_dev_s *dev) { - struct stm32wb_serial_s *priv = (struct stm32wb_serial_s *)dev->priv; + struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; uint32_t regval; /* Mark device as uninitialized. */ @@ -1307,17 +1307,17 @@ static void stm32wb_serial_shutdown(struct uart_dev_s *dev) /* Disable all interrupts */ - stm32wb_serial_disableusartint(priv, NULL); + stm32_serial_disableusartint(priv, NULL); /* Disable USART APB1/2 clock */ - stm32wb_serial_setapbclock(dev, false); + stm32_serial_setapbclock(dev, false); /* Disable Rx, Tx, and the UART */ - regval = stm32wb_serial_getreg(priv, STM32_USART_CR1_OFFSET); + regval = stm32_serial_getreg(priv, STM32_USART_CR1_OFFSET); regval &= ~(USART_CR1_UE | USART_CR1_TE | USART_CR1_RE); - stm32wb_serial_putreg(priv, STM32_USART_CR1_OFFSET, regval); + stm32_serial_putreg(priv, STM32_USART_CR1_OFFSET, regval); /* Release pins. "If the serial-attached device is powered down, the TX * pin causes back-powering, potentially confusing the device to the point @@ -1329,38 +1329,38 @@ static void stm32wb_serial_shutdown(struct uart_dev_s *dev) if (priv->tx_gpio != 0) { - stm32wb_unconfiggpio(priv->tx_gpio); + stm32_unconfiggpio(priv->tx_gpio); } if (priv->rx_gpio != 0) { - stm32wb_unconfiggpio(priv->rx_gpio); + stm32_unconfiggpio(priv->rx_gpio); } #ifdef CONFIG_SERIAL_OFLOWCONTROL if (priv->cts_gpio != 0) { - stm32wb_unconfiggpio(priv->cts_gpio); + stm32_unconfiggpio(priv->cts_gpio); } #endif #ifdef CONFIG_SERIAL_IFLOWCONTROL if (priv->rts_gpio != 0) { - stm32wb_unconfiggpio(priv->rts_gpio); + stm32_unconfiggpio(priv->rts_gpio); } #endif #ifdef HAVE_RS485 if (priv->rs485_dir_gpio != 0) { - stm32wb_unconfiggpio(priv->rs485_dir_gpio); + stm32_unconfiggpio(priv->rs485_dir_gpio); } #endif } /**************************************************************************** - * Name: stm32wb_serial_dmashutdown + * Name: stm32_serial_dmashutdown * * Description: * Disable the USART. This method is called when the serial @@ -1369,27 +1369,27 @@ static void stm32wb_serial_shutdown(struct uart_dev_s *dev) ****************************************************************************/ #ifdef SERIAL_HAVE_RXDMA -static void stm32wb_serial_dmashutdown(struct uart_dev_s *dev) +static void stm32_serial_dmashutdown(struct uart_dev_s *dev) { - struct stm32wb_serial_s *priv = (struct stm32wb_serial_s *)dev->priv; + struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; /* Perform the normal UART shutdown */ - stm32wb_serial_shutdown(dev); + stm32_serial_shutdown(dev); /* Stop the DMA channel */ - stm32wb_dmastop(priv->rxdma); + stm32_dmastop(priv->rxdma); /* Release the DMA channel */ - stm32wb_dmafree(priv->rxdma); + stm32_dmafree(priv->rxdma); priv->rxdma = NULL; } #endif /**************************************************************************** - * Name: stm32wb_serial_attach + * Name: stm32_serial_attach * * Description: * Configure the USART to operation in interrupt driven mode. This method @@ -1404,9 +1404,9 @@ static void stm32wb_serial_dmashutdown(struct uart_dev_s *dev) * ****************************************************************************/ -static int stm32wb_serial_attach(struct uart_dev_s *dev) +static int stm32_serial_attach(struct uart_dev_s *dev) { - struct stm32wb_serial_s *priv = (struct stm32wb_serial_s *)dev->priv; + struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; int ret; /* Attach and enable the IRQ */ @@ -1425,7 +1425,7 @@ static int stm32wb_serial_attach(struct uart_dev_s *dev) } /**************************************************************************** - * Name: stm32wb_serial_detach + * Name: stm32_serial_detach * * Description: * Detach USART interrupts. This method is called when the serial port is @@ -1434,9 +1434,9 @@ static int stm32wb_serial_attach(struct uart_dev_s *dev) * ****************************************************************************/ -static void stm32wb_serial_detach(struct uart_dev_s *dev) +static void stm32_serial_detach(struct uart_dev_s *dev) { - struct stm32wb_serial_s *priv = (struct stm32wb_serial_s *)dev->priv; + struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; up_disable_irq(priv->irq); irq_detach(priv->irq); } @@ -1455,7 +1455,7 @@ static void stm32wb_serial_detach(struct uart_dev_s *dev) static int up_interrupt(int irq, void *context, void *arg) { - struct stm32wb_serial_s *priv = (struct stm32wb_serial_s *)arg; + struct stm32_serial_s *priv = (struct stm32_serial_s *)arg; int passes; bool handled; @@ -1478,7 +1478,7 @@ static int up_interrupt(int irq, void *context, void *arg) /* Get the masked USART status word. */ - priv->sr = stm32wb_serial_getreg(priv, STM32_USART_ISR_OFFSET); + priv->sr = stm32_serial_getreg(priv, STM32_USART_ISR_OFFSET); /* USART interrupts: * @@ -1520,8 +1520,8 @@ static int up_interrupt(int irq, void *context, void *arg) (priv->ie & USART_CR1_TCIE) != 0 && (priv->ie & USART_CR1_TXEIE) == 0) { - stm32wb_gpiowrite(priv->rs485_dir_gpio, !priv->rs485_dir_polarity); - stm32wb_serial_restoreusartint(priv, priv->ie & ~USART_CR1_TCIE); + stm32_gpiowrite(priv->rs485_dir_gpio, !priv->rs485_dir_polarity); + stm32_serial_restoreusartint(priv, priv->ie & ~USART_CR1_TCIE); } #endif @@ -1550,7 +1550,7 @@ static int up_interrupt(int irq, void *context, void *arg) * interrupt clear register (ICR). */ - stm32wb_serial_putreg(priv, STM32_USART_ICR_OFFSET, + stm32_serial_putreg(priv, STM32_USART_ICR_OFFSET, (USART_ICR_NCF | USART_ICR_ORECF | USART_ICR_FECF)); } @@ -1571,14 +1571,14 @@ static int up_interrupt(int irq, void *context, void *arg) } /**************************************************************************** - * Name: stm32wb_serial_ioctl + * Name: stm32_serial_ioctl * * Description: * All ioctl calls will be routed through this method * ****************************************************************************/ -static int stm32wb_serial_ioctl(struct file *filep, int cmd, +static int stm32_serial_ioctl(struct file *filep, int cmd, unsigned long arg) { #if defined(CONFIG_SERIAL_TERMIOS) || defined(CONFIG_SERIAL_TIOCSERGSTRUCT) @@ -1586,7 +1586,7 @@ static int stm32wb_serial_ioctl(struct file *filep, int cmd, struct uart_dev_s *dev = inode->i_private; #endif #if defined(CONFIG_SERIAL_TERMIOS) - struct stm32wb_serial_s *priv = (struct stm32wb_serial_s *)dev->priv; + struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; #endif int ret = OK; @@ -1595,14 +1595,14 @@ static int stm32wb_serial_ioctl(struct file *filep, int cmd, #ifdef CONFIG_SERIAL_TIOCSERGSTRUCT case TIOCSERGSTRUCT: { - struct stm32wb_serial_s *user = (struct stm32wb_serial_s *)arg; + struct stm32_serial_s *user = (struct stm32_serial_s *)arg; if (!user) { ret = -EINVAL; } else { - memcpy(user, dev, sizeof(struct stm32wb_serial_s)); + memcpy(user, dev, sizeof(struct stm32_serial_s)); } } break; @@ -1619,19 +1619,19 @@ static int stm32wb_serial_ioctl(struct file *filep, int cmd, /* Get the original state of UE */ - cr1 = stm32wb_serial_getreg(priv, STM32_USART_CR1_OFFSET); + cr1 = stm32_serial_getreg(priv, STM32_USART_CR1_OFFSET); cr1_ue = cr1 & USART_CR1_UE; cr1 &= ~USART_CR1_UE; /* Disable UE, HDSEL can only be written when UE=0 */ - stm32wb_serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1); + stm32_serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1); /* Change the TX port to be open-drain/push-pull and enable/disable * half-duplex mode. */ - uint32_t cr = stm32wb_serial_getreg(priv, STM32_USART_CR3_OFFSET); + uint32_t cr = stm32_serial_getreg(priv, STM32_USART_CR3_OFFSET); if ((arg & SER_SINGLEWIRE_ENABLED) != 0) { @@ -1648,7 +1648,7 @@ static int stm32wb_serial_ioctl(struct file *filep, int cmd, if (priv->tx_gpio != 0) { - stm32wb_configgpio((priv->tx_gpio & ~(GPIO_PUPD_MASK | + stm32_configgpio((priv->tx_gpio & ~(GPIO_PUPD_MASK | GPIO_OPENDRAIN)) | gpio_val); } @@ -1659,7 +1659,7 @@ static int stm32wb_serial_ioctl(struct file *filep, int cmd, { if (priv->tx_gpio != 0) { - stm32wb_configgpio((priv->tx_gpio & ~(GPIO_PUPD_MASK | + stm32_configgpio((priv->tx_gpio & ~(GPIO_PUPD_MASK | GPIO_OPENDRAIN)) | GPIO_PUSHPULL); } @@ -1667,11 +1667,11 @@ static int stm32wb_serial_ioctl(struct file *filep, int cmd, cr &= ~USART_CR3_HDSEL; } - stm32wb_serial_putreg(priv, STM32_USART_CR3_OFFSET, cr); + stm32_serial_putreg(priv, STM32_USART_CR3_OFFSET, cr); /* Re-enable UE if appropriate */ - stm32wb_serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1 | cr1_ue); + stm32_serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1 | cr1_ue); leave_critical_section(flags); } break; @@ -1688,17 +1688,17 @@ static int stm32wb_serial_ioctl(struct file *filep, int cmd, /* Get the original state of UE */ - cr1 = stm32wb_serial_getreg(priv, STM32_USART_CR1_OFFSET); + cr1 = stm32_serial_getreg(priv, STM32_USART_CR1_OFFSET); cr1_ue = cr1 & USART_CR1_UE; cr1 &= ~USART_CR1_UE; /* Disable UE, {R,T}XINV can only be written when UE=0 */ - stm32wb_serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1); + stm32_serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1); /* Enable/disable signal inversion. */ - uint32_t cr = stm32wb_serial_getreg(priv, STM32_USART_CR2_OFFSET); + uint32_t cr = stm32_serial_getreg(priv, STM32_USART_CR2_OFFSET); if (arg & SER_INVERT_ENABLED_RX) { @@ -1718,11 +1718,11 @@ static int stm32wb_serial_ioctl(struct file *filep, int cmd, cr &= ~USART_CR2_TXINV; } - stm32wb_serial_putreg(priv, STM32_USART_CR2_OFFSET, cr); + stm32_serial_putreg(priv, STM32_USART_CR2_OFFSET, cr); /* Re-enable UE if appropriate */ - stm32wb_serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1 | cr1_ue); + stm32_serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1 | cr1_ue); leave_critical_section(flags); } break; @@ -1739,17 +1739,17 @@ static int stm32wb_serial_ioctl(struct file *filep, int cmd, /* Get the original state of UE */ - cr1 = stm32wb_serial_getreg(priv, STM32_USART_CR1_OFFSET); + cr1 = stm32_serial_getreg(priv, STM32_USART_CR1_OFFSET); cr1_ue = cr1 & USART_CR1_UE; cr1 &= ~USART_CR1_UE; /* Disable UE, SWAP can only be written when UE=0 */ - stm32wb_serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1); + stm32_serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1); /* Enable/disable Swap mode. */ - uint32_t cr = stm32wb_serial_getreg(priv, STM32_USART_CR2_OFFSET); + uint32_t cr = stm32_serial_getreg(priv, STM32_USART_CR2_OFFSET); if (arg == SER_SWAP_ENABLED) { @@ -1760,11 +1760,11 @@ static int stm32wb_serial_ioctl(struct file *filep, int cmd, cr &= ~USART_CR2_SWAP; } - stm32wb_serial_putreg(priv, STM32_USART_CR2_OFFSET, cr); + stm32_serial_putreg(priv, STM32_USART_CR2_OFFSET, cr); /* Re-enable UE if appropriate */ - stm32wb_serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1 | cr1_ue); + stm32_serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1 | cr1_ue); leave_critical_section(flags); } break; @@ -1860,7 +1860,7 @@ static int stm32wb_serial_ioctl(struct file *filep, int cmd, * TCSADRAIN / TCSAFLUSH */ - stm32wb_serial_setformat(dev); + stm32_serial_setformat(dev); } break; #endif /* CONFIG_SERIAL_TERMIOS */ @@ -1877,7 +1877,7 @@ static int stm32wb_serial_ioctl(struct file *filep, int cmd, priv->ie |= USART_CR1_IE_BREAK_INPROGRESS; - stm32wb_serial_txint(dev, false); + stm32_serial_txint(dev, false); /* Configure TX as a GPIO output pin and Send a break signal */ @@ -1885,7 +1885,7 @@ static int stm32wb_serial_ioctl(struct file *filep, int cmd, { uint32_t tx_break = GPIO_OUTPUT | (~(GPIO_MODE_MASK | GPIO_OUTPUT_SET) & priv->tx_gpio); - stm32wb_configgpio(tx_break); + stm32_configgpio(tx_break); } leave_critical_section(flags); @@ -1902,14 +1902,14 @@ static int stm32wb_serial_ioctl(struct file *filep, int cmd, if (priv->tx_gpio != 0) { - stm32wb_configgpio(priv->tx_gpio); + stm32_configgpio(priv->tx_gpio); } priv->ie &= ~USART_CR1_IE_BREAK_INPROGRESS; /* Enable further tx activity */ - stm32wb_serial_txint(dev, true); + stm32_serial_txint(dev, true); leave_critical_section(flags); } @@ -1921,8 +1921,8 @@ static int stm32wb_serial_ioctl(struct file *filep, int cmd, irqstate_t flags; flags = enter_critical_section(); - cr1 = stm32wb_serial_getreg(priv, STM32_USART_CR1_OFFSET); - stm32wb_serial_putreg(priv, STM32_USART_CR1_OFFSET, + cr1 = stm32_serial_getreg(priv, STM32_USART_CR1_OFFSET); + stm32_serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1 | USART_CR1_SBK); leave_critical_section(flags); } @@ -1934,8 +1934,8 @@ static int stm32wb_serial_ioctl(struct file *filep, int cmd, irqstate_t flags; flags = enter_critical_section(); - cr1 = stm32wb_serial_getreg(priv, STM32_USART_CR1_OFFSET); - stm32wb_serial_putreg(priv, STM32_USART_CR1_OFFSET, + cr1 = stm32_serial_getreg(priv, STM32_USART_CR1_OFFSET); + stm32_serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1 & ~USART_CR1_SBK); leave_critical_section(flags); } @@ -1952,7 +1952,7 @@ static int stm32wb_serial_ioctl(struct file *filep, int cmd, } /**************************************************************************** - * Name: stm32wb_serial_receive + * Name: stm32_serial_receive * * Description: * Called (usually) from the interrupt level to receive one @@ -1962,15 +1962,15 @@ static int stm32wb_serial_ioctl(struct file *filep, int cmd, ****************************************************************************/ #ifndef SERIAL_HAVE_ONLY_DMA -static int stm32wb_serial_receive(struct uart_dev_s *dev, +static int stm32_serial_receive(struct uart_dev_s *dev, unsigned int *status) { - struct stm32wb_serial_s *priv = (struct stm32wb_serial_s *)dev->priv; + struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; uint32_t rdr; /* Get the Rx byte */ - rdr = stm32wb_serial_getreg(priv, STM32_USART_RDR_OFFSET); + rdr = stm32_serial_getreg(priv, STM32_USART_RDR_OFFSET); /* Get the Rx byte plux error information. Return those in status */ @@ -1984,7 +1984,7 @@ static int stm32wb_serial_receive(struct uart_dev_s *dev, #endif /**************************************************************************** - * Name: stm32wb_serial_rxint + * Name: stm32_serial_rxint * * Description: * Call to enable or disable RX interrupts @@ -1992,9 +1992,9 @@ static int stm32wb_serial_receive(struct uart_dev_s *dev, ****************************************************************************/ #ifndef SERIAL_HAVE_ONLY_DMA -static void stm32wb_serial_rxint(struct uart_dev_s *dev, bool enable) +static void stm32_serial_rxint(struct uart_dev_s *dev, bool enable) { - struct stm32wb_serial_s *priv = (struct stm32wb_serial_s *)dev->priv; + struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; irqstate_t flags; uint16_t ie; @@ -2040,13 +2040,13 @@ static void stm32wb_serial_rxint(struct uart_dev_s *dev, bool enable) /* Then set the new interrupt state */ - stm32wb_serial_restoreusartint(priv, ie); + stm32_serial_restoreusartint(priv, ie); leave_critical_section(flags); } #endif /**************************************************************************** - * Name: stm32wb_serial_rxavailable + * Name: stm32_serial_rxavailable * * Description: * Return true if the receive register is not empty @@ -2054,17 +2054,17 @@ static void stm32wb_serial_rxint(struct uart_dev_s *dev, bool enable) ****************************************************************************/ #ifndef SERIAL_HAVE_ONLY_DMA -static bool stm32wb_serial_rxavailable(struct uart_dev_s *dev) +static bool stm32_serial_rxavailable(struct uart_dev_s *dev) { - struct stm32wb_serial_s *priv = (struct stm32wb_serial_s *)dev->priv; + struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; - return ((stm32wb_serial_getreg(priv, STM32_USART_ISR_OFFSET) & + return ((stm32_serial_getreg(priv, STM32_USART_ISR_OFFSET) & USART_ISR_RXNE) != 0); } #endif /**************************************************************************** - * Name: stm32wb_serial_rxflowcontrol + * Name: stm32_serial_rxflowcontrol * * Description: * Called when Rx buffer is full (or exceeds configured watermark levels @@ -2087,10 +2087,10 @@ static bool stm32wb_serial_rxavailable(struct uart_dev_s *dev) ****************************************************************************/ #ifdef CONFIG_SERIAL_IFLOWCONTROL -static bool stm32wb_serial_rxflowcontrol(struct uart_dev_s *dev, +static bool stm32_serial_rxflowcontrol(struct uart_dev_s *dev, unsigned int nbuffered, bool upper) { - struct stm32wb_serial_s *priv = (struct stm32wb_serial_s *)dev->priv; + struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; #if defined(CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS) && \ defined(CONFIG_STM32WB_FLOWCONTROL_BROKEN) @@ -2098,7 +2098,7 @@ static bool stm32wb_serial_rxflowcontrol(struct uart_dev_s *dev, { /* Assert/de-assert nRTS set it high resume/stop sending */ - stm32wb_gpiowrite(priv->rts_gpio, upper); + stm32_gpiowrite(priv->rts_gpio, upper); if (upper) { @@ -2160,7 +2160,7 @@ static bool stm32wb_serial_rxflowcontrol(struct uart_dev_s *dev, #endif /**************************************************************************** - * Name: stm32wb_serial_dmareceive + * Name: stm32_serial_dmareceive * * Description: * Called (usually) from the interrupt level to receive one @@ -2170,13 +2170,13 @@ static bool stm32wb_serial_rxflowcontrol(struct uart_dev_s *dev, ****************************************************************************/ #ifdef SERIAL_HAVE_RXDMA -static int stm32wb_serial_dmareceive(struct uart_dev_s *dev, +static int stm32_serial_dmareceive(struct uart_dev_s *dev, unsigned int *status) { - struct stm32wb_serial_s *priv = (struct stm32wb_serial_s *)dev->priv; + struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; int c = 0; - if (stm32wb_serial_dmanextrx(priv) != priv->rxdmanext) + if (stm32_serial_dmanextrx(priv) != priv->rxdmanext) { c = priv->rxfifo[priv->rxdmanext]; @@ -2203,7 +2203,7 @@ static int stm32wb_serial_dmareceive(struct uart_dev_s *dev, #endif /**************************************************************************** - * Name: stm32wb_serial_dmareenable + * Name: stm32_serial_dmareenable * * Description: * Call to re-enable RX DMA. @@ -2211,14 +2211,14 @@ static int stm32wb_serial_dmareceive(struct uart_dev_s *dev, ****************************************************************************/ #if defined(SERIAL_HAVE_RXDMA) -static void stm32wb_serial_dmareenable(struct stm32wb_serial_s *priv) +static void stm32_serial_dmareenable(struct stm32_serial_s *priv) { #ifdef CONFIG_SERIAL_IFLOWCONTROL if (priv->iflow) { /* Configure for non-circular DMA reception into the RX FIFO */ - stm32wb_dmasetup(priv->rxdma, + stm32_dmasetup(priv->rxdma, priv->usartbase + STM32_USART_RDR_OFFSET, (uint32_t)priv->rxfifo, RXDMA_BUFFER_SIZE, @@ -2229,7 +2229,7 @@ static void stm32wb_serial_dmareenable(struct stm32wb_serial_s *priv) { /* Configure for circular DMA reception into the RX FIFO */ - stm32wb_dmasetup(priv->rxdma, + stm32_dmasetup(priv->rxdma, priv->usartbase + STM32_USART_RDR_OFFSET, (uint32_t)priv->rxfifo, RXDMA_BUFFER_SIZE, @@ -2250,7 +2250,7 @@ static void stm32wb_serial_dmareenable(struct stm32wb_serial_s *priv) * in and DMA transfer is stopped. */ - stm32wb_dmastart(priv->rxdma, stm32wb_serial_dmarxcallback, priv, + stm32_dmastart(priv->rxdma, stm32_serial_dmarxcallback, priv, false); } else @@ -2261,7 +2261,7 @@ static void stm32wb_serial_dmareenable(struct stm32wb_serial_s *priv) * worth of time to claim bytes before they are overwritten. */ - stm32wb_dmastart(priv->rxdma, stm32wb_serial_dmarxcallback, priv, + stm32_dmastart(priv->rxdma, stm32_serial_dmarxcallback, priv, true); } @@ -2274,7 +2274,7 @@ static void stm32wb_serial_dmareenable(struct stm32wb_serial_s *priv) #endif /**************************************************************************** - * Name: stm32wb_serial_dmaiflowrestart + * Name: stm32_serial_dmaiflowrestart * * Description: * Call to restart RX DMA for input flow-controlled USART @@ -2282,7 +2282,7 @@ static void stm32wb_serial_dmareenable(struct stm32wb_serial_s *priv) ****************************************************************************/ #if defined(SERIAL_HAVE_RXDMA) && defined(CONFIG_SERIAL_IFLOWCONTROL) -static bool stm32wb_serial_dmaiflowrestart(struct stm32wb_serial_s *priv) +static bool stm32_serial_dmaiflowrestart(struct stm32_serial_s *priv) { if (!priv->rxenable) { @@ -2298,7 +2298,7 @@ static bool stm32wb_serial_dmaiflowrestart(struct stm32wb_serial_s *priv) { /* Rx DMA in suspended state. */ - if (stm32wb_serial_dmarxavailable(&priv->dev)) + if (stm32_serial_dmarxavailable(&priv->dev)) { /* DMA buffer has unprocessed data, do not re-enable yet. */ @@ -2316,14 +2316,14 @@ static bool stm32wb_serial_dmaiflowrestart(struct stm32wb_serial_s *priv) * re-enabling without data loss is now safe. */ - stm32wb_serial_dmareenable(priv); + stm32_serial_dmareenable(priv); return true; } #endif /**************************************************************************** - * Name: stm32wb_serial_dmarxint + * Name: stm32_serial_dmarxint * * Description: * Call to enable or disable RX interrupts @@ -2331,9 +2331,9 @@ static bool stm32wb_serial_dmaiflowrestart(struct stm32wb_serial_s *priv) ****************************************************************************/ #ifdef SERIAL_HAVE_RXDMA -static void stm32wb_serial_dmarxint(struct uart_dev_s *dev, bool enable) +static void stm32_serial_dmarxint(struct uart_dev_s *dev, bool enable) { - struct stm32wb_serial_s *priv = (struct stm32wb_serial_s *)dev->priv; + struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; /* En/disable DMA reception. * @@ -2350,14 +2350,14 @@ static void stm32wb_serial_dmarxint(struct uart_dev_s *dev, bool enable) { /* Re-enable RX DMA. */ - stm32wb_serial_dmaiflowrestart(priv); + stm32_serial_dmaiflowrestart(priv); } #endif } #endif /**************************************************************************** - * Name: stm32wb_serial_dmarxavailable + * Name: stm32_serial_dmarxavailable * * Description: * Return true if the receive register is not empty @@ -2365,51 +2365,51 @@ static void stm32wb_serial_dmarxint(struct uart_dev_s *dev, bool enable) ****************************************************************************/ #ifdef SERIAL_HAVE_RXDMA -static bool stm32wb_serial_dmarxavailable(struct uart_dev_s *dev) +static bool stm32_serial_dmarxavailable(struct uart_dev_s *dev) { - struct stm32wb_serial_s *priv = (struct stm32wb_serial_s *)dev->priv; + struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; /* Compare our receive pointer to the current DMA pointer, if they * do not match, then there are bytes to be received. */ - return (stm32wb_serial_dmanextrx(priv) != priv->rxdmanext); + return (stm32_serial_dmanextrx(priv) != priv->rxdmanext); } #endif /**************************************************************************** - * Name: stm32wb_serial_send + * Name: stm32_serial_send * * Description: * This method will send one byte on the USART * ****************************************************************************/ -static void stm32wb_serial_send(struct uart_dev_s *dev, int ch) +static void stm32_serial_send(struct uart_dev_s *dev, int ch) { - struct stm32wb_serial_s *priv = (struct stm32wb_serial_s *)dev->priv; + struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; #ifdef HAVE_RS485 if (priv->rs485_dir_gpio != 0) { - stm32wb_gpiowrite(priv->rs485_dir_gpio, priv->rs485_dir_polarity); + stm32_gpiowrite(priv->rs485_dir_gpio, priv->rs485_dir_polarity); } #endif - stm32wb_serial_putreg(priv, STM32_USART_TDR_OFFSET, (uint32_t)ch); + stm32_serial_putreg(priv, STM32_USART_TDR_OFFSET, (uint32_t)ch); } /**************************************************************************** - * Name: stm32wb_serial_txint + * Name: stm32_serial_txint * * Description: * Call to enable or disable TX interrupts * ****************************************************************************/ -static void stm32wb_serial_txint(struct uart_dev_s *dev, bool enable) +static void stm32_serial_txint(struct uart_dev_s *dev, bool enable) { - struct stm32wb_serial_s *priv = (struct stm32wb_serial_s *)dev->priv; + struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; irqstate_t flags; @@ -2452,7 +2452,7 @@ static void stm32wb_serial_txint(struct uart_dev_s *dev, bool enable) } # endif - stm32wb_serial_restoreusartint(priv, ie); + stm32_serial_restoreusartint(priv, ie); /* Fake a TX interrupt here by just calling uart_xmitchars() with * interrupts disabled (note this may recurse). @@ -2465,29 +2465,29 @@ static void stm32wb_serial_txint(struct uart_dev_s *dev, bool enable) { /* Disable the TX interrupt */ - stm32wb_serial_restoreusartint(priv, priv->ie & ~USART_CR1_TXEIE); + stm32_serial_restoreusartint(priv, priv->ie & ~USART_CR1_TXEIE); } leave_critical_section(flags); } /**************************************************************************** - * Name: stm32wb_serial_txready + * Name: stm32_serial_txready * * Description: * Return true if the transmit data register is empty * ****************************************************************************/ -static bool stm32wb_serial_txready(struct uart_dev_s *dev) +static bool stm32_serial_txready(struct uart_dev_s *dev) { - struct stm32wb_serial_s *priv = (struct stm32wb_serial_s *)dev->priv; - return ((stm32wb_serial_getreg(priv, STM32_USART_ISR_OFFSET) & + struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; + return ((stm32_serial_getreg(priv, STM32_USART_ISR_OFFSET) & USART_ISR_TXE) != 0); } /**************************************************************************** - * Name: stm32wb_serial_dmarxcallback + * Name: stm32_serial_dmarxcallback * * Description: * This function checks the current DMA state and calls the generic @@ -2496,12 +2496,12 @@ static bool stm32wb_serial_txready(struct uart_dev_s *dev) ****************************************************************************/ #ifdef SERIAL_HAVE_RXDMA -static void stm32wb_serial_dmarxcallback(DMA_HANDLE handle, uint8_t status, +static void stm32_serial_dmarxcallback(DMA_HANDLE handle, uint8_t status, void *arg) { - struct stm32wb_serial_s *priv = (struct stm32wb_serial_s *)arg; + struct stm32_serial_s *priv = (struct stm32_serial_s *)arg; - if (priv->rxenable && stm32wb_serial_dmarxavailable(&priv->dev)) + if (priv->rxenable && stm32_serial_dmarxavailable(&priv->dev)) { uart_recvchars(&priv->dev); @@ -2510,7 +2510,7 @@ static void stm32wb_serial_dmarxcallback(DMA_HANDLE handle, uint8_t status, { /* Re-enable RX DMA. */ - stm32wb_serial_dmaiflowrestart(priv); + stm32_serial_dmaiflowrestart(priv); } #endif } @@ -2525,11 +2525,11 @@ static void stm32wb_serial_dmarxcallback(DMA_HANDLE handle, uint8_t status, * will release Rx DMA. */ - priv->sr = stm32wb_serial_getreg(priv, STM32_USART_ISR_OFFSET); + priv->sr = stm32_serial_getreg(priv, STM32_USART_ISR_OFFSET); if ((priv->sr & (USART_ISR_ORE | USART_ISR_NE | USART_ISR_FE)) != 0) { - stm32wb_serial_putreg(priv, STM32_USART_ICR_OFFSET, + stm32_serial_putreg(priv, STM32_USART_ICR_OFFSET, (USART_ICR_NCF | USART_ICR_ORECF | USART_ICR_FECF)); } @@ -2537,7 +2537,7 @@ static void stm32wb_serial_dmarxcallback(DMA_HANDLE handle, uint8_t status, #endif /**************************************************************************** - * Name: stm32wb_serial_pmnotify + * Name: stm32_serial_pmnotify * * Description: * Notify the driver of new power state. This callback is called after @@ -2559,17 +2559,17 @@ static void stm32wb_serial_dmarxcallback(DMA_HANDLE handle, uint8_t status, ****************************************************************************/ #ifdef CONFIG_PM -static void stm32wb_serial_pmnotify(struct pm_callback_s *cb, int domain, +static void stm32_serial_pmnotify(struct pm_callback_s *cb, int domain, enum pm_state_e pmstate) { switch (pmstate) { case PM_NORMAL: - stm32wb_serial_pm_setsuspend(false); + stm32_serial_pm_setsuspend(false); break; case PM_IDLE: - stm32wb_serial_pm_setsuspend(false); + stm32_serial_pm_setsuspend(false); break; case PM_STANDBY: @@ -2579,11 +2579,11 @@ static void stm32wb_serial_pmnotify(struct pm_callback_s *cb, int domain, * Rx/Tx buffers are empty (checked in pmprepare). */ - stm32wb_serial_pm_setsuspend(true); + stm32_serial_pm_setsuspend(true); break; case PM_SLEEP: - stm32wb_serial_pm_setsuspend(true); + stm32_serial_pm_setsuspend(true); break; default: @@ -2594,7 +2594,7 @@ static void stm32wb_serial_pmnotify(struct pm_callback_s *cb, int domain, #endif /**************************************************************************** - * Name: stm32wb_serial_pmprepare + * Name: stm32_serial_pmprepare * * Description: * Request the driver to prepare for a new power state. This is a warning @@ -2627,7 +2627,7 @@ static void stm32wb_serial_pmnotify(struct pm_callback_s *cb, int domain, ****************************************************************************/ #ifdef CONFIG_PM -static int stm32wb_serial_pmprepare(struct pm_callback_s *cb, int domain, +static int stm32_serial_pmprepare(struct pm_callback_s *cb, int domain, enum pm_state_e pmstate) { int n; @@ -2648,7 +2648,7 @@ static int stm32wb_serial_pmprepare(struct pm_callback_s *cb, int domain, * buffers. */ - stm32wb_serial_dma_poll(); + stm32_serial_dma_poll(); #endif /* Check if any of the active ports have data pending on Tx/Rx @@ -2657,7 +2657,7 @@ static int stm32wb_serial_pmprepare(struct pm_callback_s *cb, int domain, for (n = 0; n < STM32_NLPUART + STM32_NUSART; n++) { - struct stm32wb_serial_s *priv = g_uart_devs[n]; + struct stm32_serial_s *priv = g_uart_devs[n]; if (!priv || !priv->initialized) { @@ -2727,14 +2727,14 @@ void arm_earlyserialinit(void) { if (g_uart_devs[i]) { - stm32wb_serial_disableusartint(g_uart_devs[i], NULL); + stm32_serial_disableusartint(g_uart_devs[i], NULL); } } /* Configure whichever one is the console */ #if CONSOLE_UART > 0 - stm32wb_serial_setup(&g_uart_devs[CONSOLE_UART - 1]->dev); + stm32_serial_setup(&g_uart_devs[CONSOLE_UART - 1]->dev); #endif #endif /* HAVE UART */ } @@ -2779,7 +2779,7 @@ void arm_serialinit(void) #ifdef SERIAL_HAVE_CONSOLE_DMA /* If we need to re-initialise the console to enable DMA do that here. */ - stm32wb_serial_dmasetup(&g_uart_devs[CONSOLE_UART - 1]->dev); + stm32_serial_dmasetup(&g_uart_devs[CONSOLE_UART - 1]->dev); #endif #endif /* CONSOLE_UART > 0 */ @@ -2814,7 +2814,7 @@ void arm_serialinit(void) } /**************************************************************************** - * Name: stm32wb_serial_dma_poll + * Name: stm32_serial_dma_poll * * Description: * Checks receive DMA buffers for received bytes that have not accumulated @@ -2825,7 +2825,7 @@ void arm_serialinit(void) ****************************************************************************/ #ifdef SERIAL_HAVE_RXDMA -void stm32wb_serial_dma_poll(void) +void stm32_serial_dma_poll(void) { irqstate_t flags; @@ -2834,14 +2834,14 @@ void stm32wb_serial_dma_poll(void) #ifdef CONFIG_LPUART1_RXDMA if (g_lpuart1priv.rxdma != NULL) { - stm32wb_serial_dmarxcallback(g_lpuart1priv.rxdma, 0, &g_lpuart1priv); + stm32_serial_dmarxcallback(g_lpuart1priv.rxdma, 0, &g_lpuart1priv); } #endif #ifdef CONFIG_USART1_RXDMA if (g_usart1priv.rxdma != NULL) { - stm32wb_serial_dmarxcallback(g_usart1priv.rxdma, 0, &g_usart1priv); + stm32_serial_dmarxcallback(g_usart1priv.rxdma, 0, &g_usart1priv); } #endif @@ -2860,12 +2860,12 @@ void stm32wb_serial_dma_poll(void) void up_putc(int ch) { #if CONSOLE_UART > 0 - struct stm32wb_serial_s *priv = g_uart_devs[CONSOLE_UART - 1]; + struct stm32_serial_s *priv = g_uart_devs[CONSOLE_UART - 1]; uint16_t ie; - stm32wb_serial_disableusartint(priv, &ie); + stm32_serial_disableusartint(priv, &ie); arm_lowputc(ch); - stm32wb_serial_restoreusartint(priv, ie); + stm32_serial_restoreusartint(priv, ie); #endif } diff --git a/arch/arm/src/stm32wb/stm32wb_spi.c b/arch/arm/src/stm32wb/stm32wb_spi.c index 67e1cf36b01..84e96d003b6 100644 --- a/arch/arm/src/stm32wb/stm32wb_spi.c +++ b/arch/arm/src/stm32wb/stm32wb_spi.c @@ -21,22 +21,22 @@ ****************************************************************************/ /**************************************************************************** - * The external functions, stm32wb_spi1/2select and stm32wb_spi1/2status + * The external functions, stm32_spi1/2select and stm32_spi1/2status * must be provided by board-specific logic. They are implementations of the * select and status methods of the SPI interface defined by struct spi_ops_s * (see include/nuttx/spi/spi.h). All other methods (including - * stm32wb_spibus_initialize()) are provided by common STM32 logic. To use + * stm32_spibus_initialize()) are provided by common STM32 logic. To use * this common SPI logic on your board: * - * 1. Provide logic in stm32wb_board_initialize() to configure SPI chip + * 1. Provide logic in stm32_board_initialize() to configure SPI chip * select pins. - * 2. Provide stm32wb_spi1/2select() and stm32wb_spi1/2status() + * 2. Provide stm32_spi1/2select() and stm32_spi1/2status() * functions in your board-specific logic. These functions will perform * chip selection and status operations using GPIOs in the way your * board is configured. - * 3. Add a calls to stm32wb_spibus_initialize() in your low level + * 3. Add a calls to stm32_spibus_initialize() in your low level * application initialization logic - * 4. The handle returned by stm32wb_spibus_initialize() may then be used + * 4. The handle returned by stm32_spibus_initialize() may then be used * to bind the SPI driver to higher level logic (e.g., calling * mmcsd_spislotinitialize(), for example, will bind the SPI driver to * the SPI MMC/SD driver). @@ -73,7 +73,7 @@ #include "arm_internal.h" #include "chip.h" -#include "stm32wb.h" +#include "stm32.h" #include "stm32wb_gpio.h" #include "stm32wb_dma.h" #include "stm32wb_spi.h" @@ -131,7 +131,7 @@ * Private Types ****************************************************************************/ -struct stm32wb_spidev_s +struct stm32_spidev_s { struct spi_dev_s spidev; /* Externally visible part of the SPI interface */ uint32_t spibase; /* SPIn base address */ @@ -172,34 +172,34 @@ struct stm32wb_spidev_s /* Helpers */ -static inline uint16_t spi_getreg(struct stm32wb_spidev_s *priv, +static inline uint16_t spi_getreg(struct stm32_spidev_s *priv, uint8_t offset); -static inline void spi_putreg(struct stm32wb_spidev_s *priv, +static inline void spi_putreg(struct stm32_spidev_s *priv, uint8_t offset, uint16_t value); -static inline uint16_t spi_readword(struct stm32wb_spidev_s *priv); -static inline void spi_writeword(struct stm32wb_spidev_s *priv, +static inline uint16_t spi_readword(struct stm32_spidev_s *priv); +static inline void spi_writeword(struct stm32_spidev_s *priv, uint16_t byte); -static inline bool spi_16bitmode(struct stm32wb_spidev_s *priv); +static inline bool spi_16bitmode(struct stm32_spidev_s *priv); /* DMA support */ #ifdef CONFIG_STM32WB_SPI_DMA -static int spi_dmarxwait(struct stm32wb_spidev_s *priv); -static int spi_dmatxwait(struct stm32wb_spidev_s *priv); -static inline void spi_dmarxwakeup(struct stm32wb_spidev_s *priv); -static inline void spi_dmatxwakeup(struct stm32wb_spidev_s *priv); +static int spi_dmarxwait(struct stm32_spidev_s *priv); +static int spi_dmatxwait(struct stm32_spidev_s *priv); +static inline void spi_dmarxwakeup(struct stm32_spidev_s *priv); +static inline void spi_dmatxwakeup(struct stm32_spidev_s *priv); static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg); static void spi_dmatxcallback(DMA_HANDLE handle, uint8_t isr, void *arg); -static void spi_dmarxsetup(struct stm32wb_spidev_s *priv, +static void spi_dmarxsetup(struct stm32_spidev_s *priv, void *rxbuffer, void *rxdummy, size_t nwords); -static void spi_dmatxsetup(struct stm32wb_spidev_s *priv, +static void spi_dmatxsetup(struct stm32_spidev_s *priv, const void *txbuffer, const void *txdummy, size_t nwords); -static inline void spi_dmarxstart(struct stm32wb_spidev_s *priv); -static inline void spi_dmatxstart(struct stm32wb_spidev_s *priv); +static inline void spi_dmarxstart(struct stm32_spidev_s *priv); +static inline void spi_dmatxstart(struct stm32_spidev_s *priv); #endif /* SPI methods */ @@ -230,7 +230,7 @@ static void spi_recvblock(struct spi_dev_s *dev, /* Initialization */ -static void spi_bus_initialize(struct stm32wb_spidev_s *priv); +static void spi_bus_initialize(struct stm32_spidev_s *priv); /* PM interface */ @@ -247,16 +247,16 @@ static int spi_pm_prepare(struct pm_callback_s *cb, int domain, static const struct spi_ops_s g_spi1ops = { .lock = spi_lock, - .select = stm32wb_spi1select, + .select = stm32_spi1select, .setfrequency = spi_setfrequency, .setmode = spi_setmode, .setbits = spi_setbits, #ifdef CONFIG_SPI_HWFEATURES .hwfeatures = spi_hwfeatures, #endif - .status = stm32wb_spi1status, + .status = stm32_spi1status, #ifdef CONFIG_SPI_CMDDATA - .cmddata = stm32wb_spi1cmddata, + .cmddata = stm32_spi1cmddata, #endif .send = spi_send, #ifdef CONFIG_SPI_EXCHANGE @@ -269,13 +269,13 @@ static const struct spi_ops_s g_spi1ops = .trigger = spi_trigger, #endif #ifdef CONFIG_SPI_CALLBACK - .registercallback = stm32wb_spi1register, /* Provided externally */ + .registercallback = stm32_spi1register, /* Provided externally */ #else .registercallback = 0, /* Not implemented */ #endif }; -static struct stm32wb_spidev_s g_spi1dev = +static struct stm32_spidev_s g_spi1dev = { .spidev = { @@ -305,16 +305,16 @@ static struct stm32wb_spidev_s g_spi1dev = static const struct spi_ops_s g_spi2ops = { .lock = spi_lock, - .select = stm32wb_spi2select, + .select = stm32_spi2select, .setfrequency = spi_setfrequency, .setmode = spi_setmode, .setbits = spi_setbits, #ifdef CONFIG_SPI_HWFEATURES .hwfeatures = spi_hwfeatures, #endif - .status = stm32wb_spi2status, + .status = stm32_spi2status, #ifdef CONFIG_SPI_CMDDATA - .cmddata = stm32wb_spi2cmddata, + .cmddata = stm32_spi2cmddata, #endif .send = spi_send, #ifdef CONFIG_SPI_EXCHANGE @@ -327,13 +327,13 @@ static const struct spi_ops_s g_spi2ops = .trigger = spi_trigger, #endif #ifdef CONFIG_SPI_CALLBACK - .registercallback = stm32wb_spi2register, /* provided externally */ + .registercallback = stm32_spi2register, /* provided externally */ #else .registercallback = 0, /* not implemented */ #endif }; -static struct stm32wb_spidev_s g_spi2dev = +static struct stm32_spidev_s g_spi2dev = { .spidev = { @@ -376,7 +376,7 @@ static struct stm32wb_spidev_s g_spi2dev = * ****************************************************************************/ -static inline uint16_t spi_getreg(struct stm32wb_spidev_s *priv, +static inline uint16_t spi_getreg(struct stm32_spidev_s *priv, uint8_t offset) { return getreg16(priv->spibase + offset); @@ -398,7 +398,7 @@ static inline uint16_t spi_getreg(struct stm32wb_spidev_s *priv, * ****************************************************************************/ -static inline void spi_putreg(struct stm32wb_spidev_s *priv, +static inline void spi_putreg(struct stm32_spidev_s *priv, uint8_t offset, uint16_t value) { putreg16(value, priv->spibase + offset); @@ -419,7 +419,7 @@ static inline void spi_putreg(struct stm32wb_spidev_s *priv, * ****************************************************************************/ -static inline uint8_t spi_getreg8(struct stm32wb_spidev_s *priv, +static inline uint8_t spi_getreg8(struct stm32_spidev_s *priv, uint8_t offset) { return getreg8(priv->spibase + offset); @@ -438,7 +438,7 @@ static inline uint8_t spi_getreg8(struct stm32wb_spidev_s *priv, * ****************************************************************************/ -static inline void spi_putreg8(struct stm32wb_spidev_s *priv, +static inline void spi_putreg8(struct stm32_spidev_s *priv, uint8_t offset, uint8_t value) { putreg8(value, priv->spibase + offset); @@ -458,7 +458,7 @@ static inline void spi_putreg8(struct stm32wb_spidev_s *priv, * ****************************************************************************/ -static inline uint16_t spi_readword(struct stm32wb_spidev_s *priv) +static inline uint16_t spi_readword(struct stm32_spidev_s *priv) { /* Wait until the receive buffer is not empty */ @@ -483,7 +483,7 @@ static inline uint16_t spi_readword(struct stm32wb_spidev_s *priv) * ****************************************************************************/ -static inline uint8_t spi_readbyte(struct stm32wb_spidev_s *priv) +static inline uint8_t spi_readbyte(struct stm32_spidev_s *priv) { /* Wait until the receive buffer is not empty */ @@ -509,7 +509,7 @@ static inline uint8_t spi_readbyte(struct stm32wb_spidev_s *priv) * ****************************************************************************/ -static inline void spi_writeword(struct stm32wb_spidev_s *priv, +static inline void spi_writeword(struct stm32_spidev_s *priv, uint16_t word) { /* Wait until the transmit buffer is empty */ @@ -536,7 +536,7 @@ static inline void spi_writeword(struct stm32wb_spidev_s *priv, * ****************************************************************************/ -static inline void spi_writebyte(struct stm32wb_spidev_s *priv, +static inline void spi_writebyte(struct stm32_spidev_s *priv, uint8_t byte) { /* Wait until the transmit buffer is empty */ @@ -562,7 +562,7 @@ static inline void spi_writebyte(struct stm32wb_spidev_s *priv, * ****************************************************************************/ -static inline bool spi_16bitmode(struct stm32wb_spidev_s *priv) +static inline bool spi_16bitmode(struct stm32_spidev_s *priv) { return (priv->nbits > 8); } @@ -576,7 +576,7 @@ static inline bool spi_16bitmode(struct stm32wb_spidev_s *priv) ****************************************************************************/ #ifdef CONFIG_STM32WB_SPI_DMA -static int spi_dmarxwait(struct stm32wb_spidev_s *priv) +static int spi_dmarxwait(struct stm32_spidev_s *priv) { int ret; @@ -609,7 +609,7 @@ static int spi_dmarxwait(struct stm32wb_spidev_s *priv) ****************************************************************************/ #ifdef CONFIG_STM32WB_SPI_DMA -static int spi_dmatxwait(struct stm32wb_spidev_s *priv) +static int spi_dmatxwait(struct stm32_spidev_s *priv) { int ret; @@ -642,7 +642,7 @@ static int spi_dmatxwait(struct stm32wb_spidev_s *priv) ****************************************************************************/ #ifdef CONFIG_STM32WB_SPI_DMA -static inline void spi_dmarxwakeup(struct stm32wb_spidev_s *priv) +static inline void spi_dmarxwakeup(struct stm32_spidev_s *priv) { nxsem_post(&priv->rxsem); } @@ -657,7 +657,7 @@ static inline void spi_dmarxwakeup(struct stm32wb_spidev_s *priv) ****************************************************************************/ #ifdef CONFIG_STM32WB_SPI_DMA -static inline void spi_dmatxwakeup(struct stm32wb_spidev_s *priv) +static inline void spi_dmatxwakeup(struct stm32_spidev_s *priv) { nxsem_post(&priv->txsem); } @@ -674,7 +674,7 @@ static inline void spi_dmatxwakeup(struct stm32wb_spidev_s *priv) #ifdef CONFIG_STM32WB_SPI_DMA static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) { - struct stm32wb_spidev_s *priv = (struct stm32wb_spidev_s *)arg; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)arg; /* Wake-up the SPI driver */ @@ -694,7 +694,7 @@ static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) #ifdef CONFIG_STM32WB_SPI_DMA static void spi_dmatxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) { - struct stm32wb_spidev_s *priv = (struct stm32wb_spidev_s *)arg; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)arg; /* Wake-up the SPI driver */ @@ -712,7 +712,7 @@ static void spi_dmatxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) ****************************************************************************/ #ifdef CONFIG_STM32WB_SPI_DMA -static void spi_dmarxsetup(struct stm32wb_spidev_s *priv, +static void spi_dmarxsetup(struct stm32_spidev_s *priv, void *rxbuffer, void *rxdummy, size_t nwords) { /* 8- or 16-bit mode? */ @@ -748,7 +748,7 @@ static void spi_dmarxsetup(struct stm32wb_spidev_s *priv, /* Configure the RX DMA */ - stm32wb_dmasetup(priv->rxdma, priv->spibase + STM32_SPI_DR_OFFSET, + stm32_dmasetup(priv->rxdma, priv->spibase + STM32_SPI_DR_OFFSET, (uint32_t)rxbuffer, nwords, priv->rxccr); } #endif @@ -762,7 +762,7 @@ static void spi_dmarxsetup(struct stm32wb_spidev_s *priv, ****************************************************************************/ #ifdef CONFIG_STM32WB_SPI_DMA -static void spi_dmatxsetup(struct stm32wb_spidev_s *priv, +static void spi_dmatxsetup(struct stm32_spidev_s *priv, const void *txbuffer, const void *txdummy, size_t nwords) { @@ -799,7 +799,7 @@ static void spi_dmatxsetup(struct stm32wb_spidev_s *priv, /* Setup the TX DMA */ - stm32wb_dmasetup(priv->txdma, priv->spibase + STM32_SPI_DR_OFFSET, + stm32_dmasetup(priv->txdma, priv->spibase + STM32_SPI_DR_OFFSET, (uint32_t)txbuffer, nwords, priv->txccr); } #endif @@ -813,10 +813,10 @@ static void spi_dmatxsetup(struct stm32wb_spidev_s *priv, ****************************************************************************/ #ifdef CONFIG_STM32WB_SPI_DMA -static inline void spi_dmarxstart(struct stm32wb_spidev_s *priv) +static inline void spi_dmarxstart(struct stm32_spidev_s *priv) { priv->rxresult = 0; - stm32wb_dmastart(priv->rxdma, spi_dmarxcallback, priv, false); + stm32_dmastart(priv->rxdma, spi_dmarxcallback, priv, false); } #endif @@ -829,10 +829,10 @@ static inline void spi_dmarxstart(struct stm32wb_spidev_s *priv) ****************************************************************************/ #ifdef CONFIG_STM32WB_SPI_DMA -static inline void spi_dmatxstart(struct stm32wb_spidev_s *priv) +static inline void spi_dmatxstart(struct stm32_spidev_s *priv) { priv->txresult = 0; - stm32wb_dmastart(priv->txdma, spi_dmatxcallback, priv, false); + stm32_dmastart(priv->txdma, spi_dmatxcallback, priv, false); } #endif @@ -852,7 +852,7 @@ static inline void spi_dmatxstart(struct stm32wb_spidev_s *priv) * ****************************************************************************/ -static void spi_modifycr(uint32_t addr, struct stm32wb_spidev_s *priv, +static void spi_modifycr(uint32_t addr, struct stm32_spidev_s *priv, uint16_t setbits, uint16_t clrbits) { uint16_t cr; @@ -886,7 +886,7 @@ static void spi_modifycr(uint32_t addr, struct stm32wb_spidev_s *priv, static int spi_lock(struct spi_dev_s *dev, bool lock) { - struct stm32wb_spidev_s *priv = (struct stm32wb_spidev_s *)dev; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; int ret; if (lock) @@ -918,7 +918,7 @@ static int spi_lock(struct spi_dev_s *dev, bool lock) static uint32_t spi_setfrequency(struct spi_dev_s *dev, uint32_t frequency) { - struct stm32wb_spidev_s *priv = (struct stm32wb_spidev_s *)dev; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; uint16_t setbits; uint32_t actual; @@ -1026,7 +1026,7 @@ static uint32_t spi_setfrequency(struct spi_dev_s *dev, uint32_t frequency) static void spi_setmode(struct spi_dev_s *dev, enum spi_mode_e mode) { - struct stm32wb_spidev_s *priv = (struct stm32wb_spidev_s *)dev; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; uint16_t setbits; uint16_t clrbits; @@ -1094,7 +1094,7 @@ static void spi_setmode(struct spi_dev_s *dev, enum spi_mode_e mode) static void spi_setbits(struct spi_dev_s *dev, int nbits) { - struct stm32wb_spidev_s *priv = (struct stm32wb_spidev_s *)dev; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; uint16_t setbits; uint16_t clrbits; @@ -1162,7 +1162,7 @@ static void spi_setbits(struct spi_dev_s *dev, int nbits) static int spi_hwfeatures(struct spi_dev_s *dev, spi_hwfeatures_t features) { #if defined(CONFIG_SPI_BITORDER) || defined(CONFIG_SPI_TRIGGER) - struct stm32wb_spidev_s *priv = (struct stm32wb_spidev_s *)dev; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; #endif #ifdef CONFIG_SPI_BITORDER @@ -1226,7 +1226,7 @@ static int spi_hwfeatures(struct spi_dev_s *dev, spi_hwfeatures_t features) static uint32_t spi_send(struct spi_dev_s *dev, uint32_t wd) { - struct stm32wb_spidev_s *priv = (struct stm32wb_spidev_s *)dev; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; uint32_t regval; uint32_t ret; @@ -1300,7 +1300,7 @@ static void spi_exchange_nodma(struct spi_dev_s *dev, size_t nwords) #endif { - struct stm32wb_spidev_s *priv = (struct stm32wb_spidev_s *)dev; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; DEBUGASSERT(priv && priv->spibase); spiinfo("txbuffer=%p rxbuffer=%p nwords=%d\n", txbuffer, rxbuffer, nwords); @@ -1401,14 +1401,14 @@ static void spi_exchange_nodma(struct spi_dev_s *dev, static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, void *rxbuffer, size_t nwords) { - struct stm32wb_spidev_s *priv = (struct stm32wb_spidev_s *)dev; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; int ret; #ifdef CONFIG_STM32WB_DMACAPABLE if ((txbuffer != NULL && - !stm32wb_dmacapable((uint32_t)txbuffer, nwords, priv->txccr)) || + !stm32_dmacapable((uint32_t)txbuffer, nwords, priv->txccr)) || (rxbuffer != NULL && - !stm32wb_dmacapable((uint32_t)rxbuffer, nwords, priv->rxccr))) + !stm32_dmacapable((uint32_t)rxbuffer, nwords, priv->rxccr))) { /* Unsupported memory region, fall back to non-DMA method. */ @@ -1596,8 +1596,8 @@ static void spi_recvblock(struct spi_dev_s *dev, void *rxbuffer, static int spi_pm_prepare(struct pm_callback_s *cb, int domain, enum pm_state_e pmstate) { - struct stm32wb_spidev_s *priv = (struct stm32wb_spidev_s *)((char *)cb - - offsetof(struct stm32wb_spidev_s, pm_cb)); + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)((char *)cb - + offsetof(struct stm32_spidev_s, pm_cb)); /* Logic to prepare for a reduced power state goes here. */ @@ -1647,7 +1647,7 @@ static int spi_pm_prepare(struct pm_callback_s *cb, int domain, * ****************************************************************************/ -static void spi_bus_initialize(struct stm32wb_spidev_s *priv) +static void spi_bus_initialize(struct stm32_spidev_s *priv) { uint16_t setbits; uint16_t clrbits; @@ -1689,16 +1689,16 @@ static void spi_bus_initialize(struct stm32wb_spidev_s *priv) spi_putreg(priv, STM32_SPI_CRCPR_OFFSET, 7); #ifdef CONFIG_STM32WB_SPI_DMA - /* Get DMA channels. NOTE: stm32wb_dmachannel() will always assign the DMA - * channel. If the channel is not available, then stm32wb_dmachannel() + /* Get DMA channels. NOTE: stm32_dmachannel() will always assign the DMA + * channel. If the channel is not available, then stm32_dmachannel() * will block and wait until the channel becomes available. WARNING: If * you have another device sharing a DMA channel with SPI and the code - * never releases that channel, then the call to stm32wb_dmachannel() will + * never releases that channel, then the call to stm32_dmachannel() will * hang forever in this function! Don't let your design do that! */ - priv->rxdma = stm32wb_dmachannel(priv->rxch); - priv->txdma = stm32wb_dmachannel(priv->txch); + priv->rxdma = stm32_dmachannel(priv->rxch); + priv->txdma = stm32_dmachannel(priv->txch); DEBUGASSERT(priv->rxdma && priv->txdma); spi_modifycr(STM32_SPI_CR2_OFFSET, priv, @@ -1723,7 +1723,7 @@ static void spi_bus_initialize(struct stm32wb_spidev_s *priv) ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_spibus_initialize + * Name: stm32_spibus_initialize * * Description: * Initialize the selected SPI bus @@ -1736,9 +1736,9 @@ static void spi_bus_initialize(struct stm32wb_spidev_s *priv) * ****************************************************************************/ -struct spi_dev_s *stm32wb_spibus_initialize(int bus) +struct spi_dev_s *stm32_spibus_initialize(int bus) { - struct stm32wb_spidev_s *priv = NULL; + struct stm32_spidev_s *priv = NULL; irqstate_t flags = enter_critical_section(); @@ -1755,9 +1755,9 @@ struct spi_dev_s *stm32wb_spibus_initialize(int bus) { /* Configure SPI1 pins: SCK, MISO, and MOSI */ - stm32wb_configgpio(GPIO_SPI1_SCK); - stm32wb_configgpio(GPIO_SPI1_MISO); - stm32wb_configgpio(GPIO_SPI1_MOSI); + stm32_configgpio(GPIO_SPI1_SCK); + stm32_configgpio(GPIO_SPI1_MISO); + stm32_configgpio(GPIO_SPI1_MOSI); /* Set up default configuration: Master, 8-bit, etc. */ @@ -1780,9 +1780,9 @@ struct spi_dev_s *stm32wb_spibus_initialize(int bus) { /* Configure SPI2 pins: SCK, MISO, and MOSI */ - stm32wb_configgpio(GPIO_SPI2_SCK); - stm32wb_configgpio(GPIO_SPI2_MISO); - stm32wb_configgpio(GPIO_SPI2_MOSI); + stm32_configgpio(GPIO_SPI2_SCK); + stm32_configgpio(GPIO_SPI2_MISO); + stm32_configgpio(GPIO_SPI2_MOSI); /* Set up default configuration: Master, 8-bit, etc. */ diff --git a/arch/arm/src/stm32wb/stm32wb_spi.h b/arch/arm/src/stm32wb/stm32wb_spi.h index f7998c56b6e..79fb78f1dee 100644 --- a/arch/arm/src/stm32wb/stm32wb_spi.h +++ b/arch/arm/src/stm32wb/stm32wb_spi.h @@ -58,7 +58,7 @@ struct spi_dev_s; ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_spibus_initialize + * Name: stm32_spibus_initialize * * Description: * Initialize the selected SPI bus @@ -71,33 +71,33 @@ struct spi_dev_s; * ****************************************************************************/ -struct spi_dev_s *stm32wb_spibus_initialize(int bus); +struct spi_dev_s *stm32_spibus_initialize(int bus); /**************************************************************************** - * Name: stm32wb_spi1/2/...select and stm32wb_spi1/2/...status + * Name: stm32_spi1/2/...select and stm32_spi1/2/...status * * Description: - * The external functions, stm32wb_spi1/2/...select, - * stm32wb_spi1/2/...status, and stm32wb_spi1/2/...cmddata must be + * The external functions, stm32_spi1/2/...select, + * stm32_spi1/2/...status, and stm32_spi1/2/...cmddata must be * provided by board-specific logic. These are implementations of the * select, status, and cmddata methods of the SPI interface defined by * struct spi_ops_s (see include/nuttx/spi/spi.h). All other methods - * (including stm32wb_spibus_initialize()) are provided by common + * (including stm32_spibus_initialize()) are provided by common * STM32 logic. To use this common SPI logic on your board: * - * 1. Provide logic in stm32wb_board_initialize() to configure SPI chip + * 1. Provide logic in stm32_board_initialize() to configure SPI chip * select pins. - * 2. Provide stm32wb_spi1/2/...select() and stm32wb_spi1/2/...status() + * 2. Provide stm32_spi1/2/...select() and stm32_spi1/2/...status() * functions in your board-specific logic. These functions will perform * chip selection and status operations using GPIOs in the way your * board is configured. * 3. If CONFIG_SPI_CMDDATA is defined in your NuttX configuration file, - * then provide stm32wb_spi1/2/...cmddata() functions in your + * then provide stm32_spi1/2/...cmddata() functions in your * board-specific logic. These functions will perform cmd/data selection * operations using GPIOs in the way your board is configured. - * 4. Add a calls to stm32wb_spibus_initialize() in your low level + * 4. Add a calls to stm32_spibus_initialize() in your low level * application initialization logic - * 5. The handle returned by stm32wb_spibus_initialize() may then be used + * 5. The handle returned by stm32_spibus_initialize() may then be used * to bind the SPI driver to higher level logic (e.g., calling * mmcsd_spislotinitialize(), for example, will bind the SPI driver to * the SPI MMC/SD driver). @@ -105,21 +105,21 @@ struct spi_dev_s *stm32wb_spibus_initialize(int bus); ****************************************************************************/ #ifdef CONFIG_STM32WB_SPI1 -void stm32wb_spi1select(struct spi_dev_s *dev, +void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected); -uint8_t stm32wb_spi1status(struct spi_dev_s *dev, uint32_t devid); -int stm32wb_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); +uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid); +int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); #endif #ifdef CONFIG_STM32WB_SPI2 -void stm32wb_spi2select(struct spi_dev_s *dev, +void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected); -uint8_t stm32wb_spi2status(struct spi_dev_s *dev, uint32_t devid); -int stm32wb_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); +uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid); +int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); #endif /**************************************************************************** - * Name: stm32wb_spi1/2/...register + * Name: stm32_spi1/2/...register * * Description: * If the board supports a card detect callback to inform the SPI-based @@ -140,12 +140,12 @@ int stm32wb_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); #ifdef CONFIG_SPI_CALLBACK #ifdef CONFIG_STM32WB_SPI1 -int stm32wb_spi1register(struct spi_dev_s *dev, spi_mediachange_t callback, +int stm32_spi1register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif #ifdef CONFIG_STM32WB_SPI2 -int stm32wb_spi2register(struct spi_dev_s *dev, spi_mediachange_t callback, +int stm32_spi2register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif #endif diff --git a/arch/arm/src/stm32wb/stm32wb_start.c b/arch/arm/src/stm32wb/stm32wb_start.c index 660cd4db3a6..eade4167de7 100644 --- a/arch/arm/src/stm32wb/stm32wb_start.c +++ b/arch/arm/src/stm32wb/stm32wb_start.c @@ -164,15 +164,15 @@ void __start(void) /* Configure the UART so that we can get debug output as soon as possible */ - stm32wb_clockconfig(); + stm32_clockconfig(); #ifdef CONFIG_STM32WB_IPCC - stm32wb_ipccreset(); + stm32_ipccreset(); #endif arm_fpuconfig(); - /* Todo: stm32wb_lowsetup(); */ + /* Todo: stm32_lowsetup(); */ - stm32wb_gpioinit(); + stm32_gpioinit(); showprogress('A'); /* Clear .bss. We'll do this inline (vs. calling memset) just to be @@ -223,13 +223,13 @@ void __start(void) */ #ifdef CONFIG_BUILD_PROTECTED - stm32wb_userspace(); + stm32_userspace(); showprogress('E'); #endif /* Initialize onboard resources */ - stm32wb_board_initialize(); + stm32_board_initialize(); showprogress('F'); /* Then start NuttX */ diff --git a/arch/arm/src/stm32wb/stm32wb_start.h b/arch/arm/src/stm32wb/stm32wb_start.h index e59d2843c56..c8c3eaecb1e 100644 --- a/arch/arm/src/stm32wb/stm32wb_start.h +++ b/arch/arm/src/stm32wb/stm32wb_start.h @@ -32,7 +32,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_board_initialize + * Name: stm32_board_initialize * * Description: * All STM32WB architectures must provide the following entry point. This @@ -42,6 +42,6 @@ * ****************************************************************************/ -void stm32wb_board_initialize(void); +void stm32_board_initialize(void); #endif /* __ARCH_ARM_SRC_STM32WB_STM32WB_START_H */ diff --git a/arch/arm/src/stm32wb/stm32wb_tickless.c b/arch/arm/src/stm32wb/stm32wb_tickless.c index acefc6af5ab..7d99e9082c9 100644 --- a/arch/arm/src/stm32wb/stm32wb_tickless.c +++ b/arch/arm/src/stm32wb/stm32wb_tickless.c @@ -52,7 +52,7 @@ * There are two interrupts generated from our timer, the overflow interrupt * which drives the timing handler and the capture/compare interrupt which * drives the interval handler. There are some low level timer control - * functions implemented here because the API of stm32wb_tim.c does not + * functions implemented here because the API of stm32_tim.c does not * provide adequate control over capture/compare interrupts. * ****************************************************************************/ @@ -96,13 +96,13 @@ * Private Types ****************************************************************************/ -struct stm32wb_tickless_s +struct stm32_tickless_s { uint8_t timer; /* The timer/counter in use */ uint8_t channel; /* The timer channel to use * for intervals */ - struct stm32wb_tim_dev_s *tch; /* Pointer returned by - * stm32wb_tim_init() */ + struct stm32_tim_dev_s *tch; /* Pointer returned by + * stm32_tim_init() */ uint32_t frequency; uint32_t overflow; /* Timer counter overflow */ volatile bool pending; /* True: pending task */ @@ -114,93 +114,93 @@ struct stm32wb_tickless_s * Private Data ****************************************************************************/ -static struct stm32wb_tickless_s g_tickless; +static struct stm32_tickless_s g_tickless; /**************************************************************************** * Private Functions ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_getreg16 + * Name: stm32_getreg16 * * Description: * Get a 16-bit register value by offset * ****************************************************************************/ -static inline uint16_t stm32wb_getreg16(uint8_t offset) +static inline uint16_t stm32_getreg16(uint8_t offset) { return getreg16(g_tickless.base + offset); } /**************************************************************************** - * Name: stm32wb_putreg16 + * Name: stm32_putreg16 * * Description: * Put a 16-bit register value by offset * ****************************************************************************/ -static inline void stm32wb_putreg16(uint8_t offset, uint16_t value) +static inline void stm32_putreg16(uint8_t offset, uint16_t value) { putreg16(value, g_tickless.base + offset); } /**************************************************************************** - * Name: stm32wb_modifyreg16 + * Name: stm32_modifyreg16 * * Description: * Modify a 16-bit register value by offset * ****************************************************************************/ -static inline void stm32wb_modifyreg16(uint8_t offset, uint16_t clearbits, +static inline void stm32_modifyreg16(uint8_t offset, uint16_t clearbits, uint16_t setbits) { modifyreg16(g_tickless.base + offset, clearbits, setbits); } /**************************************************************************** - * Name: stm32wb_tickless_enableint + * Name: stm32_tickless_enableint ****************************************************************************/ -static inline void stm32wb_tickless_enableint(int channel) +static inline void stm32_tickless_enableint(int channel) { - stm32wb_modifyreg16(STM32_TIM_DIER_OFFSET, 0, 1 << channel); + stm32_modifyreg16(STM32_TIM_DIER_OFFSET, 0, 1 << channel); } /**************************************************************************** - * Name: stm32wb_tickless_disableint + * Name: stm32_tickless_disableint ****************************************************************************/ -static inline void stm32wb_tickless_disableint(int channel) +static inline void stm32_tickless_disableint(int channel) { - stm32wb_modifyreg16(STM32_TIM_DIER_OFFSET, 1 << channel, 0); + stm32_modifyreg16(STM32_TIM_DIER_OFFSET, 1 << channel, 0); } /**************************************************************************** - * Name: stm32wb_tickless_ackint + * Name: stm32_tickless_ackint ****************************************************************************/ -static inline void stm32wb_tickless_ackint(int channel) +static inline void stm32_tickless_ackint(int channel) { - stm32wb_putreg16(STM32_TIM_SR_OFFSET, ~(1 << channel)); + stm32_putreg16(STM32_TIM_SR_OFFSET, ~(1 << channel)); } /**************************************************************************** - * Name: stm32wb_tickless_getint + * Name: stm32_tickless_getint ****************************************************************************/ -static inline uint16_t stm32wb_tickless_getint(void) +static inline uint16_t stm32_tickless_getint(void) { - return stm32wb_getreg16(STM32_TIM_SR_OFFSET); + return stm32_getreg16(STM32_TIM_SR_OFFSET); } /**************************************************************************** - * Name: stm32wb_tickless_setchannel + * Name: stm32_tickless_setchannel ****************************************************************************/ -static int stm32wb_tickless_setchannel(uint8_t channel) +static int stm32_tickless_setchannel(uint8_t channel) { uint16_t ccmr_orig = 0; uint16_t ccmr_val = 0; @@ -216,7 +216,7 @@ static int stm32wb_tickless_setchannel(uint8_t channel) /* Assume that channel is disabled and polarity is active high */ - ccer_val = stm32wb_getreg16(STM32_TIM_CCER_OFFSET); + ccer_val = stm32_getreg16(STM32_TIM_CCER_OFFSET); ccer_val &= ~(GTIM_CCER_CCXE(channel) | GTIM_CCER_CCXP(channel)); /* Frozen mode because we don't want to change the GPIO, preload register @@ -234,17 +234,17 @@ static int stm32wb_tickless_setchannel(uint8_t channel) ccmr_offset = STM32_TIM_CCMR2_OFFSET; } - ccmr_orig = stm32wb_getreg16(ccmr_offset); + ccmr_orig = stm32_getreg16(ccmr_offset); ccmr_orig &= ~(GTIM_CCMR_OCXM_MASK(channel) | GTIM_CCMR_OCXPE(channel)); ccmr_orig |= ccmr_val; - stm32wb_putreg16(ccmr_offset, ccmr_orig); - stm32wb_putreg16(STM32_TIM_CCER_OFFSET, ccer_val); + stm32_putreg16(ccmr_offset, ccmr_orig); + stm32_putreg16(STM32_TIM_CCER_OFFSET, ccer_val); return OK; } /**************************************************************************** - * Name: stm32wb_interval_handler + * Name: stm32_interval_handler * * Description: * Called when the timer counter matches the compare register @@ -261,14 +261,14 @@ static int stm32wb_tickless_setchannel(uint8_t channel) * ****************************************************************************/ -static void stm32wb_interval_handler(void) +static void stm32_interval_handler(void) { tmrinfo("Expired...\n"); /* Disable the compare interrupt now. */ - stm32wb_tickless_disableint(g_tickless.channel); - stm32wb_tickless_ackint(g_tickless.channel); + stm32_tickless_disableint(g_tickless.channel); + stm32_tickless_ackint(g_tickless.channel); g_tickless.pending = false; @@ -276,7 +276,7 @@ static void stm32wb_interval_handler(void) } /**************************************************************************** - * Name: stm32wb_timing_handler + * Name: stm32_timing_handler * * Description: * Timer interrupt callback. When the freerun timer counter overflows, @@ -290,7 +290,7 @@ static void stm32wb_interval_handler(void) * ****************************************************************************/ -static void stm32wb_timing_handler(void) +static void stm32_timing_handler(void) { g_tickless.overflow++; @@ -298,7 +298,7 @@ static void stm32wb_timing_handler(void) } /**************************************************************************** - * Name: stm32wb_tickless_handler + * Name: stm32_tickless_handler * * Description: * Generic interrupt handler for this timer. It checks the source of the @@ -312,18 +312,18 @@ static void stm32wb_timing_handler(void) * ****************************************************************************/ -static int stm32wb_tickless_handler(int irq, void *context, void *arg) +static int stm32_tickless_handler(int irq, void *context, void *arg) { - int interrupt_flags = stm32wb_tickless_getint(); + int interrupt_flags = stm32_tickless_getint(); if (interrupt_flags & GTIM_SR_UIF) { - stm32wb_timing_handler(); + stm32_timing_handler(); } if (interrupt_flags & (1 << g_tickless.channel)) { - stm32wb_interval_handler(); + stm32_interval_handler(); } return OK; @@ -402,7 +402,7 @@ void up_timer_initialize(void) tmrinfo("timer=%d channel=%d frequency=%lu Hz\n", g_tickless.timer, g_tickless.channel, g_tickless.frequency); - g_tickless.tch = stm32wb_tim_init(g_tickless.timer); + g_tickless.tch = stm32_tim_init(g_tickless.timer); if (!g_tickless.tch) { tmrerr("ERROR: Failed to allocate TIM%d\n", g_tickless.timer); @@ -413,7 +413,7 @@ void up_timer_initialize(void) /* Set up to receive the callback when the counter overflow occurs */ - STM32_TIM_SETISR(g_tickless.tch, stm32wb_tickless_handler, NULL, 0); + STM32_TIM_SETISR(g_tickless.tch, stm32_tickless_handler, NULL, 0); /* Initialize interval to zero */ @@ -421,7 +421,7 @@ void up_timer_initialize(void) /* Setup compare channel for the interval timing */ - stm32wb_tickless_setchannel(g_tickless.channel); + stm32_tickless_setchannel(g_tickless.channel); /* Set timer period */ @@ -493,7 +493,7 @@ int up_timer_gettime(struct timespec *ts) DEBUGASSERT(g_tickless.tch && ts); /* Temporarily disable the overflow counter. NOTE that we have to be - * careful here because stm32wb_tc_getpending() will reset the pending + * careful here because stm32_tc_getpending() will reset the pending * interrupt status. If we do not handle the overflow here then, it will * be lost. */ @@ -679,7 +679,7 @@ int up_timer_cancel(struct timespec *ts) /* Disable the interrupt. */ - stm32wb_tickless_disableint(g_tickless.channel); + stm32_tickless_disableint(g_tickless.channel); count = STM32_TIM_GETCOUNTER(g_tickless.tch); period = g_tickless.period; @@ -829,8 +829,8 @@ int up_timer_start(const struct timespec *ts) * occurs. */ - stm32wb_tickless_ackint(g_tickless.channel); - stm32wb_tickless_enableint(g_tickless.channel); + stm32_tickless_ackint(g_tickless.channel); + stm32_tickless_enableint(g_tickless.channel); g_tickless.pending = true; leave_critical_section(flags); diff --git a/arch/arm/src/stm32wb/stm32wb_tim.c b/arch/arm/src/stm32wb/stm32wb_tim.c index d784f103c2a..2e7b56cf817 100644 --- a/arch/arm/src/stm32wb/stm32wb_tim.c +++ b/arch/arm/src/stm32wb/stm32wb_tim.c @@ -37,7 +37,7 @@ #include "arm_internal.h" #include "chip.h" -#include "stm32wb.h" +#include "stm32.h" #include "stm32wb_tim.h" #include "stm32wb_gpio.h" #include "stm32wb_rcc.h" @@ -128,10 +128,10 @@ /* TIM Device Structure */ -struct stm32wb_tim_priv_s +struct stm32_tim_priv_s { - const struct stm32wb_tim_ops_s *ops; - enum stm32wb_tim_mode_e mode; + const struct stm32_tim_ops_s *ops; + enum stm32_tim_mode_e mode; uint32_t base; /* TIMn base address */ }; @@ -141,116 +141,116 @@ struct stm32wb_tim_priv_s /* Register helpers */ -static inline uint16_t stm32wb_getreg16(struct stm32wb_tim_dev_s *dev, +static inline uint16_t stm32_getreg16(struct stm32_tim_dev_s *dev, uint8_t offset); -static inline void stm32wb_putreg16(struct stm32wb_tim_dev_s *dev, +static inline void stm32_putreg16(struct stm32_tim_dev_s *dev, uint8_t offset, uint16_t value); -static inline void stm32wb_modifyreg16(struct stm32wb_tim_dev_s *dev, +static inline void stm32_modifyreg16(struct stm32_tim_dev_s *dev, uint8_t offset, uint16_t clearbits, uint16_t setbits); -static inline uint32_t stm32wb_getreg32(struct stm32wb_tim_dev_s *dev, +static inline uint32_t stm32_getreg32(struct stm32_tim_dev_s *dev, uint8_t offset); -static inline void stm32wb_putreg32(struct stm32wb_tim_dev_s *dev, +static inline void stm32_putreg32(struct stm32_tim_dev_s *dev, uint8_t offset, uint32_t value); /* Timer helpers */ -static void stm32wb_tim_reload_counter(struct stm32wb_tim_dev_s *dev); -static void stm32wb_tim_enable(struct stm32wb_tim_dev_s *dev); -static void stm32wb_tim_disable(struct stm32wb_tim_dev_s *dev); -static void stm32wb_tim_reset(struct stm32wb_tim_dev_s *dev); +static void stm32_tim_reload_counter(struct stm32_tim_dev_s *dev); +static void stm32_tim_enable(struct stm32_tim_dev_s *dev); +static void stm32_tim_disable(struct stm32_tim_dev_s *dev); +static void stm32_tim_reset(struct stm32_tim_dev_s *dev); #if defined(HAVE_TIM1_GPIOCONFIG) || defined(HAVE_TIM2_GPIOCONFIG) || \ defined(HAVE_TIM16_GPIOCONFIG) || defined(HAVE_TIM17_GPIOCONFIG) -static void stm32wb_tim_gpioconfig(uint32_t cfg, - enum stm32wb_tim_channel_e mode); +static void stm32_tim_gpioconfig(uint32_t cfg, + enum stm32_tim_channel_e mode); #endif -static void stm32wb_tim_dumpregs(struct stm32wb_tim_dev_s *dev); +static void stm32_tim_dumpregs(struct stm32_tim_dev_s *dev); /* Timer methods */ -static int stm32wb_tim_setmode(struct stm32wb_tim_dev_s *dev, - enum stm32wb_tim_mode_e mode); -static int stm32wb_tim_setfreq(struct stm32wb_tim_dev_s *dev, uint32_t freq); -static int stm32wb_tim_setclock(struct stm32wb_tim_dev_s *dev, +static int stm32_tim_setmode(struct stm32_tim_dev_s *dev, + enum stm32_tim_mode_e mode); +static int stm32_tim_setfreq(struct stm32_tim_dev_s *dev, uint32_t freq); +static int stm32_tim_setclock(struct stm32_tim_dev_s *dev, uint32_t freq); -static uint32_t stm32wb_tim_getclock(struct stm32wb_tim_dev_s *dev); -static void stm32wb_tim_setperiod(struct stm32wb_tim_dev_s *dev, +static uint32_t stm32_tim_getclock(struct stm32_tim_dev_s *dev); +static void stm32_tim_setperiod(struct stm32_tim_dev_s *dev, uint32_t period); -static uint32_t stm32wb_tim_getperiod(struct stm32wb_tim_dev_s *dev); -static uint32_t stm32wb_tim_getcounter(struct stm32wb_tim_dev_s *dev); -static uint32_t stm32wb_tim_getwidth(struct stm32wb_tim_dev_s *dev); -static int stm32wb_tim_setchannel(struct stm32wb_tim_dev_s *dev, +static uint32_t stm32_tim_getperiod(struct stm32_tim_dev_s *dev); +static uint32_t stm32_tim_getcounter(struct stm32_tim_dev_s *dev); +static uint32_t stm32_tim_getwidth(struct stm32_tim_dev_s *dev); +static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, uint8_t channel, - enum stm32wb_tim_channel_e mode); -static int stm32wb_tim_setcompare(struct stm32wb_tim_dev_s *dev, + enum stm32_tim_channel_e mode); +static int stm32_tim_setcompare(struct stm32_tim_dev_s *dev, uint8_t channel, uint32_t compare); -static uint32_t stm32wb_tim_getcapture(struct stm32wb_tim_dev_s *dev, +static uint32_t stm32_tim_getcapture(struct stm32_tim_dev_s *dev, uint8_t channel); -static int stm32wb_tim_setisr(struct stm32wb_tim_dev_s *dev, +static int stm32_tim_setisr(struct stm32_tim_dev_s *dev, xcpt_t handler, void *arg, int source); -static void stm32wb_tim_enableint(struct stm32wb_tim_dev_s *dev, int source); -static void stm32wb_tim_disableint(struct stm32wb_tim_dev_s *dev, +static void stm32_tim_enableint(struct stm32_tim_dev_s *dev, int source); +static void stm32_tim_disableint(struct stm32_tim_dev_s *dev, int source); -static void stm32wb_tim_ackint(struct stm32wb_tim_dev_s *dev, int source); -static int stm32wb_tim_checkint(struct stm32wb_tim_dev_s *dev, int source); +static void stm32_tim_ackint(struct stm32_tim_dev_s *dev, int source); +static int stm32_tim_checkint(struct stm32_tim_dev_s *dev, int source); /**************************************************************************** * Private Data ****************************************************************************/ -static const struct stm32wb_tim_ops_s stm32wb_tim_ops = +static const struct stm32_tim_ops_s stm32_tim_ops = { - .enable = stm32wb_tim_enable, - .disable = stm32wb_tim_disable, - .setmode = stm32wb_tim_setmode, - .setfreq = stm32wb_tim_setfreq, - .setclock = stm32wb_tim_setclock, - .getclock = stm32wb_tim_getclock, - .setperiod = stm32wb_tim_setperiod, - .getperiod = stm32wb_tim_getperiod, - .getcounter = stm32wb_tim_getcounter, - .getwidth = stm32wb_tim_getwidth, - .setchannel = stm32wb_tim_setchannel, - .setcompare = stm32wb_tim_setcompare, - .getcapture = stm32wb_tim_getcapture, - .setisr = stm32wb_tim_setisr, - .enableint = stm32wb_tim_enableint, - .disableint = stm32wb_tim_disableint, - .ackint = stm32wb_tim_ackint, - .checkint = stm32wb_tim_checkint, - .dump_regs = stm32wb_tim_dumpregs, + .enable = stm32_tim_enable, + .disable = stm32_tim_disable, + .setmode = stm32_tim_setmode, + .setfreq = stm32_tim_setfreq, + .setclock = stm32_tim_setclock, + .getclock = stm32_tim_getclock, + .setperiod = stm32_tim_setperiod, + .getperiod = stm32_tim_getperiod, + .getcounter = stm32_tim_getcounter, + .getwidth = stm32_tim_getwidth, + .setchannel = stm32_tim_setchannel, + .setcompare = stm32_tim_setcompare, + .getcapture = stm32_tim_getcapture, + .setisr = stm32_tim_setisr, + .enableint = stm32_tim_enableint, + .disableint = stm32_tim_disableint, + .ackint = stm32_tim_ackint, + .checkint = stm32_tim_checkint, + .dump_regs = stm32_tim_dumpregs, }; #ifdef CONFIG_STM32WB_TIM1 -struct stm32wb_tim_priv_s stm32wb_tim1_priv = +struct stm32_tim_priv_s stm32_tim1_priv = { - .ops = &stm32wb_tim_ops, + .ops = &stm32_tim_ops, .mode = STM32_TIM_MODE_UNUSED, .base = STM32_TIM1_BASE, }; #endif #ifdef CONFIG_STM32WB_TIM2 -struct stm32wb_tim_priv_s stm32wb_tim2_priv = +struct stm32_tim_priv_s stm32_tim2_priv = { - .ops = &stm32wb_tim_ops, + .ops = &stm32_tim_ops, .mode = STM32_TIM_MODE_UNUSED, .base = STM32_TIM2_BASE, }; #endif #ifdef CONFIG_STM32WB_TIM16 -struct stm32wb_tim_priv_s stm32wb_tim16_priv = +struct stm32_tim_priv_s stm32_tim16_priv = { - .ops = &stm32wb_tim_ops, + .ops = &stm32_tim_ops, .mode = STM32_TIM_MODE_UNUSED, .base = STM32_TIM16_BASE, }; #endif #ifdef CONFIG_STM32WB_TIM17 -struct stm32wb_tim_priv_s stm32wb_tim17_priv = +struct stm32_tim_priv_s stm32_tim17_priv = { - .ops = &stm32wb_tim_ops, + .ops = &stm32_tim_ops, .mode = STM32_TIM_MODE_UNUSED, .base = STM32_TIM17_BASE, }; @@ -261,51 +261,51 @@ struct stm32wb_tim_priv_s stm32wb_tim17_priv = ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_getreg16 + * Name: stm32_getreg16 * * Description: * Get a 16-bit register value by offset * ****************************************************************************/ -static inline uint16_t stm32wb_getreg16(struct stm32wb_tim_dev_s *dev, +static inline uint16_t stm32_getreg16(struct stm32_tim_dev_s *dev, uint8_t offset) { - return getreg16(((struct stm32wb_tim_priv_s *)dev)->base + offset); + return getreg16(((struct stm32_tim_priv_s *)dev)->base + offset); } /**************************************************************************** - * Name: stm32wb_putreg16 + * Name: stm32_putreg16 * * Description: * Put a 16-bit register value by offset * ****************************************************************************/ -static inline void stm32wb_putreg16(struct stm32wb_tim_dev_s *dev, +static inline void stm32_putreg16(struct stm32_tim_dev_s *dev, uint8_t offset, uint16_t value) { - putreg16(value, ((struct stm32wb_tim_priv_s *)dev)->base + offset); + putreg16(value, ((struct stm32_tim_priv_s *)dev)->base + offset); } /**************************************************************************** - * Name: stm32wb_modifyreg16 + * Name: stm32_modifyreg16 * * Description: * Modify a 16-bit register value by offset * ****************************************************************************/ -static inline void stm32wb_modifyreg16(struct stm32wb_tim_dev_s *dev, +static inline void stm32_modifyreg16(struct stm32_tim_dev_s *dev, uint8_t offset, uint16_t clearbits, uint16_t setbits) { - modifyreg16(((struct stm32wb_tim_priv_s *)dev)->base + offset, clearbits, + modifyreg16(((struct stm32_tim_priv_s *)dev)->base + offset, clearbits, setbits); } /**************************************************************************** - * Name: stm32wb_getreg32 + * Name: stm32_getreg32 * * Description: * Get a 32-bit register value by offset. This applies only for the STM32WB @@ -313,14 +313,14 @@ static inline void stm32wb_modifyreg16(struct stm32wb_tim_dev_s *dev, * ****************************************************************************/ -static inline uint32_t stm32wb_getreg32(struct stm32wb_tim_dev_s *dev, +static inline uint32_t stm32_getreg32(struct stm32_tim_dev_s *dev, uint8_t offset) { - return getreg32(((struct stm32wb_tim_priv_s *)dev)->base + offset); + return getreg32(((struct stm32_tim_priv_s *)dev)->base + offset); } /**************************************************************************** - * Name: stm32wb_putreg32 + * Name: stm32_putreg32 * * Description: * Put a 32-bit register value by offset. This applies only for the STM32WB @@ -328,49 +328,49 @@ static inline uint32_t stm32wb_getreg32(struct stm32wb_tim_dev_s *dev, * ****************************************************************************/ -static inline void stm32wb_putreg32(struct stm32wb_tim_dev_s *dev, +static inline void stm32_putreg32(struct stm32_tim_dev_s *dev, uint8_t offset, uint32_t value) { - putreg32(value, ((struct stm32wb_tim_priv_s *)dev)->base + offset); + putreg32(value, ((struct stm32_tim_priv_s *)dev)->base + offset); } /**************************************************************************** - * Name: stm32wb_tim_reload_counter + * Name: stm32_tim_reload_counter ****************************************************************************/ -static void stm32wb_tim_reload_counter(struct stm32wb_tim_dev_s *dev) +static void stm32_tim_reload_counter(struct stm32_tim_dev_s *dev) { - uint16_t val = stm32wb_getreg16(dev, STM32_TIM_EGR_OFFSET); + uint16_t val = stm32_getreg16(dev, STM32_TIM_EGR_OFFSET); val |= GTIM_EGR_UG; - stm32wb_putreg16(dev, STM32_TIM_EGR_OFFSET, val); + stm32_putreg16(dev, STM32_TIM_EGR_OFFSET, val); } /**************************************************************************** - * Name: stm32wb_tim_enable + * Name: stm32_tim_enable ****************************************************************************/ -static void stm32wb_tim_enable(struct stm32wb_tim_dev_s *dev) +static void stm32_tim_enable(struct stm32_tim_dev_s *dev) { - uint16_t val = stm32wb_getreg16(dev, STM32_TIM_CR1_OFFSET); + uint16_t val = stm32_getreg16(dev, STM32_TIM_CR1_OFFSET); val |= GTIM_CR1_CEN; - stm32wb_tim_reload_counter(dev); - stm32wb_putreg16(dev, STM32_TIM_CR1_OFFSET, val); + stm32_tim_reload_counter(dev); + stm32_putreg16(dev, STM32_TIM_CR1_OFFSET, val); } /**************************************************************************** - * Name: stm32wb_tim_disable + * Name: stm32_tim_disable ****************************************************************************/ -static void stm32wb_tim_disable(struct stm32wb_tim_dev_s *dev) +static void stm32_tim_disable(struct stm32_tim_dev_s *dev) { - uint16_t val = stm32wb_getreg16(dev, STM32_TIM_CR1_OFFSET); + uint16_t val = stm32_getreg16(dev, STM32_TIM_CR1_OFFSET); val &= ~GTIM_CR1_CEN; - stm32wb_putreg16(dev, STM32_TIM_CR1_OFFSET, val); + stm32_putreg16(dev, STM32_TIM_CR1_OFFSET, val); } /**************************************************************************** - * Name: stm32wb_tim_reset + * Name: stm32_tim_reset * * Description: * Reset timer into system default state, but do not affect output/input @@ -378,86 +378,86 @@ static void stm32wb_tim_disable(struct stm32wb_tim_dev_s *dev) * ****************************************************************************/ -static void stm32wb_tim_reset(struct stm32wb_tim_dev_s *dev) +static void stm32_tim_reset(struct stm32_tim_dev_s *dev) { - ((struct stm32wb_tim_priv_s *)dev)->mode = STM32_TIM_MODE_DISABLED; - stm32wb_tim_disable(dev); + ((struct stm32_tim_priv_s *)dev)->mode = STM32_TIM_MODE_DISABLED; + stm32_tim_disable(dev); } /**************************************************************************** - * Name: stm32wb_tim_gpioconfig + * Name: stm32_tim_gpioconfig ****************************************************************************/ #if defined(HAVE_TIM1_GPIOCONFIG) || defined(HAVE_TIM2_GPIOCONFIG) || \ defined(HAVE_TIM16_GPIOCONFIG) || defined(HAVE_TIM17_GPIOCONFIG) -static void stm32wb_tim_gpioconfig(uint32_t cfg, - enum stm32wb_tim_channel_e mode) +static void stm32_tim_gpioconfig(uint32_t cfg, + enum stm32_tim_channel_e mode) { if (mode & STM32_TIM_CH_MODE_MASK) { - stm32wb_configgpio(cfg); + stm32_configgpio(cfg); } else { - stm32wb_unconfiggpio(cfg); + stm32_unconfiggpio(cfg); } } #endif /**************************************************************************** - * Name: stm32wb_tim_dumpregs + * Name: stm32_tim_dumpregs ****************************************************************************/ -static void stm32wb_tim_dumpregs(struct stm32wb_tim_dev_s *dev) +static void stm32_tim_dumpregs(struct stm32_tim_dev_s *dev) { - struct stm32wb_tim_priv_s *priv = (struct stm32wb_tim_priv_s *)dev; + struct stm32_tim_priv_s *priv = (struct stm32_tim_priv_s *)dev; ainfo(" CR1: %04x CR2: %04x SMCR: %04x DIER: %04x\n", - stm32wb_getreg16(dev, STM32_TIM_CR1_OFFSET), - stm32wb_getreg16(dev, STM32_TIM_CR2_OFFSET), - stm32wb_getreg16(dev, STM32_TIM_SMCR_OFFSET), - stm32wb_getreg16(dev, STM32_TIM_DIER_OFFSET) + stm32_getreg16(dev, STM32_TIM_CR1_OFFSET), + stm32_getreg16(dev, STM32_TIM_CR2_OFFSET), + stm32_getreg16(dev, STM32_TIM_SMCR_OFFSET), + stm32_getreg16(dev, STM32_TIM_DIER_OFFSET) ); ainfo(" SR: %04x EGR: 0000 CCMR1: %04x CCMR2: %04x\n", - stm32wb_getreg16(dev, STM32_TIM_SR_OFFSET), - stm32wb_getreg16(dev, STM32_TIM_CCMR1_OFFSET), - stm32wb_getreg16(dev, STM32_TIM_CCMR2_OFFSET) + stm32_getreg16(dev, STM32_TIM_SR_OFFSET), + stm32_getreg16(dev, STM32_TIM_CCMR1_OFFSET), + stm32_getreg16(dev, STM32_TIM_CCMR2_OFFSET) ); ainfo(" CCER: %04x CNT: %04x PSC: %04x ARR: %04x\n", - stm32wb_getreg16(dev, STM32_TIM_CCER_OFFSET), - stm32wb_getreg16(dev, STM32_TIM_CNT_OFFSET), - stm32wb_getreg16(dev, STM32_TIM_PSC_OFFSET), - stm32wb_getreg16(dev, STM32_TIM_ARR_OFFSET) + stm32_getreg16(dev, STM32_TIM_CCER_OFFSET), + stm32_getreg16(dev, STM32_TIM_CNT_OFFSET), + stm32_getreg16(dev, STM32_TIM_PSC_OFFSET), + stm32_getreg16(dev, STM32_TIM_ARR_OFFSET) ); ainfo(" CCR1: %04x CCR2: %04x CCR3: %04x CCR4: %04x\n", - stm32wb_getreg16(dev, STM32_TIM_CCR1_OFFSET), - stm32wb_getreg16(dev, STM32_TIM_CCR2_OFFSET), - stm32wb_getreg16(dev, STM32_TIM_CCR3_OFFSET), - stm32wb_getreg16(dev, STM32_TIM_CCR4_OFFSET) + stm32_getreg16(dev, STM32_TIM_CCR1_OFFSET), + stm32_getreg16(dev, STM32_TIM_CCR2_OFFSET), + stm32_getreg16(dev, STM32_TIM_CCR3_OFFSET), + stm32_getreg16(dev, STM32_TIM_CCR4_OFFSET) ); if (priv->base == STM32_TIM1_BASE) { ainfo(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n", - stm32wb_getreg16(dev, STM32_TIM_RCR_OFFSET), - stm32wb_getreg16(dev, STM32_TIM_BDTR_OFFSET), - stm32wb_getreg16(dev, STM32_TIM_DCR_OFFSET), - stm32wb_getreg16(dev, STM32_TIM_DMAR_OFFSET)); + stm32_getreg16(dev, STM32_TIM_RCR_OFFSET), + stm32_getreg16(dev, STM32_TIM_BDTR_OFFSET), + stm32_getreg16(dev, STM32_TIM_DCR_OFFSET), + stm32_getreg16(dev, STM32_TIM_DMAR_OFFSET)); } else { ainfo(" DCR: %04x DMAR: %04x\n", - stm32wb_getreg16(dev, STM32_TIM_DCR_OFFSET), - stm32wb_getreg16(dev, STM32_TIM_DMAR_OFFSET)); + stm32_getreg16(dev, STM32_TIM_DCR_OFFSET), + stm32_getreg16(dev, STM32_TIM_DMAR_OFFSET)); } } /**************************************************************************** - * Name: stm32wb_tim_setmode + * Name: stm32_tim_setmode ****************************************************************************/ -static int stm32wb_tim_setmode(struct stm32wb_tim_dev_s *dev, - enum stm32wb_tim_mode_e mode) +static int stm32_tim_setmode(struct stm32_tim_dev_s *dev, + enum stm32_tim_mode_e mode) { uint16_t val; @@ -469,14 +469,14 @@ static int stm32wb_tim_setmode(struct stm32wb_tim_dev_s *dev, if ((mode == STM32_TIM_MODE_DOWN || mode == STM32_TIM_MODE_UPDOWN)) { #if defined(CONFIG_STM32WB_TIM16) - if (((struct stm32wb_tim_priv_s *)dev)->base == STM32_TIM16_BASE) + if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM16_BASE) { return -EINVAL; } #endif #if defined(CONFIG_STM32WB_TIM17) - if (((struct stm32wb_tim_priv_s *)dev)->base == STM32_TIM17_BASE) + if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM17_BASE) { return -EINVAL; } @@ -519,15 +519,15 @@ static int stm32wb_tim_setmode(struct stm32wb_tim_dev_s *dev, return -EINVAL; } - stm32wb_tim_reload_counter(dev); - stm32wb_putreg16(dev, STM32_TIM_CR1_OFFSET, val); + stm32_tim_reload_counter(dev); + stm32_putreg16(dev, STM32_TIM_CR1_OFFSET, val); #ifdef CONFIG_STM32WB_TIM1 /* Advanced registers require Main Output Enable */ - if (((struct stm32wb_tim_priv_s *)dev)->base == STM32_TIM1_BASE) + if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM1_BASE) { - stm32wb_modifyreg16(dev, STM32_TIM_BDTR_OFFSET, 0, TIM1_BDTR_MOE); + stm32_modifyreg16(dev, STM32_TIM_BDTR_OFFSET, 0, TIM1_BDTR_MOE); } #endif @@ -535,10 +535,10 @@ static int stm32wb_tim_setmode(struct stm32wb_tim_dev_s *dev, } /**************************************************************************** - * Name: stm32wb_tim_setfreq + * Name: stm32_tim_setfreq ****************************************************************************/ -static int stm32wb_tim_setfreq(struct stm32wb_tim_dev_s *dev, uint32_t freq) +static int stm32_tim_setfreq(struct stm32_tim_dev_s *dev, uint32_t freq) { uint32_t freqin; int prescaler; @@ -551,7 +551,7 @@ static int stm32wb_tim_setfreq(struct stm32wb_tim_dev_s *dev, uint32_t freq) if (freq == 0) { - stm32wb_tim_disable(dev); + stm32_tim_disable(dev); return 0; } @@ -561,7 +561,7 @@ static int stm32wb_tim_setfreq(struct stm32wb_tim_dev_s *dev, uint32_t freq) * must be defined in the board.h header file. */ - switch (((struct stm32wb_tim_priv_s *)dev)->base) + switch (((struct stm32_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32WB_TIM1 case STM32_TIM1_BASE: @@ -647,17 +647,17 @@ static int stm32wb_tim_setfreq(struct stm32wb_tim_dev_s *dev, uint32_t freq) /* Set the reload and prescaler values */ - stm32wb_putreg16(dev, STM32_TIM_PSC_OFFSET, prescaler - 1); - stm32wb_putreg16(dev, STM32_TIM_ARR_OFFSET, reload); + stm32_putreg16(dev, STM32_TIM_PSC_OFFSET, prescaler - 1); + stm32_putreg16(dev, STM32_TIM_ARR_OFFSET, reload); return (timclk / reload); } /**************************************************************************** - * Name: stm32wb_tim_setclock + * Name: stm32_tim_setclock ****************************************************************************/ -static int stm32wb_tim_setclock(struct stm32wb_tim_dev_s *dev, uint32_t freq) +static int stm32_tim_setclock(struct stm32_tim_dev_s *dev, uint32_t freq) { uint32_t freqin; int prescaler; @@ -668,7 +668,7 @@ static int stm32wb_tim_setclock(struct stm32wb_tim_dev_s *dev, uint32_t freq) if (freq == 0) { - stm32wb_tim_disable(dev); + stm32_tim_disable(dev); return 0; } @@ -678,7 +678,7 @@ static int stm32wb_tim_setclock(struct stm32wb_tim_dev_s *dev, uint32_t freq) * must be defined in the board.h header file. */ - switch (((struct stm32wb_tim_priv_s *)dev)->base) + switch (((struct stm32_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32WB_TIM1 case STM32_TIM1_BASE: @@ -730,16 +730,16 @@ static int stm32wb_tim_setclock(struct stm32wb_tim_dev_s *dev, uint32_t freq) prescaler = 0xffff; } - stm32wb_putreg16(dev, STM32_TIM_PSC_OFFSET, prescaler); + stm32_putreg16(dev, STM32_TIM_PSC_OFFSET, prescaler); return prescaler; } /**************************************************************************** - * Name: stm32wb_tim_getclock + * Name: stm32_tim_getclock ****************************************************************************/ -static uint32_t stm32wb_tim_getclock(struct stm32wb_tim_dev_s *dev) +static uint32_t stm32_tim_getclock(struct stm32_tim_dev_s *dev) { uint32_t freqin; uint32_t clock; @@ -751,7 +751,7 @@ static uint32_t stm32wb_tim_getclock(struct stm32wb_tim_dev_s *dev) * must be defined in the board.h header file. */ - switch (((struct stm32wb_tim_priv_s *)dev)->base) + switch (((struct stm32_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32WB_TIM1 case STM32_TIM1_BASE: @@ -782,44 +782,44 @@ static uint32_t stm32wb_tim_getclock(struct stm32wb_tim_dev_s *dev) /* From chip datasheet, at page 1179. */ - clock = freqin / (stm32wb_getreg16(dev, STM32_TIM_PSC_OFFSET) + 1); + clock = freqin / (stm32_getreg16(dev, STM32_TIM_PSC_OFFSET) + 1); return clock; } /**************************************************************************** - * Name: stm32wb_tim_setperiod + * Name: stm32_tim_setperiod ****************************************************************************/ -static void stm32wb_tim_setperiod(struct stm32wb_tim_dev_s *dev, +static void stm32_tim_setperiod(struct stm32_tim_dev_s *dev, uint32_t period) { DEBUGASSERT(dev != NULL); - stm32wb_putreg32(dev, STM32_TIM_ARR_OFFSET, period); + stm32_putreg32(dev, STM32_TIM_ARR_OFFSET, period); } /**************************************************************************** - * Name: stm32wb_tim_getperiod + * Name: stm32_tim_getperiod ****************************************************************************/ -static uint32_t stm32wb_tim_getperiod (struct stm32wb_tim_dev_s *dev) +static uint32_t stm32_tim_getperiod (struct stm32_tim_dev_s *dev) { DEBUGASSERT(dev != NULL); - return stm32wb_getreg32 (dev, STM32_TIM_ARR_OFFSET); + return stm32_getreg32 (dev, STM32_TIM_ARR_OFFSET); } /**************************************************************************** - * Name: stm32wb_tim_getcounter + * Name: stm32_tim_getcounter ****************************************************************************/ -static uint32_t stm32wb_tim_getcounter(struct stm32wb_tim_dev_s *dev) +static uint32_t stm32_tim_getcounter(struct stm32_tim_dev_s *dev) { DEBUGASSERT(dev != NULL); - uint32_t counter = stm32wb_getreg32(dev, STM32_TIM_CNT_OFFSET); + uint32_t counter = stm32_getreg32(dev, STM32_TIM_CNT_OFFSET); /* TIM2 is a 32-bit timer. */ #if defined(CONFIG_STM32WB_TIM2) - if (((struct stm32wb_tim_priv_s *)dev)->base == STM32_TIM2_BASE) + if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM2_BASE) { return counter; } @@ -829,15 +829,15 @@ static uint32_t stm32wb_tim_getcounter(struct stm32wb_tim_dev_s *dev) } /**************************************************************************** - * Name: stm32wb_tim_getwidth + * Name: stm32_tim_getwidth ****************************************************************************/ -static uint32_t stm32wb_tim_getwidth(struct stm32wb_tim_dev_s *dev) +static uint32_t stm32_tim_getwidth(struct stm32_tim_dev_s *dev) { /* Only TIM2 is a 32-bit timer. */ #if defined(CONFIG_STM32WB_TIM2) - if (((struct stm32wb_tim_priv_s *)dev)->base == STM32_TIM2_BASE) + if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM2_BASE) { return 32; } @@ -849,12 +849,12 @@ static uint32_t stm32wb_tim_getwidth(struct stm32wb_tim_dev_s *dev) } /**************************************************************************** - * Name: stm32wb_tim_setchannel + * Name: stm32_tim_setchannel ****************************************************************************/ -static int stm32wb_tim_setchannel(struct stm32wb_tim_dev_s *dev, +static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, uint8_t channel, - enum stm32wb_tim_channel_e mode) + enum stm32_tim_channel_e mode) { uint16_t ccmr_orig = 0; uint16_t ccmr_val = 0; @@ -872,7 +872,7 @@ static int stm32wb_tim_setchannel(struct stm32wb_tim_dev_s *dev, /* Assume that channel is disabled and polarity is active high */ - ccer_val = stm32wb_getreg16(dev, STM32_TIM_CCER_OFFSET); + ccer_val = stm32_getreg16(dev, STM32_TIM_CCER_OFFSET); ccer_val &= ~(GTIM_CCER_CCXE(channel) | GTIM_CCER_CCXP(channel)); /* Decode configuration */ @@ -903,15 +903,15 @@ static int stm32wb_tim_setchannel(struct stm32wb_tim_dev_s *dev, ccmr_offset = STM32_TIM_CCMR2_OFFSET; } - ccmr_orig = stm32wb_getreg16(dev, ccmr_offset); + ccmr_orig = stm32_getreg16(dev, ccmr_offset); ccmr_orig &= ~(GTIM_CCMR_OCXM_MASK(channel) | GTIM_CCMR_OCXPE(channel)); ccmr_orig |= ccmr_val; - stm32wb_putreg16(dev, ccmr_offset, ccmr_orig); - stm32wb_putreg16(dev, STM32_TIM_CCER_OFFSET, ccer_val); + stm32_putreg16(dev, ccmr_offset, ccmr_orig); + stm32_putreg16(dev, STM32_TIM_CCER_OFFSET, ccer_val); /* set GPIO */ - switch (((struct stm32wb_tim_priv_s *)dev)->base) + switch (((struct stm32_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32WB_TIM1 case STM32_TIM1_BASE: @@ -919,25 +919,25 @@ static int stm32wb_tim_setchannel(struct stm32wb_tim_dev_s *dev, { #if defined(GPIO_TIM1_CH1OUT) case 0: - stm32wb_tim_gpioconfig(GPIO_TIM1_CH1OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM1_CH1OUT, mode); break; #endif #if defined(GPIO_TIM1_CH2OUT) case 1: - stm32wb_tim_gpioconfig(GPIO_TIM1_CH2OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM1_CH2OUT, mode); break; #endif #if defined(GPIO_TIM1_CH3OUT) case 2: - stm32wb_tim_gpioconfig(GPIO_TIM1_CH3OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM1_CH3OUT, mode); break; #endif #if defined(GPIO_TIM1_CH4OUT) case 3: - stm32wb_tim_gpioconfig(GPIO_TIM1_CH4OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM1_CH4OUT, mode); break; #endif @@ -952,25 +952,25 @@ static int stm32wb_tim_setchannel(struct stm32wb_tim_dev_s *dev, { #if defined(GPIO_TIM2_CH1OUT) case 0: - stm32wb_tim_gpioconfig(GPIO_TIM2_CH1OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM2_CH1OUT, mode); break; #endif #if defined(GPIO_TIM2_CH2OUT) case 1: - stm32wb_tim_gpioconfig(GPIO_TIM2_CH2OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM2_CH2OUT, mode); break; #endif #if defined(GPIO_TIM2_CH3OUT) case 2: - stm32wb_tim_gpioconfig(GPIO_TIM2_CH3OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM2_CH3OUT, mode); break; #endif #if defined(GPIO_TIM2_CH4OUT) case 3: - stm32wb_tim_gpioconfig(GPIO_TIM2_CH4OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM2_CH4OUT, mode); break; #endif @@ -985,7 +985,7 @@ static int stm32wb_tim_setchannel(struct stm32wb_tim_dev_s *dev, { #if defined(GPIO_TIM16_CH1OUT) case 0: - stm32wb_tim_gpioconfig(GPIO_TIM16_CH1OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM16_CH1OUT, mode); break; #endif @@ -1000,7 +1000,7 @@ static int stm32wb_tim_setchannel(struct stm32wb_tim_dev_s *dev, { #if defined(GPIO_TIM17_CH1OUT) case 0: - stm32wb_tim_gpioconfig(GPIO_TIM17_CH1OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM17_CH1OUT, mode); break; #endif @@ -1018,10 +1018,10 @@ static int stm32wb_tim_setchannel(struct stm32wb_tim_dev_s *dev, } /**************************************************************************** - * Name: stm32wb_tim_setcompare + * Name: stm32_tim_setcompare ****************************************************************************/ -static int stm32wb_tim_setcompare(struct stm32wb_tim_dev_s *dev, +static int stm32_tim_setcompare(struct stm32_tim_dev_s *dev, uint8_t channel, uint32_t compare) { DEBUGASSERT(dev != NULL); @@ -1029,19 +1029,19 @@ static int stm32wb_tim_setcompare(struct stm32wb_tim_dev_s *dev, switch (channel) { case 1: - stm32wb_putreg32(dev, STM32_TIM_CCR1_OFFSET, compare); + stm32_putreg32(dev, STM32_TIM_CCR1_OFFSET, compare); break; case 2: - stm32wb_putreg32(dev, STM32_TIM_CCR2_OFFSET, compare); + stm32_putreg32(dev, STM32_TIM_CCR2_OFFSET, compare); break; case 3: - stm32wb_putreg32(dev, STM32_TIM_CCR3_OFFSET, compare); + stm32_putreg32(dev, STM32_TIM_CCR3_OFFSET, compare); break; case 4: - stm32wb_putreg32(dev, STM32_TIM_CCR4_OFFSET, compare); + stm32_putreg32(dev, STM32_TIM_CCR4_OFFSET, compare); break; default: @@ -1052,10 +1052,10 @@ static int stm32wb_tim_setcompare(struct stm32wb_tim_dev_s *dev, } /**************************************************************************** - * Name: stm32wb_tim_getcapture + * Name: stm32_tim_getcapture ****************************************************************************/ -static uint32_t stm32wb_tim_getcapture(struct stm32wb_tim_dev_s *dev, +static uint32_t stm32_tim_getcapture(struct stm32_tim_dev_s *dev, uint8_t channel) { DEBUGASSERT(dev != NULL); @@ -1063,26 +1063,26 @@ static uint32_t stm32wb_tim_getcapture(struct stm32wb_tim_dev_s *dev, switch (channel) { case 1: - return stm32wb_getreg32(dev, STM32_TIM_CCR1_OFFSET); + return stm32_getreg32(dev, STM32_TIM_CCR1_OFFSET); case 2: - return stm32wb_getreg32(dev, STM32_TIM_CCR2_OFFSET); + return stm32_getreg32(dev, STM32_TIM_CCR2_OFFSET); case 3: - return stm32wb_getreg32(dev, STM32_TIM_CCR3_OFFSET); + return stm32_getreg32(dev, STM32_TIM_CCR3_OFFSET); case 4: - return stm32wb_getreg32(dev, STM32_TIM_CCR4_OFFSET); + return stm32_getreg32(dev, STM32_TIM_CCR4_OFFSET); } return -EINVAL; } /**************************************************************************** - * Name: stm32wb_tim_setisr + * Name: stm32_tim_setisr ****************************************************************************/ -static int stm32wb_tim_setisr(struct stm32wb_tim_dev_s *dev, +static int stm32_tim_setisr(struct stm32_tim_dev_s *dev, xcpt_t handler, void *arg, int source) { int vectorno; @@ -1090,7 +1090,7 @@ static int stm32wb_tim_setisr(struct stm32wb_tim_dev_s *dev, DEBUGASSERT(dev != NULL); DEBUGASSERT(source == 0); - switch (((struct stm32wb_tim_priv_s *)dev)->base) + switch (((struct stm32_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32WB_TIM1 case STM32_TIM1_BASE: @@ -1138,41 +1138,41 @@ static int stm32wb_tim_setisr(struct stm32wb_tim_dev_s *dev, } /**************************************************************************** - * Name: stm32wb_tim_enableint + * Name: stm32_tim_enableint ****************************************************************************/ -static void stm32wb_tim_enableint(struct stm32wb_tim_dev_s *dev, int source) +static void stm32_tim_enableint(struct stm32_tim_dev_s *dev, int source) { DEBUGASSERT(dev != NULL); - stm32wb_modifyreg16(dev, STM32_TIM_DIER_OFFSET, 0, source); + stm32_modifyreg16(dev, STM32_TIM_DIER_OFFSET, 0, source); } /**************************************************************************** - * Name: stm32wb_tim_disableint + * Name: stm32_tim_disableint ****************************************************************************/ -static void stm32wb_tim_disableint(struct stm32wb_tim_dev_s *dev, int source) +static void stm32_tim_disableint(struct stm32_tim_dev_s *dev, int source) { DEBUGASSERT(dev != NULL); - stm32wb_modifyreg16(dev, STM32_TIM_DIER_OFFSET, source, 0); + stm32_modifyreg16(dev, STM32_TIM_DIER_OFFSET, source, 0); } /**************************************************************************** - * Name: stm32wb_tim_ackint + * Name: stm32_tim_ackint ****************************************************************************/ -static void stm32wb_tim_ackint(struct stm32wb_tim_dev_s *dev, int source) +static void stm32_tim_ackint(struct stm32_tim_dev_s *dev, int source) { - stm32wb_putreg16(dev, STM32_TIM_SR_OFFSET, ~source); + stm32_putreg16(dev, STM32_TIM_SR_OFFSET, ~source); } /**************************************************************************** - * Name: stm32wb_tim_checkint + * Name: stm32_tim_checkint ****************************************************************************/ -static int stm32wb_tim_checkint(struct stm32wb_tim_dev_s *dev, int source) +static int stm32_tim_checkint(struct stm32_tim_dev_s *dev, int source) { - uint16_t regval = stm32wb_getreg16(dev, STM32_TIM_SR_OFFSET); + uint16_t regval = stm32_getreg16(dev, STM32_TIM_SR_OFFSET); return (regval & source) ? 1 : 0; } @@ -1181,12 +1181,12 @@ static int stm32wb_tim_checkint(struct stm32wb_tim_dev_s *dev, int source) ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_tim_init + * Name: stm32_tim_init ****************************************************************************/ -struct stm32wb_tim_dev_s *stm32wb_tim_init(int timer) +struct stm32_tim_dev_s *stm32_tim_init(int timer) { - struct stm32wb_tim_dev_s *dev = NULL; + struct stm32_tim_dev_s *dev = NULL; /* Get structure and enable power */ @@ -1194,28 +1194,28 @@ struct stm32wb_tim_dev_s *stm32wb_tim_init(int timer) { #ifdef CONFIG_STM32WB_TIM1 case 1: - dev = (struct stm32wb_tim_dev_s *)&stm32wb_tim1_priv; + dev = (struct stm32_tim_dev_s *)&stm32_tim1_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM1EN); break; #endif #ifdef CONFIG_STM32WB_TIM2 case 2: - dev = (struct stm32wb_tim_dev_s *)&stm32wb_tim2_priv; + dev = (struct stm32_tim_dev_s *)&stm32_tim2_priv; modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM2EN); break; #endif #ifdef CONFIG_STM32WB_TIM16 case 16: - dev = (struct stm32wb_tim_dev_s *)&stm32wb_tim16_priv; + dev = (struct stm32_tim_dev_s *)&stm32_tim16_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM16EN); break; #endif #ifdef CONFIG_STM32WB_TIM17 case 17: - dev = (struct stm32wb_tim_dev_s *)&stm32wb_tim17_priv; + dev = (struct stm32_tim_dev_s *)&stm32_tim17_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM17EN); break; #endif @@ -1226,30 +1226,30 @@ struct stm32wb_tim_dev_s *stm32wb_tim_init(int timer) /* Is device already allocated */ - if (((struct stm32wb_tim_priv_s *)dev)->mode != STM32_TIM_MODE_UNUSED) + if (((struct stm32_tim_priv_s *)dev)->mode != STM32_TIM_MODE_UNUSED) { return NULL; } - stm32wb_tim_reset(dev); + stm32_tim_reset(dev); return dev; } /**************************************************************************** - * Name: stm32wb_tim_deinit + * Name: stm32_tim_deinit * * TODO: Detach interrupts, and close down all TIM Channels * ****************************************************************************/ -int stm32wb_tim_deinit(struct stm32wb_tim_dev_s *dev) +int stm32_tim_deinit(struct stm32_tim_dev_s *dev) { DEBUGASSERT(dev != NULL); /* Disable power */ - switch (((struct stm32wb_tim_priv_s *)dev)->base) + switch (((struct stm32_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32WB_TIM1 case STM32_TIM1_BASE: @@ -1281,7 +1281,7 @@ int stm32wb_tim_deinit(struct stm32wb_tim_dev_s *dev) /* Mark it as free */ - ((struct stm32wb_tim_priv_s *)dev)->mode = STM32_TIM_MODE_UNUSED; + ((struct stm32_tim_priv_s *)dev)->mode = STM32_TIM_MODE_UNUSED; return OK; } diff --git a/arch/arm/src/stm32wb/stm32wb_tim.h b/arch/arm/src/stm32wb/stm32wb_tim.h index ead07f60195..a7ea2c73451 100644 --- a/arch/arm/src/stm32wb/stm32wb_tim.h +++ b/arch/arm/src/stm32wb/stm32wb_tim.h @@ -101,14 +101,14 @@ extern "C" /* TIM Device Structure */ -struct stm32wb_tim_dev_s +struct stm32_tim_dev_s { - struct stm32wb_tim_ops_s *ops; + struct stm32_tim_ops_s *ops; }; /* TIM Modes of Operation */ -enum stm32wb_tim_mode_e +enum stm32_tim_mode_e { STM32_TIM_MODE_UNUSED = -1, @@ -145,7 +145,7 @@ enum stm32wb_tim_mode_e /* TIM Channel Modes */ -enum stm32wb_tim_channel_e +enum stm32_tim_channel_e { STM32_TIM_CH_DISABLED = 0x00, @@ -178,37 +178,37 @@ enum stm32wb_tim_channel_e /* TIM Operations */ -struct stm32wb_tim_ops_s +struct stm32_tim_ops_s { - void (*enable)(struct stm32wb_tim_dev_s *dev); - void (*disable)(struct stm32wb_tim_dev_s *dev); - int (*setmode)(struct stm32wb_tim_dev_s *dev, - enum stm32wb_tim_mode_e mode); - int (*setfreq)(struct stm32wb_tim_dev_s *dev, uint32_t freq); - int (*setclock)(struct stm32wb_tim_dev_s *dev, uint32_t freq); - uint32_t (*getclock)(struct stm32wb_tim_dev_s *dev); - void (*setperiod)(struct stm32wb_tim_dev_s *dev, uint32_t period); - uint32_t (*getperiod)(struct stm32wb_tim_dev_s *dev); - uint32_t (*getcounter)(struct stm32wb_tim_dev_s *dev); - uint32_t (*getwidth)(struct stm32wb_tim_dev_s *dev); - int (*setchannel)(struct stm32wb_tim_dev_s *dev, uint8_t channel, - enum stm32wb_tim_channel_e mode); - int (*setcompare)(struct stm32wb_tim_dev_s *dev, uint8_t channel, + void (*enable)(struct stm32_tim_dev_s *dev); + void (*disable)(struct stm32_tim_dev_s *dev); + int (*setmode)(struct stm32_tim_dev_s *dev, + enum stm32_tim_mode_e mode); + int (*setfreq)(struct stm32_tim_dev_s *dev, uint32_t freq); + int (*setclock)(struct stm32_tim_dev_s *dev, uint32_t freq); + uint32_t (*getclock)(struct stm32_tim_dev_s *dev); + void (*setperiod)(struct stm32_tim_dev_s *dev, uint32_t period); + uint32_t (*getperiod)(struct stm32_tim_dev_s *dev); + uint32_t (*getcounter)(struct stm32_tim_dev_s *dev); + uint32_t (*getwidth)(struct stm32_tim_dev_s *dev); + int (*setchannel)(struct stm32_tim_dev_s *dev, uint8_t channel, + enum stm32_tim_channel_e mode); + int (*setcompare)(struct stm32_tim_dev_s *dev, uint8_t channel, uint32_t compare); - uint32_t (*getcapture)(struct stm32wb_tim_dev_s *dev, uint8_t channel); + uint32_t (*getcapture)(struct stm32_tim_dev_s *dev, uint8_t channel); /* Timer interrupts */ - int (*setisr)(struct stm32wb_tim_dev_s *dev, + int (*setisr)(struct stm32_tim_dev_s *dev, xcpt_t handler, void *arg, int source); - void (*enableint)(struct stm32wb_tim_dev_s *dev, int source); - void (*disableint)(struct stm32wb_tim_dev_s *dev, int source); - void (*ackint)(struct stm32wb_tim_dev_s *dev, int source); - int (*checkint)(struct stm32wb_tim_dev_s *dev, int source); + void (*enableint)(struct stm32_tim_dev_s *dev, int source); + void (*disableint)(struct stm32_tim_dev_s *dev, int source); + void (*ackint)(struct stm32_tim_dev_s *dev, int source); + int (*checkint)(struct stm32_tim_dev_s *dev, int source); /* Debug */ - void (*dump_regs)(struct stm32wb_tim_dev_s *dev); + void (*dump_regs)(struct stm32_tim_dev_s *dev); }; /**************************************************************************** @@ -217,14 +217,14 @@ struct stm32wb_tim_ops_s /* Power-up timer and get its structure */ -struct stm32wb_tim_dev_s *stm32wb_tim_init(int timer); +struct stm32_tim_dev_s *stm32_tim_init(int timer); /* Power-down timer, mark it as unused */ -int stm32wb_tim_deinit(struct stm32wb_tim_dev_s *dev); +int stm32_tim_deinit(struct stm32_tim_dev_s *dev); /**************************************************************************** - * Name: stm32wb_timer_initialize + * Name: stm32_timer_initialize * * Description: * Bind the configuration timer to a timer lower half instance and @@ -242,7 +242,7 @@ int stm32wb_tim_deinit(struct stm32wb_tim_dev_s *dev); ****************************************************************************/ #ifdef CONFIG_TIMER -int stm32wb_timer_initialize(const char *devpath, int timer); +int stm32_timer_initialize(const char *devpath, int timer); #endif #undef EXTERN diff --git a/arch/arm/src/stm32wb/stm32wb_tim_lowerhalf.c b/arch/arm/src/stm32wb/stm32wb_tim_lowerhalf.c index ced3f62d5f9..37e35b0f985 100644 --- a/arch/arm/src/stm32wb/stm32wb_tim_lowerhalf.c +++ b/arch/arm/src/stm32wb/stm32wb_tim_lowerhalf.c @@ -58,10 +58,10 @@ * timer_lowerhalf_s structure. */ -struct stm32wb_lowerhalf_s +struct stm32_lowerhalf_s { const struct timer_ops_s *ops; /* Lower half operations */ - struct stm32wb_tim_dev_s *tim; /* stm32 timer driver */ + struct stm32_tim_dev_s *tim; /* stm32 timer driver */ tccb_t callback; /* Current upper half interrupt callback */ void *arg; /* Argument passed to upper half callback */ bool started; /* True: Timer has been started */ @@ -74,17 +74,17 @@ struct stm32wb_lowerhalf_s /* Interrupt handling *******************************************************/ -static int stm32wb_timer_handler(int irq, void *context, void *arg); +static int stm32_timer_handler(int irq, void *context, void *arg); /* "Lower half" driver methods **********************************************/ -static int stm32wb_start(struct timer_lowerhalf_s *lower); -static int stm32wb_stop(struct timer_lowerhalf_s *lower); -static int stm32wb_getstatus(struct timer_lowerhalf_s *lower, +static int stm32_start(struct timer_lowerhalf_s *lower); +static int stm32_stop(struct timer_lowerhalf_s *lower); +static int stm32_getstatus(struct timer_lowerhalf_s *lower, struct timer_status_s *status); -static int stm32wb_settimeout(struct timer_lowerhalf_s *lower, +static int stm32_settimeout(struct timer_lowerhalf_s *lower, uint32_t timeout); -static void stm32wb_setcallback(struct timer_lowerhalf_s *lower, +static void stm32_setcallback(struct timer_lowerhalf_s *lower, tccb_t callback, void *arg); /**************************************************************************** @@ -95,16 +95,16 @@ static void stm32wb_setcallback(struct timer_lowerhalf_s *lower, static const struct timer_ops_s g_timer_ops = { - .start = stm32wb_start, - .stop = stm32wb_stop, - .getstatus = stm32wb_getstatus, - .settimeout = stm32wb_settimeout, - .setcallback = stm32wb_setcallback, + .start = stm32_start, + .stop = stm32_stop, + .getstatus = stm32_getstatus, + .settimeout = stm32_settimeout, + .setcallback = stm32_setcallback, .ioctl = NULL, }; #ifdef CONFIG_STM32WB_TIM1 -static struct stm32wb_lowerhalf_s g_tim1_lowerhalf = +static struct stm32_lowerhalf_s g_tim1_lowerhalf = { .ops = &g_timer_ops, .resolution = STM32_TIM1_RES, @@ -112,7 +112,7 @@ static struct stm32wb_lowerhalf_s g_tim1_lowerhalf = #endif #ifdef CONFIG_STM32WB_TIM2 -static struct stm32wb_lowerhalf_s g_tim2_lowerhalf = +static struct stm32_lowerhalf_s g_tim2_lowerhalf = { .ops = &g_timer_ops, .resolution = STM32_TIM2_RES, @@ -120,7 +120,7 @@ static struct stm32wb_lowerhalf_s g_tim2_lowerhalf = #endif #ifdef CONFIG_STM32WB_TIM16 -static struct stm32wb_lowerhalf_s g_tim16_lowerhalf = +static struct stm32_lowerhalf_s g_tim16_lowerhalf = { .ops = &g_timer_ops, .resolution = STM32_TIM16_RES, @@ -128,7 +128,7 @@ static struct stm32wb_lowerhalf_s g_tim16_lowerhalf = #endif #ifdef CONFIG_STM32WB_TIM17 -static struct stm32wb_lowerhalf_s g_tim17_lowerhalf = +static struct stm32_lowerhalf_s g_tim17_lowerhalf = { .ops = &g_timer_ops, .resolution = STM32_TIM17_RES, @@ -140,7 +140,7 @@ static struct stm32wb_lowerhalf_s g_tim17_lowerhalf = ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_timer_handler + * Name: stm32_timer_handler * * Description: * timer interrupt handler @@ -151,9 +151,9 @@ static struct stm32wb_lowerhalf_s g_tim17_lowerhalf = * ****************************************************************************/ -static int stm32wb_timer_handler(int irq, void *context, void *arg) +static int stm32_timer_handler(int irq, void *context, void *arg) { - struct stm32wb_lowerhalf_s *lower = (struct stm32wb_lowerhalf_s *)arg; + struct stm32_lowerhalf_s *lower = (struct stm32_lowerhalf_s *)arg; uint32_t next_interval_us = 0; STM32_TIM_ACKINT(lower->tim, GTIM_DIER_UIE); @@ -167,14 +167,14 @@ static int stm32wb_timer_handler(int irq, void *context, void *arg) } else { - stm32wb_stop((struct timer_lowerhalf_s *)lower); + stm32_stop((struct timer_lowerhalf_s *)lower); } return OK; } /**************************************************************************** - * Name: stm32wb_start + * Name: stm32_start * * Description: * Start the timer, resetting the time to the current timeout, @@ -188,9 +188,9 @@ static int stm32wb_timer_handler(int irq, void *context, void *arg) * ****************************************************************************/ -static int stm32wb_start(struct timer_lowerhalf_s *lower) +static int stm32_start(struct timer_lowerhalf_s *lower) { - struct stm32wb_lowerhalf_s *priv = (struct stm32wb_lowerhalf_s *)lower; + struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; if (!priv->started) { @@ -198,7 +198,7 @@ static int stm32wb_start(struct timer_lowerhalf_s *lower) if (priv->callback != NULL) { - STM32_TIM_SETISR(priv->tim, stm32wb_timer_handler, priv, 0); + STM32_TIM_SETISR(priv->tim, stm32_timer_handler, priv, 0); STM32_TIM_ENABLEINT(priv->tim, GTIM_DIER_UIE); } @@ -212,7 +212,7 @@ static int stm32wb_start(struct timer_lowerhalf_s *lower) } /**************************************************************************** - * Name: stm32wb_stop + * Name: stm32_stop * * Description: * Stop the timer @@ -226,9 +226,9 @@ static int stm32wb_start(struct timer_lowerhalf_s *lower) * ****************************************************************************/ -static int stm32wb_stop(struct timer_lowerhalf_s *lower) +static int stm32_stop(struct timer_lowerhalf_s *lower) { - struct stm32wb_lowerhalf_s *priv = (struct stm32wb_lowerhalf_s *)lower; + struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; if (priv->started) { @@ -245,7 +245,7 @@ static int stm32wb_stop(struct timer_lowerhalf_s *lower) } /**************************************************************************** - * Name: stm32wb_getstatus + * Name: stm32_getstatus * * Description: * get timer status @@ -260,10 +260,10 @@ static int stm32wb_stop(struct timer_lowerhalf_s *lower) * ****************************************************************************/ -static int stm32wb_getstatus(struct timer_lowerhalf_s *lower, +static int stm32_getstatus(struct timer_lowerhalf_s *lower, struct timer_status_s *status) { - struct stm32wb_lowerhalf_s *priv = (struct stm32wb_lowerhalf_s *)lower; + struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; uint64_t maxtimeout; uint32_t timeout; uint32_t clock; @@ -311,7 +311,7 @@ static int stm32wb_getstatus(struct timer_lowerhalf_s *lower, } /**************************************************************************** - * Name: stm32wb_settimeout + * Name: stm32_settimeout * * Description: * Set a new timeout value (and reset the timer) @@ -326,10 +326,10 @@ static int stm32wb_getstatus(struct timer_lowerhalf_s *lower, * ****************************************************************************/ -static int stm32wb_settimeout(struct timer_lowerhalf_s *lower, +static int stm32_settimeout(struct timer_lowerhalf_s *lower, uint32_t timeout) { - struct stm32wb_lowerhalf_s *priv = (struct stm32wb_lowerhalf_s *)lower; + struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; uint64_t maxtimeout; if (priv->started) @@ -354,7 +354,7 @@ static int stm32wb_settimeout(struct timer_lowerhalf_s *lower, } /**************************************************************************** - * Name: stm32wb_sethandler + * Name: stm32_sethandler * * Description: * Call this user provided timeout handler. @@ -373,10 +373,10 @@ static int stm32wb_settimeout(struct timer_lowerhalf_s *lower, * ****************************************************************************/ -static void stm32wb_setcallback(struct timer_lowerhalf_s *lower, +static void stm32_setcallback(struct timer_lowerhalf_s *lower, tccb_t callback, void *arg) { - struct stm32wb_lowerhalf_s *priv = (struct stm32wb_lowerhalf_s *)lower; + struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; irqstate_t flags = enter_critical_section(); /* Save the new callback */ @@ -386,7 +386,7 @@ static void stm32wb_setcallback(struct timer_lowerhalf_s *lower, if (callback != NULL && priv->started) { - STM32_TIM_SETISR(priv->tim, stm32wb_timer_handler, priv, 0); + STM32_TIM_SETISR(priv->tim, stm32_timer_handler, priv, 0); STM32_TIM_ENABLEINT(priv->tim, GTIM_DIER_UIE); } else @@ -403,7 +403,7 @@ static void stm32wb_setcallback(struct timer_lowerhalf_s *lower, ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_timer_initialize + * Name: stm32_timer_initialize * * Description: * Bind the configuration timer to a timer lower half instance and @@ -420,9 +420,9 @@ static void stm32wb_setcallback(struct timer_lowerhalf_s *lower, * ****************************************************************************/ -int stm32wb_timer_initialize(const char *devpath, int timer) +int stm32_timer_initialize(const char *devpath, int timer) { - struct stm32wb_lowerhalf_s *lower; + struct stm32_lowerhalf_s *lower; switch (timer) { @@ -458,7 +458,7 @@ int stm32wb_timer_initialize(const char *devpath, int timer) lower->started = false; lower->callback = NULL; - lower->tim = stm32wb_tim_init(timer); + lower->tim = stm32_tim_init(timer); if (lower->tim == NULL) { diff --git a/arch/arm/src/stm32wb/stm32wb_timerisr.c b/arch/arm/src/stm32wb/stm32wb_timerisr.c index a01219c737b..7a9f118a595 100644 --- a/arch/arm/src/stm32wb/stm32wb_timerisr.c +++ b/arch/arm/src/stm32wb/stm32wb_timerisr.c @@ -77,7 +77,7 @@ ****************************************************************************/ /**************************************************************************** - * Function: stm32wb_timerisr + * Function: stm32_timerisr * * Description: * The timer ISR will perform a variety of services for various portions @@ -85,7 +85,7 @@ * ****************************************************************************/ -static int stm32wb_timerisr(int irq, uint32_t *regs, void *arg) +static int stm32_timerisr(int irq, uint32_t *regs, void *arg) { /* Process timer interrupt */ @@ -135,7 +135,7 @@ void up_timer_initialize(void) /* Attach the timer interrupt vector */ - irq_attach(STM32_IRQ_SYSTICK, (xcpt_t)stm32wb_timerisr, NULL); + irq_attach(STM32_IRQ_SYSTICK, (xcpt_t)stm32_timerisr, NULL); /* Enable SysTick interrupts */ diff --git a/arch/arm/src/stm32wb/stm32wb_uart.h b/arch/arm/src/stm32wb/stm32wb_uart.h index dc4e2dadff4..2fd4f3019d1 100644 --- a/arch/arm/src/stm32wb/stm32wb_uart.h +++ b/arch/arm/src/stm32wb/stm32wb_uart.h @@ -151,7 +151,7 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_serial_dma_poll + * Name: stm32_serial_dma_poll * * Description: * Must be called periodically if any STM32WB UART is configured for DMA. @@ -164,7 +164,7 @@ extern "C" ****************************************************************************/ #ifdef SERIAL_HAVE_RXDMA -void stm32wb_serial_dma_poll(void); +void stm32_serial_dma_poll(void); #endif #undef EXTERN diff --git a/arch/arm/src/stm32wb/stm32wb_uid.c b/arch/arm/src/stm32wb/stm32wb_uid.c index 17a3808d363..da688a44086 100644 --- a/arch/arm/src/stm32wb/stm32wb_uid.c +++ b/arch/arm/src/stm32wb/stm32wb_uid.c @@ -35,7 +35,7 @@ * Public Functions ****************************************************************************/ -void stm32wb_get_uniqueid(uint8_t uniqueid[12]) +void stm32_get_uniqueid(uint8_t uniqueid[12]) { int i; diff --git a/arch/arm/src/stm32wb/stm32wb_uid.h b/arch/arm/src/stm32wb/stm32wb_uid.h index e1f01292df5..8b95f7d1f68 100644 --- a/arch/arm/src/stm32wb/stm32wb_uid.h +++ b/arch/arm/src/stm32wb/stm32wb_uid.h @@ -33,6 +33,6 @@ * Public Function Prototypes ****************************************************************************/ -void stm32wb_get_uniqueid(uint8_t uniqueid[12]); +void stm32_get_uniqueid(uint8_t uniqueid[12]); #endif /* __ARCH_ARM_SRC_STM32WB_STM32WB_UID_H */ diff --git a/arch/arm/src/stm32wb/stm32wb_userspace.c b/arch/arm/src/stm32wb/stm32wb_userspace.c index 6f9a3451e63..e07473c8d67 100644 --- a/arch/arm/src/stm32wb/stm32wb_userspace.c +++ b/arch/arm/src/stm32wb/stm32wb_userspace.c @@ -41,7 +41,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_userspace + * Name: stm32_userspace * * Description: * For the case of the separate user-/kernel-space build, perform whatever @@ -51,7 +51,7 @@ * ****************************************************************************/ -void stm32wb_userspace(void) +void stm32_userspace(void) { uint8_t *src; uint8_t *dest; @@ -87,7 +87,7 @@ void stm32wb_userspace(void) /* Configure the MPU to permit user-space access to its FLASH and RAM */ - stm32wb_mpuinitialize(); + stm32_mpuinitialize(); } #endif /* CONFIG_BUILD_PROTECTED */ diff --git a/arch/arm/src/stm32wb/stm32wb_userspace.h b/arch/arm/src/stm32wb/stm32wb_userspace.h index 4a428e9b7c8..26526ef2128 100644 --- a/arch/arm/src/stm32wb/stm32wb_userspace.h +++ b/arch/arm/src/stm32wb/stm32wb_userspace.h @@ -34,7 +34,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_userspace + * Name: stm32_userspace * * Description: * For the case of the separate user-/kernel-space build, perform whatever @@ -45,7 +45,7 @@ ****************************************************************************/ #ifdef CONFIG_BUILD_PROTECTED -void stm32wb_userspace(void); +void stm32_userspace(void); #endif #endif /* __ARCH_ARM_SRC_STM32W_STM32W_USERSPACE_H */ diff --git a/arch/arm/src/stm32wb/stm32wb_waste.c b/arch/arm/src/stm32wb/stm32wb_waste.c index 48f022c7d48..a3660b4ee5b 100644 --- a/arch/arm/src/stm32wb/stm32wb_waste.c +++ b/arch/arm/src/stm32wb/stm32wb_waste.c @@ -40,7 +40,7 @@ uint32_t g_waste_counter; * Public Functions ****************************************************************************/ -void stm32wb_waste(void) +void stm32_waste(void) { g_waste_counter++; } diff --git a/arch/arm/src/stm32wb/stm32wb_waste.h b/arch/arm/src/stm32wb/stm32wb_waste.h index 97660bf1608..66c493178f5 100644 --- a/arch/arm/src/stm32wb/stm32wb_waste.h +++ b/arch/arm/src/stm32wb/stm32wb_waste.h @@ -46,7 +46,7 @@ extern "C" /* Waste CPU Time * - * stm32wb_waste() is the logic that will be executed when portions of + * stm32_waste() is the logic that will be executed when portions of * kernel or user-app is polling some register or similar, waiting for * desired status. This time is wasted away. This function offers a * measure of badly written piece of software or some undesired behavior. @@ -55,7 +55,7 @@ extern "C" * cannot be used for other purposes (yet). */ -void stm32wb_waste(void); +void stm32_waste(void); #undef EXTERN #if defined(__cplusplus) diff --git a/boards/arm/stm32wb/flipperzero/include/board.h b/boards/arm/stm32wb/flipperzero/include/board.h index bb948a3f3c6..606ccde42c5 100644 --- a/boards/arm/stm32wb/flipperzero/include/board.h +++ b/boards/arm/stm32wb/flipperzero/include/board.h @@ -113,7 +113,7 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_board_initialize + * Name: stm32_board_initialize * * Description: * All STM32WB architectures must provide the following entry point. @@ -123,7 +123,7 @@ extern "C" * ****************************************************************************/ -void stm32wb_board_initialize(void); +void stm32_board_initialize(void); #undef EXTERN #if defined(__cplusplus) diff --git a/boards/arm/stm32wb/flipperzero/src/flipperzero.h b/boards/arm/stm32wb/flipperzero/src/flipperzero.h index b7b1015a424..db2509ef533 100644 --- a/boards/arm/stm32wb/flipperzero/src/flipperzero.h +++ b/boards/arm/stm32wb/flipperzero/src/flipperzero.h @@ -82,7 +82,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_spidev_initialize + * Name: stm32_spidev_initialize * * Description: * Called to configure SPI chip select GPIO pins. @@ -90,7 +90,7 @@ ****************************************************************************/ #ifdef CONFIG_SPI -void weak_function stm32wb_spidev_initialize(void); +void weak_function stm32_spidev_initialize(void); #endif #endif /* __ASSEMBLY__ */ diff --git a/boards/arm/stm32wb/flipperzero/src/stm32_boot.c b/boards/arm/stm32wb/flipperzero/src/stm32_boot.c index b83f7f7bab3..334cf54abbe 100644 --- a/boards/arm/stm32wb/flipperzero/src/stm32_boot.c +++ b/boards/arm/stm32wb/flipperzero/src/stm32_boot.c @@ -58,7 +58,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_board_initialize + * Name: stm32_board_initialize * * Description: * All STM32WB architectures must provide the following entry point. This @@ -68,16 +68,16 @@ * ****************************************************************************/ -void stm32wb_board_initialize(void) +void stm32_board_initialize(void) { /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak * function stm32_spidev_initialize() has been brought into the link. */ #ifdef CONFIG_SPI - if (stm32wb_spidev_initialize) + if (stm32_spidev_initialize) { - stm32wb_spidev_initialize(); + stm32_spidev_initialize(); } #endif @@ -142,7 +142,7 @@ void board_late_initialize(void) #ifdef CONFIG_RTC_DRIVER /* Instantiate the STM32WB lower-half RTC driver */ - rtclower = stm32wb_rtc_lowerhalf(); + rtclower = stm32_rtc_lowerhalf(); if (!rtclower) { serr("ERROR: Failed to instantiate the RTC lower-half driver\n"); @@ -166,7 +166,7 @@ void board_late_initialize(void) #ifdef CONFIG_TIMER /* Initialize and register the timer driver */ - ret = stm32wb_timer_initialize("/dev/timer0", 1); + ret = stm32_timer_initialize("/dev/timer0", 1); if (ret < 0) { syslog(LOG_ERR, "ERROR: Failed to register the timer driver: %d\n", @@ -186,7 +186,7 @@ void board_late_initialize(void) #ifdef CONFIG_STM32WB_BLE /* Initialize and register BLE HCI driver */ - stm32wb_blehci_initialize(); + stm32_blehci_initialize(); #endif } #endif @@ -206,7 +206,7 @@ int board_uniqueid(uint8_t *uniqueid) return -EINVAL; } - stm32wb_get_uniqueid(uniqueid); + stm32_get_uniqueid(uniqueid); return OK; } #endif diff --git a/boards/arm/stm32wb/flipperzero/src/stm32_lcd_st7565.c b/boards/arm/stm32wb/flipperzero/src/stm32_lcd_st7565.c index 4eea343833d..de3771d6062 100644 --- a/boards/arm/stm32wb/flipperzero/src/stm32_lcd_st7565.c +++ b/boards/arm/stm32wb/flipperzero/src/stm32_lcd_st7565.c @@ -55,14 +55,14 @@ * Private Function Prototypes ****************************************************************************/ -static void stm32wb_st7565_reset(struct st7565_lcd_s *lcd, bool on); -static void stm32wb_st7565_select(struct st7565_lcd_s *lcd); -static void stm32wb_st7565_deselect(struct st7565_lcd_s *lcd); -static void stm32wb_st7565_cmddata(struct st7565_lcd_s *lcd, +static void stm32_st7565_reset(struct st7565_lcd_s *lcd, bool on); +static void stm32_st7565_select(struct st7565_lcd_s *lcd); +static void stm32_st7565_deselect(struct st7565_lcd_s *lcd); +static void stm32_st7565_cmddata(struct st7565_lcd_s *lcd, const uint8_t cmd); -static int stm32wb_st7565_senddata(struct st7565_lcd_s *lcd, +static int stm32_st7565_senddata(struct st7565_lcd_s *lcd, const uint8_t *data, int size); -static int stm32wb_st7565_backlight(struct st7565_lcd_s *lcd, int level); +static int stm32_st7565_backlight(struct st7565_lcd_s *lcd, int level); /**************************************************************************** * Private Data @@ -73,43 +73,43 @@ static struct lcd_dev_s *g_lcddev; static struct st7565_lcd_s g_st7565_dev = { - .reset = stm32wb_st7565_reset, - .select = stm32wb_st7565_select, - .deselect = stm32wb_st7565_deselect, - .cmddata = stm32wb_st7565_cmddata, - .senddata = stm32wb_st7565_senddata, - .backlight = stm32wb_st7565_backlight + .reset = stm32_st7565_reset, + .select = stm32_st7565_select, + .deselect = stm32_st7565_deselect, + .cmddata = stm32_st7565_cmddata, + .senddata = stm32_st7565_senddata, + .backlight = stm32_st7565_backlight }; -static void stm32wb_st7565_reset(struct st7565_lcd_s *lcd, bool on) +static void stm32_st7565_reset(struct st7565_lcd_s *lcd, bool on) { - stm32wb_gpiowrite(STM32_LCD_RST, !on); + stm32_gpiowrite(STM32_LCD_RST, !on); } -static void stm32wb_st7565_select(struct st7565_lcd_s *lcd) +static void stm32_st7565_select(struct st7565_lcd_s *lcd) { - stm32wb_gpiowrite(STM32_LCD_CS, 0); + stm32_gpiowrite(STM32_LCD_CS, 0); } -static void stm32wb_st7565_deselect(struct st7565_lcd_s *lcd) +static void stm32_st7565_deselect(struct st7565_lcd_s *lcd) { - stm32wb_gpiowrite(STM32_LCD_CS, 1); + stm32_gpiowrite(STM32_LCD_CS, 1); } -static void stm32wb_st7565_cmddata(struct st7565_lcd_s *lcd, +static void stm32_st7565_cmddata(struct st7565_lcd_s *lcd, const uint8_t cmd) { - stm32wb_gpiowrite(STM32_LCD_A0, !cmd); + stm32_gpiowrite(STM32_LCD_A0, !cmd); } -static int stm32wb_st7565_senddata(struct st7565_lcd_s *lcd, +static int stm32_st7565_senddata(struct st7565_lcd_s *lcd, const uint8_t *data, int size) { SPI_SNDBLOCK(g_spidev, data, size); return 0; } -static int stm32wb_st7565_backlight(struct st7565_lcd_s *lcd, int level) +static int stm32_st7565_backlight(struct st7565_lcd_s *lcd, int level) { return 0; } @@ -124,10 +124,10 @@ static int stm32wb_st7565_backlight(struct st7565_lcd_s *lcd, int level) int board_lcd_initialize(void) { - stm32wb_configgpio(STM32_LCD_RST); - stm32wb_configgpio(STM32_LCD_A0); + stm32_configgpio(STM32_LCD_RST); + stm32_configgpio(STM32_LCD_A0); - g_spidev = stm32wb_spibus_initialize(STM32_LCD_SPINO); + g_spidev = stm32_spibus_initialize(STM32_LCD_SPINO); if (!g_spidev) { @@ -139,9 +139,9 @@ int board_lcd_initialize(void) g_spidev->ops->setbits(g_spidev, 8); g_spidev->ops->setfrequency(g_spidev, 1000000); - stm32wb_gpiowrite(STM32_LCD_RST, 0); + stm32_gpiowrite(STM32_LCD_RST, 0); up_mdelay(1); - stm32wb_gpiowrite(STM32_LCD_RST, 1); + stm32_gpiowrite(STM32_LCD_RST, 1); return OK; } diff --git a/boards/arm/stm32wb/flipperzero/src/stm32_spi.c b/boards/arm/stm32wb/flipperzero/src/stm32_spi.c index cfb057dae1e..9e4e5fd13be 100644 --- a/boards/arm/stm32wb/flipperzero/src/stm32_spi.c +++ b/boards/arm/stm32wb/flipperzero/src/stm32_spi.c @@ -40,45 +40,45 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_spidev_initialize + * Name: stm32_spidev_initialize * * Description: * Called to configure SPI chip select GPIO pins. * ****************************************************************************/ -void weak_function stm32wb_spidev_initialize(void) +void weak_function stm32_spidev_initialize(void) { - /* NOTE: Clocking was already provided in stm32wb_rcc.c. + /* NOTE: Clocking was already provided in stm32_rcc.c. * Here, we only initialize chip select pins unique to the board * architecture. */ #ifdef CONFIG_LCD_ST7565 - stm32wb_configgpio(STM32_LCD_CS); /* ST7565 chip select */ + stm32_configgpio(STM32_LCD_CS); /* ST7565 chip select */ #endif } /**************************************************************************** - * Name: stm32wb_spi1/2select and stm32wb_spi1/2status + * Name: stm32_spi1/2select and stm32_spi1/2status * * Description: - * The external functions, stm32wb_spi1/2select and stm32wb_spi1/2status + * The external functions, stm32_spi1/2select and stm32_spi1/2status * must be provided by board-specific logic. They are implementations of * the select and status methods of the SPI interface defined by struct * spi_ops_s (see include/nuttx/spi/spi.h). All other methods (including - * stm32wb_spibus_initialize()) are provided by common STM32 logic. + * stm32_spibus_initialize()) are provided by common STM32 logic. * To use this common SPI logic on your board: * - * 1. Provide logic in stm32wb_boardinitialize() to configure SPI chip + * 1. Provide logic in stm32_boardinitialize() to configure SPI chip * select pins. - * 2. Provide stm32wb_spi1/2select() and stm32wb_spi1/2status() functions + * 2. Provide stm32_spi1/2select() and stm32_spi1/2status() functions * in your board-specific logic. These functions will perform chip * selection and status operations using GPIOs in the way your board is * configured. - * 3. Add a calls to stm32wb_spibus_initialize() in your low level + * 3. Add a calls to stm32_spibus_initialize() in your low level * application initialization logic - * 4. The handle returned by stm32wb_spibus_initialize() may then be used + * 4. The handle returned by stm32_spibus_initialize() may then be used * to bind the SPI driver to higher level logic (e.g., calling * mmcsd_spislotinitialize(), for example, will bind the SPI driver to * the SPI MMC/SD driver). @@ -86,17 +86,17 @@ void weak_function stm32wb_spidev_initialize(void) ****************************************************************************/ #ifdef CONFIG_STM32WB_SPI2 -void stm32wb_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected) +void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected) { #ifdef CONFIG_LCD_ST7565 if (devid == SPIDEV_DISPLAY(0)) { - stm32wb_gpiowrite(STM32_LCD_CS, !selected); + stm32_gpiowrite(STM32_LCD_CS, !selected); } #endif } -uint8_t stm32wb_spi2status(struct spi_dev_s *dev, uint32_t devid) +uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) { return 0; } diff --git a/boards/arm/stm32wb/nucleo-wb55rg/include/board.h b/boards/arm/stm32wb/nucleo-wb55rg/include/board.h index 328fba31d5f..22040bc8c1a 100644 --- a/boards/arm/stm32wb/nucleo-wb55rg/include/board.h +++ b/boards/arm/stm32wb/nucleo-wb55rg/include/board.h @@ -183,7 +183,7 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_board_initialize + * Name: stm32_board_initialize * * Description: * All STM32WB architectures must provide the following entry point. @@ -193,7 +193,7 @@ extern "C" * ****************************************************************************/ -void stm32wb_board_initialize(void); +void stm32_board_initialize(void); #undef EXTERN #if defined(__cplusplus) diff --git a/boards/arm/stm32wb/nucleo-wb55rg/src/stm32_autoleds.c b/boards/arm/stm32wb/nucleo-wb55rg/src/stm32_autoleds.c index 1b81d27c678..61ff88b7ea0 100644 --- a/boards/arm/stm32wb/nucleo-wb55rg/src/stm32_autoleds.c +++ b/boards/arm/stm32wb/nucleo-wb55rg/src/stm32_autoleds.c @@ -34,7 +34,7 @@ #include "chip.h" #include "arm_internal.h" -#include "stm32wb.h" +#include "stm32.h" #include "nucleo-wb55rg.h" #ifdef CONFIG_ARCH_LEDS @@ -51,9 +51,9 @@ void board_autoled_initialize(void) { /* Configure LEDs GPIO for output. Initial state is OFF */ - stm32wb_configgpio(GPIO_LED1); - stm32wb_configgpio(GPIO_LED2); - stm32wb_configgpio(GPIO_LED3); + stm32_configgpio(GPIO_LED1); + stm32_configgpio(GPIO_LED2); + stm32_configgpio(GPIO_LED3); } /**************************************************************************** @@ -68,15 +68,15 @@ void board_autoled_on(int led) break; case BOARD_LED1: - stm32wb_gpiowrite(GPIO_LED1, true); + stm32_gpiowrite(GPIO_LED1, true); break; case BOARD_LED2: - stm32wb_gpiowrite(GPIO_LED2, true); + stm32_gpiowrite(GPIO_LED2, true); break; case BOARD_LED3: - stm32wb_gpiowrite(GPIO_LED3, true); + stm32_gpiowrite(GPIO_LED3, true); break; } } @@ -93,15 +93,15 @@ void board_autoled_off(int led) break; case BOARD_LED1: - stm32wb_gpiowrite(GPIO_LED1, false); + stm32_gpiowrite(GPIO_LED1, false); break; case BOARD_LED2: - stm32wb_gpiowrite(GPIO_LED2, false); + stm32_gpiowrite(GPIO_LED2, false); break; case BOARD_LED3: - stm32wb_gpiowrite(GPIO_LED3, false); + stm32_gpiowrite(GPIO_LED3, false); break; } } diff --git a/boards/arm/stm32wb/nucleo-wb55rg/src/stm32_boot.c b/boards/arm/stm32wb/nucleo-wb55rg/src/stm32_boot.c index a8199219abe..140f2dbb255 100644 --- a/boards/arm/stm32wb/nucleo-wb55rg/src/stm32_boot.c +++ b/boards/arm/stm32wb/nucleo-wb55rg/src/stm32_boot.c @@ -58,7 +58,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_board_initialize + * Name: stm32_board_initialize * * Description: * All STM32WB architectures must provide the following entry point. This @@ -68,7 +68,7 @@ * ****************************************************************************/ -void stm32wb_board_initialize(void) +void stm32_board_initialize(void) { /* Configure on-board LEDs if LED support has been selected. */ @@ -131,7 +131,7 @@ void board_late_initialize(void) #ifdef CONFIG_RTC_DRIVER /* Instantiate the STM32WB lower-half RTC driver */ - rtclower = stm32wb_rtc_lowerhalf(); + rtclower = stm32_rtc_lowerhalf(); if (!rtclower) { serr("ERROR: Failed to instantiate the RTC lower-half driver\n"); @@ -155,7 +155,7 @@ void board_late_initialize(void) #ifdef CONFIG_TIMER /* Initialize and register the timer driver */ - ret = stm32wb_timer_initialize("/dev/timer0", 1); + ret = stm32_timer_initialize("/dev/timer0", 1); if (ret < 0) { syslog(LOG_ERR, "ERROR: Failed to register the timer driver: %d\n", @@ -167,7 +167,7 @@ void board_late_initialize(void) #ifdef CONFIG_STM32WB_BLE /* Initialize and register BLE HCI driver */ - stm32wb_blehci_initialize(); + stm32_blehci_initialize(); #endif UNUSED(ret); } @@ -188,7 +188,7 @@ int board_uniqueid(uint8_t *uniqueid) return -EINVAL; } - stm32wb_get_uniqueid(uniqueid); + stm32_get_uniqueid(uniqueid); return OK; } #endif diff --git a/boards/arm/stm32wb/nucleo-wb55rg/src/stm32_userleds.c b/boards/arm/stm32wb/nucleo-wb55rg/src/stm32_userleds.c index 054482588df..6c911a423c8 100644 --- a/boards/arm/stm32wb/nucleo-wb55rg/src/stm32_userleds.c +++ b/boards/arm/stm32wb/nucleo-wb55rg/src/stm32_userleds.c @@ -35,7 +35,7 @@ #include "chip.h" #include "arm_internal.h" -#include "stm32wb.h" +#include "stm32.h" #include "nucleo-wb55rg.h" #ifndef CONFIG_ARCH_LEDS @@ -94,8 +94,8 @@ static void led_pm_notify(struct pm_callback_s *cb, int domain, { /* Entering IDLE mode - Turn leds off */ - stm32wb_gpiowrite(GPIO_LED_RED, 0); - stm32wb_gpiowrite(GPIO_LED_GREEN, 0); + stm32_gpiowrite(GPIO_LED_RED, 0); + stm32_gpiowrite(GPIO_LED_GREEN, 0); } break; @@ -103,8 +103,8 @@ static void led_pm_notify(struct pm_callback_s *cb, int domain, { /* Entering STANDBY mode - Logic for PM_STANDBY goes here */ - stm32wb_gpiowrite(GPIO_LED_RED, 0); - stm32wb_gpiowrite(GPIO_LED_GREEN, 0); + stm32_gpiowrite(GPIO_LED_RED, 0); + stm32_gpiowrite(GPIO_LED_GREEN, 0); } break; @@ -112,8 +112,8 @@ static void led_pm_notify(struct pm_callback_s *cb, int domain, { /* Entering SLEEP mode - Logic for PM_SLEEP goes here */ - stm32wb_gpiowrite(GPIO_LED_RED, 0); - stm32wb_gpiowrite(GPIO_LED_GREEN, 0); + stm32_gpiowrite(GPIO_LED_RED, 0); + stm32_gpiowrite(GPIO_LED_GREEN, 0); } break; @@ -160,9 +160,9 @@ static int led_pm_prepare(struct pm_callback_s *cb, int domain, uint32_t board_userled_initialize(void) { - stm32wb_configgpio(GPIO_LED_RED); - stm32wb_configgpio(GPIO_LED_GREEN); - stm32wb_configgpio(GPIO_LED_BLUE); + stm32_configgpio(GPIO_LED_RED); + stm32_configgpio(GPIO_LED_GREEN); + stm32_configgpio(GPIO_LED_BLUE); return BOARD_NLEDS; } @@ -178,15 +178,15 @@ void board_userled(int led, bool ledon) break; case BOARD_LED_RED: - stm32wb_gpiowrite(GPIO_LED_RED, ledon); + stm32_gpiowrite(GPIO_LED_RED, ledon); break; case GPIO_LED_GREEN: - stm32wb_gpiowrite(GPIO_LED_GREEN, ledon); + stm32_gpiowrite(GPIO_LED_GREEN, ledon); break; case GPIO_LED_BLUE: - stm32wb_gpiowrite(GPIO_LED_BLUE, ledon); + stm32_gpiowrite(GPIO_LED_BLUE, ledon); break; } } @@ -197,9 +197,9 @@ void board_userled(int led, bool ledon) void board_userled_all(uint32_t ledset) { - stm32wb_gpiowrite(GPIO_LED1, (ledset & BOARD_LED1_BIT) != 0); - stm32wb_gpiowrite(GPIO_LED2, (ledset & BOARD_LED2_BIT) != 0); - stm32wb_gpiowrite(GPIO_LED3, (ledset & BOARD_LED3_BIT) != 0); + stm32_gpiowrite(GPIO_LED1, (ledset & BOARD_LED1_BIT) != 0); + stm32_gpiowrite(GPIO_LED2, (ledset & BOARD_LED2_BIT) != 0); + stm32_gpiowrite(GPIO_LED3, (ledset & BOARD_LED3_BIT) != 0); } /****************************************************************************