Aksal/nuttx
3
1
Fork 1
mirror of https://github.com/apache/nuttx.git synced 2026-10-13 01:00:12 +00:00
Code Issues Projects Releases Packages Wiki Activity Actions 2

arch/arm/stm32h5: Use common Cortex-M33 USART support

Browse source 
Select STM32_HAVE_IP_USART_M33_V3 and drop the family serial, USART
header, and low-level console sources. Provide the USART clock and RCC
gate definitions for all thirteen ports in stm32_rcc_m33.h and the RX
DMA request numbers in the family DMA signal map. Include the family
DMA header from stm32.h so the common driver reaches the DMA API.

Extend the common Cortex-M33 v3 USART support with the STM32H5
features: USART6, UART7-9, USART10-11, and UART12 ports, the LPUART
prescaler for low baud rates, RX DMA through the family-provided
request number, wakeup-from-stop CR3 definitions, and per-port
descriptors gated by the family peripheral options.

Enable the USART FIFO for every Cortex-M33 family. The low-level
console uses the per-port kernel clock and RCC gate, which corrects
the UART9 and UART12 enable register. The RX DMA callback delivers
data only while reception is enabled.

The non-BSD break ioctl now uses the send-break request register
instead of a CR1 bit this USART IP does not have. Correct the UART12
gates and the RXDMA and console undef lists in the USART driver
header. Raise STM32_NUSART to six on the H56x and H57x parts so UART12
fits the device table, add the missing UART9 buffers, write LPUART CR1
only on the USART path, and build device names with snprintf so minors
above nine are valid.

Keep the termios flow control fields writable so TCSETS compiles with
input flow control, let up_putc emit a bare newline since syslog adds
the carriage return, and make the unconfigure-on-close options
available to every Cortex-M33 family.

Signed-off-by: raiden00pl <raiden00@railab.me>
Assisted-by: Claude Code
This commit is contained in:
raiden00pl 2026-08-26 10:58:29 +02:00 • committed by Alan C. Assis
parent ba50b9d27d
commit f093edb26c
18 changed files with 1824 additions and 6491 deletions
Download patch file Download diff file Expand all files Collapse all files

2
arch/arm/include/stm32h5/chip.h
View file

@ -79,7 +79,7 @@
#if defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32_STM32H57XXX)
# define STM32_NUART (6) /* UART 4-5, 7-8, 9, 12 */
# define STM32_NUSART (5) /* USART 1-3, 6, 10-11 */
# define STM32_NUSART (6) /* USART 1-3, 6, 10-11 */
#elif defined(CONFIG_STM32_STM32H52XXX) || defined(CONFIG_STM32_STM32H53XXX)
# define STM32_NUART (2) /* UART 4-5 */
# define STM32_NUSART (4) /* USART 1-3, 6*/

2
arch/arm/src/common/stm32/Kconfig.have
View file

@ -1077,7 +1077,7 @@ config STM32_HAVE_USART_WUS
config STM32_HAVE_USART_UNCONFIG_ON_CLOSE
bool
default y if ARCH_CHIP_STM32H5
default y if STM32_HAVE_IP_USART_M33_V3
default y if ARCH_CHIP_STM32N6
config STM32_HAVE_USART2

31
arch/arm/src/common/stm32/hardware/stm32_uart_m33_v3.h
View file

@ -184,10 +184,25 @@
#define USART_CR1_TXFEIE (1 << 30)
#define USART_CR1_RXFFIE (1 << 31)
#define USART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE
#define USART_CR1_ALLINTS (USART_CR1_IDLEIE | USART_CR1_RXNEIE | USART_CR1_TCIE | \
USART_CR1_TXEIE | USART_CR1_PEIE | USART_CR1_CMIE | \
USART_CR1_RTOIE | USART_CR1_EOBIE | USART_CR1_TXFEIE | \
USART_CR1_RXFFIE)
#define USART_CR1_ALLINTS (USART_CR1_IDLEIE | \
USART_CR1_RXNEIE | \
USART_CR1_TCIE | \
USART_CR1_TXEIE | \
USART_CR1_PEIE | \
USART_CR1_CMIE | \
USART_CR1_RTOIE | \
USART_CR1_EOBIE | \
USART_CR1_TXFEIE | \
USART_CR1_RXFFIE)
#define LPUART_CR1_ALLINTS (USART_CR1_IDLEIE | \
USART_CR1_RXNEIE | \
USART_CR1_TCIE | \
USART_CR1_TXEIE | \
USART_CR1_PEIE | \
USART_CR1_CMIE | \
USART_CR1_TXFEIE | \
USART_CR1_RXFFIE)
/* USART control register 2 */
@ -265,6 +280,12 @@
#define USART_CR3_TXFTCFG(n) ((n) << USART_CR3_TXFTCFG_SHIFT)
#define USART_CR3_SCARCNT2_SHIFT USART_CR3_SCARCNT_SHIFT
#define USART_CR3_SCARCNT2_MASK USART_CR3_SCARCNT_MASK
#define USART_CR3_WUS_SHIFT (20)
#define USART_CR3_WUS_MASK (3 << USART_CR3_WUS_SHIFT)
#define USART_CR3_WUS_ADDRESS (0 << USART_CR3_WUS_SHIFT)
#define USART_CR3_WUS_START (2 << USART_CR3_WUS_SHIFT)
#define USART_CR3_WUS_RXNE (3 << USART_CR3_WUS_SHIFT)
#define USART_CR3_WUFIE (1 << 22)
#define USART_CR3_RXFTCFG_1_8 USART_CR3_RXFTCFG(0)
#define USART_CR3_RXFTCFG_1_4 USART_CR3_RXFTCFG(1)
#define USART_CR3_RXFTCFG_1_2 USART_CR3_RXFTCFG(2)
@ -339,6 +360,7 @@
#define USART_ISR_CMF (1 << 17)
#define USART_ISR_SBKF (1 << 18)
#define USART_ISR_RWU (1 << 19)
#define USART_ISR_WUF (1 << 20)
#define USART_ISR_TEACK (1 << 21)
#define USART_ISR_REACK (1 << 22)
#define USART_ISR_TXFE (1 << 23)
@ -367,6 +389,7 @@
#define USART_ICR_EOBCF (1 << 12)
#define USART_ICR_UDRCF (1 << 13)
#define USART_ICR_CMCF (1 << 17)
#define USART_ICR_WUCF (1 << 20)
#define USART_ICR_NCF USART_ICR_NECF
/* USART receive-data register */

140
arch/arm/src/common/stm32/stm32_lowputc_usart_m33_v3.c
View file

@ -165,6 +165,146 @@
# define STM32_CONSOLE_RS485_DIR_POLARITY true
# endif
# endif
# elif defined(CONFIG_USART6_SERIAL_CONSOLE)
# define STM32_CONSOLE_IS_LPUART 0
# define STM32_CONSOLE_BASE STM32_USART6_BASE
# define STM32_APBCLOCK STM32_USART6_FREQUENCY
# define STM32_CONSOLE_APBREG STM32_USART6_RCC_REG
# define STM32_CONSOLE_APBEN STM32_USART6_RCC_EN
# define STM32_CONSOLE_BAUD CONFIG_USART6_BAUD
# define STM32_CONSOLE_BITS CONFIG_USART6_BITS
# define STM32_CONSOLE_PARITY CONFIG_USART6_PARITY
# define STM32_CONSOLE_2STOP CONFIG_USART6_2STOP
# define STM32_CONSOLE_TX GPIO_USART6_TX
# define STM32_CONSOLE_RX GPIO_USART6_RX
# ifdef CONFIG_USART6_RS485
# define STM32_CONSOLE_RS485_DIR GPIO_USART6_RS485_DIR
# if (CONFIG_USART6_RS485_DIR_POLARITY == 0)
# define STM32_CONSOLE_RS485_DIR_POLARITY false
# else
# define STM32_CONSOLE_RS485_DIR_POLARITY true
# endif
# endif
# elif defined(CONFIG_UART7_SERIAL_CONSOLE)
# define STM32_CONSOLE_IS_LPUART 0
# define STM32_CONSOLE_BASE STM32_UART7_BASE
# define STM32_APBCLOCK STM32_UART7_FREQUENCY
# define STM32_CONSOLE_APBREG STM32_UART7_RCC_REG
# define STM32_CONSOLE_APBEN STM32_UART7_RCC_EN
# define STM32_CONSOLE_BAUD CONFIG_UART7_BAUD
# define STM32_CONSOLE_BITS CONFIG_UART7_BITS
# define STM32_CONSOLE_PARITY CONFIG_UART7_PARITY
# define STM32_CONSOLE_2STOP CONFIG_UART7_2STOP
# define STM32_CONSOLE_TX GPIO_UART7_TX
# define STM32_CONSOLE_RX GPIO_UART7_RX
# ifdef CONFIG_UART7_RS485
# define STM32_CONSOLE_RS485_DIR GPIO_UART7_RS485_DIR
# if (CONFIG_UART7_RS485_DIR_POLARITY == 0)
# define STM32_CONSOLE_RS485_DIR_POLARITY false
# else
# define STM32_CONSOLE_RS485_DIR_POLARITY true
# endif
# endif
# elif defined(CONFIG_UART8_SERIAL_CONSOLE)
# define STM32_CONSOLE_IS_LPUART 0
# define STM32_CONSOLE_BASE STM32_UART8_BASE
# define STM32_APBCLOCK STM32_UART8_FREQUENCY
# define STM32_CONSOLE_APBREG STM32_UART8_RCC_REG
# define STM32_CONSOLE_APBEN STM32_UART8_RCC_EN
# define STM32_CONSOLE_BAUD CONFIG_UART8_BAUD
# define STM32_CONSOLE_BITS CONFIG_UART8_BITS
# define STM32_CONSOLE_PARITY CONFIG_UART8_PARITY
# define STM32_CONSOLE_2STOP CONFIG_UART8_2STOP
# define STM32_CONSOLE_TX GPIO_UART8_TX
# define STM32_CONSOLE_RX GPIO_UART8_RX
# ifdef CONFIG_UART8_RS485
# define STM32_CONSOLE_RS485_DIR GPIO_UART8_RS485_DIR
# if (CONFIG_UART8_RS485_DIR_POLARITY == 0)
# define STM32_CONSOLE_RS485_DIR_POLARITY false
# else
# define STM32_CONSOLE_RS485_DIR_POLARITY true
# endif
# endif
# elif defined(CONFIG_UART9_SERIAL_CONSOLE)
# define STM32_CONSOLE_IS_LPUART 0
# define STM32_CONSOLE_BASE STM32_UART9_BASE
# define STM32_APBCLOCK STM32_UART9_FREQUENCY
# define STM32_CONSOLE_APBREG STM32_UART9_RCC_REG
# define STM32_CONSOLE_APBEN STM32_UART9_RCC_EN
# define STM32_CONSOLE_BAUD CONFIG_UART9_BAUD
# define STM32_CONSOLE_BITS CONFIG_UART9_BITS
# define STM32_CONSOLE_PARITY CONFIG_UART9_PARITY
# define STM32_CONSOLE_2STOP CONFIG_UART9_2STOP
# define STM32_CONSOLE_TX GPIO_UART9_TX
# define STM32_CONSOLE_RX GPIO_UART9_RX
# ifdef CONFIG_UART9_RS485
# define STM32_CONSOLE_RS485_DIR GPIO_UART9_RS485_DIR
# if (CONFIG_UART9_RS485_DIR_POLARITY == 0)
# define STM32_CONSOLE_RS485_DIR_POLARITY false
# else
# define STM32_CONSOLE_RS485_DIR_POLARITY true
# endif
# endif
# elif defined(CONFIG_USART10_SERIAL_CONSOLE)
# define STM32_CONSOLE_IS_LPUART 0
# define STM32_CONSOLE_BASE STM32_USART10_BASE
# define STM32_APBCLOCK STM32_USART10_FREQUENCY
# define STM32_CONSOLE_APBREG STM32_USART10_RCC_REG
# define STM32_CONSOLE_APBEN STM32_USART10_RCC_EN
# define STM32_CONSOLE_BAUD CONFIG_USART10_BAUD
# define STM32_CONSOLE_BITS CONFIG_USART10_BITS
# define STM32_CONSOLE_PARITY CONFIG_USART10_PARITY
# define STM32_CONSOLE_2STOP CONFIG_USART10_2STOP
# define STM32_CONSOLE_TX GPIO_USART10_TX
# define STM32_CONSOLE_RX GPIO_USART10_RX
# ifdef CONFIG_USART10_RS485
# define STM32_CONSOLE_RS485_DIR GPIO_USART10_RS485_DIR
# if (CONFIG_USART10_RS485_DIR_POLARITY == 0)
# define STM32_CONSOLE_RS485_DIR_POLARITY false
# else
# define STM32_CONSOLE_RS485_DIR_POLARITY true
# endif
# endif
# elif defined(CONFIG_USART11_SERIAL_CONSOLE)
# define STM32_CONSOLE_IS_LPUART 0
# define STM32_CONSOLE_BASE STM32_USART11_BASE
# define STM32_APBCLOCK STM32_USART11_FREQUENCY
# define STM32_CONSOLE_APBREG STM32_USART11_RCC_REG
# define STM32_CONSOLE_APBEN STM32_USART11_RCC_EN
# define STM32_CONSOLE_BAUD CONFIG_USART11_BAUD
# define STM32_CONSOLE_BITS CONFIG_USART11_BITS
# define STM32_CONSOLE_PARITY CONFIG_USART11_PARITY
# define STM32_CONSOLE_2STOP CONFIG_USART11_2STOP
# define STM32_CONSOLE_TX GPIO_USART11_TX
# define STM32_CONSOLE_RX GPIO_USART11_RX
# ifdef CONFIG_USART11_RS485
# define STM32_CONSOLE_RS485_DIR GPIO_USART11_RS485_DIR
# if (CONFIG_USART11_RS485_DIR_POLARITY == 0)
# define STM32_CONSOLE_RS485_DIR_POLARITY false
# else
# define STM32_CONSOLE_RS485_DIR_POLARITY true
# endif
# endif
# elif defined(CONFIG_UART12_SERIAL_CONSOLE)
# define STM32_CONSOLE_IS_LPUART 0
# define STM32_CONSOLE_BASE STM32_UART12_BASE
# define STM32_APBCLOCK STM32_UART12_FREQUENCY
# define STM32_CONSOLE_APBREG STM32_UART12_RCC_REG
# define STM32_CONSOLE_APBEN STM32_UART12_RCC_EN
# define STM32_CONSOLE_BAUD CONFIG_UART12_BAUD
# define STM32_CONSOLE_BITS CONFIG_UART12_BITS
# define STM32_CONSOLE_PARITY CONFIG_UART12_PARITY
# define STM32_CONSOLE_2STOP CONFIG_UART12_2STOP
# define STM32_CONSOLE_TX GPIO_UART12_TX
# define STM32_CONSOLE_RX GPIO_UART12_RX
# ifdef CONFIG_UART12_RS485
# define STM32_CONSOLE_RS485_DIR GPIO_UART12_RS485_DIR
# if (CONFIG_UART12_RS485_DIR_POLARITY == 0)
# define STM32_CONSOLE_RS485_DIR_POLARITY false
# else
# define STM32_CONSOLE_RS485_DIR_POLARITY true
# endif
# endif
# endif
/* CR1 settings */

1391
arch/arm/src/common/stm32/stm32_serial_m33_v3.c
View file

File diff suppressed because it is too large Load diff

289
arch/arm/src/common/stm32/stm32_uart_m33_v3.h
View file

@ -42,6 +42,27 @@
* device.
*/
#if !defined(CONFIG_STM32_HAVE_UART12)
# undef CONFIG_STM32_UART12
#endif
#if !defined(CONFIG_STM32_HAVE_USART11)
# undef CONFIG_STM32_USART11
#endif
#if !defined(CONFIG_STM32_HAVE_USART10)
# undef CONFIG_STM32_USART10
#endif
#if !defined(CONFIG_STM32_HAVE_UART9)
# undef CONFIG_STM32_UART9
#endif
#if !defined(CONFIG_STM32_HAVE_UART8)
# undef CONFIG_STM32_UART8
#endif
#if !defined(CONFIG_STM32_HAVE_UART7)
# undef CONFIG_STM32_UART7
#endif
#if !defined(CONFIG_STM32_HAVE_USART6)
# undef CONFIG_STM32_USART6
#endif
#if !defined(CONFIG_STM32_HAVE_UART5)
# undef CONFIG_STM32_UART5
#endif
@ -87,12 +108,44 @@
# undef CONFIG_STM32_UART5_SERIALDRIVER
# undef CONFIG_STM32_UART5_1WIREDRIVER
#endif
#if !defined(CONFIG_STM32_USART6)
# undef CONFIG_STM32_USART6_SERIALDRIVER
# undef CONFIG_STM32_USART6_1WIREDRIVER
#endif
#if !defined(CONFIG_STM32_UART7)
# undef CONFIG_STM32_UART7_SERIALDRIVER
# undef CONFIG_STM32_UART7_1WIREDRIVER
#endif
#if !defined(CONFIG_STM32_UART8)
# undef CONFIG_STM32_UART8_SERIALDRIVER
# undef CONFIG_STM32_UART8_1WIREDRIVER
#endif
#if !defined(CONFIG_STM32_UART9)
# undef CONFIG_STM32_UART9_SERIALDRIVER
# undef CONFIG_STM32_UART9_1WIREDRIVER
#endif
#if !defined(CONFIG_STM32_USART10)
# undef CONFIG_STM32_USART10_SERIALDRIVER
# undef CONFIG_STM32_USART10_1WIREDRIVER
#endif
#if !defined(CONFIG_STM32_USART11)
# undef CONFIG_STM32_USART11_SERIALDRIVER
# undef CONFIG_STM32_USART11_1WIREDRIVER
#endif
#if !defined(CONFIG_STM32_UART12)
# undef CONFIG_STM32_UART12_SERIALDRIVER
# undef CONFIG_STM32_UART12_1WIREDRIVER
#endif
/* Is there a USART enabled? */
#if defined(CONFIG_STM32_LPUART1) || defined(CONFIG_STM32_USART1) || \
defined(CONFIG_STM32_USART2) || defined(CONFIG_STM32_USART3) || \
defined(CONFIG_STM32_UART4) || defined(CONFIG_STM32_UART5)
defined(CONFIG_STM32_UART4) || defined(CONFIG_STM32_UART5) || \
defined(CONFIG_STM32_USART6) || defined(CONFIG_STM32_UART7) || \
defined(CONFIG_STM32_UART8) || defined(CONFIG_STM32_UART9) || \
defined(CONFIG_STM32_USART10) || defined(CONFIG_STM32_USART11) || \
defined(CONFIG_STM32_UART12)
# define HAVE_UART 1
#endif
@ -104,6 +157,13 @@
# undef CONFIG_USART3_SERIAL_CONSOLE
# undef CONFIG_UART4_SERIAL_CONSOLE
# undef CONFIG_UART5_SERIAL_CONSOLE
# undef CONFIG_USART6_SERIAL_CONSOLE
# undef CONFIG_UART7_SERIAL_CONSOLE
# undef CONFIG_UART8_SERIAL_CONSOLE
# undef CONFIG_UART9_SERIAL_CONSOLE
# undef CONFIG_USART10_SERIAL_CONSOLE
# undef CONFIG_USART11_SERIAL_CONSOLE
# undef CONFIG_UART12_SERIAL_CONSOLE
# define CONSOLE_UART 1
# define HAVE_CONSOLE 1
#elif defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART1_SERIALDRIVER)
@ -112,42 +172,193 @@
# undef CONFIG_USART3_SERIAL_CONSOLE
# undef CONFIG_UART4_SERIAL_CONSOLE
# undef CONFIG_UART5_SERIAL_CONSOLE
# undef CONFIG_USART6_SERIAL_CONSOLE
# undef CONFIG_UART7_SERIAL_CONSOLE
# undef CONFIG_UART8_SERIAL_CONSOLE
# undef CONFIG_UART9_SERIAL_CONSOLE
# undef CONFIG_USART10_SERIAL_CONSOLE
# undef CONFIG_USART11_SERIAL_CONSOLE
# undef CONFIG_UART12_SERIAL_CONSOLE
# define CONSOLE_UART 2
# define HAVE_CONSOLE 1
#elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART2_SERIALDRIVER)
# undef CONFIG_LPUART1_SERIAL_CONSOLE
# undef CONFIG_USART1_SERIAL_CONSOLE
# undef CONFIG_USART3_SERIAL_CONSOLE
# undef CONFIG_UART4_SERIAL_CONSOLE
# undef CONFIG_UART5_SERIAL_CONSOLE
# undef CONFIG_USART6_SERIAL_CONSOLE
# undef CONFIG_UART7_SERIAL_CONSOLE
# undef CONFIG_UART8_SERIAL_CONSOLE
# undef CONFIG_UART9_SERIAL_CONSOLE
# undef CONFIG_USART10_SERIAL_CONSOLE
# undef CONFIG_USART11_SERIAL_CONSOLE
# undef CONFIG_UART12_SERIAL_CONSOLE
# define CONSOLE_UART 3
# define HAVE_CONSOLE 1
#elif defined(CONFIG_USART3_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART3_SERIALDRIVER)
# undef CONFIG_LPUART1_SERIAL_CONSOLE
# undef CONFIG_USART1_SERIAL_CONSOLE
# undef CONFIG_USART2_SERIAL_CONSOLE
# undef CONFIG_UART4_SERIAL_CONSOLE
# undef CONFIG_UART5_SERIAL_CONSOLE
# undef CONFIG_USART6_SERIAL_CONSOLE
# undef CONFIG_UART7_SERIAL_CONSOLE
# undef CONFIG_UART8_SERIAL_CONSOLE
# undef CONFIG_UART9_SERIAL_CONSOLE
# undef CONFIG_USART10_SERIAL_CONSOLE
# undef CONFIG_USART11_SERIAL_CONSOLE
# undef CONFIG_UART12_SERIAL_CONSOLE
# define CONSOLE_UART 4
# define HAVE_CONSOLE 1
#elif defined(CONFIG_UART4_SERIAL_CONSOLE) && defined(CONFIG_STM32_UART4_SERIALDRIVER)
# undef CONFIG_LPUART1_SERIAL_CONSOLE
# undef CONFIG_USART1_SERIAL_CONSOLE
# undef CONFIG_USART2_SERIAL_CONSOLE
# undef CONFIG_USART3_SERIAL_CONSOLE
# undef CONFIG_UART5_SERIAL_CONSOLE
# undef CONFIG_USART6_SERIAL_CONSOLE
# undef CONFIG_UART7_SERIAL_CONSOLE
# undef CONFIG_UART8_SERIAL_CONSOLE
# undef CONFIG_UART9_SERIAL_CONSOLE
# undef CONFIG_USART10_SERIAL_CONSOLE
# undef CONFIG_USART11_SERIAL_CONSOLE
# undef CONFIG_UART12_SERIAL_CONSOLE
# define CONSOLE_UART 5
# define HAVE_CONSOLE 1
#elif defined(CONFIG_UART5_SERIAL_CONSOLE) && defined(CONFIG_STM32_UART5_SERIALDRIVER)
# undef CONFIG_LPUART1_SERIAL_CONSOLE
# undef CONFIG_USART1_SERIAL_CONSOLE
# undef CONFIG_USART2_SERIAL_CONSOLE
# undef CONFIG_USART3_SERIAL_CONSOLE
# undef CONFIG_UART4_SERIAL_CONSOLE
# undef CONFIG_USART6_SERIAL_CONSOLE
# undef CONFIG_UART7_SERIAL_CONSOLE
# undef CONFIG_UART8_SERIAL_CONSOLE
# undef CONFIG_UART9_SERIAL_CONSOLE
# undef CONFIG_USART10_SERIAL_CONSOLE
# undef CONFIG_USART11_SERIAL_CONSOLE
# undef CONFIG_UART12_SERIAL_CONSOLE
# define CONSOLE_UART 6
# define HAVE_CONSOLE 1
#elif defined(CONFIG_USART6_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART6_SERIALDRIVER)
# undef CONFIG_LPUART1_SERIAL_CONSOLE
# undef CONFIG_USART1_SERIAL_CONSOLE
# undef CONFIG_USART2_SERIAL_CONSOLE
# undef CONFIG_USART3_SERIAL_CONSOLE
# undef CONFIG_UART4_SERIAL_CONSOLE
# undef CONFIG_UART5_SERIAL_CONSOLE
# undef CONFIG_UART7_SERIAL_CONSOLE
# undef CONFIG_UART8_SERIAL_CONSOLE
# undef CONFIG_UART9_SERIAL_CONSOLE
# undef CONFIG_USART10_SERIAL_CONSOLE
# undef CONFIG_USART11_SERIAL_CONSOLE
# undef CONFIG_UART12_SERIAL_CONSOLE
# define CONSOLE_UART 7
# define HAVE_CONSOLE 1
#elif defined(CONFIG_UART7_SERIAL_CONSOLE) && defined(CONFIG_STM32_UART7_SERIALDRIVER)
# undef CONFIG_LPUART1_SERIAL_CONSOLE
# undef CONFIG_USART1_SERIAL_CONSOLE
# undef CONFIG_USART2_SERIAL_CONSOLE
# undef CONFIG_USART3_SERIAL_CONSOLE
# undef CONFIG_UART4_SERIAL_CONSOLE
# undef CONFIG_UART5_SERIAL_CONSOLE
# undef CONFIG_USART6_SERIAL_CONSOLE
# undef CONFIG_UART8_SERIAL_CONSOLE
# undef CONFIG_UART9_SERIAL_CONSOLE
# undef CONFIG_USART10_SERIAL_CONSOLE
# undef CONFIG_USART11_SERIAL_CONSOLE
# undef CONFIG_UART12_SERIAL_CONSOLE
# define CONSOLE_UART 8
# define HAVE_CONSOLE 1
#elif defined(CONFIG_UART8_SERIAL_CONSOLE) && defined(CONFIG_STM32_UART8_SERIALDRIVER)
# undef CONFIG_LPUART1_SERIAL_CONSOLE
# undef CONFIG_USART1_SERIAL_CONSOLE
# undef CONFIG_USART2_SERIAL_CONSOLE
# undef CONFIG_USART3_SERIAL_CONSOLE
# undef CONFIG_UART4_SERIAL_CONSOLE
# undef CONFIG_UART5_SERIAL_CONSOLE
# undef CONFIG_USART6_SERIAL_CONSOLE
# undef CONFIG_UART7_SERIAL_CONSOLE
# undef CONFIG_UART9_SERIAL_CONSOLE
# undef CONFIG_USART10_SERIAL_CONSOLE
# undef CONFIG_USART11_SERIAL_CONSOLE
# undef CONFIG_UART12_SERIAL_CONSOLE
# define CONSOLE_UART 9
# define HAVE_CONSOLE 1
#elif defined(CONFIG_UART9_SERIAL_CONSOLE) && defined(CONFIG_STM32_UART9_SERIALDRIVER)
# undef CONFIG_LPUART1_SERIAL_CONSOLE
# undef CONFIG_USART1_SERIAL_CONSOLE
# undef CONFIG_USART2_SERIAL_CONSOLE
# undef CONFIG_USART3_SERIAL_CONSOLE
# undef CONFIG_UART4_SERIAL_CONSOLE
# undef CONFIG_UART5_SERIAL_CONSOLE
# undef CONFIG_USART6_SERIAL_CONSOLE
# undef CONFIG_UART7_SERIAL_CONSOLE
# undef CONFIG_UART8_SERIAL_CONSOLE
# undef CONFIG_USART10_SERIAL_CONSOLE
# undef CONFIG_USART11_SERIAL_CONSOLE
# undef CONFIG_UART12_SERIAL_CONSOLE
# define CONSOLE_UART 10
# define HAVE_CONSOLE 1
#elif defined(CONFIG_USART10_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART10_SERIALDRIVER)
# undef CONFIG_LPUART1_SERIAL_CONSOLE
# undef CONFIG_USART1_SERIAL_CONSOLE
# undef CONFIG_USART2_SERIAL_CONSOLE
# undef CONFIG_USART3_SERIAL_CONSOLE
# undef CONFIG_UART4_SERIAL_CONSOLE
# undef CONFIG_UART5_SERIAL_CONSOLE
# undef CONFIG_USART6_SERIAL_CONSOLE
# undef CONFIG_UART7_SERIAL_CONSOLE
# undef CONFIG_UART8_SERIAL_CONSOLE
# undef CONFIG_UART9_SERIAL_CONSOLE
# undef CONFIG_USART11_SERIAL_CONSOLE
# undef CONFIG_UART12_SERIAL_CONSOLE
# define CONSOLE_UART 11
# define HAVE_CONSOLE 1
#elif defined(CONFIG_USART11_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART11_SERIALDRIVER)
# undef CONFIG_LPUART1_SERIAL_CONSOLE
# undef CONFIG_USART1_SERIAL_CONSOLE
# undef CONFIG_USART2_SERIAL_CONSOLE
# undef CONFIG_USART3_SERIAL_CONSOLE
# undef CONFIG_UART4_SERIAL_CONSOLE
# undef CONFIG_UART5_SERIAL_CONSOLE
# undef CONFIG_USART6_SERIAL_CONSOLE
# undef CONFIG_UART7_SERIAL_CONSOLE
# undef CONFIG_UART8_SERIAL_CONSOLE
# undef CONFIG_UART9_SERIAL_CONSOLE
# undef CONFIG_USART10_SERIAL_CONSOLE
# undef CONFIG_UART12_SERIAL_CONSOLE
# define CONSOLE_UART 12
# define HAVE_CONSOLE 1
#elif defined(CONFIG_UART12_SERIAL_CONSOLE) && defined(CONFIG_STM32_UART12_SERIALDRIVER)
# undef CONFIG_LPUART1_SERIAL_CONSOLE
# undef CONFIG_USART1_SERIAL_CONSOLE
# undef CONFIG_USART2_SERIAL_CONSOLE
# undef CONFIG_USART3_SERIAL_CONSOLE
# undef CONFIG_UART4_SERIAL_CONSOLE
# undef CONFIG_UART5_SERIAL_CONSOLE
# undef CONFIG_USART6_SERIAL_CONSOLE
# undef CONFIG_UART7_SERIAL_CONSOLE
# undef CONFIG_UART8_SERIAL_CONSOLE
# undef CONFIG_UART9_SERIAL_CONSOLE
# undef CONFIG_USART10_SERIAL_CONSOLE
# undef CONFIG_USART11_SERIAL_CONSOLE
# define CONSOLE_UART 13
# define HAVE_CONSOLE 1
#else
# undef CONFIG_USART1_SERIAL_CONSOLE
# undef CONFIG_USART2_SERIAL_CONSOLE
# undef CONFIG_USART3_SERIAL_CONSOLE
# undef CONFIG_UART4_SERIAL_CONSOLE
# undef CONFIG_UART5_SERIAL_CONSOLE
# undef CONFIG_USART6_SERIAL_CONSOLE
# undef CONFIG_UART7_SERIAL_CONSOLE
# undef CONFIG_UART8_SERIAL_CONSOLE
# undef CONFIG_UART9_SERIAL_CONSOLE
# undef CONFIG_USART10_SERIAL_CONSOLE
# undef CONFIG_USART11_SERIAL_CONSOLE
# undef CONFIG_UART12_SERIAL_CONSOLE
# define CONSOLE_UART 0
# undef HAVE_CONSOLE
#endif
@ -157,11 +368,19 @@
*/
#if !defined(HAVE_UART) || !defined(CONFIG_ARCH_DMA)
# undef CONFIG_LPUART1_RXDMA
# undef CONFIG_USART1_RXDMA
# undef CONFIG_USART2_RXDMA
# undef CONFIG_USART3_RXDMA
# undef CONFIG_UART4_RXDMA
# undef CONFIG_UART5_RXDMA
# undef CONFIG_USART6_RXDMA
# undef CONFIG_UART7_RXDMA
# undef CONFIG_UART8_RXDMA
# undef CONFIG_UART9_RXDMA
# undef CONFIG_USART10_RXDMA
# undef CONFIG_USART11_RXDMA
# undef CONFIG_UART12_RXDMA
#endif
/* Disable the DMA configuration on all unused USARTs */
@ -190,12 +409,44 @@
# undef CONFIG_UART5_RXDMA
#endif
#ifndef CONFIG_STM32_USART6_SERIALDRIVER
# undef CONFIG_USART6_RXDMA
#endif
#ifndef CONFIG_STM32_UART7_SERIALDRIVER
# undef CONFIG_UART7_RXDMA
#endif
#ifndef CONFIG_STM32_UART8_SERIALDRIVER
# undef CONFIG_UART8_RXDMA
#endif
#ifndef CONFIG_STM32_UART9_SERIALDRIVER
# undef CONFIG_UART9_RXDMA
#endif
#ifndef CONFIG_STM32_USART10_SERIALDRIVER
# undef CONFIG_USART10_RXDMA
#endif
#ifndef CONFIG_STM32_USART11_SERIALDRIVER
# undef CONFIG_USART11_RXDMA
#endif
#ifndef CONFIG_STM32_UART12_SERIALDRIVER
# undef CONFIG_UART12_RXDMA
#endif
/* Is DMA available on any (enabled) USART? */
#undef SERIAL_HAVE_DMA
#if defined(CONFIG_LPUART1_RXDMA) || defined(CONFIG_USART1_RXDMA) || \
defined(CONFIG_USART2_RXDMA) || defined(CONFIG_USART3_RXDMA) || \
defined(CONFIG_UART4_RXDMA) || defined(CONFIG_UART5_RXDMA)
defined(CONFIG_UART4_RXDMA) || defined(CONFIG_UART5_RXDMA) || \
defined(CONFIG_USART6_RXDMA) || defined(CONFIG_UART7_RXDMA) || \
defined(CONFIG_UART8_RXDMA) || defined(CONFIG_UART9_RXDMA) || \
defined(CONFIG_USART10_RXDMA) || defined(CONFIG_USART11_RXDMA) || \
defined(CONFIG_UART12_RXDMA)
# define SERIAL_HAVE_DMA 1
#endif
@ -214,6 +465,20 @@
# define SERIAL_HAVE_CONSOLE_DMA 1
#elif defined(CONFIG_UART5_SERIAL_CONSOLE) && defined(CONFIG_UART5_RXDMA)
# define SERIAL_HAVE_CONSOLE_DMA 1
#elif defined(CONFIG_USART6_SERIAL_CONSOLE) && defined(CONFIG_USART6_RXDMA)
# define SERIAL_HAVE_CONSOLE_DMA 1
#elif defined(CONFIG_UART7_SERIAL_CONSOLE) && defined(CONFIG_UART7_RXDMA)
# define SERIAL_HAVE_CONSOLE_DMA 1
#elif defined(CONFIG_UART8_SERIAL_CONSOLE) && defined(CONFIG_UART8_RXDMA)
# define SERIAL_HAVE_CONSOLE_DMA 1
#elif defined(CONFIG_UART9_SERIAL_CONSOLE) && defined(CONFIG_UART9_RXDMA)
# define SERIAL_HAVE_CONSOLE_DMA 1
#elif defined(CONFIG_USART10_SERIAL_CONSOLE) && defined(CONFIG_USART10_RXDMA)
# define SERIAL_HAVE_CONSOLE_DMA 1
#elif defined(CONFIG_USART11_SERIAL_CONSOLE) && defined(CONFIG_USART11_RXDMA)
# define SERIAL_HAVE_CONSOLE_DMA 1
#elif defined(CONFIG_UART12_SERIAL_CONSOLE) && defined(CONFIG_UART12_RXDMA)
# define SERIAL_HAVE_CONSOLE_DMA 1
#endif
/* Is DMA used on all (enabled) USARTs */
@ -231,13 +496,31 @@
# undef SERIAL_HAVE_ONLY_DMA
#elif defined(CONFIG_STM32_UART5_SERIALDRIVER) && !defined(CONFIG_UART5_RXDMA)
# undef SERIAL_HAVE_ONLY_DMA
#elif defined(CONFIG_STM32_USART6_SERIALDRIVER) && !defined(CONFIG_USART6_RXDMA)
# undef SERIAL_HAVE_ONLY_DMA
#elif defined(CONFIG_STM32_UART7_SERIALDRIVER) && !defined(CONFIG_UART7_RXDMA)
# undef SERIAL_HAVE_ONLY_DMA
#elif defined(CONFIG_STM32_UART8_SERIALDRIVER) && !defined(CONFIG_UART8_RXDMA)
# undef SERIAL_HAVE_ONLY_DMA
#elif defined(CONFIG_STM32_UART9_SERIALDRIVER) && !defined(CONFIG_UART9_RXDMA)
# undef SERIAL_HAVE_ONLY_DMA
#elif defined(CONFIG_STM32_USART10_SERIALDRIVER) && !defined(CONFIG_USART10_RXDMA)
# undef SERIAL_HAVE_ONLY_DMA
#elif defined(CONFIG_STM32_USART11_SERIALDRIVER) && !defined(CONFIG_USART11_RXDMA)
# undef SERIAL_HAVE_ONLY_DMA
#elif defined(CONFIG_STM32_UART12_SERIALDRIVER) && !defined(CONFIG_UART12_RXDMA)
# undef SERIAL_HAVE_ONLY_DMA
#endif
/* Is RS-485 used? */
#if defined(CONFIG_LPUART1_RS485) || defined(CONFIG_USART1_RS485) || \
defined(CONFIG_USART2_RS485) || defined(CONFIG_USART3_RS485) || \
defined(CONFIG_UART4_RS485) || defined(CONFIG_UART5_RS485)
defined(CONFIG_UART4_RS485) || defined(CONFIG_UART5_RS485) || \
defined(CONFIG_USART6_RS485) || defined(CONFIG_UART7_RS485) || \
defined(CONFIG_UART8_RS485) || defined(CONFIG_UART9_RS485) || \
defined(CONFIG_USART10_RS485) || defined(CONFIG_USART11_RS485) || \
defined(CONFIG_UART12_RS485)
# define HAVE_RS485 1
#endif

5
arch/arm/src/stm32h5/CMakeLists.txt
View file

@ -37,17 +37,12 @@ endif()
list(
APPEND
SRCS
stm32_lowputc.c
stm32_rcc.c
stm32_pwr.c
stm32_lse.c
stm32_lsi.c
stm32_sdmmc.c)
if(CONFIG_STM32_USART)
list(APPEND SRCS stm32_serial.c)
endif()
if(CONFIG_TIMER)
list(APPEND SRCS stm32_tim_lowerhalf.c)
endif()

1
arch/arm/src/stm32h5/Kconfig
View file

@ -12,6 +12,7 @@ config STM32_H5_PERIPHERALS
default y
select STM32_HAVE_IP_EXTI_M33_V1
select STM32_HAVE_IP_GPIO_M33_V1
select STM32_HAVE_IP_USART_M33_V3
select STM32_HAVE_DMA1
select STM32_HAVE_DMA2
select STM32_HAVE_I2C1

6
arch/arm/src/stm32h5/Make.defs
View file

@ -40,14 +40,10 @@ endif
# Required STM32H5 files
CHIP_CSRCS += stm32_lowputc.c stm32_rcc.c
CHIP_CSRCS += stm32_rcc.c
CHIP_CSRCS += stm32_pwr.c
CHIP_CSRCS += stm32_lse.c stm32_lsi.c stm32_sdmmc.c
ifeq ($(CONFIG_STM32_USART),y)
CHIP_CSRCS += stm32_serial.c
endif
ifeq ($(CONFIG_TIMER),y)
CHIP_CSRCS += stm32_tim_lowerhalf.c
endif

43
arch/arm/src/stm32h5/hardware/stm32_uart.h
View file

@ -1,43 +0,0 @@
/****************************************************************************
* arch/arm/src/stm32h5/hardware/stm32_uart.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32_UART_H
#define __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32_UART_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#if defined(CONFIG_STM32_STM32H50XXX) || \
defined(CONFIG_STM32_STM32H52XXX) || \
defined(CONFIG_STM32_STM32H53XXX) || \
defined(CONFIG_STM32_STM32H56XXX) || \
defined(CONFIG_STM32_STM32H57XXX)
# include "hardware/stm32h5xxx_uart.h"
#else
# error "Unsupported STM32 H5 uart"
#endif
#endif /* __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32_UART_H */

18
arch/arm/src/stm32h5/hardware/stm32h56x_dmasigmap.h
View file

@ -215,4 +215,20 @@
#define GPDMA_TRIG_LPTIM6_CH1 (42)
#define GPDMA_TRIG_LPTIM6_CH2 (43)
#endif /* __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32H56X_DMASIGMAP_H */
/* USART RX DMA request numbers */
#define STM32_LPUART1_RXDMA_REQ GPDMA_REQ_LPUART1_RX
#define STM32_USART1_RXDMA_REQ GPDMA_REQ_USART1_RX
#define STM32_USART2_RXDMA_REQ GPDMA_REQ_USART2_RX
#define STM32_USART3_RXDMA_REQ GPDMA_REQ_USART3_RX
#define STM32_UART4_RXDMA_REQ GPDMA_REQ_UART4_RX
#define STM32_UART5_RXDMA_REQ GPDMA_REQ_UART5_RX
#define STM32_USART6_RXDMA_REQ GPDMA_REQ_USART6_RX
#define STM32_UART7_RXDMA_REQ GPDMA_REQ_UART7_RX
#define STM32_UART8_RXDMA_REQ GPDMA_REQ_UART8_RX
#define STM32_UART9_RXDMA_REQ GPDMA_REQ_UART9_RX
#define STM32_USART10_RXDMA_REQ GPDMA_REQ_USART10_RX
#define STM32_USART11_RXDMA_REQ GPDMA_REQ_USART11_RX
#define STM32_UART12_RXDMA_REQ GPDMA_REQ_UART12_RX
#endif /* __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32H56X_DMASIGMAP_H */

464
arch/arm/src/stm32h5/hardware/stm32h5xxx_uart.h
View file

@ -1,464 +0,0 @@
/****************************************************************************
* arch/arm/src/stm32h5/hardware/stm32h5xxx_uart.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32H5XXX_UART_H
#define __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32H5XXX_UART_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register Offsets *********************************************************/
#define STM32_USART_CR1_OFFSET 0x0000 /* Control register 1 */
#define STM32_USART_CR2_OFFSET 0x0004 /* Control register 2 */
#define STM32_USART_CR3_OFFSET 0x0008 /* Control register 3 */
#define STM32_USART_BRR_OFFSET 0x000c /* Baud Rate register */
#define STM32_USART_GTPR_OFFSET 0x0010 /* Guard time and prescaler register */
#define STM32_USART_RTOR_OFFSET 0x0014 /* Receiver timeout register */
#define STM32_USART_RQR_OFFSET 0x0018 /* Request register */
#define STM32_USART_ISR_OFFSET 0x001c /* Interrupt and status register */
#define STM32_USART_ICR_OFFSET 0x0020 /* Interrupt flag clear register */
#define STM32_USART_RDR_OFFSET 0x0024 /* Receive Data register */
#define STM32_USART_TDR_OFFSET 0x0028 /* Transmit Data register */
#define STM32_USART_PRESC_OFFSET 0x002c /* Prescaler register */
/* Register Addresses *******************************************************/
#if STM32_NLPUART > 0
# define STM32_LPUART1_CR1 (STM32_LPUART1_BASE + STM32_USART_CR1_OFFSET)
# define STM32_LPUART1_CR2 (STM32_LPUART1_BASE + STM32_USART_CR2_OFFSET)
# define STM32_LPUART1_CR3 (STM32_LPUART1_BASE + STM32_USART_CR3_OFFSET)
# define STM32_LPUART1_BRR (STM32_LPUART1_BASE + STM32_USART_BRR_OFFSET)
# define STM32_LPUART1_GTPR (STM32_LPUART1_BASE + STM32_USART_GTPR_OFFSET)
# define STM32_LPUART1_RTOR (STM32_LPUART1_BASE + STM32_USART_RTOR_OFFSET)
# define STM32_LPUART1_RQR (STM32_LPUART1_BASE + STM32_USART_RQR_OFFSET)
# define STM32_LPUART1_ISR (STM32_LPUART1_BASE + STM32_USART_ISR_OFFSET)
# define STM32_LPUART1_ICR (STM32_LPUART1_BASE + STM32_USART_ICR_OFFSET)
# define STM32_LPUART1_RDR (STM32_LPUART1_BASE + STM32_USART_RDR_OFFSET)
# define STM32_LPUART1_TDR (STM32_LPUART1_BASE + STM32_USART_TDR_OFFSET)
# define STM32_LPUART1_PRESC (STM32_LPUART1_BASE + STM32_USART_PRESC_OFFSET)
#endif
#if STM32_NUSART > 0
# define STM32_USART1_CR1 (STM32_USART1_BASE + STM32_USART_CR1_OFFSET)
# define STM32_USART1_CR2 (STM32_USART1_BASE + STM32_USART_CR2_OFFSET)
# define STM32_USART1_CR3 (STM32_USART1_BASE + STM32_USART_CR3_OFFSET)
# define STM32_USART1_BRR (STM32_USART1_BASE + STM32_USART_BRR_OFFSET)
# define STM32_USART1_GTPR (STM32_USART1_BASE + STM32_USART_GTPR_OFFSET)
# define STM32_USART1_RTOR (STM32_USART1_BASE + STM32_USART_RTOR_OFFSET)
# define STM32_USART1_RQR (STM32_USART1_BASE + STM32_USART_RQR_OFFSET)
# define STM32_USART1_ISR (STM32_USART1_BASE + STM32_USART_ISR_OFFSET)
# define STM32_USART1_ICR (STM32_USART1_BASE + STM32_USART_ICR_OFFSET)
# define STM32_USART1_RDR (STM32_USART1_BASE + STM32_USART_RDR_OFFSET)
# define STM32_USART1_TDR (STM32_USART1_BASE + STM32_USART_TDR_OFFSET)
# define STM32_USART1_PRESC (STM32_USART1_BASE + STM32_USART_PRESC_OFFSET)
#endif
#if STM32_NUSART > 1
# define STM32_USART2_CR1 (STM32_USART2_BASE + STM32_USART_CR1_OFFSET)
# define STM32_USART2_CR2 (STM32_USART2_BASE + STM32_USART_CR2_OFFSET)
# define STM32_USART2_CR3 (STM32_USART2_BASE + STM32_USART_CR3_OFFSET)
# define STM32_USART2_BRR (STM32_USART2_BASE + STM32_USART_BRR_OFFSET)
# define STM32_USART2_GTPR (STM32_USART2_BASE + STM32_USART_GTPR_OFFSET)
# define STM32_USART2_RTOR (STM32_USART2_BASE + STM32_USART_RTOR_OFFSET)
# define STM32_USART2_RQR (STM32_USART2_BASE + STM32_USART_RQR_OFFSET)
# define STM32_USART2_ISR (STM32_USART2_BASE + STM32_USART_ISR_OFFSET)
# define STM32_USART2_ICR (STM32_USART2_BASE + STM32_USART_ICR_OFFSET)
# define STM32_USART2_RDR (STM32_USART2_BASE + STM32_USART_RDR_OFFSET)
# define STM32_USART2_TDR (STM32_USART2_BASE + STM32_USART_TDR_OFFSET)
# define STM32_USART2_PRESC (STM32_USART2_BASE + STM32_USART_PRESC_OFFSET)
#endif
#if STM32_NUSART > 2
# define STM32_USART3_CR1 (STM32_USART3_BASE + STM32_USART_CR1_OFFSET)
# define STM32_USART3_CR2 (STM32_USART3_BASE + STM32_USART_CR2_OFFSET)
# define STM32_USART3_CR3 (STM32_USART3_BASE + STM32_USART_CR3_OFFSET)
# define STM32_USART3_BRR (STM32_USART3_BASE + STM32_USART_BRR_OFFSET)
# define STM32_USART3_GTPR (STM32_USART3_BASE + STM32_USART_GTPR_OFFSET)
# define STM32_USART3_RTOR (STM32_USART3_BASE + STM32_USART_RTOR_OFFSET)
# define STM32_USART3_RQR (STM32_USART3_BASE + STM32_USART_RQR_OFFSET)
# define STM32_USART3_ISR (STM32_USART3_BASE + STM32_USART_ISR_OFFSET)
# define STM32_USART3_ICR (STM32_USART3_BASE + STM32_USART_ICR_OFFSET)
# define STM32_USART3_RDR (STM32_USART3_BASE + STM32_USART_RDR_OFFSET)
# define STM32_USART3_TDR (STM32_USART3_BASE + STM32_USART_TDR_OFFSET)
# define STM32_USART3_PRESC (STM32_USART3_BASE + STM32_USART_PRESC_OFFSET)
#endif
#if STM32_NUSART > 4
# define STM32_USART6_CR1 (STM32_USART6_BASE + STM32_USART_CR1_OFFSET)
# define STM32_USART6_CR2 (STM32_USART6_BASE + STM32_USART_CR2_OFFSET)
# define STM32_USART6_CR3 (STM32_USART6_BASE + STM32_USART_CR3_OFFSET)
# define STM32_USART6_BRR (STM32_USART6_BASE + STM32_USART_BRR_OFFSET)
# define STM32_USART6_GTPR (STM32_USART6_BASE + STM32_USART_GTPR_OFFSET)
# define STM32_USART6_RTOR (STM32_USART6_BASE + STM32_USART_RTOR_OFFSET)
# define STM32_USART6_RQR (STM32_USART6_BASE + STM32_USART_RQR_OFFSET)
# define STM32_USART6_ISR (STM32_USART6_BASE + STM32_USART_ISR_OFFSET)
# define STM32_USART6_ICR (STM32_USART6_BASE + STM32_USART_ICR_OFFSET)
# define STM32_USART6_RDR (STM32_USART6_BASE + STM32_USART_RDR_OFFSET)
# define STM32_USART6_TDR (STM32_USART6_BASE + STM32_USART_TDR_OFFSET)
# define STM32_USART6_PRESC (STM32_USART6_BASE + STM32_USART_PRESC_OFFSET)
#endif
#if STM32_NUSART > 5
# define STM32_USART10_CR1 (STM32_USART10_BASE + STM32_USART_CR1_OFFSET)
# define STM32_USART10_CR2 (STM32_USART10_BASE + STM32_USART_CR2_OFFSET)
# define STM32_USART10_CR3 (STM32_USART10_BASE + STM32_USART_CR3_OFFSET)
# define STM32_USART10_BRR (STM32_USART10_BASE + STM32_USART_BRR_OFFSET)
# define STM32_USART10_GTPR (STM32_USART10_BASE + STM32_USART_GTPR_OFFSET)
# define STM32_USART10_RTOR (STM32_USART10_BASE + STM32_USART_RTOR_OFFSET)
# define STM32_USART10_RQR (STM32_USART10_BASE + STM32_USART_RQR_OFFSET)
# define STM32_USART10_ISR (STM32_USART10_BASE + STM32_USART_ISR_OFFSET)
# define STM32_USART10_ICR (STM32_USART10_BASE + STM32_USART_ICR_OFFSET)
# define STM32_USART10_RDR (STM32_USART10_BASE + STM32_USART_RDR_OFFSET)
# define STM32_USART10_TDR (STM32_USART10_BASE + STM32_USART_TDR_OFFSET)
# define STM32_USART10_PRESC (STM32_USART10_BASE + STM32_USART_PRESC_OFFSET)
#endif
#if STM32_NUSART > 6
# define STM32_USART11_CR1 (STM32_USART11_BASE + STM32_USART_CR1_OFFSET)
# define STM32_USART11_CR2 (STM32_USART11_BASE + STM32_USART_CR2_OFFSET)
# define STM32_USART11_CR3 (STM32_USART11_BASE + STM32_USART_CR3_OFFSET)
# define STM32_USART11_BRR (STM32_USART11_BASE + STM32_USART_BRR_OFFSET)
# define STM32_USART11_GTPR (STM32_USART11_BASE + STM32_USART_GTPR_OFFSET)
# define STM32_USART11_RTOR (STM32_USART11_BASE + STM32_USART_RTOR_OFFSET)
# define STM32_USART11_RQR (STM32_USART11_BASE + STM32_USART_RQR_OFFSET)
# define STM32_USART11_ISR (STM32_USART11_BASE + STM32_USART_ISR_OFFSET)
# define STM32_USART11_ICR (STM32_USART11_BASE + STM32_USART_ICR_OFFSET)
# define STM32_USART11_RDR (STM32_USART11_BASE + STM32_USART_RDR_OFFSET)
# define STM32_USART11_TDR (STM32_USART11_BASE + STM32_USART_TDR_OFFSET)
# define STM32_USART11_PRESC (STM32_USART11_BASE + STM32_USART_PRESC_OFFSET)
#endif
#if STM32_NUART > 0
# define STM32_UART4_CR1 (STM32_UART4_BASE + STM32_USART_CR1_OFFSET)
# define STM32_UART4_CR2 (STM32_UART4_BASE + STM32_USART_CR2_OFFSET)
# define STM32_UART4_CR3 (STM32_UART4_BASE + STM32_USART_CR3_OFFSET)
# define STM32_UART4_BRR (STM32_UART4_BASE + STM32_USART_BRR_OFFSET)
# define STM32_UART4_GTPR (STM32_UART4_BASE + STM32_USART_GTPR_OFFSET)
# define STM32_UART4_RTOR (STM32_UART4_BASE + STM32_USART_RTOR_OFFSET)
# define STM32_UART4_RQR (STM32_UART4_BASE + STM32_USART_RQR_OFFSET)
# define STM32_UART4_ISR (STM32_UART4_BASE + STM32_USART_ISR_OFFSET)
# define STM32_UART4_ICR (STM32_UART4_BASE + STM32_USART_ICR_OFFSET)
# define STM32_UART4_RDR (STM32_UART4_BASE + STM32_USART_RDR_OFFSET)
# define STM32_UART4_TDR (STM32_UART4_BASE + STM32_USART_TDR_OFFSET)
# define STM32_UART4_PRESC (STM32_UART4_BASE + STM32_USART_PRESC_OFFSET)
#endif
#if STM32_NUART > 1
# define STM32_UART5_CR1 (STM32_UART5_BASE + STM32_USART_CR1_OFFSET)
# define STM32_UART5_CR2 (STM32_UART5_BASE + STM32_USART_CR2_OFFSET)
# define STM32_UART5_CR3 (STM32_UART5_BASE + STM32_USART_CR3_OFFSET)
# define STM32_UART5_BRR (STM32_UART5_BASE + STM32_USART_BRR_OFFSET)
# define STM32_UART5_GTPR (STM32_UART5_BASE + STM32_USART_GTPR_OFFSET)
# define STM32_UART5_RTOR (STM32_UART5_BASE + STM32_USART_RTOR_OFFSET)
# define STM32_UART5_RQR (STM32_UART5_BASE + STM32_USART_RQR_OFFSET)
# define STM32_UART5_ISR (STM32_UART5_BASE + STM32_USART_ISR_OFFSET)
# define STM32_UART5_ICR (STM32_UART5_BASE + STM32_USART_ICR_OFFSET)
# define STM32_UART5_RDR (STM32_UART5_BASE + STM32_USART_RDR_OFFSET)
# define STM32_UART5_TDR (STM32_UART5_BASE + STM32_USART_TDR_OFFSET)
# define STM32_UART5_PRESC (STM32_UART5_BASE + STM32_USART_PRESC_OFFSET)
#endif
#if STM32_NUART > 2
# define STM32_UART7_CR1 (STM32_UART7_BASE + STM32_USART_CR1_OFFSET)
# define STM32_UART7_CR2 (STM32_UART7_BASE + STM32_USART_CR2_OFFSET)
# define STM32_UART7_CR3 (STM32_UART7_BASE + STM32_USART_CR3_OFFSET)
# define STM32_UART7_BRR (STM32_UART7_BASE + STM32_USART_BRR_OFFSET)
# define STM32_UART7_GTPR (STM32_UART7_BASE + STM32_USART_GTPR_OFFSET)
# define STM32_UART7_RTOR (STM32_UART7_BASE + STM32_USART_RTOR_OFFSET)
# define STM32_UART7_RQR (STM32_UART7_BASE + STM32_USART_RQR_OFFSET)
# define STM32_UART7_ISR (STM32_UART7_BASE + STM32_USART_ISR_OFFSET)
# define STM32_UART7_ICR (STM32_UART7_BASE + STM32_USART_ICR_OFFSET)
# define STM32_UART7_RDR (STM32_UART7_BASE + STM32_USART_RDR_OFFSET)
# define STM32_UART7_TDR (STM32_UART7_BASE + STM32_USART_TDR_OFFSET)
# define STM32_UART7_PRESC (STM32_UART7_BASE + STM32_USART_PRESC_OFFSET)
#endif
#if STM32_NUART > 3
# define STM32_UART8_CR1 (STM32_UART8_BASE + STM32_USART_CR1_OFFSET)
# define STM32_UART8_CR2 (STM32_UART8_BASE + STM32_USART_CR2_OFFSET)
# define STM32_UART8_CR3 (STM32_UART8_BASE + STM32_USART_CR3_OFFSET)
# define STM32_UART8_BRR (STM32_UART8_BASE + STM32_USART_BRR_OFFSET)
# define STM32_UART8_GTPR (STM32_UART8_BASE + STM32_USART_GTPR_OFFSET)
# define STM32_UART8_RTOR (STM32_UART8_BASE + STM32_USART_RTOR_OFFSET)
# define STM32_UART8_RQR (STM32_UART8_BASE + STM32_USART_RQR_OFFSET)
# define STM32_UART8_ISR (STM32_UART8_BASE + STM32_USART_ISR_OFFSET)
# define STM32_UART8_ICR (STM32_UART8_BASE + STM32_USART_ICR_OFFSET)
# define STM32_UART8_RDR (STM32_UART8_BASE + STM32_USART_RDR_OFFSET)
# define STM32_UART8_TDR (STM32_UART8_BASE + STM32_USART_TDR_OFFSET)
# define STM32_UART8_PRESC (STM32_UART8_BASE + STM32_USART_PRESC_OFFSET)
#endif
#if STM32_NUART > 4
# define STM32_UART9_CR1 (STM32_UART9_BASE + STM32_USART_CR1_OFFSET)
# define STM32_UART9_CR2 (STM32_UART9_BASE + STM32_USART_CR2_OFFSET)
# define STM32_UART9_CR3 (STM32_UART9_BASE + STM32_USART_CR3_OFFSET)
# define STM32_UART9_BRR (STM32_UART9_BASE + STM32_USART_BRR_OFFSET)
# define STM32_UART9_GTPR (STM32_UART9_BASE + STM32_USART_GTPR_OFFSET)
# define STM32_UART9_RTOR (STM32_UART9_BASE + STM32_USART_RTOR_OFFSET)
# define STM32_UART9_RQR (STM32_UART9_BASE + STM32_USART_RQR_OFFSET)
# define STM32_UART9_ISR (STM32_UART9_BASE + STM32_USART_ISR_OFFSET)
# define STM32_UART9_ICR (STM32_UART9_BASE + STM32_USART_ICR_OFFSET)
# define STM32_UART9_RDR (STM32_UART9_BASE + STM32_USART_RDR_OFFSET)
# define STM32_UART9_TDR (STM32_UART9_BASE + STM32_USART_TDR_OFFSET)
# define STM32_UART9_PRESC (STM32_UART9_BASE + STM32_USART_PRESC_OFFSET)
#endif
#if STM32_NUART > 5
# define STM32_UART12_CR1 (STM32_UART12_BASE + STM32_USART_CR1_OFFSET)
# define STM32_UART12_CR2 (STM32_UART12_BASE + STM32_USART_CR2_OFFSET)
# define STM32_UART12_CR3 (STM32_UART12_BASE + STM32_USART_CR3_OFFSET)
# define STM32_UART12_BRR (STM32_UART12_BASE + STM32_USART_BRR_OFFSET)
# define STM32_UART12_GTPR (STM32_UART12_BASE + STM32_USART_GTPR_OFFSET)
# define STM32_UART12_RTOR (STM32_UART12_BASE + STM32_USART_RTOR_OFFSET)
# define STM32_UART12_RQR (STM32_UART12_BASE + STM32_USART_RQR_OFFSET)
# define STM32_UART12_ISR (STM32_UART12_BASE + STM32_USART_ISR_OFFSET)
# define STM32_UART12_ICR (STM32_UART12_BASE + STM32_USART_ICR_OFFSET)
# define STM32_UART12_RDR (STM32_UART12_BASE + STM32_USART_RDR_OFFSET)
# define STM32_UART12_TDR (STM32_UART12_BASE + STM32_USART_TDR_OFFSET)
# define STM32_UART12_PRESC (STM32_UART12_BASE + STM32_USART_PRESC_OFFSET)
#endif
/* Register Bitfield Definitions ********************************************/
/* Control register 1 */
#define USART_CR1_UE (1 << 0) /* Bit 0: USART Enable */
#define USART_CR1_UESM (1 << 1) /* Bit 1: USART Enable in Stop mode */
#define USART_CR1_RE (1 << 2) /* Bit 2: Receiver Enable */
#define USART_CR1_TE (1 << 3) /* Bit 3: Transmitter Enable */
#define USART_CR1_IDLEIE (1 << 4) /* Bit 4: IDLE Interrupt Enable */
#define USART_CR1_RXNEIE (1 << 5) /* Bit 5: RXNE Interrupt Enable */
#define USART_CR1_TCIE (1 << 6) /* Bit 6: Transmission Complete Interrupt Enable */
#define USART_CR1_TXEIE (1 << 7) /* Bit 7: TXE Interrupt Enable */
#define USART_CR1_PEIE (1 << 8) /* Bit 8: PE Interrupt Enable */
#define USART_CR1_PS (1 << 9) /* Bit 9: Parity Selection */
#define USART_CR1_PCE (1 << 10) /* Bit 10: Parity Control Enable */
#define USART_CR1_WAKE (1 << 11) /* Bit 11: Wakeup method */
#define USART_CR1_M0 (1 << 12) /* Bit 12: Word length */
#define USART_CR1_MME (1 << 13) /* Bit 13: Mute mode enable */
#define USART_CR1_CMIE (1 << 14) /* Bit 14: Character match interrupt enable */
#define USART_CR1_OVER8 (1 << 15) /* Bit 15: Oversampling mode */
#define USART_CR1_DEDT_SHIFT (16) /* Bits 16..20 DE deactivation delay */
#define USART_CR1_DEDT_MASK (0x1f << USART_CR1_DEDT_SHIFT)
#define USART_CR1_DEAT_SHIFT (21) /* Bits 21..25 DE activation delay */
#define USART_CR1_DEAT_MASK (0x1f << USART_CR1_DEAT_SHIFT)
#define USART_CR1_RTOIE (1 << 26) /* Bit 26: Receiver timeout interrupt enable */
#define USART_CR1_EOBIE (1 << 27) /* Bit 27: End of block interrupt enable */
#define USART_CR1_M1 (1 << 28) /* Bit 28: Word length */
#define USART_CR1_FIFOEN (1 << 29) /* Bit 29: FIFO EN */
#define USART_CR1_TXFEIE (1 << 30) /* Bit 30: TX FIFO empty interrupt enable */
#define USART_CR1_RXFFIE (1 << 31) /* Bit 31: RX FIFO full interrupt enable */
#define USART_CR1_ALLINTS (USART_CR1_IDLEIE|USART_CR1_RXNEIE| \
USART_CR1_TCIE|USART_CR1_TXEIE| \
USART_CR1_PEIE|USART_CR1_CMIE| \
USART_CR1_RTOIE|USART_CR1_EOBIE| \
USART_CR1_TXFEIE|USART_CR1_RXFFIE)
#define LPUART_CR1_ALLINTS \
(USART_CR1_IDLEIE | USART_CR1_RXNEIE | USART_CR1_TCIE | \
USART_CR1_TXEIE | USART_CR1_PEIE | USART_CR1_CMIE | \
USART_CR1_TXFEIE | USART_CR1_RXFFIE | \
USART_CR1_TXFEIE | USART_CR1_RXFFIE)
/* Control register 2 */
#define USART_CR2_ADDM7 (1 << 4) /* Bit 4: 7-bit/4-bit Address Detection */
#define USART_CR2_LBDL (1 << 5) /* Bit 5: LIN Break Detection Length */
#define USART_CR2_LBDIE (1 << 6) /* Bit 6: LIN Break Detection Interrupt Enable */
#define USART_CR2_LBCL (1 << 8) /* Bit 8: Last Bit Clock pulse */
#define USART_CR2_CPHA (1 << 9) /* Bit 9: Clock Phase */
#define USART_CR2_CPOL (1 << 10) /* Bit 10: Clock Polarity */
#define USART_CR2_CLKEN (1 << 11) /* Bit 11: Clock Enable */
#define USART_CR2_STOP_SHIFT (12) /* Bits 13-12: STOP bits */
#define USART_CR2_STOP_MASK (3 << USART_CR2_STOP_SHIFT)
# define USART_CR2_STOP1 (0 << USART_CR2_STOP_SHIFT) /* 00: 1 Stop bit */
# define USART_CR2_STOP0p5 (1 << USART_CR2_STOP_SHIFT) /* 01: 0.5 Stop bit */
# define USART_CR2_STOP2 (2 << USART_CR2_STOP_SHIFT) /* 10: 2 Stop bits */
# define USART_CR2_STOP1p5 (3 << USART_CR2_STOP_SHIFT) /* 11: 1.5 Stop bit */
#define USART_CR2_LINEN (1 << 14) /* Bit 14: LIN mode enable */
#define USART_CR2_SWAP (1 << 15) /* Bit 15: Swap TX/RX pins */
#define USART_CR2_RXINV (1 << 16) /* Bit 16: RX pin active level inversion */
#define USART_CR2_TXINV (1 << 17) /* Bit 17: TX pin active level inversion */
#define USART_CR2_DATAINV (1 << 18) /* Bit 18: Binary data inversion */
#define USART_CR2_MSBFIRST (1 << 19) /* Bit 19: Most significant bit first */
#define USART_CR2_ABREN (1 << 20) /* Bit 20: Auto Baud rate enable */
#define USART_CR2_ABRMOD_SHIFT (21) /* Bits 21-22: Autobaud rate mode*/
#define USART_CR2_ABRMOD_MASK (3 << USART_CR2_ABRMOD_SHIFT)
#define USART_CR2_ABRMOD_START (0 << USART_CR2_ABRMOD_SHIFT) /* 00: Start bit */
#define USART_CR2_ABRMOD_EDGES (1 << USART_CR2_ABRMOD_SHIFT) /* 01: Falling-to-falling edge -> frame must start with 10xxxxxx */
#define USART_CR2_ABRMOD_7F (2 << USART_CR2_ABRMOD_SHIFT) /* 10: 0x7F */
#define USART_CR2_ABRMOD_55 (3 << USART_CR2_ABRMOD_SHIFT) /* 11: 0x55 */
#define USART_CR2_RTOEN (1 << 23) /* Bit 23: Receiver timeout enable */
#define USART_CR2_ADD_SHIFT (24) /* Bits 24-31: Address of the USART node */
#define USART_CR2_ADD_MASK (0xff << USART_CR2_ADD_SHIFT)
/* Control register 3 */
#define USART_CR3_EIE (1 << 0) /* Bit 0: Error Interrupt Enable */
#define USART_CR3_IREN (1 << 1) /* Bit 1: IrDA mode Enable */
#define USART_CR3_IRLP (1 << 2) /* Bit 2: IrDA Low-Power */
#define USART_CR3_HDSEL (1 << 3) /* Bit 3: Half-Duplex Selection */
#define USART_CR3_NACK (1 << 4) /* Bit 4: Smartcard NACK enable */
#define USART_CR3_SCEN (1 << 5) /* Bit 5: Smartcard mode enable */
#define USART_CR3_DMAR (1 << 6) /* Bit 6: DMA Enable Receiver */
#define USART_CR3_DMAT (1 << 7) /* Bit 7: DMA Enable Transmitter */
#define USART_CR3_RTSE (1 << 8) /* Bit 8: RTS Enable */
#define USART_CR3_CTSE (1 << 9) /* Bit 9: CTS Enable */
#define USART_CR3_CTSIE (1 << 10) /* Bit 10: CTS Interrupt Enable */
#define USART_CR3_ONEBIT (1 << 11) /* Bit 11: One sample bit method Enable */
#define USART_CR3_OVRDIS (1 << 12) /* Bit 12: Overrun Disable */
#define USART_CR3_DDRE (1 << 13) /* Bit 13: DMA disable on Reception error */
#define USART_CR3_DEM (1 << 14) /* Bit 14: Driver Enable mode */
#define USART_CR3_DEP (1 << 15) /* Bit 15: Driver Enable polarity selection */
#define USART_CR3_SCARCNT2_SHIFT (17) /* Bits 17-19: Smart card auto retry count */
#define USART_CR3_SCARCNT2_MASK (7 << USART_CR3_SCARCNT2_SHIFT)
#define USART_CR3_WUS_SHIFT (20) /* Bits 20-21: Wakeup from Stop mode interrupt flag selection */
#define USART_CR3_WUS_MASK (3 << USART_CR3_WUS_SHIFT)
#define USART_CR3_WUS_ADDRESS (0 << USART_CR3_WUS_SHIFT) /* 00: WUF active on address match */
#define USART_CR3_WUS_START (2 << USART_CR3_WUS_SHIFT) /* 10: WUF active on Start bit detection */
#define USART_CR3_WUS_RXNE (3 << USART_CR3_WUS_SHIFT) /* 11: WUF active on RXNE */
#define USART_CR3_WUFIE (1 << 22) /* Bit 22: Wakeup from Stop mode interrupt enable */
#define USART_CR3_TXFTIE (1 << 23) /* Bit 23: TXFIFO threshold interrupt enable */
#define USART_CR3_TCBGTIE (1 << 24) /* Bit 24: Transmission Complete before guard time, interrupt enable */
#define USART_CR3_RXFTCFG_SHIFT (25) /* Bits 25-27: Receive FIFO threshold configuration */
#define USART_CR3_RXFTCFG_MASK (7 << USART_CR3_RXFTCFG_SHIFT)
#define USART_CR3_RXFTIE (1 << 28) /* Bit 28: RXFIFO threshold interrupt enable */
#define USART_CR3_TXFTCFG_SHIFT (29) /* Bits 29-31: Transmit FIFO threshold configuration */
#define USART_CR3_TXFTCFG_MASK (7 << USART_CR3_TXFTCFG_SHIFT)
#define USART_CR3_TXFTCFG_0 (0) /* TX FIFO reaches 1/8 depth */
#define USART_CR3_TXFTCFG_1 (1) /* TX FIFO reaches 1/4 depth */
#define USART_CR3_TXFTCFG_2 (2) /* TX FIFO reaches 1/2 depth */
#define USART_CR3_TXFTCFG_3 (3) /* TX FIFO reaches 3/4 depth */
#define USART_CR3_TXFTCFG_4 (4) /* TX FIFO reaches 7/8 depth */
#define USART_CR3_TXFTCFG_5 (5) /* TX FIFO reaches full depth */
#define USART_CR3_RXFTCFG_0 (0) /* RX FIFO reaches 1/8 depth */
#define USART_CR3_RXFTCFG_1 (1) /* RX FIFO reaches 1/4 depth */
#define USART_CR3_RXFTCFG_2 (2) /* RX FIFO reaches 1/2 depth */
#define USART_CR3_RXFTCFG_3 (3) /* RX FIFO reaches 3/4 depth */
#define USART_CR3_RXFTCFG_4 (4) /* RX FIFO reaches 7/8 depth */
#define USART_CR3_RXFTCFG_5 (5) /* RX FIFO reaches full depth */
/* Baud Rate Register */
#define USART_BRR_FRAC_SHIFT (0) /* Bits 3-0: fraction of USARTDIV */
#define USART_BRR_FRAC_MASK (0x0f << USART_BRR_FRAC_SHIFT)
#define USART_BRR_MANT_SHIFT (4) /* Bits 15-4: mantissa of USARTDIV */
#define USART_BRR_MANT_MASK (0x0fff << USART_BRR_MANT_SHIFT)
/* Guard time and prescaler register */
#define USART_GTPR_PSC_SHIFT (0) /* Bits 0-7: Prescaler value */
#define USART_GTPR_PSC_MASK (0xff << USART_GTPR_PSC_SHIFT)
#define USART_GTPR_GT_SHIFT (8) /* Bits 8-15: Guard time value */
#define USART_GTPR_GT_MASK (0xff << USART_GTPR_GT_SHIFT)
/* Receiver timeout register */
/* Request Register */
#define USART_CR1_SBRKQ (1 << 1) /* Bit 1: Send Break */
/* Interrupt and Status register */
#define USART_ISR_PE (1 << 0) /* Bit 0: Parity Error */
#define USART_ISR_FE (1 << 1) /* Bit 1: Framing Error */
#define USART_ISR_NF (1 << 2) /* Bit 2: Noise Error Flag */
#define USART_ISR_ORE (1 << 3) /* Bit 3: OverRun Error */
#define USART_ISR_IDLE (1 << 4) /* Bit 4: IDLE line detected */
#define USART_ISR_RXNE (1 << 5) /* Bit 5: Read Data Register Not Empty */
#define USART_ISR_TC (1 << 6) /* Bit 6: Transmission Complete */
#define USART_ISR_TXE (1 << 7) /* Bit 7: Transmit Data Register Empty */
#define USART_ISR_LBDF (1 << 8) /* Bit 8: LIN Break Detection Flag */
#define USART_ISR_CTSIF (1 << 9) /* Bit 9: CTS Interrupt Flag */
#define USART_ISR_CTS (1 << 10) /* Bit 10: CTS Flag */
#define USART_ISR_RTOF (1 << 11) /* Bit 11: Receiver timeout Flag */
#define USART_ISR_EOBF (1 << 12) /* Bit 12: End of block Flag */
#define USART_ISR_UDR (1 << 13) /* Bit 13: SPI slave underrun error flag */
#define USART_ISR_ABRE (1 << 14) /* Bit 14: Auto baud rate Error */
#define USART_ISR_ABRF (1 << 15) /* Bit 15: Auto baud rate Flag */
#define USART_ISR_BUSY (1 << 16) /* Bit 16: Busy Flag */
#define USART_ISR_CMF (1 << 17) /* Bit 17: Character match Flag */
#define USART_ISR_SBKF (1 << 18) /* Bit 18: Send break Flag */
#define USART_ISR_RWU (1 << 19) /* Bit 19: Receiver wakeup from Mute mode */
#define USART_ISR_WUF (1 << 20) /* Bit 20: Wakeup from Stop mode Flag */
#define USART_ISR_TEACK (1 << 21) /* Bit 21: Transmit enable acknowledge Flag */
#define USART_ISR_REACK (1 << 22) /* Bit 22: Receive enable acknowledge Flag */
#define USART_ISR_TXFE (1 << 23) /* Bit 23: TXFIFO empty */
#define USART_ISR_RXFF (1 << 24) /* Bit 24: RXFIFO full */
#define USART_ISR_TCBGT (1 << 25) /* Bit 25: Transmission complete before guard time flag */
#define USART_ISR_RXFT (1 << 26) /* Bit 26: RXFIFO threshold reached */
#define USART_ISR_TXFT (1 << 27) /* Bit 27: TXFIFO threshold reached */
/* ICR */
#define USART_ICR_PECF (1 << 0) /* Bit 0: Parity error clear flag */
#define USART_ICR_FECF (1 << 1) /* Bit 1: Framing error clear flag */
#define USART_ICR_NCF (1 << 2) /* Bit 2: Noise detected clear flag */
#define USART_ICR_ORECF (1 << 3) /* Bit 3: Overrun error clear flag */
#define USART_ICR_IDLECF (1 << 4) /* Bit 4: Idle line detected clear flag */
#define USART_ICR_TCCF (1 << 6) /* Bit 6: Transmission complete clear flag */
#define USART_ICR_LBDCF (1 << 8) /* Bit 8: LIN break detection clear flag */
#define USART_ICR_CTSCF (1 << 9) /* Bit 9: CTS clear flag */
#define USART_ICR_RTOCF (1 << 11) /* Bit 11: Receiver timeout clear flag */
#define USART_ICR_EOBCF (1 << 12) /* Bit 12: End of block clear flag */
#define USART_ICR_CMCF (1 << 17) /* Bit 17: Character match clear flag */
#define USART_ICR_WUCF (1 << 20) /* Bit 20: Wakeup from Stop mode clear flag */
/* Receive Data register */
#define USART_RDR_SHIFT (0) /* Bits 8:0: Data value */
#define USART_RDR_MASK (0xff << USART_RDR_SHIFT)
/* Transmit Data register */
#define USART_TDR_SHIFT (0) /* Bits 8:0: Data value */
#define USART_TDR_MASK (0xff << USART_TDR_SHIFT)
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
#endif /* __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32H5XXX_UART_H */

1
arch/arm/src/stm32h5/stm32.h
View file

@ -39,6 +39,7 @@
#include "chip.h"
#include "stm32_adc.h"
#include "stm32_dbgmcu.h"
#include "stm32_dma.h"
#include "stm32_dts.h"
#include "stm32_flash.h"
#include "stm32_gpio.h"

552
arch/arm/src/stm32h5/stm32_lowputc.c
View file

@ -1,552 +0,0 @@
/****************************************************************************
* arch/arm/src/stm32h5/stm32_lowputc.c
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <arch/board/board.h>
#include "arm_internal.h"
#include "chip.h"
#include "stm32.h"
#include "stm32_rcc.h"
#include "stm32_gpio.h"
#include "stm32_uart.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Select USART parameters for the selected console */
#ifdef HAVE_CONSOLE
# if defined(CONFIG_LPUART1_SERIAL_CONSOLE)
# define STM32_CONSOLE_BASE STM32_LPUART1_BASE
# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY
# define STM32_CONSOLE_APBREG STM32_RCC_APB3ENR
# define STM32_CONSOLE_APBEN RCC_APB3ENR_LPUART1EN
# define STM32_CONSOLE_BAUD CONFIG_LPUART1_BAUD
# define STM32_CONSOLE_BITS CONFIG_LPUART1_BITS
# define STM32_CONSOLE_PARITY CONFIG_LPUART1_PARITY
# define STM32_CONSOLE_2STOP CONFIG_LPUART1_2STOP
# define STM32_CONSOLE_TX GPIO_LPUART1_TX
# define STM32_CONSOLE_RX GPIO_LPUART1_RX
# ifdef CONFIG_LPUART1_RS485
# define STM32_CONSOLE_RS485_DIR GPIO_LPUART1_RS485_DIR
# if (CONFIG_LPUART1_RS485_DIR_POLARITY == 0)
# define STM32_CONSOLE_RS485_DIR_POLARITY false
# else
# define STM32_CONSOLE_RS485_DIR_POLARITY true
# endif
# endif
# elif defined(CONFIG_USART1_SERIAL_CONSOLE)
# define STM32_CONSOLE_BASE STM32_USART1_BASE
# define STM32_APBCLOCK STM32_PCLK2_FREQUENCY
# define STM32_CONSOLE_APBREG STM32_RCC_APB2ENR
# define STM32_CONSOLE_APBEN RCC_APB2ENR_USART1EN
# define STM32_CONSOLE_BAUD CONFIG_USART1_BAUD
# define STM32_CONSOLE_BITS CONFIG_USART1_BITS
# define STM32_CONSOLE_PARITY CONFIG_USART1_PARITY
# define STM32_CONSOLE_2STOP CONFIG_USART1_2STOP
# define STM32_CONSOLE_TX GPIO_USART1_TX
# define STM32_CONSOLE_RX GPIO_USART1_RX
# ifdef CONFIG_USART1_RS485
# define STM32_CONSOLE_RS485_DIR GPIO_USART1_RS485_DIR
# if (CONFIG_USART1_RS485_DIR_POLARITY == 0)
# define STM32_CONSOLE_RS485_DIR_POLARITY false
# else
# define STM32_CONSOLE_RS485_DIR_POLARITY true
# endif
# endif
# elif defined(CONFIG_USART2_SERIAL_CONSOLE)
# define STM32_CONSOLE_BASE STM32_USART2_BASE
# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY
# define STM32_CONSOLE_APBREG STM32_RCC_APB1LENR
# define STM32_CONSOLE_APBEN RCC_APB1LENR_USART2EN
# define STM32_CONSOLE_BAUD CONFIG_USART2_BAUD
# define STM32_CONSOLE_BITS CONFIG_USART2_BITS
# define STM32_CONSOLE_PARITY CONFIG_USART2_PARITY
# define STM32_CONSOLE_2STOP CONFIG_USART2_2STOP
# define STM32_CONSOLE_TX GPIO_USART2_TX
# define STM32_CONSOLE_RX GPIO_USART2_RX
# ifdef CONFIG_USART2_RS485
# define STM32_CONSOLE_RS485_DIR GPIO_USART2_RS485_DIR
# if (CONFIG_USART2_RS485_DIR_POLARITY == 0)
# define STM32_CONSOLE_RS485_DIR_POLARITY false
# else
# define STM32_CONSOLE_RS485_DIR_POLARITY true
# endif
# endif
# elif defined(CONFIG_USART3_SERIAL_CONSOLE)
# define STM32_CONSOLE_BASE STM32_USART3_BASE
# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY
# define STM32_CONSOLE_APBREG STM32_RCC_APB1LENR
# define STM32_CONSOLE_APBEN RCC_APB1LENR_USART3EN
# define STM32_CONSOLE_BAUD CONFIG_USART3_BAUD
# define STM32_CONSOLE_BITS CONFIG_USART3_BITS
# define STM32_CONSOLE_PARITY CONFIG_USART3_PARITY
# define STM32_CONSOLE_2STOP CONFIG_USART3_2STOP
# define STM32_CONSOLE_TX GPIO_USART3_TX
# define STM32_CONSOLE_RX GPIO_USART3_RX
# ifdef CONFIG_USART3_RS485
# define STM32_CONSOLE_RS485_DIR GPIO_USART3_RS485_DIR
# if (CONFIG_USART3_RS485_DIR_POLARITY == 0)
# define STM32_CONSOLE_RS485_DIR_POLARITY false
# else
# define STM32_CONSOLE_RS485_DIR_POLARITY true
# endif
# endif
# elif defined(CONFIG_UART4_SERIAL_CONSOLE)
# define STM32_CONSOLE_BASE STM32_UART4_BASE
# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY
# define STM32_CONSOLE_APBREG STM32_RCC_APB1LENR
# define STM32_CONSOLE_APBEN RCC_APB1LENR_UART4EN
# define STM32_CONSOLE_BAUD CONFIG_UART4_BAUD
# define STM32_CONSOLE_BITS CONFIG_UART4_BITS
# define STM32_CONSOLE_PARITY CONFIG_UART4_PARITY
# define STM32_CONSOLE_2STOP CONFIG_UART4_2STOP
# define STM32_CONSOLE_TX GPIO_UART4_TX
# define STM32_CONSOLE_RX GPIO_UART4_RX
# ifdef CONFIG_UART4_RS485
# define STM32_CONSOLE_RS485_DIR GPIO_UART4_RS485_DIR
# if (CONFIG_UART4_RS485_DIR_POLARITY == 0)
# define STM32_CONSOLE_RS485_DIR_POLARITY false
# else
# define STM32_CONSOLE_RS485_DIR_POLARITY true
# endif
# endif
# elif defined(CONFIG_UART5_SERIAL_CONSOLE)
# define STM32_CONSOLE_BASE STM32_UART5_BASE
# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY
# define STM32_CONSOLE_APBREG STM32_RCC_APB1LENR
# define STM32_CONSOLE_APBEN RCC_APB1LENR_UART5EN
# define STM32_CONSOLE_BAUD CONFIG_UART5_BAUD
# define STM32_CONSOLE_BITS CONFIG_UART5_BITS
# define STM32_CONSOLE_PARITY CONFIG_UART5_PARITY
# define STM32_CONSOLE_2STOP CONFIG_UART5_2STOP
# define STM32_CONSOLE_TX GPIO_UART5_TX
# define STM32_CONSOLE_RX GPIO_UART5_RX
# ifdef CONFIG_UART5_RS485
# define STM32_CONSOLE_RS485_DIR GPIO_UART5_RS485_DIR
# if (CONFIG_UART5_RS485_DIR_POLARITY == 0)
# define STM32_CONSOLE_RS485_DIR_POLARITY false
# else
# define STM32_CONSOLE_RS485_DIR_POLARITY true
# endif
# endif
# elif defined(CONFIG_USART6_SERIAL_CONSOLE)
# define STM32_CONSOLE_BASE STM32_USART6_BASE
# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY
# define STM32_CONSOLE_APBREG STM32_RCC_APB1LENR
# define STM32_CONSOLE_APBEN RCC_APB1LENR_USART6EN
# define STM32_CONSOLE_BAUD CONFIG_USART6_BAUD
# define STM32_CONSOLE_BITS CONFIG_USART6_BITS
# define STM32_CONSOLE_PARITY CONFIG_USART6_PARITY
# define STM32_CONSOLE_2STOP CONFIG_USART6_2STOP
# define STM32_CONSOLE_TX GPIO_USART6_TX
# define STM32_CONSOLE_RX GPIO_USART6_RX
# ifdef CONFIG_USART6_RS485
# define STM32_CONSOLE_RS485_DIR GPIO_USART6_RS485_DIR
# if (CONFIG_USART6_RS485_DIR_POLARITY == 0)
# define STM32_CONSOLE_RS485_DIR_POLARITY false
# else
# define STM32_CONSOLE_RS485_DIR_POLARITY true
# endif
# endif
# elif defined(CONFIG_UART7_SERIAL_CONSOLE)
# define STM32_CONSOLE_BASE STM32_UART7_BASE
# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY
# define STM32_CONSOLE_APBREG STM32_RCC_APB1LENR
# define STM32_CONSOLE_APBEN RCC_APB1LENR_UART7EN
# define STM32_CONSOLE_BAUD CONFIG_UART7_BAUD
# define STM32_CONSOLE_BITS CONFIG_UART7_BITS
# define STM32_CONSOLE_PARITY CONFIG_UART7_PARITY
# define STM32_CONSOLE_2STOP CONFIG_UART7_2STOP
# define STM32_CONSOLE_TX GPIO_UART7_TX
# define STM32_CONSOLE_RX GPIO_UART7_RX
# ifdef CONFIG_UART7_RS485
# define STM32_CONSOLE_RS485_DIR GPIO_UART7_RS485_DIR
# if (CONFIG_UART7_RS485_DIR_POLARITY == 0)
# define STM32_CONSOLE_RS485_DIR_POLARITY false
# else
# define STM32_CONSOLE_RS485_DIR_POLARITY true
# endif
# endif
# elif defined(CONFIG_UART8_SERIAL_CONSOLE)
# define STM32_CONSOLE_BASE STM32_UART8_BASE
# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY
# define STM32_CONSOLE_APBREG STM32_RCC_APB1LENR
# define STM32_CONSOLE_APBEN RCC_APB1LENR_UART8EN
# define STM32_CONSOLE_BAUD CONFIG_UART8_BAUD
# define STM32_CONSOLE_BITS CONFIG_UART8_BITS
# define STM32_CONSOLE_PARITY CONFIG_UART8_PARITY
# define STM32_CONSOLE_2STOP CONFIG_UART8_2STOP
# define STM32_CONSOLE_TX GPIO_UART8_TX
# define STM32_CONSOLE_RX GPIO_UART8_RX
# ifdef CONFIG_UART8_RS485
# define STM32_CONSOLE_RS485_DIR GPIO_UART8_RS485_DIR
# if (CONFIG_UART8_RS485_DIR_POLARITY == 0)
# define STM32_CONSOLE_RS485_DIR_POLARITY false
# else
# define STM32_CONSOLE_RS485_DIR_POLARITY true
# endif
# endif
# elif defined(CONFIG_UART9_SERIAL_CONSOLE)
# define STM32_CONSOLE_BASE STM32_UART9_BASE
# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY
# define STM32_CONSOLE_APBREG STM32_RCC_APB1LENR
# define STM32_CONSOLE_APBEN RCC_APB1LENR_UART9EN
# define STM32_CONSOLE_BAUD CONFIG_UART9_BAUD
# define STM32_CONSOLE_BITS CONFIG_UART9_BITS
# define STM32_CONSOLE_PARITY CONFIG_UART9_PARITY
# define STM32_CONSOLE_2STOP CONFIG_UART9_2STOP
# define STM32_CONSOLE_TX GPIO_UART9_TX
# define STM32_CONSOLE_RX GPIO_UART9_RX
# ifdef CONFIG_UART9_RS485
# define STM32_CONSOLE_RS485_DIR GPIO_UART9_RS485_DIR
# if (CONFIG_UART9_RS485_DIR_POLARITY == 0)
# define STM32_CONSOLE_RS485_DIR_POLARITY false
# else
# define STM32_CONSOLE_RS485_DIR_POLARITY true
# endif
# endif
# elif defined(CONFIG_USART10_SERIAL_CONSOLE)
# define STM32_CONSOLE_BASE STM32_USART10_BASE
# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY
# define STM32_CONSOLE_APBREG STM32_RCC_APB1LENR
# define STM32_CONSOLE_APBEN RCC_APB1LENR_USART10EN
# define STM32_CONSOLE_BAUD CONFIG_USART10_BAUD
# define STM32_CONSOLE_BITS CONFIG_USART10_BITS
# define STM32_CONSOLE_PARITY CONFIG_USART10_PARITY
# define STM32_CONSOLE_2STOP CONFIG_USART10_2STOP
# define STM32_CONSOLE_TX GPIO_USART10_TX
# define STM32_CONSOLE_RX GPIO_USART10_RX
# ifdef CONFIG_USART10_RS485
# define STM32_CONSOLE_RS485_DIR GPIO_USART10_RS485_DIR
# if (CONFIG_USART10_RS485_DIR_POLARITY == 0)
# define STM32_CONSOLE_RS485_DIR_POLARITY false
# else
# define STM32_CONSOLE_RS485_DIR_POLARITY true
# endif
# endif
# elif defined(CONFIG_USART11_SERIAL_CONSOLE)
# define STM32_CONSOLE_BASE STM32_USART11_BASE
# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY
# define STM32_CONSOLE_APBREG STM32_RCC_APB1LENR
# define STM32_CONSOLE_APBEN RCC_APB1LENR_USART11EN
# define STM32_CONSOLE_BAUD CONFIG_USART11_BAUD
# define STM32_CONSOLE_BITS CONFIG_USART11_BITS
# define STM32_CONSOLE_PARITY CONFIG_USART11_PARITY
# define STM32_CONSOLE_2STOP CONFIG_USART11_2STOP
# define STM32_CONSOLE_TX GPIO_USART11_TX
# define STM32_CONSOLE_RX GPIO_USART11_RX
# ifdef CONFIG_USART11_RS485
# define STM32_CONSOLE_RS485_DIR GPIO_USART11_RS485_DIR
# if (CONFIG_USART11_RS485_DIR_POLARITY == 0)
# define STM32_CONSOLE_RS485_DIR_POLARITY false
# else
# define STM32_CONSOLE_RS485_DIR_POLARITY true
# endif
# endif
# elif defined(CONFIG_UART12_SERIAL_CONSOLE)
# define STM32_CONSOLE_BASE STM32_UART12_BASE
# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY
# define STM32_CONSOLE_APBREG STM32_RCC_APB1LENR
# define STM32_CONSOLE_APBEN RCC_APB1LENR_UART12EN
# define STM32_CONSOLE_BAUD CONFIG_UART12_BAUD
# define STM32_CONSOLE_BITS CONFIG_UART12_BITS
# define STM32_CONSOLE_PARITY CONFIG_UART12_PARITY
# define STM32_CONSOLE_2STOP CONFIG_UART12_2STOP
# define STM32_CONSOLE_TX GPIO_UART12_TX
# define STM32_CONSOLE_RX GPIO_UART12_RX
# ifdef CONFIG_UART12_RS485
# define STM32_CONSOLE_RS485_DIR GPIO_UART12_RS485_DIR
# if (CONFIG_UART12_RS485_DIR_POLARITY == 0)
# define STM32_CONSOLE_RS485_DIR_POLARITY false
# else
# define STM32_CONSOLE_RS485_DIR_POLARITY true
# endif
# endif
# endif
/* CR1 settings */
# if STM32_CONSOLE_BITS == 9
# define USART_CR1_M0_VALUE USART_CR1_M0
# define USART_CR1_M1_VALUE 0
# elif STM32_CONSOLE_BITS == 7
# define USART_CR1_M0_VALUE 0
# define USART_CR1_M1_VALUE USART_CR1_M1
# else /* 8 bits */
# define USART_CR1_M0_VALUE 0
# define USART_CR1_M1_VALUE 0
# endif
# if STM32_CONSOLE_PARITY == 1 /* odd parity */
# define USART_CR1_PARITY_VALUE (USART_CR1_PCE|USART_CR1_PS)
# elif STM32_CONSOLE_PARITY == 2 /* even parity */
# define USART_CR1_PARITY_VALUE USART_CR1_PCE
# else /* no parity */
# define USART_CR1_PARITY_VALUE 0
# endif
# if STM32_CONSOLE_BASE == STM32_LPUART1_BASE
# define USART_CR1_CLRBITS \
(USART_CR1_UE | USART_CR1_UESM | USART_CR1_RE | USART_CR1_TE | USART_CR1_PS | \
USART_CR1_PCE | USART_CR1_WAKE | USART_CR1_M0 | USART_CR1_M1 | \
USART_CR1_MME | USART_CR1_OVER8 | USART_CR1_DEDT_MASK | \
USART_CR1_DEAT_MASK | LPUART_CR1_ALLINTS)
# else
# define USART_CR1_CLRBITS \
(USART_CR1_UE | USART_CR1_UESM | USART_CR1_RE | USART_CR1_TE | USART_CR1_PS | \
USART_CR1_PCE | USART_CR1_WAKE | USART_CR1_M0 | USART_CR1_M1 | \
USART_CR1_MME | USART_CR1_OVER8 | USART_CR1_DEDT_MASK | \
USART_CR1_DEAT_MASK | USART_CR1_ALLINTS)
# endif
# define USART_CR1_SETBITS (USART_CR1_M0_VALUE|USART_CR1_M1_VALUE|USART_CR1_PARITY_VALUE)
/* CR2 settings */
# if STM32_CONSOLE_2STOP != 0
# define USART_CR2_STOP2_VALUE USART_CR2_STOP2
# else
# define USART_CR2_STOP2_VALUE 0
# endif
# define USART_CR2_CLRBITS \
(USART_CR2_ADDM7 | USART_CR2_LBDL | USART_CR2_LBDIE | USART_CR2_LBCL | \
USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_CLKEN | USART_CR2_STOP_MASK | \
USART_CR2_LINEN | USART_CR2_SWAP | USART_CR2_RXINV | USART_CR2_TXINV | \
USART_CR2_DATAINV | USART_CR2_MSBFIRST | USART_CR2_ABREN | \
USART_CR2_ABRMOD_MASK | USART_CR2_RTOEN | USART_CR2_ADD_MASK)
# define USART_CR2_SETBITS USART_CR2_STOP2_VALUE
/* CR3 settings */
# define USART_CR3_CLRBITS \
(USART_CR3_EIE | USART_CR3_IREN | USART_CR3_IRLP | USART_CR3_HDSEL | \
USART_CR3_NACK | USART_CR3_SCEN | USART_CR3_DMAR | USART_CR3_DMAT | \
USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_CTSIE | USART_CR3_ONEBIT | \
USART_CR3_OVRDIS | USART_CR3_DDRE | USART_CR3_DEM | USART_CR3_DEP | \
USART_CR3_SCARCNT2_MASK | USART_CR3_WUS_MASK | USART_CR3_WUFIE)
# define USART_CR3_SETBITS 0
# undef USE_OVER8
/* Calculate USART BAUD rate divider */
# if STM32_CONSOLE_BASE == STM32_LPUART1_BASE
/* BRR = (256 * (APBCLOCK / Prescaler)) / (Baud rate)
* With Prescaler == 16, BRR = (16 * APBCLOCK / (Baud rate)
* Set Prescaler to 16 to support wide range of standard baud rates
*/
# define STM32_BRR_VALUE \
(((STM32_APBCLOCK & 0xf0000000) / STM32_CONSOLE_BAUD) << 4) + \
(((STM32_APBCLOCK & 0x0fffffff) << 4) / STM32_CONSOLE_BAUD)
# define STM32_PRESC_VALUE 0x7
# else
/* Baud rate for standard USART (SPI mode included):
*
* In case of oversampling by 16, the equation is:
* baud = fCK / UARTDIV
* UARTDIV = fCK / baud
*
* In case of oversampling by 8, the equation is:
*
* baud = 2 * fCK / UARTDIV
* UARTDIV = 2 * fCK / baud
*/
# define STM32_USARTDIV8 \
(((STM32_APBCLOCK << 1) + (STM32_CONSOLE_BAUD >> 1)) / STM32_CONSOLE_BAUD)
# define STM32_USARTDIV16 \
((STM32_APBCLOCK + (STM32_CONSOLE_BAUD >> 1)) / STM32_CONSOLE_BAUD)
/* Use oversamply by 8 only if the divisor is small. But what is small? */
# if STM32_USARTDIV8 > 2000
# define STM32_BRR_VALUE STM32_USARTDIV16
# else
# define USE_OVER8 1
# define STM32_BRR_VALUE \
((STM32_USARTDIV8 & 0xfff0) | ((STM32_USARTDIV8 & 0x000f) >> 1))
# endif
# endif
#endif /* HAVE_CONSOLE */
/****************************************************************************
* Private Types
****************************************************************************/
/****************************************************************************
* Private Function Prototypes
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Private Variables
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: arm_lowputc
*
* Description:
* Output one byte on the serial console
*
****************************************************************************/
void arm_lowputc(char ch)
{
#ifdef HAVE_CONSOLE
/* Wait until the TX data register is empty */
while ((getreg32(STM32_CONSOLE_BASE + STM32_USART_ISR_OFFSET) &
USART_ISR_TXE) == 0);
#ifdef STM32_CONSOLE_RS485_DIR
stm32_gpiowrite(STM32_CONSOLE_RS485_DIR,
STM32_CONSOLE_RS485_DIR_POLARITY);
#endif
/* Then send the character */
putreg32((uint32_t)ch, STM32_CONSOLE_BASE + STM32_USART_TDR_OFFSET);
#ifdef STM32_CONSOLE_RS485_DIR
while ((getreg32(STM32_CONSOLE_BASE + STM32_USART_ISR_OFFSET) &
USART_ISR_TC) == 0);
stm32_gpiowrite(STM32_CONSOLE_RS485_DIR,
!STM32_CONSOLE_RS485_DIR_POLARITY);
#endif
#endif /* HAVE_CONSOLE */
}
/****************************************************************************
* Name: stm32_lowsetup
*
* Description:
* This performs basic initialization of the USART used for the serial
* console. Its purpose is to get the console output available as soon
* as possible.
*
****************************************************************************/
void stm32_lowsetup(void)
{
#if defined(HAVE_UART)
#if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG)
uint32_t cr;
#endif
#if defined(HAVE_CONSOLE)
/* Enable USART APB clock */
modifyreg32(STM32_CONSOLE_APBREG, 0, STM32_CONSOLE_APBEN);
#endif
/* Enable the console USART and configure GPIO pins needed for rx/tx.
*
* NOTE: Clocking for selected U[S]ARTs was already provided in
* stm32_rcc.c
*/
#ifdef STM32_CONSOLE_TX
stm32_configgpio(STM32_CONSOLE_TX);
#endif
#ifdef STM32_CONSOLE_RX
stm32_configgpio(STM32_CONSOLE_RX);
#endif
#ifdef STM32_CONSOLE_RS485_DIR
stm32_configgpio(STM32_CONSOLE_RS485_DIR);
stm32_gpiowrite(STM32_CONSOLE_RS485_DIR,
!STM32_CONSOLE_RS485_DIR_POLARITY);
#endif
/* Enable and configure the selected console device */
#if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG)
/* Configure CR2 */
cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR2_OFFSET);
cr &= ~USART_CR2_CLRBITS;
cr |= USART_CR2_SETBITS;
putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR2_OFFSET);
/* Configure CR1 */
cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET);
cr &= ~USART_CR1_CLRBITS;
cr |= USART_CR1_SETBITS;
putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET);
/* Configure CR3 */
cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR3_OFFSET);
cr &= ~USART_CR3_CLRBITS;
cr |= USART_CR3_SETBITS;
putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR3_OFFSET);
/* Configure the USART Baud Rate */
putreg32(STM32_BRR_VALUE,
STM32_CONSOLE_BASE + STM32_USART_BRR_OFFSET);
/* Select oversampling by 8 */
cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET);
#ifdef USE_OVER8
cr |= USART_CR1_OVER8;
putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET);
#endif
/* Enable Rx, Tx, and the USART */
cr |= (USART_CR1_UE | USART_CR1_TE | USART_CR1_RE);
putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET);
#endif /* HAVE_CONSOLE && !CONFIG_SUPPRESS_UART_CONFIG */
#endif /* HAVE_UART */
}

66
arch/arm/src/stm32h5/stm32_lowputc.h
View file

@ -1,66 +0,0 @@
/****************************************************************************
* arch/arm/src/stm32h5/stm32_lowputc.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32H5_STM32_LOWPUTC_H
#define __ARCH_ARM_SRC_STM32H5_STM32_LOWPUTC_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Name: stm32_lowsetup
*
* Description:
* Called at the very beginning of _start. Performs low level
* initialization of serial console.
*
****************************************************************************/
void stm32_lowsetup(void);
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_STM32H5_STM32_LOWPUTC_H */

248
arch/arm/src/stm32h5/stm32_rcc_m33.h
View file

@ -29,6 +29,8 @@
#include <nuttx/config.h>
#include <arch/board/board.h>
#include "arm_internal.h"
#include "chip.h"
@ -117,6 +119,252 @@ static inline void stm32_mco2config(uint32_t source, uint32_t div)
putreg32(regval, STM32_RCC_CFGR1);
}
/* USART clock and RCC definitions */
#define STM32_LPUART1_FREQUENCY STM32_PCLK3_FREQUENCY
#define STM32_LPUART1_RCC_REG STM32_RCC_APB3ENR
#define STM32_LPUART1_RCC_EN RCC_APB3ENR_LPUART1EN
#if !defined(STM32_RCC_CCIPR1_USART1SEL) || \
STM32_RCC_CCIPR1_USART1SEL == RCC_CCIPR1_USART1SEL_RCCPCLK2
# define STM32_USART1_FREQUENCY STM32_PCLK2_FREQUENCY
#elif STM32_RCC_CCIPR1_USART1SEL == RCC_CCIPR1_USART1SEL_PLL2QCK
# define STM32_USART1_FREQUENCY STM32_PLL2Q_FREQUENCY
#elif STM32_RCC_CCIPR1_USART1SEL == RCC_CCIPR1_USART1SEL_PLL3QCK
# define STM32_USART1_FREQUENCY STM32_PLL3Q_FREQUENCY
#elif STM32_RCC_CCIPR1_USART1SEL == RCC_CCIPR1_USART1SEL_HSIKERCK
# define STM32_USART1_FREQUENCY STM32_HSI_FREQUENCY
#elif STM32_RCC_CCIPR1_USART1SEL == RCC_CCIPR1_USART1SEL_CSIKERCK
# define STM32_USART1_FREQUENCY STM32_CSI_FREQUENCY
#elif STM32_RCC_CCIPR1_USART1SEL == RCC_CCIPR1_USART1SEL_LSECK
# define STM32_USART1_FREQUENCY STM32_LSE_FREQUENCY
#else
# error "Unsupported USART1 Clock Selection"
#endif
#define STM32_USART1_RCC_REG STM32_RCC_APB2ENR
#define STM32_USART1_RCC_EN RCC_APB2ENR_USART1EN
#if !defined(STM32_RCC_CCIPR1_USART2SEL) || \
STM32_RCC_CCIPR1_USART2SEL == RCC_CCIPR1_USART2SEL_RCCPCLK1
# define STM32_USART2_FREQUENCY STM32_PCLK1_FREQUENCY
#elif STM32_RCC_CCIPR1_USART2SEL == RCC_CCIPR1_USART2SEL_PLL2QCK
# define STM32_USART2_FREQUENCY STM32_PLL2Q_FREQUENCY
#elif STM32_RCC_CCIPR1_USART2SEL == RCC_CCIPR1_USART2SEL_PLL3QCK
# define STM32_USART2_FREQUENCY STM32_PLL3Q_FREQUENCY
#elif STM32_RCC_CCIPR1_USART2SEL == RCC_CCIPR1_USART2SEL_HSIKERCK
# define STM32_USART2_FREQUENCY STM32_HSI_FREQUENCY
#elif STM32_RCC_CCIPR1_USART2SEL == RCC_CCIPR1_USART2SEL_CSIKERCK
# define STM32_USART2_FREQUENCY STM32_CSI_FREQUENCY
#elif STM32_RCC_CCIPR1_USART2SEL == RCC_CCIPR1_USART2SEL_LSECK
# define STM32_USART2_FREQUENCY STM32_LSE_FREQUENCY
#else
# error "Unsupported USART2 Clock Selection"
#endif
#define STM32_USART2_RCC_REG STM32_RCC_APB1LENR
#define STM32_USART2_RCC_EN RCC_APB1LENR_USART2EN
#if !defined(STM32_RCC_CCIPR1_USART3SEL) || \
STM32_RCC_CCIPR1_USART3SEL == RCC_CCIPR1_USART3SEL_RCCPCLK1
# define STM32_USART3_FREQUENCY STM32_PCLK1_FREQUENCY
#elif STM32_RCC_CCIPR1_USART3SEL == RCC_CCIPR1_USART3SEL_PLL2QCK
# define STM32_USART3_FREQUENCY STM32_PLL2Q_FREQUENCY
#elif STM32_RCC_CCIPR1_USART3SEL == RCC_CCIPR1_USART3SEL_PLL3QCK
# define STM32_USART3_FREQUENCY STM32_PLL3Q_FREQUENCY
#elif STM32_RCC_CCIPR1_USART3SEL == RCC_CCIPR1_USART3SEL_HSIKERCK
# define STM32_USART3_FREQUENCY STM32_HSI_FREQUENCY
#elif STM32_RCC_CCIPR1_USART3SEL == RCC_CCIPR1_USART3SEL_CSIKERCK
# define STM32_USART3_FREQUENCY STM32_CSI_FREQUENCY
#elif STM32_RCC_CCIPR1_USART3SEL == RCC_CCIPR1_USART3SEL_LSECK
# define STM32_USART3_FREQUENCY STM32_LSE_FREQUENCY
#else
# error "Unsupported USART3 Clock Selection"
#endif
#define STM32_USART3_RCC_REG STM32_RCC_APB1LENR
#define STM32_USART3_RCC_EN RCC_APB1LENR_USART3EN
#if !defined(STM32_RCC_CCIPR1_UART4SEL) || \
STM32_RCC_CCIPR1_UART4SEL == RCC_CCIPR1_UART4SEL_RCCPCLK1
# define STM32_UART4_FREQUENCY STM32_PCLK1_FREQUENCY
#elif STM32_RCC_CCIPR1_UART4SEL == RCC_CCIPR1_UART4SEL_PLL2QCK
# define STM32_UART4_FREQUENCY STM32_PLL2Q_FREQUENCY
#elif STM32_RCC_CCIPR1_UART4SEL == RCC_CCIPR1_UART4SEL_PLL3QCK
# define STM32_UART4_FREQUENCY STM32_PLL3Q_FREQUENCY
#elif STM32_RCC_CCIPR1_UART4SEL == RCC_CCIPR1_UART4SEL_HSIKERCK
# define STM32_UART4_FREQUENCY STM32_HSI_FREQUENCY
#elif STM32_RCC_CCIPR1_UART4SEL == RCC_CCIPR1_UART4SEL_CSIKERCK
# define STM32_UART4_FREQUENCY STM32_CSI_FREQUENCY
#elif STM32_RCC_CCIPR1_UART4SEL == RCC_CCIPR1_UART4SEL_LSECK
# define STM32_UART4_FREQUENCY STM32_LSE_FREQUENCY
#else
# error "Unsupported UART4 Clock Selection"
#endif
#define STM32_UART4_RCC_REG STM32_RCC_APB1LENR
#define STM32_UART4_RCC_EN RCC_APB1LENR_UART4EN
#if !defined(STM32_RCC_CCIPR1_UART5SEL) || \
STM32_RCC_CCIPR1_UART5SEL == RCC_CCIPR1_UART5SEL_RCCPCLK1
# define STM32_UART5_FREQUENCY STM32_PCLK1_FREQUENCY
#elif STM32_RCC_CCIPR1_UART5SEL == RCC_CCIPR1_UART5SEL_PLL2QCK
# define STM32_UART5_FREQUENCY STM32_PLL2Q_FREQUENCY
#elif STM32_RCC_CCIPR1_UART5SEL == RCC_CCIPR1_UART5SEL_PLL3QCK
# define STM32_UART5_FREQUENCY STM32_PLL3Q_FREQUENCY
#elif STM32_RCC_CCIPR1_UART5SEL == RCC_CCIPR1_UART5SEL_HSIKERCK
# define STM32_UART5_FREQUENCY STM32_HSI_FREQUENCY
#elif STM32_RCC_CCIPR1_UART5SEL == RCC_CCIPR1_UART5SEL_CSIKERCK
# define STM32_UART5_FREQUENCY STM32_CSI_FREQUENCY
#elif STM32_RCC_CCIPR1_UART5SEL == RCC_CCIPR1_UART5SEL_LSECK
# define STM32_UART5_FREQUENCY STM32_LSE_FREQUENCY
#else
# error "Unsupported UART5 Clock Selection"
#endif
#define STM32_UART5_RCC_REG STM32_RCC_APB1LENR
#define STM32_UART5_RCC_EN RCC_APB1LENR_UART5EN
#if !defined(STM32_RCC_CCIPR1_USART6SEL) || \
STM32_RCC_CCIPR1_USART6SEL == RCC_CCIPR1_USART6SEL_RCCPCLK1
# define STM32_USART6_FREQUENCY STM32_PCLK1_FREQUENCY
#elif STM32_RCC_CCIPR1_USART6SEL == RCC_CCIPR1_USART6SEL_PLL2QCK
# define STM32_USART6_FREQUENCY STM32_PLL2Q_FREQUENCY
#elif STM32_RCC_CCIPR1_USART6SEL == RCC_CCIPR1_USART6SEL_PLL3QCK
# define STM32_USART6_FREQUENCY STM32_PLL3Q_FREQUENCY
#elif STM32_RCC_CCIPR1_USART6SEL == RCC_CCIPR1_USART6SEL_HSIKERCK
# define STM32_USART6_FREQUENCY STM32_HSI_FREQUENCY
#elif STM32_RCC_CCIPR1_USART6SEL == RCC_CCIPR1_USART6SEL_CSIKERCK
# define STM32_USART6_FREQUENCY STM32_CSI_FREQUENCY
#elif STM32_RCC_CCIPR1_USART6SEL == RCC_CCIPR1_USART6SEL_LSECK
# define STM32_USART6_FREQUENCY STM32_LSE_FREQUENCY
#else
# error "Unsupported USART6 Clock Selection"
#endif
#define STM32_USART6_RCC_REG STM32_RCC_APB1LENR
#define STM32_USART6_RCC_EN RCC_APB1LENR_USART6EN
#if !defined(STM32_RCC_CCIPR1_UART7SEL) || \
STM32_RCC_CCIPR1_UART7SEL == RCC_CCIPR1_UART7SEL_RCCPCLK1
# define STM32_UART7_FREQUENCY STM32_PCLK1_FREQUENCY
#elif STM32_RCC_CCIPR1_UART7SEL == RCC_CCIPR1_UART7SEL_PLL2QCK
# define STM32_UART7_FREQUENCY STM32_PLL2Q_FREQUENCY
#elif STM32_RCC_CCIPR1_UART7SEL == RCC_CCIPR1_UART7SEL_PLL3QCK
# define STM32_UART7_FREQUENCY STM32_PLL3Q_FREQUENCY
#elif STM32_RCC_CCIPR1_UART7SEL == RCC_CCIPR1_UART7SEL_HSIKERCK
# define STM32_UART7_FREQUENCY STM32_HSI_FREQUENCY
#elif STM32_RCC_CCIPR1_UART7SEL == RCC_CCIPR1_UART7SEL_CSIKERCK
# define STM32_UART7_FREQUENCY STM32_CSI_FREQUENCY
#elif STM32_RCC_CCIPR1_UART7SEL == RCC_CCIPR1_UART7SEL_LSECK
# define STM32_UART7_FREQUENCY STM32_LSE_FREQUENCY
#else
# error "Unsupported UART7 Clock Selection"
#endif
#define STM32_UART7_RCC_REG STM32_RCC_APB1LENR
#define STM32_UART7_RCC_EN RCC_APB1LENR_UART7EN
#if !defined(STM32_RCC_CCIPR1_UART8SEL) || \
STM32_RCC_CCIPR1_UART8SEL == RCC_CCIPR1_UART8SEL_RCCPCLK1
# define STM32_UART8_FREQUENCY STM32_PCLK1_FREQUENCY
#elif STM32_RCC_CCIPR1_UART8SEL == RCC_CCIPR1_UART8SEL_PLL2QCK
# define STM32_UART8_FREQUENCY STM32_PLL2Q_FREQUENCY
#elif STM32_RCC_CCIPR1_UART8SEL == RCC_CCIPR1_UART8SEL_PLL3QCK
# define STM32_UART8_FREQUENCY STM32_PLL3Q_FREQUENCY
#elif STM32_RCC_CCIPR1_UART8SEL == RCC_CCIPR1_UART8SEL_HSIKERCK
# define STM32_UART8_FREQUENCY STM32_HSI_FREQUENCY
#elif STM32_RCC_CCIPR1_UART8SEL == RCC_CCIPR1_UART8SEL_CSIKERCK
# define STM32_UART8_FREQUENCY STM32_CSI_FREQUENCY
#elif STM32_RCC_CCIPR1_UART8SEL == RCC_CCIPR1_UART8SEL_LSECK
# define STM32_UART8_FREQUENCY STM32_LSE_FREQUENCY
#else
# error "Unsupported UART8 Clock Selection"
#endif
#define STM32_UART8_RCC_REG STM32_RCC_APB1LENR
#define STM32_UART8_RCC_EN RCC_APB1LENR_UART8EN
#if !defined(STM32_RCC_CCIPR1_UART9SEL) || \
STM32_RCC_CCIPR1_UART9SEL == RCC_CCIPR1_UART9SEL_RCCPCLK1
# define STM32_UART9_FREQUENCY STM32_PCLK1_FREQUENCY
#elif STM32_RCC_CCIPR1_UART9SEL == RCC_CCIPR1_UART9SEL_PLL2QCK
# define STM32_UART9_FREQUENCY STM32_PLL2Q_FREQUENCY
#elif STM32_RCC_CCIPR1_UART9SEL == RCC_CCIPR1_UART9SEL_PLL3QCK
# define STM32_UART9_FREQUENCY STM32_PLL3Q_FREQUENCY
#elif STM32_RCC_CCIPR1_UART9SEL == RCC_CCIPR1_UART9SEL_HSIKERCK
# define STM32_UART9_FREQUENCY STM32_HSI_FREQUENCY
#elif STM32_RCC_CCIPR1_UART9SEL == RCC_CCIPR1_UART9SEL_CSIKERCK
# define STM32_UART9_FREQUENCY STM32_CSI_FREQUENCY
#elif STM32_RCC_CCIPR1_UART9SEL == RCC_CCIPR1_UART9SEL_LSECK
# define STM32_UART9_FREQUENCY STM32_LSE_FREQUENCY
#else
# error "Unsupported UART9 Clock Selection"
#endif
#define STM32_UART9_RCC_REG STM32_RCC_APB1HENR
#define STM32_UART9_RCC_EN RCC_APB1HENR_UART9EN
#if !defined(STM32_RCC_CCIPR1_USART10SEL) || \
STM32_RCC_CCIPR1_USART10SEL == RCC_CCIPR1_USART10SEL_RCCPCLK1
# define STM32_USART10_FREQUENCY STM32_PCLK1_FREQUENCY
#elif STM32_RCC_CCIPR1_USART10SEL == RCC_CCIPR1_USART10SEL_PLL2QCK
# define STM32_USART10_FREQUENCY STM32_PLL2Q_FREQUENCY
#elif STM32_RCC_CCIPR1_USART10SEL == RCC_CCIPR1_USART10SEL_PLL3QCK
# define STM32_USART10_FREQUENCY STM32_PLL3Q_FREQUENCY
#elif STM32_RCC_CCIPR1_USART10SEL == RCC_CCIPR1_USART10SEL_HSIKERCK
# define STM32_USART10_FREQUENCY STM32_HSI_FREQUENCY
#elif STM32_RCC_CCIPR1_USART10SEL == RCC_CCIPR1_USART10SEL_CSIKERCK
# define STM32_USART10_FREQUENCY STM32_CSI_FREQUENCY
#elif STM32_RCC_CCIPR1_USART10SEL == RCC_CCIPR1_USART10SEL_LSECK
# define STM32_USART10_FREQUENCY STM32_LSE_FREQUENCY
#else
# error "Unsupported USART10 Clock Selection"
#endif
#define STM32_USART10_RCC_REG STM32_RCC_APB1LENR
#define STM32_USART10_RCC_EN RCC_APB1LENR_USART10EN
#if !defined(STM32_RCC_CCIPR2_USART11SEL) || \
STM32_RCC_CCIPR2_USART11SEL == RCC_CCIPR2_USART11SEL_RCCPCLK1
# define STM32_USART11_FREQUENCY STM32_PCLK1_FREQUENCY
#elif STM32_RCC_CCIPR2_USART11SEL == RCC_CCIPR2_USART11SEL_PLL2QCK
# define STM32_USART11_FREQUENCY STM32_PLL2Q_FREQUENCY
#elif STM32_RCC_CCIPR2_USART11SEL == RCC_CCIPR2_USART11SEL_PLL3QCK
# define STM32_USART11_FREQUENCY STM32_PLL3Q_FREQUENCY
#elif STM32_RCC_CCIPR2_USART11SEL == RCC_CCIPR2_USART11SEL_HSIKERCK
# define STM32_USART11_FREQUENCY STM32_HSI_FREQUENCY
#elif STM32_RCC_CCIPR2_USART11SEL == RCC_CCIPR2_USART11SEL_CSIKERCK
# define STM32_USART11_FREQUENCY STM32_CSI_FREQUENCY
#elif STM32_RCC_CCIPR2_USART11SEL == RCC_CCIPR2_USART11SEL_LSECK
# define STM32_USART11_FREQUENCY STM32_LSE_FREQUENCY
#else
# error "Unsupported USART11 Clock Selection"
#endif
#define STM32_USART11_RCC_REG STM32_RCC_APB1LENR
#define STM32_USART11_RCC_EN RCC_APB1LENR_USART11EN
#if !defined(STM32_RCC_CCIPR2_UART12SEL) || \
STM32_RCC_CCIPR2_UART12SEL == RCC_CCIPR2_UART12SEL_RCCPCLK1
# define STM32_UART12_FREQUENCY STM32_PCLK1_FREQUENCY
#elif STM32_RCC_CCIPR2_UART12SEL == RCC_CCIPR2_UART12SEL_PLL2QCK
# define STM32_UART12_FREQUENCY STM32_PLL2Q_FREQUENCY
#elif STM32_RCC_CCIPR2_UART12SEL == RCC_CCIPR2_UART12SEL_PLL3QCK
# define STM32_UART12_FREQUENCY STM32_PLL3Q_FREQUENCY
#elif STM32_RCC_CCIPR2_UART12SEL == RCC_CCIPR2_UART12SEL_HSIKERCK
# define STM32_UART12_FREQUENCY STM32_HSI_FREQUENCY
#elif STM32_RCC_CCIPR2_UART12SEL == RCC_CCIPR2_UART12SEL_CSIKERCK
# define STM32_UART12_FREQUENCY STM32_CSI_FREQUENCY
#elif STM32_RCC_CCIPR2_UART12SEL == RCC_CCIPR2_UART12SEL_LSECK
# define STM32_UART12_FREQUENCY STM32_LSE_FREQUENCY
#else
# error "Unsupported UART12 Clock Selection"
#endif
#define STM32_UART12_RCC_REG STM32_RCC_APB1HENR
#define STM32_UART12_RCC_EN RCC_APB1HENR_UART12EN
/****************************************************************************
* Public Function Prototypes
****************************************************************************/

4481
arch/arm/src/stm32h5/stm32_serial.c
View file

File diff suppressed because it is too large Load diff

575
arch/arm/src/stm32h5/stm32_uart.h
View file

@ -1,575 +0,0 @@
/****************************************************************************
* arch/arm/src/stm32h5/stm32_uart.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_STC_STM32H5_STM32_UART_H
#define __ARCH_ARM_STC_STM32H5_STM32_UART_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/serial/serial.h>
#include "chip.h"
#if defined(CONFIG_STM32_STM32H5XXXX)
# include "hardware/stm32_uart.h"
#else
# error "Unsupported STM32H5 chip"
#endif
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Make sure that we have not enabled more U[S]ARTs than are supported by the
* device.
*/
#if !defined(CONFIG_STM32_HAVE_UART12)
# undef CONFIG_STM32_UART12
#endif
#if !defined(CONFIG_STM32_HAVE_USART11)
# undef CONFIG_STM32_USART11
#endif
#if !defined(CONFIG_STM32_HAVE_USART10)
# undef CONFIG_STM32_USART10
#endif
#if !defined(CONFIG_STM32_HAVE_UART9)
# undef CONFIG_STM32_UART9
#endif
#if !defined(CONFIG_STM32_HAVE_UART8)
# undef CONFIG_STM32_UART8
#endif
#if !defined(CONFIG_STM32_HAVE_UART7)
# undef CONFIG_STM32_UART7
#endif
#if !defined(CONFIG_STM32_HAVE_USART6)
# undef CONFIG_STM32_USART6
#endif
#if !defined(CONFIG_STM32_HAVE_UART5)
# undef CONFIG_STM32_UART5
#endif
#if !defined(CONFIG_STM32_HAVE_UART4)
# undef CONFIG_STM32_UART4
#endif
#if !defined(CONFIG_STM32_HAVE_USART3)
# undef CONFIG_STM32_USART3
#endif
#if !defined(CONFIG_STM32_HAVE_USART2)
# undef CONFIG_STM32_USART2
#endif
#if !defined(CONFIG_STM32_HAVE_USART1)
# undef CONFIG_STM32_USART1
#endif
#if !defined(CONFIG_STM32_HAVE_LPUART1)
# undef CONFIG_STM32_LPUART1
#endif
/* Sanity checks */
#if !defined(CONFIG_STM32_LPUART1)
# undef CONFIG_STM32_LPUART1_SERIALDRIVER
# undef CONFIG_STM32_LPUART1_1WIREDRIVER
#endif
#if !defined(CONFIG_STM32_USART1)
# undef CONFIG_STM32_USART1_SERIALDRIVER
# undef CONFIG_STM32_USART1_1WIREDRIVER
#endif
#if !defined(CONFIG_STM32_USART2)
# undef CONFIG_STM32_USART2_SERIALDRIVER
# undef CONFIG_STM32_USART2_1WIREDRIVER
#endif
#if !defined(CONFIG_STM32_USART3)
# undef CONFIG_STM32_USART3_SERIALDRIVER
# undef CONFIG_STM32_USART3_1WIREDRIVER
#endif
#if !defined(CONFIG_STM32_UART4)
# undef CONFIG_STM32_UART4_SERIALDRIVER
# undef CONFIG_STM32_UART4_1WIREDRIVER
#endif
#if !defined(CONFIG_STM32_UART5)
# undef CONFIG_STM32_UART5_SERIALDRIVER
# undef CONFIG_STM32_UART5_1WIREDRIVER
#endif
#if !defined(CONFIG_STM32_USART6)
# undef CONFIG_STM32_USART6_SERIALDRIVER
# undef CONFIG_STM32_USART6_1WIREDRIVER
#endif
#if !defined(CONFIG_STM32_UART7)
# undef CONFIG_STM32_UART7_SERIALDRIVER
# undef CONFIG_STM32_UART7_1WIREDRIVER
#endif
#if !defined(CONFIG_STM32_UART8)
# undef CONFIG_STM32_UART8_SERIALDRIVER
# undef CONFIG_STM32_UART8_1WIREDRIVER
#endif
#if !defined(CONFIG_STM32_UART9)
# undef CONFIG_STM32_UART9_SERIALDRIVER
# undef CONFIG_STM32_UART9_1WIREDRIVER
#endif
#if !defined(CONFIG_STM32_USART10)
# undef CONFIG_STM32_USART10_SERIALDRIVER
# undef CONFIG_STM32_USART10_1WIREDRIVER
#endif
#if !defined(CONFIG_STM32_USART11)
# undef CONFIG_STM32_USART11_SERIALDRIVER
# undef CONFIG_STM32_USART11_1WIREDRIVER
#endif
#if !defined(CONFIG_STM32_UART12)
# undef CONFIG_STM32_UART12_SERIALDRIVER
# undef CONFIG_STM32_UART12_1WIREDRIVER
#endif
/* Is there a USART enabled? */
#if defined(CONFIG_STM32_LPUART1) || defined(CONFIG_STM32_USART1) || \
defined(CONFIG_STM32_USART2) || defined(CONFIG_STM32_USART3) || \
defined(CONFIG_STM32_UART4) || defined(CONFIG_STM32_UART5) || \
defined(CONFIG_STM32_USART6) || defined(CONFIG_STM32_UART7) || \
defined(CONFIG_STM32_UART8) || defined(CONFIG_STM32_UART9) || \
defined(CONFIG_STM32_USART10) || defined(CONFIG_STM32_USART11) || \
defined(CONFIG_STM32_USART12)
# define HAVE_UART 1
#endif
/* Is there a serial console? */
#if defined(CONFIG_LPUART1_SERIAL_CONSOLE) && defined(CONFIG_STM32_LPUART1_SERIALDRIVER)
# undef CONFIG_USART1_SERIAL_CONSOLE
# undef CONFIG_USART2_SERIAL_CONSOLE
# undef CONFIG_USART3_SERIAL_CONSOLE
# undef CONFIG_UART4_SERIAL_CONSOLE
# undef CONFIG_UART5_SERIAL_CONSOLE
# undef CONFIG_USART6_SERIAL_CONSOLE
# undef CONFIG_UART7_SERIAL_CONSOLE
# undef CONFIG_UART8_SERIAL_CONSOLE
# undef CONFIG_UART9_SERIAL_CONSOLE
# undef CONFIG_USART10_SERIAL_CONSOLE
# undef CONFIG_USART11_SERIAL_CONSOLE
# undef CONFIG_UART12_SERIAL_CONSOLE
# define CONSOLE_UART 1
# define HAVE_CONSOLE 1
#elif defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART1_SERIALDRIVER)
# undef CONFIG_LPUART1_SERIAL_CONSOLE
# undef CONFIG_USART2_SERIAL_CONSOLE
# undef CONFIG_USART3_SERIAL_CONSOLE
# undef CONFIG_UART4_SERIAL_CONSOLE
# undef CONFIG_UART5_SERIAL_CONSOLE
# undef CONFIG_USART6_SERIAL_CONSOLE
# undef CONFIG_UART7_SERIAL_CONSOLE
# undef CONFIG_UART8_SERIAL_CONSOLE
# undef CONFIG_UART9_SERIAL_CONSOLE
# undef CONFIG_USART10_SERIAL_CONSOLE
# undef CONFIG_USART11_SERIAL_CONSOLE
# undef CONFIG_UART12_SERIAL_CONSOLE
# define CONSOLE_UART 2
# define HAVE_CONSOLE 1
#elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART2_SERIALDRIVER)
# undef CONFIG_LPUART1_SERIAL_CONSOLE
# undef CONFIG_USART1_SERIAL_CONSOLE
# undef CONFIG_USART3_SERIAL_CONSOLE
# undef CONFIG_UART4_SERIAL_CONSOLE
# undef CONFIG_UART5_SERIAL_CONSOLE
# undef CONFIG_USART6_SERIAL_CONSOLE
# undef CONFIG_UART7_SERIAL_CONSOLE
# undef CONFIG_UART8_SERIAL_CONSOLE
# undef CONFIG_UART9_SERIAL_CONSOLE
# undef CONFIG_USART10_SERIAL_CONSOLE
# undef CONFIG_USART11_SERIAL_CONSOLE
# undef CONFIG_UART12_SERIAL_CONSOLE
# define CONSOLE_UART 3
# define HAVE_CONSOLE 1
#elif defined(CONFIG_USART3_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART3_SERIALDRIVER)
# undef CONFIG_LPUART1_SERIAL_CONSOLE
# undef CONFIG_USART1_SERIAL_CONSOLE
# undef CONFIG_USART2_SERIAL_CONSOLE
# undef CONFIG_UART4_SERIAL_CONSOLE
# undef CONFIG_UART5_SERIAL_CONSOLE
# undef CONFIG_USART6_SERIAL_CONSOLE
# undef CONFIG_UART7_SERIAL_CONSOLE
# undef CONFIG_UART8_SERIAL_CONSOLE
# undef CONFIG_UART9_SERIAL_CONSOLE
# undef CONFIG_USART10_SERIAL_CONSOLE
# undef CONFIG_USART11_SERIAL_CONSOLE
# undef CONFIG_UART12_SERIAL_CONSOLE
# define CONSOLE_UART 4
# define HAVE_CONSOLE 1
#elif defined(CONFIG_UART4_SERIAL_CONSOLE) && defined(CONFIG_STM32_UART4_SERIALDRIVER)
# undef CONFIG_LPUART1_SERIAL_CONSOLE
# undef CONFIG_USART1_SERIAL_CONSOLE
# undef CONFIG_USART2_SERIAL_CONSOLE
# undef CONFIG_USART3_SERIAL_CONSOLE
# undef CONFIG_UART5_SERIAL_CONSOLE
# undef CONFIG_USART6_SERIAL_CONSOLE
# undef CONFIG_UART7_SERIAL_CONSOLE
# undef CONFIG_UART8_SERIAL_CONSOLE
# undef CONFIG_UART9_SERIAL_CONSOLE
# undef CONFIG_USART10_SERIAL_CONSOLE
# undef CONFIG_USART11_SERIAL_CONSOLE
# undef CONFIG_UART12_SERIAL_CONSOLE
# define CONSOLE_UART 5
# define HAVE_CONSOLE 1
#elif defined(CONFIG_UART5_SERIAL_CONSOLE) && defined(CONFIG_STM32_UART5_SERIALDRIVER)
# undef CONFIG_LPUART1_SERIAL_CONSOLE
# undef CONFIG_USART1_SERIAL_CONSOLE
# undef CONFIG_USART2_SERIAL_CONSOLE
# undef CONFIG_USART3_SERIAL_CONSOLE
# undef CONFIG_UART4_SERIAL_CONSOLE
# undef CONFIG_USART6_SERIAL_CONSOLE
# undef CONFIG_UART7_SERIAL_CONSOLE
# undef CONFIG_UART8_SERIAL_CONSOLE
# undef CONFIG_UART9_SERIAL_CONSOLE
# undef CONFIG_USART10_SERIAL_CONSOLE
# undef CONFIG_USART11_SERIAL_CONSOLE
# undef CONFIG_UART12_SERIAL_CONSOLE
# define CONSOLE_UART 6
# define HAVE_CONSOLE 1
#elif defined(CONFIG_USART6_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART6_SERIALDRIVER)
# undef CONFIG_LPUART1_SERIAL_CONSOLE
# undef CONFIG_USART1_SERIAL_CONSOLE
# undef CONFIG_USART2_SERIAL_CONSOLE
# undef CONFIG_USART3_SERIAL_CONSOLE
# undef CONFIG_UART4_SERIAL_CONSOLE
# undef CONFIG_UART5_SERIAL_CONSOLE
# undef CONFIG_UART7_SERIAL_CONSOLE
# undef CONFIG_UART8_SERIAL_CONSOLE
# undef CONFIG_UART9_SERIAL_CONSOLE
# undef CONFIG_USART10_SERIAL_CONSOLE
# undef CONFIG_USART11_SERIAL_CONSOLE
# undef CONFIG_UART12_SERIAL_CONSOLE
# define CONSOLE_UART 7
# define HAVE_CONSOLE 1
#elif defined(CONFIG_UART7_SERIAL_CONSOLE) && defined(CONFIG_STM32_UART7_SERIALDRIVER)
# undef CONFIG_LPUART1_SERIAL_CONSOLE
# undef CONFIG_USART1_SERIAL_CONSOLE
# undef CONFIG_USART2_SERIAL_CONSOLE
# undef CONFIG_USART3_SERIAL_CONSOLE
# undef CONFIG_UART4_SERIAL_CONSOLE
# undef CONFIG_UART5_SERIAL_CONSOLE
# undef CONFIG_USART6_SERIAL_CONSOLE
# undef CONFIG_UART8_SERIAL_CONSOLE
# undef CONFIG_UART9_SERIAL_CONSOLE
# undef CONFIG_USART10_SERIAL_CONSOLE
# undef CONFIG_USART11_SERIAL_CONSOLE
# undef CONFIG_UART12_SERIAL_CONSOLE
# define CONSOLE_UART 8
# define HAVE_CONSOLE 1
#elif defined(CONFIG_UART8_SERIAL_CONSOLE) && defined(CONFIG_STM32_UART8_SERIALDRIVER)
# undef CONFIG_LPUART1_SERIAL_CONSOLE
# undef CONFIG_USART1_SERIAL_CONSOLE
# undef CONFIG_USART2_SERIAL_CONSOLE
# undef CONFIG_USART3_SERIAL_CONSOLE
# undef CONFIG_UART4_SERIAL_CONSOLE
# undef CONFIG_UART5_SERIAL_CONSOLE
# undef CONFIG_USART6_SERIAL_CONSOLE
# undef CONFIG_UART7_SERIAL_CONSOLE
# undef CONFIG_UART9_SERIAL_CONSOLE
# undef CONFIG_USART10_SERIAL_CONSOLE
# undef CONFIG_USART11_SERIAL_CONSOLE
# undef CONFIG_UART12_SERIAL_CONSOLE
# define CONSOLE_UART 9
# define HAVE_CONSOLE 1
#elif defined(CONFIG_UART9_SERIAL_CONSOLE) && defined(CONFIG_STM32_UART9_SERIALDRIVER)
# undef CONFIG_LPUART1_SERIAL_CONSOLE
# undef CONFIG_USART1_SERIAL_CONSOLE
# undef CONFIG_USART2_SERIAL_CONSOLE
# undef CONFIG_USART3_SERIAL_CONSOLE
# undef CONFIG_UART4_SERIAL_CONSOLE
# undef CONFIG_UART5_SERIAL_CONSOLE
# undef CONFIG_USART6_SERIAL_CONSOLE
# undef CONFIG_UART7_SERIAL_CONSOLE
# undef CONFIG_UART8_SERIAL_CONSOLE
# undef CONFIG_USART10_SERIAL_CONSOLE
# undef CONFIG_USART11_SERIAL_CONSOLE
# undef CONFIG_UART12_SERIAL_CONSOLE
# define CONSOLE_UART 10
# define HAVE_CONSOLE 1
#elif defined(CONFIG_USART10_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART10_SERIALDRIVER)
# undef CONFIG_LPUART1_SERIAL_CONSOLE
# undef CONFIG_USART1_SERIAL_CONSOLE
# undef CONFIG_USART2_SERIAL_CONSOLE
# undef CONFIG_USART3_SERIAL_CONSOLE
# undef CONFIG_UART4_SERIAL_CONSOLE
# undef CONFIG_UART5_SERIAL_CONSOLE
# undef CONFIG_USART6_SERIAL_CONSOLE
# undef CONFIG_UART7_SERIAL_CONSOLE
# undef CONFIG_UART8_SERIAL_CONSOLE
# undef CONFIG_UART9_SERIAL_CONSOLE
# undef CONFIG_USART11_SERIAL_CONSOLE
# undef CONFIG_UART12_SERIAL_CONSOLE
# define CONSOLE_UART 11
# define HAVE_CONSOLE 1
#elif defined(CONFIG_USART11_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART11_SERIALDRIVER)
# undef CONFIG_LPUART1_SERIAL_CONSOLE
# undef CONFIG_USART1_SERIAL_CONSOLE
# undef CONFIG_USART2_SERIAL_CONSOLE
# undef CONFIG_USART3_SERIAL_CONSOLE
# undef CONFIG_UART4_SERIAL_CONSOLE
# undef CONFIG_UART5_SERIAL_CONSOLE
# undef CONFIG_USART6_SERIAL_CONSOLE
# undef CONFIG_UART7_SERIAL_CONSOLE
# undef CONFIG_UART8_SERIAL_CONSOLE
# undef CONFIG_UART9_SERIAL_CONSOLE
# undef CONFIG_USART10_SERIAL_CONSOLE
# undef CONFIG_UART12_SERIAL_CONSOLE
# define CONSOLE_UART 12
# define HAVE_CONSOLE 1
#elif defined(CONFIG_UART12_SERIAL_CONSOLE) && defined(CONFIG_STM32_UART12_SERIALDRIVER)
# undef CONFIG_LPUART1_SERIAL_CONSOLE
# undef CONFIG_USART1_SERIAL_CONSOLE
# undef CONFIG_USART2_SERIAL_CONSOLE
# undef CONFIG_USART3_SERIAL_CONSOLE
# undef CONFIG_UART4_SERIAL_CONSOLE
# undef CONFIG_UART5_SERIAL_CONSOLE
# undef CONFIG_USART6_SERIAL_CONSOLE
# undef CONFIG_UART7_SERIAL_CONSOLE
# undef CONFIG_UART8_SERIAL_CONSOLE
# undef CONFIG_UART9_SERIAL_CONSOLE
# undef CONFIG_USART10_SERIAL_CONSOLE
# undef CONFIG_USART11_SERIAL_CONSOLE
# define CONSOLE_UART 13
# define HAVE_CONSOLE 1
#else
# undef CONFIG_USART1_SERIAL_CONSOLE
# undef CONFIG_USART2_SERIAL_CONSOLE
# undef CONFIG_USART3_SERIAL_CONSOLE
# undef CONFIG_UART4_SERIAL_CONSOLE
# undef CONFIG_UART5_SERIAL_CONSOLE
# define CONSOLE_UART 0
# undef HAVE_CONSOLE
#endif
/* DMA support is only provided if CONFIG_ARCH_DMA is in the NuttX
* configuration
*/
#if !defined(HAVE_UART) || !defined(CONFIG_ARCH_DMA)
# undef CONFIG_USART1_RXDMA
# undef CONFIG_USART2_RXDMA
# undef CONFIG_USART3_RXDMA
# undef CONFIG_UART4_RXDMA
# undef CONFIG_UART5_RXDMA
# undef CONFIG_USART7_RXDMA
# undef CONFIG_UART7_RXDMA
# undef CONFIG_UART8_RXDMA
# undef CONFIG_UART9_RXDMA
# undef CONFIG_USART10_RXDMA
# undef CONFIG_USART11_RXDMA
# undef CONFIG_UART12_RXDMA
#endif
/* Disable the DMA configuration on all unused USARTs */
#ifndef CONFIG_STM32_LPUART1_SERIALDRIVER
# undef CONFIG_LPUART1_RXDMA
#endif
#ifndef CONFIG_STM32_USART1_SERIALDRIVER
# undef CONFIG_USART1_RXDMA
#endif
#ifndef CONFIG_STM32_USART2_SERIALDRIVER
# undef CONFIG_USART2_RXDMA
#endif
#ifndef CONFIG_STM32_USART3_SERIALDRIVER
# undef CONFIG_USART3_RXDMA
#endif
#ifndef CONFIG_STM32_UART4_SERIALDRIVER
# undef CONFIG_UART4_RXDMA
#endif
#ifndef CONFIG_STM32_UART5_SERIALDRIVER
# undef CONFIG_UART5_RXDMA
#endif
#ifndef CONFIG_STM32_USART6_SERIALDRIVER
# undef CONFIG_USART6_RXDMA
#endif
#ifndef CONFIG_STM32_UART7_SERIALDRIVER
# undef CONFIG_UART7_RXDMA
#endif
#ifndef CONFIG_STM32_UART8_SERIALDRIVER
# undef CONFIG_UART8_RXDMA
#endif
#ifndef CONFIG_STM32_UART9_SERIALDRIVER
# undef CONFIG_UART9_RXDMA
#endif
#ifndef CONFIG_STM32_USART10_SERIALDRIVER
# undef CONFIG_USART10_RXDMA
#endif
#ifndef CONFIG_STM32_USART11_SERIALDRIVER
# undef CONFIG_USART11_RXDMA
#endif
#ifndef CONFIG_STM32_UART12_SERIALDRIVER
# undef CONFIG_UART12_RXDMA
#endif
/* Is DMA available on any (enabled) USART? */
#undef SERIAL_HAVE_DMA
#if defined(CONFIG_LPUART1_RXDMA) || defined(CONFIG_USART1_RXDMA) || \
defined(CONFIG_USART2_RXDMA) || defined(CONFIG_USART3_RXDMA) || \
defined(CONFIG_UART4_RXDMA) || defined(CONFIG_UART5_RXDMA) || \
defined(CONFIG_USART6_RXDMA) || defined(CONFIG_UART7_RXDMA) || \
defined(CONFIG_UART8_RXDMA) || defined(CONFIG_UART9_RXDMA) || \
defined(CONFIG_USART10_RXDMA) || defined(CONFIG_USART11_RXDMA) || \
defined(CONFIG_USART12_RXDMA)
# define SERIAL_HAVE_DMA 1
#endif
/* Is DMA used on the console UART? */
#undef SERIAL_HAVE_CONSOLE_DMA
#if defined(CONFIG_LPUART1_SERIAL_CONSOLE) && defined(CONFIG_LPUART1_RXDMA)
# define SERIAL_HAVE_CONSOLE_DMA 1
#elif defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_USART1_RXDMA)
# define SERIAL_HAVE_CONSOLE_DMA 1
#elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(CONFIG_USART2_RXDMA)
# define SERIAL_HAVE_CONSOLE_DMA 1
#elif defined(CONFIG_USART3_SERIAL_CONSOLE) && defined(CONFIG_USART3_RXDMA)
# define SERIAL_HAVE_CONSOLE_DMA 1
#elif defined(CONFIG_UART4_SERIAL_CONSOLE) && defined(CONFIG_UART4_RXDMA)
# define SERIAL_HAVE_CONSOLE_DMA 1
#elif defined(CONFIG_UART5_SERIAL_CONSOLE) && defined(CONFIG_UART5_RXDMA)
# define SERIAL_HAVE_CONSOLE_DMA 1
#elif defined(CONFIG_USART6_SERIAL_CONSOLE) && defined(CONFIG_USART6_RXDMA)
# define SERIAL_HAVE_CONSOLE_DMA 1
#elif defined(CONFIG_UART7_SERIAL_CONSOLE) && defined(CONFIG_UART7_RXDMA)
# define SERIAL_HAVE_CONSOLE_DMA 1
#elif defined(CONFIG_UART8_SERIAL_CONSOLE) && defined(CONFIG_UART8_RXDMA)
# define SERIAL_HAVE_CONSOLE_DMA 1
#elif defined(CONFIG_UART9_SERIAL_CONSOLE) && defined(CONFIG_UART9_RXDMA)
# define SERIAL_HAVE_CONSOLE_DMA 1
#elif defined(CONFIG_USART10_SERIAL_CONSOLE) && defined(CONFIG_USART10_RXDMA)
# define SERIAL_HAVE_CONSOLE_DMA 1
#elif defined(CONFIG_USART11_SERIAL_CONSOLE) && defined(CONFIG_USART11_RXDMA)
# define SERIAL_HAVE_CONSOLE_DMA 1
#elif defined(CONFIG_UART12_SERIAL_CONSOLE) && defined(CONFIG_UART12_RXDMA)
# define SERIAL_HAVE_CONSOLE_DMA 1
#endif
/* Is DMA used on all (enabled) USARTs */
#define SERIAL_HAVE_ONLY_DMA 1
#if defined(CONFIG_STM32_LPUART1_SERIALDRIVER) && !defined(CONFIG_LPUART1_RXDMA)
# undef SERIAL_HAVE_ONLY_DMA
#elif defined(CONFIG_STM32_USART1_SERIALDRIVER) && !defined(CONFIG_USART1_RXDMA)
# undef SERIAL_HAVE_ONLY_DMA
#elif defined(CONFIG_STM32_USART2_SERIALDRIVER) && !defined(CONFIG_USART2_RXDMA)
# undef SERIAL_HAVE_ONLY_DMA
#elif defined(CONFIG_STM32_USART3_SERIALDRIVER) && !defined(CONFIG_USART3_RXDMA)
# undef SERIAL_HAVE_ONLY_DMA
#elif defined(CONFIG_STM32_UART4_SERIALDRIVER) && !defined(CONFIG_UART4_RXDMA)
# undef SERIAL_HAVE_ONLY_DMA
#elif defined(CONFIG_STM32_UART5_SERIALDRIVER) && !defined(CONFIG_UART5_RXDMA)
# undef SERIAL_HAVE_ONLY_DMA
#elif defined(CONFIG_STM32_USART6_SERIALDRIVER) && !defined(CONFIG_USART6_RXDMA)
# undef SERIAL_HAVE_ONLY_DMA
#elif defined(CONFIG_STM32_UART7_SERIALDRIVER) && !defined(CONFIG_UART7_RXDMA)
# undef SERIAL_HAVE_ONLY_DMA
#elif defined(CONFIG_STM32_UART8_SERIALDRIVER) && !defined(CONFIG_UART8_RXDMA)
# undef SERIAL_HAVE_ONLY_DMA
#elif defined(CONFIG_STM32_UART9_SERIALDRIVER) && !defined(CONFIG_UART9_RXDMA)
# undef SERIAL_HAVE_ONLY_DMA
#elif defined(CONFIG_STM32_USART10_SERIALDRIVER) && !defined(CONFIG_USART10_RXDMA)
# undef SERIAL_HAVE_ONLY_DMA
#elif defined(CONFIG_STM32_USART11_SERIALDRIVER) && !defined(CONFIG_USART11_RXDMA)
# undef SERIAL_HAVE_ONLY_DMA
#elif defined(CONFIG_STM32_UART12_SERIALDRIVER) && !defined(CONFIG_UART12_RXDMA)
# undef SERIAL_HAVE_ONLY_DMA
#endif
/* Is RS-485 used? */
#if defined(CONFIG_LPUART1_RS485) || defined(CONFIG_USART1_RS485) || \
defined(CONFIG_USART2_RS485) || defined(CONFIG_USART3_RS485) || \
defined(CONFIG_UART4_RS485) || defined(CONFIG_UART5_RS485) || \
defined(CONFIG_USART6_RS485) || defined(CONFIG_UART7_RS485) || \
defined(CONFIG_UART8_RS485) || defined(CONFIG_UART9_RS485) || \
defined(CONFIG_USART10_RS485) || defined(CONFIG_USART11_RS485) || \
defined(CONFIG_UART12_RS485)
# define HAVE_RS485 1
#endif
#ifdef HAVE_RS485
# define USART_CR1_USED_INTS (USART_CR1_RXNEIE | USART_CR1_TXEIE | USART_CR1_PEIE | USART_CR1_TCIE)
#else
# define USART_CR1_USED_INTS (USART_CR1_RXNEIE | USART_CR1_TXEIE | USART_CR1_PEIE)
#endif
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: stm32_serial_dma_poll
*
* Description:
* Must be called periodically if any STM32 UART is configured for DMA.
* The DMA callback is triggered for each fifo size/2 bytes, but this can
* result in some bytes being transferred but not collected if the incoming
* data is not a whole multiple of half the FIFO size.
*
* May be safely called from either interrupt or thread context.
*
****************************************************************************/
#ifdef SERIAL_HAVE_DMA
void stm32_serial_dma_poll(void);
#endif
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_STC_STM32H5_STM32_UART_H */