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Remove the arch/ subdirectory; replace it with a submodule

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Gregory Nutt 2015-07-22 10:56:22 -06:00
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.gitmodules vendored
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[submodule "configs"]
path = configs
url = https://bitbucket.org/nuttx/boards.git
[submodule "arch"]
path = arch
url = https://bitbucket.org/nuttx/arch.git

1
arch Submodule

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Subproject commit 029a72b36baa4f7c58f0553692a3af193980ace5

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arch/Kconfig
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#
# For a description of the syntax of this configuration file,
# see the file kconfig-language.txt in the NuttX tools repository.
#
choice
prompt "CPU Architecture"
default ARCH_ARM
config ARCH_ARM
bool "ARM"
select ARCH_HAVE_INTERRUPTSTACK
select ARCH_HAVE_VFORK
select ARCH_HAVE_STACKCHECK
select ARCH_HAVE_CUSTOMOPT
---help---
The ARM architectures
config ARCH_AVR
bool "AVR"
select ARCH_NOINTC
select ARCH_HAVE_INTERRUPTSTACK
select ARCH_HAVE_CUSTOMOPT
---help---
Atmel 8-bit bit AVR and 32-bit AVR32 architectures
config ARCH_HC
bool "Freescale HC"
select ARCH_NOINTC
select ARCH_HAVE_INTERRUPTSTACK
---help---
Freescale HC architectures (M9S12)
config ARCH_MIPS
bool "MIPS"
select ARCH_HAVE_INTERRUPTSTACK
select ARCH_HAVE_CUSTOMOPT
---help---
MIPS architectures (PIC32)
config ARCH_RGMP
bool "RGMP"
---help---
RTOS and GPOS on Multi-Processor (RGMP) architecture. See
http://rgmp.sourceforge.net/wiki/index.php/Main_Page.
config ARCH_SH
bool "Renesas"
select ARCH_NOINTC
select ARCH_HAVE_INTERRUPTSTACK
---help---
Renesas architectures (SH and M16C).
config ARCH_SIM
bool "Simulation"
select ARCH_HAVE_TICKLESS
select ARCH_HAVE_POWEROFF
---help---
Linux/Cywgin user-mode simulation.
config ARCH_X86
bool "x86"
---help---
Intel x86 architectures.
config ARCH_Z16
bool "ZNEO"
select ARCH_HAVE_HEAP2
---help---
ZiLOG ZNEO 16-bit architectures (z16f).
config ARCH_Z80
bool "z80"
select ARCH_HAVE_HEAP2
---help---
ZiLOG 8-bit architectures (z80, ez80, z8).
endchoice
config ARCH
string
default "arm" if ARCH_ARM
default "avr" if ARCH_AVR
default "hc" if ARCH_HC
default "mips" if ARCH_MIPS
default "rgmp" if ARCH_RGMP
default "sh" if ARCH_SH
default "sim" if ARCH_SIM
default "x86" if ARCH_X86
default "z16" if ARCH_Z16
default "z80" if ARCH_Z80
source arch/arm/Kconfig
source arch/avr/Kconfig
source arch/hc/Kconfig
source arch/mips/Kconfig
source arch/rgmp/Kconfig
source arch/sh/Kconfig
source arch/sim/Kconfig
source arch/x86/Kconfig
source arch/z16/Kconfig
source arch/z80/Kconfig
comment "Architecture Options"
config ARCH_NOINTC
bool
default n
config ARCH_VECNOTIRQ
bool
default n
config ARCH_DMA
bool
default n
config ARCH_HAVE_IRQPRIO
bool
default n
config ARCH_L2CACHE
bool
default n
config ARCH_HAVE_COHERENT_DCACHE
bool
default n
config ARCH_HAVE_ADDRENV
bool
default n
config ARCH_NEED_ADDRENV_MAPPING
bool
default n
config ARCH_HAVE_VFORK
bool
default n
config ARCH_HAVE_MMU
bool
default n
config ARCH_HAVE_MPU
bool
default n
config ARCH_NAND_HWECC
bool
default n
config ARCH_HAVE_EXTCLK
bool
default n
config ARCH_HAVE_POWEROFF
bool
default n
config ARCH_HAVE_RESET
bool
default n
config ARCH_USE_MMU
bool "Enable MMU"
default n
depends on ARCH_HAVE_MMU
---help---
The architecture supports supports an MMU. Enable this option in
order to enable use of the MMU. For most architectures, this is
not really an option: It is required to use the MMU. In those
cases, this selection will always be forced.
config ARCH_USE_MPU
bool "Enable MPU"
default n
depends on ARCH_HAVE_MPU
---help---
The architecture supports supports an MPU. Enable this option in
order to enable use of the MPU. For most architectures, this option
is enabled by other, platform-specific logic. In those cases, this
selection will always be forced.
menuconfig ARCH_ADDRENV
bool "Address environments"
default n
depends on ARCH_HAVE_ADDRENV
---help---
Support per-task address environments using the MMU... i.e., support
"processes"
if ARCH_ADDRENV && ARCH_NEED_ADDRENV_MAPPING
config ARCH_TEXT_VBASE
hex "Virtual .text base"
---help---
The virtual address of the beginning the .text region
config ARCH_DATA_VBASE
hex "Virtual .bss/.data base"
---help---
The virtual address of the beginning of the .bss/.data region.
config ARCH_HEAP_VBASE
hex "Virtual heap base"
---help---
The virtual address of the beginning of the heap region.
config ARCH_SHM_VBASE
hex "Shared memory base"
depends on MM_SHM
---help---
The virtual address of the beginning of the shared memory region.
config ARCH_TEXT_NPAGES
int "Max .text pages"
default 1
---help---
The maximum number of pages that can allocated for the .text region.
This, along with knowledge of the page size, determines the size of
the .text virtual address space. Default is 1.
config ARCH_DATA_NPAGES
int "Max .bss/.data pages"
default 1
---help---
The maximum number of pages that can allocated for the .bss/.data
region. This, along with knowledge of the page size, determines the
size of the .bss/.data virtual address space. Default is 1.
config ARCH_HEAP_NPAGES
int "Max heap pages"
default 1
---help---
The maximum number of pages that can allocated for the heap region.
This, along with knowledge of the page size, determines the size of
the heap virtual address space. Default is 1.
if MM_SHM
config ARCH_SHM_MAXREGIONS
int "Max shared memory regions"
default 1
---help---
The maximum number of regions that can allocated for the shared
memory space. This hard-coded value permits static allocation of
the shared memory data structures and serves no other purpose.
Default is 1.
The size of the virtual shared memory address space is then
determined by the product of the maximum number of regions, the
maximum number of pages per region, and the configured size of
each page.
config ARCH_SHM_NPAGES
int "Max shared memory pages"
default 1
---help---
The maximum number of pages that can allocated per region for the shared memory
region. Default is 1.
The size of the virtual shared memory address space is then
determined by the product of the maximum number of regions, the
maximum number of pages per region, and the configured size of
each page.
endif # MM_SHM
config ARCH_STACK_DYNAMIC
bool "Dynamic user stack"
default n
depends on BUILD_KERNEL && EXPERIMENTAL
---help---
Select this option if the user process stack resides in its own
address space. The naming of this selection implies that dynamic
stack allocation is supported. Certainly this option must be set if
dynamic stack allocation is supported by a platform. But the more
general meaning of this configuration environment is simply that the
stack has its own address space.
NOTE: This option not yet fully implemented in the code base.
Hence, it is marked EXPERIMENTAL: Do not enable it unless you plan
finish the implementation.
if ARCH_STACK_DYNAMIC
config ARCH_STACK_VBASE
hex "Virtual stack base"
---help---
The virtual address of the beginning the stack region
config ARCH_STACK_NPAGES
int "Max. stack pages"
default 1
---help---
The maximum number of pages that can allocated for the stack region.
This, along with knowledge of the page size, determines the size of
the stack virtual address space. Default is 1.
endif # ARCH_STACK_DYNAMIC
config ARCH_KERNEL_STACK
bool "Kernel process stack"
default n if !LIBC_EXECFUNCS
default y if LIBC_EXECFUNCS
depends on BUILD_KERNEL
---help---
It this option is selected, then every user process will have two
stacks: A large, potentially dynamically sized user stack and small
kernel stack that is used during system call process.
If this option is not selected, then kernel system calls will simply
use the caller's user stack. So, in most cases, this option is not
required. However, this option is *required* if both BUILD_KERNEL
and LIBC_EXECFUNCS are selected. Why? Because when we instantiate
and initialize the address environment of the new user process, we
will temporarily lose the address environment of the old user
process, including its stack contents. The kernel C logic will
crash immediately with no valid stack in place.
When this option is selected, the smaller kernel stack stays in
place during system call processing event though the original user
stack may or may not be accessible.
if ARCH_KERNEL_STACK
config ARCH_KERNEL_STACKSIZE
int "Kernel stack size"
default 1568
---help---
The common size of each process' kernel stack
endif # ARCH_KERNEL_STACK
config ARCH_PGPOOL_MAPPING
bool "Have page pool mapping"
default n
---help---
If there is a MMU mapping in place for the page pool memory, then
this mapping can be utilized to simplify some page table operations.
Otherwise, a temporary mapping will have to be established each time
it is necessary to modify the contents of a page.
if ARCH_PGPOOL_MAPPING
config ARCH_PGPOOL_PBASE
hex "Page pool physical address"
default 0x0
---help---
The physical address of the start of the page pool memory. This
setting is probably equivalent to other platform specific definitions
but is required again in order to modularize the common address
environment logic.
config ARCH_PGPOOL_VBASE
hex "Page pool virtual address"
default 0x0
---help---
The virtual address of the start of the page pool memory. This
setting is probably equivalent to other platform specific definitions
but is required again in order to modularize the common address
environment logic.
config ARCH_PGPOOL_SIZE
int "Page pool size (byes)"
default 0
---help---
The size of the page pool memory in bytes. This setting is probably
equivalent to other platform specific definitions but is required again
in order to modularize the common address environment logic.
endif # ARCH_PGPOOL_MAPPING
endif # ARCH_ADDRENV && ARCH_NEED_ADDRENV_MAPPING
menuconfig PAGING
bool "On-demand paging"
default n
depends on ARCH_USE_MMU && !ARCH_ROMPGTABLE
---help---
If set =y in your configation file, this setting will enable the on-demand
paging feature as described in http://www.nuttx.org/NuttXDemandPaging.html.
if PAGING
config PAGING_PAGESIZE
int "Page size (bytes)"
default 4096
---help---
The size of one managed page. This must be a value supported by the
processor's memory management unit
config PAGING_NLOCKED
int "Number of locked pages"
default 48
---help---
This is the number of locked pages in the memory map.
config PAGING_CUSTOM_BASE
bool "Custom paging base address"
default n
---help---
By default, the page begins at RAM_START/VSTART. That base address
can be changed if this value is selected.
if PAGING_CUSTOM_BASE
config PAGING_LOCKED_PBASE
hex "Physical base address"
config PAGING_LOCKED_VBASE
hex "Virtual base address"
endif # PAGING_CUSTOM_BASE
config PAGING_NPPAGED
int "Number of physical pages"
default 256
---help---
This is the number of physical pages available to support the paged
text region.
config PAGING_NVPAGED
int "Number of virtual pages"
default 1024
---help---
This actual size of the virtual paged text region (in pages). This
is also the number of virtual pages required to span the entire
paged region. The on-demand paging feature is intended to support
only the case where the virtual paged text area is much larger the
available physical pages. Otherwise, why would you enable on-demand paging?
config PAGING_NDATA
int "Number of data pages"
default 256
---help---
This is the number of data pages in the memory map. The data region
will extend to the end of RAM unless overridden by a setting in the
configuration file.
NOTE: In some architectures, it may be necessary to take some memory
from the end of RAM for page tables or other system usage. The
configuration settings and linker directives must be cognizant of
that: PAGING_NDATA should be defined to prevent the data region from
extending all the way to the end of memory.
config PAGING_DEFPRIO
int "Page fill worker thread priority"
default 100
---help---
The default, minimum priority of the page fill worker thread. The
priority of the page fill work thread will be boosted boosted
dynamically so that it matches the priority of the task on behalf
of which it performs the fill. This defines the minimum priority
that will be used. Default: 100.
config PAGING_STACKSIZE
int "Page fill worker thread stack size"
default 1024
---help---
Defines the size of the allocated stack for the page fill worker
thread. Default: 1024.
config PAGING_BLOCKINGFILL
bool "Blocking fill"
default n
---help---
The architecture specific up_fillpage() function may be blocking
or non-blocking. If defined, this setting indicates that the
up_fillpage() implementation will block until the transfer is
completed. Default: Undefined (non-blocking).
config PAGING_WORKPERIOD
int "Work period (usec)"
default 500000
---help---
The page fill worker thread will wake periodically even if there
is no mapping to do. This selection controls that wake-up period
(in microseconds). This wake-up a failsafe that will handle any
cases where a single is lost (that would really be a bug and
shouldn't happen!) and also supports timeouts for case of non-
blocking, asynchronous fills (see CONFIG_PAGING_TIMEOUT_TICKS).
config PAGING_TIMEOUT
bool "Paging timeout"
default n
---help---
If defined, the implementation will monitor the (asynchronous) page
fill logic. If the fill takes longer than than a timeout value,
then a fatal error will be declared. Default: No timeouts monitored
config PAGING_TIMEOUT_TICKS
int "Paging timeout ticks"
default 10
depends on PAGING_TIMEOUT
---help---
If PAGING_TIMEOUT is defined, then implementation will monitor the
(asynchronous) page fill logic. If the fill takes longer than this
number if microseconds, then a fatal error will be declared.
Default: No timeouts monitored
endif # PAGING
config ARCH_IRQPRIO
bool "Prioritized interrupt support"
default n
depends on ARCH_HAVE_IRQPRIO
---help---
Enable support for prioritized interrupts.
NOTE: The use of interrupt priorities implies that you also have
support for nested interrupts. Most architectures do not support
nesting of interrupts or, if they do, they only supported nested
interrupts with certain configuration options. So this selection
should be used with caution.
config ARCH_STACKDUMP
bool "Dump stack on assertions"
default n
---help---
Enable to do stack dumps after assertions
config ARCH_USBDUMP
bool "Dump USB trace data"
default n
depends on USBDEV_TRACE
---help---
Enable to do USB trace after assertions
config ENDIAN_BIG
bool "Big Endian Architecture"
default n
---help---
Select if architecture operates using big-endian byte ordering.
config ARCH_IDLE_CUSTOM
bool "Custom IDLE loop"
default n
---help---
Each architecture provides a "default" IDLE loop that exits when the
MCU has nothing else to do. This default IDLE loop can be replaced
by a custom, board-specific IDLE loop by setting this option. Such
a custom IDLE loop may do things like a continuous built-in test or
perhaps or IDLE low power operations.
NOTE: As of this writing, this capability is only supported by the
STM32. However, the implementation is trivial: If CONFIG_ARCH_IDLE_CUSTOM,
then the default IDLE loop file is not included in the MCU-specific
Make.defs file.
config ARCH_CUSTOM_PMINIT
bool "Custom PM initialization"
default n
depends on PM
---help---
Each architecture provides default power management (PM)
initialization that is called automatically when the system is
started. This default PM initialization can be replaced by custom,
board-specific PM initialization by setting this option. Such a
custom initialization may do additional PM-related initialization
that is unique to the board power management requirements.
NOTE: As of this writing, this capability is only supported by the
STM32. However, the implementation is trivial: If CONFIG_ARCH_CUSTOM_PMINIT,
then the default PM initialization is not included in the MCU-specific
Make.defs file.
config ARCH_HAVE_RAMFUNCS
bool
default n
config ARCH_RAMFUNCS
bool "Copy functions to RAM on startup"
default y
depends on ARCH_HAVE_RAMFUNCS
---help---
Copy some functions to RAM at boot time. This is done in some
architectures to improve performance. In other cases, it is done
so that FLASH can be reconfigured while the MCU executes out of
SRAM.
config ARCH_HAVE_RAMVECTORS
bool
default n
config ARCH_RAMVECTORS
bool "Support RAM interrupt vectors"
default n
depends on ARCH_HAVE_RAMVECTORS
---help---
If ARCH_RAMVECTORS is defined, then the architecture will support
modifiable vectors in a RAM-based vector table.
comment "Board Settings"
config BOARD_LOOPSPERMSEC
int "Delay loops per millisecond"
default 5000
---help---
Simple delay loops are used by some logic, especially during boot-up,
driver initialization. These delay loops must be calibrated for each
board in order to assure accurate timing by the delay loops.
config ARCH_CALIBRATION
bool "Calibrate delay loop"
default n
---help---
Enables some built in instrumentation that causes a 100 second delay
during boot-up. This 100 second delay serves no purpose other than it
allows you to calibrate BOARD_LOOPSPERMSEC. You simply use a stop
watch to measure the actual delay then adjust BOARD_LOOPSPERMSEC until
the actual delay is 100 seconds.
comment "Interrupt options"
config ARCH_HAVE_INTERRUPTSTACK
bool
default n
config ARCH_INTERRUPTSTACK
int "Interrupt Stack Size"
depends on ARCH_HAVE_INTERRUPTSTACK
default 0
---help---
This architecture supports an interrupt stack. If defined, this symbol
will be the size of the interrupt stack in bytes. If not defined (or
defined to be zero), the user task stacks will be used during interrupt
handling.
config ARCH_HAVE_HIPRI_INTERRUPT
bool
default n
config ARCH_HIPRI_INTERRUPT
bool "High priority interrupts"
default n
depends on ARCH_HAVE_HIPRI_INTERRUPT && ARCH_HAVE_IRQPRIO
select ARMV7M_USEBASEPRI
select ARCH_IRQPRIO
---help---
NOTE: This description is currently unique to the Cortex-M family
which is the only family that currently supports this feature. The
general feature is not conceptually unique to the Cortex-M but it
is extended to any other family, then this discussion will have to
be generalized.
If ARMV7M_USEBASEPRI is selected, then interrupts will be disabled
by setting the BASEPRI register to NVIC_SYSH_DISABLE_PRIORITY so
that most interrupts will not have execution priority. SVCall must
have execution priority in all cases.
In the normal cases, interrupts are not nest-able and all interrupts
run at an execution priority between NVIC_SYSH_PRIORITY_MIN and
NVIC_SYSH_PRIORITY_MAX (with NVIC_SYSH_PRIORITY_MAX reserved for
SVCall).
If, in addition, ARCH_HIPRI_INTERRUPT is defined, then special high
priority interrupts are supported. These are not "nested" in the
normal sense of the word. These high priority interrupts can
interrupt normal processing but execute outside of OS (although they
can "get back into the game" via a PendSV interrupt).
How do you specify a high priority interrupt? You need to do two
things:
1) You need to change the address in the vector table so that
the high priority interrupt vectors to your special C
interrupt handler. There are two ways to do this:
a) If you select CONFIG_ARCH_RAMVECTORS, then vectors will
be kept in RAM and the system will support the interface:
int up_ramvec_attach(int irq, up_vector_t vector)
that can be used to attach your C interrupt handler to the
vector at run time.
b) Alternatively, you could keep your vectors in FLASH but in
order to this, you would have to develop your own custom
vector table.
2) Then set the priority of your interrupt to NVIC to
NVIC_SYSH_HIGH_PRIORITY using the standard interface:
int up_prioritize_irq(int irq, int priority)
NOTE: ARCH_INTERRUPTSTACK must be set in kernel mode (BUILD_KERNEL).
In kernel mode without an interrupt stack, the interrupt handler
will set the MSP to the stack pointer of the interrupted thread. If
the interrupted thread was a privileged thread, that will be the MSP
otherwise it will be the PSP. If the PSP is used, then the value of
the MSP will be invalid when the interrupt handler returns because
it will be a pointer to an old position in the unprivileged stack.
Then when the high priority interrupt occurs and uses this stale MSP,
there will most likely be a system failure.
If the interrupt stack is selected, on the other hand, then the
interrupt handler will always set the the MSP to the interrupt
stack. So when the high priority interrupt occurs, it will either
use the MSP of the last privileged thread to run or, in the case of
the nested interrupt, the interrupt stack if no privileged task has
run
config ARCH_INT_DISABLEALL
bool "Disable high priority interrupts"
default y
depends on ARCH_HIPRI_INTERRUPT && EXPERIMENTAL
---help---
If ARCH_HIPRI_INTERRUPT is defined, then special high priority
interrupts are supported. These are not "nested" in the normal
sense of the word. These high priority interrupts can interrupt
normal processing but execute outside of OS (although they can "get
back into the game" via a PendSV interrupt).
In the normal course of things, interrupts must occasionally be
disabled using the irqsave() inline function to prevent contention
in use of resources that may be shared between interrupt level and
non-interrupt level logic. Now the question arises, if
ARCH_HIPRI_INTERRUPT, do we disable all interrupts (except SVCall),
or do we only disable the "normal" interrupts. Since the high
priority interrupts cannot interact with the OS, you may want to
permit the high priority interrupts even if interrupts are
disabled. The setting ARCH_INT_DISABLEALL can be used to select
either behavior:
----------------------------+--------------+----------------------------
CONFIG_ARCH_HIPRI_INTERRUPT | NO | YES
----------------------------+--------------+--------------+-------------
CONFIG_ARCH_INT_DISABLEALL | N/A | YES | NO
----------------------------+--------------+--------------+-------------
| | | SVCall
| SVCall | SVCall | HIGH
Disable here and below --------> MAXNORMAL ---> HIGH --------> MAXNORMAL
| | MAXNORMAL |
----------------------------+--------------+--------------+-------------
NOTE: This does not work now because interrupts get disabled in the
standard interrupt handling, prohibiting nesting. Fix is simple: Need
to used more priority levels so that we can make a cleaner distinction
with the standard interrupt handler.
comment "Boot options"
choice
prompt "Boot Mode"
default BOOT_RUNFROMFLASH
config BOOT_RUNFROMEXTSRAM
bool "Run from external SRAM"
---help---
Some configuration support booting and running from external SRAM.
config BOOT_RUNFROMFLASH
bool "Boot and run from flash"
---help---
Most configurations support XIP operation from FLASH but must copy
initialized .data sections to RAM. (This is the default).
config BOOT_RUNFROMISRAM
bool "Boot and run from internal SRAM"
---help---
Some configuration support booting and running from internal SRAM.
config BOOT_RUNFROMSDRAM
bool "Boot and run from external SDRAM"
---help---
Some configuration support booting and running from external SDRAM.
config BOOT_COPYTORAM
bool "Boot from FLASH but copy to ram"
---help---
Some configurations boot in FLASH but copy themselves entirely into
RAM for better performance.
endchoice
menu "Boot Memory Configuration"
config RAM_START
hex "Primary RAM start address (physical)"
default 0x0
help
The physical start address of primary installed RAM. "Primary" RAM
refers to the RAM that you link program code into. If program code
does not execute out of RAM but from FLASH, then you may designate
any block of RAM as "primary."
config RAM_VSTART
hex "Primary RAM start address (virtual)"
default 0x0
depends on ARCH_USE_MMU
help
The virtual start address of installed primary RAM. "Primary" RAM
refers to the RAM that you link program code into. If program code
does not execute out of RAM but from FLASH, then you may designate
any block of RAM as "primary."
config RAM_SIZE
int "Primary RAM size"
default 0
help
The size in bytes of the installed primary RAM. "Primary" RAM
refers to the RAM that you link program code into. If program code
does not execute out of RAM but from FLASH, then you may designate
any block of RAM as "primary."
if BOOT_RUNFROMFLASH && ARCH_USE_MMU
config FLASH_START
hex "Boot FLASH start address (physical)"
default 0x0
help
The physical start address of installed boot FLASH. "Boot" FLASH
refers to the FLASH that you link program code into.
config FLASH_VSTART
hex "Boot FLASH start address (virtual)"
default 0x0
help
The virtual start address of installed boot FLASH. "Boot" FLASH
refers to the FLASH that you link program code into.
config FLASH_SIZE
int "Boot FLASH size"
default 0
help
The size in bytes of the installed boot FLASH. "Boot" FLASH
refers to the FLASH that you link program code into.
endif # BOOT_RUNFROMFLASH && ARCH_USE_MMU
config ARCH_HAVE_SDRAM
bool
default n
config BOOT_SDRAM_DATA
bool "Data in SDRAM"
default n
depends on ARCH_HAVE_SDRAM && !BOOT_RUNFROMSDRAM
---help---
This selection should be set if data lies in SDRAM (vs. SRAM) and if
SDRAM was not previously initialized by a loader. Obviously, this
does not apply if we booting from SDRAM because SDRAM must have been
initialized priority to loading NuttX into SDRAM.
In the case where SDRAM must be initialized by NuttX, the
initialization sequence is a little different: Normally, .data and
.bss must be initialized before starting the system. But in this
case SDRAM must be configured by board-specific logic before the
.data and .bss sections can be initialized.
endmenu # Boot Memory Configuration

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arch/README.txt
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Architecture-Specific Code
^^^^^^^^^^^^^^^^^^^^^^^^^^
Table of Contents
^^^^^^^^^^^^^^^^^
o Architecture-Specific Code
o Summary of Files
o Supported Architectures
o Configuring NuttX
Architecture-Specific Code
^^^^^^^^^^^^^^^^^^^^^^^^^^
The NuttX configuration consists of:
o Processor architecture specific files. These are the files contained
in the arch/<arch-name>/ directory discussed in this README.
o Chip/SoC specific files. Each processor processor architecture
is embedded in chip or System-on-a-Chip (SoC) architecture. The
full chip architecture includes the processor architecture plus
chip-specific interrupt logic, general purpose I/O (GIO) logic, and
specialized, internal peripherals (such as UARTs, USB, etc.).
These chip-specific files are contained within chip-specific
sub-directories in the arch/<arch-name>/ directory and are selected
via the CONFIG_ARCH_name selection
o Board specific files. In order to be usable, the chip must be
contained in a board environment. The board configuration defines
additional properties of the board including such things as
peripheral LEDs, external peripherals (such as network, USB, etc.).
These board-specific configuration files can be found in the
configs/<board-name>/ sub-directories.
This README will address the processor architecture specific files
that are contained in the arch/<arch-name>/ directory. The file
include/nuttx/arch.h identifies all of the APIs that must
be provided by this architecture specific logic. (It also includes
arch/<arch-name>/arch.h as described below).
Directory Structure
^^^^^^^^^^^^^^^^^^^
The arch directory contains architecture specific logic. The complete
board port in is defined by the architecture-specific code in this
directory (plus the board-specific configurations in the config/
subdirectory). Each architecture must provide a subdirectory <arch-name>
under arch/ with the following characteristics:
<arch-name>/
|-- include/
| |--<chip-name>/
| | `-- (chip-specific header files)
| |--<other-chips>/
| |-- arch.h
| |-- irq.h
| `-- types.h
`-- src/
|--<chip-name>/
| `-- (chip-specific source files)
|--<other-chips>/
|-- Makefile
`-- (architecture-specific source files)
Summary of Files
^^^^^^^^^^^^^^^^
include/<chip-name>/
This sub-directory contains chip-specific header files.
include/arch.h
This is a hook for any architecture specific definitions that may
be needed by the system. It is included by include/nuttx/arch.h
include/types.h
This provides architecture/toolchain-specific definitions for
standard types. This file should typedef:
_int8_t, _uint8_t, _int16_t, _uint16_t, _int32_t, _uint32_t
and if the architecture supports 64-bit integers.
_int24_t, _uint24_t, int64_t, uint64_t
NOTE that these type names have a leading underscore character. This
file will be included(indirectly) by include/stdint.h and typedef'ed to
the final name without the underscore character. This roundabout way of
doings things allows the stdint.h to be removed from the include/
directory in the event that the user prefers to use the definitions
provided by their toolchain header files
irqstate_t
Must be defined to the be the size required to hold the interrupt
enable/disable state.
This file will be included by include/sys/types.h and be made
available to all files.
include/irq.h
This file needs to define some architecture specific functions (usually
inline if the compiler supports inlining) and structure. These include:
- struct xcptcontext. This structures represents the saved context
of a thread.
- irqstate_t irqsave(void) -- Used to disable all interrupts.
- void irqrestore(irqstate_t flags) -- Used to restore interrupt
enables to the same state as before irqsave was called.
This file must also define NR_IRQS, the total number of IRQs supported
by the board.
src/<chip-name>/
This sub-directory contains chip-specific source files.
src/Makefile
This makefile will be executed to build the targets src/libup.a and
src/up_head.o. The up_head.o file holds the entry point into the system
(power-on reset entry point, for example). It will be used in
the final link with libup.a and other system archives to generate the
final executable.
Supported Architectures
^^^^^^^^^^^^^^^^^^^^^^^
arch/sim - Linux/Cygwin simulation
A user-mode port of NuttX to the x86 Linux platform is available.
The purpose of this port is primarily to support OS feature development.
This port does not support interrupts or a real timer (and hence no
round robin scheduler) Otherwise, it is complete.
arch/arm - ARM-based micro-controllers
This directory holds common ARM architectures. At present, this includes
the following subdirectories:
arch/arm/include and arch/arm/src/common
Common ARM/Cortex-M3 logic.
arch/arm/src/arm and arch/arm/include/arm
Common ARM-specific logic
arch/arm/src/armv7-m and arch/arm/include/armv7-m
Common ARMv7-M logic (Cortex-M3 and Cortex-M4)
arch/arm/include/c5471 and arch/arm/src/c5471
TI TMS320C5471 (also called TMS320DM180 or just C5471).
NuttX operates on the ARM7 of this dual core processor. This port
complete, verified, and included in the NuttX release 0.1.1.
arch/arm/include/calypso and arch/arm/src/calypso
TI "Calypso" MCU used in various cell phones (and, in particular,
by the Osmocom-bb project). Like the c5471, NuttX operates on the
ARM7 of this dual core processor. This port was contributed by
Denis Carilki and includes the work of Denis, Alan Carvalho de Assis,
and Stefan Richter. Calypso support first appeared in NuttX-6.17.
arch/arm/include/dm320 and arch/arm/src/dm320
TI TMS320DM320 (also called just DM320).
NuttX operates on the ARM9EJS of this dual core processor. This port
complete, verified, and included in the NuttX release 0.2.1.
arch/arm/include/imx and arch/arm/src/imx
Freescale MC9328MX1 or i.MX1. This port uses the Freescale MX1ADS
development board with a GNU arm-elf toolchain* under either Linux or Cygwin.
STATUS: This port has stalled because of development tool issues. Coding
is complete on the basic port (timer, serial console, SPI).
arch/arm/include/lm and arch/arm/src/lm
These directories contain support for the Luminary LM3S/4F family. The
initial, release of this port was included in NuttX version 0.4.6. The
current port includes timer, serial console, Ethernet, SSI, and microSD
support. There are working configurations the NuttX OS test, to run the
NuttShell (NSH), the NuttX networking test, and the uIP web server.
arch/arm/include/lpc214x and arch/arm/src/lpc214x
These directories provide support for NXP LPC214x family of
ARM7TDMI processors. This port boots and passes the OS test (examples/ostest).
The port is complete and verifed. As of NuttX 0.3.17, the port includes:
timer interrupts, serial console, USB driver, and SPI-based MMC/SD card
support. A verifed NuttShell (NSH) configuration is also available.
arch/arm/include/lpc2378 and arch/arm/src/lpc2378.
NXP LPC2378. Support is provided for the NXP LPC2378 MCU. This port was
contributed by Rommel Marcelo is was first released in NuttX-5.3.
STATUS: This port boots and passes the OS test (examples/ostest) and
includes a working implementation of the NuttShell (NSH). The port is
complete and verified. As of NuttX 5.3, the port includes only basic
timer interrupts and serial console support.
arch/arm/include/lpc31xx and arch/arm/src/lpc31xx
These directories provide support for NXP LPC31xx family of
ARM926EJ-S processors. The port for the NXP LPC3131 was first
released in NuttX-5.1 (but was not functional until NuttX-5.2).
STATUS: The basic EA3131 port is complete and verified in NuttX-5.2
This basic port includes basic boot-up, serial console, and timer
interrupts. This port was extended in NuttX 5.3 with a USB high
speed driver contributed by David Hewson. This port has been
verified using the NuttX OS test, USB serial and mass storage tests
and includes a working implementation of the NuttShell ((NSH)).
This port was later extended to support additional members of the
LPC31xx family including, specifically, the LPC3152.
arch/arm/include/sam3u and arch/arm/src/sam3u
Atmel AT91SAM3U. This port is for Atmel AT91SAM3U4E MCU.
STATUS: The basic AT91SAM3U port was released in NuttX version 5.1.
The basic port includes boot-up logic, interrupt driven serial
console, and system timer interrupts. That release passes the
NuttX OS test and is proven to have a valid OS implementation. A
onfiguration to support the NuttShell is also included.
arch/arm/include/stm32 and arch/arm/src/stm32
These directories contain support for the STMicro STM32 F1, F2, and
F4 families.
STATUS: The basic STM32 F1 port was released in NuttX version 0.4.12.
and has continued to develop consistently over time. It now includes
support for the F2 and F4 families and a rich offering of peripheral
drivers.
arch/arm/include/str71x and arch/arm/src/str71x
These directories provide support for the STMicro STR71x processors.
Coding is complete on the basic port (boot logic, system time, serial console),
but no testing has been performed due to some problems I am having with my
JTAG wiggler and OpenOCD on Linux.
arch/avr
This directory is dedicated to ports to the Atmel AVR (8-bit) and AVR32 (32-bit)
MCU families. STATUS: Under development.
arch/avr/include/avr and arch/avr/src/avr
Common support for all 8-bit AVR MCUs
arch/avr/include/atmega and arch/avr/src/atmega
Support specifically for the AVR ATMega family (specifically only for
the ATMega128 at the moment).
arch/avr/include/at90usb and arch/avr/src/at90usb
Support specifically for the AVR AT90USB646, 647, 1286, and 1287 family.
arch/avr/include/avr32 and arch/avr/src/avr32
Common support for all AVR32 MCUs
arch/avr/include/at32uc3 and arch/avr/src/at32uc3
Support specifically for the AT32UC3Bxxx family (specifically only for
the AT32UC3B0256 at the moment).
arch/hc
This directory is dedicated to ports to the Freescale HC family.
arch/arm/include/m9s12 and arch/arm/src/m9s12
These directories provide support for the Freescale mc9s12x family.
STATUS: Fragments of this port were first released in nuttx-5.0 and
the port was "code-complete" as nuttx-5.18. However, the final
verification effort has been stalled because of higher priority tasks.
arch/mips
This directory is dedicated to ports to the MIPS family.
arch/mips/include/mips32 and arch/mips/src/mips32
Common support for all MIPS32 architectures
arch/mips/include/pic32mx and arch/mips/src/pic32mx
Support for all MicroChip PIC32MX architectures
arch/rgmp
RGMP stands for RTOS and GPOS on Multi-Processor. RGMP is a project
for running GPOS and RTOS simultaneously on multi-processor platforms.
You can port your favorite RTOS to RGMP together with an unmodified
Linux to form a hybrid operating system. This makes your application
able to use both RTOS and GPOS features.
See http://rgmp.sourceforge.net/wiki/index.php/Main_Page for further
information about RGMP.
arch/sh - SuperH and related Hitachi/Renesas microcontrollers
arch/sh/include and arch/sh/src/common
Common SuperH logic.
arch/sh/include/shs and arch/sh/src/sh1
Support for the SH-1 processor.
arch/x86 - Intel x86 architectures
This directory holds related, 32- and 64-bit architectures from Intel.
At present, this includes the following subdirectories:
arch/x86/include and arch/x86/src/common
Common x86 logic.
arch/x86/include/i486 and arch/x86/src/i486
These directories hold definitions and logic appropriate for any
instantiation of the 32-bit i486 architecture.
arch/x86/include/qemu and arch/x86/src/qemu
This is the implementation of NuttX on the QEMU x86 simulation.
arch/z16 - ZiLOG 16-bit processors
This directory holds related, 16-bit architectures from ZiLOG. At
present, this includes the following subdirectories:
arch/z16/include and arch/z16/src/common
Common microcontroller logic.
arch/z16/include/z16f and arch/z16/src/z16f
ZiLOG z16f Microcontroller.
STATUS: Released in nuttx-0.3.7. Fully functional other than issues
addressed in ${TOPDIR}/TODO.
arch/z80 - ZiLOG 8-bit microcontrollers
This directory holds related, 8-bit architectures from ZiLOG. At
present, this includes the following subdirectories:
arch/z80/include and arch/z80/src/common
Common microcontroller logic.
arch/z80/include/z80 and arch/z80/src/z80
Classic ZiLOG z80 Microcontroller.
STATUS: Functional with no known defects. There are still several
OS features that have not yet been tested (e.g., networking).
arch/z80/include/z8 and arch/z80/src/z8
ZiLOG Z8Encore! Microcontroller
arch/z80/include/ez80 and arch/z80/src/ez80
ZiLOG ez80 Acclaim! Microcontroller

533
arch/arm/Kconfig
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@ -1,533 +0,0 @@
#
# For a description of the syntax of this configuration file,
# see the file kconfig-language.txt in the NuttX tools repository.
#
if ARCH_ARM
comment "ARM Options"
choice
prompt "ARM chip selection"
default ARCH_CHIP_STM32
config ARCH_CHIP_A1X
bool "Allwinner A1X"
select ARCH_CORTEXA8
select ARCH_HAVE_FPU
select ARCH_HAVE_MMU
select ARCH_USE_MMU
select ARCH_HAVE_LOWVECTORS
select ARCH_HAVE_SDRAM
select BOOT_RUNFROMSDRAM
select ARCH_HAVE_ADDRENV
select ARCH_NEED_ADDRENV_MAPPING
---help---
Allwinner A1X family: A10, A10S (A12), A13 (ARM Cortex-A8)
config ARCH_CHIP_C5471
bool "TMS320 C5471"
select ARCH_ARM7TDMI
select ARCH_HAVE_LOWVECTORS
select ARCH_HAVE_OTHER_UART
---help---
TI TMS320 C5471, A180, or DA180 (ARM7TDMI)
config ARCH_CHIP_CALYPSO
bool "Calypso"
select ARCH_ARM7TDMI
select ARCH_HAVE_HEAP2
select ARCH_HAVE_LOWVECTORS
select ARCH_HAVE_OTHER_UART
select ARCH_HAVE_POWEROFF
---help---
TI Calypso-based cell phones (ARM7TDMI)
config ARCH_CHIP_DM320
bool "TMS320 DM320"
select ARCH_ARM926EJS
select ARCH_HAVE_LOWVECTORS
---help---
TI DMS320 DM320 (ARM926EJS)
config ARCH_CHIP_EFM32
bool "Energy Micro"
select ARCH_HAVE_CMNVECTOR
select ARMV7M_CMNVECTOR
---help---
Energy Micro EFM32 microcontrollers (ARM Cortex-M).
config ARCH_CHIP_IMX
bool "Freescale iMX"
select ARCH_ARM920T
select ARCH_HAVE_HEAP2
select ARCH_HAVE_LOWVECTORS
---help---
Freescale iMX architectures (ARM920T)
config ARCH_CHIP_KINETIS
bool "Freescale Kinetis"
select ARCH_CORTEXM4
select ARCH_HAVE_MPU
select ARCH_HAVE_FPU
select ARCH_HAVE_RAMFUNCS
---help---
Freescale Kinetis Architectures (ARM Cortex-M4)
config ARCH_CHIP_KL
bool "Freescale Kinetis L"
select ARCH_CORTEXM0
select ARCH_HAVE_CMNVECTOR
---help---
Freescale Kinetis L Architectures (ARM Cortex-M0+)
config ARCH_CHIP_LM
bool "TI/Luminary Stellaris"
select ARCH_HAVE_CMNVECTOR
select ARCH_HAVE_MPU
---help---
TI/Luminary Stellaris LMS3 and LM4F architectures (ARM Cortex-M3/4)
config ARCH_CHIP_TIVA
bool "TI Tiva"
select ARCH_HAVE_CMNVECTOR
select ARCH_HAVE_MPU
select ARCH_HAVE_FPU
---help---
TI Tiva TM4C architectures (ARM Cortex-M4)
config ARCH_CHIP_LPC11XX
bool "NXP LPC11xx"
select ARCH_CORTEXM0
select ARCH_HAVE_CMNVECTOR
---help---
NXP LPC11xx architectures (ARM Cortex-M0)
config ARCH_CHIP_LPC17XX
bool "NXP LPC17xx"
select ARCH_CORTEXM3
select ARCH_HAVE_CMNVECTOR
select ARCH_HAVE_MPU
---help---
NXP LPC17xx architectures (ARM Cortex-M3)
config ARCH_CHIP_LPC214X
bool "NXP LPC214x"
select ARCH_ARM7TDMI
select ARCH_HAVE_LOWVECTORS
---help---
NXP LPC2145x architectures (ARM7TDMI)
config ARCH_CHIP_LPC2378
bool "NXP LPC2378"
select ARCH_ARM7TDMI
select ARCH_HAVE_LOWVECTORS
---help---
NXP LPC2145x architectures (ARM7TDMI)
config ARCH_CHIP_LPC31XX
bool "NXP LPC31XX"
select ARCH_ARM926EJS
select ARCH_HAVE_LOWVECTORS
---help---
NPX LPC31XX architectures (ARM926EJS).
config ARCH_CHIP_LPC43XX
bool "NXP LPC43XX"
select ARCH_CORTEXM4
select ARCH_HAVE_CMNVECTOR
select ARMV7M_CMNVECTOR
select ARCH_HAVE_MPU
select ARCH_HAVE_FPU
---help---
NPX LPC43XX architectures (ARM Cortex-M4).
config ARCH_CHIP_NUC1XX
bool "Nuvoton NUC100/120"
select ARCH_CORTEXM0
select ARCH_HAVE_CMNVECTOR
---help---
NPX LPC43XX architectures (ARM Cortex-M4).
config ARCH_CHIP_SAMA5
bool "Atmel SAMA5"
select ARCH_CORTEXA5
select ARCH_HAVE_FPU
select ARCH_HAVE_LOWVECTORS
select ARCH_HAVE_I2CRESET
select ARCH_HAVE_TICKLESS
select ARCH_HAVE_ADDRENV
select ARCH_NEED_ADDRENV_MAPPING
---help---
Atmel SAMA5 (ARM Cortex-A5)
config ARCH_CHIP_SAMD
bool "Atmel SAMD"
select ARCH_CORTEXM0
select ARCH_HAVE_CMNVECTOR
---help---
Atmel SAMD (ARM Cortex-M0+)
config ARCH_CHIP_SAML
bool "Atmel SAML"
select ARCH_CORTEXM0
select ARCH_HAVE_CMNVECTOR
---help---
Atmel SAML (ARM Cortex-M0+)
config ARCH_CHIP_SAM34
bool "Atmel SAM3/SAM4"
select ARCH_HAVE_CMNVECTOR
select ARCH_HAVE_MPU
select ARCH_HAVE_RAMFUNCS
select ARMV7M_HAVE_STACKCHECK
---help---
Atmel SAM3 (ARM Cortex-M3) and SAM4 (ARM Cortex-M4) architectures
config ARCH_CHIP_SAMV7
bool "Atmel SAMV7"
select ARCH_HAVE_CMNVECTOR
select ARMV7M_CMNVECTOR
select ARCH_CORTEXM7
select ARCH_HAVE_MPU
select ARCH_HAVE_RAMFUNCS
select ARMV7M_HAVE_STACKCHECK
---help---
Atmel SAMV7 (ARM Cortex-M7) architectures
config ARCH_CHIP_STM32
bool "STMicro STM32 F1/F2/F3/F4"
select ARCH_HAVE_CMNVECTOR
select ARCH_HAVE_MPU
select ARCH_HAVE_I2CRESET
select ARCH_HAVE_HEAPCHECK
select ARMV7M_HAVE_STACKCHECK
---help---
STMicro STM32 architectures (ARM Cortex-M3/4).
config ARCH_CHIP_STM32F7
bool "STMicro STM32 F7"
select ARCH_HAVE_CMNVECTOR
select ARMV7M_CMNVECTOR
select ARCH_CORTEXM7
select ARCH_HAVE_MPU
select ARCH_HAVE_I2CRESET
select ARCH_HAVE_HEAPCHECK
select ARMV7M_HAVE_STACKCHECK
---help---
STMicro STM32 architectures (ARM Cortex-M7).
config ARCH_CHIP_STR71X
bool "STMicro STR71x"
select ARCH_ARM7TDMI
select ARCH_HAVE_LOWVECTORS
---help---
STMicro STR71x architectures (ARM7TDMI).
endchoice
config ARCH_ARM7TDMI
bool
default n
config ARCH_ARM926EJS
bool
default n
select ARCH_HAVE_MMU
select ARCH_USE_MMU
config ARCH_ARM920T
bool
default n
select ARCH_HAVE_MMU
select ARCH_USE_MMU
config ARCH_CORTEXM0
bool
default n
select ARCH_HAVE_IRQPRIO
select ARCH_HAVE_RESET
config ARCH_CORTEXM3
bool
default n
select ARCH_HAVE_IRQPRIO
select ARCH_HAVE_RAMVECTORS
select ARCH_HAVE_HIPRI_INTERRUPT
select ARCH_HAVE_RESET
config ARCH_CORTEXM4
bool
default n
select ARCH_HAVE_IRQPRIO
select ARCH_HAVE_RAMVECTORS
select ARCH_HAVE_HIPRI_INTERRUPT
select ARCH_HAVE_RESET
config ARCH_CORTEXM7
bool
default n
select ARCH_HAVE_FPU
select ARCH_HAVE_IRQPRIO
select ARCH_HAVE_RAMVECTORS
select ARCH_HAVE_HIPRI_INTERRUPT
config ARCH_CORTEXA5
bool
default n
select ARCH_HAVE_IRQPRIO
select ARCH_HAVE_MMU
select ARCH_USE_MMU
select ARCH_HAVE_COHERENT_DCACHE if ELF
config ARCH_CORTEXA8
bool
default n
select ARCH_HAVE_IRQPRIO
select ARCH_HAVE_MMU
select ARCH_USE_MMU
select ARCH_HAVE_COHERENT_DCACHE if ELF
config ARCH_FAMILY
string
default "arm" if ARCH_ARM7TDMI || ARCH_ARM926EJS || ARCH_ARM920T
default "armv6-m" if ARCH_CORTEXM0
default "armv7-a" if ARCH_CORTEXA5 || ARCH_CORTEXA8
default "armv7-m" if ARCH_CORTEXM3 || ARCH_CORTEXM4 || ARCH_CORTEXM7
config ARCH_CHIP
string
default "a1x" if ARCH_CHIP_A1X
default "c5471" if ARCH_CHIP_C5471
default "calypso" if ARCH_CHIP_CALYPSO
default "dm320" if ARCH_CHIP_DM320
default "efm32" if ARCH_CHIP_EFM32
default "imx" if ARCH_CHIP_IMX
default "kinetis" if ARCH_CHIP_KINETIS
default "kl" if ARCH_CHIP_KL
default "tiva" if ARCH_CHIP_LM || ARCH_CHIP_TIVA
default "lpc11xx" if ARCH_CHIP_LPC11XX
default "lpc17xx" if ARCH_CHIP_LPC17XX
default "lpc214x" if ARCH_CHIP_LPC214X
default "lpc2378" if ARCH_CHIP_LPC2378
default "lpc31xx" if ARCH_CHIP_LPC31XX
default "lpc43xx" if ARCH_CHIP_LPC43XX
default "nuc1xx" if ARCH_CHIP_NUC1XX
default "sama5" if ARCH_CHIP_SAMA5
default "samdl" if ARCH_CHIP_SAMD || ARCH_CHIP_SAML
default "sam34" if ARCH_CHIP_SAM34
default "samv7" if ARCH_CHIP_SAMV7
default "stm32" if ARCH_CHIP_STM32
default "stm32f7" if ARCH_CHIP_STM32F7
default "str71x" if ARCH_CHIP_STR71X
config ARMV7M_USEBASEPRI
bool "Use BASEPRI Register"
default n
depends on ARCH_CORTEXM3 || ARCH_CORTEXM4 || ARCH_CORTEXM7
---help---
Use the BASEPRI register to enable and disable interrupts. By
default, the PRIMASK register is used for this purpose. This
usually results in hardfaults when supervisor calls are made.
Though, these hardfaults are properly handled by the RTOS, the
hardfaults can confuse some debuggers. With the BASEPRI
register, these hardfaults, will be avoided. For more details see
http://www.nuttx.org/doku.php?id=wiki:nxinternal:svcall
config ARCH_HAVE_CMNVECTOR
bool
config ARMV7M_CMNVECTOR
bool "Use common ARMv7-M vectors"
default n
depends on ARCH_HAVE_CMNVECTOR
---help---
Some architectures use their own, built-in vector logic. Some use only
the common vector logic. Some can use either their own built-in vector
logic or the common vector logic. This applies only to ARMv7-M
architectures.
config ARMV7M_LAZYFPU
bool "Lazy FPU storage"
default n
depends on ARCH_HAVE_CMNVECTOR
---help---
There are two forms of the common vector logic. There are pros and
cons to each option:
1) The standard common vector logic exploits features of the ARMv7-M
architecture to save the all of floating registers on entry into
each interrupt and then to restore the floating registers when
the interrupt returns. The primary advantage to this approach is
that floating point operations are available in interrupt
handling logic. Since the volatile registers are preserved,
operations on the floating point registers by interrupt handling
logic has no ill effect. The downside is, of course, that more
stack operations are required on each interrupt to save and store
the floating point registers. Because of the some special
features of the ARMv-M, this is not as much overhead as you might
expect, but overhead nonetheless.
2) The lazy FPU common vector logic does not save or restore
floating point registers on entry and exit from the interrupt
handler. Rather, the floating point registers are not restored
until it is absolutely necessary to do so when a context switch
occurs and the interrupt handler will be returning to a different
floating point context. Since floating point registers are not
protected, floating point operations must not be performed in
interrupt handling logic. Better interrupt performance is be
expected, however.
By default, the "standard" common vector logic is build. This
option selects the alternate lazy FPU common vector logic.
config ARCH_HAVE_FPU
bool
default n
config ARCH_HAVE_DPFPU
bool
default n
config ARCH_FPU
bool "FPU support"
default y
depends on ARCH_HAVE_FPU
---help---
Build in support for the ARM Cortex-M4 Floating Point Unit (FPU).
Check your chip specifications first; not all Cortex-M4 chips
support the FPU.
config ARCH_DPFPU
bool "Double precision FPU support"
default y
depends on ARCH_FPU && ARCH_HAVE_DPFPU
---help---
Enable toolchain support for double precision (64-bit) floating
point if both the toolchain and the hardware support it.
config ARMV7M_MPU
bool "MPU support"
default n
depends on ARCH_HAVE_MPU
select ARCH_USE_MPU
---help---
Build in support for the ARM Cortex-M3/4 Memory Protection Unit (MPU).
Check your chip specifications first; not all Cortex-M3/4 chips
support the MPU.
config ARMV7M_MPU_NREGIONS
int "Number of MPU regions"
default 8
depends on ARMV7M_MPU
---help---
This is the number of protection regions supported by the MPU.
config ARCH_HAVE_LOWVECTORS
bool
config ARCH_LOWVECTORS
bool "Vectors in low memory"
default n
depends on ARCH_HAVE_LOWVECTORS
---help---
Support ARM vectors in low memory.
config ARCH_ROMPGTABLE
bool "ROM page table"
default n
depends on ARCH_USE_MMU
---help---
Support a fixed memory mapping use a (read-only) page table in ROM/FLASH.
config DEBUG_HARDFAULT
bool "Verbose Hard-Fault Debug"
default n
depends on DEBUG && (ARCH_CORTEXM3 || ARCH_CORTEXM4 || ARCH_CORTEXM7)
---help---
Enables verbose debug output when a hard fault is occurs. This verbose
output is sometimes helpful when debugging difficult hard fault problems,
but may be more than you typcially want to see.
if ARCH_CORTEXM0
source arch/arm/src/armv6-m/Kconfig
endif
if ARCH_CORTEXA5 || ARCH_CORTEXA8
source arch/arm/src/armv7-a/Kconfig
endif
if ARCH_CORTEXM3 || ARCH_CORTEXM4 || ARCH_CORTEXM7
source arch/arm/src/armv7-m/Kconfig
endif
if ARCH_ARM7TDMI || ARCH_ARM926EJS
source arch/arm/src/arm/Kconfig
endif
if ARCH_CHIP_A1X
source arch/arm/src/a1x/Kconfig
endif
if ARCH_CHIP_C5471
source arch/arm/src/c5471/Kconfig
endif
if ARCH_CHIP_CALYPSO
source arch/arm/src/calypso/Kconfig
endif
if ARCH_CHIP_DM320
source arch/arm/src/dm320/Kconfig
endif
if ARCH_CHIP_EFM32
source arch/arm/src/efm32/Kconfig
endif
if ARCH_CHIP_IMX
source arch/arm/src/imx/Kconfig
endif
if ARCH_CHIP_KINETIS
source arch/arm/src/kinetis/Kconfig
endif
if ARCH_CHIP_KL
source arch/arm/src/kl/Kconfig
endif
if ARCH_CHIP_LM || ARCH_CHIP_TIVA
source arch/arm/src/tiva/Kconfig
endif
if ARCH_CHIP_LPC11XX
source arch/arm/src/lpc11xx/Kconfig
endif
if ARCH_CHIP_LPC17XX
source arch/arm/src/lpc17xx/Kconfig
endif
if ARCH_CHIP_LPC214X
source arch/arm/src/lpc214x/Kconfig
endif
if ARCH_CHIP_LPC2378
source arch/arm/src/lpc2378/Kconfig
endif
if ARCH_CHIP_LPC31XX
source arch/arm/src/lpc31xx/Kconfig
endif
if ARCH_CHIP_LPC43XX
source arch/arm/src/lpc43xx/Kconfig
endif
if ARCH_CHIP_NUC1XX
source arch/arm/src/nuc1xx/Kconfig
endif
if ARCH_CHIP_SAMA5
source arch/arm/src/sama5/Kconfig
endif
if ARCH_CHIP_SAMD || ARCH_CHIP_SAML
source arch/arm/src/samdl/Kconfig
endif
if ARCH_CHIP_SAM34
source arch/arm/src/sam34/Kconfig
endif
if ARCH_CHIP_SAMV7
source arch/arm/src/samv7/Kconfig
endif
if ARCH_CHIP_STM32
source arch/arm/src/stm32/Kconfig
endif
if ARCH_CHIP_STM32F7
source arch/arm/src/stm32f7/Kconfig
endif
if ARCH_CHIP_STR71X
source arch/arm/src/str71x/Kconfig
endif
endif

3
arch/arm/include/.gitignore vendored
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@ -1,3 +0,0 @@
/board
/chip

223
arch/arm/include/a1x/a10_irq.h
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@ -1,223 +0,0 @@
/****************************************************************************************
* arch/arm/include/a1x/a10_irq.h
*
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************************/
/* This file should never be included directed but, rather, only indirectly through
* nuttx/irq.h
*/
#ifndef __ARCH_ARM_INCLUDE_A1X_A10_IRQ_H
#define __ARCH_ARM_INCLUDE_A1X_A10_IRQ_H
/****************************************************************************************
* Included Files
****************************************************************************************/
/****************************************************************************************
* Pre-processor Definitions
****************************************************************************************/
/* External interrupts numbers */
#define A1X_IRQ_NMI 0 /* External Non-Mask Interrupt */
# define A1X_IRQ_POWER 0 /* Power module */
# define A1X_IRQ_BATTERY 0 /* Brownout detect */
# define A1X_IRQ_BROWNOUT 0 /* Brownout */
#define A1X_IRQ_UART0 1 /* UART 0 interrupt */
#define A1X_IRQ_UART1 2 /* UART 1 interrupt */
#define A1X_IRQ_UART2 3 /* UART 2 interrupt */
#define A1X_IRQ_UART3 4 /* UART 3 interrupt */
#define A1X_IRQ_IR0 5 /* IR 0 interrupt */
#define A1X_IRQ_IR1 6 /* IR 1 interrupt */
#define A1X_IRQ_TWI0 7 /* TWI 0 interrupt */
#define A1X_IRQ_TWI1 8 /* TWI 1 interrupt */
#define A1X_IRQ_TWI2 9 /* TWI 2 interrupt */
#define A1X_IRQ_SPI0 10 /* SPI 0 interrupt */
#define A1X_IRQ_SPI1 11 /* SPI 1 interrupt */
#define A1X_IRQ_SPI2 12 /* SPI 2 interrupt */
#define A1X_IRQ_NC 13 /* NC */
#define A1X_IRQ_AC97 14 /* AC97 interrupt */
#define A1X_IRQ_TS 15 /* TS interrupt */
#define A1X_IRQ_IIS 16 /* Digital Audio Controller interrupt */
#define A1X_IRQ_UART4 17 /* UART 4 interrupt */
#define A1X_IRQ_UART5 18 /* UART 5 interrupt */
#define A1X_IRQ_UART6 19 /* UART 6 interrupt */
#define A1X_IRQ_UART7 20 /* UART 7 interrupt */
#define A1X_IRQ_KEYPAD 21 /* Keypad interrupt */
#define A1X_IRQ_TIMER0 22 /* Timer port 0 */
#define A1X_IRQ_TIMER1 23 /* Timer port 1 */
#define A1X_IRQ_TIMER2 24 /* Timer 2 */
# define A1X_IRQ_ALARM 24 /* Alarm */
# define A1X_IRQ_WD 24 /* Watchdog */
#define A1X_IRQ_TIMER3 25 /* Timer 3 interrupt */
#define A1X_IRQ_CAN 26 /* CAN Bus controller interrupt */
#define A1X_IRQ_DMA 27 /* DMA channel interrupt */
#define A1X_IRQ_PIO 28 /* PIO interrupt */
#define A1X_IRQ_TOUCH 29 /* Touch Panel interrupt */
#define A1X_IRQ_AUDIO 30 /* Analog Audio Codec interrupt */
#define A1X_IRQ_LRADC 31 /* LRADC interrupt */
#define A1X_IRQ_SDMMC0 32 /* SD/MMC Host Controller 0 interrupt */
#define A1X_IRQ_SDMMC1 33 /* SD/MMC Host Controller 1 interrupt */
#define A1X_IRQ_SDMMC2 34 /* SD/MMC Host Controller 2 interrupt */
#define A1X_IRQ_SDMMC3 35 /* SD/MMC Host Controller 3 interrupt */
#define A1X_IRQ_RESERVED36 36
#define A1X_IRQ_NAND 37 /* NAND Flash Controller (NFC) interrupt */
#define A1X_IRQ_USB0 38 /* USB 0 wakeup, connect, disconnect interrupt */
#define A1X_IRQ_USB1 39 /* USB 1 wakeup, connect, disconnect interrupt */
#define A1X_IRQ_USB2 40 /* USB 2 wakeup, connect, disconnect interrupt */
#define A1X_IRQ_SCR 41 /* SCR interrupt */
#define A1X_IRQ_CSI0 42 /* CSI 0 interrupt */
#define A1X_IRQ_CSI1 43 /* CSI 1 interrupt */
#define A1X_IRQ_LCDC0 44 /* LCD Controller 0 interrupt */
#define A1X_IRQ_LCDC1 45 /* LCD Controller 1 interrupt */
#define A1X_IRQ_MP 46 /* MP interrupt */
#define A1X_IRQ_DEFE0 47 /* DE-FE0 interrupt */
# define A1X_IRQ_DEBE0 47 /* DE-BE0 interrupt */
#define A1X_IRQ_DEFE1 48 /* DE-FE1 interrupt */
# define A1X_IRQ_DEBE1 48 /* DE-BE1 interrupt */
#define A1X_IRQ_PMU 49 /* PMU interrupt */
#define A1X_IRQ_SPI3 50 /* SPI3 interrupt */
#define A1X_IRQ_TZASC 51 /* TZASC interrupt */
#define A1X_IRQ_PATA 52 /* PATA interrupt */
#define A1X_IRQ_VE 53 /* VE interrupt */
#define A1X_IRQ_SS 54 /* Security System interrupt */
#define A1X_IRQ_EMAC 55 /* EMAC interrupt */
#define A1X_IRQ_RESERVED56 56
#define A1X_IRQ_RESERVED57 57
#define A1X_IRQ_HDMI 58 /* HDMI interrupt */
#define A1X_IRQ_TVE 59 /* TV encoder 0/1 interrupt */
#define A1X_IRQ_ACE 60 /* ACE interrupt */
#define A1X_IRQ_TVD 61 /* TV decoder interrupt */
#define A1X_IRQ_PS20 62 /* PS2-0 interrupt */
#define A1X_IRQ_PS21 63 /* PS2-1 interrupt */
#define A1X_IRQ_USB3 64 /* USB 3 wakeup, connect, disconnect interrupt */
#define A1X_IRQ_USB4 65 /* USB 4 wakeup, connect, disconnect interrupt */
#define A1X_IRQ_PLE 66 /* PLE interrupts */
# define A1X_IRQ_PERFMU 66 /* Performance monitor interrupt */
#define A1X_IRQ_TIMER4 67 /* Timer 4 interrupt */
#define A1X_IRQ_TIMER5 68 /* Timer 5 interrupt */
#define A1X_IRQ_GPU_GP 69
#define A1X_IRQ_GPU_GPMMU 70
#define A1X_IRQ_GPU_PP0 71
#define A1X_IRQ_GPU_PPMMU0 72
#define A1X_IRQ_GPU_PMU 73
#define A1X_IRQ_GPU_RSV0 74
#define A1X_IRQ_GPU_RSV1 75
#define A1X_IRQ_GPU_RSV2 76
#define A1X_IRQ_GPU_RSV3 77
#define A1X_IRQ_GPU_RSV4 78
#define A1X_IRQ_GPU_RSV5 79
#define A1X_IRQ_GPU_RSV6 80
/* Total number of interrupts */
#define A1X_IRQ_NINT 81
/* Up to 32 external PIO interrupts */
#ifdef CONFIG_A1X_PIO_IRQ
# define A1X_PIO_EINT0 (A1X_IRQ_NINT+0)
# define A1X_PIO_EINT1 (A1X_IRQ_NINT+1)
# define A1X_PIO_EINT2 (A1X_IRQ_NINT+2)
# define A1X_PIO_EINT3 (A1X_IRQ_NINT+3)
# define A1X_PIO_EINT4 (A1X_IRQ_NINT+4)
# define A1X_PIO_EINT5 (A1X_IRQ_NINT+5)
# define A1X_PIO_EINT6 (A1X_IRQ_NINT+6)
# define A1X_PIO_EINT7 (A1X_IRQ_NINT+7)
# define A1X_PIO_EINT8 (A1X_IRQ_NINT+8)
# define A1X_PIO_EINT9 (A1X_IRQ_NINT+9)
# define A1X_PIO_EINT10 (A1X_IRQ_NINT+10)
# define A1X_PIO_EINT11 (A1X_IRQ_NINT+11)
# define A1X_PIO_EINT12 (A1X_IRQ_NINT+12)
# define A1X_PIO_EINT13 (A1X_IRQ_NINT+13)
# define A1X_PIO_EINT14 (A1X_IRQ_NINT+14)
# define A1X_PIO_EINT15 (A1X_IRQ_NINT+15)
# define A1X_PIO_EINT16 (A1X_IRQ_NINT+16)
# define A1X_PIO_EINT17 (A1X_IRQ_NINT+17)
# define A1X_PIO_EINT18 (A1X_IRQ_NINT+18)
# define A1X_PIO_EINT19 (A1X_IRQ_NINT+19)
# define A1X_PIO_EINT20 (A1X_IRQ_NINT+20)
# define A1X_PIO_EINT21 (A1X_IRQ_NINT+21)
# define A1X_PIO_EINT22 (A1X_IRQ_NINT+22)
# define A1X_PIO_EINT23 (A1X_IRQ_NINT+23)
# define A1X_PIO_EINT24 (A1X_IRQ_NINT+24)
# define A1X_PIO_EINT25 (A1X_IRQ_NINT+25)
# define A1X_PIO_EINT26 (A1X_IRQ_NINT+26)
# define A1X_PIO_EINT27 (A1X_IRQ_NINT+27)
# define A1X_PIO_EINT28 (A1X_IRQ_NINT+28)
# define A1X_PIO_EINT29 (A1X_IRQ_NINT+29)
# define A1X_PIO_EINT30 (A1X_IRQ_NINT+30)
# define A1X_PIO_EINT31 (A1X_IRQ_NINT+31)
# define A1X_PIO_NINT 32
#else
# define A1X_PIO_NINT 0
#endif
/* Total number of IRQ numbers */
#define NR_IRQS (A1X_IRQ_NINT + A1X_PIO_NINT)
/****************************************************************************************
* Public Types
****************************************************************************************/
/****************************************************************************************
* Inline functions
****************************************************************************************/
/****************************************************************************************
* Public Variables
****************************************************************************************/
/****************************************************************************************
* Public Function Prototypes
****************************************************************************************/
#ifndef __ASSEMBLY__
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif
#endif /* __ARCH_ARM_INCLUDE_A1X_A10_IRQ_H */

68
arch/arm/include/a1x/chip.h
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@ -1,68 +0,0 @@
/************************************************************************************
* arch/arm/include/a1x/chip.h
*
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_INCLUDE_A1X_CHIP_H
#define __ARCH_ARM_INCLUDE_A1X_CHIP_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* A1X Family */
#if defined(CONFIG_ARCH_CHIP_A10)
# define ALLWINNER_A1X 1 /* A1X family */
#else
# error Unrecognized A1X chip
#endif
/************************************************************************************
* Public Types
************************************************************************************/
/************************************************************************************
* Public Data
************************************************************************************/
/************************************************************************************
* Public Functions
************************************************************************************/
#endif /* __ARCH_ARM_INCLUDE_A1X_CHIP_H */

91
arch/arm/include/a1x/irq.h
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@ -1,91 +0,0 @@
/****************************************************************************************
* arch/arm/include/a1x/irq.h
*
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************************/
/* This file should never be included directed but, rather, only indirectly through
* nuttx/irq.h
*/
#ifndef __ARCH_ARM_INCLUDE_A1X_IRQ_H
#define __ARCH_ARM_INCLUDE_A1X_IRQ_H
/****************************************************************************************
* Included Files
****************************************************************************************/
#include <nuttx/config.h>
#include <arch/a1x/chip.h>
/****************************************************************************************
* Pre-processor Definitions
****************************************************************************************/
/* Chip-Specific External interrupts */
#if defined(CONFIG_ARCH_CHIP_A10)
# include <arch/a1x/a10_irq.h>
#else
# error Unrecognized A1X chip
#endif
/****************************************************************************************
* Public Types
****************************************************************************************/
#ifndef __ASSEMBLY__
/****************************************************************************************
* Public Data
****************************************************************************************/
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************************
* Public Function Prototypes
****************************************************************************************/
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif
#endif /* __ARCH_ARM_INCLUDE_A1X_IRQ_H */

210
arch/arm/include/arch.h
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@ -1,210 +0,0 @@
/****************************************************************************
* arch/arm/include/arch.h
*
* Copyright (C) 2007-2009, 2014 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/* This file should never be included directed but, rather,
* only indirectly through nuttx/arch.h
*/
#ifndef __ARCH_ARM_INCLUDE_ARCH_H
#define __ARCH_ARM_INCLUDE_ARCH_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#ifndef __ASSEMBLY__
# include <stdint.h>
# include <nuttx/pgalloc.h>
# include <nuttx/addrenv.h>
#endif
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#ifdef CONFIG_PIC
/* This identifies the register the is used by the processor as the PIC base
* register. It is usually r9 or r10
*/
#define PIC_REG r10
#define PIC_REG_STRING "r10"
/* Macros to get and set the PIC base register. picbase is assumed to be
* of type (void*) and that it will fit into a uint32_t. These must be
* inline so that they will be compatible with the ABIs rules for
* preserving the PIC register
*/
#define up_getpicbase(ppicbase) \
do { \
uint32_t picbase; \
__asm__ \
( \
"\tmov %0, " PIC_REG_STRING "\n\t" \
: "=r"(picbase) \
); \
*ppicbase = (FAR void*)picbase; \
} while (0)
#define up_setpicbase(picbase) \
do { \
uint32_t _picbase = (uint32_t)picbase; \
__asm__ \
( \
"\tmov " PIC_REG_STRING ", %0\n\t" \
: : "r"(_picbase) : PIC_REG_STRING \
); \
} while (0)
#endif /* CONFIG_PIC */
#ifdef CONFIG_ARCH_ADDRENV
#if CONFIG_MM_PGSIZE != 4096
# error Only pages sizes of 4096 are currently supported (CONFIG_ARCH_ADDRENV)
#endif
/* Convert 4KiB pages to 1MiB sections */
# define __PG2SECT_SHIFT (20 - MM_PGSHIFT)
# define __PG2SECT_MASK ((1 << __PG2SECT_SHIFT) - 1)
# define ARCH_PG2SECT(p) (((p) + __PG2SECT_MASK) >> __PG2SECT_SHIFT)
# define ARCH_SECT2PG(s) ((s) << __PG2SECT_SHIFT)
# define ARCH_TEXT_NSECTS ARCH_PG2SECT(CONFIG_ARCH_TEXT_NPAGES)
# define ARCH_DATA_NSECTS ARCH_PG2SECT(CONFIG_ARCH_DATA_NPAGES)
# define ARCH_HEAP_NSECTS ARCH_PG2SECT(CONFIG_ARCH_HEAP_NPAGES)
# ifdef CONFIG_MM_SHM
# define ARCH_SHM_NSECTS ARCH_PG2SECT(ARCH_SHM_MAXPAGES)
# endif
# ifdef CONFIG_ARCH_STACK_DYNAMIC
# define ARCH_STACK_NSECTS ARCH_PG2SECT(CONFIG_ARCH_STACK_NPAGES)
# endif
#endif /* CONFIG_ARCH_ADDRENV */
/****************************************************************************
* Inline functions
****************************************************************************/
/****************************************************************************
* Public Types
****************************************************************************/
#ifdef CONFIG_ARCH_ADDRENV
/* The task group resources are retained in a single structure, task_group_s
* that is defined in the header file nuttx/include/nuttx/sched.h. The type
* group_addrenv_t must be defined by platform specific logic in
* nuttx/arch/<architecture>/include/arch.h.
*
* These tables would hold the physical address of the level 2 page tables.
* All would be initially NULL and would not be backed up with physical memory
* until mappings in the level 2 page table are required.
*/
struct group_addrenv_s
{
/* Level 1 page table entries for each group section */
FAR uintptr_t *text[ARCH_TEXT_NSECTS];
FAR uintptr_t *data[ARCH_DATA_NSECTS];
#ifdef CONFIG_BUILD_KERNEL
FAR uintptr_t *heap[ARCH_HEAP_NSECTS];
#ifdef CONFIG_MM_SHM
FAR uintptr_t *shm[ARCH_SHM_NSECTS];
#endif
/* Initial heap allocation (in bytes). This exists only provide an
* indirect path for passing the size of the initial heap to the heap
* initialization logic. These operations are separated in time and
* architecture. REVISIT: I would like a better way to do this.
*/
size_t heapsize;
#endif
};
typedef struct group_addrenv_s group_addrenv_t;
/* This type is used when the OS needs to temporarily instantiate a
* different address environment. Used in the implementation of
*
* int up_addrenv_select(group_addrenv_t addrenv, save_addrenv_t *oldenv);
* int up_addrenv_restore(save_addrenv_t oldenv);
*
* In this case, the saved valued in the L1 page table are returned
*/
struct save_addrenv_s
{
FAR uint32_t text[ARCH_TEXT_NSECTS];
FAR uint32_t data[ARCH_DATA_NSECTS];
#ifdef CONFIG_BUILD_KERNEL
FAR uint32_t heap[ARCH_HEAP_NSECTS];
#ifdef CONFIG_MM_SHM
FAR uint32_t shm[ARCH_SHM_NSECTS];
#endif
#endif
};
typedef struct save_addrenv_s save_addrenv_t;
#endif
/****************************************************************************
* Public Variables
****************************************************************************/
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif /* __ARCH_ARM_INCLUDE_ARCH_H */

231
arch/arm/include/arm/irq.h
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@ -1,231 +0,0 @@
/****************************************************************************
* arch/arm/include/arm/irq.h
*
* Copyright (C) 2009-2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/* This file should never be included directed but, rather, only indirectly
* through nuttx/irq.h
*/
#ifndef __ARCH_ARM_INCLUDE_ARM_IRQ_H
#define __ARCH_ARM_INCLUDE_ARM_IRQ_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/irq.h>
#ifndef __ASSEMBLY__
# include <stdint.h>
#endif
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* IRQ Stack Frame Format:
*
* Context is always saved/restored in the same way:
*
* (1) stmia rx, {r0-r14}
* (2) then the PC and CPSR
*
* This results in the following set of indices that
* can be used to access individual registers in the
* xcp.regs array:
*/
#define REG_R0 (0)
#define REG_R1 (1)
#define REG_R2 (2)
#define REG_R3 (3)
#define REG_R4 (4)
#define REG_R5 (5)
#define REG_R6 (6)
#define REG_R7 (7)
#define REG_R8 (8)
#define REG_R9 (9)
#define REG_R10 (10)
#define REG_R11 (11)
#define REG_R12 (12)
#define REG_R13 (13)
#define REG_R14 (14)
#define REG_R15 (15)
#define REG_CPSR (16)
#define XCPTCONTEXT_REGS (17)
#define XCPTCONTEXT_SIZE (4 * XCPTCONTEXT_REGS)
#define REG_A1 REG_R0
#define REG_A2 REG_R1
#define REG_A3 REG_R2
#define REG_A4 REG_R3
#define REG_V1 REG_R4
#define REG_V2 REG_R5
#define REG_V3 REG_R6
#define REG_V4 REG_R7
#define REG_V5 REG_R8
#define REG_V6 REG_R9
#define REG_V7 REG_R10
#define REG_SB REG_R9
#define REG_SL REG_R10
#define REG_FP REG_R11
#define REG_IP REG_R12
#define REG_SP REG_R13
#define REG_LR REG_R14
#define REG_PC REG_R15
/* The PIC register is usually R10. It can be R9 is stack checking is enabled
* or if the user changes it with -mpic-register on the GCC command line.
*/
#define REG_PIC REG_R10
/****************************************************************************
* Public Types
****************************************************************************/
/* This struct defines the way the registers are stored. We
* need to save:
*
* 1 CPSR
* 7 Static registers, v1-v7 (aka r4-r10)
* 1 Frame pointer, fp (aka r11)
* 1 Stack pointer, sp (aka r13)
* 1 Return address, lr (aka r14)
* ---
* 11 (XCPTCONTEXT_USER_REG)
*
* On interrupts, we also need to save:
* 4 Volatile registers, a1-a4 (aka r0-r3)
* 1 Scratch Register, ip (aka r12)
*---
* 5 (XCPTCONTEXT_IRQ_REGS)
*
* For a total of 17 (XCPTCONTEXT_REGS)
*/
#ifndef __ASSEMBLY__
struct xcptcontext
{
/* The following function pointer is non-zero if there
* are pending signals to be processed.
*/
#ifndef CONFIG_DISABLE_SIGNALS
void *sigdeliver; /* Actual type is sig_deliver_t */
/* These are saved copies of LR and CPSR used during
* signal processing.
*/
uint32_t saved_pc;
uint32_t saved_cpsr;
#endif
/* Register save area */
uint32_t regs[XCPTCONTEXT_REGS];
/* Extra fault address register saved for common paging logic. In the
* case of the prefetch abort, this value is the same as regs[REG_R15];
* For the case of the data abort, this value is the value of the fault
* address register (FAR) at the time of data abort exception.
*/
#ifdef CONFIG_PAGING
uintptr_t far;
#endif
};
#endif
/****************************************************************************
* Inline functions
****************************************************************************/
#ifndef __ASSEMBLY__
/* Save the current interrupt enable state & disable IRQs */
static inline irqstate_t irqsave(void)
{
unsigned int flags;
unsigned int temp;
__asm__ __volatile__
(
"\tmrs %0, cpsr\n"
"\torr %1, %0, #128\n"
"\tmsr cpsr_c, %1"
: "=r" (flags), "=r" (temp)
:
: "memory");
return flags;
}
/* Restore saved IRQ & FIQ state */
static inline void irqrestore(irqstate_t flags)
{
__asm__ __volatile__
(
"msr cpsr_c, %0"
:
: "r" (flags)
: "memory");
}
#endif /* __ASSEMBLY__ */
/****************************************************************************
* Public Variables
****************************************************************************/
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#ifndef __ASSEMBLY__
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif
#endif /* __ARCH_ARM_INCLUDE_ARM_IRQ_H */

244
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@ -1,244 +0,0 @@
/****************************************************************************
* arch/arm/include/arm/syscall.h
*
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/* This file should never be included directed but, rather, only indirectly
* through include/syscall.h or include/sys/sycall.h
*/
#ifndef __ARCH_ARM_INCLUDE_ARM_SYSCALL_H
#define __ARCH_ARM_INCLUDE_ARM_SYSCALL_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#ifndef __ASSEMBLY__
# include <stdint.h>
#endif
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define SYS_syscall 0x900001
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Inline functions
****************************************************************************/
#ifndef __ASSEMBLY__
/* SWI with SYS_ call number and no parameters */
static inline uintptr_t sys_call0(unsigned int nbr)
{
register long reg0 __asm__("r0") = (long)(nbr);
__asm__ __volatile__
(
"swi %1"
: "=r"(reg0)
: "i"(SYS_syscall), "r"(reg0)
: "memory", "r14"
);
return reg0;
}
/* SWI with SYS_ call number and one parameter */
static inline uintptr_t sys_call1(unsigned int nbr, uintptr_t parm1)
{
register long reg0 __asm__("r0") = (long)(nbr);
register long reg1 __asm__("r1") = (long)(parm1);
__asm__ __volatile__
(
"swi %1"
: "=r"(reg0)
: "i"(SYS_syscall), "r"(reg0), "r"(reg1)
: "memory", "r14"
);
return reg0;
}
/* SWI with SYS_ call number and two parameters */
static inline uintptr_t sys_call2(unsigned int nbr, uintptr_t parm1,
uintptr_t parm2)
{
register long reg0 __asm__("r0") = (long)(nbr);
register long reg2 __asm__("r2") = (long)(parm2);
register long reg1 __asm__("r1") = (long)(parm1);
__asm__ __volatile__
(
"swi %1"
: "=r"(reg0)
: "i"(SYS_syscall), "r"(reg0), "r"(reg1), "r"(reg2)
: "memory", "r14"
);
return reg0;
}
/* SWI with SYS_ call number and three parameters */
static inline uintptr_t sys_call3(unsigned int nbr, uintptr_t parm1,
uintptr_t parm2, uintptr_t parm3)
{
register long reg0 __asm__("r0") = (long)(nbr);
register long reg3 __asm__("r3") = (long)(parm3);
register long reg2 __asm__("r2") = (long)(parm2);
register long reg1 __asm__("r1") = (long)(parm1);
__asm__ __volatile__
(
"swi %1"
: "=r"(reg0)
: "i"(SYS_syscall), "r"(reg0), "r"(reg1), "r"(reg2), "r"(reg3)
: "memory", "r14"
);
return reg0;
}
/* SWI with SYS_ call number and four parameters */
static inline uintptr_t sys_call4(unsigned int nbr, uintptr_t parm1,
uintptr_t parm2, uintptr_t parm3,
uintptr_t parm4)
{
register long reg0 __asm__("r0") = (long)(nbr);
register long reg4 __asm__("r4") = (long)(parm4);
register long reg3 __asm__("r3") = (long)(parm3);
register long reg2 __asm__("r2") = (long)(parm2);
register long reg1 __asm__("r1") = (long)(parm1);
__asm__ __volatile__
(
"swi %1"
: "=r"(reg0)
: "i"(SYS_syscall), "r"(reg0), "r"(reg1), "r"(reg2),
"r"(reg3), "r"(reg4)
: "memory", "r14"
);
return reg0;
}
/* SWI with SYS_ call number and five parameters */
static inline uintptr_t sys_call5(unsigned int nbr, uintptr_t parm1,
uintptr_t parm2, uintptr_t parm3,
uintptr_t parm4, uintptr_t parm5)
{
register long reg0 __asm__("r0") = (long)(nbr);
register long reg5 __asm__("r5") = (long)(parm5);
register long reg4 __asm__("r4") = (long)(parm4);
register long reg3 __asm__("r3") = (long)(parm3);
register long reg2 __asm__("r2") = (long)(parm2);
register long reg1 __asm__("r1") = (long)(parm1);
__asm__ __volatile__
(
"swi %1"
: "=r"(reg0)
: "i"(SYS_syscall), "r"(reg0), "r"(reg1), "r"(reg2),
"r"(reg3), "r"(reg4), "r"(reg5)
: "memory", "r14"
);
return reg0;
}
/* SWI with SYS_ call number and six parameters */
static inline uintptr_t sys_call6(unsigned int nbr, uintptr_t parm1,
uintptr_t parm2, uintptr_t parm3,
uintptr_t parm4, uintptr_t parm5,
uintptr_t parm6)
{
register long reg0 __asm__("r0") = (long)(nbr);
register long reg6 __asm__("r6") = (long)(parm6);
register long reg5 __asm__("r5") = (long)(parm5);
register long reg4 __asm__("r4") = (long)(parm4);
register long reg3 __asm__("r3") = (long)(parm3);
register long reg2 __asm__("r2") = (long)(parm2);
register long reg1 __asm__("r1") = (long)(parm1);
__asm__ __volatile__
(
"swi %1"
: "=r"(reg0)
: "i"(SYS_syscall), "r"(reg0), "r"(reg1), "r"(reg2),
"r"(reg3), "r"(reg4), "r"(reg5), "r"(reg6)
: "memory", "r14"
);
return reg0;
}
/****************************************************************************
* Public Variables
****************************************************************************/
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_INCLUDE_ARM_SYSCALL_H */

378
arch/arm/include/armv6-m/irq.h
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@ -1,378 +0,0 @@
/****************************************************************************
* arch/arm/include/armv6-m/irq.h
*
* Copyright (C) 2013-2014 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/* This file should never be included directed but, rather, only indirectly
* through nuttx/irq.h
*/
#ifndef __ARCH_ARM_INCLUDE_ARMV6_M_IRQ_H
#define __ARCH_ARM_INCLUDE_ARMV6_M_IRQ_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/irq.h>
#ifndef __ASSEMBLY__
# include <nuttx/compiler.h>
# include <stdint.h>
#endif
#include <arch/chip/chip.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Configuration ************************************************************/
/* If this is a kernel build, how many nested system calls should we support? */
#ifndef CONFIG_SYS_NNEST
# define CONFIG_SYS_NNEST 2
#endif
/* IRQ Stack Frame Format ***************************************************
*
* The following additional registers are stored by the interrupt handling
* logic.
*/
#define REG_R13 (0) /* R13 = SP at time of interrupt */
#define REG_PRIMASK (1) /* PRIMASK */
#define REG_R4 (2) /* R4 */
#define REG_R5 (3) /* R5 */
#define REG_R6 (4) /* R6 */
#define REG_R7 (5) /* R7 */
#define REG_R8 (6) /* R8 */
#define REG_R9 (7) /* R9 */
#define REG_R10 (8) /* R10 */
#define REG_R11 (9) /* R11 */
/* In the kernel build, we may return to either privileged or unprivileged
* modes.
*/
#ifdef CONFIG_BUILD_PROTECTED
# define REG_EXC_RETURN (10) /* EXC_RETURN */
# define SW_XCPT_REGS (11)
#else
# define SW_XCPT_REGS (10)
#endif
/* The total number of registers saved by software */
#define SW_XCPT_SIZE (4 * SW_XCPT_REGS)
/* On entry into an IRQ, the hardware automatically saves the following
* registers on the stack in this (address) order:
*/
#define REG_R0 (SW_XCPT_REGS+0) /* R0 */
#define REG_R1 (SW_XCPT_REGS+1) /* R1 */
#define REG_R2 (SW_XCPT_REGS+2) /* R2 */
#define REG_R3 (SW_XCPT_REGS+3) /* R3 */
#define REG_R12 (SW_XCPT_REGS+4) /* R12 */
#define REG_R14 (SW_XCPT_REGS+5) /* R14 = LR */
#define REG_R15 (SW_XCPT_REGS+6) /* R15 = PC */
#define REG_XPSR (SW_XCPT_REGS+7) /* xPSR */
#define HW_XCPT_REGS (8)
#define HW_XCPT_SIZE (4 * HW_XCPT_REGS)
#define XCPTCONTEXT_REGS (HW_XCPT_REGS + SW_XCPT_REGS)
#define XCPTCONTEXT_SIZE (4 * XCPTCONTEXT_REGS)
/* Alternate register names */
#define REG_A1 REG_R0
#define REG_A2 REG_R1
#define REG_A3 REG_R2
#define REG_A4 REG_R3
#define REG_V1 REG_R4
#define REG_V2 REG_R5
#define REG_V3 REG_R6
#define REG_V4 REG_R7
#define REG_V5 REG_R8
#define REG_V6 REG_R9
#define REG_V7 REG_R10
#define REG_SB REG_R9
#define REG_SL REG_R10
#define REG_FP REG_R11
#define REG_IP REG_R12
#define REG_SP REG_R13
#define REG_LR REG_R14
#define REG_PC REG_R15
/* The PIC register is usually R10. It can be R9 is stack checking is enabled
* or if the user changes it with -mpic-register on the GCC command line.
*/
#define REG_PIC REG_R10
/****************************************************************************
* Public Types
****************************************************************************/
#ifndef __ASSEMBLY__
/* This structure represents the return state from a system call */
#ifdef CONFIG_LIB_SYSCALL
struct xcpt_syscall_s
{
uint32_t excreturn; /* The EXC_RETURN value */
uint32_t sysreturn; /* The return PC */
};
#endif
/* The following structure is included in the TCB and defines the complete
* state of the thread.
*/
struct xcptcontext
{
#ifndef CONFIG_DISABLE_SIGNALS
/* The following function pointer is non-zero if there
* are pending signals to be processed.
*/
void *sigdeliver; /* Actual type is sig_deliver_t */
/* These are saved copies of LR, PRIMASK, and xPSR used during
* signal processing.
*/
uint32_t saved_pc;
uint32_t saved_primask;
uint32_t saved_xpsr;
#ifdef CONFIG_BUILD_PROTECTED
uint32_t saved_lr;
#endif
# ifdef CONFIG_BUILD_PROTECTED
/* This is the saved address to use when returning from a user-space
* signal handler.
*/
uint32_t sigreturn;
# endif
#endif
#ifdef CONFIG_LIB_SYSCALL
/* The following array holds the return address and the exc_return value
* needed to return from each nested system call.
*/
uint8_t nsyscalls;
struct xcpt_syscall_s syscall[CONFIG_SYS_NNEST];
#endif
/* Register save area */
uint32_t regs[XCPTCONTEXT_REGS];
};
#endif
/****************************************************************************
* Inline functions
****************************************************************************/
#ifndef __ASSEMBLY__
/* Get/set the PRIMASK register */
static inline uint8_t getprimask(void) inline_function;
static inline uint8_t getprimask(void)
{
uint32_t primask;
__asm__ __volatile__
(
"\tmrs %0, primask\n"
: "=r" (primask)
:
: "memory");
return (uint8_t)primask;
}
static inline void setprimask(uint32_t primask) inline_function;
static inline void setprimask(uint32_t primask)
{
__asm__ __volatile__
(
"\tmsr primask, %0\n"
:
: "r" (primask)
: "memory");
}
/* Disable IRQs */
static inline void irqdisable(void) inline_function;
static inline void irqdisable(void)
{
__asm__ __volatile__ ("\tcpsid i\n");
}
/* Save the current primask state & disable IRQs */
static inline irqstate_t irqsave(void) inline_function;
static inline irqstate_t irqsave(void)
{
unsigned short primask;
/* Return the current value of primask register and set
* bit 0 of the primask register to disable interrupts
*/
__asm__ __volatile__
(
"\tmrs %0, primask\n"
"\tcpsid i\n"
: "=r" (primask)
:
: "memory");
return primask;
}
/* Enable IRQs */
static inline void irqenable(void) inline_function;
static inline void irqenable(void)
{
__asm__ __volatile__ ("\tcpsie i\n");
}
/* Restore saved primask state */
static inline void irqrestore(irqstate_t flags) inline_function;
static inline void irqrestore(irqstate_t flags)
{
/* If bit 0 of the primask is 0, then we need to restore
* interrupts.
*/
__asm__ __volatile__
(
"\tmsr primask, %0\n"
:
: "r" (flags)
: "memory");
}
/* Get/set IPSR */
static inline uint32_t getipsr(void) inline_function;
static inline uint32_t getipsr(void)
{
uint32_t ipsr;
__asm__ __volatile__
(
"\tmrs %0, ipsr\n"
: "=r" (ipsr)
:
: "memory");
return ipsr;
}
static inline void setipsr(uint32_t ipsr) inline_function;
static inline void setipsr(uint32_t ipsr)
{
__asm__ __volatile__
(
"\tmsr ipsr, %0\n"
:
: "r" (ipsr)
: "memory");
}
/* Get/set CONTROL */
static inline uint32_t getcontrol(void) inline_function;
static inline uint32_t getcontrol(void)
{
uint32_t control;
__asm__ __volatile__
(
"\tmrs %0, control\n"
: "=r" (control)
:
: "memory");
return control;
}
static inline void setcontrol(uint32_t control) inline_function;
static inline void setcontrol(uint32_t control)
{
__asm__ __volatile__
(
"\tmsr control, %0\n"
:
: "r" (control)
: "memory");
}
#endif /* __ASSEMBLY__ */
/****************************************************************************
* Public Variables
****************************************************************************/
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#ifndef __ASSEMBLY__
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif
#endif /* __ARCH_ARM_INCLUDE_ARMV6_M_IRQ_H */

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arch/arm/include/armv6-m/syscall.h
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@ -1,267 +0,0 @@
/****************************************************************************
* arch/arm/include/armv6-m/syscall.h
*
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/* This file should never be included directed but, rather, only indirectly
* through include/syscall.h or include/sys/sycall.h
*/
#ifndef __ARCH_ARM_INCLUDE_ARMV6_M_SYSCALL_H
#define __ARCH_ARM_INCLUDE_ARMV6_M_SYSCALL_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#ifndef __ASSEMBLY__
# include <stdint.h>
#endif
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* This is the value used as the argument to the SVC instruction. It is not
* used.
*/
#define SYS_syscall 0x00
/* The SYS_signal_handler_return is executed here... its value is not always
* available in this context and so is assumed to be 7.
*/
#ifndef SYS_signal_handler_return
# define SYS_signal_handler_return (7)
#elif SYS_signal_handler_return != 7
# error "SYS_signal_handler_return was assumed to be 7"
#endif
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Inline functions
****************************************************************************/
#ifndef __ASSEMBLY__
/* SVC call with SYS_ call number and no parameters */
static inline uintptr_t sys_call0(unsigned int nbr)
{
register long reg0 __asm__("r0") = (long)(nbr);
__asm__ __volatile__
(
"svc %1"
: "=r"(reg0)
: "i"(SYS_syscall), "r"(reg0)
: "memory"
);
return reg0;
}
/* SVC call with SYS_ call number and one parameter */
static inline uintptr_t sys_call1(unsigned int nbr, uintptr_t parm1)
{
register long reg0 __asm__("r0") = (long)(nbr);
register long reg1 __asm__("r1") = (long)(parm1);
__asm__ __volatile__
(
"svc %1"
: "=r"(reg0)
: "i"(SYS_syscall), "r"(reg0), "r"(reg1)
: "memory"
);
return reg0;
}
/* SVC call with SYS_ call number and two parameters */
static inline uintptr_t sys_call2(unsigned int nbr, uintptr_t parm1,
uintptr_t parm2)
{
register long reg0 __asm__("r0") = (long)(nbr);
register long reg2 __asm__("r2") = (long)(parm2);
register long reg1 __asm__("r1") = (long)(parm1);
__asm__ __volatile__
(
"svc %1"
: "=r"(reg0)
: "i"(SYS_syscall), "r"(reg0), "r"(reg1), "r"(reg2)
: "memory"
);
return reg0;
}
/* SVC call with SYS_ call number and three parameters */
static inline uintptr_t sys_call3(unsigned int nbr, uintptr_t parm1,
uintptr_t parm2, uintptr_t parm3)
{
register long reg0 __asm__("r0") = (long)(nbr);
register long reg3 __asm__("r3") = (long)(parm3);
register long reg2 __asm__("r2") = (long)(parm2);
register long reg1 __asm__("r1") = (long)(parm1);
__asm__ __volatile__
(
"svc %1"
: "=r"(reg0)
: "i"(SYS_syscall), "r"(reg0), "r"(reg1), "r"(reg2), "r"(reg3)
: "memory"
);
return reg0;
}
/* SVC call with SYS_ call number and four parameters.
*
* NOTE the nonstandard parameter passing: parm4 is in R4
*/
static inline uintptr_t sys_call4(unsigned int nbr, uintptr_t parm1,
uintptr_t parm2, uintptr_t parm3,
uintptr_t parm4)
{
register long reg0 __asm__("r0") = (long)(nbr);
register long reg4 __asm__("r4") = (long)(parm4);
register long reg3 __asm__("r3") = (long)(parm3);
register long reg2 __asm__("r2") = (long)(parm2);
register long reg1 __asm__("r1") = (long)(parm1);
__asm__ __volatile__
(
"svc %1"
: "=r"(reg0)
: "i"(SYS_syscall), "r"(reg0), "r"(reg1), "r"(reg2),
"r"(reg3), "r"(reg4)
: "memory"
);
return reg0;
}
/* SVC call with SYS_ call number and five parameters.
*
* NOTE the nonstandard parameter passing: parm4 and parm5 are in R4 and R5
*/
static inline uintptr_t sys_call5(unsigned int nbr, uintptr_t parm1,
uintptr_t parm2, uintptr_t parm3,
uintptr_t parm4, uintptr_t parm5)
{
register long reg0 __asm__("r0") = (long)(nbr);
register long reg5 __asm__("r5") = (long)(parm5);
register long reg4 __asm__("r4") = (long)(parm4);
register long reg3 __asm__("r3") = (long)(parm3);
register long reg2 __asm__("r2") = (long)(parm2);
register long reg1 __asm__("r1") = (long)(parm1);
__asm__ __volatile__
(
"svc %1"
: "=r"(reg0)
: "i"(SYS_syscall), "r"(reg0), "r"(reg1), "r"(reg2),
"r"(reg3), "r"(reg4), "r"(reg5)
: "memory"
);
return reg0;
}
/* SVC call with SYS_ call number and six parameters.
*
* NOTE the nonstandard parameter passing: parm4-parm6 are in R4-R6
*/
static inline uintptr_t sys_call6(unsigned int nbr, uintptr_t parm1,
uintptr_t parm2, uintptr_t parm3,
uintptr_t parm4, uintptr_t parm5,
uintptr_t parm6)
{
register long reg0 __asm__("r0") = (long)(nbr);
register long reg6 __asm__("r6") = (long)(parm6);
register long reg5 __asm__("r5") = (long)(parm5);
register long reg4 __asm__("r4") = (long)(parm4);
register long reg3 __asm__("r3") = (long)(parm3);
register long reg2 __asm__("r2") = (long)(parm2);
register long reg1 __asm__("r1") = (long)(parm1);
__asm__ __volatile__
(
"svc %1"
: "=r"(reg0)
: "i"(SYS_syscall), "r"(reg0), "r"(reg1), "r"(reg2),
"r"(reg3), "r"(reg4), "r"(reg5), "r"(reg6)
: "memory"
);
return reg0;
}
/****************************************************************************
* Public Variables
****************************************************************************/
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_INCLUDE_ARMV6_M_SYSCALL_H */

412
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@ -1,412 +0,0 @@
/****************************************************************************
* arch/arm/include/armv7-a/irq.h
*
* Copyright (C) 2013-2014 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/* This file should never be included directed but, rather, only indirectly
* through nuttx/irq.h
*/
#ifndef __ARCH_ARM_INCLUDE_ARMV7_A_IRQ_H
#define __ARCH_ARM_INCLUDE_ARMV7_A_IRQ_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/irq.h>
#ifndef __ASSEMBLY__
# include <stdint.h>
# include <arch/arch.h>
#endif
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* IRQ Stack Frame Format:
*
* Context is always saved/restored in the same way:
*
* (1) stmia rx, {r0-r14}
* (2) then the PC and CPSR
*
* This results in the following set of indices that can be used to access
* individual registers in the xcp.regs array:
*/
#define REG_R0 (0)
#define REG_R1 (1)
#define REG_R2 (2)
#define REG_R3 (3)
#define REG_R4 (4)
#define REG_R5 (5)
#define REG_R6 (6)
#define REG_R7 (7)
#define REG_R8 (8)
#define REG_R9 (9)
#define REG_R10 (10)
#define REG_R11 (11)
#define REG_R12 (12)
#define REG_R13 (13)
#define REG_R14 (14)
#define REG_R15 (15)
#define REG_CPSR (16)
#define ARM_CONTEXT_REGS (17)
/* If the MCU supports a floating point unit, then it will be necessary
* to save the state of the FPU status register and data registers on
* each context switch. These registers are not saved during interrupt
* level processing, however. So, as a consequence, floating point
* operations may NOT be performed in interrupt handlers.
*
* The FPU provides an extension register file containing 32 single-
* precision registers. These can be viewed as:
*
* - Sixteen 64-bit double word registers, D0-D15
* - Thirty-two 32-bit single-word registers, S0-S31
* S<2n> maps to the least significant half of D<n>
* S<2n+1> maps to the most significant half of D<n>.
*/
#ifdef CONFIG_ARCH_FPU
# define REG_D0 (ARM_CONTEXT_REGS+0) /* D0 */
# define REG_S0 (ARM_CONTEXT_REGS+0) /* S0 */
# define REG_S1 (ARM_CONTEXT_REGS+1) /* S1 */
# define REG_D1 (ARM_CONTEXT_REGS+2) /* D1 */
# define REG_S2 (ARM_CONTEXT_REGS+2) /* S2 */
# define REG_S3 (ARM_CONTEXT_REGS+3) /* S3 */
# define REG_D2 (ARM_CONTEXT_REGS+4) /* D2 */
# define REG_S4 (ARM_CONTEXT_REGS+4) /* S4 */
# define REG_S5 (ARM_CONTEXT_REGS+5) /* S5 */
# define REG_D3 (ARM_CONTEXT_REGS+6) /* D3 */
# define REG_S6 (ARM_CONTEXT_REGS+6) /* S6 */
# define REG_S7 (ARM_CONTEXT_REGS+7) /* S7 */
# define REG_D4 (ARM_CONTEXT_REGS+8) /* D4 */
# define REG_S8 (ARM_CONTEXT_REGS+8) /* S8 */
# define REG_S9 (ARM_CONTEXT_REGS+9) /* S9 */
# define REG_D5 (ARM_CONTEXT_REGS+10) /* D5 */
# define REG_S10 (ARM_CONTEXT_REGS+10) /* S10 */
# define REG_S11 (ARM_CONTEXT_REGS+11) /* S11 */
# define REG_D6 (ARM_CONTEXT_REGS+12) /* D6 */
# define REG_S12 (ARM_CONTEXT_REGS+12) /* S12 */
# define REG_S13 (ARM_CONTEXT_REGS+13) /* S13 */
# define REG_D7 (ARM_CONTEXT_REGS+14) /* D7 */
# define REG_S14 (ARM_CONTEXT_REGS+14) /* S14 */
# define REG_S15 (ARM_CONTEXT_REGS+15) /* S15 */
# define REG_D8 (ARM_CONTEXT_REGS+16) /* D8 */
# define REG_S16 (ARM_CONTEXT_REGS+16) /* S16 */
# define REG_S17 (ARM_CONTEXT_REGS+17) /* S17 */
# define REG_D9 (ARM_CONTEXT_REGS+18) /* D9 */
# define REG_S18 (ARM_CONTEXT_REGS+18) /* S18 */
# define REG_S19 (ARM_CONTEXT_REGS+19) /* S19 */
# define REG_D10 (ARM_CONTEXT_REGS+20) /* D10 */
# define REG_S20 (ARM_CONTEXT_REGS+20) /* S20 */
# define REG_S21 (ARM_CONTEXT_REGS+21) /* S21 */
# define REG_D11 (ARM_CONTEXT_REGS+22) /* D11 */
# define REG_S22 (ARM_CONTEXT_REGS+22) /* S22 */
# define REG_S23 (ARM_CONTEXT_REGS+23) /* S23 */
# define REG_D12 (ARM_CONTEXT_REGS+24) /* D12 */
# define REG_S24 (ARM_CONTEXT_REGS+24) /* S24 */
# define REG_S25 (ARM_CONTEXT_REGS+25) /* S25 */
# define REG_D13 (ARM_CONTEXT_REGS+26) /* D13 */
# define REG_S26 (ARM_CONTEXT_REGS+26) /* S26 */
# define REG_S27 (ARM_CONTEXT_REGS+27) /* S27 */
# define REG_D14 (ARM_CONTEXT_REGS+28) /* D14 */
# define REG_S28 (ARM_CONTEXT_REGS+28) /* S28 */
# define REG_S29 (ARM_CONTEXT_REGS+29) /* S29 */
# define REG_D15 (ARM_CONTEXT_REGS+30) /* D15 */
# define REG_S30 (ARM_CONTEXT_REGS+30) /* S30 */
# define REG_S31 (ARM_CONTEXT_REGS+31) /* S31 */
# define REG_FPSCR (ARM_CONTEXT_REGS+32) /* Floating point status and control */
# define FPU_CONTEXT_REGS (33)
#else
# define FPU_CONTEXT_REGS (0)
#endif
/* The total number of registers saved by software */
#define XCPTCONTEXT_REGS (ARM_CONTEXT_REGS + FPU_CONTEXT_REGS)
#define XCPTCONTEXT_SIZE (4 * XCPTCONTEXT_REGS)
/* Friendly register names */
#define REG_A1 REG_R0
#define REG_A2 REG_R1
#define REG_A3 REG_R2
#define REG_A4 REG_R3
#define REG_V1 REG_R4
#define REG_V2 REG_R5
#define REG_V3 REG_R6
#define REG_V4 REG_R7
#define REG_V5 REG_R8
#define REG_V6 REG_R9
#define REG_V7 REG_R10
#define REG_SB REG_R9
#define REG_SL REG_R10
#define REG_FP REG_R11
#define REG_IP REG_R12
#define REG_SP REG_R13
#define REG_LR REG_R14
#define REG_PC REG_R15
/* The PIC register is usually R10. It can be R9 is stack checking is enabled
* or if the user changes it with -mpic-register on the GCC command line.
*/
#define REG_PIC REG_R10
/****************************************************************************
* Public Types
****************************************************************************/
#ifndef __ASSEMBLY__
/* This structure represents the return state from a system call */
#ifdef CONFIG_LIB_SYSCALL
struct xcpt_syscall_s
{
#ifdef CONFIG_BUILD_KERNEL
uint32_t cpsr; /* The CPSR value */
#endif
uint32_t sysreturn; /* The return PC */
};
#endif
/* This struct defines the way the registers are stored. We need to save:
*
* 1 CPSR
* 7 Static registers, v1-v7 (aka r4-r10)
* 1 Frame pointer, fp (aka r11)
* 1 Stack pointer, sp (aka r13)
* 1 Return address, lr (aka r14)
* ---
* 11 (XCPTCONTEXT_USER_REG)
*
* On interrupts, we also need to save:
* 4 Volatile registers, a1-a4 (aka r0-r3)
* 1 Scratch Register, ip (aka r12)
*---
* 5 (XCPTCONTEXT_IRQ_REGS)
*
* For a total of 17 (XCPTCONTEXT_REGS)
*/
#ifndef __ASSEMBLY__
struct xcptcontext
{
/* The following function pointer is non-zero if there are pending signals
* to be processed.
*/
#ifndef CONFIG_DISABLE_SIGNALS
void *sigdeliver; /* Actual type is sig_deliver_t */
/* These are saved copies of LR and CPSR used during signal processing. */
uint32_t saved_pc;
uint32_t saved_cpsr;
# ifdef CONFIG_BUILD_KERNEL
/* This is the saved address to use when returning from a user-space
* signal handler.
*/
uint32_t sigreturn;
# endif
#endif
/* Register save area */
uint32_t regs[XCPTCONTEXT_REGS];
/* Extra fault address register saved for common paging logic. In the
* case of the pre-fetch abort, this value is the same as regs[REG_R15];
* For the case of the data abort, this value is the value of the fault
* address register (FAR) at the time of data abort exception.
*/
#ifdef CONFIG_PAGING
uintptr_t far;
#endif
#ifdef CONFIG_LIB_SYSCALL
/* The following array holds the return address and the exc_return value
* needed to return from each nested system call.
*/
uint8_t nsyscalls;
struct xcpt_syscall_s syscall[CONFIG_SYS_NNEST];
#endif
#ifdef CONFIG_ARCH_ADDRENV
#ifdef CONFIG_ARCH_STACK_DYNAMIC
/* This array holds the physical address of the level 2 page table used
* to map the thread's stack memory. This array will be initially of
* zeroed and would be back-up up with pages during page fault exception
* handling to support dynamically sized stacks for each thread.
*/
FAR uintptr_t *ustack[ARCH_STACK_NSECTS];
#endif
#ifdef CONFIG_ARCH_KERNEL_STACK
/* In this configuration, all syscalls execute from an internal kernel
* stack. Why? Because when we instantiate and initialize the address
* environment of the new user process, we will temporarily lose the
* address environment of the old user process, including its stack
* contents. The kernel C logic will crash immediately with no valid
* stack in place.
*/
FAR uint32_t *ustkptr; /* Saved user stack pointer */
FAR uint32_t *kstack; /* Allocate base of the (aligned) kernel stack */
#ifndef CONFIG_DISABLE_SIGNALS
FAR uint32_t *kstkptr; /* Saved kernel stack pointer */
#endif
#endif
#endif
};
#endif
#endif /* __ASSEMBLY__ */
/****************************************************************************
* Inline functions
****************************************************************************/
#ifndef __ASSEMBLY__
/* Return the current IRQ state */
static inline irqstate_t irqstate(void)
{
unsigned int cpsr;
__asm__ __volatile__
(
"\tmrs %0, cpsr\n"
: "=r" (cpsr)
:
: "memory"
);
return cpsr;
}
/* Disable IRQs and return the previous IRQ state */
static inline irqstate_t irqsave(void)
{
unsigned int cpsr;
__asm__ __volatile__
(
"\tmrs %0, cpsr\n"
"\tcpsid i\n"
#if defined(CONFIG_ARMV7A_DECODEFIQ)
"\tcpsid f\n"
#endif
: "=r" (cpsr)
:
: "memory"
);
return cpsr;
}
/* Enable IRQs and return the previous IRQ state */
static inline irqstate_t irqenable(void)
{
unsigned int cpsr;
__asm__ __volatile__
(
"\tmrs %0, cpsr\n"
"\tcpsie i\n"
#if defined(CONFIG_ARMV7A_DECODEFIQ)
"\tcpsie f\n"
#endif
: "=r" (cpsr)
:
: "memory"
);
return cpsr;
}
/* Restore saved IRQ & FIQ state */
static inline void irqrestore(irqstate_t flags)
{
__asm__ __volatile__
(
"msr cpsr_c, %0"
:
: "r" (flags)
: "memory"
);
}
#endif /* __ASSEMBLY__ */
/****************************************************************************
* Public Variables
****************************************************************************/
#ifndef __ASSEMBLY__
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif
#endif /* __ARCH_ARM_INCLUDE_ARMV7_A_IRQ_H */

243
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@ -1,243 +0,0 @@
/****************************************************************************
* arch/arm/include/armv-7a/syscall.h
*
* Copyright (C) 2014 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/* This file should never be included directed but, rather, only indirectly
* through include/syscall.h or include/sys/sycall.h
*/
#ifndef __ARCH_ARM_INCLUDE_ARMV7_A_SYSCALL_H
#define __ARCH_ARM_INCLUDE_ARMV7_A_SYSCALL_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#ifndef __ASSEMBLY__
# include <stdint.h>
#endif
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define SYS_syscall 0x900001
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Inline functions
****************************************************************************/
#ifndef __ASSEMBLY__
/* SVC with SYS_ call number and no parameters */
static inline uintptr_t sys_call0(unsigned int nbr)
{
register long reg0 __asm__("r0") = (long)(nbr);
__asm__ __volatile__
(
"svc %1"
: "=r"(reg0)
: "i"(SYS_syscall), "r"(reg0)
: "memory", "r14"
);
return reg0;
}
/* SVC with SYS_ call number and one parameter */
static inline uintptr_t sys_call1(unsigned int nbr, uintptr_t parm1)
{
register long reg0 __asm__("r0") = (long)(nbr);
register long reg1 __asm__("r1") = (long)(parm1);
__asm__ __volatile__
(
"svc %1"
: "=r"(reg0)
: "i"(SYS_syscall), "r"(reg0), "r"(reg1)
: "memory", "r14"
);
return reg0;
}
/* SVC with SYS_ call number and two parameters */
static inline uintptr_t sys_call2(unsigned int nbr, uintptr_t parm1,
uintptr_t parm2)
{
register long reg0 __asm__("r0") = (long)(nbr);
register long reg2 __asm__("r2") = (long)(parm2);
register long reg1 __asm__("r1") = (long)(parm1);
__asm__ __volatile__
(
"svc %1"
: "=r"(reg0)
: "i"(SYS_syscall), "r"(reg0), "r"(reg1), "r"(reg2)
: "memory", "r14"
);
return reg0;
}
/* SVC with SYS_ call number and three parameters */
static inline uintptr_t sys_call3(unsigned int nbr, uintptr_t parm1,
uintptr_t parm2, uintptr_t parm3)
{
register long reg0 __asm__("r0") = (long)(nbr);
register long reg3 __asm__("r3") = (long)(parm3);
register long reg2 __asm__("r2") = (long)(parm2);
register long reg1 __asm__("r1") = (long)(parm1);
__asm__ __volatile__
(
"svc %1"
: "=r"(reg0)
: "i"(SYS_syscall), "r"(reg0), "r"(reg1), "r"(reg2), "r"(reg3)
: "memory", "r14"
);
return reg0;
}
/* SVC with SYS_ call number and four parameters */
static inline uintptr_t sys_call4(unsigned int nbr, uintptr_t parm1,
uintptr_t parm2, uintptr_t parm3,
uintptr_t parm4)
{
register long reg0 __asm__("r0") = (long)(nbr);
register long reg4 __asm__("r4") = (long)(parm4);
register long reg3 __asm__("r3") = (long)(parm3);
register long reg2 __asm__("r2") = (long)(parm2);
register long reg1 __asm__("r1") = (long)(parm1);
__asm__ __volatile__
(
"svc %1"
: "=r"(reg0)
: "i"(SYS_syscall), "r"(reg0), "r"(reg1), "r"(reg2),
"r"(reg3), "r"(reg4)
: "memory", "r14"
);
return reg0;
}
/* SVC with SYS_ call number and five parameters */
static inline uintptr_t sys_call5(unsigned int nbr, uintptr_t parm1,
uintptr_t parm2, uintptr_t parm3,
uintptr_t parm4, uintptr_t parm5)
{
register long reg0 __asm__("r0") = (long)(nbr);
register long reg5 __asm__("r5") = (long)(parm5);
register long reg4 __asm__("r4") = (long)(parm4);
register long reg3 __asm__("r3") = (long)(parm3);
register long reg2 __asm__("r2") = (long)(parm2);
register long reg1 __asm__("r1") = (long)(parm1);
__asm__ __volatile__
(
"svc %1"
: "=r"(reg0)
: "i"(SYS_syscall), "r"(reg0), "r"(reg1), "r"(reg2),
"r"(reg3), "r"(reg4), "r"(reg5)
: "memory", "r14"
);
return reg0;
}
/* SVC with SYS_ call number and six parameters */
static inline uintptr_t sys_call6(unsigned int nbr, uintptr_t parm1,
uintptr_t parm2, uintptr_t parm3,
uintptr_t parm4, uintptr_t parm5,
uintptr_t parm6)
{
register long reg0 __asm__("r0") = (long)(nbr);
register long reg6 __asm__("r6") = (long)(parm6);
register long reg5 __asm__("r5") = (long)(parm5);
register long reg4 __asm__("r4") = (long)(parm4);
register long reg3 __asm__("r3") = (long)(parm3);
register long reg2 __asm__("r2") = (long)(parm2);
register long reg1 __asm__("r1") = (long)(parm1);
__asm__ __volatile__
(
"svc %1"
: "=r"(reg0)
: "i"(SYS_syscall), "r"(reg0), "r"(reg1), "r"(reg2),
"r"(reg3), "r"(reg4), "r"(reg5), "r"(reg6)
: "memory", "r14"
);
return reg0;
}
/****************************************************************************
* Public Variables
****************************************************************************/
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_INCLUDE_ARMV7_A_SYSCALL_H */

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@ -1,394 +0,0 @@
/****************************************************************************
* arch/arm/include/armv7-m/irq.h
*
* Copyright (C) 2009, 2011-2012, 2014 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/* This file should never be included directed but, rather, only indirectly
* through nuttx/irq.h
*/
#ifndef __ARCH_ARM_INCLUDE_ARMV7_M_IRQ_H
#define __ARCH_ARM_INCLUDE_ARMV7_M_IRQ_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/irq.h>
#ifndef __ASSEMBLY__
# include <nuttx/compiler.h>
# include <stdint.h>
#endif
/* Included implementation-dependent register save structure layouts */
#if defined(CONFIG_ARMV7M_CMNVECTOR) && !defined(CONFIG_ARMV7M_LAZYFPU)
# include <arch/armv7-m/irq_cmnvector.h>
#else
# include <arch/armv7-m/irq_lazyfpu.h>
#endif
#ifdef CONFIG_ARMV7M_USEBASEPRI
# include <arch/chip/chip.h>
#endif
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Configuration ************************************************************/
/* If this is a kernel build, how many nested system calls should we support? */
#ifndef CONFIG_SYS_NNEST
# define CONFIG_SYS_NNEST 2
#endif
/* Alternate register names *************************************************/
#define REG_A1 REG_R0
#define REG_A2 REG_R1
#define REG_A3 REG_R2
#define REG_A4 REG_R3
#define REG_V1 REG_R4
#define REG_V2 REG_R5
#define REG_V3 REG_R6
#define REG_V4 REG_R7
#define REG_V5 REG_R8
#define REG_V6 REG_R9
#define REG_V7 REG_R10
#define REG_SB REG_R9
#define REG_SL REG_R10
#define REG_FP REG_R11
#define REG_IP REG_R12
#define REG_SP REG_R13
#define REG_LR REG_R14
#define REG_PC REG_R15
/* The PIC register is usually R10. It can be R9 is stack checking is enabled
* or if the user changes it with -mpic-register on the GCC command line.
*/
#define REG_PIC REG_R10
/****************************************************************************
* Public Types
****************************************************************************/
#ifndef __ASSEMBLY__
/* This structure represents the return state from a system call */
#ifdef CONFIG_LIB_SYSCALL
struct xcpt_syscall_s
{
uint32_t excreturn; /* The EXC_RETURN value */
uint32_t sysreturn; /* The return PC */
};
#endif
/* The following structure is included in the TCB and defines the complete
* state of the thread.
*/
struct xcptcontext
{
#ifndef CONFIG_DISABLE_SIGNALS
/* The following function pointer is non-zero if there
* are pending signals to be processed.
*/
void *sigdeliver; /* Actual type is sig_deliver_t */
/* These are saved copies of LR, PRIMASK, and xPSR used during
* signal processing.
*/
uint32_t saved_pc;
#ifdef CONFIG_ARMV7M_USEBASEPRI
uint32_t saved_basepri;
#else
uint32_t saved_primask;
#endif
uint32_t saved_xpsr;
#ifdef CONFIG_BUILD_PROTECTED
uint32_t saved_lr;
#endif
# ifdef CONFIG_BUILD_PROTECTED
/* This is the saved address to use when returning from a user-space
* signal handler.
*/
uint32_t sigreturn;
# endif
#endif
#ifdef CONFIG_LIB_SYSCALL
/* The following array holds the return address and the exc_return value
* needed to return from each nested system call.
*/
uint8_t nsyscalls;
struct xcpt_syscall_s syscall[CONFIG_SYS_NNEST];
#endif
/* Register save area */
uint32_t regs[XCPTCONTEXT_REGS];
};
#endif
/****************************************************************************
* Inline functions
****************************************************************************/
#ifndef __ASSEMBLY__
/* Get/set the PRIMASK register */
static inline uint8_t getprimask(void) inline_function;
static inline uint8_t getprimask(void)
{
uint32_t primask;
__asm__ __volatile__
(
"\tmrs %0, primask\n"
: "=r" (primask)
:
: "memory");
return (uint8_t)primask;
}
static inline void setprimask(uint32_t primask) inline_function;
static inline void setprimask(uint32_t primask)
{
__asm__ __volatile__
(
"\tmsr primask, %0\n"
:
: "r" (primask)
: "memory");
}
/* Get/set the BASEPRI register. The BASEPRI register defines the minimum
* priority for exception processing. When BASEPRI is set to a nonzero
* value, it prevents the activation of all exceptions with the same or
* lower priority level as the BASEPRI value.
*/
static inline uint8_t getbasepri(void) inline_function;
static inline uint8_t getbasepri(void)
{
uint32_t basepri;
__asm__ __volatile__
(
"\tmrs %0, basepri\n"
: "=r" (basepri)
:
: "memory");
return (uint8_t)basepri;
}
static inline void setbasepri(uint32_t basepri) inline_function;
static inline void setbasepri(uint32_t basepri)
{
__asm__ __volatile__
(
"\tmsr basepri, %0\n"
:
: "r" (basepri)
: "memory");
}
/* Disable IRQs */
static inline void irqdisable(void) inline_function;
static inline void irqdisable(void)
{
#ifdef CONFIG_ARMV7M_USEBASEPRI
setbasepri(NVIC_SYSH_DISABLE_PRIORITY);
#else
__asm__ __volatile__ ("\tcpsid i\n");
#endif
}
/* Save the current primask state & disable IRQs */
static inline irqstate_t irqsave(void) inline_function;
static inline irqstate_t irqsave(void)
{
#ifdef CONFIG_ARMV7M_USEBASEPRI
uint8_t basepri = getbasepri();
setbasepri(NVIC_SYSH_DISABLE_PRIORITY);
return (irqstate_t)basepri;
#else
unsigned short primask;
/* Return the current value of primask register and set
* bit 0 of the primask register to disable interrupts
*/
__asm__ __volatile__
(
"\tmrs %0, primask\n"
"\tcpsid i\n"
: "=r" (primask)
:
: "memory");
return primask;
#endif
}
/* Enable IRQs */
static inline void irqenable(void) inline_function;
static inline void irqenable(void)
{
setbasepri(0);
__asm__ __volatile__ ("\tcpsie i\n");
}
/* Restore saved primask state */
static inline void irqrestore(irqstate_t flags) inline_function;
static inline void irqrestore(irqstate_t flags)
{
#ifdef CONFIG_ARMV7M_USEBASEPRI
setbasepri((uint32_t)flags);
#else
/* If bit 0 of the primask is 0, then we need to restore
* interrupts.
*/
__asm__ __volatile__
(
"\ttst %0, #1\n"
"\tbne.n 1f\n"
"\tcpsie i\n"
"1:\n"
:
: "r" (flags)
: "memory");
#endif
}
/* Get/set IPSR */
static inline uint32_t getipsr(void) inline_function;
static inline uint32_t getipsr(void)
{
uint32_t ipsr;
__asm__ __volatile__
(
"\tmrs %0, ipsr\n"
: "=r" (ipsr)
:
: "memory");
return ipsr;
}
static inline void setipsr(uint32_t ipsr) inline_function;
static inline void setipsr(uint32_t ipsr)
{
__asm__ __volatile__
(
"\tmsr ipsr, %0\n"
:
: "r" (ipsr)
: "memory");
}
/* Get/set CONTROL */
static inline uint32_t getcontrol(void) inline_function;
static inline uint32_t getcontrol(void)
{
uint32_t control;
__asm__ __volatile__
(
"\tmrs %0, control\n"
: "=r" (control)
:
: "memory");
return control;
}
static inline void setcontrol(uint32_t control) inline_function;
static inline void setcontrol(uint32_t control)
{
__asm__ __volatile__
(
"\tmsr control, %0\n"
:
: "r" (control)
: "memory");
}
#endif /* __ASSEMBLY__ */
/****************************************************************************
* Public Variables
****************************************************************************/
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#ifndef __ASSEMBLY__
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif
#endif /* __ARCH_ARM_INCLUDE_ARMV7_M_IRQ_H */

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arch/arm/include/armv7-m/irq_cmnvector.h
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@ -1,168 +0,0 @@
/****************************************************************************
* arch/arm/include/armv7-m/irq_cmnvector.h
*
* Copyright (C) 2012 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
#ifndef __ARCH_ARM_INCLUDE_ARMV7_M_IRQ_CMNVECTOR_H
#define __ARCH_ARM_INCLUDE_ARMV7_M_IRQ_CMNVECTOR_H
/****************************************************************************
* Included Files
****************************************************************************/
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* IRQ Stack Frame Format: */
/* The following additional registers are stored by the interrupt handling
* logic.
*/
#define REG_R13 (0) /* R13 = SP at time of interrupt */
#ifdef CONFIG_ARMV7M_USEBASEPRI
# define REG_BASEPRI (1) /* BASEPRI */
#else
# define REG_PRIMASK (1) /* PRIMASK */
#endif
#define REG_R4 (2) /* R4 */
#define REG_R5 (3) /* R5 */
#define REG_R6 (4) /* R6 */
#define REG_R7 (5) /* R7 */
#define REG_R8 (6) /* R8 */
#define REG_R9 (7) /* R9 */
#define REG_R10 (8) /* R10 */
#define REG_R11 (9) /* R11 */
#define REG_EXC_RETURN (10) /* EXC_RETURN */
#define SW_INT_REGS (11)
#ifdef CONFIG_ARCH_FPU
/* If the MCU supports a floating point unit, then it will be necessary
* to save the state of the non-volatile registers before calling code
* that may save and overwrite them.
*/
# define REG_S16 (SW_INT_REGS+0) /* S16 */
# define REG_S17 (SW_INT_REGS+1) /* S17 */
# define REG_S18 (SW_INT_REGS+2) /* S18 */
# define REG_S19 (SW_INT_REGS+3) /* S19 */
# define REG_S20 (SW_INT_REGS+4) /* S20 */
# define REG_S21 (SW_INT_REGS+5) /* S21 */
# define REG_S22 (SW_INT_REGS+6) /* S22 */
# define REG_S23 (SW_INT_REGS+7) /* S23 */
# define REG_S24 (SW_INT_REGS+8) /* S24 */
# define REG_S25 (SW_INT_REGS+9) /* S25 */
# define REG_S26 (SW_INT_REGS+10) /* S26 */
# define REG_S27 (SW_INT_REGS+11) /* S27 */
# define REG_S28 (SW_INT_REGS+12) /* S28 */
# define REG_S29 (SW_INT_REGS+13) /* S29 */
# define REG_S30 (SW_INT_REGS+14) /* S30 */
# define REG_S31 (SW_INT_REGS+15) /* S31 */
# define SW_FPU_REGS (16)
#else
# define SW_FPU_REGS (0)
#endif
/* The total number of registers saved by software */
#define SW_XCPT_REGS (SW_INT_REGS + SW_FPU_REGS)
#define SW_XCPT_SIZE (4 * SW_XCPT_REGS)
/* On entry into an IRQ, the hardware automatically saves the following
* registers on the stack in this (address) order:
*/
#define REG_R0 (SW_XCPT_REGS+0) /* R0 */
#define REG_R1 (SW_XCPT_REGS+1) /* R1 */
#define REG_R2 (SW_XCPT_REGS+2) /* R2 */
#define REG_R3 (SW_XCPT_REGS+3) /* R3 */
#define REG_R12 (SW_XCPT_REGS+4) /* R12 */
#define REG_R14 (SW_XCPT_REGS+5) /* R14 = LR */
#define REG_R15 (SW_XCPT_REGS+6) /* R15 = PC */
#define REG_XPSR (SW_XCPT_REGS+7) /* xPSR */
#define HW_INT_REGS (8)
#ifdef CONFIG_ARCH_FPU
/* If the FPU is enabled, the hardware also saves the volatile FP registers.
*/
# define REG_S0 (SW_XCPT_REGS+8) /* S0 */
# define REG_S1 (SW_XCPT_REGS+9) /* S1 */
# define REG_S2 (SW_XCPT_REGS+10) /* S2 */
# define REG_S3 (SW_XCPT_REGS+11) /* S3 */
# define REG_S4 (SW_XCPT_REGS+12) /* S4 */
# define REG_S5 (SW_XCPT_REGS+13) /* S5 */
# define REG_S6 (SW_XCPT_REGS+14) /* S6 */
# define REG_S7 (SW_XCPT_REGS+15) /* S7 */
# define REG_S8 (SW_XCPT_REGS+16) /* S8 */
# define REG_S9 (SW_XCPT_REGS+17) /* S9 */
# define REG_S10 (SW_XCPT_REGS+18) /* S10 */
# define REG_S11 (SW_XCPT_REGS+19) /* S11 */
# define REG_S12 (SW_XCPT_REGS+20) /* S12 */
# define REG_S13 (SW_XCPT_REGS+21) /* S13 */
# define REG_S14 (SW_XCPT_REGS+22) /* S14 */
# define REG_S15 (SW_XCPT_REGS+23) /* S15 */
# define REG_FPSCR (SW_XCPT_REGS+24) /* FPSCR */
# define REG_FPReserved (SW_XCPT_REGS+25) /* Reserved */
# define HW_FPU_REGS (18)
#else
# define HW_FPU_REGS (0)
#endif
#define HW_XCPT_REGS (HW_INT_REGS + HW_FPU_REGS)
#define HW_XCPT_SIZE (4 * HW_XCPT_REGS)
#define XCPTCONTEXT_REGS (HW_XCPT_REGS + SW_XCPT_REGS)
#define XCPTCONTEXT_SIZE (4 * XCPTCONTEXT_REGS)
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Inline functions
****************************************************************************/
/****************************************************************************
* Public Variables
****************************************************************************/
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_INCLUDE_ARMV7_M_IRQ_CMNVECTOR_H */

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arch/arm/include/armv7-m/irq_lazyfpu.h
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@ -1,186 +0,0 @@
/****************************************************************************
* arch/arm/include/armv7-m/irq_lazyfpu.h
*
* Copyright (C) 2009, 2011-2012 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
#ifndef __ARCH_ARM_INCLUDE_ARMV7_M_IRQ_LAZYFPU_H
#define __ARCH_ARM_INCLUDE_ARMV7_M_IRQ_LAZYFPU_H
/****************************************************************************
* Included Files
****************************************************************************/
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* IRQ Stack Frame Format: */
/* The following additional registers are stored by the interrupt handling
* logic.
*/
#define REG_R13 (0) /* R13 = SP at time of interrupt */
#ifdef CONFIG_ARMV7M_USEBASEPRI
# define REG_BASEPRI (1) /* BASEPRI */
#else
# define REG_PRIMASK (1) /* PRIMASK */
#endif
#define REG_R4 (2) /* R4 */
#define REG_R5 (3) /* R5 */
#define REG_R6 (4) /* R6 */
#define REG_R7 (5) /* R7 */
#define REG_R8 (6) /* R8 */
#define REG_R9 (7) /* R9 */
#define REG_R10 (8) /* R10 */
#define REG_R11 (9) /* R11 */
#ifdef CONFIG_BUILD_PROTECTED
# define REG_EXC_RETURN (10) /* EXC_RETURN */
# define SW_INT_REGS (11)
#else
# define SW_INT_REGS (10)
#endif
/* If the MCU supports a floating point unit, then it will be necessary
* to save the state of the FPU status register and data registers on
* each context switch. These registers are not saved during interrupt
* level processing, however. So, as a consequence, floating point
* operations may NOT be performed in interrupt handlers.
*
* The FPU provides an extension register file containing 32 single-
* precision registers. These can be viewed as:
*
* - Sixteen 64-bit doubleword registers, D0-D15
* - Thirty-two 32-bit single-word registers, S0-S31
* S<2n> maps to the least significant half of D<n>
* S<2n+1> maps to the most significant half of D<n>.
*/
#ifdef CONFIG_ARCH_FPU
# define REG_D0 (SW_INT_REGS+0) /* D0 */
# define REG_S0 (SW_INT_REGS+0) /* S0 */
# define REG_S1 (SW_INT_REGS+1) /* S1 */
# define REG_D1 (SW_INT_REGS+2) /* D1 */
# define REG_S2 (SW_INT_REGS+2) /* S2 */
# define REG_S3 (SW_INT_REGS+3) /* S3 */
# define REG_D2 (SW_INT_REGS+4) /* D2 */
# define REG_S4 (SW_INT_REGS+4) /* S4 */
# define REG_S5 (SW_INT_REGS+5) /* S5 */
# define REG_D3 (SW_INT_REGS+6) /* D3 */
# define REG_S6 (SW_INT_REGS+6) /* S6 */
# define REG_S7 (SW_INT_REGS+7) /* S7 */
# define REG_D4 (SW_INT_REGS+8) /* D4 */
# define REG_S8 (SW_INT_REGS+8) /* S8 */
# define REG_S9 (SW_INT_REGS+9) /* S9 */
# define REG_D5 (SW_INT_REGS+10) /* D5 */
# define REG_S10 (SW_INT_REGS+10) /* S10 */
# define REG_S11 (SW_INT_REGS+11) /* S11 */
# define REG_D6 (SW_INT_REGS+12) /* D6 */
# define REG_S12 (SW_INT_REGS+12) /* S12 */
# define REG_S13 (SW_INT_REGS+13) /* S13 */
# define REG_D7 (SW_INT_REGS+14) /* D7 */
# define REG_S14 (SW_INT_REGS+14) /* S14 */
# define REG_S15 (SW_INT_REGS+15) /* S15 */
# define REG_D8 (SW_INT_REGS+16) /* D8 */
# define REG_S16 (SW_INT_REGS+16) /* S16 */
# define REG_S17 (SW_INT_REGS+17) /* S17 */
# define REG_D9 (SW_INT_REGS+18) /* D9 */
# define REG_S18 (SW_INT_REGS+18) /* S18 */
# define REG_S19 (SW_INT_REGS+19) /* S19 */
# define REG_D10 (SW_INT_REGS+20) /* D10 */
# define REG_S20 (SW_INT_REGS+20) /* S20 */
# define REG_S21 (SW_INT_REGS+21) /* S21 */
# define REG_D11 (SW_INT_REGS+22) /* D11 */
# define REG_S22 (SW_INT_REGS+22) /* S22 */
# define REG_S23 (SW_INT_REGS+23) /* S23 */
# define REG_D12 (SW_INT_REGS+24) /* D12 */
# define REG_S24 (SW_INT_REGS+24) /* S24 */
# define REG_S25 (SW_INT_REGS+25) /* S25 */
# define REG_D13 (SW_INT_REGS+26) /* D13 */
# define REG_S26 (SW_INT_REGS+26) /* S26 */
# define REG_S27 (SW_INT_REGS+27) /* S27 */
# define REG_D14 (SW_INT_REGS+28) /* D14 */
# define REG_S28 (SW_INT_REGS+28) /* S28 */
# define REG_S29 (SW_INT_REGS+29) /* S29 */
# define REG_D15 (SW_INT_REGS+30) /* D15 */
# define REG_S30 (SW_INT_REGS+30) /* S30 */
# define REG_S31 (SW_INT_REGS+31) /* S31 */
# define REG_FPSCR (SW_INT_REGS+32) /* Floating point status and control */
# define SW_FPU_REGS (33)
#else
# define SW_FPU_REGS (0)
#endif
/* The total number of registers saved by software */
#define SW_XCPT_REGS (SW_INT_REGS + SW_FPU_REGS)
#define SW_XCPT_SIZE (4 * SW_XCPT_REGS)
/* On entry into an IRQ, the hardware automatically saves the following
* registers on the stack in this (address) order:
*/
#define REG_R0 (SW_XCPT_REGS+0) /* R0 */
#define REG_R1 (SW_XCPT_REGS+1) /* R1 */
#define REG_R2 (SW_XCPT_REGS+2) /* R2 */
#define REG_R3 (SW_XCPT_REGS+3) /* R3 */
#define REG_R12 (SW_XCPT_REGS+4) /* R12 */
#define REG_R14 (SW_XCPT_REGS+5) /* R14 = LR */
#define REG_R15 (SW_XCPT_REGS+6) /* R15 = PC */
#define REG_XPSR (SW_XCPT_REGS+7) /* xPSR */
#define HW_XCPT_REGS (8)
#define HW_XCPT_SIZE (4 * HW_XCPT_REGS)
#define XCPTCONTEXT_REGS (HW_XCPT_REGS + SW_XCPT_REGS)
#define XCPTCONTEXT_SIZE (HW_XCPT_SIZE + SW_XCPT_SIZE)
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Inline functions
****************************************************************************/
/****************************************************************************
* Public Variables
****************************************************************************/
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_INCLUDE_ARMV7_M_IRQ_LAZYFPU_H */

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arch/arm/include/armv7-m/syscall.h
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@ -1,267 +0,0 @@
/****************************************************************************
* arch/arm/include/armv7-m/syscall.h
*
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/* This file should never be included directed but, rather, only indirectly
* through include/syscall.h or include/sys/sycall.h
*/
#ifndef __ARCH_ARM_INCLUDE_ARMV7_M_SYSCALL_H
#define __ARCH_ARM_INCLUDE_ARMV7_M_SYSCALL_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#ifndef __ASSEMBLY__
# include <stdint.h>
#endif
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* This is the value used as the argument to the SVC instruction. It is not
* used.
*/
#define SYS_syscall 0x00
/* The SYS_signal_handler_return is executed here... its value is not always
* available in this context and so is assumed to be 7.
*/
#ifndef SYS_signal_handler_return
# define SYS_signal_handler_return (7)
#elif SYS_signal_handler_return != 7
# error "SYS_signal_handler_return was assumed to be 7"
#endif
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Inline functions
****************************************************************************/
#ifndef __ASSEMBLY__
/* SVC call with SYS_ call number and no parameters */
static inline uintptr_t sys_call0(unsigned int nbr)
{
register long reg0 __asm__("r0") = (long)(nbr);
__asm__ __volatile__
(
"svc %1"
: "=r"(reg0)
: "i"(SYS_syscall), "r"(reg0)
: "memory"
);
return reg0;
}
/* SVC call with SYS_ call number and one parameter */
static inline uintptr_t sys_call1(unsigned int nbr, uintptr_t parm1)
{
register long reg0 __asm__("r0") = (long)(nbr);
register long reg1 __asm__("r1") = (long)(parm1);
__asm__ __volatile__
(
"svc %1"
: "=r"(reg0)
: "i"(SYS_syscall), "r"(reg0), "r"(reg1)
: "memory"
);
return reg0;
}
/* SVC call with SYS_ call number and two parameters */
static inline uintptr_t sys_call2(unsigned int nbr, uintptr_t parm1,
uintptr_t parm2)
{
register long reg0 __asm__("r0") = (long)(nbr);
register long reg2 __asm__("r2") = (long)(parm2);
register long reg1 __asm__("r1") = (long)(parm1);
__asm__ __volatile__
(
"svc %1"
: "=r"(reg0)
: "i"(SYS_syscall), "r"(reg0), "r"(reg1), "r"(reg2)
: "memory"
);
return reg0;
}
/* SVC call with SYS_ call number and three parameters */
static inline uintptr_t sys_call3(unsigned int nbr, uintptr_t parm1,
uintptr_t parm2, uintptr_t parm3)
{
register long reg0 __asm__("r0") = (long)(nbr);
register long reg3 __asm__("r3") = (long)(parm3);
register long reg2 __asm__("r2") = (long)(parm2);
register long reg1 __asm__("r1") = (long)(parm1);
__asm__ __volatile__
(
"svc %1"
: "=r"(reg0)
: "i"(SYS_syscall), "r"(reg0), "r"(reg1), "r"(reg2), "r"(reg3)
: "memory"
);
return reg0;
}
/* SVC call with SYS_ call number and four parameters.
*
* NOTE the nonstandard parameter passing: parm4 is in R4
*/
static inline uintptr_t sys_call4(unsigned int nbr, uintptr_t parm1,
uintptr_t parm2, uintptr_t parm3,
uintptr_t parm4)
{
register long reg0 __asm__("r0") = (long)(nbr);
register long reg4 __asm__("r4") = (long)(parm4);
register long reg3 __asm__("r3") = (long)(parm3);
register long reg2 __asm__("r2") = (long)(parm2);
register long reg1 __asm__("r1") = (long)(parm1);
__asm__ __volatile__
(
"svc %1"
: "=r"(reg0)
: "i"(SYS_syscall), "r"(reg0), "r"(reg1), "r"(reg2),
"r"(reg3), "r"(reg4)
: "memory"
);
return reg0;
}
/* SVC call with SYS_ call number and five parameters.
*
* NOTE the nonstandard parameter passing: parm4 and parm5 are in R4 and R5
*/
static inline uintptr_t sys_call5(unsigned int nbr, uintptr_t parm1,
uintptr_t parm2, uintptr_t parm3,
uintptr_t parm4, uintptr_t parm5)
{
register long reg0 __asm__("r0") = (long)(nbr);
register long reg5 __asm__("r5") = (long)(parm5);
register long reg4 __asm__("r4") = (long)(parm4);
register long reg3 __asm__("r3") = (long)(parm3);
register long reg2 __asm__("r2") = (long)(parm2);
register long reg1 __asm__("r1") = (long)(parm1);
__asm__ __volatile__
(
"svc %1"
: "=r"(reg0)
: "i"(SYS_syscall), "r"(reg0), "r"(reg1), "r"(reg2),
"r"(reg3), "r"(reg4), "r"(reg5)
: "memory"
);
return reg0;
}
/* SVC call with SYS_ call number and six parameters.
*
* NOTE the nonstandard parameter passing: parm4-parm6 are in R4-R6
*/
static inline uintptr_t sys_call6(unsigned int nbr, uintptr_t parm1,
uintptr_t parm2, uintptr_t parm3,
uintptr_t parm4, uintptr_t parm5,
uintptr_t parm6)
{
register long reg0 __asm__("r0") = (long)(nbr);
register long reg6 __asm__("r6") = (long)(parm6);
register long reg5 __asm__("r5") = (long)(parm5);
register long reg4 __asm__("r4") = (long)(parm4);
register long reg3 __asm__("r3") = (long)(parm3);
register long reg2 __asm__("r2") = (long)(parm2);
register long reg1 __asm__("r1") = (long)(parm1);
__asm__ __volatile__
(
"svc %1"
: "=r"(reg0)
: "i"(SYS_syscall), "r"(reg0), "r"(reg1), "r"(reg2),
"r"(reg3), "r"(reg4), "r"(reg5), "r"(reg6)
: "memory"
);
return reg0;
}
/****************************************************************************
* Public Variables
****************************************************************************/
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_INCLUDE_ARMV7_M_SYSCALL_H */

106
arch/arm/include/c5471/irq.h
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@ -1,106 +0,0 @@
/****************************************************************************
* arch/arm/include/c5471/irq.h
*
* Copyright (C) 2007, 2008 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/* This file should never be included directed but, rather,
* only indirectly through nuttx/irq.h
*/
#ifndef __ARCH_ARM_INCLUDE_C5471_IRQ_H
#define __ARCH_ARM_INCLUDE_C5471_IRQ_H
/****************************************************************************
* Included Files
****************************************************************************/
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* C5471 Interrupts */
#define C5471_IRQ_TIMER0 0
#define C5471_IRQ_TIMER1 1
#define C5471_IRQ_TIMER2 2
#define C5471_IRQ_GPIO0 3
#define C5471_IRQ_ETHER 4
#define C5471_IRQ_KBGPIO_0_7 5
#define C5471_IRQ_UART 6
#define C5471_IRQ_UART_IRDA 7
#define C5471_IRQ_KBGPIO_8_15 8
#define C5471_IRQ_GPIO3 9
#define C5471_IRQ_GPIO2 10
#define C5471_IRQ_I2C 11
#define C5471_IRQ_GPIO1 12
#define C5471_IRQ_SPI 13
#define C5471_IRQ_GPIO_4_19 14
#define C5471_IRQ_API 15
#define C5471_IRQ_WATCHDOG C5471_IRQ_TIMER0
#define C5471_IRQ_SYSTIMER C5471_IRQ_TIMER2
#define NR_IRQS (C5471_IRQ_API+1)
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Inline functions
****************************************************************************/
/****************************************************************************
* Public Variables
****************************************************************************/
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#ifndef __ASSEMBLY__
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif
#endif /* __ARCH_ARM_INCLUDE_C5471_IRQ_H */

49
arch/arm/include/calypso/armio.h
View file

@ -1,49 +0,0 @@
/****************************************************************************
* Driver for Calypso ARMIO
*
* Copyright (C) 2011 Stefan Richter. All rights reserved.
* Author: Stefan Richter <ichgeh@l--putt.de>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
/****************************************************************************
* Prototypes for interrupt handling
****************************************************************************/
inline int calypso_kbd_irq(int irq, uint32_t *regs);
/****************************************************************************
* Initialize device, add /dev/... nodes
****************************************************************************/
void calypso_armio(void);

67
arch/arm/include/calypso/clock.h
View file

@ -1,67 +0,0 @@
#ifndef _CALYPSO_CLK_H
#define _CALYPSO_CLK_H
#include <stdint.h>
#define CALYPSO_PLL26_52_MHZ ((2 << 8) | 0)
#define CALYPSO_PLL26_86_7_MHZ ((10 << 8) | 2)
#define CALYPSO_PLL26_87_MHZ ((3 << 8) | 0)
#define CALYPSO_PLL13_104_MHZ ((8 << 8) | 0)
enum mclk_div {
_ARM_MCLK_DIV_1 = 0,
ARM_MCLK_DIV_1 = 1,
ARM_MCLK_DIV_2 = 2,
ARM_MCLK_DIV_3 = 3,
ARM_MCLK_DIV_4 = 4,
ARM_MCLK_DIV_5 = 5,
ARM_MCLK_DIV_6 = 6,
ARM_MCLK_DIV_7 = 7,
ARM_MCLK_DIV_1_5 = 0x80 | 1,
ARM_MCLK_DIV_2_5 = 0x80 | 2,
};
void calypso_clock_set(uint8_t vtcxo_div2, uint16_t inp, enum mclk_div mclk_div);
void calypso_pll_set(uint16_t inp);
void calypso_clk_dump(void);
/* CNTL_RST */
enum calypso_rst {
RESET_DSP = (1 << 1),
RESET_EXT = (1 << 2),
RESET_WDOG = (1 << 3),
};
void calypso_reset_set(enum calypso_rst calypso_rst, int active);
int calypso_reset_get(enum calypso_rst);
enum calypso_bank {
CALYPSO_nCS0 = 0,
CALYPSO_nCS1 = 2,
CALYPSO_nCS2 = 4,
CALYPSO_nCS3 = 6,
CALYPSO_nCS7 = 8,
CALYPSO_CS4 = 0xa,
CALYPSO_nCS6 = 0xc,
};
enum calypso_mem_width {
CALYPSO_MEM_8bit = 0,
CALYPSO_MEM_16bit = 1,
CALYPSO_MEM_32bit = 2,
};
void calypso_mem_cfg(enum calypso_bank bank, uint8_t ws,
enum calypso_mem_width width, int we);
/* Enable or disable the internal bootrom mapped to 0x0000'0000 */
void calypso_bootrom(int enable);
/* Enable or disable the debug unit */
void calypso_debugunit(int enable);
/* configure the RHEA bus bridge[s] */
void calypso_rhea_cfg(uint8_t fac0, uint8_t fac1, uint8_t timeout,
uint8_t ws_h, uint8_t ws_l, uint8_t w_en0, uint8_t w_en1);
#endif /* _CALYPSO_CLK_H */

31
arch/arm/include/calypso/debug.h
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@ -1,31 +0,0 @@
#ifndef _DEBUG_H
#define _DEBUG_H
#ifndef ARRAY_SIZE
#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
#endif
/*
* Check at compile time that something is of a particular type.
* Always evaluates to 1 so you may use it easily in comparisons.
*/
#define typecheck(type,x) \
({ type __dummy; \
typeof(x) __dummy2; \
(void)(&__dummy == &__dummy2); \
1; \
})
#ifdef DEBUG
#define dputchar(x) putchar(x)
#define dputs(x) puts(x)
#define dphex(x,y) phex(x,y)
#define printd(x, ...) printf(x, ##__VA_ARGS__)
#else
#define dputchar(x)
#define dputs(x)
#define dphex(x,y)
#define printd(x, args ...)
#endif
#endif /* _DEBUG_H */

18
arch/arm/include/calypso/defines.h
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@ -1,18 +0,0 @@
#ifndef _DEFINES_H
#define _DEFINES_H
#define __attribute_const__ __attribute__((__const__))
/* type properties */
#define __packed __attribute__((packed))
#define __aligned(alignment) __attribute__((aligned(alignment)))
#define __unused __attribute__((unused))
/* linkage */
#define __section(name) __attribute__((section(name)))
/* force placement in zero-waitstate memory */
#define __ramtext __section(".ramtext")
#endif /* !_DEFINES_H */

81
arch/arm/include/calypso/irq.h
View file

@ -1,81 +0,0 @@
/****************************************************************************
* arch/arm/include/calypso/irq.h
* Driver for Calypso IRQ controller
*
* (C) 2010 by Harald Welte <laforge@gnumonks.org>
* (C) 2011 by Stefan Richter <ichgeh@l--putt.de>
*
* This source code is derivated from Osmocom-BB project and was
* relicensed as BSD with permission from original authors.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
**************************************************************************/
#ifndef __INCLUDE_NUTTX_IRQ_H
#error "This file should never be included directly! Use <nuttx/irq.h>"
#endif
#ifndef _CALYPSO_IRQ_H
#define _CALYPSO_IRQ_H
#ifndef __ASSEMBLY__
enum irq_nr {
IRQ_WATCHDOG = 0,
IRQ_TIMER1 = 1,
IRQ_TIMER2 = 2,
IRQ_TSP_RX = 3,
IRQ_TPU_FRAME = 4,
IRQ_TPU_PAGE = 5,
IRQ_SIMCARD = 6,
IRQ_UART_MODEM = 7,
IRQ_KEYPAD_GPIO = 8,
IRQ_RTC_TIMER = 9,
IRQ_RTC_ALARM_I2C = 10,
IRQ_ULPD_GAUGING = 11,
IRQ_EXTERNAL = 12,
IRQ_SPI = 13,
IRQ_DMA = 14,
IRQ_API = 15,
IRQ_SIM_DETECT = 16,
IRQ_EXTERNAL_FIQ = 17,
IRQ_UART_IRDA = 18,
IRQ_ULPD_GSM_TIMER = 19,
IRQ_GEA = 20,
_NR_IRQS
};
#endif /* __ASSEMBLY__ */
/* Don't use _NR_IRQS!!! Won't work in preprocessor... */
#define NR_IRQS 21
#define IRQ_SYSTIMER IRQ_TIMER2
#endif /* _CALYPSO_IRQ_H */

28
arch/arm/include/calypso/memory.h
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@ -1,28 +0,0 @@
#ifndef _MEMORY_H
#define _MEMORY_H
#define __arch_getb(a) (*(volatile unsigned char *)(a))
#define __arch_getw(a) (*(volatile unsigned short *)(a))
#define __arch_getl(a) (*(volatile unsigned int *)(a))
#define __arch_putb(v,a) (*(volatile unsigned char *)(a) = (v))
#define __arch_putw(v,a) (*(volatile unsigned short *)(a) = (v))
#define __arch_putl(v,a) (*(volatile unsigned int *)(a) = (v))
#define __raw_writeb(v,a) __arch_putb(v,a)
#define __raw_writew(v,a) __arch_putw(v,a)
#define __raw_writel(v,a) __arch_putl(v,a)
#define __raw_readb(a) __arch_getb(a)
#define __raw_readw(a) __arch_getw(a)
#define __raw_readl(a) __arch_getl(a)
#define writeb(v,a) __arch_putb(v,a)
#define writew(v,a) __arch_putw(v,a)
#define writel(v,a) __arch_putl(v,a)
#define readb(a) __arch_getb(a)
#define readw(a) __arch_getw(a)
#define readl(a) __arch_getl(a)
#endif /* _MEMORY_H */

25
arch/arm/include/calypso/timer.h
View file

@ -1,25 +0,0 @@
#ifndef _CAL_TIMER_H
#define _CAL_TIMER_H
/* Enable or Disable a timer */
void hwtimer_enable(int num, int on);
/* Configure pre-scaler and if timer is auto-reload */
void hwtimer_config(int num, uint8_t pre_scale, int auto_reload);
/* Load a timer with the given value */
void hwtimer_load(int num, uint16_t val);
/* Read the current timer value */
uint16_t hwtimer_read(int num);
/* Enable or disable the watchdog */
void wdog_enable(int on);
/* Reset cpu using watchdog */
void wdog_reset(void);
/* power up the timers */
void hwtimer_init(void);
#endif /* _CAL_TIMER_H */

6
arch/arm/include/calypso/uwire.h
View file

@ -1,6 +0,0 @@
#ifndef _CALYPSO_UWIRE_H
#define _CALYPSO_UWIRE_H
void uwire_init(void);
int uwire_xfer(int cs, int bitlen, const void *dout, void *din);
#endif

135
arch/arm/include/dm320/irq.h
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@ -1,135 +0,0 @@
/****************************************************************************
* arch/arm/include/dm320/irq.h
*
* Copyright (C) 2007, 2008 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/* This file should never be included directed but, rather,
* only indirectly through nuttx/irq.h
*/
#ifndef __ARCH_ARM_INCLUDE_DM320_IRQ_H
#define __ARCH_ARM_INCLUDE_DM320_IRQ_H
/****************************************************************************
* Included Files
****************************************************************************/
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* DM320 Interrupts */
#define DM320_IRQ_TMR0 0 /* IRQ0: Timer 0 Interrupt */
#define DM320_IRQ_TMR1 1 /* IRQ1: Timer 1 Interrupt */
#define DM320_IRQ_TMR2 2 /* IRQ2: Timer 2 Interrupt (CCD timer 0) */
#define DM320_IRQ_TMR3 3 /* IRQ3: Timer 3 Interrupt (CCD timer 1) */
#define DM320_IRQ_CCDVD0 4 /* IRQ4: CCD VD Interrupt #0 */
#define DM320_IRQ_CCDVD1 5 /* IRQ5: CCD VD Interrupt #1 */
#define DM320_IRQ_CCDWEN 6 /* IRQ6: CCD WEN Interrupt */
#define DM320_IRQ_VENC 7 /* IRQ7: Video Encoder Interrupt */
#define DM320_IRQ_SP0 8 /* IRQ8: Serial Port 0 Interrupt (with DMA) */
#define DM320_IRQ_SP1 9 /* IRQ9: Serial Port 1 Interrupt */
#define DM320_IRQ_EXTHOST 10 /* IRQ10: External host interrupt */
#define DM320_IRQ_IMGBUF 11 /* IRQ11: Image Buffer */
#define DM320_IRQ_UART0 12 /* IRQ12: UART0 Interrupt */
#define DM320_IRQ_UART1 13 /* IRQ13: UART1 Interrupt */
#define DM320_IRQ_USB0 14 /* IRQ14: USB 0 Interrupt (DMA) */
#define DM320_IRQ_USB1 15 /* IRQ15: USB 1 Interrupt (Core) */
#define DM320_IRQ_VLYNQ 16 /* IRQ16: VLYNQ Interrupt */
#define DM320_IRQ_MTC0 17 /* IRQ17: Memory Traffic Controller 0 (DMA) */
#define DM320_IRQ_MTC1 18 /* IRQ18: Memory Traffic Controller 1 (CFC_RDY) */
#define DM320_IRQ_MMCSD0 19 /* IRQ19: MMC/SD or MS 0 Interrupt */
#define DM320_IRQ_MMCSD1 20 /* IRQ20: MMC/SD or MS 1 Interrupt */
#define DM320_IRQ_EXT0 21 /* IRQ21: External Interrupt #0 (GIO0) */
#define DM320_IRQ_EXT1 22 /* IRQ22: External Interrupt #1 (GIO1) */
#define DM320_IRQ_EXT2 23 /* IRQ23: External Interrupt #2 (GIO2) */
#define DM320_IRQ_EXT3 24 /* IRQ24: External Interrupt #3 (GIO3) */
#define DM320_IRQ_EXT4 25 /* IRQ25: External Interrupt #4 (GIO4) */
#define DM320_IRQ_EXT5 26 /* IRQ26: External Interrupt #5 (GIO5) */
#define DM320_IRQ_EXT6 27 /* IRQ27: External Interrupt #6 (GIO6) */
#define DM320_IRQ_EXT7 28 /* IRQ28: External Interrupt #7 (GIO7) */
#define DM320_IRQ_EXT8 29 /* IRQ29: External Interrupt #8 (GIO8) */
#define DM320_IRQ_EXT9 30 /* IRQ30: External Interrupt #9 (GIO9) */
#define DM320_IRQ_EXT10 31 /* IRQ31: External Interrupt #10 (GIO10) */
#define DM320_IRQ_EXT11 32 /* IRQ32: External Interrupt #11 (GIO11) */
#define DM320_IRQ_EXT12 33 /* IRQ33: External Interrupt #12 (GIO12) */
#define DM320_IRQ_EXT13 34 /* IRQ34: External Interrupt #13 (GIO13) */
#define DM320_IRQ_EXT14 35 /* IRQ35: External Interrupt #14 (GIO14) */
#define DM320_IRQ_EXT15 36 /* IRQ36: External Interrupt #15 (GIO15) */
#define DM320_IRQ_PREV0 37 /* IRQ37: Preview Engine 0 (Preview Over) */
#define DM320_IRQ_PREV1 38 /* IRQ38: Preview Engine 1 (Preview Historgram Over) */
#define DM320_IRQ_WDT 39 /* IRQ39: Watchdog Timer Interrupt */
#define DM320_IRQ_I2C 40 /* IRQ40: I2C Interrupt */
#define DM320_IRQ_CLKC 41 /* IRQ41: Clock controller Interrupt (wake up) */
#define DM320_IRQ_E2ICE 42 /* IRQ42: Embedded ICE Interrupt */
#define DM320_IRQ_ARMCOMRX 43 /* IRQ43: ARMCOMM Receive Interrupt */
#define DM320_IRQ_ARMCOMTX 44 /* IRQ44: ARMCOMM Transmit Interrupt */
#define DM320_IRQ_RSV 45 /* IRQ45: Reserved Interrupt */
#define DM320_IRQ_SYSTIMER DM320_IRQ_TMR0
#define NR_IRQS (DM320_IRQ_RSV+1)
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Inline functions
****************************************************************************/
/****************************************************************************
* Public Variables
****************************************************************************/
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#ifndef __ASSEMBLY__
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif
#endif /* __ARCH_ARM_INCLUDE_DM320_IRQ_H */

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/************************************************************************************
* arch/arm/include/efm32/chip.h
*
* Copyright (C) 2014 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_INCLUDE_EFM32_CHIP_H
#define __ARCH_ARM_INCLUDE_EFM32_CHIP_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* EFM32 EnergyMicro ****************************************************************/
/* Tiny Gecko with 32KiB FLASH and 4KiB RAM in a QFN64 package */
#if defined(CONFIG_ARCH_CHIP_EFM32TG840F32)
/* Gecko with 128KiB FLASH and 16KiB SRAM in LQFP100 (EFM32G880F128) or BGA112
* (EFM32G890F128) package
*/
#elif defined(CONFIG_ARCH_CHIP_EFM32G880F128) || \
defined(CONFIG_ARCH_CHIP_EFM32G890F128)
/* Giant Gecko with 1024KiB FLASH and 128KiB RAM in a QFP64 package
* (EFM32GG332F1024) or BGA112 (EFM32GG990F1024) package
*/
#elif defined(CONFIG_ARCH_CHIP_EFM32GG332F1024) || \
defined(CONFIG_ARCH_CHIP_EFM32GG990F1024)
#else
# error "Unsupported EFM32 chip"
#endif
/* NVIC priority levels *************************************************************/
#define NVIC_SYSH_PRIORITY_MIN 0xe0 /* Bits [7:5] set in minimum priority */
#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */
#define NVIC_SYSH_PRIORITY_STEP 0x20 /* Three bits of interrupt priority used */
/* If CONFIG_ARMV7M_USEBASEPRI is selected, then interrupts will be disabled
* by setting the BASEPRI register to NVIC_SYSH_DISABLE_PRIORITY so that most
* interrupts will not have execution priority. SVCall must have execution
* priority in all cases.
*
* In the normal cases, interrupts are not nest-able and all interrupts run
* at an execution priority between NVIC_SYSH_PRIORITY_MIN and
* NVIC_SYSH_PRIORITY_MAX (with NVIC_SYSH_PRIORITY_MAX reserved for SVCall).
*
* If, in addition, CONFIG_ARCH_HIPRI_INTERRUPT is defined, then special
* high priority interrupts are supported. These are not "nested" in the
* normal sense of the word. These high priority interrupts can interrupt
* normal processing but execute outside of OS (although they can "get back
* into the game" via a PendSV interrupt).
*
* In the normal course of things, interrupts must occasionally be disabled
* using the irqsave() inline function to prevent contention in use of
* resources that may be shared between interrupt level and non-interrupt
* level logic. Now the question arises, if CONFIG_ARCH_HIPRI_INTERRUPT,
* do we disable all interrupts (except SVCall), or do we only disable the
* "normal" interrupts. Since the high priority interrupts cannot interact
* with the OS, you may want to permit the high priority interrupts even if
* interrupts are disabled. The setting CONFIG_ARCH_INT_DISABLEALL can be
* used to select either behavior:
*
* ----------------------------+--------------+----------------------------
* CONFIG_ARCH_HIPRI_INTERRUPT | NO | YES
* ----------------------------+--------------+--------------+-------------
* CONFIG_ARCH_INT_DISABLEALL | N/A | YES | NO
* ----------------------------+--------------+--------------+-------------
* | | | SVCall
* | SVCall | SVCall | HIGH
* Disable here and below --------> MAXNORMAL ---> HIGH --------> MAXNORMAL
* | | MAXNORMAL |
* ----------------------------+--------------+--------------+-------------
*/
#if defined(CONFIG_ARCH_HIPRI_INTERRUPT) && defined(CONFIG_ARCH_INT_DISABLEALL)
# define NVIC_SYSH_MAXNORMAL_PRIORITY (NVIC_SYSH_PRIORITY_MAX + 2*NVIC_SYSH_PRIORITY_STEP)
# define NVIC_SYSH_HIGH_PRIORITY (NVIC_SYSH_PRIORITY_MAX + NVIC_SYSH_PRIORITY_STEP)
# define NVIC_SYSH_DISABLE_PRIORITY NVIC_SYSH_HIGH_PRIORITY
# define NVIC_SYSH_SVCALL_PRIORITY NVIC_SYSH_PRIORITY_MAX
#else
# define NVIC_SYSH_MAXNORMAL_PRIORITY (NVIC_SYSH_PRIORITY_MAX + NVIC_SYSH_PRIORITY_STEP)
# define NVIC_SYSH_HIGH_PRIORITY NVIC_SYSH_PRIORITY_MAX
# define NVIC_SYSH_DISABLE_PRIORITY NVIC_SYSH_MAXNORMAL_PRIORITY
# define NVIC_SYSH_SVCALL_PRIORITY NVIC_SYSH_PRIORITY_MAX
#endif
#endif /* __ARCH_ARM_INCLUDE_EFM32_CHIP_H */

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arch/arm/include/efm32/efm32g_irq.h
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@ -1,121 +0,0 @@
/*****************************************************************************
* arch/arm/include/efm32s/efm32g_irq.h
*
* Copyright (C) 2014 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*****************************************************************************/
/* This file should never be included directed but, rather, only indirectly
* through nuttx/irq.h
*/
#ifndef __ARCH_ARM_INCLUDE_EFM32G_IRQ_H
#define __ARCH_ARM_INCLUDE_EFM32G_IRQ_H
/*****************************************************************************
* Included Files
*****************************************************************************/
/*****************************************************************************
* Pre-processor Definitions
*****************************************************************************/
/* IRQ numbers. The IRQ number corresponds vector number and hence map
* directly to bits in the NVIC. This does, however, waste several words of
* memory in the IRQ to handle mapping tables.
*
* Processor Exceptions (vectors 0-15). These common definitions can be
* found in nuttx/arch/arm/include/efm32/irq.h
*
* External interrupts (vectors >= 16)
*/
/* IRQ# Source */
#define EFM32_IRQ_DMA (EFM32_IRQ_INTERRUPTS+ 0) /* 0 DMA */
#define EFM32_IRQ_GPIO_EVEN (EFM32_IRQ_INTERRUPTS+ 1) /* 1 GPIO_EVEN */
#define EFM32_IRQ_TIMER0 (EFM32_IRQ_INTERRUPTS+ 2) /* 2 TIMER0 */
#define EFM32_IRQ_USART0_RX (EFM32_IRQ_INTERRUPTS+ 3) /* 3 USART0_RX */
#define EFM32_IRQ_USART0_TX (EFM32_IRQ_INTERRUPTS+ 4) /* 4 USART0_TX */
#define EFM32_IRQ_ACMP (EFM32_IRQ_INTERRUPTS+ 5) /* 5 ACMP0/ACMP1 */
#define EFM32_IRQ_ADC0 (EFM32_IRQ_INTERRUPTS+ 6) /* 6 ADC0 */
#define EFM32_IRQ_DAC0 (EFM32_IRQ_INTERRUPTS+ 7) /* 7 DAC0 */
#define EFM32_IRQ_I2C0 (EFM32_IRQ_INTERRUPTS+ 8) /* 8 I2C0 */
#define EFM32_IRQ_GPIO_ODD (EFM32_IRQ_INTERRUPTS+ 9) /* 9 GPIO_ODD */
#define EFM32_IRQ_TIMER1 (EFM32_IRQ_INTERRUPTS+10) /* 10 TIMER1 */
#define EFM32_IRQ_TIMER2 (EFM32_IRQ_INTERRUPTS+11) /* 11 TIMER2 */
#define EFM32_IRQ_USART1_RX (EFM32_IRQ_INTERRUPTS+12) /* 12 USART1_RX */
#define EFM32_IRQ_USART1_TX (EFM32_IRQ_INTERRUPTS+13) /* 13 USART1_TX */
#define EFM32_IRQ_USART2_RX (EFM32_IRQ_INTERRUPTS+14) /* 14 USART2_RX */
#define EFM32_IRQ_USART2_TX (EFM32_IRQ_INTERRUPTS+15) /* 15 USART2_TX */
#define EFM32_IRQ_UART0_RX (EFM32_IRQ_INTERRUPTS+16) /* 16 UART0_RX */
#define EFM32_IRQ_UART0_TX (EFM32_IRQ_INTERRUPTS+17) /* 17 UART0_TX */
#define EFM32_IRQ_LEUART0 (EFM32_IRQ_INTERRUPTS+18) /* 18 LEUART0 */
#define EFM32_IRQ_LEUART1 (EFM32_IRQ_INTERRUPTS+19) /* 19 LEUART1 */
#define EFM32_IRQ_LETIMER0 (EFM32_IRQ_INTERRUPTS+20) /* 20 LETIMER0 */
#define EFM32_IRQ_PCNT0 (EFM32_IRQ_INTERRUPTS+21) /* 21 PCNT0 */
#define EFM32_IRQ_PCNT1 (EFM32_IRQ_INTERRUPTS+22) /* 22 PCNT1 */
#define EFM32_IRQ_PCNT2 (EFM32_IRQ_INTERRUPTS+23) /* 23 PCNT2 */
#define EFM32_IRQ_RTC (EFM32_IRQ_INTERRUPTS+24) /* 24 RTC */
#define EFM32_IRQ_CMU (EFM32_IRQ_INTERRUPTS+25) /* 25 CMU */
#define EFM32_IRQ_VCMP (EFM32_IRQ_INTERRUPTS+26) /* 26 VCMP */
#define EFM32_IRQ_LCD (EFM32_IRQ_INTERRUPTS+27) /* 27 LCD */
#define EFM32_IRQ_MSC (EFM32_IRQ_INTERRUPTS+28) /* 28 MSC */
#define EFM32_IRQ_AES (EFM32_IRQ_INTERRUPTS+29) /* 29 AES */
#define NR_VECTORS (EFM32_IRQ_INTERRUPTS+30)
/*****************************************************************************
* Public Types
*****************************************************************************/
/*****************************************************************************
* Public Data
*****************************************************************************/
#ifndef __ASSEMBLY__
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/*****************************************************************************
* Public Functions
*****************************************************************************/
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif
#endif /* __ARCH_ARM_INCLUDE_EFM32G_IRQ_H */

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arch/arm/include/efm32/efm32gg_irq.h
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@ -1,130 +0,0 @@
/*****************************************************************************
* arch/arm/include/efm32s/efm32gg_irq.h
*
* Copyright (C) 2014 Pierre-noel Bouteville . All rights reserved.
* Author: Pierre-noel Bouteville <pnb990@gmail.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*****************************************************************************/
/* This file should never be included directed but, rather, only indirectly
* through nuttx/irq.h
*/
#ifndef __ARCH_ARM_INCLUDE_EFM32GG_IRQ_H
#define __ARCH_ARM_INCLUDE_EFM32GG_IRQ_H
/*****************************************************************************
* Included Files
*****************************************************************************/
/*****************************************************************************
* Pre-processor Definitions
*****************************************************************************/
/* IRQ numbers. The IRQ number corresponds vector number and hence map
* directly to bits in the NVIC. This does, however, waste several words of
* memory in the IRQ to handle mapping tables.
*
* Processor Exceptions (vectors 0-15). These common definitions can be
* found in nuttx/arch/arm/include/efm32/irq.h
*
* External interrupts (vectors >= 16)
*/
#define EFM32_IRQ_DMA (EFM32_IRQ_INTERRUPTS+ 0)
#define EFM32_IRQ_GPIO_EVEN (EFM32_IRQ_INTERRUPTS+ 1)
#define EFM32_IRQ_TIMER0 (EFM32_IRQ_INTERRUPTS+ 2)
#define EFM32_IRQ_USART0_RX (EFM32_IRQ_INTERRUPTS+ 3)
#define EFM32_IRQ_USART0_TX (EFM32_IRQ_INTERRUPTS+ 4)
#define EFM32_IRQ_USB (EFM32_IRQ_INTERRUPTS+ 5)
#define EFM32_IRQ_ACMP (EFM32_IRQ_INTERRUPTS+ 6)
#define EFM32_IRQ_ADC0 (EFM32_IRQ_INTERRUPTS+ 7)
#define EFM32_IRQ_DAC0 (EFM32_IRQ_INTERRUPTS+ 8)
#define EFM32_IRQ_I2C0 (EFM32_IRQ_INTERRUPTS+ 9)
#define EFM32_IRQ_I2C1 (EFM32_IRQ_INTERRUPTS+10)
#define EFM32_IRQ_GPIO_ODD (EFM32_IRQ_INTERRUPTS+11)
#define EFM32_IRQ_TIMER1 (EFM32_IRQ_INTERRUPTS+12)
#define EFM32_IRQ_TIMER2 (EFM32_IRQ_INTERRUPTS+13)
#define EFM32_IRQ_TIMER3 (EFM32_IRQ_INTERRUPTS+14)
#define EFM32_IRQ_USART1_RX (EFM32_IRQ_INTERRUPTS+15)
#define EFM32_IRQ_USART1_TX (EFM32_IRQ_INTERRUPTS+16)
#define EFM32_IRQ_LESENSE (EFM32_IRQ_INTERRUPTS+17)
#define EFM32_IRQ_USART2_RX (EFM32_IRQ_INTERRUPTS+18)
#define EFM32_IRQ_USART2_TX (EFM32_IRQ_INTERRUPTS+19)
#define EFM32_IRQ_UART0_RX (EFM32_IRQ_INTERRUPTS+20)
#define EFM32_IRQ_UART0_TX (EFM32_IRQ_INTERRUPTS+21)
#define EFM32_IRQ_UART1_RX (EFM32_IRQ_INTERRUPTS+22)
#define EFM32_IRQ_UART1_TX (EFM32_IRQ_INTERRUPTS+23)
#define EFM32_IRQ_LEUART0 (EFM32_IRQ_INTERRUPTS+24)
#define EFM32_IRQ_LEUART1 (EFM32_IRQ_INTERRUPTS+25)
#define EFM32_IRQ_LETIMER0 (EFM32_IRQ_INTERRUPTS+26)
#define EFM32_IRQ_PCNT0 (EFM32_IRQ_INTERRUPTS+27)
#define EFM32_IRQ_PCNT1 (EFM32_IRQ_INTERRUPTS+28)
#define EFM32_IRQ_PCNT2 (EFM32_IRQ_INTERRUPTS+29)
#define EFM32_IRQ_RTC (EFM32_IRQ_INTERRUPTS+30)
#define EFM32_IRQ_BURTC (EFM32_IRQ_INTERRUPTS+31)
#define EFM32_IRQ_CMU (EFM32_IRQ_INTERRUPTS+32)
#define EFM32_IRQ_VCMP (EFM32_IRQ_INTERRUPTS+33)
#define EFM32_IRQ_LCD (EFM32_IRQ_INTERRUPTS+34)
#define EFM32_IRQ_MSC (EFM32_IRQ_INTERRUPTS+35)
#define EFM32_IRQ_AES (EFM32_IRQ_INTERRUPTS+36)
#define EFM32_IRQ_EBI (EFM32_IRQ_INTERRUPTS+37)
#define EFM32_IRQ_EMI (EFM32_IRQ_INTERRUPTS+38)
#define NR_VECTORS (EFM32_IRQ_INTERRUPTS+39)
/*****************************************************************************
* Public Types
*****************************************************************************/
/*****************************************************************************
* Public Data
*****************************************************************************/
#ifndef __ASSEMBLY__
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/*****************************************************************************
* Public Functions
*****************************************************************************/
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif
#endif /* __ARCH_ARM_INCLUDE_EFM32GG_IRQ_H */

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arch/arm/include/efm32/efm32tg_irq.h
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@ -1,114 +0,0 @@
/*****************************************************************************
* arch/arm/include/efm32s/efm32tg_irq.h
*
* Copyright (C) 2014 Pierre-noel Bouteville . All rights reserved.
* Author: Pierre-noel Bouteville <pnb990@gmail.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*****************************************************************************/
/* This file should never be included directed but, rather, only indirectly
* through nuttx/irq.h
*/
#ifndef __ARCH_ARM_INCLUDE_EFM32TG_IRQ_H
#define __ARCH_ARM_INCLUDE_EFM32TG_IRQ_H
/*****************************************************************************
* Included Files
*****************************************************************************/
/*****************************************************************************
* Pre-processor Definitions
*****************************************************************************/
/* IRQ numbers. The IRQ number corresponds vector number and hence map
* directly to bits in the NVIC. This does, however, waste several words of
* memory in the IRQ to handle mapping tables.
*
* Processor Exceptions (vectors 0-15). These common definitions can be
* found in nuttx/arch/arm/include/efm32/irq.h
*
* External interrupts (vectors >= 16)
*/
#define EFM32_IRQ_DMA (EFM32_IRQ_INTERRUPTS+ 0)
#define EFM32_IRQ_GPIO_EVEN (EFM32_IRQ_INTERRUPTS+ 1)
#define EFM32_IRQ_TIMER0 (EFM32_IRQ_INTERRUPTS+ 2)
#define EFM32_IRQ_USART0_RX (EFM32_IRQ_INTERRUPTS+ 3)
#define EFM32_IRQ_USART0_TX (EFM32_IRQ_INTERRUPTS+ 4)
#define EFM32_IRQ_ACMP (EFM32_IRQ_INTERRUPTS+ 5)
#define EFM32_IRQ_ADC0 (EFM32_IRQ_INTERRUPTS+ 6)
#define EFM32_IRQ_DAC0 (EFM32_IRQ_INTERRUPTS+ 7)
#define EFM32_IRQ_I2C0 (EFM32_IRQ_INTERRUPTS+ 8)
#define EFM32_IRQ_GPIO_ODD (EFM32_IRQ_INTERRUPTS+ 9)
#define EFM32_IRQ_TIMER1 (EFM32_IRQ_INTERRUPTS+10)
#define EFM32_IRQ_USART1_RX (EFM32_IRQ_INTERRUPTS+11)
#define EFM32_IRQ_USART1_TX (EFM32_IRQ_INTERRUPTS+12)
#define EFM32_IRQ_LESENSE (EFM32_IRQ_INTERRUPTS+13)
#define EFM32_IRQ_LEUART0 (EFM32_IRQ_INTERRUPTS+14)
#define EFM32_IRQ_LETIMER0 (EFM32_IRQ_INTERRUPTS+15)
#define EFM32_IRQ_PCNT0 (EFM32_IRQ_INTERRUPTS+16)
#define EFM32_IRQ_RTC (EFM32_IRQ_INTERRUPTS+17)
#define EFM32_IRQ_CMU (EFM32_IRQ_INTERRUPTS+18)
#define EFM32_IRQ_VCMP (EFM32_IRQ_INTERRUPTS+19)
#define EFM32_IRQ_LCD (EFM32_IRQ_INTERRUPTS+20)
#define EFM32_IRQ_MSC (EFM32_IRQ_INTERRUPTS+21)
#define EFM32_IRQ_AES (EFM32_IRQ_INTERRUPTS+22)
#define NR_VECTORS (EFM32_IRQ_INTERRUPTS+23)
/*****************************************************************************
* Public Types
*****************************************************************************/
/*****************************************************************************
* Public Data
*****************************************************************************/
#ifndef __ASSEMBLY__
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/*****************************************************************************
* Public Functions
*****************************************************************************/
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif
#endif /* __ARCH_ARM_INCLUDE_EFM32TG_IRQ_H */

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arch/arm/include/efm32/irq.h
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@ -1,147 +0,0 @@
/************************************************************************************
* arch/arm/include/efm32s/irq.h
*
* Copyright (C) 2014 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
/* This file should never be included directed but, rather, only indirectly through
* nuttx/irq.h
*/
#ifndef __ARCH_ARM_INCLUDE_EFM32_IRQ_H
#define __ARCH_ARM_INCLUDE_EFM32_IRQ_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include <nuttx/irq.h>
#include <arch/efm32/chip.h>
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* IRQ numbers. The IRQ number corresponds vector number and hence map directly to
* bits in the NVIC. This does, however, waste several words of memory in the IRQ
* to handle mapping tables.
*/
/* Processor Exceptions (vectors 0-15) */
#define EFM32_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG) */
/* Vector 0: Reset stack pointer value */
/* Vector 1: Reset (not handler as an IRQ) */
#define EFM32_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */
#define EFM32_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */
#define EFM32_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */
#define EFM32_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */
#define EFM32_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */
#define EFM32_IRQ_SVCALL (11) /* Vector 11: SVC call */
#define EFM32_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */
/* Vector 13: Reserved */
#define EFM32_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */
#define EFM32_IRQ_SYSTICK (15) /* Vector 15: System tick */
/* External interrupts (vectors >= 16). These definitions are chip-specific */
#define EFM32_IRQ_INTERRUPTS (16) /* Vector number of the first external interrupt */
#if defined(CONFIG_EFM32_EFM32TG)
# include <arch/efm32/efm32tg_irq.h>
#elif defined(CONFIG_EFM32_EFM32G)
# include <arch/efm32/efm32g_irq.h>
#elif defined(CONFIG_EFM32_EFM32GG)
# include <arch/efm32/efm32gg_irq.h>
#else
# error "Unsupported EFM32 chip"
#endif
#ifdef CONFIG_EFM32_GPIO_IRQ
/* If GPIO interrupt support is enabled then up to 16 additional GPIO interrupt
* sources are available. There are actually only two physical interrupt lines:
* GPIO_EVEN and GPIO_ODD. However, from the software point of view, there are
* 16-additional interrupts generated from a second level of decoding.
*/
# define EFM32_IRQ_EXTI0 (NR_VECTORS+0) /* Port[n], pin0 external interrupt */
# define EFM32_IRQ_EXTI1 (NR_VECTORS+1) /* Port[n], pin1 external interrupt */
# define EFM32_IRQ_EXTI2 (NR_VECTORS+2) /* Port[n], pin2 external interrupt */
# define EFM32_IRQ_EXTI3 (NR_VECTORS+3) /* Port[n], pin3 external interrupt */
# define EFM32_IRQ_EXTI4 (NR_VECTORS+4) /* Port[n], pin4 external interrupt */
# define EFM32_IRQ_EXTI5 (NR_VECTORS+5) /* Port[n], pin5 external interrupt */
# define EFM32_IRQ_EXTI6 (NR_VECTORS+6) /* Port[n], pin6 external interrupt */
# define EFM32_IRQ_EXTI7 (NR_VECTORS+7) /* Port[n], pin7 external interrupt */
# define EFM32_IRQ_EXTI8 (NR_VECTORS+8) /* Port[n], pin8 external interrupt */
# define EFM32_IRQ_EXTI9 (NR_VECTORS+9) /* Port[n], pin9 external interrupt */
# define EFM32_IRQ_EXTI10 (NR_VECTORS+10) /* Port[n], pin10 external interrupt */
# define EFM32_IRQ_EXTI11 (NR_VECTORS+11) /* Port[n], pin11 external interrupt */
# define EFM32_IRQ_EXTI12 (NR_VECTORS+12) /* Port[n], pin12 external interrupt */
# define EFM32_IRQ_EXTI13 (NR_VECTORS+13) /* Port[n], pin13 external interrupt */
# define EFM32_IRQ_EXTI14 (NR_VECTORS+14) /* Port[n], pin14 external interrupt */
# define EFM32_IRQ_EXTI15 (NR_VECTORS+15) /* Port[n], pin15 external interrupt */
# define NR_IRQS (NR_VECTORS+16) /* Total number of interrupts */
#else
# define NR_IRQS NR_VECTORS /* Total number of interrupts */
#endif
/************************************************************************************
* Public Types
************************************************************************************/
/************************************************************************************
* Public Data
************************************************************************************/
#ifndef __ASSEMBLY__
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/************************************************************************************
* Public Functions
************************************************************************************/
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif
#endif /* __ARCH_ARM_INCLUDE_EFM32_IRQ_H */

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arch/arm/include/elf.h
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@ -1,243 +0,0 @@
/****************************************************************************
* arch/arm/include/syscall.h
*
* Copyright (C) 2012 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Reference: "ELF for the ARM® Architecture," ARM IHI 0044D, current through
* ABI release 2.08, October 28, 2009, ARM Limited.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
#ifndef __ARCH_ARM_INCLUDE_ELF_H
#define __ARCH_ARM_INCLUDE_ELF_H
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* 4.3.1 ELF Identification. Should have:
*
* e_machine = EM_ARM
* e_ident[EI_CLASS] = ELFCLASS32
* e_ident[EI_DATA] = ELFDATA2LSB (little endian) or ELFDATA2MSB (big endian)
*/
#if 0 /* Defined in include/elf32.h */
#define EM_ARM 40
#endif
/* Table 4-2, ARM-specific e_flags */
#define EF_ARM_EABI_MASK 0xff000000
#define EF_ARM_EABI_UNKNOWN 0x00000000
#define EF_ARM_EABI_VER1 0x01000000
#define EF_ARM_EABI_VER2 0x02000000
#define EF_ARM_EABI_VER3 0x03000000
#define EF_ARM_EABI_VER4 0x04000000
#define EF_ARM_EABI_VER5 0x05000000
#define EF_ARM_BE8 0x00800000
/* Table 4-4, Processor specific section types */
#define SHT_ARM_EXIDX 0x70000001 /* Exception Index table */
#define SHT_ARM_PREEMPTMAP 0x70000002 /* BPABI DLL dynamic linking pre-emption map */
#define SHT_ARM_ATTRIBUTES 0x70000003 /* Object file compatibility attributes */
#define SHT_ARM_DEBUGOVERLAY 0x70000004
#define SHT_ARM_OVERLAYSECTION 0x70000005
/* 4.7.1 Relocation codes
*
* S (when used on its own) is the address of the symbol.
* A is the addend for the relocation.
* P is the address of the place being relocated (derived from r_offset).
* Pa is the adjusted address of the place being relocated, defined as (P & 0xFFFFFFFC).
* T is 1 if the target symbol S has type STT_FUNC and the symbol addresses a Thumb instruction;
* it is 0 otherwise.
* B(S) is the addressing origin of the output segment defining the symbol S.
* GOT_ORG is the addressing origin of the Global Offset Table
* GOT(S) is the address of the GOT entry for the symbol S.
*/
#define R_ARM_NONE 0 /* No relocation */
#define R_ARM_PC24 1 /* ARM ((S + A) | T) - P */
#define R_ARM_ABS32 2 /* Data (S + A) | T */
#define R_ARM_REL32 3 /* Data ((S + A) | T) - P */
#define R_ARM_LDR_PC_G0 4 /* ARM S + A - P */
#define R_ARM_ABS16 5 /* Data S + A */
#define R_ARM_ABS12 6 /* ARM S + A */
#define R_ARM_THM_ABS5 7 /* Thumb16 S + A */
#define R_ARM_ABS8 8 /* Data S + A */
#define R_ARM_SBREL32 9 /* Data ((S + A) | T) - B(S) */
#define R_ARM_THM_CALL 10 /* Thumb32 ((S + A) | T) - P */
#define R_ARM_THM_PC8 11 /* Thumb16 S + A - Pa */
#define R_ARM_BREL_ADJ 12 /* Data ?B(S) + A */
#define R_ARM_TLS_DESC 13 /* Data */
#define R_ARM_THM_SWI8 14 /* Obsolete */
#define R_ARM_XPC25 15 /* Obsolete */
#define R_ARM_THM_XPC22 16 /* Obsolete */
#define R_ARM_TLS_DTPMOD32 17 /* Data Module[S] */
#define R_ARM_TLS_DTPOFF32 18 /* Data S + A - TLS */
#define R_ARM_TLS_TPOFF32 19 /* Data S + A - tp */
#define R_ARM_COPY 20 /* Miscellaneous */
#define R_ARM_GLOB_DAT 21 /* Data (S + A) | T */
#define R_ARM_JUMP_SLOT 22 /* Data (S + A) | T */
#define R_ARM_RELATIVE 23 /* Data B(S) + A */
#define R_ARM_GOTOFF32 24 /* Data ((S + A) | T) - GOT_ORG */
#define R_ARM_BASE_PREL 25 /* Data B(S) + A - P */
#define R_ARM_GOT_BREL 26 /* Data GOT(S) + A - GOT_ORG */
#define R_ARM_PLT32 27 /* ARM ((S + A) | T) - P */
#define R_ARM_CALL 28 /* ARM ((S + A) | T) - P */
#define R_ARM_JUMP24 29 /* ARM ((S + A) | T) - P */
#define R_ARM_THM_JUMP24 30 /* Thumb32 ((S + A) | T) - P */
#define R_ARM_BASE_ABS 31 /* Data B(S) + A */
#define R_ARM_ALU_PCREL_7_0 32 /* Obsolete */
#define R_ARM_ALU_PCREL_15_8 33 /* Obsolete */
#define R_ARM_ALU_PCREL_23_15 34 /* Obsolete */
#define R_ARM_LDR_SBREL_11_0_NC 35 /* ARM S + A - B(S) */
#define R_ARM_ALU_SBREL_19_12_NC 36 /* ARM S + A - B(S) */
#define R_ARM_ALU_SBREL_27_20_CK 37 /* ARM S + A - B(S) */
#define R_ARM_TARGET1 38 /* Miscellaneous (S + A) | T or ((S + A) | T) - P */
#define R_ARM_SBREL31 39 /* Data ((S + A) | T) - B(S) */
#define R_ARM_V4BX 40 /* Miscellaneous */
#define R_ARM_TARGET2 41 /* Miscellaneous */
#define R_ARM_PREL31 42 /* Data ((S + A) | T) - P */
#define R_ARM_MOVW_ABS_NC 43 /* ARM (S + A) | T */
#define R_ARM_MOVT_ABS 44 /* ARM S + A */
#define R_ARM_MOVW_PREL_NC 45 /* ARM ((S + A) | T) - P */
#define R_ARM_MOVT_PREL 46 /* ARM S + A - P */
#define R_ARM_THM_MOVW_ABS_NC 47 /* Thumb32 (S + A) | T */
#define R_ARM_THM_MOVT_ABS 48 /* Thumb32 S + A */
#define R_ARM_THM_MOVW_PREL_NC 49 /* Thumb32 ((S + A) | T) - P */
#define R_ARM_THM_MOVT_PREL 50 /* Thumb32 S + A - P */
#define R_ARM_THM_JUMP19 51 /* Thumb32 ((S + A) | T) - P */
#define R_ARM_THM_JUMP6 52 /* Thumb16 S + A - P */
#define R_ARM_THM_ALU_PREL_11_0 53 /* Thumb32 ((S + A) | T) - Pa */
#define R_ARM_THM_PC12 54 /* Thumb32 S + A - Pa */
#define R_ARM_ABS32_NOI 55 /* Data S + A */
#define R_ARM_REL32_NOI 56 /* Data S + A - P */
#define R_ARM_ALU_PC_G0_NC 57 /* ARM ((S + A) | T) - P */
#define R_ARM_ALU_PC_G0 58 /* ARM ((S + A) | T) - P */
#define R_ARM_ALU_PC_G1_NC 59 /* ARM ((S + A) | T) - P */
#define R_ARM_ALU_PC_G1 60 /* ARM ((S + A) | T) - P */
#define R_ARM_ALU_PC_G2 61 /* ARM ((S + A) | T) - P */
#define R_ARM_LDR_PC_G1 62 /* ARM S + A - P */
#define R_ARM_LDR_PC_G2 63 /* ARM S + A - P */
#define R_ARM_LDRS_PC_G0 64 /* ARM S + A - P */
#define R_ARM_LDRS_PC_G1 65 /* ARM S + A - P */
#define R_ARM_LDRS_PC_G2 66 /* ARM S + A - P */
#define R_ARM_LDC_PC_G0 67 /* ARM S + A - P */
#define R_ARM_LDC_PC_G1 68 /* ARM S + A - P */
#define R_ARM_LDC_PC_G2 69 /* ARM S + A - P */
#define R_ARM_ALU_SB_G0_NC 70 /* ARM ((S + A) | T) - B(S) */
#define R_ARM_ALU_SB_G0 71 /* ARM ((S + A) | T) - B(S) */
#define R_ARM_ALU_SB_G1_NC 72 /* ARM ((S + A) | T) - B(S) */
#define R_ARM_ALU_SB_G1 73 /* ARM ((S + A) | T) - B(S) */
#define R_ARM_ALU_SB_G2 74 /* ARM ((S + A) | T) - B(S) */
#define R_ARM_LDR_SB_G0 75 /* ARM S + A - B(S) */
#define R_ARM_LDR_SB_G1 76 /* ARM S + A - B(S) */
#define R_ARM_LDR_SB_G2 77 /* ARM S + A - B(S) */
#define R_ARM_LDRS_SB_G0 78 /* ARM S + A - B(S) */
#define R_ARM_LDRS_SB_G1 79 /* ARM S + A - B(S) */
#define R_ARM_LDRS_SB_G2 80 /* ARM S + A - B(S) */
#define R_ARM_LDC_SB_G0 81 /* ARM S + A - B(S) */
#define R_ARM_LDC_SB_G1 82 /* ARM S + A - B(S) */
#define R_ARM_LDC_SB_G2 83 /* ARM S + A - B(S) */
#define R_ARM_MOVW_BREL_NC 84 /* ARM ((S + A) | T) - B(S) */
#define R_ARM_MOVT_BREL 85 /* ARM S + A - B(S) */
#define R_ARM_MOVW_BREL 86 /* ARM ((S + A) | T) - B(S) */
#define R_ARM_THM_MOVW_BREL_NC 87 /* Thumb32 ((S + A) | T) - B(S) */
#define R_ARM_THM_MOVT_BREL 88 /* Thumb32 S + A - B(S) */
#define R_ARM_THM_MOVW_BREL 89 /* Thumb32 ((S + A) | T) - B(S) */
#define R_ARM_TLS_GOTDESC 90 /* Data */
#define R_ARM_TLS_CALL 91 /* ARM */
#define R_ARM_TLS_DESCSEQ 92 /* ARM TLS relaxation */
#define R_ARM_THM_TLS_CALL 93 /* Thumb32 */
#define R_ARM_PLT32_ABS 94 /* Data PLT(S) + A */
#define R_ARM_GOT_ABS 95 /* Data GOT(S) + A */
#define R_ARM_GOT_PREL 96 /* Data GOT(S) + A - P */
#define R_ARM_GOT_BREL12 97 /* ARM GOT(S) + A - GOT_ORG */
#define R_ARM_GOTOFF12 98 /* ARM S + A - GOT_ORG */
#define R_ARM_GOTRELAX 99 /* Miscellaneous */
#define R_ARM_GNU_VTENTRY 100 /* Data */
#define R_ARM_GNU_VTINHERIT 101 /* Data */
#define R_ARM_THM_JUMP11 102 /* Thumb16 S + A - P */
#define R_ARM_THM_JUMP8 103 /* Thumb16 S + A - P */
#define R_ARM_TLS_GD32 104 /* Data GOT(S) + A - P */
#define R_ARM_TLS_LDM32 105 /* Data GOT(S) + A - P */
#define R_ARM_TLS_LDO32 106 /* Data S + A - TLS */
#define R_ARM_TLS_IE32 107 /* Data GOT(S) + A - P */
#define R_ARM_TLS_LE32 108 /* Data S + A - tp */
#define R_ARM_TLS_LDO12 109 /* ARM S + A - TLS */
#define R_ARM_TLS_LE12 110 /* ARM S + A - tp */
#define R_ARM_TLS_IE12GP 111 /* ARM GOT(S) + A - GOT_ORG */
#define R_ARM_ME_TOO 128 /* Obsolete */
#define R_ARM_THM_TLS_DESCSEQ16 129 /* Thumb16 */
#define R_ARM_THM_TLS_DESCSEQ32 130 /* Thumb32 */
/* 5.2.1 Platform architecture compatibility data */
#define PT_ARM_ARCHEXT_FMTMSK 0xff000000
#define PT_ARM_ARCHEXT_PROFMSK 0x00ff0000
#define PT_ARM_ARCHEXT_ARCHMSK 0x000000ff
#define PT_ARM_ARCHEXT_FMT_OS 0x00000000
#define PT_ARM_ARCHEXT_FMT_ABI 0x01000000
#define PT_ARM_ARCHEXT_PROF_NONE 0x00000000
#define PT_ARM_ARCHEXT_PROF_ARM 0x00410000
#define PT_ARM_ARCHEXT_PROF_RT 0x00520000
#define PT_ARM_ARCHEXT_PROF_MC 0x004d0000
#define PT_ARM_ARCHEXT_PROF_CLASSIC 0x00530000
#define PT_ARM_ARCHEXT_ARCH_UNKNOWN 0x00
#define PT_ARM_ARCHEXT_ARCHv4 0x01
#define PT_ARM_ARCHEXT_ARCHv4T 0x02
#define PT_ARM_ARCHEXT_ARCHv5T 0x03
#define PT_ARM_ARCHEXT_ARCHv5TE 0x04
#define PT_ARM_ARCHEXT_ARCHv5TEJ 0x05
#define PT_ARM_ARCHEXT_ARCHv6 0x06
#define PT_ARM_ARCHEXT_ARCHv6KZ 0x07
#define PT_ARM_ARCHEXT_ARCHv6T2 0x08
#define PT_ARM_ARCHEXT_ARCHv6K 0x09
#define PT_ARM_ARCHEXT_ARCHv7 0x0a
#define PT_ARM_ARCHEXT_ARCHv6M 0x0b
#define PT_ARM_ARCHEXT_ARCHv6SM 0x0c
#define PT_ARM_ARCHEXT_ARCHv7EM 0x0d
/* Table 5-6, ARM-specific dynamic array tags */
#define DT_ARM_RESERVED1 0x70000000
#define DT_ARM_SYMTABSZ 0x70000001
#define DT_ARM_PREEMPTMAP 0x70000002
#define DT_ARM_RESERVED2 0x70000003
#endif /* __ARCH_ARM_INCLUDE_ELF_H */

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arch/arm/include/imx/irq.h
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/****************************************************************************
* arch/arm/include/imx/irq.h
*
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/* This file should never be included directed but, rather,
* only indirectly through nuttx/irq.h
*/
#ifndef __ARCH_ARM_INCLUDE_IMX_IRQ_H
#define __ARCH_ARM_INCLUDE_IMX_IRQ_H
/****************************************************************************
* Included Files
****************************************************************************/
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* i.MX1 Interrupts */
#ifndef CONFIG_ARCH_CHIP_IMXL
# define IMX_IRQ_UART3PFERR ( 0)
# define IMX_IRQ_UART3RTS ( 1)
# define IMX_IRQ_UART3DTR ( 2)
# define IMX_IRQ_UART3UARTC ( 3)
# define IMX_IRQ_UART3TX ( 4)
# define IMX_IRQ_PENUP ( 5)
#endif
#define IMX_IRQ_CSI ( 6)
#define IMX_IRQ_MMAMAC ( 7)
#define IMX_IRQ_MMA ( 8)
#ifndef CONFIG_ARCH_CHIP_IMXL
# define IMX_IRQ_COMP ( 9)
#endif
#define IMX_IRQ_MSHCXINT (10)
#define IMX_IRQ_GPIOPORTA (11)
#define IMX_IRQ_GPIOPORTB (12)
#define IMX_IRQ_GPIOPORTC (13)
#define IMX_IRQ_LCDC (14)
#ifndef CONFIG_ARCH_CHIP_IMXL
# define IMX_IRQ_SIM (15)
# define IMX_IRQ_SIMDATA (16)
#endif
#define IMX_IRQ_RTC (17)
#define IMX_IRQ_RTCSAMINT (18)
#define IMX_IRQ_UART2PFERR (19)
#define IMX_IRQ_UART2RTS (20)
#define IMX_IRQ_UART2DTR (21)
#define IMX_IRQ_UART2UARTC (22)
#define IMX_IRQ_UART2TX (23)
#define IMX_IRQ_UART2RX (24)
#define IMX_IRQ_UART1PFERR (25)
#define IMX_IRQ_UART1RTS (26)
#define IMX_IRQ_UART1DTR (27)
#define IMX_IRQ_UART1UARTC (28)
#define IMX_IRQ_UART1TX (29)
#define IMX_IRQ_UART1RX (30)
#ifndef CONFIG_ARCH_CHIP_IMXL
# define IMX_IRQ_PENDATA (33)
#endif
#define IMX_IRQ_PWM (34)
#define IMX_IRQ_MMCSD (35)
#ifndef CONFIG_ARCH_CHIP_IMXL
# define IMX_IRQ_SSI2TX (36)
# define IMX_IRQ_SSI2RX (37)
# define IMX_IRQ_SSI2ERR (38)
#endif
#define IMX_IRQ_I2C (39)
#define IMX_IRQ_CSPI2 (40)
#define IMX_IRQ_CSPI1 (41)
#define IMX_IRQ_SSITX (42)
#define IMX_IRQ_SSITXERR (43)
#define IMX_IRQ_SSIRX (44)
#define IMX_IRQ_SSIRXERR (45)
#ifndef CONFIG_ARCH_CHIP_IMXL
# define IMX_IRQ_TOUCH (46)
#endif
#define IMX_IRQ_USBD0 (47)
#define IMX_IRQ_USBD1 (48)
#define IMX_IRQ_USBD2 (49)
#define IMX_IRQ_USBD3 (50)
#define IMX_IRQ_USBD4 (51)
#define IMX_IRQ_USBD5 (52)
#define IMX_IRQ_USBD6 (53)
#ifndef CONFIG_ARCH_CHIP_IMXL
# define IMX_IRQ_UART3RX (54)
# define IMX_IRQ_BTSYS (55)
# define IMX_IRQ_BTTIM (56)
# define IMX_IRQ_BTWUI (57)
#endif
#define IMX_IRQ_TIMER2 (58)
#define IMX_IRQ_TIMER1 (59)
#define IMX_IRQ_DMAERR (60)
#define IMX_IRQ_DMA (61)
#define IMX_IRQ_GPIOPORTD (62)
#define IMX_IRQ_WDT (63)
#define IMX_IRQ_SYSTIMER IMX_IRQ_TIMER1
#define NR_IRQS (64)
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Inline functions
****************************************************************************/
/****************************************************************************
* Public Variables
****************************************************************************/
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#ifndef __ASSEMBLY__
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif
#endif /* __ARCH_ARM_INCLUDE_IMX_IRQ_H */

106
arch/arm/include/irq.h
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/****************************************************************************
* arch/arm/include/irq.h
*
* Copyright (C) 2007-2009, 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/* This file should never be included directed but, rather, only indirectly
* through nuttx/irq.h
*/
#ifndef __ARCH_ARM_INCLUDE_IRQ_H
#define __ARCH_ARM_INCLUDE_IRQ_H
/****************************************************************************
* Included Files
****************************************************************************/
/* Include NuttX-specific IRQ definitions */
#include <nuttx/irq.h>
/* Include chip-specific IRQ definitions (including IRQ numbers) */
#include <arch/chip/irq.h>
/* Include ARM architecture-specific IRQ definitions (including register
* save structure and irqsave()/irqrestore() macros)
*/
#if defined(CONFIG_ARCH_CORTEXA5) || defined(CONFIG_ARCH_CORTEXA8)
# include <arch/armv7-a/irq.h>
#elif defined(CONFIG_ARCH_CORTEXM3) || defined(CONFIG_ARCH_CORTEXM4) || \
defined(CONFIG_ARCH_CORTEXM7)
# include <arch/armv7-m/irq.h>
#elif defined(CONFIG_ARCH_CORTEXM0)
# include <arch/armv6-m/irq.h>
#else
# include <arch/arm/irq.h>
#endif
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Inline functions
****************************************************************************/
/****************************************************************************
* Public Variables
****************************************************************************/
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#ifndef __ASSEMBLY__
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif
#endif /* __ARCH_ARM_INCLUDE_IRQ_H */

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/************************************************************************************
* arch/arm/include/kinetis/irq.h
*
* Copyright (C) 2011, 2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
/* This file should never be included directed but, rather, only indirectly through
* nuttx/irq.h
*/
#ifndef __ARCH_ARM_INCLUDE_KINETIS_IRQ_H
#define __ARCH_ARM_INCLUDE_KINETIS_IRQ_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include <nuttx/irq.h>
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* IRQ numbers **********************************************************************/
/* The IRQ numbers corresponds directly to vector numbers and hence map directly to
* bits in the NVIC. This does, however, waste several words of memory in the IRQ
* to handle mapping tables.
*/
/* Processor Exceptions (vectors 0-15) */
#define KINETIS_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG) */
/* Vector 0: Reset stack pointer value */
/* Vector 1: Reset (not handler as an IRQ) */
#define KINETIS_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */
#define KINETIS_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */
#define KINETIS_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */
#define KINETIS_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */
#define KINETIS_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */
/* Vectors 7-10: Reserved */
#define KINETIS_IRQ_SVCALL (11) /* Vector 11: SVC call */
#define KINETIS_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */
/* Vector 13: Reserved */
#define KINETIS_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */
#define KINETIS_IRQ_SYSTICK (15) /* Vector 15: System tick */
/* External interrupts (vectors >= 16) */
#define KINETIS_IRQ_EXTINT (16)
/* K20 Family ***********************************************************************
*
* The interrupt vectors for the following parts is defined in Freescale document
* K20P64M72SF1RM
*/
#if defined(CONFIG_ARCH_CHIP_MK20DX256VLH7)
# define KINETIS_IRQ_DMACH0 (16) /* Vector 16: DMA channel 0 transfer complete */
# define KINETIS_IRQ_DMACH1 (17) /* Vector 17: DMA channel 1 transfer complete */
# define KINETIS_IRQ_DMACH2 (18) /* Vector 18: DMA channel 2 transfer complete */
# define KINETIS_IRQ_DMACH3 (19) /* Vector 19: DMA channel 3 transfer complete */
# define KINETIS_IRQ_DMACH4 (20) /* Vector 20: DMA channel 4 transfer complete */
# define KINETIS_IRQ_DMACH5 (21) /* Vector 21: DMA channel 5 transfer complete */
# define KINETIS_IRQ_DMACH6 (22) /* Vector 22: DMA channel 6 transfer complete */
# define KINETIS_IRQ_DMACH7 (23) /* Vector 23: DMA channel 7 transfer complete */
# define KINETIS_IRQ_DMACH8 (24) /* Vector 24: DMA channel 8 transfer complete */
# define KINETIS_IRQ_DMACH9 (25) /* Vector 25: DMA channel 9 transfer complete */
# define KINETIS_IRQ_DMACH10 (26) /* Vector 26: DMA channel 10 transfer complete */
# define KINETIS_IRQ_DMACH11 (27) /* Vector 27: DMA channel 11 transfer complete */
# define KINETIS_IRQ_DMACH12 (28) /* Vector 28: DMA channel 12 transfer complete */
# define KINETIS_IRQ_DMACH13 (29) /* Vector 29: DMA channel 13 transfer complete */
# define KINETIS_IRQ_DMACH14 (30) /* Vector 30: DMA channel 14 transfer complete */
# define KINETIS_IRQ_DMACH15 (31) /* Vector 31: DMA channel 15 transfer complete */
# define KINETIS_IRQ_DMAERR (32) /* Vector 32: DMA error interrupt channels 0-15 */
# define KINETIS_IRQ_FLASHCC (34) /* Vector 34: Flash memory command complete */
# define KINETIS_IRQ_FLASHRC (35) /* Vector 35: Flash memory read collision */
# define KINETIS_IRQ_SMCLVD (36) /* Vector 36: Mode Controller low-voltage
* detect, low-voltage warning */
# define KINETIS_IRQ_LLWU (37) /* Vector 37: LLWU Normal Low Leakage Wakeup */
# define KINETIS_IRQ_WDOG (38) /* Vector 38: Watchdog */
# define KINETIS_IRQ_I2C0 (40) /* Vector 40: I2C0 */
# define KINETIS_IRQ_I2C1 (41) /* Vector 41: I2C1 */
# define KINETIS_IRQ_SPI0 (42) /* Vector 42: SPI0 all sources */
# define KINETIS_IRQ_SPI1 (43) /* Vector 43: SPI1 all sources */
# define KINETIS_IRQ_CAN0MB (45) /* Vector 45: CAN0 OR'ed Message buffer (0-15) */
# define KINETIS_IRQ_CAN0BO (46) /* Vector 46: CAN0 Bus Off */
# define KINETIS_IRQ_CAN0ERR (47) /* Vector 47: CAN0 Error */
# define KINETIS_IRQ_CAN0TW (48) /* Vector 48: CAN0 Transmit Warning */
# define KINETIS_IRQ_CAN0RW (49) /* Vector 49: CAN0 Receive Warning */
# define KINETIS_IRQ_CAN0WU (50) /* Vector 50: CAN0 Wake UP */
//TODO UART0_LON
# define KINETIS_IRQ_UART0S (61) /* Vector 61: UART0 status */
# define KINETIS_IRQ_UART0E (62) /* Vector 62: UART0 error */
# define KINETIS_IRQ_UART1S (63) /* Vector 63: UART1 status */
# define KINETIS_IRQ_UART1E (64) /* Vector 64: UART1 error */
# define KINETIS_IRQ_UART2S (65) /* Vector 65: UART2 status */
# define KINETIS_IRQ_UART2E (66) /* Vector 66: UART2 error */
# define KINETIS_IRQ_ADC0 (73) /* Vector 73: ADC0 */
# define KINETIS_IRQ_ADC1 (74) /* Vector 74: ADC1 */
# define KINETIS_IRQ_CMP0 (75) /* Vector 75: CMP0 */
# define KINETIS_IRQ_CMP1 (76) /* Vector 76: CMP1 */
# define KINETIS_IRQ_CMP2 (77) /* Vector 77: CMP2 */
# define KINETIS_IRQ_FTM0 (78) /* Vector 78: FTM0 all sources */
# define KINETIS_IRQ_FTM1 (79) /* Vector 79: FTM1 all sources */
# define KINETIS_IRQ_FTM2 (80) /* Vector 80: FTM2 all sources */
# define KINETIS_IRQ_CMT (81) /* Vector 81: CMT */
# define KINETIS_IRQ_RTC (82) /* Vector 82: RTC alarm interrupt */
//TODO RTC_SECOND
# define KINETIS_IRQ_PITCH0 (84) /* Vector 84: PIT channel 0 */
# define KINETIS_IRQ_PITCH1 (85) /* Vector 85: PIT channel 1 */
# define KINETIS_IRQ_PITCH2 (86) /* Vector 86: PIT channel 2 */
# define KINETIS_IRQ_PITCH3 (87) /* Vector 87: PIT channel 3 */
# define KINETIS_IRQ_PDB (88) /* Vector 88: PDB */
# define KINETIS_IRQ_USBOTG (89) /* Vector 88: USB OTG */
# define KINETIS_IRQ_USBCD (90) /* Vector 90: USB charger detect */
# define KINETIS_IRQ_DAC0 (97) /* Vector 97: DAC0 */
# define KINETIS_IRQ_TSI (99) /* Vector 97: TSI all sources */
# define KINETIS_IRQ_MCG (100) /* Vector 100: MCG */
# define KINETIS_IRQ_LPT (101) /* Vector 101: Low power timer */
# define KINETIS_IRQ_PORTA (103) /* Vector 103: Pin detect port A */
# define KINETIS_IRQ_PORTB (104) /* Vector 104: Pin detect port B */
# define KINETIS_IRQ_PORTC (105) /* Vector 105: Pin detect port C */
# define KINETIS_IRQ_PORTD (106) /* Vector 106: Pin detect port D */
# define KINETIS_IRQ_PORTE (107) /* Vector 107: Pin detect port E */
# define KINETIS_IRQ_SWI (110) /* Vector 110: Software interrupt */
# define NR_VECTORS (111) /* 111 vectors */
# define NR_IRQS (111) /* 94 interrupts but 111 IRQ numbers */
/* K40 Family ***********************************************************************
*
* The interrupt vectors for the following parts is defined in Freescale document
* K40P144M100SF2RM
*/
#elif defined(CONFIG_ARCH_CHIP_MK40X128VLQ100) || defined(CONFIG_ARCH_CHIP_MK40X128VMD100) || \
defined(CONFIG_ARCH_CHIP_MK40X256VLQ100) || defined(CONFIG_ARCH_CHIP_MK40X256VMD100) || \
defined(CONFIG_ARCH_CHIP_MK40N512VLQ100) || defined(CONFIG_ARCH_CHIP_MK40N512VMD100)
# define KINETIS_IRQ_DMACH0 (16) /* Vector 16: DMA channel 0 transfer complete */
# define KINETIS_IRQ_DMACH1 (17) /* Vector 17: DMA channel 1 transfer complete */
# define KINETIS_IRQ_DMACH2 (18) /* Vector 18: DMA channel 2 transfer complete */
# define KINETIS_IRQ_DMACH3 (19) /* Vector 19: DMA channel 3 transfer complete */
# define KINETIS_IRQ_DMACH4 (20) /* Vector 20: DMA channel 4 transfer complete */
# define KINETIS_IRQ_DMACH5 (21) /* Vector 21: DMA channel 5 transfer complete */
# define KINETIS_IRQ_DMACH6 (22) /* Vector 22: DMA channel 6 transfer complete */
# define KINETIS_IRQ_DMACH7 (23) /* Vector 23: DMA channel 7 transfer complete */
# define KINETIS_IRQ_DMACH8 (24) /* Vector 24: DMA channel 8 transfer complete */
# define KINETIS_IRQ_DMACH9 (25) /* Vector 25: DMA channel 9 transfer complete */
# define KINETIS_IRQ_DMACH10 (26) /* Vector 26: DMA channel 10 transfer complete */
# define KINETIS_IRQ_DMACH11 (27) /* Vector 27: DMA channel 11 transfer complete */
# define KINETIS_IRQ_DMACH12 (28) /* Vector 28: DMA channel 12 transfer complete */
# define KINETIS_IRQ_DMACH13 (29) /* Vector 29: DMA channel 13 transfer complete */
# define KINETIS_IRQ_DMACH14 (30) /* Vector 30: DMA channel 14 transfer complete */
# define KINETIS_IRQ_DMACH15 (31) /* Vector 31: DMA channel 15 transfer complete */
# define KINETIS_IRQ_DMAERR (32) /* Vector 32: DMA error interrupt channels 0-15 */
# define KINETIS_IRQ_MCM (33) /* Vector 33: MCM Normal interrupt */
# define KINETIS_IRQ_FLASHCC (34) /* Vector 34: Flash memory command complete */
# define KINETIS_IRQ_FLASHRC (35) /* Vector 35: Flash memory read collision */
# define KINETIS_IRQ_SMCLVD (36) /* Vector 36: Mode Controller low-voltage
* detect, low-voltage warning */
# define KINETIS_IRQ_LLWU (37) /* Vector 37: LLWU Normal Low Leakage Wakeup */
# define KINETIS_IRQ_WDOG (38) /* Vector 38: Watchdog */
/* Vector 39: Reserved */
# define KINETIS_IRQ_I2C0 (40) /* Vector 40: I2C0 */
# define KINETIS_IRQ_I2C1 (41) /* Vector 41: I2C1 */
# define KINETIS_IRQ_SPI0 (42) /* Vector 42: SPI0 all sources */
# define KINETIS_IRQ_SPI1 (43) /* Vector 43: SPI1 all sources */
# define KINETIS_IRQ_SPI2 (44) /* Vector 44: SPI2 all sources */
# define KINETIS_IRQ_CAN0MB (45) /* Vector 45: CAN0 OR'ed Message buffer (0-15) */
# define KINETIS_IRQ_CAN0BO (46) /* Vector 46: CAN0 Bus Off */
# define KINETIS_IRQ_CAN0ERR (47) /* Vector 47: CAN0 Error */
# define KINETIS_IRQ_CAN0TW (48) /* Vector 48: CAN0 Transmit Warning */
# define KINETIS_IRQ_CAN0RW (49) /* Vector 49: CAN0 Receive Warning */
# define KINETIS_IRQ_CAN0WU (50) /* Vector 50: CAN0 Wake UP */
/* Vectors 51-52: Reserved */
# define KINETIS_IRQ_CAN1MB (53) /* Vector 53: CAN1 OR'ed Message buffer (0-15) */
# define KINETIS_IRQ_CAN1BO (54) /* Vector 54: CAN1 Bus Off */
# define KINETIS_IRQ_CAN1ERR (55) /* Vector 55: CAN1 Error */
# define KINETIS_IRQ_CAN1TW (56) /* Vector 56: CAN1 Transmit Warning */
# define KINETIS_IRQ_CAN1RW (57) /* Vector 57: CAN1 Receive Warning */
# define KINETIS_IRQ_CAN1WU (58) /* Vector 58: CAN1 Wake UP */
/* Vectors 59-60: Reserved */
# define KINETIS_IRQ_UART0S (61) /* Vector 61: UART0 status */
# define KINETIS_IRQ_UART0E (62) /* Vector 62: UART0 error */
# define KINETIS_IRQ_UART1S (63) /* Vector 63: UART1 status */
# define KINETIS_IRQ_UART1E (64) /* Vector 64: UART1 error */
# define KINETIS_IRQ_UART2S (65) /* Vector 65: UART2 status */
# define KINETIS_IRQ_UART2E (66) /* Vector 66: UART2 error */
# define KINETIS_IRQ_UART3S (67) /* Vector 67: UART3 status */
# define KINETIS_IRQ_UART3E (68) /* Vector 68: UART3 error */
# define KINETIS_IRQ_UART4S (69) /* Vector 69: UART4 status */
# define KINETIS_IRQ_UART4E (70) /* Vector 70: UART4 error */
# define KINETIS_IRQ_UART5S (71) /* Vector 71: UART5 status */
# define KINETIS_IRQ_UART5E (72) /* Vector 72: UART5 error */
# define KINETIS_IRQ_ADC0 (73) /* Vector 73: ADC0 */
# define KINETIS_IRQ_ADC1 (74) /* Vector 74: ADC1 */
# define KINETIS_IRQ_CMP0 (75) /* Vector 75: CMP0 */
# define KINETIS_IRQ_CMP1 (76) /* Vector 76: CMP1 */
# define KINETIS_IRQ_CMP2 (77) /* Vector 77: CMP2 */
# define KINETIS_IRQ_FTM0 (78) /* Vector 78: FTM0 all sources */
# define KINETIS_IRQ_FTM1 (79) /* Vector 79: FTM1 all sources */
# define KINETIS_IRQ_FTM2 (80) /* Vector 80: FTM2 all sources */
# define KINETIS_IRQ_CMT (81) /* Vector 81: CMT */
# define KINETIS_IRQ_RTC (82) /* Vector 82: RTC alarm interrupt */
/* Vector 83: Reserved */
# define KINETIS_IRQ_PITCH0 (84) /* Vector 84: PIT channel 0 */
# define KINETIS_IRQ_PITCH1 (85) /* Vector 85: PIT channel 1 */
# define KINETIS_IRQ_PITCH2 (86) /* Vector 86: PIT channel 2 */
# define KINETIS_IRQ_PITCH3 (87) /* Vector 87: PIT channel 3 */
# define KINETIS_IRQ_PDB (88) /* Vector 88: PDB */
# define KINETIS_IRQ_USBOTG (89) /* Vector 88: USB OTG */
# define KINETIS_IRQ_USBCD (90) /* Vector 90: USB charger detect */
/* Vectors 91-94: Reserved */
# define KINETIS_IRQ_I2S0 (95) /* Vector 95: I2S0 */
# define KINETIS_IRQ_SDHC (96) /* Vector 96: SDHC */
# define KINETIS_IRQ_DAC0 (97) /* Vector 97: DAC0 */
# define KINETIS_IRQ_DAC1 (98) /* Vector 98: DAC1 */
# define KINETIS_IRQ_TSI (99) /* Vector 97: TSI all sources */
# define KINETIS_IRQ_MCG (100) /* Vector 100: MCG */
# define KINETIS_IRQ_LPT (101) /* Vector 101: Low power timer */
# define KINETIS_IRQ_SLCD (102) /* Vector 102: Segment LCD all sources */
# define KINETIS_IRQ_PORTA (103) /* Vector 103: Pin detect port A */
# define KINETIS_IRQ_PORTB (104) /* Vector 104: Pin detect port B */
# define KINETIS_IRQ_PORTC (105) /* Vector 105: Pin detect port C */
# define KINETIS_IRQ_PORTD (106) /* Vector 106: Pin detect port D */
# define KINETIS_IRQ_PORTE (107) /* Vector 107: Pin detect port E */
/* Vectors 108-109: Reserved */
# define KINETIS_IRQ_SWI (110) /* Vector 110: Software interrupt */
/* Note that the total number of IRQ numbers supported is equal to the number of
* valid interrupt vectors. This is wasteful in that certain tables are sized by
* this value. There are only 94 valid interrupts so, potentially the numver of
* IRQs to could be reduced to 94. However, equating IRQ numbers with vector numbers
* also simplifies operations on NVIC registers and (at least in my state of mind
* now) seems to justify the waste.
*/
# define NR_VECTORS (111) /* 111 vectors */
# define NR_IRQS (111) /* 94 interrupts but 111 IRQ numbers */
/* K60 Family ***********************************************************************
*
* The memory map for the following parts is defined in Freescale document
* K60P144M100SF2RM
*/
#elif defined(CONFIG_ARCH_CHIP_MK60N256VLQ100) || defined(CONFIG_ARCH_CHIP_MK60X256VLQ100) || \
defined(CONFIG_ARCH_CHIP_MK60N512VLQ100) || defined(CONFIG_ARCH_CHIP_MK60N256VMD100) || \
defined(CONFIG_ARCH_CHIP_MK60X256VMD100) || defined(CONFIG_ARCH_CHIP_MK60N512VMD100)
# define KINETIS_IRQ_DMACH0 (16) /* Vector 16: DMA channel 0 transfer complete */
# define KINETIS_IRQ_DMACH1 (17) /* Vector 17: DMA channel 1 transfer complete */
# define KINETIS_IRQ_DMACH2 (18) /* Vector 18: DMA channel 2 transfer complete */
# define KINETIS_IRQ_DMACH3 (19) /* Vector 19: DMA channel 3 transfer complete */
# define KINETIS_IRQ_DMACH4 (20) /* Vector 20: DMA channel 4 transfer complete */
# define KINETIS_IRQ_DMACH5 (21) /* Vector 21: DMA channel 5 transfer complete */
# define KINETIS_IRQ_DMACH6 (22) /* Vector 22: DMA channel 6 transfer complete */
# define KINETIS_IRQ_DMACH7 (23) /* Vector 23: DMA channel 7 transfer complete */
# define KINETIS_IRQ_DMACH8 (24) /* Vector 24: DMA channel 8 transfer complete */
# define KINETIS_IRQ_DMACH9 (25) /* Vector 25: DMA channel 9 transfer complete */
# define KINETIS_IRQ_DMACH10 (26) /* Vector 26: DMA channel 10 transfer complete */
# define KINETIS_IRQ_DMACH11 (27) /* Vector 27: DMA channel 11 transfer complete */
# define KINETIS_IRQ_DMACH12 (28) /* Vector 28: DMA channel 12 transfer complete */
# define KINETIS_IRQ_DMACH13 (29) /* Vector 29: DMA channel 13 transfer complete */
# define KINETIS_IRQ_DMACH14 (30) /* Vector 30: DMA channel 14 transfer complete */
# define KINETIS_IRQ_DMACH15 (31) /* Vector 31: DMA channel 15 transfer complete */
# define KINETIS_IRQ_DMAERR (32) /* Vector 32: DMA error interrupt channels 0-15 */
# define KINETIS_IRQ_MCM (33) /* Vector 33: MCM Normal interrupt */
# define KINETIS_IRQ_FLASHCC (34) /* Vector 34: Flash memory command complete */
# define KINETIS_IRQ_FLASHRC (35) /* Vector 35: Flash memory read collision */
# define KINETIS_IRQ_SMCLVD (36) /* Vector 36: Mode Controller low-voltage
* detect, low-voltage warning */
# define KINETIS_IRQ_LLWU (37) /* Vector 37: LLWU Normal Low Leakage Wakeup */
# define KINETIS_IRQ_WDOG (38) /* Vector 38: Watchdog */
# define KINETIS_IRQ_RNGB (39) /* Vector 39: Random number generator */
# define KINETIS_IRQ_I2C0 (40) /* Vector 40: I2C0 */
# define KINETIS_IRQ_I2C1 (41) /* Vector 41: I2C1 */
# define KINETIS_IRQ_SPI0 (42) /* Vector 42: SPI0 all sources */
# define KINETIS_IRQ_SPI1 (43) /* Vector 43: SPI1 all sources */
# define KINETIS_IRQ_SPI2 (44) /* Vector 44: SPI2 all sources */
# define KINETIS_IRQ_CAN0MB (45) /* Vector 45: CAN0 OR'ed Message buffer (0-15) */
# define KINETIS_IRQ_CAN0BO (46) /* Vector 46: CAN0 Bus Off */
# define KINETIS_IRQ_CAN0ERR (47) /* Vector 47: CAN0 Error */
# define KINETIS_IRQ_CAN0TW (48) /* Vector 48: CAN0 Transmit Warning */
# define KINETIS_IRQ_CAN0RW (49) /* Vector 49: CAN0 Receive Warning */
# define KINETIS_IRQ_CAN0WU (50) /* Vector 50: CAN0 Wake UP */
/* Vectors 51-52: Reserved */
# define KINETIS_IRQ_CAN1MB (53) /* Vector 53: CAN1 OR'ed Message buffer (0-15) */
# define KINETIS_IRQ_CAN1BO (54) /* Vector 54: CAN1 Bus Off */
# define KINETIS_IRQ_CAN1ERR (55) /* Vector 55: CAN1 Error */
# define KINETIS_IRQ_CAN1TW (56) /* Vector 56: CAN1 Transmit Warning */
# define KINETIS_IRQ_CAN1RW (57) /* Vector 57: CAN1 Receive Warning */
# define KINETIS_IRQ_CAN1WU (58) /* Vector 58: CAN1 Wake UP */
/* Vectors 59-60: Reserved */
# define KINETIS_IRQ_UART0S (61) /* Vector 61: UART0 status */
# define KINETIS_IRQ_UART0E (62) /* Vector 62: UART0 error */
# define KINETIS_IRQ_UART1S (63) /* Vector 63: UART1 status */
# define KINETIS_IRQ_UART1E (64) /* Vector 64: UART1 error */
# define KINETIS_IRQ_UART2S (65) /* Vector 65: UART2 status */
# define KINETIS_IRQ_UART2E (66) /* Vector 66: UART2 error */
# define KINETIS_IRQ_UART3S (67) /* Vector 67: UART3 status */
# define KINETIS_IRQ_UART3E (68) /* Vector 68: UART3 error */
# define KINETIS_IRQ_UART4S (69) /* Vector 69: UART4 status */
# define KINETIS_IRQ_UART4E (70) /* Vector 70: UART4 error */
# define KINETIS_IRQ_UART5S (71) /* Vector 71: UART5 status */
# define KINETIS_IRQ_UART5E (72) /* Vector 72: UART5 error */
# define KINETIS_IRQ_ADC0 (73) /* Vector 73: ADC0 */
# define KINETIS_IRQ_ADC1 (74) /* Vector 74: ADC1 */
# define KINETIS_IRQ_CMP0 (75) /* Vector 75: CMP0 */
# define KINETIS_IRQ_CMP1 (76) /* Vector 76: CMP1 */
# define KINETIS_IRQ_CMP2 (77) /* Vector 77: CMP2 */
# define KINETIS_IRQ_FTM0 (78) /* Vector 78: FTM0 all sources */
# define KINETIS_IRQ_FTM1 (79) /* Vector 79: FTM1 all sources */
# define KINETIS_IRQ_FTM2 (80) /* Vector 80: FTM2 all sources */
# define KINETIS_IRQ_CMT (81) /* Vector 81: CMT */
# define KINETIS_IRQ_RTC (82) /* Vector 82: RTC alarm interrupt */
/* Vector 83: Reserved */
# define KINETIS_IRQ_PITCH0 (84) /* Vector 84: PIT channel 0 */
# define KINETIS_IRQ_PITCH1 (85) /* Vector 85: PIT channel 1 */
# define KINETIS_IRQ_PITCH2 (86) /* Vector 86: PIT channel 2 */
# define KINETIS_IRQ_PITCH3 (87) /* Vector 87: PIT channel 3 */
# define KINETIS_IRQ_PDB (88) /* Vector 88: PDB */
# define KINETIS_IRQ_USBOTG (89) /* Vector 88: USB OTG */
# define KINETIS_IRQ_USBCD (90) /* Vector 90: USB charger detect */
# define KINETIS_IRQ_EMACTMR (91) /* Vector 91: Ethernet MAC IEEE 1588 timer interrupt */
# define KINETIS_IRQ_EMACTX (92) /* Vector 92: Ethernet MAC transmit interrupt */
# define KINETIS_IRQ_EMACRX (93) /* Vector 93: Ethernet MAC receive interrupt */
# define KINETIS_IRQ_EMACMISC (94) /* Vector 94: Ethernet MAC error and misc interrupt */
# define KINETIS_IRQ_I2S0 (95) /* Vector 95: I2S0 */
# define KINETIS_IRQ_SDHC (96) /* Vector 96: SDHC */
# define KINETIS_IRQ_DAC0 (97) /* Vector 97: DAC0 */
# define KINETIS_IRQ_DAC1 (98) /* Vector 98: DAC1 */
# define KINETIS_IRQ_TSI (99) /* Vector 97: TSI all sources */
# define KINETIS_IRQ_MCG (100) /* Vector 100: MCG */
# define KINETIS_IRQ_LPT (101) /* Vector 101: Low power timer */
/* Vector 102: Reserved */
# define KINETIS_IRQ_PORTA (103) /* Vector 103: Pin detect port A */
# define KINETIS_IRQ_PORTB (104) /* Vector 104: Pin detect port B */
# define KINETIS_IRQ_PORTC (105) /* Vector 105: Pin detect port C */
# define KINETIS_IRQ_PORTD (106) /* Vector 106: Pin detect port D */
# define KINETIS_IRQ_PORTE (107) /* Vector 107: Pin detect port E */
/* Vectors 108-119: Reserved */
/* Note that the total number of IRQ numbers supported is equal to the number of
* valid interrupt vectors. This is wasteful in that certain tables are sized by
* this value. There are only 97 valid interrupts so, potentially the number of
* IRQs to could be reduced to 97. However, equating IRQ numbers with vector numbers
* also simplifies operations on NVIC registers and (at least in my state of mind
* now) seems to justify the waste.
*/
# define NR_VECTORS (120) /* 120 vectors */
# define NR_IRQS (108) /* 120 interrupts but 108 IRQ numbers */
#else
/* The interrupt vectors for other parts are defined in other documents and may or
* may not be the same as above (the family members are all very similar) This
* error just means that you have to look at the document and determine for yourself
* if the vectors are the same.
*/
# error "No IRQ numbers for this Kinetis part"
#endif
/************************************************************************************
* Public Types
************************************************************************************/
/************************************************************************************
* Public Data
************************************************************************************/
#ifndef __ASSEMBLY__
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/************************************************************************************
* Public Functions
************************************************************************************/
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif
#endif /* __ARCH_ARM_INCLUDE_KINETIS_IRQ_H */

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arch/arm/include/kl/chip.h
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@ -1,193 +0,0 @@
/************************************************************************************
* arch/arm/include/kinetis/chip.h
*
* Copyright (C) 2013, 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_INCLUDE_KL_CHIP_H
#define __ARCH_ARM_INCLUDE_KL_CHIP_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Get customizations for each supported chip */
#if defined(CONFIG_ARCH_CHIP_MKL25Z64)
# define KL_Z64 1 /* Kinetics KL25Z128 family */
# define KL_FLASH_SIZE (64*1024) /* 64Kb */
# define KL_SRAM_SIZE (8*1024) /* 8Kb */
# undef KL_MPU /* No memory protection unit */
# undef KL_EXTBUS /* No external bus interface */
# define KL_NDMACH 4 /* Up to 4 DMA channels */
# undef KL_NENET /* No Ethernet controller */
# define KL_NUSBHOST 1 /* One USB host controller */
# define KL_NUSBOTG 1 /* With USB OTG controller */
# define KL_NUSBDEV 1 /* One USB device controller */
# undef KL_NSDHC /* No SD host controller */
# define KL_NTOUCHIF 1 /* Xtrinsic touch sensing interface */
# define KL_NI2C 2 /* Two I2C modules */
# define KL_NUART 3 /* Three UARTs */
# define KL_NSPI 2 /* Two SPI modules */
# undef KL_NCAN /* No CAN in 64-pin chips */
# define KL_NI2S 1 /* One I2S module */
# undef KL_NSLCD /* One segment LCD interface (up to 25x8/29x4) */
# define KL_NADC16 1 /* One 16-bit ADC */
# undef KL_NADC12 /* No 12-channel ADC */
# undef KL_NADC13 /* No 13-channel ADC */
# undef KL_NADC15 /* No 15-channel ADC */
# undef KL_NADC18 /* No 18-channel ADC */
# undef KL_NPGA /* No Programmable Gain Amplifiers */
# define KL_NCMP 1 /* One analog comparator */
# define KL_NDAC6 1 /* Three 6-bit DAC */
# define KL_NDAC12 1 /* Two 12-bit DAC */
# define KL_NVREF 1 /* Voltage reference */
# define KL_NTIMERS6 1 /* One 6 channel timer */
# define KL_NTIMERS2 2 /* Two 2 channel timers */
# undef KL_NRNG /* No random number generator */
# define KL_NRTC 1 /* Real time clock */
# undef KL_NMMCAU /* No hardware encryption */
# undef KL_NTAMPER /* No tamper detect */
# undef KL_NCRC /* No CRC */
#elif defined(CONFIG_ARCH_CHIP_MKL25Z128)
# define KL_Z128 1 /* Kinetics KL25Z128 family */
# define KL_FLASH_SIZE (128*1024) /* 64Kb */
# define KL_SRAM_SIZE (16*1024) /* 16Kb */
# undef KL_MPU /* No memory protection unit */
# undef KL_EXTBUS /* No external bus interface */
# define KL_NDMACH 4 /* Up to 4 DMA channels */
# undef KL_NENET /* No Ethernet controller */
# define KL_NUSBHOST 1 /* One USB host controller */
# define KL_NUSBOTG 1 /* With USB OTG controller */
# define KL_NUSBDEV 1 /* One USB device controller */
# undef KL_NSDHC /* No SD host controller */
# define KL_NTOUCHIF 1 /* Xtrinsic touch sensing interface */
# define KL_NI2C 2 /* Two I2C modules */
# define KL_NUART 3 /* Three UARTs */
# define KL_NSPI 2 /* Two SPI modules */
# undef KL_NCAN /* No CAN in 64-pin chips */
# define KL_NI2S 1 /* One I2S module */
# undef KL_NSLCD /* One segment LCD interface (up to 25x8/29x4) */
# define KL_NADC16 1 /* One 16-bit ADC */
# undef KL_NADC12 /* No 12-channel ADC */
# undef KL_NADC13 /* No 13-channel ADC */
# undef KL_NADC15 /* No 15-channel ADC */
# undef KL_NADC18 /* No 18-channel ADC */
# undef KL_NPGA /* No Programmable Gain Amplifiers */
# define KL_NCMP 1 /* One analog comparator */
# define KL_NDAC6 1 /* Three 6-bit DAC */
# define KL_NDAC12 1 /* Two 12-bit DAC */
# define KL_NVREF 1 /* Voltage reference */
# define KL_NTIMERS8 1 /* One 8 channel timers */
# undef KL_NTIMERS12 /* No 12 channel timers */
# undef KL_NTIMERS20 /* No 20 channel timers */
# undef KL_NRNG /* No random number generator */
# define KL_NRTC 1 /* Real time clock */
# undef KL_NMMCAU /* No hardware encryption */
# undef KL_NTAMPER /* No tamper detect */
# undef KL_NCRC /* No CRC */
#elif defined(CONFIG_ARCH_CHIP_MKL26Z128)
# define KL_Z128 1 /* Kinetics KL25Z128 family */
# define KL_FLASH_SIZE (128*1024) /* 64Kb */
# define KL_SRAM_SIZE (16*1024) /* 16Kb */
# undef KL_MPU /* No memory protection unit */
# undef KL_EXTBUS /* No external bus interface */
# define KL_NDMACH 4 /* Up to 4 DMA channels */
# undef KL_NENET /* No Ethernet controller */
# define KL_NUSBHOST 1 /* One USB host controller */
# define KL_NUSBOTG 1 /* With USB OTG controller */
# define KL_NUSBDEV 1 /* One USB device controller */
# undef KL_NSDHC /* No SD host controller */
# define KL_NTOUCHIF 1 /* Xtrinsic touch sensing interface */
# define KL_NI2C 2 /* Two I2C modules */
# define KL_NUART 3 /* Three UARTs */
# define KL_NSPI 2 /* Two SPI modules */
# undef KL_NCAN /* No CAN in 64-pin chips */
# define KL_NI2S 1 /* One I2S module */
# undef KL_NSLCD /* One segment LCD interface (up to 25x8/29x4) */
# define KL_NADC16 1 /* One 16-bit ADC */
# undef KL_NADC12 /* No 12-channel ADC */
# undef KL_NADC13 /* No 13-channel ADC */
# undef KL_NADC15 /* No 15-channel ADC */
# undef KL_NADC18 /* No 18-channel ADC */
# undef KL_NPGA /* No Programmable Gain Amplifiers */
# define KL_NCMP 1 /* One analog comparator */
# define KL_NDAC6 1 /* Three 6-bit DAC */
# define KL_NDAC12 1 /* Two 12-bit DAC */
# define KL_NVREF 1 /* Voltage reference */
# define KL_NTIMERS8 1 /* One 8 channel timers */
# undef KL_NTIMERS12 /* No 12 channel timers */
# undef KL_NTIMERS20 /* No 20 channel timers */
# undef KL_NRNG /* No random number generator */
# define KL_NRTC 1 /* Real time clock */
# undef KL_NMMCAU /* No hardware encryption */
# undef KL_NTAMPER /* No tamper detect */
# undef KL_NCRC /* No CRC */
#else
# error "Unsupported Kinetis chip"
#endif
/* NVIC priority levels *************************************************************/
/* Each priority field holds a priority value, 0-15. The lower the value, the greater
* the priority of the corresponding interrupt. The processor implements only
* bits[7:4] of each field, bits[3:0] read as zero and ignore writes.
*/
#define NVIC_SYSH_PRIORITY_MIN 0xc0 /* All bits[7:6] set is minimum priority */
#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */
#define NVIC_SYSH_PRIORITY_STEP 0x40 /* Steps between supported priority values */
/************************************************************************************
* Public Types
************************************************************************************/
/************************************************************************************
* Public Data
************************************************************************************/
/************************************************************************************
* Public Functions
************************************************************************************/
#endif /* __ARCH_ARM_INCLUDE_KL_CHIP_H */

212
arch/arm/include/kl/irq.h
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@ -1,212 +0,0 @@
/************************************************************************************
* arch/arm/include/kinetis/irq.h
*
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
/* This file should never be included directed but, rather, only indirectly through
* nuttx/irq.h
*/
#ifndef __ARCH_ARM_INCLUDE_KL_IRQ_H
#define __ARCH_ARM_INCLUDE_KL_IRQ_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include <nuttx/irq.h>
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* IRQ numbers **********************************************************************/
/* The IRQ numbers corresponds directly to vector numbers and hence map directly to
* bits in the NVIC. This does, however, waste several words of memory in the IRQ
* to handle mapping tables.
*/
/* Processor Exceptions (vectors 0-15) */
#define KL_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG) */
/* Vector 0: Reset stack pointer value */
/* Vector 1: Reset (not handler as an IRQ) */
#define KL_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */
#define KL_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */
/* Vectors 4-10: Reserved */
#define KL_IRQ_SVCALL (11) /* Vector 11: SVC call */
/* Vector 12-13: Reserved */
#define KL_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */
#define KL_IRQ_SYSTICK (15) /* Vector 15: System tick */
/* External interrupts (vectors >= 16) */
#define KL_IRQ_EXTINT (16)
/* K40 Family ***********************************************************************
*
* The interrupt vectors for the following parts is defined in Freescale document
* K40P144M100SF2RM
*/
#if defined(CONFIG_ARCH_CHIP_MKL25Z128) || defined(CONFIG_ARCH_CHIP_MKL25Z64)
# define KL_IRQ_DMACH0 (16) /* Vector 16: DMA channel 0 transfer complete */
# define KL_IRQ_DMACH1 (17) /* Vector 17: DMA channel 1 transfer complete */
# define KL_IRQ_DMACH2 (18) /* Vector 18: DMA channel 2 transfer complete */
# define KL_IRQ_DMACH3 (19) /* Vector 19: DMA channel 3 transfer complete */
/* Vector 20: Reserved */
# define KL_IRQ_FTFA (21) /* Vector 21: FTFA */
# define KL_IRQ_LVDLVW (22) /* Vector 22: LVD_LVW */
# define KL_IRQ_LLW (23) /* Vector 23: LLW */
# define KL_IRQ_I2C0 (24) /* Vector 24: I2C0 */
# define KL_IRQ_I2C1 (25) /* Vector 25: I2C1 */
# define KL_IRQ_SPI0 (26) /* Vector 26: SPI0 */
# define KL_IRQ_SPI1 (27) /* Vector 27: SPI1 */
# define KL_IRQ_UART0 (28) /* Vector 28: UART0 */
# define KL_IRQ_UART1 (29) /* Vector 29: UART1 */
# define KL_IRQ_UART2 (30) /* Vector 30: UART2 */
# define KL_IRQ_ADC0 (31) /* Vector 31: Analog Device Converter 0 */
# define KL_IRQ_CMP0 (32) /* Vector 32: Comparator 0 */
# define KL_IRQ_TPM0 (33) /* Vector 33: Timer/PWM Module 0 */
# define KL_IRQ_TPM1 (34) /* Vector 34: Timer/PWM Module 1 */
# define KL_IRQ_TPM2 (35) /* Vector 35: Timer/PWM Module 2 */
# define KL_IRQ_RTC (36) /* Vector 36: Realtime Clock */
# define KL_IRQ_RTCSEC (37) /* Vector 37: Realtime Clock, seconds interrupt */
# define KL_IRQ_PIT (38) /* Vector 38: Programmable Interrupt Timer */
/* Vector 39: Reserved */
# define KL_IRQ_USB0 (40) /* Vector 40: USB0 */
# define KL_IRQ_DAC0 (41) /* Vector 41: Digital Analog Converter 0 */
# define KL_IRQ_TSI0 (42) /* Vector 42: TSI0 */
# define KL_IRQ_MCG (43) /* Vector 43: MCG */
# define KL_IRQ_LPTIMER (44) /* Vector 44: Low Power Timer */
/* Vector 45: Reserved */
# define KL_IRQ_PORTA (46) /* Vector 46: GPIO Port A */
# define KL_IRQ_PORTD (47) /* Vector 47: GPIO Port D */
/* Note that the total number of IRQ numbers supported is equal to the number of
* valid interrupt vectors. This is wasteful in that certain tables are sized by
* this value. There are only 94 valid interrupts so, potentially the numver of
* IRQs to could be reduced to 94. However, equating IRQ numbers with vector numbers
* also simplifies operations on NVIC registers and (at least in my state of mind
* now) seems to justify the waste.
*/
# define NR_VECTORS (64) /* 64 vectors */
# define NR_IRQS (48) /* 64 interrupts but 48 IRQ numbers */
#elif defined(CONFIG_ARCH_CHIP_MKL26Z128)
# define KL_IRQ_DMACH0 (16) /* Vector 16: DMA channel 0 transfer complete */
# define KL_IRQ_DMACH1 (17) /* Vector 17: DMA channel 1 transfer complete */
# define KL_IRQ_DMACH2 (18) /* Vector 18: DMA channel 2 transfer complete */
# define KL_IRQ_DMACH3 (19) /* Vector 19: DMA channel 3 transfer complete */
/* Vector 20: Reserved */
# define KL_IRQ_FTFA (21) /* Vector 21: FTFA */
# define KL_IRQ_LVDLVW (22) /* Vector 22: LVD_LVW */
# define KL_IRQ_LLW (23) /* Vector 23: LLW */
# define KL_IRQ_I2C0 (24) /* Vector 24: I2C0 */
# define KL_IRQ_I2C1 (25) /* Vector 25: I2C1 */
# define KL_IRQ_SPI0 (26) /* Vector 26: SPI0 */
# define KL_IRQ_SPI1 (27) /* Vector 27: SPI1 */
# define KL_IRQ_UART0 (28) /* Vector 28: UART0 */
# define KL_IRQ_UART1 (29) /* Vector 29: UART1 */
# define KL_IRQ_UART2 (30) /* Vector 30: UART2 */
# define KL_IRQ_ADC0 (31) /* Vector 31: Analog Device Converter 0 */
# define KL_IRQ_CMP0 (32) /* Vector 32: Comparator 0 */
# define KL_IRQ_TPM0 (33) /* Vector 33: Timer/PWM Module 0 */
# define KL_IRQ_TPM1 (34) /* Vector 34: Timer/PWM Module 1 */
# define KL_IRQ_TPM2 (35) /* Vector 35: Timer/PWM Module 2 */
# define KL_IRQ_RTC (36) /* Vector 36: Realtime Clock */
# define KL_IRQ_RTCSEC (37) /* Vector 37: Realtime Clock, seconds interrupt */
# define KL_IRQ_PIT (38) /* Vector 38: Programmable Interrupt Timer */
/* Vector 39: Reserved */
# define KL_IRQ_USB0 (40) /* Vector 40: USB0 */
# define KL_IRQ_DAC0 (41) /* Vector 41: Digital Analog Converter 0 */
# define KL_IRQ_TSI0 (42) /* Vector 42: TSI0 */
# define KL_IRQ_MCG (43) /* Vector 43: MCG */
# define KL_IRQ_LPTIMER (44) /* Vector 44: Low Power Timer */
/* Vector 45: Reserved */
# define KL_IRQ_PORTA (46) /* Vector 46: GPIO Port A */
# define KL_IRQ_PORTD (47) /* Vector 47: GPIO Port D */
/* Note that the total number of IRQ numbers supported is equal to the number of
* valid interrupt vectors. This is wasteful in that certain tables are sized by
* this value. There are only 94 valid interrupts so, potentially the numver of
* IRQs to could be reduced to 94. However, equating IRQ numbers with vector numbers
* also simplifies operations on NVIC registers and (at least in my state of mind
* now) seems to justify the waste.
*/
# define NR_VECTORS (64) /* 64 vectors */
# define NR_IRQS (48) /* 64 interrupts but 48 IRQ numbers */
#else
/* The interrupt vectors for other parts are defined in other documents and may or
* may not be the same as above (the family members are all very similar) This
* error just means that you have to look at the document and determine for yourself
* if the vectors are the same.
*/
# error "No IRQ numbers for this Kinetis L part"
#endif
/************************************************************************************
* Public Types
************************************************************************************/
/************************************************************************************
* Public Data
************************************************************************************/
#ifndef __ASSEMBLY__
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/************************************************************************************
* Public Functions
************************************************************************************/
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif
#endif /* __ARCH_ARM_INCLUDE_KL_IRQ_H */

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arch/arm/include/limits.h
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/****************************************************************************
* arch/arm/include/limits.h
*
* Copyright (C) 2007-2009, 2012 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
#ifndef __ARCH_ARM_INCLUDE_LIMITS_H
#define __ARCH_ARM_INCLUDE_LIMITS_H
/****************************************************************************
* Included Files
****************************************************************************/
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define CHAR_BIT 8
#define SCHAR_MIN (-SCHAR_MAX - 1)
#define SCHAR_MAX 127
#define UCHAR_MAX 255
/* These could be different on machines where char is unsigned */
#ifdef __CHAR_UNSIGNED__
#define CHAR_MIN 0
#define CHAR_MAX UCHAR_MAX
#else
#define CHAR_MIN SCHAR_MIN
#define CHAR_MAX SCHAR_MAX
#endif
#define SHRT_MIN (-SHRT_MAX - 1)
#define SHRT_MAX 32767
#define USHRT_MAX 65535U
#define INT_MIN (-INT_MAX - 1)
#define INT_MAX 2147483647
#define UINT_MAX 4294967295U
/* These change on 32-bit and 64-bit platforms */
#define LONG_MIN (-LONG_MAX - 1)
#define LONG_MAX 2147483647L
#define ULONG_MAX 4294967295UL
#define LLONG_MIN (-LLONG_MAX - 1)
#define LLONG_MAX 9223372036854775807LL
#define ULLONG_MAX 18446744073709551615ULL
/* A pointer is 4 bytes */
#define PTR_MIN (-PTR_MAX - 1)
#define PTR_MAX 2147483647
#define UPTR_MAX 4294967295U
#endif /* __ARCH_ARM_INCLUDE_LIMITS_H */

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arch/arm/include/lpc11xx/chip.h
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@ -1,141 +0,0 @@
/************************************************************************************
* arch/arm/include/lpc11xx/chip.h
*
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_INCLUDE_LPC11XX_CHIP_H
#define __ARCH_ARM_INCLUDE_LPC11XX_CHIP_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Get customizations for each supported chip */
#if defined(CONFIG_ARCH_CHIP_LPC1115)
# define LPC111x 1 /* LPC111x family */
# define LPC11_FLASH_SIZE (64*1024) /* 64Kb */
# define LPC11_SRAM_SIZE (8*1024) /* 8Kb */
# define LPC11_CPUSRAM_SIZE (8*1024)
# undef LPC11_HAVE_BANK0 /* No AHB SRAM bank 0 */
# undef LPC11_HAVE_BANK1 /* No AHB SRAM bank 1 */
# define LPC11_NETHCONTROLLERS 0 /* No Ethernet controller */
# define LPC11_NUSBHOST 0 /* No USB host controller */
# define LPC11_NUSBOTG 0 /* No USB OTG controller */
# define LPC11_NUSBDEV 1 /* One USB device controller */
# define LPC11_NCAN 1 /* One CAN controller */
# define LPC11_NI2S 0 /* No I2S modules */
# define LPC11_NDAC 0 /* No DAC module */
#else
# error "Unsupported LPC11xx chip"
#endif
/* NVIC priority levels *************************************************************/
/* Each priority field holds a priority value, 0-31. The lower the value, the greater
* the priority of the corresponding interrupt. The processor implements only
* bits[7:3] of each field, bits[2:0] read as zero and ignore writes.
*/
#define NVIC_SYSH_PRIORITY_MIN 0xf8 /* All bits[7:3] set is minimum priority */
#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */
#define NVIC_SYSH_PRIORITY_STEP 0x08 /* Five bits of interrupt priority used */
/* If CONFIG_ARMV7M_USEBASEPRI is selected, then interrupts will be disabled
* by setting the BASEPRI register to NVIC_SYSH_DISABLE_PRIORITY so that most
* interrupts will not have execution priority. SVCall must have execution
* priority in all cases.
*
* In the normal cases, interrupts are not nest-able and all interrupts run
* at an execution priority between NVIC_SYSH_PRIORITY_MIN and
* NVIC_SYSH_PRIORITY_MAX (with NVIC_SYSH_PRIORITY_MAX reserved for SVCall).
*
* If, in addition, CONFIG_ARCH_HIPRI_INTERRUPT is defined, then special
* high priority interrupts are supported. These are not "nested" in the
* normal sense of the word. These high priority interrupts can interrupt
* normal processing but execute outside of OS (although they can "get back
* into the game" via a PendSV interrupt).
*
* In the normal course of things, interrupts must occasionally be disabled
* using the irqsave() inline function to prevent contention in use of
* resources that may be shared between interrupt level and non-interrupt
* level logic. Now the question arises, if CONFIG_ARCH_HIPRI_INTERRUPT,
* do we disable all interrupts (except SVCall), or do we only disable the
* "normal" interrupts. Since the high priority interrupts cannot interact
* with the OS, you may want to permit the high priority interrupts even if
* interrupts are disabled. The setting CONFIG_ARCH_INT_DISABLEALL can be
* used to select either behavior:
*
* ----------------------------+--------------+----------------------------
* CONFIG_ARCH_HIPRI_INTERRUPT | NO | YES
* ----------------------------+--------------+--------------+-------------
* CONFIG_ARCH_INT_DISABLEALL | N/A | YES | NO
* ----------------------------+--------------+--------------+-------------
* | | | SVCall
* | SVCall | SVCall | HIGH
* Disable here and below --------> MAXNORMAL ---> HIGH --------> MAXNORMAL
* | | MAXNORMAL |
* ----------------------------+--------------+--------------+-------------
*/
#if defined(CONFIG_ARCH_HIPRI_INTERRUPT) && defined(CONFIG_ARCH_INT_DISABLEALL)
# define NVIC_SYSH_MAXNORMAL_PRIORITY (NVIC_SYSH_PRIORITY_MAX + 2*NVIC_SYSH_PRIORITY_STEP)
# define NVIC_SYSH_HIGH_PRIORITY (NVIC_SYSH_PRIORITY_MAX + NVIC_SYSH_PRIORITY_STEP)
# define NVIC_SYSH_DISABLE_PRIORITY NVIC_SYSH_HIGH_PRIORITY
# define NVIC_SYSH_SVCALL_PRIORITY NVIC_SYSH_PRIORITY_MAX
#else
# define NVIC_SYSH_MAXNORMAL_PRIORITY (NVIC_SYSH_PRIORITY_MAX + NVIC_SYSH_PRIORITY_STEP)
# define NVIC_SYSH_HIGH_PRIORITY NVIC_SYSH_PRIORITY_MAX
# define NVIC_SYSH_DISABLE_PRIORITY NVIC_SYSH_MAXNORMAL_PRIORITY
# define NVIC_SYSH_SVCALL_PRIORITY NVIC_SYSH_PRIORITY_MAX
#endif
/************************************************************************************
* Public Types
************************************************************************************/
/************************************************************************************
* Public Data
************************************************************************************/
/************************************************************************************
* Public Functions
************************************************************************************/
#endif /* __ARCH_ARM_INCLUDE_LPC11XX_CHIP_H */

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@ -1,144 +0,0 @@
/****************************************************************************
* arch/arm/include/lpc11xxx/irq.h
*
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/* This file should never be included directed but, rather, only indirectly
* through nuttx/irq.h
*/
#ifndef __ARCH_ARM_INCLUDE_LPC11XX_IRQ_H
#define __ARCH_ARM_INCLUDE_LPC11XX_IRQ_H
/****************************************************************************
* Included Files
****************************************************************************/
#ifndef __ASSEMBLY__
# include <stdint.h>
#endif
#include <arch/lpc11xx/chip.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* IRQ numbers. The IRQ number corresponds vector number and hence map
* directly to bits in the NVIC. This does, however, waste several words of
* memory in the IRQ to handle mapping tables.
*/
/* Common Processor Exceptions (vectors 0-15) */
#define LPC11_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG) */
/* Vector 0: Reset stack pointer value */
/* Vector 1: Reset (not handler as an IRQ) */
#define LPC11_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */
#define LPC11_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */
/* Vectors 4-10: Reserved */
#define LPC11_IRQ_SVCALL (11) /* Vector 11: SVC call */
/* Vector 12-13: Reserved */
#define LPC11_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */
#define LPC11_IRQ_SYSTICK (15) /* Vector 15: System tick */
/* External interrupts (vectors >= 16) */
#define LPC11_IRQ_EXTINT (16) /* Vector number of the first external interrupt */
#if defined(CONFIG_ARCH_CHIP_LPC1115)
#define LPC11_IRQ_PIO0_0 (16) /* Vector 16: PIO0_0 */
#define LPC11_IRQ_PIO0_1 (17) /* Vector 17: PIO0_1 */
#define LPC11_IRQ_PIO0_2 (18) /* Vector 18: PIO0_2 */
#define LPC11_IRQ_PIO0_3 (19) /* Vector 19: PIO0_3 */
#define LPC11_IRQ_PIO0_4 (20) /* Vector 20: PIO0_4 */
#define LPC11_IRQ_PIO0_5 (21) /* Vector 21: PIO0_5 */
#define LPC11_IRQ_PIO0_6 (22) /* Vector 22: PIO0_6 */
#define LPC11_IRQ_PIO0_7 (23) /* Vector 23: PIO0_7 */
#define LPC11_IRQ_PIO0_8 (24) /* Vector 24: PIO0_8 */
#define LPC11_IRQ_PIO0_9 (25) /* Vector 25: PIO0_9 */
#define LPC11_IRQ_PIO0_10 (26) /* Vector 26: PIO0_10 */
#define LPC11_IRQ_PIO0_11 (27) /* Vector 27: PIO0_11 */
#define LPC11_IRQ_PIO1_0 (28) /* Vector 28: PIO1_0 */
#define LPC11_IRQ_CCAN (29) /* Vector 29: C_CAN controller for LPC11Cxx */
#define LPC11_IRQ_SSP1 (30) /* Vector 30: SPI1/SSP1 */
#define LPC11_IRQ_I2C (31) /* Vector 31: I2C */
#define LPC11_IRQ_CT16B0 (32) /* Vector 32: Clock/Timer0 16 bits */
#define LPC11_IRQ_CT16B1 (33) /* Vector 33: Clock/Timer1 16 bits */
#define LPC11_IRQ_CT32B0 (34) /* Vector 34: Clock/Timer0 32 bits */
#define LPC11_IRQ_CT32B1 (35) /* Vector 35: Clock/Timer1 32 bits */
#define LPC11_IRQ_SSP0 (36) /* Vector 36: SPI0/SSP0 */
#define LPC11_IRQ_UART (37) /* Vector 37: UART */
/* Vector 38: Reserved */
/* Vector 39: Reserved */
#define LPC11_IRQ_ADC (40) /* Vector 40: Analog/Digital Converter */
#define LPC11_IRQ_WDT (41) /* Vector 41: Watchdog timer */
#define LPC11_IRQ_BOD (42) /* Vector 42: Brownout Detection */
/* Vector 43: Reserved */
#define LPC11_IRQ_PIO3 (44) /* Vector 44: PIO3 */
#define LPC11_IRQ_PIO2 (45) /* Vector 45: PIO2 */
#define LPC11_IRQ_PIO1 (46) /* Vector 46: PIO1 */
#define LPC11_IRQ_PIO0 (47) /* Vector 47: PIO0 */
#endif
#define NR_VECTORS (64) /* 64 vectors */
#define NR_IRQS (48) /* 64 interrupts but 48 IRQ numbers */
/****************************************************************************
* Public Types
****************************************************************************/
#ifndef __ASSEMBLY__
typedef void (*vic_vector_t)(uint32_t *regs);
/****************************************************************************
* Inline functions
****************************************************************************/
/****************************************************************************
* Public Variables
****************************************************************************/
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#ifdef __cplusplus
extern "C"
{
#endif
#ifdef __cplusplus
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_INCLUDE_LPC11XX_IRQ_H */

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arch/arm/include/lpc17xx/chip.h
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@ -1,437 +0,0 @@
/************************************************************************************
* arch/arm/include/lpc17xx/chip.h
*
* Copyright (C) 2010-2011, 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
* with LPC178x support from Rommel Marcelo
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_INCLUDE_LPC17XX_CHIP_H
#define __ARCH_ARM_INCLUDE_LPC17XX_CHIP_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Get customizations for each supported chip */
#if defined(CONFIG_ARCH_CHIP_LPC1751)
# define LPC176x 1 /* LPC175/6 family */
# undef LPC178x /* Not LPC177/8 family */
# define LPC17_FLASH_SIZE (32*1024) /* 32Kb */
# define LPC17_SRAM_SIZE (8*1024) /* 8Kb */
# define LPC17_CPUSRAM_SIZE (8*1024)
# undef LPC17_HAVE_BANK0 /* No AHB SRAM bank 0 */
# undef LPC17_HAVE_BANK1 /* No AHB SRAM bank 1 */
# define LPC17_NETHCONTROLLERS 0 /* No Ethernet controller */
# define LPC17_NUSBHOST 0 /* No USB host controller */
# define LPC17_NUSBOTG 0 /* No USB OTG controller */
# define LPC17_NUSBDEV 1 /* One USB device controller */
# define LPC17_NCAN 1 /* One CAN controller */
# define LPC17_NI2S 0 /* No I2S modules */
# define LPC17_NDAC 0 /* No DAC module */
#elif defined(CONFIG_ARCH_CHIP_LPC1752)
# define LPC176x 1 /* LPC175/6 family */
# undef LPC178x /* Not LPC177/8 family */
# define LPC17_FLASH_SIZE (64*1024) /* 65Kb */
# define LPC17_SRAM_SIZE (16*1024) /* 16Kb */
# define LPC17_CPUSRAM_SIZE (16*1024)
# undef LPC17_HAVE_BANK0 /* No AHB SRAM bank 0 */
# undef LPC17_HAVE_BANK1 /* No AHB SRAM bank 1 */
# define LPC17_NETHCONTROLLERS 0 /* No Ethernet controller */
# define LPC17_NUSBHOST 0 /* No USB host controller */
# define LPC17_NUSBOTG 0 /* No USB OTG controller */
# define LPC17_NUSBDEV 1 /* One USB device controller */
# define LPC17_NCAN 1 /* One CAN controller */
# define LPC17_NI2S 0 /* No I2S modules */
# define LPC17_NDAC 0 /* No DAC module */
#elif defined(CONFIG_ARCH_CHIP_LPC1754)
# define LPC176x 1 /* LPC175/6 family */
# undef LPC178x /* Not LPC177/8 family */
# define LPC17_FLASH_SIZE (128*1024) /* 128Kb */
# define LPC17_SRAM_SIZE (32*1024) /* 32Kb */
# define LPC17_CPUSRAM_SIZE (16*1024)
# define LPC17_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */
# undef LPC17_HAVE_BANK1 /* No AHB SRAM bank 1 */
# define LPC17_NETHCONTROLLERS 0 /* No Ethernet controller */
# define LPC17_NUSBHOST 1 /* One USB host controller */
# define LPC17_NUSBOTG 1 /* One USB OTG controller */
# define LPC17_NUSBDEV 1 /* One USB device controller */
# define LPC17_NCAN 1 /* One CAN controller */
# define LPC17_NI2S 0 /* No I2S modules */
# define LPC17_NDAC 1 /* One DAC module */
#elif defined(CONFIG_ARCH_CHIP_LPC1756)
# define LPC176x 1 /* LPC175/6 family */
# undef LPC178x /* Not LPC177/8 family */
# define LPC17_FLASH_SIZE (256*1024) /* 256Kb */
# define LPC17_SRAM_SIZE (32*1024) /* 32Kb */
# define LPC17_CPUSRAM_SIZE (16*1024)
# define LPC17_HAVE_BANK0 1 /* No AHB SRAM bank 0 */
# undef LPC17_HAVE_BANK1 /* No AHB SRAM bank 1 */
# define LPC17_NETHCONTROLLERS 0 /* No Ethernet controller */
# define LPC17_NUSBHOST 1 /* One USB host controller */
# define LPC17_NUSBOTG 1 /* One USB OTG controller */
# define LPC17_NUSBDEV 1 /* One USB device controller */
# define LPC17_NCAN 2 /* Two CAN controllers */
# define LPC17_NI2S 1 /* One I2S module */
# define LPC17_NDAC 1 /* One DAC module */
#elif defined(CONFIG_ARCH_CHIP_LPC1758)
# define LPC176x 1 /* LPC175/6 family */
# undef LPC178x /* Not LPC177/8 family */
# define LPC17_FLASH_SIZE (512*1024) /* 512Kb */
# define LPC17_SRAM_SIZE (64*1024) /* 64Kb */
# define LPC17_CPUSRAM_SIZE (32*1024)
# define LPC17_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */
# define LPC17_HAVE_BANK1 1 /* Have AHB SRAM bank 1 */
# define LPC17_NETHCONTROLLERS 1 /* One Ethernet controller */
# define LPC17_NUSBHOST 1 /* One USB host controller */
# define LPC17_NUSBOTG 1 /* One USB OTG controller */
# define LPC17_NUSBDEV 1 /* One USB device controller */
# define LPC17_NCAN 2 /* Two CAN controllers */
# define LPC17_NI2S 1 /* One I2S module */
# define LPC17_NDAC 1 /* One DAC module */
#elif defined(CONFIG_ARCH_CHIP_LPC1759)
# define LPC176x 1 /* LPC175/6 family */
# undef LPC178x /* Not LPC177/8 family */
# define LPC17_FLASH_SIZE (512*1024) /* 512Kb */
# define LPC17_SRAM_SIZE (64*1024) /* 64Kb */
# define LPC17_CPUSRAM_SIZE (32*1024)
# define LPC17_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */
# define LPC17_HAVE_BANK1 1 /* Have AHB SRAM bank 1 */
# define LPC17_NETHCONTROLLERS 0 /* No Ethernet controller */
# define LPC17_NUSBHOST 1 /* One USB host controller */
# define LPC17_NUSBOTG 1 /* One USB OTG controller */
# define LPC17_NUSBDEV 1 /* One USB device controller */
# define LPC17_NCAN 2 /* Two CAN controllers */
# define LPC17_NI2S 1 /* One I2S module */
# define LPC17_NDAC 1 /* One DAC module */
#elif defined(CONFIG_ARCH_CHIP_LPC1764)
# define LPC176x 1 /* LPC175/6 family */
# undef LPC178x /* Not LPC177/8 family */
# define LPC17_FLASH_SIZE (128*1024) /* 128Kb */
# define LPC17_SRAM_SIZE (32*1024) /* 32Kb */
# define LPC17_CPUSRAM_SIZE (16*1024)
# define LPC17_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */
# undef LPC17_HAVE_BANK1 /* No AHB SRAM bank 1 */
# define LPC17_NETHCONTROLLERS 1 /* One Ethernet controller */
# define LPC17_NUSBHOST 0 /* No USB host controller */
# define LPC17_NUSBOTG 0 /* No USB OTG controller */
# define LPC17_NUSBDEV 1 /* One USB device controller */
# define LPC17_NCAN 2 /* Two CAN controllers */
# define LPC17_NI2S 0 /* No I2S modules */
# define LPC17_NDAC 0 /* No DAC module */
#elif defined(CONFIG_ARCH_CHIP_LPC1765)
# define LPC176x 1 /* LPC175/6 family */
# undef LPC178x /* Not LPC177/8 family */
# define LPC17_FLASH_SIZE (256*1024) /* 256Kb */
# define LPC17_SRAM_SIZE (64*1024) /* 64Kb */
# define LPC17_CPUSRAM_SIZE (32*1024)
# define LPC17_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */
# define LPC17_HAVE_BANK1 1 /* Have AHB SRAM bank 1 */
# define LPC17_NETHCONTROLLERS 0 /* No Ethernet controller */
# define LPC17_NUSBHOST 1 /* One USB host controller */
# define LPC17_NUSBOTG 1 /* One USB OTG controller */
# define LPC17_NUSBDEV 1 /* One USB device controller */
# define LPC17_NCAN 2 /* Two CAN controllers */
# define LPC17_NI2S 1 /* One I2S module */
# define LPC17_NDAC 1 /* One DAC module */
#elif defined(CONFIG_ARCH_CHIP_LPC1766)
# define LPC176x 1 /* LPC175/6 family */
# undef LPC178x /* Not LPC177/8 family */
# define LPC17_FLASH_SIZE (256*1024) /* 256Kb */
# define LPC17_SRAM_SIZE (64*1024) /* 64Kb */
# define LPC17_CPUSRAM_SIZE (32*1024)
# define LPC17_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */
# define LPC17_HAVE_BANK1 1 /* Have AHB SRAM bank 1 */
# define LPC17_NETHCONTROLLERS 1 /* One Ethernet controller */
# define LPC17_NUSBHOST 1 /* One USB host controller */
# define LPC17_NUSBOTG 1 /* One USB OTG controller */
# define LPC17_NUSBDEV 1 /* One USB device controller */
# define LPC17_NCAN 2 /* Two CAN controllers */
# define LPC17_NI2S 1 /* One I2S module */
# define LPC17_NDAC 1 /* One DAC module */
#elif defined(CONFIG_ARCH_CHIP_LPC1767)
# define LPC176x 1 /* LPC175/6 family */
# undef LPC178x /* Not LPC177/8 family */
# define LPC17_FLASH_SIZE (512*1024) /* 512Kb */
# define LPC17_SRAM_SIZE (64*1024) /* 64Kb */
# define LPC17_CPUSRAM_SIZE (32*1024)
# define LPC17_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */
# define LPC17_HAVE_BANK1 1 /* Have AHB SRAM bank 1 */
# define LPC17_NETHCONTROLLERS 1 /* One Ethernet controller */
# define LPC17_NUSBHOST 0 /* No USB host controller */
# define LPC17_NUSBOTG 0 /* No USB OTG controller */
# define LPC17_NUSBDEV 0 /* No USB device controller */
# define LPC17_NCAN 0 /* No CAN controllers */
# define LPC17_NI2S 1 /* One I2S module */
# define LPC17_NDAC 1 /* One DAC module */
#elif defined(CONFIG_ARCH_CHIP_LPC1769) || defined(CONFIG_ARCH_CHIP_LPC1768)
# define LPC176x 1 /* LPC175/6 family */
# undef LPC178x /* Not LPC177/8 family */
# define LPC17_FLASH_SIZE (512*1024) /* 512Kb */
# define LPC17_SRAM_SIZE (64*1024) /* 64Kb */
# define LPC17_CPUSRAM_SIZE (32*1024)
# define LPC17_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */
# define LPC17_HAVE_BANK1 1 /* Have AHB SRAM bank 1 */
# define LPC17_NETHCONTROLLERS 1 /* One Ethernet controller */
# define LPC17_NUSBHOST 1 /* One USB host controller */
# define LPC17_NUSBOTG 1 /* One USB OTG controller */
# define LPC17_NUSBDEV 1 /* One USB device controller */
# define LPC17_NCAN 2 /* Two CAN controllers */
# define LPC17_NI2S 1 /* One I2S module */
# define LPC17_NDAC 1 /* One DAC module */
#elif defined(CONFIG_ARCH_CHIP_LPC1773)
# undef LPC176x /* Not LPC175/6 family */
# define LPC178x 1 /* LPC177/8 family */
# define LPC17_FLASH_SIZE (128*1024) /* 128Kb */
# define LPC17_SRAM_SIZE (40*1024) /* 40Kb */
# define LPC17_CPUSRAM_SIZE (32*1024)
# define LPC17_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0 */
# undef LPC17_HAVE_BANK1 /* No Peripheral SRAM bank 1 */
# define LPC17_NETHCONTROLLERS 1 /* One Ethernet controller */
# undef LPC17_NUSBHOST /* No USB host controller */
# undef LPC17_NUSBOTG /* No USB OTG controller */
# define LPC17_NUSBDEV 1 /* One USB device controller */
# define LPC17_HAVE_SPIFI 1 /* Have SPIFI interface */
# undef LPC17_HAVE_LCD /* No LCD controller */
# undef LPC17_HAVE_QEI /* No QEI interface */
# undef LPC17_HAVE_SD /* No SD controller */
#elif defined(CONFIG_ARCH_CHIP_LPC1774)
# undef LPC176x /* Not LPC175/6 family */
# define LPC178x 1 /* LPC177/8 family */
# define LPC17_FLASH_SIZE (128*1024) /* 128Kb */
# define LPC17_SRAM_SIZE (40*1024) /* 40Kb */
# define LPC17_CPUSRAM_SIZE (32*1024)
# define LPC17_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0*/
# undef LPC17_HAVE_BANK1 /* Have Peripheral SRAM bank 1 */
# define LPC17_NETHCONTROLLERS 1 /* One Ethernet controller */
# undef LPC17_NUSBHOST /* One USB host controller */
# undef LPC17_NUSBOTG /* One USB OTG controller */
# define LPC17_NUSBDEV 1 /* One USB device controller */
# undef LPC17_HAVE_SPIFI /* Have SPIFI interface */
# undef LPC17_HAVE_LCD /* One LCD controller */
# define LPC17_HAVE_QEI 1 /* One QEI interface */
# define LPC17_HAVE_SD 1 /* One SD controller */
#elif defined(CONFIG_ARCH_CHIP_LPC1776)
# undef LPC176x /* Not LPC175/6 family */
# define LPC178x 1 /* LPC177/8 family */
# define LPC17_FLASH_SIZE (256*1024) /* 256Kb */
# define LPC17_SRAM_SIZE (80*1024) /* 80Kb */
# define LPC17_CPUSRAM_SIZE (64*1024)
# define LPC17_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0 */
# undef LPC17_HAVE_BANK1 /* Have Peripheral SRAM bank 1 */
# define LPC17_NETHCONTROLLERS 1 /* One Ethernet controller */
# define LPC17_NUSBHOST 1 /* One USB host controller */
# define LPC17_NUSBOTG 1 /* One USB OTG controller */
# define LPC17_NUSBDEV 1 /* One USB device controller */
# undef LPC17_HAVE_SPIFI /* Have SPIFI interface */
# undef LPC17_HAVE_LCD /* One LCD controller */
# define LPC17_HAVE_QEI 1 /* One QEI interface */
# define LPC17_HAVE_SD 1 /* One SD controller */
#elif defined(CONFIG_ARCH_CHIP_LPC1777)
# undef LPC176x /* Not LPC175/6 family */
# define LPC178x 1 /* LPC177/8 family */
# define LPC17_FLASH_SIZE (512*1024) /* 512Kb */
# define LPC17_SRAM_SIZE (96*1024) /* 96Kb */
# define LPC17_CPUSRAM_SIZE (64*1024)
# define LPC17_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0 */
# define LPC17_HAVE_BANK1 1 /* Have Peripheral SRAM bank 1 */
# undef LPC17_NETHCONTROLLERS /* One Ethernet controller */
# define LPC17_NUSBHOST 1 /* One USB host controller */
# define LPC17_NUSBOTG 1 /* One USB OTG controller */
# define LPC17_NUSBDEV 1 /* One USB device controller */
# undef LPC17_HAVE_SPIFI /* Have SPIFI interface */
# undef LPC17_HAVE_LCD /* One LCD controller */
# define LPC17_HAVE_QEI 1 /* One QEI interface */
# define LPC17_HAVE_SD 1 /* One SD controller */
#elif defined(CONFIG_ARCH_CHIP_LPC1778)
# undef LPC176x /* Not LPC175/6 family */
# define LPC178x 1 /* LPC177/8 family */
# define LPC17_FLASH_SIZE (512*1024) /* 512Kb */
# define LPC17_SRAM_SIZE (96*1024) /* 64Kb */
# define LPC17_CPUSRAM_SIZE (64*1024)
# define LPC17_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0 */
# define LPC17_HAVE_BANK1 1 /* Have Peripheral SRAM bank 1 */
# define LPC17_NETHCONTROLLERS 1 /* One Ethernet controller */
# define LPC17_NUSBHOST 1 /* One USB host controller */
# define LPC17_NUSBOTG 1 /* One USB OTG controller */
# define LPC17_NUSBDEV 1 /* One USB device controller */
# undef LPC17_HAVE_SPIFI /* Have SPIFI interface */
# undef LPC17_HAVE_LCD /* One LCD controller */
# define LPC17_HAVE_QEI 1 /* One QEI interface */
# define LPC17_HAVE_SD 1 /* One SD controller */
#elif defined(CONFIG_ARCH_CHIP_LPC1785)
# undef LPC176x /* Not LPC175/6 family */
# define LPC178x 1 /* LPC177/8 family */
# define LPC17_FLASH_SIZE (256*1024) /* 256Kb */
# define LPC17_SRAM_SIZE (80*1024) /* 80Kb */
# define LPC17_CPUSRAM_SIZE (64*1024)
# define LPC17_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0 */
# undef LPC17_HAVE_BANK1 /* Have Peripheral SRAM bank 1 */
# undef LPC17_NETHCONTROLLERS /* One Ethernet controller */
# define LPC17_NUSBHOST 1 /* One USB host controller */
# define LPC17_NUSBOTG 1 /* One USB OTG controller */
# define LPC17_NUSBDEV 1 /* One USB device controller */
# undef LPC17_HAVE_SPIFI /* Have SPIFI interface */
# define LPC17_HAVE_LCD 1 /* One LCD controller */
# undef LPC17_HAVE_QEI /* One QEI interface */
# define LPC17_HAVE_SD 1 /* One SD controller */
#elif defined(CONFIG_ARCH_CHIP_LPC1786)
# undef LPC176x /* Not LPC175/6 family */
# define LPC178x 1 /* LPC177/8 family */
# define LPC17_FLASH_SIZE (256*1024) /* 256Kb */
# define LPC17_SRAM_SIZE (80*1024) /* 80Kb */
# define LPC17_CPUSRAM_SIZE (64*1024)
# define LPC17_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0 */
# undef LPC17_HAVE_BANK1 /* Have Peripheral SRAM bank 1 */
# define LPC17_NETHCONTROLLERS 1 /* One Ethernet controller */
# define LPC17_NUSBHOST 1 /* One USB host controller */
# define LPC17_NUSBOTG 1 /* One USB OTG controller */
# define LPC17_NUSBDEV 1 /* One USB device controller */
# undef LPC17_HAVE_SPIFI /* Have SPIFI interface */
# define LPC17_HAVE_LCD 1 /* One LCD controller */
# define LPC17_HAVE_QEI 1 /* One QEI interface */
# define LPC17_HAVE_SD 1 /* One SD controller */
#elif defined(CONFIG_ARCH_CHIP_LPC1787)
# undef LPC176x /* Not LPC175/6 family */
# define LPC178x 1 /* LPC177/8 family */
# define LPC17_FLASH_SIZE (512*1024) /* 512Kb */
# define LPC17_SRAM_SIZE (96*1024) /* 96Kb */
# define LPC17_CPUSRAM_SIZE (64*1024)
# define LPC17_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0 */
# define LPC17_HAVE_BANK1 1 /* Have Peripheral SRAM bank 1 */
# undef LPC17_NETHCONTROLLERS /* One Ethernet controller */
# define LPC17_NUSBHOST 1 /* One USB host controller */
# define LPC17_NUSBOTG 1 /* One USB OTG controller */
# define LPC17_NUSBDEV 1 /* One USB device controller */
# undef LPC17_HAVE_SPIFI /* Have SPIFI interface */
# define LPC17_HAVE_LCD 1 /* One LCD controller */
# define LPC17_HAVE_QEI 1 /* One QEI interface */
# define LPC17_HAVE_SD 1 /* One SD controller */
#elif defined(CONFIG_ARCH_CHIP_LPC1788)
# undef LPC176x /* Not LPC175/6 family */
# define LPC178x 1 /* LPC177/8 family */
# define LPC17_FLASH_SIZE (512*1024) /* 512Kb */
# define LPC17_SRAM_SIZE (96*1024) /* 96Kb */
# define LPC17_CPUSRAM_SIZE (64*1024)
# define LPC17_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0 */
# define LPC17_HAVE_BANK1 1 /* Have Peripheral SRAM bank 1 */
# define LPC17_NETHCONTROLLERS 1 /* One Ethernet controller */
# define LPC17_NUSBHOST 1 /* One USB host controller */
# define LPC17_NUSBOTG 1 /* One USB OTG controller */
# define LPC17_NUSBDEV 1 /* One USB device controller */
# undef LPC17_HAVE_SPIFI /* Have SPIFI interface */
# define LPC17_HAVE_LCD 1 /* One LCD controller */
# define LPC17_HAVE_QEI 1 /* One QEI interface */
# define LPC17_HAVE_SD 1 /* One SD controller */
#else
# error "Unsupported LPC17xx chip"
#endif
/* NVIC priority levels *************************************************************/
/* Each priority field holds a priority value, 0-31. The lower the value, the greater
* the priority of the corresponding interrupt. The processor implements only
* bits[7:3] of each field, bits[2:0] read as zero and ignore writes.
*/
#define NVIC_SYSH_PRIORITY_MIN 0xf8 /* All bits[7:3] set is minimum priority */
#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */
#define NVIC_SYSH_PRIORITY_STEP 0x08 /* Five bits of interrupt priority used */
/* If CONFIG_ARMV7M_USEBASEPRI is selected, then interrupts will be disabled
* by setting the BASEPRI register to NVIC_SYSH_DISABLE_PRIORITY so that most
* interrupts will not have execution priority. SVCall must have execution
* priority in all cases.
*
* In the normal cases, interrupts are not nest-able and all interrupts run
* at an execution priority between NVIC_SYSH_PRIORITY_MIN and
* NVIC_SYSH_PRIORITY_MAX (with NVIC_SYSH_PRIORITY_MAX reserved for SVCall).
*
* If, in addition, CONFIG_ARCH_HIPRI_INTERRUPT is defined, then special
* high priority interrupts are supported. These are not "nested" in the
* normal sense of the word. These high priority interrupts can interrupt
* normal processing but execute outside of OS (although they can "get back
* into the game" via a PendSV interrupt).
*
* In the normal course of things, interrupts must occasionally be disabled
* using the irqsave() inline function to prevent contention in use of
* resources that may be shared between interrupt level and non-interrupt
* level logic. Now the question arises, if CONFIG_ARCH_HIPRI_INTERRUPT,
* do we disable all interrupts (except SVCall), or do we only disable the
* "normal" interrupts. Since the high priority interrupts cannot interact
* with the OS, you may want to permit the high priority interrupts even if
* interrupts are disabled. The setting CONFIG_ARCH_INT_DISABLEALL can be
* used to select either behavior:
*
* ----------------------------+--------------+----------------------------
* CONFIG_ARCH_HIPRI_INTERRUPT | NO | YES
* ----------------------------+--------------+--------------+-------------
* CONFIG_ARCH_INT_DISABLEALL | N/A | YES | NO
* ----------------------------+--------------+--------------+-------------
* | | | SVCall
* | SVCall | SVCall | HIGH
* Disable here and below --------> MAXNORMAL ---> HIGH --------> MAXNORMAL
* | | MAXNORMAL |
* ----------------------------+--------------+--------------+-------------
*/
#if defined(CONFIG_ARCH_HIPRI_INTERRUPT) && defined(CONFIG_ARCH_INT_DISABLEALL)
# define NVIC_SYSH_MAXNORMAL_PRIORITY (NVIC_SYSH_PRIORITY_MAX + 2*NVIC_SYSH_PRIORITY_STEP)
# define NVIC_SYSH_HIGH_PRIORITY (NVIC_SYSH_PRIORITY_MAX + NVIC_SYSH_PRIORITY_STEP)
# define NVIC_SYSH_DISABLE_PRIORITY NVIC_SYSH_HIGH_PRIORITY
# define NVIC_SYSH_SVCALL_PRIORITY NVIC_SYSH_PRIORITY_MAX
#else
# define NVIC_SYSH_MAXNORMAL_PRIORITY (NVIC_SYSH_PRIORITY_MAX + NVIC_SYSH_PRIORITY_STEP)
# define NVIC_SYSH_HIGH_PRIORITY NVIC_SYSH_PRIORITY_MAX
# define NVIC_SYSH_DISABLE_PRIORITY NVIC_SYSH_MAXNORMAL_PRIORITY
# define NVIC_SYSH_SVCALL_PRIORITY NVIC_SYSH_PRIORITY_MAX
#endif
/************************************************************************************
* Public Types
************************************************************************************/
/************************************************************************************
* Public Data
************************************************************************************/
/************************************************************************************
* Public Functions
************************************************************************************/
#endif /* __ARCH_ARM_INCLUDE_LPC17XX_CHIP_H */

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@ -1,119 +0,0 @@
/****************************************************************************
* arch/arm/include/lpc17xxx/irq.h
*
* Copyright (C) 2010-2011, 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/* This file should never be included directed but, rather, only indirectly
* through nuttx/irq.h
*/
#ifndef __ARCH_ARM_INCLUDE_LPC17XX_IRQ_H
#define __ARCH_ARM_INCLUDE_LPC17XX_IRQ_H
/****************************************************************************
* Included Files
****************************************************************************/
#ifndef __ASSEMBLY__
# include <stdint.h>
#endif
#include <arch/lpc17xx/chip.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* IRQ numbers. The IRQ number corresponds vector number and hence map
* directly to bits in the NVIC. This does, however, waste several words of
* memory in the IRQ to handle mapping tables.
*/
/* Common Processor Exceptions (vectors 0-15) */
#define LPC17_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG) */
/* Vector 0: Reset stack pointer value */
/* Vector 1: Reset (not handler as an IRQ) */
#define LPC17_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */
#define LPC17_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */
#define LPC17_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */
#define LPC17_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */
#define LPC17_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */
#define LPC17_IRQ_SVCALL (11) /* Vector 11: SVC call */
#define LPC17_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */
/* Vector 13: Reserved */
#define LPC17_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */
#define LPC17_IRQ_SYSTICK (15) /* Vector 15: System tick */
/* External interrupts (vectors >= 16) */
#define LPC17_IRQ_EXTINT (16) /* Vector number of the first external interrupt */
/* Family Specfic Interrupts */
#if defined(LPC176x) /* LPC175/6 family */
# include <arch/lpc17xx/lpc176x_irq.h>
#elif defined(LPC178x) /* LPC177/8 family */
# include <arch/lpc17xx/lpc178x_irq.h>
#else
# error "Unknown LPC17xx family"
#endif
/****************************************************************************
* Public Types
****************************************************************************/
#ifndef __ASSEMBLY__
typedef void (*vic_vector_t)(uint32_t *regs);
/****************************************************************************
* Inline functions
****************************************************************************/
/****************************************************************************
* Public Variables
****************************************************************************/
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#ifdef __cplusplus
extern "C"
{
#endif
#ifdef __cplusplus
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_INCLUDE_LPC17XX_IRQ_H */

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@ -1,246 +0,0 @@
/****************************************************************************
* arch/lpc17xx/lpc176x_irq.h
*
* Copyright (C) 2010-2011, 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/* This file should never be included directed but, rather, only indirectly
* through nuttx/irq.h
*/
#ifndef __ARCH_ARM_INCLUDE_LPC17XX_LPC176X_IRQ_H
#define __ARCH_ARM_INCLUDE_LPC17XX_LPC176X_IRQ_H
/****************************************************************************
* Included Files
****************************************************************************/
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* IRQ numbers. The IRQ number corresponds vector number and hence map
* directly to bits in the NVIC. This does, however, waste several words of
* memory in the IRQ to handle mapping tables.
*/
/* External interrupts (vectors >= 16) */
#define LPC17_IRQ_WDT (LPC17_IRQ_EXTINT+0) /* WDT Watchdog Interrupt (WDINT) */
#define LPC17_IRQ_TMR0 (LPC17_IRQ_EXTINT+1) /* Timer 0 Match 0 - 1 (MR0, MR1)
* Capture 0 - 1 (CR0, CR1) */
#define LPC17_IRQ_TMR1 (LPC17_IRQ_EXTINT+2) /* Timer 1 Match 0 - 2 (MR0, MR1, MR2)
* Capture 0 - 1 (CR0, CR1) */
#define LPC17_IRQ_TMR2 (LPC17_IRQ_EXTINT+3) /* Timer 2 Match 0-3
* Capture 0-1 */
#define LPC17_IRQ_TMR3 (LPC17_IRQ_EXTINT+4) /* Timer 3 Match 0-3
* Capture 0-1 */
#define LPC17_IRQ_UART0 (LPC17_IRQ_EXTINT+5) /* UART 0 Rx Line Status (RLS)
* Transmit Holding Register Empty (THRE)
* Rx Data Available (RDA)
* Character Time-out Indicator (CTI)
* End of Auto-Baud (ABEO)
* Auto-Baud Time-Out (ABTO) */
#define LPC17_IRQ_UART1 (LPC17_IRQ_EXTINT+6) /* UART 1 Rx Line Status (RLS)
* Transmit Holding Register Empty (THRE)
* Rx Data Available (RDA)
* Character Time-out Indicator (CTI)
* Modem Control Change
* End of Auto-Baud (ABEO)
* Auto-Baud Time-Out (ABTO) */
#define LPC17_IRQ_UART2 (LPC17_IRQ_EXTINT+7) /* UART 2 Rx Line Status (RLS)
* Transmit Holding Register Empty (THRE)
* Rx Data Available (RDA)
* Character Time-out Indicator (CTI)
* End of Auto-Baud (ABEO)
* Auto-Baud Time-Out (ABTO) */
#define LPC17_IRQ_UART3 (LPC17_IRQ_EXTINT+8) /* UART 3 Rx Line Status (RLS)
* Transmit Holding Register Empty (THRE)
* Rx Data Available (RDA)
* Character Time-out Indicator (CTI)
* End of Auto-Baud (ABEO)
* Auto-Baud Time-Out (ABTO) */
#define LPC17_IRQ_PWM1 (LPC17_IRQ_EXTINT+9) /* PWM1 Match 0 - 6 of PWM1
* Capture 0-1 of PWM1 */
#define LPC17_IRQ_I2C0 (LPC17_IRQ_EXTINT+10) /* I2C0 SI (state change) */
#define LPC17_IRQ_I2C1 (LPC17_IRQ_EXTINT+11) /* I2C1 SI (state change) */
#define LPC17_IRQ_I2C2 (LPC17_IRQ_EXTINT+12) /* I2C2 SI (state change) */
#define LPC17_IRQ_SPIF (LPC17_IRQ_EXTINT+13) /* SPI SPI Interrupt Flag (SPIF)
* Mode Fault (MODF) */
#define LPC17_IRQ_SSP0 (LPC17_IRQ_EXTINT+14) /* SSP0 Tx FIFO half empty of SSP0
* Rx FIFO half full of SSP0
* Rx Timeout of SSP0
* Rx Overrun of SSP0 */
#define LPC17_IRQ_SSP1 (LPC17_IRQ_EXTINT+15) /* SSP 1 Tx FIFO half empty
* Rx FIFO half full
* Rx Timeout
* Rx Overrun */
#define LPC17_IRQ_PLL0 (LPC17_IRQ_EXTINT+16) /* PLL0 (Main PLL) PLL0 Lock (PLOCK0) */
#define LPC17_IRQ_RTC (LPC17_IRQ_EXTINT+17) /* RTC Counter Increment (RTCCIF)
* Alarm (RTCALF) */
#define LPC17_IRQ_EINT0 (LPC17_IRQ_EXTINT+18) /* External Interrupt 0 (EINT0) */
#define LPC17_IRQ_EINT1 (LPC17_IRQ_EXTINT+19) /* External Interrupt 1 (EINT1) */
#define LPC17_IRQ_EINT2 (LPC17_IRQ_EXTINT+20) /* External Interrupt 2 (EINT2) */
#define LPC17_IRQ_EINT3 (LPC17_IRQ_EXTINT+21) /* External Interrupt 3 (EINT3)
* Note: EINT3 channel is shared with GPIO interrupts */
#define LPC17_IRQ_ADC (LPC17_IRQ_EXTINT+22) /* ADC A/D Converter end of conversion */
#define LPC17_IRQ_BOD (LPC17_IRQ_EXTINT+23) /* BOD Brown Out detect */
#define LPC17_IRQ_USB (LPC17_IRQ_EXTINT+24) /* USB USB_INT_REQ_LP, USB_INT_REQ_HP,
* USB_INT_REQ_DMA */
#define LPC17_IRQ_CAN (LPC17_IRQ_EXTINT+25) /* CAN CAN Common, CAN 0 Tx, CAN 0 Rx,
* CAN 1 Tx, CAN 1 Rx */
#define LPC17_IRQ_GPDMA (LPC17_IRQ_EXTINT+26) /* GPDMA IntStatus of DMA channel 0,
* IntStatus of DMA channel 1 */
#define LPC17_IRQ_I2S (LPC17_IRQ_EXTINT+27) /* I2S irq, dmareq1, dmareq2 */
#define LPC17_IRQ_ETH (LPC17_IRQ_EXTINT+28) /* Ethernet WakeupInt, SoftInt, TxDoneInt,
* TxFinishedInt, TxErrorInt,* TxUnderrunInt,
* RxDoneInt, RxFinishedInt, RxErrorInt,
* RxOverrunInt */
#define LPC17_IRQ_RITINT (LPC17_IRQ_EXTINT+29) /* Repetitive Interrupt Timer (RITINT) */
#define LPC17_IRQ_MCPWM (LPC17_IRQ_EXTINT+30) /* Motor Control PWM IPER[2:0], IPW[2:0],
* ICAP[2:0], FES */
#define LPC17_IRQ_QEI (LPC17_IRQ_EXTINT+31) /* Quadrature Encoder INX_Int, TIM_Int, VELC_Int,
* DIR_Int, ERR_Int, ENCLK_Int, POS0_Int, POS1_Int
* POS2_Int, REV_Int, POS0REV_Int, OS1REV_Int,
* POS2REV_Int */
#define LPC17_IRQ_PLL1 (LPC17_IRQ_EXTINT+32) /* PLL1 (USB PLL) PLL1 Lock (PLOCK1) */
#define LPC17_IRQ_USBACT (LPC17_IRQ_EXTINT+33) /* USB Activity Interrupt USB_NEED_CLK */
#define LPC17_IRQ_CANACT (LPC17_IRQ_EXTINT+34) /* CAN Activity Interrupt CAN1WAKE, CAN2WAKE */
#define LPC17_IRQ_NEXTINT (35)
#define LPC17_IRQ_NIRQS (LPC17_IRQ_EXTINT+LPC17_IRQ_NEXTINT)
/* GPIO interrupts. The LPC17xx supports several interrupts on ports 0 and
* 2 (only). We go through some special efforts to keep the number of IRQs
* to a minimum in this sparse interrupt case.
*
* 28 interrupts on Port 0: p0.0 - p0.11, p0.15-p0.30
* 14 interrupts on Port 2: p2.0 - p2.13
* --
* 42
*/
#ifdef CONFIG_GPIO_IRQ
# define LPC17_VALID_GPIOINT0 (0x7fff8ffful) /* GPIO port 0 interrupt set */
# define LPC17_VALID_GPIOINT2 (0x00003ffful) /* GPIO port 2 interrupt set */
/* Set 1: 12 interrupts p0.0-p0.11 */
# define LPC17_VALID_GPIOINT0L (0x00000ffful)
# define LPC17_VALID_SHIFT0L (0)
# define LPC17_VALID_FIRST0L (LPC17_IRQ_EXTINT+LPC17_IRQ_NEXTINT)
# define LPC17_IRQ_P0p0 (LPC17_VALID_FIRST0L+0)
# define LPC17_IRQ_P0p1 (LPC17_VALID_FIRST0L+1)
# define LPC17_IRQ_P0p2 (LPC17_VALID_FIRST0L+2)
# define LPC17_IRQ_P0p3 (LPC17_VALID_FIRST0L+3)
# define LPC17_IRQ_P0p4 (LPC17_VALID_FIRST0L+4)
# define LPC17_IRQ_P0p5 (LPC17_VALID_FIRST0L+5)
# define LPC17_IRQ_P0p6 (LPC17_VALID_FIRST0L+6)
# define LPC17_IRQ_P0p7 (LPC17_VALID_FIRST0L+7)
# define LPC17_IRQ_P0p8 (LPC17_VALID_FIRST0L+8)
# define LPC17_IRQ_P0p9 (LPC17_VALID_FIRST0L+9)
# define LPC17_IRQ_P0p10 (LPC17_VALID_FIRST0L+10)
# define LPC17_IRQ_P0p11 (LPC17_VALID_FIRST0L+11)
# define LPC17_VALID_NIRQS0L (12)
/* Set 2: 16 interrupts p0.15-p0.30 */
# define LPC17_VALID_GPIOINT0H (0x7fff8000ull)
# define LPC17_VALID_SHIFT0H (15)
# define LPC17_VALID_FIRST0H (LPC17_VALID_FIRST0L+LPC17_VALID_NIRQS0L)
# define LPC17_IRQ_P0p15 (LPC17_VALID_FIRST0H+0)
# define LPC17_IRQ_P0p16 (LPC17_VALID_FIRST0H+1)
# define LPC17_IRQ_P0p17 (LPC17_VALID_FIRST0H+2)
# define LPC17_IRQ_P0p18 (LPC17_VALID_FIRST0H+3)
# define LPC17_IRQ_P0p19 (LPC17_VALID_FIRST0H+4)
# define LPC17_IRQ_P0p20 (LPC17_VALID_FIRST0H+5)
# define LPC17_IRQ_P0p21 (LPC17_VALID_FIRST0H+6)
# define LPC17_IRQ_P0p22 (LPC17_VALID_FIRST0H+7)
# define LPC17_IRQ_P0p23 (LPC17_VALID_FIRST0H+8)
# define LPC17_IRQ_P0p24 (LPC17_VALID_FIRST0H+9)
# define LPC17_IRQ_P0p25 (LPC17_VALID_FIRST0H+10)
# define LPC17_IRQ_P0p26 (LPC17_VALID_FIRST0H+11)
# define LPC17_IRQ_P0p27 (LPC17_VALID_FIRST0H+12)
# define LPC17_IRQ_P0p28 (LPC17_VALID_FIRST0H+13)
# define LPC17_IRQ_P0p29 (LPC17_VALID_FIRST0H+14)
# define LPC17_IRQ_P0p30 (LPC17_VALID_FIRST0H+15)
# define LPC17_VALID_NIRQS0H (16)
/* Set 3: 14 interrupts p2.0-p2.13 */
# define LPC17_VALID_GPIOINT2 (0x00003ffful)
# define LPC17_VALID_SHIFT2 (0)
# define LPC17_VALID_FIRST2 (LPC17_VALID_FIRST0H+LPC17_VALID_NIRQS0H)
# define LPC17_IRQ_P2p0 (LPC17_VALID_FIRST2+0)
# define LPC17_IRQ_P2p1 (LPC17_VALID_FIRST2+1)
# define LPC17_IRQ_P2p2 (LPC17_VALID_FIRST2+2)
# define LPC17_IRQ_P2p3 (LPC17_VALID_FIRST2+3)
# define LPC17_IRQ_P2p4 (LPC17_VALID_FIRST2+4)
# define LPC17_IRQ_P2p5 (LPC17_VALID_FIRST2+5)
# define LPC17_IRQ_P2p6 (LPC17_VALID_FIRST2+6)
# define LPC17_IRQ_P2p7 (LPC17_VALID_FIRST2+7)
# define LPC17_IRQ_P2p8 (LPC17_VALID_FIRST2+8)
# define LPC17_IRQ_P2p9 (LPC17_VALID_FIRST2+9)
# define LPC17_IRQ_P2p10 (LPC17_VALID_FIRST2+10)
# define LPC17_IRQ_P2p11 (LPC17_VALID_FIRST2+11)
# define LPC17_IRQ_P2p12 (LPC17_VALID_FIRST2+12)
# define LPC17_IRQ_P2p13 (LPC17_VALID_FIRST2+13)
# define LPC17_VALID_NIRQS2 (14)
# define LPC17_NGPIOAIRQS (LPC17_VALID_NIRQS0L+LPC17_VALID_NIRQS0H+LPC17_VALID_NIRQS2)
#else
# define LPC17_NGPIOAIRQS (0)
#endif
/* Total number of IRQ numbers */
#define NR_VECTORS LPC17_IRQ_NIRQS
#define NR_IRQS (LPC17_IRQ_EXTINT+LPC17_IRQ_NEXTINT+LPC17_NGPIOAIRQS)
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Inline functions
****************************************************************************/
/****************************************************************************
* Public Variables
****************************************************************************/
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_INCLUDE_LPC17XX_LPC176X_IRQ_H */

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/****************************************************************************
* arch/arm/include/lpc17xxx/lpc178x_irq.h
*
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
* Authors: Rommel Marcelo
* Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/* This file should never be included directed but, rather,
* only indirectly through nuttx/irq.h
*/
#ifndef __ARCH_ARM_INCLUDE_LPC17XX_LPC178X_IRQ_H
#define __ARCH_ARM_INCLUDE_LPC17XX_LPC178X_IRQ_H
/****************************************************************************
* Included Files
****************************************************************************/
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* IRQ numbers. The IRQ number corresponds vector number and hence map
* directly to bits in the NVIC. This does, however, waste several words of
* memory in the IRQ to handle mapping tables.
*/
/* External interrupts (vectors >= 16) */
#define LPC17_IRQ_WDT (LPC17_IRQ_EXTINT+0) /* WDT Watchdog Interrupt (WDINT) */
#define LPC17_IRQ_TMR0 (LPC17_IRQ_EXTINT+1) /* Timer 0 Match 0 - 1 (MR0, MR1)
* Capture 0 - 1 (CR0, CR1) */
#define LPC17_IRQ_TMR1 (LPC17_IRQ_EXTINT+2) /* Timer 1 Match 0 - 2 (MR0, MR1, MR2)
* Capture 0 - 1 (CR0, CR1) */
#define LPC17_IRQ_TMR2 (LPC17_IRQ_EXTINT+3) /* Timer 2 Match 0-3
* Capture 0-1 */
#define LPC17_IRQ_TMR3 (LPC17_IRQ_EXTINT+4) /* Timer 3 Match 0-3
* Capture 0-1 */
#define LPC17_IRQ_UART0 (LPC17_IRQ_EXTINT+5) /* UART 0 Rx Line Status (RLS)
* Transmit Holding Register Empty (THRE)
* Rx Data Available (RDA)
* Character Time-out Indicator (CTI)
* End of Auto-Baud (ABEO)
* Auto-Baud Time-Out (ABTO) */
#define LPC17_IRQ_UART1 (LPC17_IRQ_EXTINT+6) /* UART 1 Rx Line Status (RLS)
* Transmit Holding Register Empty (THRE)
* Rx Data Available (RDA)
* Character Time-out Indicator (CTI)
* Modem Control Change
* End of Auto-Baud (ABEO)
* Auto-Baud Time-Out (ABTO) */
#define LPC17_IRQ_UART2 (LPC17_IRQ_EXTINT+7) /* UART 2 Rx Line Status (RLS)
* Transmit Holding Register Empty (THRE)
* Rx Data Available (RDA)
* Character Time-out Indicator (CTI)
* End of Auto-Baud (ABEO)
* Auto-Baud Time-Out (ABTO) */
#define LPC17_IRQ_UART3 (LPC17_IRQ_EXTINT+8) /* UART 3 Rx Line Status (RLS)
* Transmit Holding Register Empty (THRE)
* Rx Data Available (RDA)
* Character Time-out Indicator (CTI)
* End of Auto-Baud (ABEO)
* Auto-Baud Time-Out (ABTO) */
#define LPC17_IRQ_PWM1 (LPC17_IRQ_EXTINT+9) /* PWM1 Match 0 - 6 of PWM1
* Capture 0-1 of PWM1 */
#define LPC17_IRQ_I2C0 (LPC17_IRQ_EXTINT+10) /* I2C0 SI (state change) */
#define LPC17_IRQ_I2C1 (LPC17_IRQ_EXTINT+11) /* I2C1 SI (state change) */
#define LPC17_IRQ_I2C2 (LPC17_IRQ_EXTINT+12) /* I2C2 SI (state change) */
#define LPC17_IRQ_RESERVED29 (LPC17_IRQ_EXTINT+13) /* Unused */
#define LPC17_IRQ_SSP0 (LPC17_IRQ_EXTINT+14) /* SSP0 Tx FIFO half empty of SSP0
* Rx FIFO half full of SSP0
* Rx Timeout of SSP0
* Rx Overrun of SSP0 */
#define LPC17_IRQ_SSP1 (LPC17_IRQ_EXTINT+15) /* SSP 1 Tx FIFO half empty
* Rx FIFO half full
* Rx Timeout
* Rx Overrun */
#define LPC17_IRQ_PLL0 (LPC17_IRQ_EXTINT+16) /* PLL0 (Main PLL) PLL0 Lock (PLOCK0) */
#define LPC17_IRQ_RTC (LPC17_IRQ_EXTINT+17) /* RTC Counter Increment (RTCCIF)
* Alarm (RTCALF) */
#define LPC17_IRQ_EINT0 (LPC17_IRQ_EXTINT+18) /* External Interrupt 0 (EINT0) */
#define LPC17_IRQ_EINT1 (LPC17_IRQ_EXTINT+19) /* External Interrupt 1 (EINT1) */
#define LPC17_IRQ_EINT2 (LPC17_IRQ_EXTINT+20) /* External Interrupt 2 (EINT2) */
#define LPC17_IRQ_EINT3 (LPC17_IRQ_EXTINT+21) /* External Interrupt 3 (EINT3)
* Note: EINT3 channel is shared with GPIO interrupts */
#define LPC17_IRQ_ADC (LPC17_IRQ_EXTINT+22) /* ADC A/D Converter end of conversion */
#define LPC17_IRQ_BOD (LPC17_IRQ_EXTINT+23) /* BOD Brown Out detect */
#define LPC17_IRQ_USB (LPC17_IRQ_EXTINT+24) /* USB USB_INT_REQ_LP, USB_INT_REQ_HP,
* USB_INT_REQ_DMA */
#define LPC17_IRQ_CAN (LPC17_IRQ_EXTINT+25) /* CAN CAN Common, CAN 0 Tx, CAN 0 Rx,
* CAN 1 Tx, CAN 1 Rx */
#define LPC17_IRQ_GPDMA (LPC17_IRQ_EXTINT+26) /* GPDMA IntStatus of DMA channel 0,
* IntStatus of DMA channel 1 */
#define LPC17_IRQ_I2S (LPC17_IRQ_EXTINT+27) /* I2S irq, dmareq1, dmareq2 */
#define LPC17_IRQ_ETH (LPC17_IRQ_EXTINT+28) /* Ethernet WakeupInt, SoftInt, TxDoneInt,
* TxFinishedInt, TxErrorInt,* TxUnderrunInt,
* RxDoneInt, RxFinishedInt, RxErrorInt,
* RxOverrunInt */
#define LPC17_IRQ_MCI (LPC17_IRQ_EXTINT+29) /* MCI SD Card Interface */
#define LPC17_IRQ_MCPWM (LPC17_IRQ_EXTINT+30) /* Motor Control PWM IPER[2:0], IPW[2:0],
* ICAP[2:0], FES */
#define LPC17_IRQ_QEI (LPC17_IRQ_EXTINT+31) /* Quadrature Encoder INX_Int, TIM_Int, VELC_Int,
* DIR_Int, ERR_Int, ENCLK_Int, POS0_Int, POS1_Int
* POS2_Int, REV_Int, POS0REV_Int, OS1REV_Int,
* POS2REV_Int */
#define LPC17_IRQ_PLL1 (LPC17_IRQ_EXTINT+32) /* PLL1 (USB PLL) PLL1 Lock (PLOCK1) */
#define LPC17_IRQ_USBACT (LPC17_IRQ_EXTINT+33) /* USB Activity Interrupt USB_NEED_CLK */
#define LPC17_IRQ_CANACT (LPC17_IRQ_EXTINT+34) /* CAN Activity Interrupt CAN1WAKE, CAN2WAKE */
#define LPC17_IRQ_UART4 (LPC17_IRQ_EXTINT+35) /* UART 4 Rx Line Status (RLS)
* Transmit Holding Register Empty (THRE)
* Rx Data Available (RDA)
* Character Time-out Indicator (CTI)
* End of Auto-Baud (ABEO)
* Auto-Baud Time-Out (ABTO) */
#define LPC17_IRQ_SSP2 (LPC17_IRQ_EXTINT+36) /* SSP2 Tx FIFO half empty of SSP2
* Rx FIFO half full of SSP2
* Rx Timeout of SSP2
* Rx Overrun of SSP2 */
#define LPC17_IRQ_LCD (LPC17_IRQ_EXTINT+37) /* LCD interrupt
* BER, VCompI, LNBUI, FUFI, CrsrI */
#define LPC17_IRQ_GPIO (LPC17_IRQ_EXTINT+38) /* GPIO Interrupt
* P0xREI, P2xREI, P0xFEI, P2xFEI */
#define LPC17_IRQ_PWM0 (LPC17_IRQ_EXTINT+39) /* PWM0 Match 0 - 6 of PWM0
* Capture 0-1 of PWM0 */
#define LPC17_IRQ_EEPROM (LPC17_IRQ_EXTINT+40) /* EEPROM Interrupt
* EE_PROG_DONE, EE_RW_DONE */
#define LPC17_IRQ_NEXTINT (40)
#define LPC17_IRQ_NIRQS (LPC17_IRQ_EXTINT+LPC17_IRQ_NEXTINT)
/* GPIO interrupts. The LPC177x_8x supports several interrupts on ports 0 and
* 2 (only). We go through some special efforts to keep the number of IRQs
* to a minimum in this sparse interrupt case.
*
* 31 interrupts on Port 0: p0.0 - p0.30
* 31 interrupts on Port 2: p2.0 - p2.30
* --
* 42
*/
#ifdef CONFIG_GPIO_IRQ
# define LPC17_VALID_GPIOINT0 (0xfffffffful) /* GPIO port 0 interrupt set */
# define LPC17_VALID_GPIOINT2 (0xfffffffful) /* GPIO port 2 interrupt set */
/* Set 1: 16 interrupts p0.0-p0.15 */
# define LPC17_VALID_SHIFT0L (0)
# define LPC17_VALID_FIRST0L (LPC17_IRQ_EXTINT+LPC17_IRQ_NEXTINT)
# define LPC17_IRQ_P0p0 (LPC17_VALID_FIRST0L+0)
# define LPC17_IRQ_P0p1 (LPC17_VALID_FIRST0L+1)
# define LPC17_IRQ_P0p2 (LPC17_VALID_FIRST0L+2)
# define LPC17_IRQ_P0p3 (LPC17_VALID_FIRST0L+3)
# define LPC17_IRQ_P0p4 (LPC17_VALID_FIRST0L+4)
# define LPC17_IRQ_P0p5 (LPC17_VALID_FIRST0L+5)
# define LPC17_IRQ_P0p6 (LPC17_VALID_FIRST0L+6)
# define LPC17_IRQ_P0p7 (LPC17_VALID_FIRST0L+7)
# define LPC17_IRQ_P0p8 (LPC17_VALID_FIRST0L+8)
# define LPC17_IRQ_P0p9 (LPC17_VALID_FIRST0L+9)
# define LPC17_IRQ_P0p10 (LPC17_VALID_FIRST0L+10)
# define LPC17_IRQ_P0p11 (LPC17_VALID_FIRST0L+11)
# define LPC17_IRQ_P0p12 (LPC17_VALID_FIRST0L+12)
# define LPC17_IRQ_P0p13 (LPC17_VALID_FIRST0L+13)
# define LPC17_IRQ_P0p14 (LPC17_VALID_FIRST0L+14)
# define LPC17_IRQ_P0p15 (LPC17_VALID_FIRST0L+15)
# define LPC17_VALID_NIRQS0L (16)
/* Set 2: 16 interrupts p0.16-p0.31 */
# define LPC17_VALID_SHIFT0H (16)
# define LPC17_VALID_FIRST0H (LPC17_VALID_FIRST0L+LPC17_VALID_NIRQS0L)
# define LPC17_IRQ_P0p16 (LPC17_VALID_FIRST0H+0)
# define LPC17_IRQ_P0p17 (LPC17_VALID_FIRST0H+1)
# define LPC17_IRQ_P0p18 (LPC17_VALID_FIRST0H+2)
# define LPC17_IRQ_P0p19 (LPC17_VALID_FIRST0H+3)
# define LPC17_IRQ_P0p20 (LPC17_VALID_FIRST0H+4)
# define LPC17_IRQ_P0p21 (LPC17_VALID_FIRST0H+5)
# define LPC17_IRQ_P0p22 (LPC17_VALID_FIRST0H+6)
# define LPC17_IRQ_P0p23 (LPC17_VALID_FIRST0H+7)
# define LPC17_IRQ_P0p24 (LPC17_VALID_FIRST0H+8)
# define LPC17_IRQ_P0p25 (LPC17_VALID_FIRST0H+9)
# define LPC17_IRQ_P0p26 (LPC17_VALID_FIRST0H+10)
# define LPC17_IRQ_P0p27 (LPC17_VALID_FIRST0H+11)
# define LPC17_IRQ_P0p28 (LPC17_VALID_FIRST0H+12)
# define LPC17_IRQ_P0p29 (LPC17_VALID_FIRST0H+13)
# define LPC17_IRQ_P0p30 (LPC17_VALID_FIRST0H+14)
# define LPC17_IRQ_P0p31 (LPC17_VALID_FIRST0H+15)
# define LPC17_VALID_NIRQS0H (16)
/* Set 3: 16 interrupts p2.0-p2.15 */
# define LPC17_VALID_SHIFT2L (0)
# define LPC17_VALID_FIRST2L (LPC17_VALID_FIRST0H+LPC17_VALID_NIRQS0H)
# define LPC17_IRQ_P2p0 (LPC17_VALID_FIRST2L+0)
# define LPC17_IRQ_P2p1 (LPC17_VALID_FIRST2L+1)
# define LPC17_IRQ_P2p2 (LPC17_VALID_FIRST2L+2)
# define LPC17_IRQ_P2p3 (LPC17_VALID_FIRST2L+3)
# define LPC17_IRQ_P2p4 (LPC17_VALID_FIRST2L+4)
# define LPC17_IRQ_P2p5 (LPC17_VALID_FIRST2L+5)
# define LPC17_IRQ_P2p6 (LPC17_VALID_FIRST2L+6)
# define LPC17_IRQ_P2p7 (LPC17_VALID_FIRST2L+7)
# define LPC17_IRQ_P2p8 (LPC17_VALID_FIRST2L+8)
# define LPC17_IRQ_P2p9 (LPC17_VALID_FIRST2L+9)
# define LPC17_IRQ_P2p10 (LPC17_VALID_FIRST2L+10)
# define LPC17_IRQ_P2p11 (LPC17_VALID_FIRST2L+11)
# define LPC17_IRQ_P2p12 (LPC17_VALID_FIRST2L+12)
# define LPC17_IRQ_P2p13 (LPC17_VALID_FIRST2L+13)
# define LPC17_IRQ_P2p14 (LPC17_VALID_FIRST2L+14)
# define LPC17_IRQ_P2p15 (LPC17_VALID_FIRST2L+15)
# define LPC17_VALID_NIRQS2L (16)
/* Set 4: 16 interrupts p2.16 - p2.31 */
# define LPC17_VALID_SHIFT2H (16)
# define LPC17_VALID_FIRST2H (LPC17_VALID_FIRST2L+LPC17_VALID_NIRQS2L)
# define LPC17_IRQ_P2p16 (LPC17_VALID_FIRST2H+0)
# define LPC17_IRQ_P2p17 (LPC17_VALID_FIRST2H+1)
# define LPC17_IRQ_P2p18 (LPC17_VALID_FIRST2H+2)
# define LPC17_IRQ_P2p19 (LPC17_VALID_FIRST2H+3)
# define LPC17_IRQ_P2p20 (LPC17_VALID_FIRST2H+4)
# define LPC17_IRQ_P2p21 (LPC17_VALID_FIRST2H+5)
# define LPC17_IRQ_P2p22 (LPC17_VALID_FIRST2H+6)
# define LPC17_IRQ_P2p23 (LPC17_VALID_FIRST2H+7)
# define LPC17_IRQ_P2p24 (LPC17_VALID_FIRST2H+8)
# define LPC17_IRQ_P2p25 (LPC17_VALID_FIRST2H+9)
# define LPC17_IRQ_P2p26 (LPC17_VALID_FIRST2H+10)
# define LPC17_IRQ_P2p27 (LPC17_VALID_FIRST2H+11)
# define LPC17_IRQ_P2p28 (LPC17_VALID_FIRST2H+12)
# define LPC17_IRQ_P2p29 (LPC17_VALID_FIRST2H+13)
# define LPC17_IRQ_P2p30 (LPC17_VALID_FIRST2H+14)
# define LPC17_IRQ_P2p31 (LPC17_VALID_FIRST2H+15)
# define LPC17_VALID_NIRQS2H (16)
# define LPC17_NGPIOAIRQS (LPC17_VALID_NIRQS0L+LPC17_VALID_NIRQS0H+LPC17_VALID_NIRQS2L+LPC17_VALID_NIRQS2H)
#else
# define LPC17_NGPIOAIRQS (0)
#endif
/* Total number of IRQ numbers */
#define NR_VECTORS LPC17_IRQ_NIRQS
#define NR_IRQS (LPC17_IRQ_EXTINT+LPC17_IRQ_NEXTINT+LPC17_NGPIOAIRQS)
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Inline functions
****************************************************************************/
/****************************************************************************
* Public Variables
****************************************************************************/
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_INCLUDE_LPC17XX_LPC178X_IRQ_H */

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@ -1,131 +0,0 @@
/****************************************************************************
* arch/lpc214x/irq.h
*
* Copyright (C) 2007, 2008, 2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/* This file should never be included directed but, rather,
* only indirectly through nuttx/irq.h
*/
#ifndef __ARCH_LPC214X_IRQ_H
#define __ARCH_LPC214X_IRQ_H
/****************************************************************************
* Included Files
****************************************************************************/
#ifndef __ASSEMBLY__
# include <stdint.h>
#endif
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* LPC214X Interrupts */
#define LPC214X_WDT_IRQ 0 /* Watchdog */
#define LPC214X_RESERVED_IRQ 1 /* SWI only */
#define LPC214X_DBGCOMMRX_IRQ 2 /* Embedded debug */
#define LPC214X_DBGCOMMTX_IRQ 3 /* Embedded debug */
#define LPC214X_TIMER0_IRQ 4 /* Timer 0 */
#define LPC214X_TIMER1_IRQ 5 /* Timer 1 */
#define LPC214X_UART0_IRQ 6 /* UART 0 */
#define LPC214X_UART1_IRQ 7 /* UART 1 */
#define LPC214X_PWM0_IRQ 8 /* PWM 0 */
#define LPC214X_I2C0_IRQ 9 /* I2C 0 */
#define LPC214X_SPI0_IRQ 10 /* SPI 0 */
#define LPC214X_SPI1_IRQ 11 /* SPI 1 */
#define LPC214X_PLL_IRQ 12 /* PLL Lock IRQ */
#define LPC214X_RTC_IRQ 13 /* Real Time Clock */
#define LPC214X_EINT0_IRQ 14 /* External interrupt 0 */
#define LPC214X_EINT1_IRQ 15 /* External interrupt 1 */
#define LPC214X_EINT2_IRQ 16 /* External interrupt 2 */
#define LPC214X_EINT3_IRQ 17 /* External interrupt 3 */
#define LPC214X_ADC0_IRQ 18 /* ADC 0 */
#define LPC214X_I2C1_IRQ 19 /* I2C 1 */
#define LPC214X_BOD_IRQ 20 /* Brown Out Detect */
#define LPC214X_ADC1_IRQ 21 /* ADC 1 */
#define LPC214X_USB_IRQ 22 /* USB */
#define LPC214X_IRQ_SYSTIMER LPC214X_TIMER0_IRQ
#define NR_IRQS 23
/* There are 16 vectored interrupts. If vectored interrupts are enabled, the
* following will be used by the system.
*/
#define LPC214X_SYSTIMER_VEC 0 /* System timer */
/****************************************************************************
* Public Types
****************************************************************************/
#ifndef __ASSEMBLY__
typedef void (*vic_vector_t)(uint32_t *regs);
#endif
/****************************************************************************
* Inline functions
****************************************************************************/
/****************************************************************************
* Public Variables
****************************************************************************/
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#ifndef __ASSEMBLY__
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
#ifndef CONFIG_VECTORED_INTERRUPTS
void up_attach_vector(int irq, int vector, vic_vector_t handler);
void up_detach_vector(int vector);
#endif
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif
#endif /* __ARCH_LPC214X_IRQ_H */

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arch/arm/include/lpc2378/irq.h
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@ -1,152 +0,0 @@
/****************************************************************************
* arch/lpc2378/irq.h
*
* Copyright (C) 2010 Rommel Marcelo. All rights reserved.
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
* Author: Rommel Marcelo
*
* This file is part of the NuttX RTOS and based on the lpc2148 port:
*
* Copyright (C) 2010 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/* This file should never be included directed but, rather,
* only indirectly through nuttx/irq.h
*/
#ifndef __ARCH_LPC2378_IRQ_H
#define __ARCH_LPC2378_IRQ_H
/****************************************************************************
* Included Files
****************************************************************************/
#ifndef __ASSEMBLY__
# include <stdint.h>
#endif
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* LPC2378 Interrupts */
#define WDT_IRQ 0 /* Watchdog */
#define RESERVED_IRQ 1 /* SWI only */
#define DBGCOMMRX_IRQ 2 /* Embedded debug */
#define DBGCOMMTX_IRQ 3 /* Embedded debug */
#define TIMER0_IRQ 4 /* Timer 0 */
#define TIMER1_IRQ 5 /* Timer 1 */
#define UART0_IRQ 6 /* UART 0 */
#define UART1_IRQ 7 /* UART 1 */
#define PWM0_IRQ 8 /* PWM 0 */
#define I2C0_IRQ 9 /* I2C 0 */
#define SPI0_IRQ 10 /* SPI 0 */
#define SSP0_IRQ 10 /* SSP 0 */
#define SSP1_IRQ 11 /* SSP 1 */
#define PLL_IRQ 12 /* PLL Lock IRQ */
#define RTC_IRQ 13 /* Real Time Clock */
#define EINT0_IRQ 14 /* External interrupt 0 */
#define EINT1_IRQ 15 /* External interrupt 1 */
#define EINT2_IRQ 16 /* External interrupt 2 */
#define EINT3_IRQ 17 /* External interrupt 3 */
#define ADC0_IRQ 18 /* ADC 0 */
#define I2C1_IRQ 19 /* I2C 1 */
#define BOD_IRQ 20 /* Brown Out Detect */
#define EMAC_IRQ 21 /* Ethernet */
#define USB_IRQ 22 /* USB */
#define CAN_IRQ 23 /* CAN */
#define MCI_IRQ 24 /* SD/MMC Interface */
#define GPDMA_IRQ 25 /* General Purpose DMA */
#define TIMER2_IRQ 26 /* Timer 2 */
#define TIMER3_IRQ 27 /* Timer 3 */
#define UART2_IRQ 28 /* Uart 2 */
#define UART3_IRQ 29 /* Uart 3 */
#define I2C2_IRQ 30 /* I2C 2 */
#define I2S_IRQ 31 /* I2S */
#define IRQ_SYSTIMER TIMER0_IRQ
#define NR_IRQS 32
/* There are 32 vectored interrupts. If vectored interrupts are enabled, the
* following will be used by the system.
*/
#define SYSTIMER_VEC 0 /* System timer */
#define CLASS_IRQ 0
#define CLASS_FIQ 1
#define PRIORITY_LOWEST 15
#define PRIORITY_HIGHEST 0 /* System timer */
/****************************************************************************
* Public Types
****************************************************************************/
#ifndef __ASSEMBLY__
typedef void (*vic_vector_t)(uint32_t *regs);
#endif
/****************************************************************************
* Inline functions
****************************************************************************/
/****************************************************************************
* Public Variables
****************************************************************************/
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#ifndef __ASSEMBLY__
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
#ifndef CONFIG_VECTORED_INTERRUPTS
void up_attach_vector(int irq, int priority, vic_vector_t handler);
void up_detach_vector(int vector);
#endif
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif
#endif /* __ARCH_LPC2378_IRQ_H */

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arch/arm/include/lpc31xx/irq.h
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@ -1,119 +0,0 @@
/****************************************************************************
* arch/arm/include/lpc31xx/irq.h
*
* Copyright (C) 2009-2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/* This file should never be included directed but, rather,
* only indirectly through nuttx/irq.h
*/
#ifndef __ARCH_ARM_INCLUDE_LPC31XX_IRQ_H
#define __ARCH_ARM_INCLUDE_LPC31XX_IRQ_H
/****************************************************************************
* Included Files
****************************************************************************/
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* LPC31XX Interrupts */
/* IRQ0: Reserved */
#define LPC31_IRQ_IRQ0 0 /* IRQ1: Event router cascaded IRQ0 */
#define LPC31_IRQ_IRQ1 1 /* IRQ2: Event router cascaded IRQ1 */
#define LPC31_IRQ_IRQ2 2 /* IRQ3: Event router cascaded IRQ2 */
#define LPC31_IRQ_IRQ3 3 /* IRQ4: Event router cascaded IRQ3 */
#define LPC31_IRQ_TMR0 4 /* IRQ5: Timer 0 Interrupt */
#define LPC31_IRQ_TMR1 5 /* IRQ6: Timer 1 Interrupt */
#define LPC31_IRQ_TMR2 6 /* IRQ7: Timer 2 Interrupt */
#define LPC31_IRQ_TMR3 7 /* IRQ8: Timer 3 Interrupt */
#define LPC31_IRQ_ADC 8 /* IRQ9: ADC 10-bit */
#define LPC31_IRQ_UART 9 /* IRQ10: UART */
#define LPC31_IRQ_I2C0 10 /* IRQ11: I2C0 */
#define LPC31_IRQ_I2C1 11 /* IRQ12: I2C1 */
#define LPC31_IRQ_I2STX0 12 /* IRQ13: I2S0 Transmit */
#define LPC31_IRQ_I2STX1 13 /* IRQ14: I2S1 Transmit */
#define LPC31_IRQ_I2SRX0 14 /* IRQ15: I2S0 Receive */
#define LPC31_IRQ_I2SRX1 15 /* IRQ16: I2S1 Receive */
/* IRQ17: Reserved */
#define LPC31_IRQ_LCD 17 /* IRQ18: LCD Interface */
#define LPC31_IRQ_SPISMS 18 /* IRQ19: SPI SMS */
#define LPC31_IRQ_SPITX 19 /* IRQ20: SPI Transmit */
#define LPC31_IRQ_SPIRX 20 /* IRQ21: SPI Receive */
#define LPC31_IRQ_SPIOVF 21 /* IRQ22: SPI Overflow */
#define LPC31_IRQ_SPI 22 /* IRQ23: SPI */
#define LPC31_IRQ_DMA 23 /* IRQ24: DMA */
#define LPC31_IRQ_NAND 24 /* IRQ25: NAND FLASH Controller */
#define LPC31_IRQ_MCI 25 /* IRQ26: MCI */
#define LPC31_IRQ_USBOTG 26 /* IRQ27: USB OTG */
#define LPC31_IRQ_ISRAM0 27 /* IRQ28: ISRAM0 MRC Finished */
#define LPC31_IRQ_ISRAM1 28 /* IRQ29: ISRAM1 MRC Finished */
#define LPC31_IRQ_SYSTIMER LPC31_IRQ_TMR0
#define NR_IRQS (LPC31_IRQ_ISRAM1+1)
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Inline functions
****************************************************************************/
/****************************************************************************
* Public Variables
****************************************************************************/
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#ifndef __ASSEMBLY__
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif
#endif /* __ARCH_ARM_INCLUDE_LPC31XX_IRQ_H */

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arch/arm/include/lpc43xx/chip.h
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@ -1,632 +0,0 @@
/************************************************************************************
* arch/arm/include/lpc43xx/chip.h
*
* Copyright (C) 2012-2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_INCLUDE_LPC43XX_CHIP_H
#define __ARCH_ARM_INCLUDE_LPC43XX_CHIP_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Per the data sheet: LPC4350/30/20/10 Rev. 3.2 — 4 June 2012 */
/* Get customizations for each supported chip.
*
* SRAM Resources
* --------------------- -------- ------- ------- -------
* Local SRAM LPC4310 LPC4320 LPC4330 LPC4350
* --------------------- -------- ------- ------- -------
* BANK 0 (0x1000 0000) 96Kb 128Kb 128Kb 128Kb
* BANK 1 (0x1008 0000) 40Kb 40Kb 72Kb 72Kb
* --------------------- -------- ------- ------- -------
* SUBTOTAL 136Kb 168Kb 200Kb 200Kb
* --------------------- -------- ------- ------- -------
* AHB SRAM LPC4310 LPC4320 LPC4330 LPC4350
* --------------------- -------- ------- ------- -------
* BANK 0 (0x2000 0000) 16Kb 48Kb 48Kb 48Kb
* BANK 1 (0x2000 8000) NOTE 1 NOTE 1 NOTE 1
* BANK 2 (0x2000 c000) 16Kb 16Kb 16Kb 16Kb
* --------------------- -------- ------- ------- -------
* SUBTOTAL 32Kb 32Kb 64Kb 64Kb
* --------------------- -------- ------- ------- -------
* TOTAL 168Kb 200Kb 264Kb 264Kb
* --------------------- -------- ------- ------- -------
*
* NOTE 1: The 64Kb of AHB of SRAM on the LPC4350/30/20 span all AHB SRAM
* banks but are treated as two banks of 48 an 16Kb by the NuttX memory
* manager. This gives some symmetry to all of the members of the family.
*/
/* Per the user manual: UM10503, Rev. 1.2 — 8 June 2012 */
/* Get customizations for each supported chip.
*
* SRAM Resources
* --------------------- -------- ------- ------- ------- ------- -------
* Local SRAM LPC4310 LPC4320 LPC4330 LPC4350 LPC4353 LPC4357
* --------------------- -------- ------- ------- ------- ------- -------
* BANK 0 (0x1000 0000) 96Kb 96Kb 128Kb 128Kb 32Kb 32Kb
* BANK 1 (0x1008 0000) 40Kb 40Kb 72Kb 72Kb 40Kb 40Kb
* --------------------- -------- ------- ------- ------- ------- -------
* SUBTOTAL 136Kb 136Kb 200Kb 200Kb 72Kb 72Kb
* --------------------- -------- ------- ------- ------- ------- -------
* AHB SRAM LPC4310 LPC4320 LPC4330 LPC4350 LPC4353 LPC4357
* --------------------- -------- ------- ------- ------- ------- -------
* BANK 0 (0x2000 0000) 16Kb 48Kb 48Kb 48Kb 48Kb 48Kb
* BANK 1 (0x2000 8000) NOTE 1 NOTE 1 NOTE 1 NOTE 1 NOTE 1
* BANK 2 (0x2000 c000) 16Kb 16Kb 16Kb 16Kb 16Kb 16Kb
* --------------------- -------- ------- ------- ------- ------- -------
* SUBTOTAL 32Kb 64Kb 64Kb 64Kb 64Kb 64Kb
* --------------------- -------- ------- ------- ------- ------- -------
* TOTAL 168Kb 200Kb 264Kb 264Kb 136Kb 136Kb
* --------------------- -------- ------- ------- ------- ------- -------
*
* --------------------- -------- ------- ------- ------- ------- -------
* FLASH LPC4310 LPC4320 LPC4330 LPC4350 LPC4353 LPC4357
* --------------------- -------- ------- ------- ------- ------- -------
* BANK A (0x1a00 0000) 256Kb 512Kb
* BANK B (0x1b00 8000) 256Kb 512Kb
* --------------------- -------- ------- ------- ------- ------- -------
* TOTAL None None None None 512Kb 1024Kb
* --------------------- -------- ------- ------- ------- ------- -------
*
* NOTE 1: The 64Kb of AHB of SRAM on the LPC4350/30/20 span all AHB SRAM
* banks but are treated as two banks of 48 an 16Kb by the NuttX memory
* manager. This gives some symmetry to all of the members of the family.
*/
#if defined(CONFIG_ARCH_CHIP_LPC4310FBD144)
# define LPC43_FLASH_BANKA_SIZE (0) /* Flashless */
# define LPC43_FLASH_BANKB_SIZE (0)
# define LPC43_LOCSRAM_BANK0_SIZE (96*1024) /* 136Kb Local SRAM */
# define LPC43_LOCSRAM_BANK1_SIZE (40*1024)
# define LPC43_AHBSRAM_BANK0_SIZE (16*1024) /* 32Kb AHB SRAM */
# define LPC43_AHBSRAM_BANK1_SIZE (0)
# define LPC43_AHBSRAM_BANK2_SIZE (16*1024)
# define LPC43_EEPROM_SIZE (0) /* No EEPROM */
# undef LPC43_NLCD /* No LCD controller */
# undef LPC43_ETHERNET /* No Ethernet controller */
# undef LPC43_USB0 /* No USB0 (Host, Device, OTG) */
# undef LPC43_USB1 /* No USB1 (Host, Device) */
# undef LPC43_USB1_ULPI /* No USB1 (Host, Device) with ULPI I/F */
# define LPC43_MCPWM (1) /* One PWM interface */
# undef LPC43_QEI /* No Quadrature Encoder capability */
# define LPC43_NUSARTS (4) /* Three USARTs + 1 UART */
# define LPC43_NSSP (2) /* Two SSP controllers */
# define LPC43_NTIMERS (4) /* Four Timers */
# define LPC43_NI2C (2) /* Two I2C controllers */
# define LPC43_NI2S (2) /* Two I2S controllers */
# define LPC43_NCAN (2) /* Two CAN controllers */
# define LPC43_NDAC (1) /* One 10-bit DAC */
# define LPC43_NADC (2) /* Two 10-bit ADC controllers */
# define LPC43_NADC_CHANNELS (8) /* Eight ADC channels */
#elif defined(CONFIG_ARCH_CHIP_LPC4310FET100)
# define LPC43_FLASH_BANKA_SIZE (0) /* Flashless */
# define LPC43_FLASH_BANKB_SIZE (0)
# define LPC43_LOCSRAM_BANK0_SIZE (96*1024) /* 136Kb Local SRAM */
# define LPC43_LOCSRAM_BANK1_SIZE (40*1024)
# define LPC43_AHBSRAM_BANK0_SIZE (16*1024) /* 32Kb AHB SRAM */
# define LPC43_AHBSRAM_BANK1_SIZE (0)
# define LPC43_AHBSRAM_BANK2_SIZE (16*1024)
# define LPC43_EEPROM_SIZE (0) /* No EEPROM */
# undef LPC43_NLCD /* No LCD controller */
# undef LPC43_ETHERNET /* No Ethernet controller */
# undef LPC43_USB0 /* No USB0 (Host, Device, OTG) */
# undef LPC43_USB1 /* No USB1 (Host, Device) */
# undef LPC43_USB1_ULPI /* No USB1 (Host, Device) with ULPI I/F */
# undef LPC43_MCPWM /* No PWM capability */
# undef LPC43_QEI /* No Quadrature Encoder capability */
# define LPC43_NUSARTS (4) /* Three USARTs + 1 UART */
# define LPC43_NSSP (2) /* Two SSP controllers */
# define LPC43_NTIMERS (4) /* Four Timers */
# define LPC43_NI2C (2) /* Two I2C controllers */
# define LPC43_NI2S (2) /* Two I2S controllers */
# define LPC43_NCAN (2) /* Two CAN controllers */
# define LPC43_NDAC (1) /* One 10-bit DAC */
# define LPC43_NADC (2) /* Two 10-bit ADC controllers */
# define LPC43_NADC_CHANNELS (4) /* Four ADC channels */
#elif defined(CONFIG_ARCH_CHIP_LPC4320FBD144)
# warning "Data sheet and user manual are consistement for the LPC4320"
# define LPC43_FLASH_BANKA_SIZE (0) /* Flashless */
# define LPC43_FLASH_BANKB_SIZE (0)
# define LPC43_LOCSRAM_BANK0_SIZE (128*1024) /* 168Kb Local SRAM*/
# define LPC43_LOCSRAM_BANK1_SIZE (40*1024)
# define LPC43_AHBSRAM_BANK0_SIZE (16*1024) /* 32Kb AHB SRAM */
# define LPC43_AHBSRAM_BANK1_SIZE (0)
# define LPC43_AHBSRAM_BANK2_SIZE (16*1024)
# define LPC43_EEPROM_SIZE (0) /* No EEPROM */
# undef LPC43_NLCD /* No LCD controller */
# undef LPC43_ETHERNET /* No Ethernet controller */
# define LPC43_USB0 (1) /* Have USB0 (Host, Device, OTG) */
# undef LPC43_USB1 /* No USB1 (Host, Device) */
# undef LPC43_USB1_ULPI /* No USB1 (Host, Device) with ULPI I/F */
# define LPC43_MCPWM (1) /* One PWM interface */
# undef LPC43_QEI /* No Quadrature Encoder capability */
# define LPC43_NUSARTS (4) /* Three USARTs + 1 UART */
# define LPC43_NSSP (2) /* Two SSP controllers */
# define LPC43_NTIMERS (4) /* Four Timers */
# define LPC43_NI2C (2) /* Two I2C controllers */
# define LPC43_NI2S (2) /* Two I2S controllers */
# define LPC43_NCAN (2) /* Two CAN controllers */
# define LPC43_NDAC (1) /* One 10-bit DAC */
# define LPC43_NADC (2) /* Two 10-bit ADC controllers */
# define LPC43_NADC_CHANNELS (8) /* Eight ADC channels */
#elif defined(CONFIG_ARCH_CHIP_LPC4320FET100)
# warning "Data sheet and user manual are consistement for the LPC4320"
# define LPC43_FLASH_BANKA_SIZE (0) /* Flashless */
# define LPC43_FLASH_BANKB_SIZE (0)
# define LPC43_LOCSRAM_BANK0_SIZE (128*1024) /* 168Kb Local SRAM*/
# define LPC43_LOCSRAM_BANK1_SIZE (40*1024)
# define LPC43_AHBSRAM_BANK0_SIZE (16*1024) /* 32Kb AHB SRAM */
# define LPC43_AHBSRAM_BANK1_SIZE (0)
# define LPC43_AHBSRAM_BANK2_SIZE (16*1024)
# define LPC43_EEPROM_SIZE (0) /* No EEPROM */
# undef LPC43_NLCD /* No LCD controller */
# undef LPC43_ETHERNET /* No Ethernet controller */
# define LPC43_USB0 (1) /* Have USB0 (Host, Device, OTG) */
# undef LPC43_USB1 /* No USB1 (Host, Device) */
# undef LPC43_USB1_ULPI /* No USB1 (Host, Device) with ULPI I/F */
# undef LPC43_MCPWM /* No PWM capability */
# undef LPC43_QEI /* No Quadrature Encoder capability */
# define LPC43_NUSARTS (4) /* Three USARTs + 1 UART */
# define LPC43_NSSP (2) /* Two SSP controllers */
# define LPC43_NTIMERS (4) /* Four Timers */
# define LPC43_NI2C (2) /* Two I2C controllers */
# define LPC43_NI2S (2) /* Two I2S controllers */
# define LPC43_NCAN (2) /* Two CAN controllers */
# define LPC43_NDAC (1) /* One 10-bit DAC */
# define LPC43_NADC (2) /* Two 10-bit ADC controllers */
# define LPC43_NADC_CHANNELS (4) /* Four ADC channels */
#elif defined(CONFIG_ARCH_CHIP_LPC4330FBD144)
# define LPC43_FLASH_BANKA_SIZE (0) /* Flashless */
# define LPC43_FLASH_BANKB_SIZE (0)
# define LPC43_LOCSRAM_BANK0_SIZE (128*1024) /* 200Kb Local SRAM*/
# define LPC43_LOCSRAM_BANK1_SIZE (72*1024)
# define LPC43_AHBSRAM_BANK0_SIZE (48*1024) /* 64Kb AHB SRAM */
# define LPC43_AHBSRAM_BANK1_SIZE (0)
# define LPC43_AHBSRAM_BANK2_SIZE (16*1024)
# define LPC43_EEPROM_SIZE (0) /* No EEPROM */
# undef LPC43_NLCD /* No LCD controller */
# define LPC43_ETHERNET (1) /* One Ethernet controller */
# define LPC43_USB0 (1) /* Have USB0 (Host, Device, OTG) */
# define LPC43_USB1 (1) /* Have USB1 (Host, Device) */
# undef LPC43_USB1_ULPI /* No USB1 (Host, Device) with ULPI I/F */
# define LPC43_MCPWM (1) /* One PWM interface */
# undef LPC43_QEI /* No Quadrature Encoder capability */
# define LPC43_NUSARTS (4) /* Three USARTs + 1 UART */
# define LPC43_NSSP (2) /* Two SSP controllers */
# define LPC43_NTIMERS (4) /* Four Timers */
# define LPC43_NI2C (2) /* Two I2C controllers */
# define LPC43_NI2S (2) /* Two I2S controllers */
# define LPC43_NCAN (2) /* Two CAN controllers */
# define LPC43_NDAC (1) /* One 10-bit DAC */
# define LPC43_NADC (2) /* Two 10-bit ADC controllers */
# define LPC43_NADC_CHANNELS (8) /* Eight ADC channels */
#elif defined(CONFIG_ARCH_CHIP_LPC4330FET100)
# define LPC43_FLASH_BANKA_SIZE (0) /* Flashless */
# define LPC43_FLASH_BANKB_SIZE (0)
# define LPC43_LOCSRAM_BANK0_SIZE (128*1024) /* 200Kb Local SRAM*/
# define LPC43_LOCSRAM_BANK1_SIZE (72*1024)
# define LPC43_AHBSRAM_BANK0_SIZE (48*1024) /* 64Kb AHB SRAM */
# define LPC43_AHBSRAM_BANK1_SIZE (0)
# define LPC43_AHBSRAM_BANK2_SIZE (16*1024)
# define LPC43_EEPROM_SIZE (0) /* No EEPROM */
# undef LPC43_NLCD /* No LCD controller */
# define LPC43_ETHERNET (1) /* One Ethernet controller */
# define LPC43_USB0 (1) /* Have USB0 (Host, Device, OTG) */
# define LPC43_USB1 (1) /* Have USB1 (Host, Device) */
# undef LPC43_USB1_ULPI /* No USB1 (Host, Device) with ULPI I/F */
# undef LPC43_MCPWM /* No PWM capability */
# undef LPC43_QEI /* No Quadrature Encoder capability */
# define LPC43_NUSARTS (4) /* Three USARTs + 1 UART */
# define LPC43_NSSP (2) /* Two SSP controllers */
# define LPC43_NTIMERS (4) /* Four Timers */
# define LPC43_NI2C (2) /* Two I2C controllers */
# define LPC43_NI2S (2) /* Two I2S controllers */
# define LPC43_NCAN (2) /* Two CAN controllers */
# define LPC43_NDAC (1) /* One 10-bit DAC */
# define LPC43_NADC (2) /* Two 10-bit ADC controllers */
# define LPC43_NADC_CHANNELS (4) /* Four ADC channels */
#elif defined(CONFIG_ARCH_CHIP_LPC4330FET180)
# define LPC43_FLASH_BANKA_SIZE (0) /* Flashless */
# define LPC43_FLASH_BANKB_SIZE (0)
# define LPC43_LOCSRAM_BANK0_SIZE (128*1024) /* 200Kb Local SRAM*/
# define LPC43_LOCSRAM_BANK1_SIZE (72*1024)
# define LPC43_AHBSRAM_BANK0_SIZE (48*1024) /* 64Kb AHB SRAM */
# define LPC43_AHBSRAM_BANK1_SIZE (0)
# define LPC43_AHBSRAM_BANK2_SIZE (16*1024)
# define LPC43_EEPROM_SIZE (0) /* No EEPROM */
# undef LPC43_NLCD /* No LCD controller */
# define LPC43_ETHERNET (1) /* One Ethernet controller */
# define LPC43_USB0 (1) /* Have USB0 (Host, Device, OTG) */
# define LPC43_USB1 (1) /* Have USB1 (Host, Device) */
# define LPC43_USB1_ULPI (1) /* Have USB1 (Host, Device) with ULPI I/F */
# define LPC43_MCPWM (1) /* One PWM interface */
# define LPC43_QEI (1) /* One Quadrature Encoder interface */
# define LPC43_NUSARTS (4) /* Three USARTs + 1 UART */
# define LPC43_NSSP (2) /* Two SSP controllers */
# define LPC43_NTIMERS (4) /* Four Timers */
# define LPC43_NI2C (2) /* Two I2C controllers */
# define LPC43_NI2S (2) /* Two I2S controllers */
# define LPC43_NCAN (2) /* Two CAN controllers */
# define LPC43_NDAC (1) /* One 10-bit DAC */
# define LPC43_NADC (2) /* Two 10-bit ADC controllers */
# define LPC43_NADC_CHANNELS (8) /* Eight ADC channels */
#elif defined(CONFIG_ARCH_CHIP_LPC4330FET256)
# define LPC43_FLASH_BANKA_SIZE (0) /* Flashless */
# define LPC43_FLASH_BANKB_SIZE (0)
# define LPC43_LOCSRAM_BANK0_SIZE (128*1024) /* 200Kb Local SRAM*/
# define LPC43_LOCSRAM_BANK1_SIZE (72*1024)
# define LPC43_AHBSRAM_BANK0_SIZE (48*1024) /* 64Kb AHB SRAM */
# define LPC43_AHBSRAM_BANK1_SIZE (0)
# define LPC43_AHBSRAM_BANK2_SIZE (16*1024)
# define LPC43_EEPROM_SIZE (0) /* No EEPROM */
# undef LPC43_NLCD /* No LCD controller */
# define LPC43_ETHERNET (1) /* One Ethernet controller */
# define LPC43_USB0 (1) /* Have USB0 (Host, Device, OTG) */
# define LPC43_USB1 (1) /* Have USB1 (Host, Device) */
# define LPC43_USB1_ULPI (1) /* Have USB1 (Host, Device) with ULPI I/F */
# define LPC43_MCPWM (1) /* One PWM interface */
# define LPC43_QEI (1) /* One Quadrature Encoder interface */
# define LPC43_NUSARTS (4) /* Three USARTs + 1 UART */
# define LPC43_NSSP (2) /* Two SSP controllers */
# define LPC43_NTIMERS (4) /* Four Timers */
# define LPC43_NI2C (2) /* Two I2C controllers */
# define LPC43_NI2S (2) /* Two I2S controllers */
# define LPC43_NCAN (2) /* Two CAN controllers */
# define LPC43_NDAC (1) /* One 10-bit DAC */
# define LPC43_NADC (2) /* Two 10-bit ADC controllers */
# define LPC43_NADC_CHANNELS (8) /* Eight ADC channels */
#elif defined(CONFIG_ARCH_CHIP_LPC4350FBD208)
# define LPC43_FLASH_BANKA_SIZE (0) /* Flashless */
# define LPC43_FLASH_BANKB_SIZE (0)
# define LPC43_LOCSRAM_BANK0_SIZE (128*1024) /* 200Kb Local SRAM*/
# define LPC43_LOCSRAM_BANK1_SIZE (72*1024)
# define LPC43_AHBSRAM_BANK0_SIZE (48*1024) /* 64Kb AHB SRAM */
# define LPC43_AHBSRAM_BANK1_SIZE (0)
# define LPC43_AHBSRAM_BANK2_SIZE (16*1024)
# define LPC43_EEPROM_SIZE (0) /* No EEPROM */
# define LPC43_NLCD (1) /* One LCD controller */
# define LPC43_ETHERNET (1) /* One Ethernet controller */
# define LPC43_USB0 (1) /* Have USB0 (Host, Device, OTG) */
# define LPC43_USB1 (1) /* Have USB1 (Host, Device) */
# define LPC43_USB1_ULPI (1) /* Have USB1 (Host, Device) with ULPI I/F */
# define LPC43_MCPWM (1) /* One PWM interface */
# define LPC43_QEI (1) /* One Quadrature Encoder interface */
# define LPC43_NUSARTS (4) /* Three USARTs + 1 UART */
# define LPC43_NSSP (2) /* Two SSP controllers */
# define LPC43_NTIMERS (4) /* Four Timers */
# define LPC43_NI2C (2) /* Two I2C controllers */
# define LPC43_NI2S (2) /* Two I2S controllers */
# define LPC43_NCAN (2) /* Two CAN controllers */
# define LPC43_NDAC (1) /* One 10-bit DAC */
# define LPC43_NADC (2) /* Two 10-bit ADC controllers */
# define LPC43_NADC_CHANNELS (8) /* Eight ADC channels */
#elif defined(CONFIG_ARCH_CHIP_LPC4350FET180)
# define LPC43_FLASH_BANKA_SIZE (0) /* Flashless */
# define LPC43_FLASH_BANKB_SIZE (0)
# define LPC43_LOCSRAM_BANK0_SIZE (128*1024) /* 200Kb Local SRAM*/
# define LPC43_LOCSRAM_BANK1_SIZE (72*1024)
# define LPC43_AHBSRAM_BANK0_SIZE (48*1024) /* 64Kb AHB SRAM */
# define LPC43_AHBSRAM_BANK1_SIZE (0)
# define LPC43_AHBSRAM_BANK2_SIZE (16*1024)
# define LPC43_EEPROM_SIZE (0) /* No EEPROM */
# define LPC43_NLCD (1) /* One LCD controller */
# define LPC43_ETHERNET (1) /* One Ethernet controller */
# define LPC43_USB0 (1) /* Have USB0 (Host, Device, OTG) */
# define LPC43_USB1 (1) /* Have USB1 (Host, Device) */
# define LPC43_USB1_ULPI (1) /* Have USB1 (Host, Device) with ULPI I/F */
# define LPC43_MCPWM (1) /* One PWM interface */
# define LPC43_QEI (1) /* One Quadrature Encoder interface */
# define LPC43_NUSARTS (4) /* Three USARTs + 1 UART */
# define LPC43_NSSP (2) /* Two SSP controllers */
# define LPC43_NTIMERS (4) /* Four Timers */
# define LPC43_NI2C (2) /* Two I2C controllers */
# define LPC43_NI2S (2) /* Two I2S controllers */
# define LPC43_NCAN (2) /* Two CAN controllers */
# define LPC43_NDAC (1) /* One 10-bit DAC */
# define LPC43_NADC (2) /* Two 10-bit ADC controllers */
# define LPC43_NADC_CHANNELS (8) /* Eight ADC channels */
#elif defined(CONFIG_ARCH_CHIP_LPC4350FET256)
# define LPC43_FLASH_BANKA_SIZE (0) /* Flashless */
# define LPC43_FLASH_BANKB_SIZE (0)
# define LPC43_LOCSRAM_BANK0_SIZE (128*1024) /* 200Kb Local SRAM*/
# define LPC43_LOCSRAM_BANK1_SIZE (72*1024)
# define LPC43_AHBSRAM_BANK0_SIZE (48*1024) /* 64Kb AHB SRAM */
# define LPC43_AHBSRAM_BANK1_SIZE (0)
# define LPC43_AHBSRAM_BANK2_SIZE (16*1024)
# define LPC43_EEPROM_SIZE (0) /* No EEPROM */
# define LPC43_NLCD (1) /* One LCD controller */
# define LPC43_ETHERNET (1) /* One Ethernet controller */
# define LPC43_USB0 (1) /* Have USB0 (Host, Device, OTG) */
# define LPC43_USB1 (1) /* Have USB1 (Host, Device) */
# define LPC43_USB1_ULPI (1) /* Have USB1 (Host, Device) with ULPI I/F */
# define LPC43_MCPWM (1) /* One PWM interface */
# define LPC43_QEI (1) /* One Quadrature Encoder interface */
# define LPC43_NUSARTS (4) /* Three USARTs + 1 UART */
# define LPC43_NSSP (2) /* Two SSP controllers */
# define LPC43_NTIMERS (4) /* Four Timers */
# define LPC43_NI2C (2) /* Two I2C controllers */
# define LPC43_NI2S (2) /* Two I2S controllers */
# define LPC43_NCAN (2) /* Two CAN controllers */
# define LPC43_NDAC (1) /* One 10-bit DAC */
# define LPC43_NADC (2) /* Two 10-bit ADC controllers */
# define LPC43_NADC_CHANNELS (8) /* Eight ADC channels */
#elif defined(CONFIG_ARCH_CHIP_LPC4353FBD208)
# define LPC43_FLASH_BANKA_SIZE (256*1025) /* 512Kb FLASH */
# define LPC43_FLASH_BANKB_SIZE (256*1025)
# define LPC43_LOCSRAM_BANK0_SIZE (32*1024) /* 72Kb Local SRAM*/
# define LPC43_LOCSRAM_BANK1_SIZE (40*1024)
# define LPC43_AHBSRAM_BANK0_SIZE (48*1024) /* 64Kb AHB SRAM */
# define LPC43_AHBSRAM_BANK1_SIZE (0)
# define LPC43_AHBSRAM_BANK2_SIZE (16*1024)
# define LPC43_EEPROM_SIZE (16*1024) /* 16Kb EEPROM */
# define LPC43_NLCD (1) /* Has LCD controller */
# define LPC43_ETHERNET (1) /* One Ethernet controller */
# define LPC43_USB0 (1) /* Have USB0 (Host, Device, OTG) */
# define LPC43_USB1 (1) /* Have USB1 (Host, Device) */
# define LPC43_USB1_ULPI (1) /* Have USB1 (Host, Device) with ULPI I/F */
# define LPC43_MCPWM (1) /* One PWM interface */
# define LPC43_QEI (1) /* One Quadrature Encoder interface */
# define LPC43_NUSARTS (4) /* Three USARTs + 1 UART */
# define LPC43_NSSP (2) /* Two SSP controllers */
# define LPC43_NTIMERS (4) /* Four Timers */
# define LPC43_NI2C (2) /* Two I2C controllers */
# define LPC43_NI2S (2) /* Two I2S controllers */
# define LPC43_NCAN (2) /* Two CAN controllers */
# define LPC43_NDAC (1) /* One 10-bit DAC */
# define LPC43_NADC (2) /* Two 10-bit ADC controllers */
# define LPC43_NADC_CHANNELS (8) /* Eight ADC channels */
#elif defined(CONFIG_ARCH_CHIP_LPC4353FET180)
# define LPC43_FLASH_BANKA_SIZE (256*1025) /* 512Kb FLASH */
# define LPC43_FLASH_BANKB_SIZE (256*1025)
# define LPC43_LOCSRAM_BANK0_SIZE (32*1024) /* 72Kb Local SRAM*/
# define LPC43_LOCSRAM_BANK1_SIZE (40*1024)
# define LPC43_AHBSRAM_BANK0_SIZE (48*1024) /* 64Kb AHB SRAM */
# define LPC43_AHBSRAM_BANK1_SIZE (0)
# define LPC43_AHBSRAM_BANK2_SIZE (16*1024)
# define LPC43_EEPROM_SIZE (16*1024) /* 16Kb EEPROM */
# define LPC43_NLCD (1) /* Has LCD controller */
# define LPC43_ETHERNET (1) /* One Ethernet controller */
# define LPC43_USB0 (1) /* Have USB0 (Host, Device, OTG) */
# define LPC43_USB1 (1) /* Have USB1 (Host, Device) */
# define LPC43_USB1_ULPI (1) /* Have USB1 (Host, Device) with ULPI I/F */
# define LPC43_MCPWM (1) /* One PWM interface */
# define LPC43_QEI (1) /* One Quadrature Encoder interface */
# define LPC43_NUSARTS (4) /* Three USARTs + 1 UART */
# define LPC43_NSSP (2) /* Two SSP controllers */
# define LPC43_NTIMERS (4) /* Four Timers */
# define LPC43_NI2C (2) /* Two I2C controllers */
# define LPC43_NI2S (2) /* Two I2S controllers */
# define LPC43_NCAN (2) /* Two CAN controllers */
# define LPC43_NDAC (1) /* One 10-bit DAC */
# define LPC43_NADC (2) /* Two 10-bit ADC controllers */
# define LPC43_NADC_CHANNELS (8) /* Eight ADC channels */
#elif defined(CONFIG_ARCH_CHIP_LPC4353FET256)
# define LPC43_FLASH_BANKA_SIZE (256*1025) /* 512Kb FLASH */
# define LPC43_FLASH_BANKB_SIZE (256*1025)
# define LPC43_LOCSRAM_BANK0_SIZE (32*1024) /* 72Kb Local SRAM*/
# define LPC43_LOCSRAM_BANK1_SIZE (40*1024)
# define LPC43_AHBSRAM_BANK0_SIZE (48*1024) /* 64Kb AHB SRAM */
# define LPC43_AHBSRAM_BANK1_SIZE (0)
# define LPC43_AHBSRAM_BANK2_SIZE (16*1024)
# define LPC43_EEPROM_SIZE (16*1024) /* 16Kb EEPROM */
# define LPC43_NLCD (1) /* Has LCD controller */
# define LPC43_ETHERNET (1) /* One Ethernet controller */
# define LPC43_USB0 (1) /* Have USB0 (Host, Device, OTG) */
# define LPC43_USB1 (1) /* Have USB1 (Host, Device) */
# define LPC43_USB1_ULPI (1) /* Have USB1 (Host, Device) with ULPI I/F */
# define LPC43_MCPWM (1) /* One PWM interface */
# define LPC43_QEI (1) /* One Quadrature Encoder interface */
# define LPC43_NUSARTS (4) /* Three USARTs + 1 UART */
# define LPC43_NSSP (2) /* Two SSP controllers */
# define LPC43_NTIMERS (4) /* Four Timers */
# define LPC43_NI2C (2) /* Two I2C controllers */
# define LPC43_NI2S (2) /* Two I2S controllers */
# define LPC43_NCAN (2) /* Two CAN controllers */
# define LPC43_NDAC (1) /* One 10-bit DAC */
# define LPC43_NADC (2) /* Two 10-bit ADC controllers */
# define LPC43_NADC_CHANNELS (8) /* Eight ADC channels */
#elif defined(CONFIG_ARCH_CHIP_LPC4357FET180)
# define LPC43_FLASH_BANKA_SIZE (512*1025) /* 1024Kb FLASH */
# define LPC43_FLASH_BANKB_SIZE (512*1025)
# define LPC43_LOCSRAM_BANK0_SIZE (32*1024) /* 72Kb Local SRAM*/
# define LPC43_LOCSRAM_BANK1_SIZE (40*1024)
# define LPC43_AHBSRAM_BANK0_SIZE (48*1024) /* 64Kb AHB SRAM */
# define LPC43_AHBSRAM_BANK1_SIZE (0)
# define LPC43_AHBSRAM_BANK2_SIZE (16*1024)
# define LPC43_EEPROM_SIZE (16*1024) /* 16Kb EEPROM */
# define LPC43_NLCD (1) /* Has LCD controller */
# define LPC43_ETHERNET (1) /* One Ethernet controller */
# define LPC43_USB0 (1) /* Have USB0 (Host, Device, OTG) */
# define LPC43_USB1 (1) /* Have USB1 (Host, Device) */
# define LPC43_USB1_ULPI (1) /* Have USB1 (Host, Device) with ULPI I/F */
# define LPC43_MCPWM (1) /* One PWM interface */
# define LPC43_QEI (1) /* One Quadrature Encoder interface */
# define LPC43_NUSARTS (4) /* Three USARTs + 1 UART */
# define LPC43_NSSP (2) /* Two SSP controllers */
# define LPC43_NTIMERS (4) /* Four Timers */
# define LPC43_NI2C (2) /* Two I2C controllers */
# define LPC43_NI2S (2) /* Two I2S controllers */
# define LPC43_NCAN (2) /* Two CAN controllers */
# define LPC43_NDAC (1) /* One 10-bit DAC */
# define LPC43_NADC (2) /* Two 10-bit ADC controllers */
# define LPC43_NADC_CHANNELS (8) /* Eight ADC channels */
#elif defined(CONFIG_ARCH_CHIP_LPC4357FBD208)
# define LPC43_FLASH_BANKA_SIZE (512*1025) /* 1024Kb FLASH */
# define LPC43_FLASH_BANKB_SIZE (512*1025)
# define LPC43_LOCSRAM_BANK0_SIZE (32*1024) /* 72Kb Local SRAM*/
# define LPC43_LOCSRAM_BANK1_SIZE (40*1024)
# define LPC43_AHBSRAM_BANK0_SIZE (48*1024) /* 64Kb AHB SRAM */
# define LPC43_AHBSRAM_BANK1_SIZE (0)
# define LPC43_AHBSRAM_BANK2_SIZE (16*1024)
# define LPC43_EEPROM_SIZE (16*1024) /* 16Kb EEPROM */
# define LPC43_NLCD (1) /* Has LCD controller */
# define LPC43_ETHERNET (1) /* One Ethernet controller */
# define LPC43_USB0 (1) /* Have USB0 (Host, Device, OTG) */
# define LPC43_USB1 (1) /* Have USB1 (Host, Device) */
# define LPC43_USB1_ULPI (1) /* Have USB1 (Host, Device) with ULPI I/F */
# define LPC43_MCPWM (1) /* One PWM interface */
# define LPC43_QEI (1) /* One Quadrature Encoder interface */
# define LPC43_NUSARTS (4) /* Three USARTs + 1 UART */
# define LPC43_NSSP (2) /* Two SSP controllers */
# define LPC43_NTIMERS (4) /* Four Timers */
# define LPC43_NI2C (2) /* Two I2C controllers */
# define LPC43_NI2S (2) /* Two I2S controllers */
# define LPC43_NCAN (2) /* Two CAN controllers */
# define LPC43_NDAC (1) /* One 10-bit DAC */
# define LPC43_NADC (2) /* Two 10-bit ADC controllers */
# define LPC43_NADC_CHANNELS (8) /* Eight ADC channels */
#elif defined(CONFIG_ARCH_CHIP_LPC4357FET256)
# define LPC43_FLASH_BANKA_SIZE (512*1025) /* 1024Kb FLASH */
# define LPC43_FLASH_BANKB_SIZE (512*1025)
# define LPC43_LOCSRAM_BANK0_SIZE (32*1024) /* 72Kb Local SRAM*/
# define LPC43_LOCSRAM_BANK1_SIZE (40*1024)
# define LPC43_AHBSRAM_BANK0_SIZE (48*1024) /* 64Kb AHB SRAM */
# define LPC43_AHBSRAM_BANK1_SIZE (0)
# define LPC43_AHBSRAM_BANK2_SIZE (16*1024)
# define LPC43_EEPROM_SIZE (16*1024) /* 16Kb EEPROM */
# define LPC43_NLCD (1) /* Has LCD controller */
# define LPC43_ETHERNET (1) /* One Ethernet controller */
# define LPC43_USB0 (1) /* Have USB0 (Host, Device, OTG) */
# define LPC43_USB1 (1) /* Have USB1 (Host, Device) */
# define LPC43_USB1_ULPI (1) /* Have USB1 (Host, Device) with ULPI I/F */
# define LPC43_MCPWM (1) /* One PWM interface */
# define LPC43_QEI (1) /* One Quadrature Encoder interface */
# define LPC43_NUSARTS (4) /* Three USARTs + 1 UART */
# define LPC43_NSSP (2) /* Two SSP controllers */
# define LPC43_NTIMERS (4) /* Four Timers */
# define LPC43_NI2C (2) /* Two I2C controllers */
# define LPC43_NI2S (2) /* Two I2S controllers */
# define LPC43_NCAN (2) /* Two CAN controllers */
# define LPC43_NDAC (1) /* One 10-bit DAC */
# define LPC43_NADC (2) /* Two 10-bit ADC controllers */
# define LPC43_NADC_CHANNELS (8) /* Eight ADC channels */
#else
# error "Unsupported LPC43xx chip"
#endif
/* NVIC priority levels *************************************************************/
/* Each priority field holds a priority value, 0-31. The lower the value, the greater
* the priority of the corresponding interrupt.
*
* The Cortex-M4 core supports up to 53 interrupts an 8 prgrammable interrupt
* priority levels; The Cortex-M0 core supports up to 32 interrupts with 4
* programmable interrupt priorities.
*/
#define LPC43M4_SYSH_PRIORITY_MIN 0xe0 /* All bits[7:5] set is minimum priority */
#define LPC43M4_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
#define LPC43M4_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */
#define LPC43M4_SYSH_PRIORITY_STEP 0x10 /* Steps between priorities */
#define LPC43M0_SYSH_PRIORITY_MIN 0xc0 /* All bits[7:6] set is minimum priority */
#define LPC43M0_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
#define LPC43M0_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */
#define LPC43M0_SYSH_PRIORITY_STEP 0x20 /* Steps between priorities */
/* Only the Cortex-M4 is supported by Nuttx */
#define NVIC_SYSH_PRIORITY_MIN LPC43M4_SYSH_PRIORITY_MIN
#define NVIC_SYSH_PRIORITY_DEFAULT LPC43M4_SYSH_PRIORITY_DEFAULT
#define NVIC_SYSH_PRIORITY_MAX LPC43M4_SYSH_PRIORITY_MAX
#define NVIC_SYSH_PRIORITY_STEP LPC43M4_SYSH_PRIORITY_INCR
/* If CONFIG_ARMV7M_USEBASEPRI is selected, then interrupts will be disabled
* by setting the BASEPRI register to NVIC_SYSH_DISABLE_PRIORITY so that most
* interrupts will not have execution priority. SVCall must have execution
* priority in all cases.
*
* In the normal cases, interrupts are not nest-able and all interrupts run
* at an execution priority between NVIC_SYSH_PRIORITY_MIN and
* NVIC_SYSH_PRIORITY_MAX (with NVIC_SYSH_PRIORITY_MAX reserved for SVCall).
*
* If, in addition, CONFIG_ARCH_HIPRI_INTERRUPT is defined, then special
* high priority interrupts are supported. These are not "nested" in the
* normal sense of the word. These high priority interrupts can interrupt
* normal processing but execute outside of OS (although they can "get back
* into the game" via a PendSV interrupt).
*
* In the normal course of things, interrupts must occasionally be disabled
* using the irqsave() inline function to prevent contention in use of
* resources that may be shared between interrupt level and non-interrupt
* level logic. Now the question arises, if CONFIG_ARCH_HIPRI_INTERRUPT,
* do we disable all interrupts (except SVCall), or do we only disable the
* "normal" interrupts. Since the high priority interrupts cannot interact
* with the OS, you may want to permit the high priority interrupts even if
* interrupts are disabled. The setting CONFIG_ARCH_INT_DISABLEALL can be
* used to select either behavior:
*
* ----------------------------+--------------+----------------------------
* CONFIG_ARCH_HIPRI_INTERRUPT | NO | YES
* ----------------------------+--------------+--------------+-------------
* CONFIG_ARCH_INT_DISABLEALL | N/A | YES | NO
* ----------------------------+--------------+--------------+-------------
* | | | SVCall
* | SVCall | SVCall | HIGH
* Disable here and below --------> MAXNORMAL ---> HIGH --------> MAXNORMAL
* | | MAXNORMAL |
* ----------------------------+--------------+--------------+-------------
*/
#if defined(CONFIG_ARCH_HIPRI_INTERRUPT) && defined(CONFIG_ARCH_INT_DISABLEALL)
# define NVIC_SYSH_MAXNORMAL_PRIORITY (NVIC_SYSH_PRIORITY_MAX + 2*NVIC_SYSH_PRIORITY_STEP)
# define NVIC_SYSH_HIGH_PRIORITY (NVIC_SYSH_PRIORITY_MAX + NVIC_SYSH_PRIORITY_STEP)
# define NVIC_SYSH_DISABLE_PRIORITY NVIC_SYSH_HIGH_PRIORITY
# define NVIC_SYSH_SVCALL_PRIORITY NVIC_SYSH_PRIORITY_MAX
#else
# define NVIC_SYSH_MAXNORMAL_PRIORITY (NVIC_SYSH_PRIORITY_MAX + NVIC_SYSH_PRIORITY_STEP)
# define NVIC_SYSH_HIGH_PRIORITY NVIC_SYSH_PRIORITY_MAX
# define NVIC_SYSH_DISABLE_PRIORITY NVIC_SYSH_MAXNORMAL_PRIORITY
# define NVIC_SYSH_SVCALL_PRIORITY NVIC_SYSH_PRIORITY_MAX
#endif
/************************************************************************************
* Public Types
************************************************************************************/
/************************************************************************************
* Public Data
************************************************************************************/
/************************************************************************************
* Public Functions
************************************************************************************/
#endif /* __ARCH_ARM_INCLUDE_LPC43XX_CHIP_H */

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arch/arm/include/lpc43xx/irq.h
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@ -1,227 +0,0 @@
/********************************************************************************************
* arch/arm/include/lpc43xxx/irq.h
*
* Copyright (C) 2012 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
********************************************************************************************/
/* This file should never be included directed but, rather,
* only indirectly through nuttx/irq.h
*/
#ifndef __ARCH_ARM_INCLUDE_LPC43XX_IRQ_H
#define __ARCH_ARM_INCLUDE_LPC43XX_IRQ_H
/********************************************************************************************
* Included Files
********************************************************************************************/
#ifndef __ASSEMBLY__
# include <stdint.h>
#endif
/********************************************************************************************
* Pre-processor Definitions
********************************************************************************************/
/* IRQ numbers. The IRQ number corresponds vector number and hence map directly to bits in
* the NVIC. This does, however, waste several words of memory in the IRQ to handle mapping
* tables.
*/
/* Processor Exceptions (vectors 0-15) */
#define LPC43_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG) */
/* Vector 0: Reset stack pointer value */
/* Vector 1: Reset (not handler as an IRQ) */
#define LPC43_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */
#define LPC43_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */
#define LPC43_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */
#define LPC43_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */
#define LPC43_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */
#define LPC43_IRQ_SIGNVALUE (7) /* Vector 7: Sign value */
#define LPC43_IRQ_SVCALL (11) /* Vector 11: SVC call */
#define LPC43_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */
/* Vector 13: Reserved */
#define LPC43_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */
#define LPC43_IRQ_SYSTICK (15) /* Vector 15: System tick */
#define LPC43_IRQ_EXTINT (16) /* Vector 16: Vector number of the first external interrupt */
/* Cortex-M4 External interrupts (vectors >= 16) */
#define LPC43M4_IRQ_DAC (LPC43_IRQ_EXTINT+0) /* D/A */
#define LPC43M4_IRQ_M0CORE (LPC43_IRQ_EXTINT+1) /* M0 Core */
#define LPC43M4_IRQ_DMA (LPC43_IRQ_EXTINT+2) /* DMA */
#define LPC43M4_IRQ_FLASHEEPROM (LPC43_IRQ_EXTINT+4) /* EEPROM interrupts (BankA or BankB) */
#define LPC43M4_IRQ_ETHERNET (LPC43_IRQ_EXTINT+5) /* Ethernet interrupt */
#define LPC43M4_IRQ_SDIO (LPC43_IRQ_EXTINT+6) /* SD/MMC interrupt */
#define LPC43M4_IRQ_LCD (LPC43_IRQ_EXTINT+7) /* LCD */
#define LPC43M4_IRQ_USB0 (LPC43_IRQ_EXTINT+8) /* USB0 OTG interrupt */
#define LPC43M4_IRQ_USB1 (LPC43_IRQ_EXTINT+9) /* USB1 interrupt */
#define LPC43M4_IRQ_SCT (LPC43_IRQ_EXTINT+10) /* SCT combined interrupt */
#define LPC43M4_IRQ_RITIMER (LPC43_IRQ_EXTINT+11) /* RITIMER interrupt */
#define LPC43M4_IRQ_TIMER0 (LPC43_IRQ_EXTINT+12) /* TIMER0 interrupt */
#define LPC43M4_IRQ_TIMER1 (LPC43_IRQ_EXTINT+13) /* TIMER1 interrupt */
#define LPC43M4_IRQ_TIMER2 (LPC43_IRQ_EXTINT+14) /* TIMER2 interrupt */
#define LPC43M4_IRQ_TIMER3 (LPC43_IRQ_EXTINT+15) /* TIMER3 interrupt */
#define LPC43M4_IRQ_MCPWM (LPC43_IRQ_EXTINT+16) /* Motor control PWM interrupt */
#define LPC43M4_IRQ_ADC0 (LPC43_IRQ_EXTINT+17) /* ADC0 interrupt */
#define LPC43M4_IRQ_I2C0 (LPC43_IRQ_EXTINT+18) /* I2C0 interrupt */
#define LPC43M4_IRQ_I2C1 (LPC43_IRQ_EXTINT+19) /* I2C1 interrupt */
#define LPC43M4_IRQ_SPI (LPC43_IRQ_EXTINT+20) /* SPI interrupt */
#define LPC43M4_IRQ_ADC1 (LPC43_IRQ_EXTINT+21) /* ADC1 interrupt */
#define LPC43M4_IRQ_SSP0 (LPC43_IRQ_EXTINT+22) /* SSP0 interrupt */
#define LPC43M4_IRQ_SSP1 (LPC43_IRQ_EXTINT+23) /* SSP1 interrupt */
#define LPC43M4_IRQ_USART0 (LPC43_IRQ_EXTINT+24) /* USART0 interrupt */
#define LPC43M4_IRQ_UART1 (LPC43_IRQ_EXTINT+25) /* UART1/Modem interrupt */
#define LPC43M4_IRQ_USART2 (LPC43_IRQ_EXTINT+26) /* USART2 interrupt */
#define LPC43M4_IRQ_USART3 (LPC43_IRQ_EXTINT+27) /* USART3/IrDA interrupt */
#define LPC43M4_IRQ_I2S0 (LPC43_IRQ_EXTINT+28) /* I2S0 interrupt */
#define LPC43M4_IRQ_I2S1 (LPC43_IRQ_EXTINT+29) /* I2S1 interrupt */
#define LPC43M4_IRQ_SPIFI (LPC43_IRQ_EXTINT+30) /* SPIFI interrupt */
#define LPC43M4_IRQ_SGPIO (LPC43_IRQ_EXTINT+31) /* SGPIO interrupt */
#define LPC43M4_IRQ_PININT0 (LPC43_IRQ_EXTINT+32) /* GPIO pin interrupt 0 */
#define LPC43M4_IRQ_PININT1 (LPC43_IRQ_EXTINT+33) /* GPIO pin interrupt 1 */
#define LPC43M4_IRQ_PININT2 (LPC43_IRQ_EXTINT+34) /* GPIO pin interrupt 2 */
#define LPC43M4_IRQ_PININT3 (LPC43_IRQ_EXTINT+35) /* GPIO pin interrupt 3 */
#define LPC43M4_IRQ_PININT4 (LPC43_IRQ_EXTINT+36) /* GPIO pin interrupt 4 */
#define LPC43M4_IRQ_PININT5 (LPC43_IRQ_EXTINT+37) /* GPIO pin interrupt 5 */
#define LPC43M4_IRQ_PININT6 (LPC43_IRQ_EXTINT+38) /* GPIO pin interrupt 6 */
#define LPC43M4_IRQ_PININT7 (LPC43_IRQ_EXTINT+39) /* GPIO pin interrupt 7 */
#define LPC43M4_IRQ_GINT0 (LPC43_IRQ_EXTINT+40) /* GPIO group interrupt 0 */
#define LPC43M4_IRQ_GINT1 (LPC43_IRQ_EXTINT+41) /* GPIO group interrupt 1 */
#define LPC43M4_IRQ_EVENTROUTER (LPC43_IRQ_EXTINT+42) /* Event router interrupt */
#define LPC43M4_IRQ_CAN1 (LPC43_IRQ_EXTINT+43) /* C_CAN1 interrupt */
#define LPC43M4_IRQ_ATIMER (LPC43_IRQ_EXTINT+46) /* ATIMER Alarm timer interrupt */
#define LPC43M4_IRQ_RTC (LPC43_IRQ_EXTINT+47) /* RTC interrupt */
#define LPC43M4_IRQ_WWDT (LPC43_IRQ_EXTINT+49) /* WWDT interrupt */
#define LPC43M4_IRQ_CAN0 (LPC43_IRQ_EXTINT+51) /* C_CAN0 interrupt */
#define LPC43M4_IRQ_QEI (LPC43_IRQ_EXTINT+52) /* QEI interrupt */
#define LPC43M4_IRQ_NEXTINT (53)
#define LPC43M4_IRQ_NIRQS (LPC43_IRQ_EXTINT+LPC43M4_IRQ_NEXTINT)
/* Total number of IRQ numbers (This will need to be revisited if/when the Cortex-M0 is
* supported)
*/
#define NR_VECTORS LPC43M4_IRQ_NIRQS
#define NR_IRQS LPC43M4_IRQ_NIRQS
/* Cortex-M0 External interrupts (vectors >= 16) */
#define LPC43M0_IRQ_RTC (LPC43_IRQ_EXTINT+0) /* RT interrupt */
#define LPC43M0_IRQ_M4CORE (LPC43_IRQ_EXTINT+1) /* Interrupt from the M4 core */
#define LPC43M0_IRQ_DMA (LPC43_IRQ_EXTINT+2) /* DMA interrupt */
#define LPC43M0_IRQ_FLASHEEPROM (LPC43_IRQ_EXTINT+4) /* EEPROM (Bank A or B) | A Timer */
#define LPC43M0_IRQ_ATIMER (LPC43_IRQ_EXTINT+4) /* EEPROM (Bank A or B) | A Timer */
#define LPC43M0_IRQ_ETHERNET (LPC43_IRQ_EXTINT+5) /* Ethernet interrupt */
#define LPC43M0_IRQ_SDIO (LPC43_IRQ_EXTINT+6) /* SDIO interrupt */
#define LPC43M0_IRQ_LCD (LPC43_IRQ_EXTINT+7) /* LCD interrupt */
#define LPC43M0_IRQ_USB0 (LPC43_IRQ_EXTINT+8) /* USB0 OTG interrupt */
#define LPC43M0_IRQ_USB1 (LPC43_IRQ_EXTINT+9) /* USB1 interrupt */
#define LPC43M0_IRQ_SCT (LPC43_IRQ_EXTINT+10) /* SCT combined interrupt */
#define LPC43M0_IRQ_RITIMER (LPC43_IRQ_EXTINT+11) /* RI Timer | WWDT interrupt */
#define LPC43M0_IRQ_WWDT (LPC43_IRQ_EXTINT+11) /* RI Timer | WWDT interrupt */
#define LPC43M0_IRQ_TIMER0 (LPC43_IRQ_EXTINT+12) /* TIMER0 interrupt */
#define LPC43M0_IRQ_GINT1 (LPC43_IRQ_EXTINT+13) /* GINT1 GPIO global interrupt 1 */
#define LPC43M0_IRQ_PININT4 (LPC43_IRQ_EXTINT+14) /* GPIO pin interrupt 4 */
#define LPC43M0_IRQ_TIMER3 (LPC43_IRQ_EXTINT+15) /* TIMER interrupt */
#define LPC43M0_IRQ_MCPWM (LPC43_IRQ_EXTINT+16) /* Motor control PWM interrupt */
#define LPC43M0_IRQ_ADC0 (LPC43_IRQ_EXTINT+17) /* ADC0 interrupt */
#define LPC43M0_IRQ_I2C0 (LPC43_IRQ_EXTINT+18) /* I2C0 | I2C1 interrupt */
#define LPC43M0_IRQ_I2C1 (LPC43_IRQ_EXTINT+18) /* I2C0 | I2C1 interrupt */
#define LPC43M0_IRQ_SGPIO (LPC43_IRQ_EXTINT+19) /* SGPIO interrupt */
#define LPC43M0_IRQ_SPI (LPC43_IRQ_EXTINT+20) /* SPI | DAC interrupt */
#define LPC43M0_IRQ_DAC (LPC43_IRQ_EXTINT+20) /* SPI | DAC interrupt */
#define LPC43M0_IRQ_ADC1 (LPC43_IRQ_EXTINT+21) /* ADC1 interrupt */
#define LPC43M0_IRQ_SSP0 (LPC43_IRQ_EXTINT+22) /* SSP0 | SSP1 interrupt */
#define LPC43M0_IRQ_SSP1 (LPC43_IRQ_EXTINT+22) /* SSP0 | SSP1 interrupt */
#define LPC43M0_IRQ_EVENTROUTER (LPC43_IRQ_EXTINT+23) /* Event router interrupt */
#define LPC43M0_IRQ_USART0 (LPC43_IRQ_EXTINT+24) /* USART0 interrupt */
#define LPC43M0_IRQ_UART1 (LPC43_IRQ_EXTINT+25) /* UART1 Modem/UART1 interrupt */
#define LPC43M0_IRQ_USART2 (LPC43_IRQ_EXTINT+26) /* USART2 | C_CAN1 interrupt */
#define LPC43M0_IRQ_CAN1 (LPC43_IRQ_EXTINT+26) /* USART2 | C_CAN1 interrupt */
#define LPC43M0_IRQ_USART3 (LPC43_IRQ_EXTINT+27) /* USART3 interrupt */
#define LPC43M0_IRQ_I2S0 (LPC43_IRQ_EXTINT+28) /* I2S0 | I2S1 | QEI interrupt */
#define LPC43M0_IRQ_I2S1 (LPC43_IRQ_EXTINT+28) /* I2S0 | I2S1 | QEI interrupt */
#define LPC43M0_IRQ_QEI (LPC43_IRQ_EXTINT+28) /* I2S0 | I2S1 | QEI interrupt */
#define LPC43M0_IRQ_CAN0 (LPC43_IRQ_EXTINT+29) /* C_CAN0 interrupt */
#define LPC43M0_IRQ_NEXTINT (30)
#define LPC43M0_IRQ_NIRQS (LPC43_IRQ_EXTINT+LPC43M0_IRQ_NEXTINT)
/* Total number of IRQ numbers (This will need to be revisited if/when the Cortex-M0 is
* supported)
*/
#if 0
#define NR_VECTORS LPC43M0_IRQ_NIRQS
#define NR_IRQS LPC43M0_IRQ_NIRQS
#endif
/********************************************************************************************
* Public Types
********************************************************************************************/
#ifndef __ASSEMBLY__
typedef void (*vic_vector_t)(uint32_t *regs);
#endif
/********************************************************************************************
* Inline functions
********************************************************************************************/
/********************************************************************************************
* Public Variables
********************************************************************************************/
/********************************************************************************************
* Public Function Prototypes
********************************************************************************************/
#ifndef __ASSEMBLY__
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif
#endif /* __ARCH_ARM_INCLUDE_LPC43XX_IRQ_H */

677
arch/arm/include/nuc1xx/chip.h
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@ -1,677 +0,0 @@
/************************************************************************************
* arch/arm/include/nuc1xx/chip.h
*
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_INCLUDE_NUC1XX_CHIP_H
#define __ARCH_ARM_INCLUDE_NUC1XX_CHIP_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Chip capabilities ****************************************************************/
/* NUC100 Advanced Line (Low Density) */
#if defined(CONFIG_ARCH_CHIP_NUC100LC1BN) /* Flash 32K SRAM 4K, LQFP48 package */
# define NUC100 1 /* NUC100 family */
# undef NUC120 /* NUC120 family */
# define NUC_LOW 1 /* Low density part */
# undef NUC_MEDIUM /* Medium density part */
# define NUC_FLASH (32*1024) /* 32K FLASH */
# define NUC_SRAM (4*1024) /* 4K SRAM */
# define NUC_NIO 35 /* (35) GPIO */
# define NUC_NTIMERS 4 /* 4x32-bit Timers */
# define NUC_NPDMA 1 /* 1 PDMA channels */
# define NUC_NUARTS 2 /* (2) UARTs */
# define NUC_NSPI 1 /* (1) SPI */
# define NUC_NI2C 2 /* (2) I2C */
# define NUC_NUSB 0 /* No USB */
# define NUC_NLIN 0 /* No LIN */
# define NUC_NCAN 0 /* No CAN */
# define NUC_NI2S 1 /* (1) I2S */
# define NUC_NCOMP 1 /* (1) Analog Comparator */
# define NUC_NPWM 4 /* (4) PWM */
# define NUC_NADC 8 /* 8x12-bit ADC */
# define NUC_RTC 1 /* RTC */
# undef NUC_EBI /* No EBI */
#elif defined(CONFIG_ARCH_CHIP_NUC100LD1BN) /* Flash 64K SRAM 4K, LQFP48 package */
# define NUC100 1 /* NUC100 family */
# undef NUC120 /* NUC120 family */
# define NUC_LOW 1 /* Low density part */
# undef NUC_MEDIUM /* Medium density part */
# define NUC_FLASH (64*1024) /* 64K FLASH */
# define NUC_SRAM (4*1024) /* 4K SRAM */
# define NUC_NIO 31 /* (35) GPIO */
# define NUC_NTIMERS 4 /* 4x32-bit Timers */
# define NUC_NPDMA 1 /* 1 PDMA channels */
# define NUC_NUARTS 2 /* (2) UARTs */
# define NUC_NSPI 1 /* (1) SPI */
# define NUC_NI2C 2 /* (2) I2C */
# define NUC_NUSB 0 /* No USB */
# define NUC_NLIN 0 /* No LIN */
# define NUC_NCAN 0 /* No CAN */
# define NUC_NI2S 1 /* (1) I2S */
# define NUC_NCOMP 1 /* (1) Analog Comparator */
# define NUC_NPWM 4 /* (4) PWM */
# define NUC_NADC 8 /* 8x12-bit ADC */
# define NUC_RTC 1 /* RTC */
# undef NUC_EBI /* No EBI */
#elif defined(CONFIG_ARCH_CHIP_NUC100LD2BN) /* Flash 64K SRAM 8K, LQFP48 package */
# define NUC100 1 /* NUC100 family */
# undef NUC120 /* NUC120 family */
# define NUC_LOW 1 /* Low density part */
# undef NUC_MEDIUM /* Medium density part */
# define NUC_FLASH (64*1024) /* 64K FLASH */
# define NUC_SRAM (8*1024) /* 8K SRAM */
# define NUC_NIO 31 /* (35) GPIO */
# define NUC_NTIMERS 4 /* 4x32-bit Timers */
# define NUC_NPDMA 1 /* 1 PDMA channels */
# define NUC_NUARTS 2 /* (2) UARTs */
# define NUC_NSPI 1 /* (1) SPI */
# define NUC_NI2C 2 /* (2) I2C */
# define NUC_NUSB 0 /* No USB */
# define NUC_NLIN 0 /* No LIN */
# define NUC_NCAN 0 /* No CAN */
# define NUC_NI2S 1 /* (1) I2S */
# define NUC_NCOMP 1 /* (1) Analog Comparator */
# define NUC_NPWM 4 /* (4) PWM */
# define NUC_NADC 8 /* 8x12-bit ADC */
# define NUC_RTC 1 /* RTC */
# undef NUC_EBI /* No EBI */
#elif defined(CONFIG_ARCH_CHIP_NUC100RC1BN) /* Flash 32K SRAM 4K, LQFP64 package */
# define NUC100 1 /* NUC100 family */
# undef NUC120 /* NUC120 family */
# define NUC_LOW 1 /* Low density part */
# undef NUC_MEDIUM /* Medium density part */
# define NUC_FLASH (32*1024) /* 32K FLASH */
# define NUC_SRAM (4*1024) /* 4K SRAM */
# define NUC_NIO 49 /* (49) GPIO */
# define NUC_NTIMERS 4 /* 4x32-bit Timers */
# define NUC_NPDMA 1 /* 1 PDMA channels */
# define NUC_NUARTS 2 /* (2) UARTs */
# define NUC_NSPI 2 /* (2) SPI */
# define NUC_NI2C 2 /* (2) I2C */
# define NUC_NUSB 0 /* No USB */
# define NUC_NLIN 0 /* No LIN */
# define NUC_NCAN 0 /* No CAN */
# define NUC_NI2S 1 /* (1) I2S */
# define NUC_NCOMP 2 /* (2) Analog Comparators */
# define NUC_NPWM 4 /* (4) PWM */
# define NUC_NADC 8 /* 8x12-bit ADC */
# define NUC_RTC 1 /* RTC */
# define NUC_EBI 1 /* Supports EBI */
#elif defined(CONFIG_ARCH_CHIP_NUC100RD1BN) /* Flash 64K SRAM 4K, LQFP64 package */
# define NUC100 1 /* NUC100 family */
# undef NUC120 /* NUC120 family */
# define NUC_LOW 1 /* Low density part */
# undef NUC_MEDIUM /* Medium density part */
# define NUC_FLASH (64*1024) /* 64K FLASH */
# define NUC_SRAM (4*1024) /* 4K SRAM */
# define NUC_NIO 49 /* (49) GPIO */
# define NUC_NTIMERS 4 /* 4x32-bit Timers */
# define NUC_NPDMA 1 /* 1 PDMA channels */
# define NUC_NUARTS 2 /* (2) UARTs */
# define NUC_NSPI 2 /* (2) SPI */
# define NUC_NI2C 2 /* (2) I2C */
# define NUC_NUSB 0 /* No USB */
# define NUC_NLIN 0 /* No LIN */
# define NUC_NCAN 0 /* No CAN */
# define NUC_NI2S 1 /* (1) I2S */
# define NUC_NCOMP 2 /* (2) Analog Comparators */
# define NUC_NPWM 4 /* (4) PWM */
# define NUC_NADC 8 /* 8x12-bit ADC */
# define NUC_RTC 1 /* RTC */
# define NUC_EBI 1 /* Supports EBI */
#elif defined(CONFIG_ARCH_CHIP_NUC100RD2BN) /* Flash 64K SRAM 8K, LQFP64 package */
# define NUC100 1 /* NUC100 family */
# undef NUC120 /* NUC120 family */
# define NUC_LOW 1 /* Low density part */
# undef NUC_MEDIUM /* Medium density part */
# define NUC_FLASH (64*1024) /* 64K FLASH */
# define NUC_SRAM (8*1024) /* 4K SRAM */
# define NUC_NIO 49 /* (49) GPIO */
# define NUC_NTIMERS 4 /* 4x32-bit Timers */
# define NUC_NPDMA 1 /* 1 PDMA channels */
# define NUC_NUARTS 2 /* (2) UARTs */
# define NUC_NSPI 2 /* (2) SPI */
# define NUC_NI2C 2 /* (2) I2C */
# define NUC_NUSB 0 /* No USB */
# define NUC_NLIN 0 /* No LIN */
# define NUC_NCAN 0 /* No CAN */
# define NUC_NI2S 1 /* (1) I2S */
# define NUC_NCOMP 2 /* (2) Analog Comparators */
# define NUC_NPWM 4 /* (4) PWM */
# define NUC_NADC 8 /* 8x12-bit ADC */
# define NUC_RTC 1 /* RTC */
# define NUC_EBI 1 /* Supports EBI */
/* NUC100 Advanced Line (Medium Density) */
#elif defined(CONFIG_ARCH_CHIP_NUC100LD3AN) /* Flash 64K SRAM 16K, LQFP48 package */
# define NUC100 1 /* NUC100 family */
# undef NUC120 /* NUC120 family */
# undef NUC_LOW /* Low density part */
# define NUC_MEDIUM 1 /* Medium density part */
# define NUC_FLASH (64*1024) /* 64K FLASH */
# define NUC_SRAM (16*1024) /* 16K SRAM */
# define NUC_NIO 35 /* (35) GPIO */
# define NUC_NTIMERS 4 /* 4x32-bit Timers */
# define NUC_NPDMA 9 /* 9 PDMA channels */
# define NUC_NUARTS 2 /* (2) UARTs */
# define NUC_NSPI 1 /* (1) SPI */
# define NUC_NI2C 2 /* (2) I2C */
# define NUC_NUSB 0 /* No USB */
# define NUC_NLIN 0 /* No LIN */
# define NUC_NCAN 0 /* No CAN */
# define NUC_NI2S 1 /* (1) I2S */
# define NUC_NCOMP 1 /* (1) Analog Comparator */
# define NUC_NPWM 6 /* (6) PWM */
# define NUC_NADC 8 /* 8x12-bit ADC */
# define NUC_RTC 1 /* RTC */
# undef NUC_EBI /* No EBI */
#elif defined(CONFIG_ARCH_CHIP_NUC100LE3AN) /* Flash 128K SRAM 16K, LQFP48 package */
# define NUC100 1 /* NUC100 family */
# undef NUC120 /* NUC120 family */
# undef NUC_LOW /* Low density part */
# define NUC_MEDIUM 1 /* Medium density part */
# define NUC_FLASH (128*1024) /* 64K FLASH */
# define NUC_SRAM (16*1024) /* 16K SRAM */
# define NUC_NIO 35 /* (35) GPIO */
# define NUC_NTIMERS 4 /* 4x32-bit Timers */
# define NUC_NPDMA 9 /* 9 PDMA channels */
# define NUC_NUARTS 2 /* (2) UARTs */
# define NUC_NSPI 1 /* (1) SPI */
# define NUC_NI2C 2 /* (2) I2C */
# define NUC_NUSB 0 /* No USB */
# define NUC_NLIN 0 /* No LIN */
# define NUC_NCAN 0 /* No CAN */
# define NUC_NI2S 1 /* (1) I2S */
# define NUC_NCOMP 1 /* (1) Analog Comparator */
# define NUC_NPWM 6 /* (6) PWM */
# define NUC_NADC 8 /* 8x12-bit ADC */
# define NUC_RTC 1 /* RTC */
# undef NUC_EBI /* No EBI */
#elif defined(CONFIG_ARCH_CHIP_NUC100RD3AN) /* Flash 64K SRAM 16K, LQFP64 package */
# define NUC100 1 /* NUC100 family */
# undef NUC120 /* NUC120 family */
# undef NUC_LOW /* Low density part */
# define NUC_MEDIUM 1 /* Medium density part */
# define NUC_FLASH (64*1024) /* 64K FLASH */
# define NUC_SRAM (16*1024) /* 16K SRAM */
# define NUC_NIO 49 /* (49) GPIO */
# define NUC_NTIMERS 4 /* 4x32-bit Timers */
# define NUC_NPDMA 9 /* 9 PDMA channels */
# define NUC_NUARTS 3 /* (3) UARTs */
# define NUC_NSPI 2 /* (2) SPI */
# define NUC_NI2C 2 /* (2) I2C */
# define NUC_NUSB 0 /* No USB */
# define NUC_NLIN 0 /* No LIN */
# define NUC_NCAN 0 /* No CAN */
# define NUC_NI2S 1 /* (1) I2S */
# define NUC_NCOMP 2 /* (2) Analog Comparator */
# define NUC_NPWM 6 /* (6) PWM */
# define NUC_NADC 8 /* 8x12-bit ADC */
# define NUC_RTC 1 /* RTC */
# undef NUC_EBI /* No EBI */
#elif defined(CONFIG_ARCH_CHIP_NUC100RE3AN) /* Flash 128K SRAM 16K, LQFP64 package */
# define NUC100 1 /* NUC100 family */
# undef NUC120 /* NUC120 family */
# undef NUC_LOW /* Low density part */
# define NUC_MEDIUM 1 /* Medium density part */
# define NUC_FLASH (128*1024) /* 128K FLASH */
# define NUC_SRAM (16*1024) /* 16K SRAM */
# define NUC_NIO 49 /* (49) GPIO */
# define NUC_NTIMERS 4 /* 4x32-bit Timers */
# define NUC_NPDMA 9 /* 9 PDMA channels */
# define NUC_NUARTS 3 /* (3) UARTs */
# define NUC_NSPI 2 /* (2) SPI */
# define NUC_NI2C 2 /* (2) I2C */
# define NUC_NUSB 0 /* No USB */
# define NUC_NLIN 0 /* No LIN */
# define NUC_NCAN 0 /* No CAN */
# define NUC_NI2S 1 /* (1) I2S */
# define NUC_NCOMP 2 /* (2) Analog Comparator */
# define NUC_NPWM 6 /* (6) PWM */
# define NUC_NADC 8 /* 8x12-bit ADC */
# define NUC_RTC 1 /* RTC */
# undef NUC_EBI /* No EBI */
#elif defined(CONFIG_ARCH_CHIP_NUC100VD2AN) /* Flash 64K SRAM 8K, LQFP100 package */
# define NUC100 1 /* NUC100 family */
# undef NUC120 /* NUC120 family */
# undef NUC_LOW /* Low density part */
# define NUC_MEDIUM 1 /* Medium density part */
# define NUC_FLASH (64*1024) /* 64K FLASH */
# define NUC_SRAM (8*1024) /* 8K SRAM */
# define NUC_NIO 80 /* (80) GPIO */
# define NUC_NTIMERS 4 /* 4x32-bit Timers */
# define NUC_NPDMA 9 /* 9 PDMA channels */
# define NUC_NUARTS 3 /* (3) UARTs */
# define NUC_NSPI 4 /* (4) SPI */
# define NUC_NI2C 2 /* (2) I2C */
# define NUC_NUSB 0 /* No USB */
# define NUC_NLIN 0 /* No LIN */
# define NUC_NCAN 0 /* No CAN */
# define NUC_NI2S 1 /* (1) I2S */
# define NUC_NCOMP 2 /* (2) Analog Comparator */
# define NUC_NPWM 8 /* (8) PWM */
# define NUC_NADC 8 /* 8x12-bit ADC */
# define NUC_RTC 1 /* RTC */
# undef NUC_EBI /* No EBI */
#elif defined(CONFIG_ARCH_CHIP_NUC100VD3AN) /* Flash 64K SRAM 16K, LQFP100 package */
# define NUC100 1 /* NUC100 family */
# undef NUC120 /* NUC120 family */
# undef NUC_LOW /* Low density part */
# define NUC_MEDIUM 1 /* Medium density part */
# define NUC_FLASH (64*1024) /* 64K FLASH */
# define NUC_SRAM (16*1024) /* 16K SRAM */
# define NUC_NIO 80 /* (80) GPIO */
# define NUC_NTIMERS 4 /* 4x32-bit Timers */
# define NUC_NPDMA 9 /* 9 PDMA channels */
# define NUC_NUARTS 3 /* (3) UARTs */
# define NUC_NSPI 4 /* (4) SPI */
# define NUC_NI2C 2 /* (2) I2C */
# define NUC_NUSB 0 /* No USB */
# define NUC_NLIN 0 /* No LIN */
# define NUC_NCAN 0 /* No CAN */
# define NUC_NI2S 1 /* (1) I2S */
# define NUC_NCOMP 2 /* (2) Analog Comparator */
# define NUC_NPWM 8 /* (8) PWM */
# define NUC_NADC 8 /* 8x12-bit ADC */
# define NUC_RTC 1 /* RTC */
# undef NUC_EBI /* No EBI */
#elif defined(CONFIG_ARCH_CHIP_NUC100VE3AN) /* Flash 128K SRAM 8K, LQFP100 package */
# define NUC100 1 /* NUC100 family */
# undef NUC120 /* NUC120 family */
# undef NUC_LOW /* Low density part */
# define NUC_MEDIUM 1 /* Medium density part */
# define NUC_FLASH (128*1024) /* 128K FLASH */
# define NUC_SRAM (16*1024) /* 16K SRAM */
# define NUC_NIO 80 /* (80) GPIO */
# define NUC_NTIMERS 4 /* 4x32-bit Timers */
# define NUC_NPDMA 9 /* 9 PDMA channels */
# define NUC_NUARTS 3 /* (3) UARTs */
# define NUC_NSPI 4 /* (4) SPI */
# define NUC_NI2C 2 /* (2) I2C */
# define NUC_NUSB 0 /* No USB */
# define NUC_NLIN 0 /* No LIN */
# define NUC_NCAN 0 /* No CAN */
# define NUC_NI2S 1 /* (1) I2S */
# define NUC_NCOMP 2 /* (2) Analog Comparator */
# define NUC_NPWM 8 /* (8) PWM */
# define NUC_NADC 8 /* 8x12-bit ADC */
# define NUC_RTC 1 /* RTC */
# undef NUC_EBI /* No EBI */
/* NUC120 USB Line (Low Density) */
#elif defined(CONFIG_ARCH_CHIP_NUC120LC1BN) /* Flash 32K SRAM 4K, LQFP48 package */
# undef NUC100 /* NUC100 family */
# define NUC120 1 /* NUC120 family */
# define NUC_LOW 1 /* Low density part */
# undef NUC_MEDIUM /* Medium density part */
# define NUC_FLASH (32*1024) /* 32K FLASH */
# define NUC_SRAM (4*1024) /* 4K SRAM */
# define NUC_NIO 31 /* (31) GPIO */
# define NUC_NTIMERS 4 /* 4x32-bit Timers */
# define NUC_NPDMA 1 /* 1 PDMA channels */
# define NUC_NUARTS 2 /* (2) UARTs */
# define NUC_NSPI 1 /* (1) SPI */
# define NUC_NI2C 2 /* (2) I2C */
# define NUC_NUSB 1 /* (1) USB 2.0 full speed */
# define NUC_NLIN 0 /* No LIN */
# define NUC_NCAN 0 /* No CAN */
# define NUC_NI2S 1 /* (1) I2S */
# define NUC_NCOMP 1 /* (1) Analog Comparator */
# define NUC_NPWM 4 /* (4) PWM */
# define NUC_NADC 8 /* 8x12-bit ADC */
# define NUC_RTC 1 /* RTC */
# undef NUC_EBI /* No EBI */
#elif defined(CONFIG_ARCH_CHIP_NUC120LD1BN) /* Flash 64K SRAM 4K, LQFP48 package */
# undef NUC100 /* NUC100 family */
# define NUC120 1 /* NUC120 family */
# define NUC_LOW 1 /* Low density part */
# undef NUC_MEDIUM /* Medium density part */
# define NUC_FLASH (64*1024) /* 64K FLASH */
# define NUC_SRAM (4*1024) /* 4K SRAM */
# define NUC_NIO 31 /* (31) GPIO */
# define NUC_NTIMERS 4 /* 4x32-bit Timers */
# define NUC_NPDMA 1 /* 1 PDMA channels */
# define NUC_NUARTS 2 /* (2) UARTs */
# define NUC_NSPI 1 /* (1) SPI */
# define NUC_NI2C 2 /* (2) I2C */
# define NUC_NUSB 1 /* (1) USB 2.0 full speed */
# define NUC_NLIN 0 /* No LIN */
# define NUC_NCAN 0 /* No CAN */
# define NUC_NI2S 1 /* (1) I2S */
# define NUC_NCOMP 1 /* (1) Analog Comparator */
# define NUC_NPWM 4 /* (4) PWM */
# define NUC_NADC 8 /* 8x12-bit ADC */
# define NUC_RTC 1 /* RTC */
# undef NUC_EBI /* No EBI */
#elif defined(CONFIG_ARCH_CHIP_NUC120LD2BN) /* Flash 64K SRAM 8K, LQFP48 package */
# undef NUC100 /* NUC100 family */
# define NUC120 1 /* NUC120 family */
# define NUC_LOW 1 /* Low density part */
# undef NUC_MEDIUM /* Medium density part */
# define NUC_FLASH (64*1024) /* 64K FLASH */
# define NUC_SRAM (8*1024) /* 8K SRAM */
# define NUC_NIO 31 /* (31) GPIO */
# define NUC_NTIMERS 4 /* 4x32-bit Timers */
# define NUC_NPDMA 1 /* 1 PDMA channels */
# define NUC_NUARTS 2 /* (2) UARTs */
# define NUC_NSPI 1 /* (1) SPI */
# define NUC_NI2C 2 /* (2) I2C */
# define NUC_NUSB 1 /* (1) USB 2.0 full speed */
# define NUC_NLIN 0 /* No LIN */
# define NUC_NCAN 0 /* No CAN */
# define NUC_NI2S 1 /* (1) I2S */
# define NUC_NCOMP 1 /* (1) Analog Comparator */
# define NUC_NPWM 4 /* (4) PWM */
# define NUC_NADC 8 /* 8x12-bit ADC */
# define NUC_RTC 1 /* RTC */
# undef NUC_EBI /* No EBI */
#elif defined(CONFIG_ARCH_CHIP_NUC120RC1BN) /* Flash 32K SRAM 4K, LQFP64 package */
# undef NUC100 /* NUC100 family */
# define NUC120 1 /* NUC120 family */
# define NUC_LOW 1 /* Low density part */
# undef NUC_MEDIUM /* Medium density part */
# define NUC_FLASH (32*1024) /* 32K FLASH */
# define NUC_SRAM (4*1024) /* 4K SRAM */
# define NUC_NIO 45 /* (45) GPIO */
# define NUC_NTIMERS 4 /* 4x32-bit Timers */
# define NUC_NPDMA 1 /* 1 PDMA channels */
# define NUC_NUARTS 2 /* (2) UARTs */
# define NUC_NSPI 2 /* (2) SPI */
# define NUC_NI2C 2 /* (2) I2C */
# define NUC_NUSB 1 /* (1) USB 2.0 full speed */
# define NUC_NLIN 0 /* No LIN */
# define NUC_NCAN 0 /* No CAN */
# define NUC_NI2S 1 /* (1) I2S */
# define NUC_NCOMP 2 /* (2) Analog Comparators */
# define NUC_NPWM 4 /* (4) PWM */
# define NUC_NADC 8 /* 8x12-bit ADC */
# define NUC_RTC 1 /* RTC */
# define NUC_EBI 1 /* Have EBI */
#elif defined(CONFIG_ARCH_CHIP_NUC120RD1BN) /* Flash 64K SRAM 4K, LQFP64 package */
# undef NUC100 /* NUC100 family */
# define NUC120 1 /* NUC120 family */
# define NUC_LOW 1 /* Low density part */
# undef NUC_MEDIUM /* Medium density part */
# define NUC_FLASH (64*1024) /* 64K FLASH */
# define NUC_SRAM (4*1024) /* 4K SRAM */
# define NUC_NIO 45 /* (45) GPIO */
# define NUC_NTIMERS 4 /* 4x32-bit Timers */
# define NUC_NPDMA 1 /* 1 PDMA channels */
# define NUC_NUARTS 2 /* (2) UARTs */
# define NUC_NSPI 2 /* (2) SPI */
# define NUC_NI2C 2 /* (2) I2C */
# define NUC_NUSB 1 /* (1) USB 2.0 full speed */
# define NUC_NLIN 0 /* No LIN */
# define NUC_NCAN 0 /* No CAN */
# define NUC_NI2S 1 /* (1) I2S */
# define NUC_NCOMP 2 /* (2) Analog Comparators */
# define NUC_NPWM 4 /* (4) PWM */
# define NUC_NADC 8 /* 8x12-bit ADC */
# define NUC_RTC 1 /* RTC */
# define NUC_EBI 1 /* Have EBI */
#elif defined(CONFIG_ARCH_CHIP_NUC120RD2BN) /* Flash 64K SRAM 8K, LQFP64 package */
# undef NUC100 /* NUC100 family */
# define NUC120 1 /* NUC120 family */
# define NUC_LOW 1 /* Low density part */
# undef NUC_MEDIUM /* Medium density part */
# define NUC_FLASH (64*1024) /* 64K FLASH */
# define NUC_SRAM (8*1024) /* 8K SRAM */
# define NUC_NIO 45 /* (45) GPIO */
# define NUC_NTIMERS 4 /* 4x32-bit Timers */
# define NUC_NPDMA 1 /* 1 PDMA channels */
# define NUC_NUARTS 2 /* (2) UARTs */
# define NUC_NSPI 2 /* (2) SPI */
# define NUC_NI2C 2 /* (2) I2C */
# define NUC_NUSB 1 /* (1) USB 2.0 full speed */
# define NUC_NLIN 0 /* No LIN */
# define NUC_NCAN 0 /* No CAN */
# define NUC_NI2S 1 /* (1) I2S */
# define NUC_NCOMP 2 /* (2) Analog Comparators */
# define NUC_NPWM 4 /* (4) PWM */
# define NUC_NADC 8 /* 8x12-bit ADC */
# define NUC_RTC 1 /* RTC */
# define NUC_EBI 1 /* Have EBI */
/* NUC120 USB Line (Medium Density) */
#elif defined(CONFIG_ARCH_CHIP_NUC120LD3AN) /* Flash 64K SRAM 16K, LQFP48 package */
# undef NUC100 /* NUC100 family */
# define NUC120 1 /* NUC120 family */
# undef NUC_LOW /* Low density part */
# define NUC_MEDIUM 1 /* Medium density part */
# define NUC_FLASH (64*1024) /* 64K FLASH */
# define NUC_SRAM (16*1024) /* 16K SRAM */
# define NUC_NIO 31 /* (31) GPIO */
# define NUC_NTIMERS 4 /* 4x32-bit Timers */
# define NUC_NPDMA 9 /* 9 PDMA channels */
# define NUC_NUARTS 2 /* (2) UARTs */
# define NUC_NSPI 1 /* (1) SPI */
# define NUC_NI2C 2 /* (2) I2C */
# define NUC_NUSB 1 /* (1) USB 2.0 full speed */
# define NUC_NLIN 0 /* No LIN */
# define NUC_NCAN 0 /* No CAN */
# define NUC_NI2S 1 /* (1) I2S */
# define NUC_NCOMP 1 /* (1) Analog Comparator */
# define NUC_NPWM 4 /* (4) PWM */
# define NUC_NADC 8 /* 8x12-bit ADC */
# define NUC_RTC 1 /* RTC */
# undef NUC_EBI /* No EBI */
#elif defined(CONFIG_ARCH_CHIP_NUC120LE3AN) /* Flash 128K SRAM 16K, LQFP48 package */
# undef NUC100 /* NUC100 family */
# define NUC120 1 /* NUC120 family */
# undef NUC_LOW /* Low density part */
# define NUC_MEDIUM 1 /* Medium density part */
# define NUC_FLASH (128*1024) /* 128K FLASH */
# define NUC_SRAM (16*1024) /* 16K SRAM */
# define NUC_NIO 31 /* (31) GPIO */
# define NUC_NTIMERS 4 /* 4x32-bit Timers */
# define NUC_NPDMA 9 /* 9 PDMA channels */
# define NUC_NUARTS 2 /* (2) UARTs */
# define NUC_NSPI 1 /* (1) SPI */
# define NUC_NI2C 2 /* (2) I2C */
# define NUC_NUSB 1 /* (1) USB 2.0 full speed */
# define NUC_NLIN 0 /* No LIN */
# define NUC_NCAN 0 /* No CAN */
# define NUC_NI2S 1 /* (1) I2S */
# define NUC_NCOMP 1 /* (1) Analog Comparator */
# define NUC_NPWM 4 /* (4) PWM */
# define NUC_NADC 8 /* 8x12-bit ADC */
# define NUC_RTC 1 /* RTC */
# undef NUC_EBI /* No EBI */
#elif defined(CONFIG_ARCH_CHIP_NUC120RD3AN) /* Flash 64K SRAM 16K, LQFP64 package */
# undef NUC100 /* NUC100 family */
# define NUC120 1 /* NUC120 family */
# undef NUC_LOW /* Low density part */
# define NUC_MEDIUM 1 /* Medium density part */
# define NUC_FLASH (64*1024) /* 64K FLASH */
# define NUC_SRAM (16*1024) /* 16K SRAM */
# define NUC_NIO 45 /* (45) GPIO */
# define NUC_NTIMERS 4 /* 4x32-bit Timers */
# define NUC_NPDMA 9 /* 9 PDMA channels */
# define NUC_NUARTS 2 /* (2) UARTs */
# define NUC_NSPI 2 /* (2) SPI */
# define NUC_NI2C 2 /* (2) I2C */
# define NUC_NUSB 1 /* (1) USB 2.0 full speed */
# define NUC_NLIN 0 /* No LIN */
# define NUC_NCAN 0 /* No CAN */
# define NUC_NI2S 1 /* (1) I2S */
# define NUC_NCOMP 2 /* (2) Analog Comparators */
# define NUC_NPWM 6 /* (6) PWM */
# define NUC_NADC 8 /* 8x12-bit ADC */
# define NUC_RTC 1 /* RTC */
# undef NUC_EBI /* No EBI */
#elif defined(CONFIG_ARCH_CHIP_NUC120RE3AN) /* Flash 128K SRAM 16K, LQFP64 package */
# undef NUC100 /* NUC100 family */
# define NUC120 1 /* NUC120 family */
# undef NUC_LOW /* Low density part */
# define NUC_MEDIUM 1 /* Medium density part */
# define NUC_FLASH (128*1024) /* 128K FLASH */
# define NUC_SRAM (16*1024) /* 16K SRAM */
# define NUC_NIO 45 /* (45) GPIO */
# define NUC_NTIMERS 4 /* 4x32-bit Timers */
# define NUC_NPDMA 9 /* 9 PDMA channels */
# define NUC_NUARTS 2 /* (2) UARTs */
# define NUC_NSPI 2 /* (2) SPI */
# define NUC_NI2C 2 /* (2) I2C */
# define NUC_NUSB 1 /* (1) USB 2.0 full speed */
# define NUC_NLIN 0 /* No LIN */
# define NUC_NCAN 0 /* No CAN */
# define NUC_NI2S 1 /* (1) I2S */
# define NUC_NCOMP 2 /* (2) Analog Comparators */
# define NUC_NPWM 6 /* (6) PWM */
# define NUC_NADC 8 /* 8x12-bit ADC */
# define NUC_RTC 1 /* RTC */
# undef NUC_EBI /* No EBI */
#elif defined(CONFIG_ARCH_CHIP_NUC120VD2AN) /* Flash 64K SRAM 8K, LQFP100 package */
# undef NUC100 /* NUC100 family */
# define NUC120 1 /* NUC120 family */
# undef NUC_LOW /* Low density part */
# define NUC_MEDIUM 1 /* Medium density part */
# define NUC_FLASH (64*1024) /* 64K FLASH */
# define NUC_SRAM (8*1024) /* 8K SRAM */
# define NUC_NIO 76 /* (76) GPIO */
# define NUC_NTIMERS 4 /* 4x32-bit Timers */
# define NUC_NPDMA 9 /* 9 PDMA channels */
# define NUC_NUARTS 3 /* (3) UARTs */
# define NUC_NSPI 4 /* (4) SPI */
# define NUC_NI2C 2 /* (2) I2C */
# define NUC_NUSB 1 /* (1) USB 2.0 full speed */
# define NUC_NLIN 0 /* No LIN */
# define NUC_NCAN 0 /* No CAN */
# define NUC_NI2S 1 /* (1) I2S */
# define NUC_NCOMP 2 /* (2) Analog Comparators */
# define NUC_NPWM 8 /* (8) PWM */
# define NUC_NADC 8 /* 8x12-bit ADC */
# define NUC_RTC 1 /* RTC */
# undef NUC_EBI /* No EBI */
#elif defined(CONFIG_ARCH_CHIP_NUC120VD3AN) /* Flash 64K SRAM 16K, LQFP100 package */
# undef NUC100 /* NUC100 family */
# define NUC120 1 /* NUC120 family */
# undef NUC_LOW /* Low density part */
# define NUC_MEDIUM 1 /* Medium density part */
# define NUC_FLASH (64*1024) /* 64K FLASH */
# define NUC_SRAM (16*1024) /* 16K SRAM */
# define NUC_NIO 76 /* (76) GPIO */
# define NUC_NTIMERS 4 /* 4x32-bit Timers */
# define NUC_NPDMA 9 /* 9 PDMA channels */
# define NUC_NUARTS 3 /* (3) UARTs */
# define NUC_NSPI 4 /* (4) SPI */
# define NUC_NI2C 2 /* (2) I2C */
# define NUC_NUSB 1 /* (1) USB 2.0 full speed */
# define NUC_NLIN 0 /* No LIN */
# define NUC_NCAN 0 /* No CAN */
# define NUC_NI2S 1 /* (1) I2S */
# define NUC_NCOMP 2 /* (2) Analog Comparators */
# define NUC_NPWM 8 /* (8) PWM */
# define NUC_NADC 8 /* 8x12-bit ADC */
# define NUC_RTC 1 /* RTC */
# undef NUC_EBI /* No EBI */
#elif defined(CONFIG_ARCH_CHIP_NUC120VE3AN) /* Flash 128K SRAM 16K, LQFP100 package */
# undef NUC100 /* NUC100 family */
# define NUC120 1 /* NUC120 family */
# undef NUC_LOW /* Low density part */
# define NUC_MEDIUM 1 /* Medium density part */
# define NUC_FLASH (128*1024) /* 128K FLASH */
# define NUC_SRAM (16*1024) /* 16K SRAM */
# define NUC_NIO 76 /* (76) GPIO */
# define NUC_NTIMERS 4 /* 4x32-bit Timers */
# define NUC_NPDMA 9 /* 9 PDMA channels */
# define NUC_NUARTS 3 /* (3) UARTs */
# define NUC_NSPI 4 /* (4) SPI */
# define NUC_NI2C 2 /* (2) I2C */
# define NUC_NUSB 1 /* (1) USB 2.0 full speed */
# define NUC_NLIN 0 /* No LIN */
# define NUC_NCAN 0 /* No CAN */
# define NUC_NI2S 1 /* (1) I2S */
# define NUC_NCOMP 2 /* (2) Analog Comparators */
# define NUC_NPWM 8 /* (8) PWM */
# define NUC_NADC 8 /* 8x12-bit ADC */
# define NUC_RTC 1 /* RTC */
# undef NUC_EBI /* No EBI */
#else
# error "Unrecognized NUC1XX chip"
#endif
/* NVIC priority levels *************************************************************/
/* Each priority field holds a priority value, 0-3. The lower the value, the greater
* the priority of the corresponding interrupt. The processor implements only
* bits[7:6] of each field, bits[5:0] read as zero and ignore writes.
*/
#define NVIC_SYSH_PRIORITY_MIN 0xc0 /* All bits[7:3] set is minimum priority */
#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */
#define NVIC_SYSH_PRIORITY_STEP 0x40 /* Five bits of interrupt priority used */
/************************************************************************************
* Public Types
************************************************************************************/
/************************************************************************************
* Public Data
************************************************************************************/
#ifndef __ASSEMBLY__
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/************************************************************************************
* Public Functions
************************************************************************************/
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_INCLUDE_NUC1XX_CHIP_H */

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arch/arm/include/nuc1xx/irq.h
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@ -1,110 +0,0 @@
/************************************************************************************
* arch/arm/include/nuc1xx/irq.h
*
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
/* This file should never be included directed but, rather, only indirectly through
* nuttx/irq.h
*/
#ifndef __ARCH_ARM_INCLUDE_NUC1XX_IRQ_H
#define __ARCH_ARM_INCLUDE_NUC1XX_IRQ_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include <arch/nuc1xx/chip.h>
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* IRQ numbers. The IRQ number corresponds vector number and hence map directly to
* bits in the NVIC. This does, however, waste several words of memory in the IRQ
* to handle mapping tables.
*/
/* Processor Exceptions (vectors 0-15) */
#define NUC_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG) */
/* Vector 0: Reset stack pointer value */
/* Vector 1: Reset (not handler as an IRQ) */
#define NUC_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */
#define NUC_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */
/* Vector 4-10: Reserved */
#define NUC_IRQ_SVCALL (11) /* Vector 11: SVC call */
/* Vector 12-13: Reserved */
#define NUC_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */
#define NUC_IRQ_SYSTICK (15) /* Vector 15: System tick */
/* External interrupts (vectors >= 16). These definitions are chip-specific */
#define NUC_IRQ_INTERRUPT (16)
#if defined(NUC120)
# include <arch/nuc1xx/nuc120_irq.h>
#else
# error "Unrecognized/unsupported NUC chip"
#endif
/************************************************************************************
* Public Types
************************************************************************************/
/************************************************************************************
* Public Data
************************************************************************************/
#ifndef __ASSEMBLY__
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/************************************************************************************
* Public Functions
************************************************************************************/
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_INCLUDE_NUC1XX_IRQ_H */

116
arch/arm/include/nuc1xx/nuc120_irq.h
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@ -1,116 +0,0 @@
/************************************************************************************
* arch/arm/include/nuc1xx/nuc120_irq.h
*
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
/* This file should never be included directed but, rather, only indirectly through
* nuttx/irq.h
*/
#ifndef __ARCH_ARM_INCLUDE_NUC1XX_NUC120_IRQ_H
#define __ARCH_ARM_INCLUDE_NUC1XX_NUC120_IRQ_H
/************************************************************************************
* Included Files
************************************************************************************/
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* NUC120 IRQ numbers */
#define NUC_IRQ_BOD (16) /* Brown-out low voltage detected */
#define NUC_IRQ_WDT (17) /* Watchdog Timer */
#define NUC_IRQ_EINT0 (18) /* Eternal interrupt from PB.14 */
#define NUC_IRQ_EINT1 (19) /* Eternal interrupt from PB.15 */
#define NUC_IRQ_GPAB (20) /* Eternal interrupt from PA[15:0]/PB[13:0] */
#define NUC_IRQ_GPCDE (21) /* Eternal interrupt from PC[15:0]/PD[15:0]/PE[15:0] */
#define NUC_IRQ_PWMA (22) /* PWM0-3 */
#define NUC_IRQ_PWMB (23) /* PWM4-7 */
#define NUC_IRQ_TMR0 (24) /* Timer 0 */
#define NUC_IRQ_TMR1 (25) /* Timer 1 */
#define NUC_IRQ_TMR2 (26) /* Timer 2 */
#define NUC_IRQ_TMR3 (27) /* Timer 3 */
#define NUC_IRQ_UART02 (28) /* UART0-1 */
#define NUC_IRQ_UART1 (29) /* UART1 */
#define NUC_IRQ_SPI0 (30) /* SPI0 */
#define NUC_IRQ_SPI1 (31) /* SPI1 */
#define NUC_IRQ_SPI2 (32) /* SPI2 */
#define NUC_IRQ_SPI3 (33) /* SPI3 */
#define NUC_IRQ_I2C0 (34) /* I2C0 */
#define NUC_IRQ_I2C1 (35) /* I2C1 */
/* 36-38: Reserved */
#define NUC_IRQ_USB (39) /* USB */
#define NUC_IRQ_PS2 (40) /* PS/2 interrupt */
#define NUC_IRQ_ACMP (41) /* Analog comparator interrupt for chip wake-up from
* power down state */
#define NUC_IRQ_PDMA (42) /* PDMA */
#define NUC_IRQ_I2S (43) /* I2S */
#define NUC_IRQ_PWRWU (44) /* Clock controller interrupt for chip wake-up from
* power down state */
#define NUC_IRQ_ADC (45) /* ADC */
/* 46: Reserved */
#define NUC_IRQ_RTC (47) /* Real time clock */
#define NR_IRQS (48)
/************************************************************************************
* Public Types
************************************************************************************/
/************************************************************************************
* Public Data
************************************************************************************/
#ifndef __ASSEMBLY__
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/************************************************************************************
* Public Functions
************************************************************************************/
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_INCLUDE_NUC1XX_NUC120_IRQ_H */

949
arch/arm/include/sam34/chip.h
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@ -1,949 +0,0 @@
/************************************************************************************
* arch/arm/include/sam34/chip.h
*
* Copyright (C) 2009-2010, 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_INCLUDE_SAM34_CHIP_H
#define __ARCH_ARM_INCLUDE_SAM34_CHIP_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Get customizations for each supported chip */
/* AT91SAM3U Family *****************************************************************/
/* FEATURE SAM3U4E SAM3U2E SAM3U1E SAM3U4C SAM3U2C SAM3U1C
* ----------- -------- -------- -------- -------- -------- --------
* Flash 2x128KB 128KB 64KB 2x128KB 128KB 64KB
* SRAM 32+16KB 16+16KB 16KB 32+16KB 16+16KB 16KB
* NFC Yes Yes Yes Yes Yes Yes
* NFC SRAM 4KB 4KB 4KB 4KB 4KB 4KB
* Package LQFP144 LQFP144 LQFP144 LQFP100 LQFP100 LQFP100
* LFBGA144 LFBGA144 LFBGA144 LFBGA100 LFBGA100 LFBGA100
* No. PIOs 96 96 96 57 57 57
* SHDN Pin Yes Yes Yes No No No
* EMAC --- --- --- --- --- ---
* EBI Yes Yes Yes Yes Yes Yes
* EBI data 8/16 8/16 8/16 8 8 8
* EBI ch 4 4 4 2 2 2
* EBI addr 24 24 24 8 8 8
* SDRAM --- --- --- --- --- ---
* DMA 4 4 4 4 4 4
* 12-bit ADC 8ch 8ch 8ch 4ch 4ch 4ch
* 10-bit ADC 8ch 8ch 8ch 4ch 4ch 4ch
* 32-bit Timer 1 1 1 1 1 1
* 16-bit Timer 3 3 3 3 3 3
* PDC Channels 17 17 17 17 17 17
* USART 4 4 4 3 3 3
* UART 2 2 2 1 1 1
* SPI 1 1 1 1 1 1
* SSC 1 1 1 1 1 1
* HSMCI 8 bit 8 bit 8 bit 4 bit 4 bit 4 bit
*/
#if defined(CONFIG_ARCH_CHIP_ATSAM3U4E)
/* Internal memory */
# define SAM34_FLASH_SIZE (256*1024) /* 256KB */
# define SAM34_SRAM0_SIZE (32*1024) /* 32KB */
# define SAM34_SRAM1_SIZE (16*1024) /* 16KB */
# define SAM34_NFCSRAM_SIZE (4*1024) /* 4KB */
/* Peripherals */
# define SAM34_NDMACHAN 4 /* 4 DMA Channels */
# define SAM34_NPDCCHAN 17 /* 17 PDC Channels */
# define SAM34_NMCI2 1 /* 1 memory card interface */
# define SAM34_NSLCD 0 /* No segment LCD interface */
# define SAM34_NAESA 0 /* No advanced encryption standard */
# define SAM34_NUDPHS 1 /* One USB high speed device */
# define SAM34_NUHPHS 0 /* No USB high speed embedded host */
# define SAM34_NUDPFS 0 /* No USB full speed device */
# define SAM34_NUHPFS 0 /* No USB full speed embedded host */
#elif defined(CONFIG_ARCH_CHIP_ATSAM3U2E)
/* Internal memory */
# define SAM34_FLASH_SIZE (128*1024) /* 128KB */
# define SAM34_SRAM0_SIZE (16*1024) /* 16KB */
# define SAM34_SRAM1_SIZE (16*1024) /* 16KB */
# define SAM34_NFCSRAM_SIZE (4*1024) /* 4KB */
/* Peripherals */
# define SAM34_NDMACHAN 4 /* 4 DMA Channels */
# define SAM34_NPDCCHAN 17 /* 17 PDC Channels */
# define SAM34_NMCI2 1 /* 1 memory card interface */
# define SAM34_NSLCD 0 /* No segment LCD interface */
# define SAM34_NAESA 0 /* No advanced encryption standard */
# define SAM34_NUDPHS 1 /* One USB high speed device */
# define SAM34_NUHPHS 0 /* No USB high speed embedded host */
# define SAM34_NUDPFS 0 /* No USB full speed device */
# define SAM34_NUHPFS 0 /* No USB full speed embedded host */
#elif defined(CONFIG_ARCH_CHIP_ATSAM3U1E)
/* Internal memory */
# define SAM34_FLASH_SIZE (64*1024) /* 64KB */
# define SAM34_SRAM0_SIZE (16*1024) /* 16KB */
# define SAM34_SRAM1_SIZE 0 /* No SRAM1 */
# define SAM34_NFCSRAM_SIZE (4*1024) /* 4KB */
/* Peripherals */
# define SAM34_NDMACHAN 4 /* 4 DMA Channels */
# define SAM34_NPDCCHAN 17 /* 17 PDC Channels */
# define SAM34_NMCI2 1 /* 1 memory card interface */
# define SAM34_NSLCD 0 /* No segment LCD interface */
# define SAM34_NAESA 0 /* No advanced encryption standard */
# define SAM34_NUDPHS 1 /* One USB high speed device */
# define SAM34_NUHPHS 0 /* No USB high speed embedded host */
# define SAM34_NUDPFS 0 /* No USB full speed device */
# define SAM34_NUHPFS 0 /* No USB full speed embedded host */
#elif defined(CONFIG_ARCH_CHIP_ATSAM3U4C)
/* Internal memory */
# define SAM34_FLASH_SIZE (256*1024) /* 256KB */
# define SAM34_SRAM0_SIZE (32*1024) /* 32KB */
# define SAM34_SRAM1_SIZE (16*1024) /* 16KB */
# define SAM34_NFCSRAM_SIZE (4*1024) /* 4KB */
/* Peripherals */
# define SAM34_NDMACHAN 4 /* 4 DMA Channels */
# define SAM34_NPDCCHAN 17 /* 17 PDC Channels */
# define SAM34_NMCI2 1 /* 1 memory card interface */
# define SAM34_NSLCD 0 /* No segment LCD interface */
# define SAM34_NAESA 0 /* No advanced encryption standard */
# define SAM34_NUDPHS 1 /* One USB high speed device */
# define SAM34_NUHPHS 0 /* No USB high speed embedded host */
# define SAM34_NUDPFS 0 /* No USB full speed device */
# define SAM34_NUHPFS 0 /* No USB full speed embedded host */
#elif defined(CONFIG_ARCH_CHIP_ATSAM3U2C)
/* Internal memory */
# define SAM34_FLASH_SIZE (128*1024) /* 128KB */
# define SAM34_SRAM0_SIZE (16*1024) /* 16KB */
# define SAM34_SRAM1_SIZE (16*1024) /* 16KB */
# define SAM34_NFCSRAM_SIZE (4*1024) /* 4KB */
/* Peripherals */
# define SAM34_NDMACHAN 4 /* 4 DMA Channels */
# define SAM34_NPDCCHAN 17 /* 17 PDC Channels */
# define SAM34_NMCI2 1 /* 1 memory card interface */
# define SAM34_NSLCD 0 /* No segment LCD interface */
# define SAM34_NAESA 0 /* No advanced encryption standard */
# define SAM34_NUDPHS 1 /* One USB high speed device */
# define SAM34_NUHPHS 0 /* No USB high speed embedded host */
# define SAM34_NUDPFS 0 /* No USB full speed device */
# define SAM34_NUHPFS 0 /* No USB full speed embedded host */
#elif defined(CONFIG_ARCH_CHIP_ATSAM3U1C)
/* Internal memory */
# define SAM34_FLASH_SIZE (64*1024) /* 64KB */
# define SAM34_SRAM0_SIZE (16*1024) /* 16KB */
# define SAM34_SRAM1_SIZE 0 /* No SRAM1 */
# define SAM34_NFCSRAM_SIZE (4*1024) /* 4KB */
/* Peripherals */
# define SAM34_NDMACHAN 4 /* 4 DMA Channels */
# define SAM34_NPDCCHAN 17 /* 17 PDC Channels */
# define SAM34_NMCI2 1 /* 1 memory card interface */
# define SAM34_NSLCD 0 /* No segment LCD interface */
# define SAM34_NAESA 0 /* No advanced encryption standard */
# define SAM34_NUDPHS 1 /* One USB high speed device */
# define SAM34_NUHPHS 0 /* No USB high speed embedded host */
# define SAM34_NUDPFS 0 /* No USB full speed device */
# define SAM34_NUHPFS 0 /* No USB full speed embedded host */
/* AT91SAM3X/3A Families ************************************************************/
/* FEATURE SAM3X8E SAM3X8C SAM3X4E SAM3X4C SAM3A8C SAM3A4C
* ------------ -------- -------- -------- -------- -------- --------
* Flash 2x256KB 2x256KB 2x128KB 2x128KB 2x256KB 2x128KB
* SRAM 64+32KB 64+32KB 32+32KB 32+32KB 64+32KB 32+32KB
* NFC Yes --- Yes --- --- ---
* NFC SRAM 4KB --- 4KB --- --- ---
* Package LQFP144 LQFP100 LQFP144 LQFP100 LQFP100 LQFP100
* LFBGA144 LFBGA100 LFBGA144 LFBGA100 LFBGA100 LFBGA100
* No. PIOs 103 63 103 63 63 63
* SHDN Pin Yes No Yes No No No
* EMAC MII/RMII RMII MII/RMII RMII --- ---
* EBI Yes --- Yes --- --- ---
* SDRAM --- --- --- --- --- ---
* DMA 6 4 6 4 4 4
* 12-bit ADC 16ch 16ch 16ch 16ch 16ch 16ch
* 12-bit DAC 2ch 2ch 2ch 2ch 2ch 2ch
* 32-bit Timer 9 9 9 9 9 9
* PDC Channels 17 17 17 15 15 15
* USART 3 3 3 3 3 3
* UART 2 1 2 1 1 1
* SPI 1/4+3 1/4+3 1/4+3 1/4+3 1/4+3 1/4+3
* HSMCI 8 bit 4 bit 8 bit 4 bit 4 bit 4 bit
*/
#elif defined(CONFIG_ARCH_CHIP_ATSAM3X8E)
/* Internal memory */
# define SAM34_FLASH_SIZE (512*1024) /* 512KB */
# define SAM34_SRAM0_SIZE (64*1024) /* 64KB */
# define SAM34_SRAM1_SIZE (32*1024) /* 32KB */
# define SAM34_NFCSRAM_SIZE (4*1024) /* 4KB */
/* Peripherals */
# define SAM34_NDMACHAN 6 /* 6 DMA Channels */
# define SAM34_NPDCCHAN 17 /* 17 PDC Channels */
# define SAM34_NMCI2 1 /* 1 memory card interface */
# define SAM34_NSLCD 0 /* No segment LCD interface */
# define SAM34_NAESA 0 /* No advanced encryption standard */
# define SAM34_NUDPHS 1 /* One USB high speed device */
# define SAM34_NUHPHS 1 /* One USB high speed embedded host */
# define SAM34_NUDPFS 0 /* No USB full speed device */
# define SAM34_NUHPFS 0 /* No USB full speed embedded host */
#elif defined(CONFIG_ARCH_CHIP_ATSAM3X8C)
/* Internal memory */
# define SAM34_FLASH_SIZE (512*1024) /* 512KB */
# define SAM34_SRAM0_SIZE (64*1024) /* 64KB */
# define SAM34_SRAM1_SIZE (32*1024) /* 32KB */
# define SAM34_NFCSRAM_SIZE 0 /* No NFC SRAM */
/* Peripherals */
# define SAM34_NDMACHAN 4 /* 4 DMA Channels */
# define SAM34_NPDCCHAN 17 /* 17 PDC Channels */
# define SAM34_NMCI2 1 /* 1 memory card interface */
# define SAM34_NSLCD 0 /* No segment LCD interface */
# define SAM34_NAESA 0 /* No advanced encryption standard */
# define SAM34_NUDPHS 1 /* One USB high speed device */
# define SAM34_NUHPHS 1 /* One USB high speed embedded host */
# define SAM34_NUDPFS 0 /* No USB full speed device */
# define SAM34_NUHPFS 0 /* No USB full speed embedded host */
#elif defined(CONFIG_ARCH_CHIP_ATSAM3X4E)
/* Internal memory */
# define SAM34_FLASH_SIZE (256*1024) /* 256KB */
# define SAM34_SRAM0_SIZE (32*1024) /* 32KB */
# define SAM34_SRAM1_SIZE (32*1024) /* 32KB */
# define SAM34_NFCSRAM_SIZE (4*1024) /* 4KB */
/* Peripherals */
# define SAM34_NDMACHAN 6 /* 4 DMA Channels */
# define SAM34_NPDCCHAN 17 /* 17 PDC Channels */
# define SAM34_NMCI2 1 /* 1 memory card interface */
# define SAM34_NSLCD 0 /* No segment LCD interface */
# define SAM34_NAESA 0 /* No advanced encryption standard */
# define SAM34_NUDPHS 1 /* One USB high speed device */
# define SAM34_NUHPHS 1 /* One USB high speed embedded host */
# define SAM34_NUDPFS 0 /* No USB full speed device */
# define SAM34_NUHPFS 0 /* No USB full speed embedded host */
#elif defined(CONFIG_ARCH_CHIP_ATSAM3X4C)
/* Internal memory */
# define SAM34_FLASH_SIZE (256*1024) /* 256KB */
# define SAM34_SRAM0_SIZE (32*1024) /* 32KB */
# define SAM34_SRAM1_SIZE (32*1024) /* 32KB */
# define SAM34_NFCSRAM_SIZE 0 /* No NFC SRAM */
/* Peripherals */
# define SAM34_NDMACHAN 4 /* 4 DMA Channels */
# define SAM34_NPDCCHAN 15 /* 15 PDC Channels */
# define SAM34_NMCI2 1 /* 1 memory card interface */
# define SAM34_NSLCD 0 /* No segment LCD interface */
# define SAM34_NAESA 0 /* No advanced encryption standard */
# define SAM34_NUDPHS 1 /* One USB high speed device */
# define SAM34_NUHPHS 1 /* One USB high speed embedded host */
# define SAM34_NUDPFS 0 /* No USB full speed device */
# define SAM34_NUHPFS 0 /* No USB full speed embedded host */
#elif defined(CONFIG_ARCH_CHIP_ATSAM3A8C)
/* Internal memory */
# define SAM34_FLASH_SIZE (512*1024) /* 512KB */
# define SAM34_SRAM0_SIZE (64*1024) /* 64KB */
# define SAM34_SRAM1_SIZE (32*1024) /* 32KB */
# define SAM34_NFCSRAM_SIZE 0 /* No NFC SRAM */
/* Peripherals */
# define SAM34_NDMACHAN 4 /* 4 DMA Channels */
# define SAM34_NPDCCHAN 15 /* 15 PDC Channels */
# define SAM34_NMCI2 1 /* 1 memory card interface */
# define SAM34_NSLCD 0 /* No segment LCD interface */
# define SAM34_NAESA 0 /* No advanced encryption standard */
# define SAM34_NUDPHS 1 /* One USB high speed device */
# define SAM34_NUHPHS 1 /* One USB high speed embedded host */
# define SAM34_NUDPFS 0 /* No USB full speed device */
# define SAM34_NUHPFS 0 /* No USB full speed embedded host */
#elif defined(CONFIG_ARCH_CHIP_ATSAM3A4C)
/* Internal memory */
# define SAM34_FLASH_SIZE (256*1024) /* 256KB */
# define SAM34_SRAM0_SIZE (32*1024) /* 64KB */
# define SAM34_SRAM1_SIZE (32*1024) /* 32KB */
# define SAM34_NFCSRAM_SIZE 0 /* No NFC SRAM */
/* Peripherals */
# define SAM34_NDMACHAN 4 /* 4 DMA Channels */
# define SAM34_NPDCCHAN 15 /* 15 PDC Channels */
# define SAM34_NMCI2 1 /* 1 memory card interface */
# define SAM34_NSLCD 0 /* No segment LCD interface */
# define SAM34_NAESA 0 /* No advanced encryption standard */
# define SAM34_NUDPHS 1 /* One USB high speed device */
# define SAM34_NUHPHS 1 /* One USB high speed embedded host */
# define SAM34_NUDPFS 0 /* No USB full speed device */
# define SAM34_NUHPFS 0 /* No USB full speed embedded host */
/* AT91SAM4C Family *****************************************************************/
/* FEATURE SAM4CMP16B
* ----------- ---------
* Flash 1024KB
* SRAM 128KB
* SMC Yes
* GMCC 2KB
* Package LQFP144
* LFBGA144
* No. PIOs 117
* SHDN Pin No
* EMAC MII
* CAN 2
* EBI Yes
* EBI data 8
* EBI ch 4
* EBI addr 24
* SDRAM ---
* DMA 4
* 16-bit ADC0 16ch
* 16-bit ADC1 8ch
* 12-bit DAC 2ch
* Timer 9
* PDC Channels 24+9
* USART 2
* UART 2
* SPI 1
* HSMCI 4 bit
*/
#elif defined(CONFIG_ARCH_CHIP_ATSAM4CMP16B)
/* Internal memory */
# define SAM34_FLASH_SIZE (1024*1024) /* 1024KB */
# define SAM34_SRAM0_SIZE (128*1024) /* 128KB */
# define SAM34_SRAM1_SIZE 0 /* None */
# define SAM34_NFCSRAM_SIZE 0 /* None */
/* Peripherals */
# define SAM34_NDMACHAN 21 /* 21 PDC Channels */
# define SAM34_NMCI2 0 /* No memory card interface */
# define SAM32_NSLCD 1 /* 1 segment LCD interface */
# define SAM32_NAESA 1 /* 1 advanced encryption standard */
# define SAM32_NUDPHS 0 /* No USB high speed device */
# define SAM32_NUHPHS 0 /* No USB high speed embedded host */
# define SAM32_NUDPFS 0 /* No USB full speed device */
# define SAM32_NUHPFS 0 /* No USB full speed embedded host */
/* AT91SAM4L Family *****************************************************************/
/* Sub-family differences:
*
* FEATURE ATSAM4LCxx ATSAM4LSxx
* ----------------------- ------------- -------------
* SEGMENT LCD Yes No
* AESA Yes No
* USB Device + Host Device Only
*
* Note: The SEGMENT LCD capability varies with packaging.
*
* FEATURE ATSAM4Lx2x ATSAM4Lx4x
* ----------------------- ------------- -------------
* FLASH 256KB 128KB
* SRAM 32KB 32KB
*
* Packaging differences:
*
* FEATURE ATSAM4LxxC ATSAM4LxxB ATSAM4LxxA
* ----------------------- ---------- ---------- ----------
* Number of Pins 100 64 48
* Max Frequency 48MHz 48MHz 48MHz
* SEGMENT LCD 4x40 4x23 4x13
* GPIO 75 43 27
* High-drive pins 6 3 1
* External Interrupts 8+NMI 8+NMI 8+NMI
* TWI Masters 2 2 1
* TWI Master/Slave 2 2 1
* USART 4 4 3
* PICOUART 1 1 1
* Peripheral DMA Channels 16 16 16
* Peripheral Even System 1 1 1
* SPI 1 1 1
* Asynchronous Timers 1 1 1
* Timer/Counter Channels 6 3 3
* Parallel Capture Inputs 8 8 8
* Frequency Meter 1 1 1
* Watchdog Timer 1 1 1
* Power Manager 1 1 1
* Glue Logic LUT 2 2 1
* ADC 15-channel 7-channel 3-channel
* DAC 1-channel 1-channel 1-channel
* Analog Comparators 4 2 1
* CATB Sensors 32 32 26
* Audio Bitstream DAC 1 1 1
* IIS Controller 1 1 1
* Packages TQFP/VFBGA TQFP/QFN TQFP/QFN
*/
#elif defined(CONFIG_ARCH_CHIP_ATSAM4LC2C) || defined (CONFIG_ARCH_CHIP_ATSAM4LC2B) || \
defined(CONFIG_ARCH_CHIP_ATSAM4LC2A)
/* Internal memory */
# define SAM34_FLASH_SIZE (128*1024) /* 128KB */
# define SAM34_SRAM0_SIZE (32*1024) /* 32KB */
# define SAM34_SRAM1_SIZE 0 /* None */
# define SAM34_NFCSRAM_SIZE 0 /* None */
/* Peripherals */
# define SAM34_NDMACHAN 0 /* No DMAC Channels */
# define SAM34_NPDCCHAN 16 /* 16 PDC Channels */
# define SAM34_NMCI2 0 /* No memory card interface */
# define SAM34_NSLCD 1 /* 1 segment LCD interface */
# define SAM34_NAESA 1 /* 1 advanced encryption standard */
# define SAM34_NUDPHS 0 /* No USB high speed device */
# define SAM34_NUHPHS 0 /* No USB high speed embedded host */
# define SAM34_NUDPFS 1 /* 1 USB full speed device */
# define SAM34_NUHPFS 1 /* 1 USB full speed embedded host */
#elif defined(CONFIG_ARCH_CHIP_ATSAM4LC4C) || defined (CONFIG_ARCH_CHIP_ATSAM4LC4B) || \
defined(CONFIG_ARCH_CHIP_ATSAM4LC4A)
/* Internal memory */
# define SAM34_FLASH_SIZE (256*1024) /* 256KB */
# define SAM34_SRAM0_SIZE (32*1024) /* 32KB */
# define SAM34_SRAM1_SIZE 0 /* None */
# define SAM34_NFCSRAM_SIZE 0 /* None */
/* Peripherals */
# define SAM34_NDMACHAN 0 /* No DMAC Channels */
# define SAM34_NPDCCHAN 16 /* 16 PDC Channels */
# define SAM34_NMCI2 0 /* No memory card interface */
# define SAM34_NSLCD 1 /* 1 segment LCD interface */
# define SAM34_NAESA 1 /* 1 advanced encryption standard */
# define SAM34_NUDPHS 0 /* No USB high speed device */
# define SAM34_NUHPHS 0 /* No USB high speed embedded host */
# define SAM34_NUDPFS 1 /* 1 USB full speed device */
# define SAM34_NUHPFS 1 /* 1 USB full speed embedded host */
#elif defined(CONFIG_ARCH_CHIP_ATSAM4LS2C) || defined (CONFIG_ARCH_CHIP_ATSAM4LS2B) || \
defined(CONFIG_ARCH_CHIP_ATSAM4LS2A)
/* Internal memory */
# define SAM34_FLASH_SIZE (128*1024) /* 128KB */
# define SAM34_SRAM0_SIZE (32*1024) /* 32KB */
# define SAM34_SRAM1_SIZE 0 /* None */
# define SAM34_NFCSRAM_SIZE 0 /* None */
/* Peripherals */
# define SAM34_NDMACHAN 0 /* No DMAC Channels */
# define SAM34_NPDCCHAN 16 /* 16 PDC Channels */
# define SAM34_NMCI2 0 /* No memory card interface */
# define SAM34_NSLCD 0 /* No segment LCD interface */
# define SAM34_NAESA 0 /* No advanced encryption standard */
# define SAM34_NUDPHS 0 /* No USB high speed device */
# define SAM34_NUHPHS 0 /* No USB high speed embedded host */
# define SAM34_NUDPFS 1 /* 1 USB full speed device */
# define SAM34_NUHPFS 0 /* No USB full speed embedded host */
#elif defined(CONFIG_ARCH_CHIP_ATSAM4LS4C) || defined (CONFIG_ARCH_CHIP_ATSAM4LS4B) || \
defined(CONFIG_ARCH_CHIP_ATSAM4LS4A)
/* Internal memory */
# define SAM34_FLASH_SIZE (256*1024) /* 256KB */
# define SAM34_SRAM0_SIZE (32*1024) /* 32KB */
# define SAM34_SRAM1_SIZE 0 /* None */
# define SAM34_NFCSRAM_SIZE 0 /* None */
/* Peripherals */
# define SAM34_NDMACHAN 0 /* No DMAC Channels */
# define SAM34_NPDCCHAN 16 /* 16 PDC Channels */
# define SAM34_NMCI2 0 /* No memory card interface */
# define SAM34_NSLCD 0 /* No segment LCD interface */
# define SAM34_NAESA 0 /* No advanced encryption standard */
# define SAM34_NUDPHS 0 /* No USB high speed device */
# define SAM34_NUHPHS 0 /* No USB high speed embedded host */
# define SAM34_NUDPFS 1 /* 1 USB full speed device */
# define SAM34_NUHPFS 0 /* No USB full speed embedded host */
/* AT91SAM4S Family *****************************************************************/
/*
* FEATURE SAM4SD32C SAM4SD32B SAM4SD16C SAM4SD16B SAM4SA16C SAM4SA16B SAM4S16C SAM4S16B SAM4S8C SAM4S8B
* ------------- --------- --------- --------- --------- --------- --------- -------- -------- ------- -------
* Flash 2x1MB 2x1MB 2x512KB 1x1MB 1x1MB 1x1MB 1x1MB 1x1MB 1x512KB 1x512KB
* SRAM 160KB 160KB 160KB 160KB 160KB 160KB 128KB 128KB 128KB 128KB
* HCACHE 2KB 2KB 2KB 2KB 2KB 2KB - - - -
* Pins 100 64 100 64 100 64 100 64 100 64
* No. PIOs 79 47 79 47 79 47 79 47 79 47
* Ext. BUS Yes No Yes No Yes No Yes No Yes No
* 12-bit ADC 16 ch 11 ch 16 ch 11 ch 16 ch 11 ch 16 ch 11 ch 16 ch 11 ch
* 12-bit DAC 2 ch 2 ch 2 ch 2 ch 2 ch 2 ch 2 ch 2 ch 2 ch 2 ch
* Timer Counter 6 ch 3 ch 6 ch 3 ch 6 ch 3 ch 6 ch 3 ch 6 ch 3 ch
* PDC 22 ch 22 ch 22 ch 22 ch 22 ch 22 ch 22 ch 22 ch 22 ch 22 ch
* USART 2 2 2 2 2 2 2 2 2 2
* UART 2 2 2 2 2 2 2 2 2 2
* HSMCI Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
*/
#elif defined(CONFIG_ARCH_CHIP_ATSAM4SD32C)
/* Internal memory */
# define SAM34_FLASH_SIZE (2*1024*1024) /* 2x1MB */
# define SAM34_SRAM0_SIZE (160*1024) /* 160KB */
# define SAM34_SRAM1_SIZE 0 /* None */
# define SAM34_NFCSRAM_SIZE 0 /* None */
/* Peripherals */
# define SAM34_NDMACHAN 0 /* No DMAC Channels */
# define SAM34_NPDCCHAN 22 /* 22 PDC Channels */
# define SAM34_NMCI2 1 /* 1 memory card interface */
# define SAM34_NSLCD 0 /* No segment LCD interface */
# define SAM34_NAESA 0 /* No advanced encryption standard */
# define SAM34_NUDPHS 0 /* No USB high speed device */
# define SAM34_NUHPHS 0 /* No USB high speed embedded host */
# define SAM34_NUDPFS 1 /* 1 USB full speed device */
# define SAM34_NUHPFS 0 /* No USB full speed embedded host */
#elif defined(CONFIG_ARCH_CHIP_ATSAM4SD32B)
/* Internal memory */
# define SAM34_FLASH_SIZE (2*1024*1024) /* 2x1MB */
# define SAM34_SRAM0_SIZE (160*1024) /* 160KB */
# define SAM34_SRAM1_SIZE 0 /* None */
# define SAM34_NFCSRAM_SIZE 0 /* None */
/* Peripherals */
# define SAM34_NDMACHAN 0 /* No DMAC Channels */
# define SAM34_NPDCCHAN 22 /* 22 PDC Channels */
# define SAM34_NMCI2 1 /* 1 memory card interface */
# define SAM34_NSLCD 0 /* No segment LCD interface */
# define SAM34_NAESA 0 /* No advanced encryption standard */
# define SAM34_NUDPHS 0 /* No USB high speed device */
# define SAM34_NUHPHS 0 /* No USB high speed embedded host */
# define SAM34_NUDPFS 1 /* 1 USB full speed device */
# define SAM34_NUHPFS 0 /* No USB full speed embedded host */
#elif defined(CONFIG_ARCH_CHIP_ATSAM4SD16C)
/* Internal memory */
# define SAM34_FLASH_SIZE (1024*1024) /* 2x512KB */
# define SAM34_SRAM0_SIZE (160*1024) /* 160KB */
# define SAM34_SRAM1_SIZE 0 /* None */
# define SAM34_NFCSRAM_SIZE 0 /* None */
/* Peripherals */
# define SAM34_NDMACHAN 0 /* No DMAC Channels */
# define SAM34_NPDCCHAN 22 /* 22 PDC Channels */
# define SAM34_NMCI2 1 /* 1 memory card interface */
# define SAM34_NSLCD 0 /* No segment LCD interface */
# define SAM34_NAESA 0 /* No advanced encryption standard */
# define SAM34_NUDPHS 0 /* No USB high speed device */
# define SAM34_NUHPHS 0 /* No USB high speed embedded host */
# define SAM34_NUDPFS 1 /* 1 USB full speed device */
# define SAM34_NUHPFS 0 /* No USB full speed embedded host */
#elif defined(CONFIG_ARCH_CHIP_ATSAM4SD16B)
/* Internal memory */
# define SAM34_FLASH_SIZE (1024*1024) /* 2x512KB */
# define SAM34_SRAM0_SIZE (160*1024) /* 160KB */
# define SAM34_SRAM1_SIZE 0 /* None */
# define SAM34_NFCSRAM_SIZE 0 /* None */
/* Peripherals */
# define SAM34_NDMACHAN 0 /* No DMAC Channels */
# define SAM34_NPDCCHAN 22 /* 22 PDC Channels */
# define SAM34_NMCI2 1 /* 1 memory card interface */
# define SAM34_NSLCD 0 /* No segment LCD interface */
# define SAM34_NAESA 0 /* No advanced encryption standard */
# define SAM34_NUDPHS 0 /* No USB high speed device */
# define SAM34_NUHPHS 0 /* No USB high speed embedded host */
# define SAM34_NUDPFS 1 /* 1 USB full speed device */
# define SAM34_NUHPFS 0 /* No USB full speed embedded host */
#elif defined(CONFIG_ARCH_CHIP_ATSAM4SA16C)
/* Internal memory */
# define SAM34_FLASH_SIZE (1024*1024) /* 1MB */
# define SAM34_SRAM0_SIZE (160*1024) /* 160KB */
# define SAM34_SRAM1_SIZE 0 /* None */
# define SAM34_NFCSRAM_SIZE 0 /* None */
/* Peripherals */
# define SAM34_NDMACHAN 0 /* No DMAC Channels */
# define SAM34_NPDCCHAN 22 /* 22 PDC Channels */
# define SAM34_NMCI2 1 /* 1 memory card interface */
# define SAM34_NSLCD 0 /* No segment LCD interface */
# define SAM34_NAESA 0 /* No advanced encryption standard */
# define SAM34_NUDPHS 0 /* No USB high speed device */
# define SAM34_NUHPHS 0 /* No USB high speed embedded host */
# define SAM34_NUDPFS 1 /* 1 USB full speed device */
# define SAM34_NUHPFS 0 /* No USB full speed embedded host */
#elif defined(CONFIG_ARCH_CHIP_ATSAM4SA16B)
/* Internal memory */
# define SAM34_FLASH_SIZE (1024*1024) /* 1MB */
# define SAM34_SRAM0_SIZE (160*1024) /* 160KB */
# define SAM34_SRAM1_SIZE 0 /* None */
# define SAM34_NFCSRAM_SIZE 0 /* None */
/* Peripherals */
# define SAM34_NDMACHAN 0 /* No DMAC Channels */
# define SAM34_NPDCCHAN 22 /* 22 PDC Channels */
# define SAM34_NMCI2 1 /* 1 memory card interface */
# define SAM34_NSLCD 0 /* No segment LCD interface */
# define SAM34_NAESA 0 /* No advanced encryption standard */
# define SAM34_NUDPHS 0 /* No USB high speed device */
# define SAM34_NUHPHS 0 /* No USB high speed embedded host */
# define SAM34_NUDPFS 1 /* 1 USB full speed device */
# define SAM34_NUHPFS 0 /* No USB full speed embedded host */
#elif defined(CONFIG_ARCH_CHIP_ATSAM4S16C)
/* Internal memory */
# define SAM34_FLASH_SIZE (1024*1024) /* 1MB */
# define SAM34_SRAM0_SIZE (128*1024) /* 128KB */
# define SAM34_SRAM1_SIZE 0 /* None */
# define SAM34_NFCSRAM_SIZE 0 /* None */
/* Peripherals */
# define SAM34_NDMACHAN 0 /* No DMAC Channels */
# define SAM34_NPDCCHAN 22 /* 22 PDC Channels */
# define SAM34_NMCI2 1 /* 1 memory card interface */
# define SAM34_NSLCD 0 /* No segment LCD interface */
# define SAM34_NAESA 0 /* No advanced encryption standard */
# define SAM34_NUDPHS 0 /* No USB high speed device */
# define SAM34_NUHPHS 0 /* No USB high speed embedded host */
# define SAM34_NUDPFS 1 /* 1 USB full speed device */
# define SAM34_NUHPFS 0 /* No USB full speed embedded host */
#elif defined(CONFIG_ARCH_CHIP_ATSAM4S16B)
/* Internal memory */
# define SAM34_FLASH_SIZE (1024*1024) /* 1MB */
# define SAM34_SRAM0_SIZE (128*1024) /* 128KB */
# define SAM34_SRAM1_SIZE 0 /* None */
# define SAM34_NFCSRAM_SIZE 0 /* None */
/* Peripherals */
# define SAM34_NDMACHAN 0 /* No DMAC Channels */
# define SAM34_NPDCCHAN 22 /* 22 PDC Channels */
# define SAM34_NMCI2 1 /* 1 memory card interface */
# define SAM34_NSLCD 0 /* No segment LCD interface */
# define SAM34_NAESA 0 /* No advanced encryption standard */
# define SAM34_NUDPHS 0 /* No USB high speed device */
# define SAM34_NUHPHS 0 /* No USB high speed embedded host */
# define SAM34_NUDPFS 1 /* 1 USB full speed device */
# define SAM34_NUHPFS 0 /* No USB full speed embedded host */
#elif defined(CONFIG_ARCH_CHIP_ATSAM4S8C)
/* Internal memory */
# define SAM34_FLASH_SIZE (512*1024) /* 512KB */
# define SAM34_SRAM0_SIZE (128*1024) /* 128KB */
# define SAM34_SRAM1_SIZE 0 /* None */
# define SAM34_NFCSRAM_SIZE 0 /* None */
/* Peripherals */
# define SAM34_NDMACHAN 0 /* No DMAC Channels */
# define SAM34_NPDCCHAN 22 /* 22 PDC Channels */
# define SAM34_NMCI2 1 /* 1 memory card interface */
# define SAM34_NSLCD 0 /* No segment LCD interface */
# define SAM34_NAESA 0 /* No advanced encryption standard */
# define SAM34_NUDPHS 0 /* No USB high speed device */
# define SAM34_NUHPHS 0 /* No USB high speed embedded host */
# define SAM34_NUDPFS 1 /* 1 USB full speed device */
# define SAM34_NUHPFS 0 /* No USB full speed embedded host */
#elif defined(CONFIG_ARCH_CHIP_ATSAM4S8B)
/* Internal memory */
# define SAM34_FLASH_SIZE (512*1024) /* 512KB */
# define SAM34_SRAM0_SIZE (128*1024) /* 128KB */
# define SAM34_SRAM1_SIZE 0 /* None */
# define SAM34_NFCSRAM_SIZE 0 /* None */
/* Peripherals */
# define SAM34_NDMACHAN 0 /* No DMAC Channels */
# define SAM34_NPDCCHAN 22 /* 22 PDC Channels */
# define SAM34_NMCI2 1 /* 1 memory card interface */
# define SAM34_NSLCD 0 /* No segment LCD interface */
# define SAM34_NAESA 0 /* No advanced encryption standard */
# define SAM34_NUDPHS 0 /* No USB high speed device */
# define SAM34_NUHPHS 0 /* No USB high speed embedded host */
# define SAM34_NUDPFS 1 /* 1 USB full speed device */
# define SAM34_NUHPFS 0 /* No USB full speed embedded host */
/* AT91SAM4E Family *****************************************************************/
/* FEATURE SAM4E16E SAM4E8E SAM4E16C SAM4E8C
* ----------- --------- -------- -------- --------
* Flash 1024KB 512KB 1024KB 512KB
* SRAM 128KB 128KB 128KB 128KB
* SMC Yes Yes Yes Yes
* GMCC 2KB 2KB 2KB 2KB
* Package LQFP144 LQFP144 LQFP100 LQFP100
* LFBGA144 LFBGA144 TFBGA100 TFBGA100
* No. PIOs 117 117 79 79
* SHDN Pin No No No No
* EMAC MII MII MII MII
* CAN 2 2 1 1
* EBI Yes Yes No No
* EBI data 8 8 --- ---
* EBI ch 4 4 --- ---
* EBI addr 24 24 --- ---
* SDRAM --- --- --- ---
* DMA 4 4 4 4
* 16-bit ADC0 16ch 16ch 6ch 6ch
* 16-bit ADC1 8ch 8ch 4ch 4ch
* 12-bit DAC 2ch 2ch 2ch 2ch
* Timer 9 9 3 3
* PDC Channels 24+9 24+9 21+9 21+9
* USART 2 2 2 2
* UART 2 2 2 2
* SPI 1 1 1 1
* HSMCI 4 bit 4 bit 4 bit 4 bit
*/
#elif defined(CONFIG_ARCH_CHIP_ATSAM4E16E)
/* Internal memory */
# define SAM34_FLASH_SIZE (1024*1024) /* 1024KB */
# define SAM34_SRAM0_SIZE (128*1024) /* 128KB */
# define SAM34_SRAM1_SIZE 0 /* None */
# define SAM34_NFCSRAM_SIZE 0 /* None */
/* Peripherals */
# define SAM34_NDMACHAN 4 /* 4 DMAC Channels */
# define SAM34_NPDCCHAN 24 /* 24 PDC Channels */
# define SAM34_NMCI2 1 /* 1 memory card interface */
# define SAM34_NSLCD 0 /* No segment LCD interface */
# define SAM34_NAESA 0 /* No advanced encryption standard */
# define SAM34_NUDPHS 0 /* No USB high speed device */
# define SAM34_NUHPHS 0 /* No USB high speed embedded host */
# define SAM34_NUDPFS 1 /* 1 USB full speed device */
# define SAM34_NUHPFS 0 /* No USB full speed embedded host */
#elif defined(CONFIG_ARCH_CHIP_ATSAM4E8E)
/* Internal memory */
# define SAM34_FLASH_SIZE (512*1024) /* 512KB */
# define SAM34_SRAM0_SIZE (128*1024) /* 128KB */
# define SAM34_SRAM1_SIZE 0 /* None */
# define SAM34_NFCSRAM_SIZE 0 /* None */
/* Peripherals */
# define SAM34_NDMACHAN 4 /* 4 DMAC Channels */
# define SAM34_NPDCCHAN 24 /* 24 PDC Channels */
# define SAM34_NMCI2 1 /* 1 memory card interface */
# define SAM34_NSLCD 0 /* No segment LCD interface */
# define SAM34_NAESA 0 /* No advanced encryption standard */
# define SAM34_NUDPHS 0 /* No USB high speed device */
# define SAM34_NUHPHS 0 /* No USB high speed embedded host */
# define SAM34_NUDPFS 1 /* 1 USB full speed device */
# define SAM34_NUHPFS 0 /* No USB full speed embedded host */
#elif defined(CONFIG_ARCH_CHIP_ATSAM4E16C)
/* Internal memory */
# define SAM34_FLASH_SIZE (1024*1024) /* 1024KB */
# define SAM34_SRAM0_SIZE (128*1024) /* 128KB */
# define SAM34_SRAM1_SIZE 0 /* None */
# define SAM34_NFCSRAM_SIZE 0 /* None */
/* Peripherals */
# define SAM34_NDMACHAN 4 /* 4 DMAC Channels */
# define SAM34_NPDCCHAN 21 /* 21 PDC Channels */
# define SAM34_NMCI2 1 /* 1 memory card interface */
# define SAM34_NSLCD 0 /* No segment LCD interface */
# define SAM34_NAESA 0 /* No advanced encryption standard */
# define SAM34_NUDPHS 0 /* No USB high speed device */
# define SAM34_NUHPHS 0 /* No USB high speed embedded host */
# define SAM34_NUDPFS 1 /* 1 USB full speed device */
# define SAM34_NUHPFS 0 /* No USB full speed embedded host */
#elif defined(CONFIG_ARCH_CHIP_ATSAM4E8C)
/* Internal memory */
# define SAM34_FLASH_SIZE (512*1024) /* 512KB */
# define SAM34_SRAM0_SIZE (128*1024) /* 128KB */
# define SAM34_SRAM1_SIZE 0 /* None */
# define SAM34_NFCSRAM_SIZE 0 /* None */
/* Peripherals */
# define SAM34_NDMACHAN 4 /* 4 DMAC Channels */
# define SAM34_NPDCCHAN 21 /* 21 PDC Channels */
# define SAM34_NMCI2 1 /* 1 memory card interface */
# define SAM34_NSLCD 0 /* No segment LCD interface */
# define SAM34_NAESA 0 /* No advanced encryption standard */
# define SAM34_NUDPHS 0 /* No USB high speed device */
# define SAM34_NUHPHS 0 /* No USB high speed embedded host */
# define SAM34_NUDPFS 1 /* 1 USB full speed device */
# define SAM34_NUHPFS 0 /* No USB full speed embedded host */
#else
# error "Unknown SAM3/4 chip type"
#endif
/* NVIC priority levels *************************************************************/
/* Each priority field holds a priority value, 0-15. The lower the value, the greater
* the priority of the corresponding interrupt. The processor implements only
* bits[7:4] of each field, bits[3:0] read as zero and ignore writes.
*/
#define NVIC_SYSH_PRIORITY_MIN 0xf0 /* All bits[7:4] set is minimum priority */
#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */
#define NVIC_SYSH_PRIORITY_STEP 0x10 /* Four bits of interrupt priority used */
/* If CONFIG_ARMV7M_USEBASEPRI is selected, then interrupts will be disabled
* by setting the BASEPRI register to NVIC_SYSH_DISABLE_PRIORITY so that most
* interrupts will not have execution priority. SVCall must have execution
* priority in all cases.
*
* In the normal cases, interrupts are not nest-able and all interrupts run
* at an execution priority between NVIC_SYSH_PRIORITY_MIN and
* NVIC_SYSH_PRIORITY_MAX (with NVIC_SYSH_PRIORITY_MAX reserved for SVCall).
*
* If, in addition, CONFIG_ARCH_HIPRI_INTERRUPT is defined, then special
* high priority interrupts are supported. These are not "nested" in the
* normal sense of the word. These high priority interrupts can interrupt
* normal processing but execute outside of OS (although they can "get back
* into the game" via a PendSV interrupt).
*
* In the normal course of things, interrupts must occasionally be disabled
* using the irqsave() inline function to prevent contention in use of
* resources that may be shared between interrupt level and non-interrupt
* level logic. Now the question arises, if CONFIG_ARCH_HIPRI_INTERRUPT,
* do we disable all interrupts (except SVCall), or do we only disable the
* "normal" interrupts. Since the high priority interrupts cannot interact
* with the OS, you may want to permit the high priority interrupts even if
* interrupts are disabled. The setting CONFIG_ARCH_INT_DISABLEALL can be
* used to select either behavior:
*
* ----------------------------+--------------+----------------------------
* CONFIG_ARCH_HIPRI_INTERRUPT | NO | YES
* ----------------------------+--------------+--------------+-------------
* CONFIG_ARCH_INT_DISABLEALL | N/A | YES | NO
* ----------------------------+--------------+--------------+-------------
* | | | SVCall
* | SVCall | SVCall | HIGH
* Disable here and below --------> MAXNORMAL ---> HIGH --------> MAXNORMAL
* | | MAXNORMAL |
* ----------------------------+--------------+--------------+-------------
*/
#if defined(CONFIG_ARCH_HIPRI_INTERRUPT) && defined(CONFIG_ARCH_INT_DISABLEALL)
# define NVIC_SYSH_MAXNORMAL_PRIORITY (NVIC_SYSH_PRIORITY_MAX + 2*NVIC_SYSH_PRIORITY_STEP)
# define NVIC_SYSH_HIGH_PRIORITY (NVIC_SYSH_PRIORITY_MAX + NVIC_SYSH_PRIORITY_STEP)
# define NVIC_SYSH_DISABLE_PRIORITY NVIC_SYSH_HIGH_PRIORITY
# define NVIC_SYSH_SVCALL_PRIORITY NVIC_SYSH_PRIORITY_MAX
#else
# define NVIC_SYSH_MAXNORMAL_PRIORITY (NVIC_SYSH_PRIORITY_MAX + NVIC_SYSH_PRIORITY_STEP)
# define NVIC_SYSH_HIGH_PRIORITY NVIC_SYSH_PRIORITY_MAX
# define NVIC_SYSH_DISABLE_PRIORITY NVIC_SYSH_MAXNORMAL_PRIORITY
# define NVIC_SYSH_SVCALL_PRIORITY NVIC_SYSH_PRIORITY_MAX
#endif
/************************************************************************************
* Public Types
************************************************************************************/
/************************************************************************************
* Public Data
************************************************************************************/
/************************************************************************************
* Public Functions
************************************************************************************/
#endif /* __ARCH_ARM_INCLUDE_SAM34_CHIP_H */

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@ -1,123 +0,0 @@
/****************************************************************************************
* arch/arm/include/sam34/irq.h
*
* Copyright (C) 2009-2011, 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************************/
/* This file should never be included directed but, rather, only indirectly through
* nuttx/irq.h
*/
#ifndef __ARCH_ARM_INCLUDE_SAM34_IRQ_H
#define __ARCH_ARM_INCLUDE_SAM34_IRQ_H
/****************************************************************************************
* Included Files
****************************************************************************************/
#include <nuttx/config.h>
#include <arch/sam34/chip.h>
/****************************************************************************************
* Pre-processor Definitions
****************************************************************************************/
/* IRQ numbers. The IRQ number corresponds vector number and hence map directly to
* bits in the NVIC. This does, however, waste several words of memory in the IRQ
* to handle mapping tables.
*/
/* Common Processor Exceptions (vectors 0-15) */
#define SAM_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG) */
/* Vector 0: Reset stack pointer value */
/* Vector 1: Reset (not handler as an IRQ) */
#define SAM_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */
#define SAM_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */
#define SAM_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */
#define SAM_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */
#define SAM_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */
#define SAM_IRQ_SVCALL (11) /* Vector 11: SVC call */
#define SAM_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */
/* Vector 13: Reserved */
#define SAM_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */
#define SAM_IRQ_SYSTICK (15) /* Vector 15: System tick */
/* Chip-Specific External interrupts */
#define SAM_IRQ_EXTINT (16) /* Vector number of the first external interrupt */
#if defined(CONFIG_ARCH_CHIP_SAM3U)
# include <arch/sam34/sam3u_irq.h>
#elif defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A)
# include <arch/sam34/sam3x_irq.h>
#elif defined(CONFIG_ARCH_CHIP_SAM4L)
# include <arch/sam34/sam4l_irq.h>
#elif defined(CONFIG_ARCH_CHIP_SAM4S)
# include <arch/sam34/sam4s_irq.h>
#elif defined(CONFIG_ARCH_CHIP_SAM4E)
# include <arch/sam34/sam4e_irq.h>
#elif defined(CONFIG_ARCH_CHIP_SAM4CM)
# include <arch/sam34/sam4cm_irq.h>
#else
# error Unrecognized SAM architecture
#endif
/****************************************************************************************
* Public Types
****************************************************************************************/
#ifndef __ASSEMBLY__
/****************************************************************************************
* Public Data
****************************************************************************************/
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************************
* Public Function Prototypes
****************************************************************************************/
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif
#endif /* __ARCH_ARM_INCLUDE_SAM34_IRQ_H */

277
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@ -1,277 +0,0 @@
/****************************************************************************************
* arch/arm/include/sam34/sam3u_irq.h
*
* Copyright (C) 2009-2011, 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************************/
/* This file should never be included directed but, rather, only indirectly through
* nuttx/irq.h
*/
#ifndef __ARCH_ARM_INCLUDE_SAM34_SAM3U_IRQ_H
#define __ARCH_ARM_INCLUDE_SAM34_SAM3U_IRQ_H
/****************************************************************************************
* Included Files
****************************************************************************************/
/****************************************************************************************
* Pre-processor Definitions
****************************************************************************************/
/* SAM3U Peripheral Identifiers */
#define SAM_PID_SUPC (0) /* Supply Controller */
#define SAM_PID_RSTC (1) /* Reset Controller */
#define SAM_PID_RTC (2) /* Real Time Clock */
#define SAM_PID_RTT (3) /* Real Time Timer */
#define SAM_PID_WDT (4) /* Watchdog Timer */
#define SAM_PID_PMC (5) /* Power Management Controller */
#define SAM_PID_EEFC0 (6) /* Enhanced Embedded Flash Controller 0 */
#define SAM_PID_EEFC1 (7) /* Enhanced Embedded Flash Controller 1 */
#define SAM_PID_UART0 (8) /* Universal Asynchronous Receiver Transmitter 0 */
#define SAM_PID_SMC (9) /* Static Memory Controller */
#define SAM_PID_PIOA (10) /* Parallel I/O Controller A */
#define SAM_PID_PIOB (11) /* Parallel I/O Controller B */
#define SAM_PID_PIOC (12) /* Parallel I/O Controller C */
#define SAM_PID_USART0 (13) /* USART 0 */
#define SAM_PID_USART1 (14) /* USART 1 */
#define SAM_PID_USART2 (15) /* USART 2 */
#define SAM_PID_USART3 (16) /* USART 3 */
#define SAM_PID_HSMCI (17) /* High Speed Multimedia Card Interface */
#define SAM_PID_TWI0 (18) /* Two-Wire Interface 0 */
#define SAM_PID_TWI1 (19) /* Two-Wire Interface 1 */
#define SAM_PID_SPI0 (20) /* Serial Peripheral Interface */
#define SAM_PID_SSC (21) /* Synchronous Serial Controller */
#define SAM_PID_TC0 (22) /* Timer Counter 0 */
#define SAM_PID_TC1 (23) /* Timer Counter 1 */
#define SAM_PID_TC2 (24) /* Timer Counter 2 */
#define SAM_PID_PWM (25) /* Pulse Width Modulation Controller */
#define SAM_PID_ADC12B (26) /* 12-bit ADC Controller */
#define SAM_PID_ADC (27) /* 10-bit ADC Controller */
#define SAM_PID_DMAC (28) /* DMA Controller */
#define SAM_PID_UDPHS (29) /* USB Device High Speed */
#define NR_PIDS (30) /* Number of peripheral identifiers */
/* External interrupts (vectors >= 16) */
#define SAM_IRQ_SUPC (SAM_IRQ_EXTINT+SAM_PID_SUPC) /* Supply Controller */
#define SAM_IRQ_RSTC (SAM_IRQ_EXTINT+SAM_PID_RSTC) /* Reset Controller */
#define SAM_IRQ_RTC (SAM_IRQ_EXTINT+SAM_PID_RTC) /* Real Time Clock */
#define SAM_IRQ_RTT (SAM_IRQ_EXTINT+SAM_PID_RTT) /* Real Time Timer */
#define SAM_IRQ_WDT (SAM_IRQ_EXTINT+SAM_PID_WDT) /* Watchdog Timer */
#define SAM_IRQ_PMC (SAM_IRQ_EXTINT+SAM_PID_PMC) /* Power Management Controller */
#define SAM_IRQ_EEFC0 (SAM_IRQ_EXTINT+SAM_PID_EEFC0) /* Enhanced Embedded Flash Controller 0 */
#define SAM_IRQ_EEFC1 (SAM_IRQ_EXTINT+SAM_PID_EEFC1) /* Enhanced Embedded Flash Controller 1 */
#define SAM_IRQ_UART0 (SAM_IRQ_EXTINT+SAM_PID_UART0) /* Universal Asynchronous Receiver Transmitter */
#define SAM_IRQ_SMC (SAM_IRQ_EXTINT+SAM_PID_SMC) /* Static Memory Controller */
#define SAM_IRQ_PIOA (SAM_IRQ_EXTINT+SAM_PID_PIOA) /* Parallel I/O Controller A */
#define SAM_IRQ_PIOB (SAM_IRQ_EXTINT+SAM_PID_PIOB) /* Parallel I/O Controller B */
#define SAM_IRQ_PIOC (SAM_IRQ_EXTINT+SAM_PID_PIOC) /* Parallel I/O Controller C */
#define SAM_IRQ_USART0 (SAM_IRQ_EXTINT+SAM_PID_USART0) /* USART 0 */
#define SAM_IRQ_USART1 (SAM_IRQ_EXTINT+SAM_PID_USART1) /* USART 1 */
#define SAM_IRQ_USART2 (SAM_IRQ_EXTINT+SAM_PID_USART2) /* USART 2 */
#define SAM_IRQ_USART3 (SAM_IRQ_EXTINT+SAM_PID_USART3) /* USART 3 */
#define SAM_IRQ_HSMCI (SAM_IRQ_EXTINT+SAM_PID_HSMCI) /* High Speed Multimedia Card Interface */
#define SAM_IRQ_TWI0 (SAM_IRQ_EXTINT+SAM_PID_TWI0) /* Two-Wire Interface 0 */
#define SAM_IRQ_TWI1 (SAM_IRQ_EXTINT+SAM_PID_TWI1) /* Two-Wire Interface 1 */
#define SAM_IRQ_SPI0 (SAM_IRQ_EXTINT+SAM_PID_SPI0) /* Serial Peripheral Interface */
#define SAM_IRQ_SSC (SAM_IRQ_EXTINT+SAM_PID_SSC) /* Synchronous Serial Controller */
#define SAM_IRQ_TC0 (SAM_IRQ_EXTINT+SAM_PID_TC0) /* Timer Counter 0 */
#define SAM_IRQ_TC1 (SAM_IRQ_EXTINT+SAM_PID_TC1) /* Timer Counter 1 */
#define SAM_IRQ_TC2 (SAM_IRQ_EXTINT+SAM_PID_TC2) /* Timer Counter 2 */
#define SAM_IRQ_PWM (SAM_IRQ_EXTINT+SAM_PID_PWM) /* Pulse Width Modulation Controller */
#define SAM_IRQ_ADC12B (SAM_IRQ_EXTINT+SAM_PID_ADC12B) /* 12-bit ADC Controller */
#define SAM_IRQ_ADC (SAM_IRQ_EXTINT+SAM_PID_ADC) /* 10-bit ADC Controller */
#define SAM_IRQ_DMAC (SAM_IRQ_EXTINT+SAM_PID_DMAC) /* DMA Controller */
#define SAM_IRQ_UDPHS (SAM_IRQ_EXTINT+SAM_PID_UDPHS) /* USB Device High Speed */
#define SAM_IRQ_NEXTINT NR_PIDS /* Total number of external interrupt numbers */
#define SAM_IRQ_NIRQS (SAM_IRQ_EXTINT+NR_PIDS) /* The number of real IRQs */
/* GPIO interrupts (derived from SAM_IRQ_PIOA/B/C) */
#ifdef CONFIG_SAM34_GPIOA_IRQ
# define SAM_IRQ_GPIOA_PINS (SAM_IRQ_EXTINT + SAM_IRQ_NEXTINT)
# define SAM_IRQ_PA0 (SAM_IRQ_GPIOA_PINS+0) /* GPIOA, PIN 0 */
# define SAM_IRQ_PA1 (SAM_IRQ_GPIOA_PINS+1) /* GPIOA, PIN 1 */
# define SAM_IRQ_PA2 (SAM_IRQ_GPIOA_PINS+2) /* GPIOA, PIN 2 */
# define SAM_IRQ_PA3 (SAM_IRQ_GPIOA_PINS+3) /* GPIOA, PIN 3 */
# define SAM_IRQ_PA4 (SAM_IRQ_GPIOA_PINS+4) /* GPIOA, PIN 4 */
# define SAM_IRQ_PA5 (SAM_IRQ_GPIOA_PINS+5) /* GPIOA, PIN 5 */
# define SAM_IRQ_PA6 (SAM_IRQ_GPIOA_PINS+6) /* GPIOA, PIN 6 */
# define SAM_IRQ_PA7 (SAM_IRQ_GPIOA_PINS+7) /* GPIOA, PIN 7 */
# define SAM_IRQ_PA8 (SAM_IRQ_GPIOA_PINS+8) /* GPIOA, PIN 8 */
# define SAM_IRQ_PA9 (SAM_IRQ_GPIOA_PINS+9) /* GPIOA, PIN 9 */
# define SAM_IRQ_PA10 (SAM_IRQ_GPIOA_PINS+10) /* GPIOA, PIN 10 */
# define SAM_IRQ_PA11 (SAM_IRQ_GPIOA_PINS+11) /* GPIOA, PIN 11 */
# define SAM_IRQ_PA12 (SAM_IRQ_GPIOA_PINS+12) /* GPIOA, PIN 12 */
# define SAM_IRQ_PA13 (SAM_IRQ_GPIOA_PINS+13) /* GPIOA, PIN 13 */
# define SAM_IRQ_PA14 (SAM_IRQ_GPIOA_PINS+14) /* GPIOA, PIN 14 */
# define SAM_IRQ_PA15 (SAM_IRQ_GPIOA_PINS+15) /* GPIOA, PIN 15 */
# define SAM_IRQ_PA16 (SAM_IRQ_GPIOA_PINS+16) /* GPIOA, PIN 16 */
# define SAM_IRQ_PA17 (SAM_IRQ_GPIOA_PINS+17) /* GPIOA, PIN 17 */
# define SAM_IRQ_PA18 (SAM_IRQ_GPIOA_PINS+18) /* GPIOA, PIN 18 */
# define SAM_IRQ_PA19 (SAM_IRQ_GPIOA_PINS+19) /* GPIOA, PIN 19 */
# define SAM_IRQ_PA20 (SAM_IRQ_GPIOA_PINS+20) /* GPIOA, PIN 20 */
# define SAM_IRQ_PA21 (SAM_IRQ_GPIOA_PINS+21) /* GPIOA, PIN 21 */
# define SAM_IRQ_PA22 (SAM_IRQ_GPIOA_PINS+22) /* GPIOA, PIN 22 */
# define SAM_IRQ_PA23 (SAM_IRQ_GPIOA_PINS+23) /* GPIOA, PIN 23 */
# define SAM_IRQ_PA24 (SAM_IRQ_GPIOA_PINS+24) /* GPIOA, PIN 24 */
# define SAM_IRQ_PA25 (SAM_IRQ_GPIOA_PINS+25) /* GPIOA, PIN 25 */
# define SAM_IRQ_PA26 (SAM_IRQ_GPIOA_PINS+26) /* GPIOA, PIN 26 */
# define SAM_IRQ_PA27 (SAM_IRQ_GPIOA_PINS+27) /* GPIOA, PIN 27 */
# define SAM_IRQ_PA28 (SAM_IRQ_GPIOA_PINS+28) /* GPIOA, PIN 28 */
# define SAM_IRQ_PA29 (SAM_IRQ_GPIOA_PINS+29) /* GPIOA, PIN 29 */
# define SAM_IRQ_PA30 (SAM_IRQ_GPIOA_PINS+30) /* GPIOA, PIN 30 */
# define SAM_IRQ_PA31 (SAM_IRQ_GPIOA_PINS+31) /* GPIOA, PIN 31 */
# define SAM_NGPIOAIRQS 32
#else
# define SAM_NGPIOAIRQS 0
#endif
#ifdef CONFIG_SAM34_GPIOB_IRQ
# define SAM_IRQ_GPIOB_PINS (SAM_IRQ_EXTINT + SAM_IRQ_NEXTINT + SAM_NGPIOAIRQS)
# define SAM_IRQ_PB0 (SAM_IRQ_GPIOB_PINS+0) /* GPIOB, PIN 0 */
# define SAM_IRQ_PB1 (SAM_IRQ_GPIOB_PINS+1) /* GPIOB, PIN 1 */
# define SAM_IRQ_PB2 (SAM_IRQ_GPIOB_PINS+2) /* GPIOB, PIN 2 */
# define SAM_IRQ_PB3 (SAM_IRQ_GPIOB_PINS+3) /* GPIOB, PIN 3 */
# define SAM_IRQ_PB4 (SAM_IRQ_GPIOB_PINS+4) /* GPIOB, PIN 4 */
# define SAM_IRQ_PB5 (SAM_IRQ_GPIOB_PINS+5) /* GPIOB, PIN 5 */
# define SAM_IRQ_PB6 (SAM_IRQ_GPIOB_PINS+6) /* GPIOB, PIN 6 */
# define SAM_IRQ_PB7 (SAM_IRQ_GPIOB_PINS+7) /* GPIOB, PIN 7 */
# define SAM_IRQ_PB8 (SAM_IRQ_GPIOB_PINS+8) /* GPIOB, PIN 8 */
# define SAM_IRQ_PB9 (SAM_IRQ_GPIOB_PINS+9) /* GPIOB, PIN 9 */
# define SAM_IRQ_PB10 (SAM_IRQ_GPIOB_PINS+10) /* GPIOB, PIN 10 */
# define SAM_IRQ_PB11 (SAM_IRQ_GPIOB_PINS+11) /* GPIOB, PIN 11 */
# define SAM_IRQ_PB12 (SAM_IRQ_GPIOB_PINS+12) /* GPIOB, PIN 12 */
# define SAM_IRQ_PB13 (SAM_IRQ_GPIOB_PINS+13) /* GPIOB, PIN 13 */
# define SAM_IRQ_PB14 (SAM_IRQ_GPIOB_PINS+14) /* GPIOB, PIN 14 */
# define SAM_IRQ_PB15 (SAM_IRQ_GPIOB_PINS+15) /* GPIOB, PIN 15 */
# define SAM_IRQ_PB16 (SAM_IRQ_GPIOB_PINS+16) /* GPIOB, PIN 16 */
# define SAM_IRQ_PB17 (SAM_IRQ_GPIOB_PINS+17) /* GPIOB, PIN 17 */
# define SAM_IRQ_PB18 (SAM_IRQ_GPIOB_PINS+18) /* GPIOB, PIN 18 */
# define SAM_IRQ_PB19 (SAM_IRQ_GPIOB_PINS+19) /* GPIOB, PIN 19 */
# define SAM_IRQ_PB20 (SAM_IRQ_GPIOB_PINS+20) /* GPIOB, PIN 20 */
# define SAM_IRQ_PB21 (SAM_IRQ_GPIOB_PINS+21) /* GPIOB, PIN 21 */
# define SAM_IRQ_PB22 (SAM_IRQ_GPIOB_PINS+22) /* GPIOB, PIN 22 */
# define SAM_IRQ_PB23 (SAM_IRQ_GPIOB_PINS+23) /* GPIOB, PIN 23 */
# define SAM_IRQ_PB24 (SAM_IRQ_GPIOB_PINS+24) /* GPIOB, PIN 24 */
# define SAM_IRQ_PB25 (SAM_IRQ_GPIOB_PINS+25) /* GPIOB, PIN 25 */
# define SAM_IRQ_PB26 (SAM_IRQ_GPIOB_PINS+26) /* GPIOB, PIN 26 */
# define SAM_IRQ_PB27 (SAM_IRQ_GPIOB_PINS+27) /* GPIOB, PIN 27 */
# define SAM_IRQ_PB28 (SAM_IRQ_GPIOB_PINS+28) /* GPIOB, PIN 28 */
# define SAM_IRQ_PB29 (SAM_IRQ_GPIOB_PINS+29) /* GPIOB, PIN 29 */
# define SAM_IRQ_PB30 (SAM_IRQ_GPIOB_PINS+30) /* GPIOB, PIN 30 */
# define SAM_IRQ_PB31 (SAM_IRQ_GPIOB_PINS+31) /* GPIOB, PIN 31 */
# define SAM_NGPIOBIRQS 32
#else
# define SAM_NGPIOBIRQS 0
#endif
#ifdef CONFIG_SAM34_GPIOC_IRQ
# define SAM_IRQ_GPIOC_PINS (SAM_IRQ_EXTINT + SAM_IRQ_NEXTINT + SAM_NGPIOAIRQS + SAM_NGPIOBIRQS)
# define SAM_IRQ_PC0 (SAM_IRQ_GPIOC_PINS+0) /* GPIOC, PIN 0 */
# define SAM_IRQ_PC1 (SAM_IRQ_GPIOC_PINS+1) /* GPIOC, PIN 1 */
# define SAM_IRQ_PC2 (SAM_IRQ_GPIOC_PINS+2) /* GPIOC, PIN 2 */
# define SAM_IRQ_PC3 (SAM_IRQ_GPIOC_PINS+3) /* GPIOC, PIN 3 */
# define SAM_IRQ_PC4 (SAM_IRQ_GPIOC_PINS+4) /* GPIOC, PIN 4 */
# define SAM_IRQ_PC5 (SAM_IRQ_GPIOC_PINS+5) /* GPIOC, PIN 5 */
# define SAM_IRQ_PC6 (SAM_IRQ_GPIOC_PINS+6) /* GPIOC, PIN 6 */
# define SAM_IRQ_PC7 (SAM_IRQ_GPIOC_PINS+7) /* GPIOC, PIN 7 */
# define SAM_IRQ_PC8 (SAM_IRQ_GPIOC_PINS+8) /* GPIOC, PIN 8 */
# define SAM_IRQ_PC9 (SAM_IRQ_GPIOC_PINS+9) /* GPIOC, PIN 9 */
# define SAM_IRQ_PC10 (SAM_IRQ_GPIOC_PINS+10) /* GPIOC, PIN 10 */
# define SAM_IRQ_PC11 (SAM_IRQ_GPIOC_PINS+11) /* GPIOC, PIN 11 */
# define SAM_IRQ_PC12 (SAM_IRQ_GPIOC_PINS+12) /* GPIOC, PIN 12 */
# define SAM_IRQ_PC13 (SAM_IRQ_GPIOC_PINS+13) /* GPIOC, PIN 13 */
# define SAM_IRQ_PC14 (SAM_IRQ_GPIOC_PINS+14) /* GPIOC, PIN 14 */
# define SAM_IRQ_PC15 (SAM_IRQ_GPIOC_PINS+15) /* GPIOC, PIN 15 */
# define SAM_IRQ_PC16 (SAM_IRQ_GPIOC_PINS+16) /* GPIOC, PIN 16 */
# define SAM_IRQ_PC17 (SAM_IRQ_GPIOC_PINS+17) /* GPIOC, PIN 17 */
# define SAM_IRQ_PC18 (SAM_IRQ_GPIOC_PINS+18) /* GPIOC, PIN 18 */
# define SAM_IRQ_PC19 (SAM_IRQ_GPIOC_PINS+19) /* GPIOC, PIN 19 */
# define SAM_IRQ_PC20 (SAM_IRQ_GPIOC_PINS+20) /* GPIOC, PIN 20 */
# define SAM_IRQ_PC21 (SAM_IRQ_GPIOC_PINS+21) /* GPIOC, PIN 21 */
# define SAM_IRQ_PC22 (SAM_IRQ_GPIOC_PINS+22) /* GPIOC, PIN 22 */
# define SAM_IRQ_PC23 (SAM_IRQ_GPIOC_PINS+23) /* GPIOC, PIN 23 */
# define SAM_IRQ_PC24 (SAM_IRQ_GPIOC_PINS+24) /* GPIOC, PIN 24 */
# define SAM_IRQ_PC25 (SAM_IRQ_GPIOC_PINS+25) /* GPIOC, PIN 25 */
# define SAM_IRQ_PC26 (SAM_IRQ_GPIOC_PINS+26) /* GPIOC, PIN 26 */
# define SAM_IRQ_PC27 (SAM_IRQ_GPIOC_PINS+27) /* GPIOC, PIN 27 */
# define SAM_IRQ_PC28 (SAM_IRQ_GPIOC_PINS+28) /* GPIOC, PIN 28 */
# define SAM_IRQ_PC29 (SAM_IRQ_GPIOC_PINS+29) /* GPIOC, PIN 29 */
# define SAM_IRQ_PC30 (SAM_IRQ_GPIOC_PINS+30) /* GPIOC, PIN 30 */
# define SAM_IRQ_PC31 (SAM_IRQ_GPIOC_PINS+31) /* GPIOC, PIN 31 */
# define SAM_NGPIOCIRQS 32
#else
# define SAM_NGPIOCIRQS 0
#endif
/* Total number of IRQ numbers */
#define NR_VECTORS SAM_IRQ_NIRQS
#define NR_IRQS (SAM_IRQ_EXTINT + SAM_IRQ_NEXTINT + \
SAM_NGPIOAIRQS + SAM_NGPIOBIRQS + SAM_NGPIOCIRQS)
/****************************************************************************************
* Public Types
****************************************************************************************/
/****************************************************************************************
* Inline functions
****************************************************************************************/
/****************************************************************************************
* Public Variables
****************************************************************************************/
/****************************************************************************************
* Public Function Prototypes
****************************************************************************************/
#ifndef __ASSEMBLY__
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif
#endif /* __ARCH_ARM_INCLUDE_SAM34_SAM3U_IRQ_H */

432
arch/arm/include/sam34/sam3x_irq.h
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@ -1,432 +0,0 @@
/****************************************************************************************
* arch/arm/include/sam34/sam3x_irq.h
*
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************************/
/* This file should never be included directed but, rather, only indirectly through
* nuttx/irq.h
*/
#ifndef __ARCH_ARM_INCLUDE_SAM34_SAM3X_IRQ_H
#define __ARCH_ARM_INCLUDE_SAM34_SAM3X_IRQ_H
/****************************************************************************************
* Included Files
****************************************************************************************/
/****************************************************************************************
* Pre-processor Definitions
****************************************************************************************/
/* SAM3X Peripheral Identifiers */
#define SAM_PID_SUPC (0) /* Supply Controller */
#define SAM_PID_RSTC (1) /* Reset Controller */
#define SAM_PID_RTC (2) /* Real Time Clock */
#define SAM_PID_RTT (3) /* Real Time Timer */
#define SAM_PID_WDT (4) /* Watchdog Timer */
#define SAM_PID_PMC (5) /* Power Management Controller */
#define SAM_PID_EEFC0 (6) /* Enhanced Embedded Flash Controller 0 */
#define SAM_PID_EEFC1 (7) /* Enhanced Embedded Flash Controller 1 */
#define SAM_PID_UART0 (8) /* Universal Asynchronous Receiver Transmitter 0 */
#define SAM_PID_SMC (9) /* Static Memory Controller */
#define SAM_PID_SDRAMC (10) /* Synchronous Dynamic RAM Controller */
#define SAM_PID_PIOA (11) /* Parallel I/O Controller A */
#define SAM_PID_PIOB (12) /* Parallel I/O Controller B */
#define SAM_PID_PIOC (13) /* Parallel I/O Controller C */
#define SAM_PID_PIOD (14) /* Parallel I/O Controller D */
#define SAM_PID_PIOE (15) /* Parallel I/O Controller E */
#define SAM_PID_PIOF (16) /* Parallel I/O Controller F */
#define SAM_PID_USART0 (17) /* USART 0 */
#define SAM_PID_USART1 (18) /* USART 1 */
#define SAM_PID_USART2 (19) /* USART 2 */
#define SAM_PID_USART3 (20) /* USART 3 */
#define SAM_PID_HSMCI (21) /* High Speed Multimedia Card Interface */
#define SAM_PID_TWI0 (22) /* Two-Wire Interface 0 */
#define SAM_PID_TWI1 (23) /* Two-Wire Interface 1 */
#define SAM_PID_SPI0 (24) /* Serial Peripheral Interface 0 */
#define SAM_PID_SPI1 (25) /* Serial Peripheral Interface 2 */
#define SAM_PID_SSC (26) /* Synchronous Serial Controller */
#define SAM_PID_TC0 (27) /* Timer Counter 0 */
#define SAM_PID_TC1 (28) /* Timer Counter 1 */
#define SAM_PID_TC2 (29) /* Timer Counter 2 */
#define SAM_PID_TC3 (30) /* Timer Counter 3 */
#define SAM_PID_TC4 (31) /* Timer Counter 4 */
#define SAM_PID_TC5 (32) /* Timer Counter 5 */
#define SAM_PID_TC6 (33) /* Timer Counter 6 */
#define SAM_PID_TC7 (34) /* Timer Counter 7 */
#define SAM_PID_TC8 (35) /* Timer Counter 8 */
#define SAM_PID_PWM (36) /* Pulse Width Modulation Controller */
#define SAM_PID_ADC (37) /* ADC Controller */
#define SAM_PID_DACC (38) /* DAC Controller */
#define SAM_PID_DMAC (39) /* DMA Controller */
#define SAM_PID_UOTGHS (40) /* USB OTG High Speed */
#define SAM_PID_TRNG (41) /* True Random Number Generator */
#define SAM_PID_EMAC (42) /* Ethernet MAC */
#define SAM_PID_CAN0 (43) /* CAN Controller 0 */
#define SAM_PID_CAN1 (44) /* CAN Controller 1 */
#define NR_PIDS (45) /* Number of peripheral identifiers */
/* External interrupts (vectors >= 16) */
#define SAM_IRQ_SUPC (SAM_IRQ_EXTINT+SAM_PID_SUPC) /* Supply Controller */
#define SAM_IRQ_RSTC (SAM_IRQ_EXTINT+SAM_PID_RSTC) /* Reset Controller */
#define SAM_IRQ_RTC (SAM_IRQ_EXTINT+SAM_PID_RTC) /* Real Time Clock */
#define SAM_IRQ_RTT (SAM_IRQ_EXTINT+SAM_PID_RTT) /* Real Time Timer */
#define SAM_IRQ_WDT (SAM_IRQ_EXTINT+SAM_PID_WDT) /* Watchdog Timer */
#define SAM_IRQ_PMC (SAM_IRQ_EXTINT+SAM_PID_PMC) /* Power Management Controller */
#define SAM_IRQ_EEFC0 (SAM_IRQ_EXTINT+SAM_PID_EEFC0) /* Enhanced Embedded Flash Controller 0 */
#define SAM_IRQ_EEFC1 (SAM_IRQ_EXTINT+SAM_PID_EEFC1) /* Enhanced Embedded Flash Controller 1 */
#define SAM_IRQ_UART0 (SAM_IRQ_EXTINT+SAM_PID_UART0) /* Universal Asynchronous Receiver Transmitter */
#define SAM_IRQ_SMC (SAM_IRQ_EXTINT+SAM_PID_SMC) /* Static Memory Controller */
#define SAM_IRQ_SDRAMC (SAM_IRQ_EXTINT+SAM_PID_SDRAMC) /* Synchronous Dynamic RAM Controller */
#define SAM_IRQ_PIOA (SAM_IRQ_EXTINT+SAM_PID_PIOA) /* Parallel I/O Controller A */
#define SAM_IRQ_PIOB (SAM_IRQ_EXTINT+SAM_PID_PIOB) /* Parallel I/O Controller B */
#define SAM_IRQ_PIOC (SAM_IRQ_EXTINT+SAM_PID_PIOC) /* Parallel I/O Controller C */
#define SAM_IRQ_PIOD (SAM_IRQ_EXTINT+SAM_PID_PIOD) /* Parallel I/O Controller D */
#define SAM_IRQ_PIOE (SAM_IRQ_EXTINT+SAM_PID_PIOE) /* Parallel I/O Controller E */
#define SAM_IRQ_PIOF (SAM_IRQ_EXTINT+SAM_PID_PIOF) /* Parallel I/O Controller F */
#define SAM_IRQ_USART0 (SAM_IRQ_EXTINT+SAM_PID_USART0) /* USART 0 */
#define SAM_IRQ_USART1 (SAM_IRQ_EXTINT+SAM_PID_USART1) /* USART 1 */
#define SAM_IRQ_USART2 (SAM_IRQ_EXTINT+SAM_PID_USART2) /* USART 2 */
#define SAM_IRQ_USART3 (SAM_IRQ_EXTINT+SAM_PID_USART3) /* USART 3 */
#define SAM_IRQ_HSMCI (SAM_IRQ_EXTINT+SAM_PID_HSMCI) /* High Speed Multimedia Card Interface */
#define SAM_IRQ_TWI0 (SAM_IRQ_EXTINT+SAM_PID_TWI0) /* Two-Wire Interface 0 */
#define SAM_IRQ_TWI1 (SAM_IRQ_EXTINT+SAM_PID_TWI1) /* Two-Wire Interface 1 */
#define SAM_IRQ_SPI0 (SAM_IRQ_EXTINT+SAM_PID_SPI0) /* Serial Peripheral Interface 0 */
#define SAM_IRQ_SPI1 (SAM_IRQ_EXTINT+SAM_PID_SPI1) /* Serial Peripheral Interface 1 */
#define SAM_IRQ_SSC (SAM_IRQ_EXTINT+SAM_PID_SSC) /* Synchronous Serial Controller */
#define SAM_IRQ_TC0 (SAM_IRQ_EXTINT+SAM_PID_TC0) /* Timer Counter 0 */
#define SAM_IRQ_TC1 (SAM_IRQ_EXTINT+SAM_PID_TC1) /* Timer Counter 1 */
#define SAM_IRQ_TC2 (SAM_IRQ_EXTINT+SAM_PID_TC2) /* Timer Counter 2 */
#define SAM_IRQ_TC3 (SAM_IRQ_EXTINT+SAM_PID_TC3) /* Timer Counter 3 */
#define SAM_IRQ_TC4 (SAM_IRQ_EXTINT+SAM_PID_TC4) /* Timer Counter 4 */
#define SAM_IRQ_TC5 (SAM_IRQ_EXTINT+SAM_PID_TC5) /* Timer Counter 5 */
#define SAM_IRQ_TC6 (SAM_IRQ_EXTINT+SAM_PID_TC6) /* Timer Counter 6 */
#define SAM_IRQ_TC7 (SAM_IRQ_EXTINT+SAM_PID_TC7) /* Timer Counter 7 */
#define SAM_IRQ_TC8 (SAM_IRQ_EXTINT+SAM_PID_TC8) /* Timer Counter 8 */
#define SAM_IRQ_PWM (SAM_IRQ_EXTINT+SAM_PID_PWM) /* Pulse Width Modulation Controller */
#define SAM_IRQ_ADC (SAM_IRQ_EXTINT+SAM_PID_ADC) /* ADC Controller */
#define SAM_IRQ_DACC (SAM_IRQ_EXTINT+SAM_PID_DACC) /* DAC Controller */
#define SAM_IRQ_DMAC (SAM_IRQ_EXTINT+SAM_PID_DMAC) /* DMA Controller */
#define SAM_IRQ_UOTGHS (SAM_IRQ_EXTINT+SAM_PID_UOTGHS) /* USB OTG High Speed */
#define SAM_IRQ_TRNG (SAM_IRQ_EXTINT+SAM_PID_TRNG) /* True Random Number Generator */
#define SAM_IRQ_EMAC (SAM_IRQ_EXTINT+SAM_PID_EMAC) /* Ethernet MAC */
#define SAM_IRQ_CAN0 (SAM_IRQ_EXTINT+SAM_PID_CAN0) /* CAN Controller 0 */
#define SAM_IRQ_CAN1 (SAM_IRQ_EXTINT+SAM_PID_CAN1) /* CAN Controller 1 */
#define SAM_IRQ_NEXTINT NR_PIDS /* Number of external interrupts */
#define SAM_IRQ_NIRQS (SAM_IRQ_EXTINT+NR_PIDS) /* The number of real IRQs */
/* GPIO interrupts (derived from SAM_IRQ_PIOA/B/C/D/E/F) */
#ifdef CONFIG_SAM34_GPIOA_IRQ
# define SAM_IRQ_GPIOA_PINS (SAM_IRQ_EXTINT + SAM_IRQ_NEXTINT)
# define SAM_IRQ_PA0 (SAM_IRQ_GPIOA_PINS+0) /* GPIOA, PIN 0 */
# define SAM_IRQ_PA1 (SAM_IRQ_GPIOA_PINS+1) /* GPIOA, PIN 1 */
# define SAM_IRQ_PA2 (SAM_IRQ_GPIOA_PINS+2) /* GPIOA, PIN 2 */
# define SAM_IRQ_PA3 (SAM_IRQ_GPIOA_PINS+3) /* GPIOA, PIN 3 */
# define SAM_IRQ_PA4 (SAM_IRQ_GPIOA_PINS+4) /* GPIOA, PIN 4 */
# define SAM_IRQ_PA5 (SAM_IRQ_GPIOA_PINS+5) /* GPIOA, PIN 5 */
# define SAM_IRQ_PA6 (SAM_IRQ_GPIOA_PINS+6) /* GPIOA, PIN 6 */
# define SAM_IRQ_PA7 (SAM_IRQ_GPIOA_PINS+7) /* GPIOA, PIN 7 */
# define SAM_IRQ_PA8 (SAM_IRQ_GPIOA_PINS+8) /* GPIOA, PIN 8 */
# define SAM_IRQ_PA9 (SAM_IRQ_GPIOA_PINS+9) /* GPIOA, PIN 9 */
# define SAM_IRQ_PA10 (SAM_IRQ_GPIOA_PINS+10) /* GPIOA, PIN 10 */
# define SAM_IRQ_PA11 (SAM_IRQ_GPIOA_PINS+11) /* GPIOA, PIN 11 */
# define SAM_IRQ_PA12 (SAM_IRQ_GPIOA_PINS+12) /* GPIOA, PIN 12 */
# define SAM_IRQ_PA13 (SAM_IRQ_GPIOA_PINS+13) /* GPIOA, PIN 13 */
# define SAM_IRQ_PA14 (SAM_IRQ_GPIOA_PINS+14) /* GPIOA, PIN 14 */
# define SAM_IRQ_PA15 (SAM_IRQ_GPIOA_PINS+15) /* GPIOA, PIN 15 */
# define SAM_IRQ_PA16 (SAM_IRQ_GPIOA_PINS+16) /* GPIOA, PIN 16 */
# define SAM_IRQ_PA17 (SAM_IRQ_GPIOA_PINS+17) /* GPIOA, PIN 17 */
# define SAM_IRQ_PA18 (SAM_IRQ_GPIOA_PINS+18) /* GPIOA, PIN 18 */
# define SAM_IRQ_PA19 (SAM_IRQ_GPIOA_PINS+19) /* GPIOA, PIN 19 */
# define SAM_IRQ_PA20 (SAM_IRQ_GPIOA_PINS+20) /* GPIOA, PIN 20 */
# define SAM_IRQ_PA21 (SAM_IRQ_GPIOA_PINS+21) /* GPIOA, PIN 21 */
# define SAM_IRQ_PA22 (SAM_IRQ_GPIOA_PINS+22) /* GPIOA, PIN 22 */
# define SAM_IRQ_PA23 (SAM_IRQ_GPIOA_PINS+23) /* GPIOA, PIN 23 */
# define SAM_IRQ_PA24 (SAM_IRQ_GPIOA_PINS+24) /* GPIOA, PIN 24 */
# define SAM_IRQ_PA25 (SAM_IRQ_GPIOA_PINS+25) /* GPIOA, PIN 25 */
# define SAM_IRQ_PA26 (SAM_IRQ_GPIOA_PINS+26) /* GPIOA, PIN 26 */
# define SAM_IRQ_PA27 (SAM_IRQ_GPIOA_PINS+27) /* GPIOA, PIN 27 */
# define SAM_IRQ_PA28 (SAM_IRQ_GPIOA_PINS+28) /* GPIOA, PIN 28 */
# define SAM_IRQ_PA29 (SAM_IRQ_GPIOA_PINS+29) /* GPIOA, PIN 29 */
# define SAM_IRQ_PA30 (SAM_IRQ_GPIOA_PINS+30) /* GPIOA, PIN 30 */
# define SAM_IRQ_PA31 (SAM_IRQ_GPIOA_PINS+31) /* GPIOA, PIN 31 */
# define SAM_NGPIOAIRQS 32
#else
# define SAM_NGPIOAIRQS 0
#endif
#ifdef CONFIG_SAM34_GPIOB_IRQ
# define SAM_IRQ_GPIOB_PINS (SAM_IRQ_EXTINT + SAM_IRQ_NEXTINT + SAM_NGPIOAIRQS)
# define SAM_IRQ_PB0 (SAM_IRQ_GPIOB_PINS+0) /* GPIOB, PIN 0 */
# define SAM_IRQ_PB1 (SAM_IRQ_GPIOB_PINS+1) /* GPIOB, PIN 1 */
# define SAM_IRQ_PB2 (SAM_IRQ_GPIOB_PINS+2) /* GPIOB, PIN 2 */
# define SAM_IRQ_PB3 (SAM_IRQ_GPIOB_PINS+3) /* GPIOB, PIN 3 */
# define SAM_IRQ_PB4 (SAM_IRQ_GPIOB_PINS+4) /* GPIOB, PIN 4 */
# define SAM_IRQ_PB5 (SAM_IRQ_GPIOB_PINS+5) /* GPIOB, PIN 5 */
# define SAM_IRQ_PB6 (SAM_IRQ_GPIOB_PINS+6) /* GPIOB, PIN 6 */
# define SAM_IRQ_PB7 (SAM_IRQ_GPIOB_PINS+7) /* GPIOB, PIN 7 */
# define SAM_IRQ_PB8 (SAM_IRQ_GPIOB_PINS+8) /* GPIOB, PIN 8 */
# define SAM_IRQ_PB9 (SAM_IRQ_GPIOB_PINS+9) /* GPIOB, PIN 9 */
# define SAM_IRQ_PB10 (SAM_IRQ_GPIOB_PINS+10) /* GPIOB, PIN 10 */
# define SAM_IRQ_PB11 (SAM_IRQ_GPIOB_PINS+11) /* GPIOB, PIN 11 */
# define SAM_IRQ_PB12 (SAM_IRQ_GPIOB_PINS+12) /* GPIOB, PIN 12 */
# define SAM_IRQ_PB13 (SAM_IRQ_GPIOB_PINS+13) /* GPIOB, PIN 13 */
# define SAM_IRQ_PB14 (SAM_IRQ_GPIOB_PINS+14) /* GPIOB, PIN 14 */
# define SAM_IRQ_PB15 (SAM_IRQ_GPIOB_PINS+15) /* GPIOB, PIN 15 */
# define SAM_IRQ_PB16 (SAM_IRQ_GPIOB_PINS+16) /* GPIOB, PIN 16 */
# define SAM_IRQ_PB17 (SAM_IRQ_GPIOB_PINS+17) /* GPIOB, PIN 17 */
# define SAM_IRQ_PB18 (SAM_IRQ_GPIOB_PINS+18) /* GPIOB, PIN 18 */
# define SAM_IRQ_PB19 (SAM_IRQ_GPIOB_PINS+19) /* GPIOB, PIN 19 */
# define SAM_IRQ_PB20 (SAM_IRQ_GPIOB_PINS+20) /* GPIOB, PIN 20 */
# define SAM_IRQ_PB21 (SAM_IRQ_GPIOB_PINS+21) /* GPIOB, PIN 21 */
# define SAM_IRQ_PB22 (SAM_IRQ_GPIOB_PINS+22) /* GPIOB, PIN 22 */
# define SAM_IRQ_PB23 (SAM_IRQ_GPIOB_PINS+23) /* GPIOB, PIN 23 */
# define SAM_IRQ_PB24 (SAM_IRQ_GPIOB_PINS+24) /* GPIOB, PIN 24 */
# define SAM_IRQ_PB25 (SAM_IRQ_GPIOB_PINS+25) /* GPIOB, PIN 25 */
# define SAM_IRQ_PB26 (SAM_IRQ_GPIOB_PINS+26) /* GPIOB, PIN 26 */
# define SAM_IRQ_PB27 (SAM_IRQ_GPIOB_PINS+27) /* GPIOB, PIN 27 */
# define SAM_IRQ_PB28 (SAM_IRQ_GPIOB_PINS+28) /* GPIOB, PIN 28 */
# define SAM_IRQ_PB29 (SAM_IRQ_GPIOB_PINS+29) /* GPIOB, PIN 29 */
# define SAM_IRQ_PB30 (SAM_IRQ_GPIOB_PINS+30) /* GPIOB, PIN 30 */
# define SAM_IRQ_PB31 (SAM_IRQ_GPIOB_PINS+31) /* GPIOB, PIN 31 */
# define SAM_NGPIOBIRQS 32
#else
# define SAM_NGPIOBIRQS 0
#endif
#ifdef CONFIG_SAM34_GPIOC_IRQ
# define SAM_IRQ_GPIOC_PINS (SAM_IRQ_EXTINT + SAM_IRQ_NEXTINT + SAM_NGPIOAIRQS + \
SAM_NGPIOBIRQS)
# define SAM_IRQ_PC0 (SAM_IRQ_GPIOC_PINS+0) /* GPIOC, PIN 0 */
# define SAM_IRQ_PC1 (SAM_IRQ_GPIOC_PINS+1) /* GPIOC, PIN 1 */
# define SAM_IRQ_PC2 (SAM_IRQ_GPIOC_PINS+2) /* GPIOC, PIN 2 */
# define SAM_IRQ_PC3 (SAM_IRQ_GPIOC_PINS+3) /* GPIOC, PIN 3 */
# define SAM_IRQ_PC4 (SAM_IRQ_GPIOC_PINS+4) /* GPIOC, PIN 4 */
# define SAM_IRQ_PC5 (SAM_IRQ_GPIOC_PINS+5) /* GPIOC, PIN 5 */
# define SAM_IRQ_PC6 (SAM_IRQ_GPIOC_PINS+6) /* GPIOC, PIN 6 */
# define SAM_IRQ_PC7 (SAM_IRQ_GPIOC_PINS+7) /* GPIOC, PIN 7 */
# define SAM_IRQ_PC8 (SAM_IRQ_GPIOC_PINS+8) /* GPIOC, PIN 8 */
# define SAM_IRQ_PC9 (SAM_IRQ_GPIOC_PINS+9) /* GPIOC, PIN 9 */
# define SAM_IRQ_PC10 (SAM_IRQ_GPIOC_PINS+10) /* GPIOC, PIN 10 */
# define SAM_IRQ_PC11 (SAM_IRQ_GPIOC_PINS+11) /* GPIOC, PIN 11 */
# define SAM_IRQ_PC12 (SAM_IRQ_GPIOC_PINS+12) /* GPIOC, PIN 12 */
# define SAM_IRQ_PC13 (SAM_IRQ_GPIOC_PINS+13) /* GPIOC, PIN 13 */
# define SAM_IRQ_PC14 (SAM_IRQ_GPIOC_PINS+14) /* GPIOC, PIN 14 */
# define SAM_IRQ_PC15 (SAM_IRQ_GPIOC_PINS+15) /* GPIOC, PIN 15 */
# define SAM_IRQ_PC16 (SAM_IRQ_GPIOC_PINS+16) /* GPIOC, PIN 16 */
# define SAM_IRQ_PC17 (SAM_IRQ_GPIOC_PINS+17) /* GPIOC, PIN 17 */
# define SAM_IRQ_PC18 (SAM_IRQ_GPIOC_PINS+18) /* GPIOC, PIN 18 */
# define SAM_IRQ_PC19 (SAM_IRQ_GPIOC_PINS+19) /* GPIOC, PIN 19 */
# define SAM_IRQ_PC20 (SAM_IRQ_GPIOC_PINS+20) /* GPIOC, PIN 20 */
# define SAM_IRQ_PC21 (SAM_IRQ_GPIOC_PINS+21) /* GPIOC, PIN 21 */
# define SAM_IRQ_PC22 (SAM_IRQ_GPIOC_PINS+22) /* GPIOC, PIN 22 */
# define SAM_IRQ_PC23 (SAM_IRQ_GPIOC_PINS+23) /* GPIOC, PIN 23 */
# define SAM_IRQ_PC24 (SAM_IRQ_GPIOC_PINS+24) /* GPIOC, PIN 24 */
# define SAM_IRQ_PC25 (SAM_IRQ_GPIOC_PINS+25) /* GPIOC, PIN 25 */
# define SAM_IRQ_PC26 (SAM_IRQ_GPIOC_PINS+26) /* GPIOC, PIN 26 */
# define SAM_IRQ_PC27 (SAM_IRQ_GPIOC_PINS+27) /* GPIOC, PIN 27 */
# define SAM_IRQ_PC28 (SAM_IRQ_GPIOC_PINS+28) /* GPIOC, PIN 28 */
# define SAM_IRQ_PC29 (SAM_IRQ_GPIOC_PINS+29) /* GPIOC, PIN 29 */
# define SAM_IRQ_PC30 (SAM_IRQ_GPIOC_PINS+30) /* GPIOC, PIN 30 */
# define SAM_IRQ_PC31 (SAM_IRQ_GPIOC_PINS+31) /* GPIOC, PIN 31 */
# define SAM_NGPIOCIRQS 32
#else
# define SAM_NGPIOCIRQS 0
#endif
#ifdef CONFIG_SAM34_GPIOD_IRQ
# define SAM_IRQ_GPIOD_PINS (SAM_IRQ_EXTINT + SAM_IRQ_NEXTINT + SAM_NGPIOAIRQS + \
SAM_NGPIOBIRQS + SAM_NGPIOCIRQS)
# define SAM_IRQ_PD0 (SAM_IRQ_GPIOD_PINS+0) /* GPIOD, PIN 0 */
# define SAM_IRQ_PD1 (SAM_IRQ_GPIOD_PINS+1) /* GPIOD, PIN 1 */
# define SAM_IRQ_PD2 (SAM_IRQ_GPIOD_PINS+2) /* GPIOD, PIN 2 */
# define SAM_IRQ_PD3 (SAM_IRQ_GPIOD_PINS+3) /* GPIOD, PIN 3 */
# define SAM_IRQ_PD4 (SAM_IRQ_GPIOD_PINS+4) /* GPIOD, PIN 4 */
# define SAM_IRQ_PD5 (SAM_IRQ_GPIOD_PINS+5) /* GPIOD, PIN 5 */
# define SAM_IRQ_PD6 (SAM_IRQ_GPIOD_PINS+6) /* GPIOD, PIN 6 */
# define SAM_IRQ_PD7 (SAM_IRQ_GPIOD_PINS+7) /* GPIOD, PIN 7 */
# define SAM_IRQ_PD8 (SAM_IRQ_GPIOD_PINS+8) /* GPIOD, PIN 8 */
# define SAM_IRQ_PD9 (SAM_IRQ_GPIOD_PINS+9) /* GPIOD, PIN 9 */
# define SAM_IRQ_PD10 (SAM_IRQ_GPIOD_PINS+10) /* GPIOD, PIN 10 */
# define SAM_IRQ_PD11 (SAM_IRQ_GPIOD_PINS+11) /* GPIOD, PIN 11 */
# define SAM_IRQ_PD12 (SAM_IRQ_GPIOD_PINS+12) /* GPIOD, PIN 12 */
# define SAM_IRQ_PD13 (SAM_IRQ_GPIOD_PINS+13) /* GPIOD, PIN 13 */
# define SAM_IRQ_PD14 (SAM_IRQ_GPIOD_PINS+14) /* GPIOD, PIN 14 */
# define SAM_IRQ_PD15 (SAM_IRQ_GPIOD_PINS+15) /* GPIOD, PIN 15 */
# define SAM_IRQ_PD16 (SAM_IRQ_GPIOD_PINS+16) /* GPIOD, PIN 16 */
# define SAM_IRQ_PD17 (SAM_IRQ_GPIOD_PINS+17) /* GPIOD, PIN 17 */
# define SAM_IRQ_PD18 (SAM_IRQ_GPIOD_PINS+18) /* GPIOD, PIN 18 */
# define SAM_IRQ_PD19 (SAM_IRQ_GPIOD_PINS+19) /* GPIOD, PIN 19 */
# define SAM_IRQ_PD20 (SAM_IRQ_GPIOD_PINS+20) /* GPIOD, PIN 20 */
# define SAM_IRQ_PD21 (SAM_IRQ_GPIOD_PINS+21) /* GPIOD, PIN 21 */
# define SAM_IRQ_PD22 (SAM_IRQ_GPIOD_PINS+22) /* GPIOD, PIN 22 */
# define SAM_IRQ_PD23 (SAM_IRQ_GPIOD_PINS+23) /* GPIOD, PIN 23 */
# define SAM_IRQ_PD24 (SAM_IRQ_GPIOD_PINS+24) /* GPIOD, PIN 24 */
# define SAM_IRQ_PD25 (SAM_IRQ_GPIOD_PINS+25) /* GPIOD, PIN 25 */
# define SAM_IRQ_PD26 (SAM_IRQ_GPIOD_PINS+26) /* GPIOD, PIN 26 */
# define SAM_IRQ_PD27 (SAM_IRQ_GPIOD_PINS+27) /* GPIOD, PIN 27 */
# define SAM_IRQ_PD28 (SAM_IRQ_GPIOD_PINS+28) /* GPIOD, PIN 28 */
# define SAM_IRQ_PD29 (SAM_IRQ_GPIOD_PINS+29) /* GPIOD, PIN 29 */
# define SAM_IRQ_PD30 (SAM_IRQ_GPIOD_PINS+30) /* GPIOD, PIN 30 */
# define SAM_IRQ_PD31 (SAM_IRQ_GPIOD_PINS+31) /* GPIOD, PIN 31 */
# define SAM_NGPIODIRQS 32
#else
# define SAM_NGPIODIRQS 0
#endif
#ifdef CONFIG_SAM34_GPIOE_IRQ
# define SAM_IRQ_GPIOE_PINS (SAM_IRQ_EXTINT + SAM_IRQ_NEXTINT + SAM_NGPIOAIRQS + \
SAM_NGPIOBIRQS + SAM_NGPIOCIRQS + SAM_NGPIODIRQS)
# define SAM_IRQ_PE0 (SAM_IRQ_GPIOE_PINS+0) /* GPIOE, PIN 0 */
# define SAM_IRQ_PE1 (SAM_IRQ_GPIOE_PINS+1) /* GPIOE, PIN 1 */
# define SAM_IRQ_PE2 (SAM_IRQ_GPIOE_PINS+2) /* GPIOE, PIN 2 */
# define SAM_IRQ_PE3 (SAM_IRQ_GPIOE_PINS+3) /* GPIOE, PIN 3 */
# define SAM_IRQ_PE4 (SAM_IRQ_GPIOE_PINS+4) /* GPIOE, PIN 4 */
# define SAM_IRQ_PE5 (SAM_IRQ_GPIOE_PINS+5) /* GPIOE, PIN 5 */
# define SAM_IRQ_PE6 (SAM_IRQ_GPIOE_PINS+6) /* GPIOE, PIN 6 */
# define SAM_IRQ_PE7 (SAM_IRQ_GPIOE_PINS+7) /* GPIOE, PIN 7 */
# define SAM_IRQ_PE8 (SAM_IRQ_GPIOE_PINS+8) /* GPIOE, PIN 8 */
# define SAM_IRQ_PE9 (SAM_IRQ_GPIOE_PINS+9) /* GPIOE, PIN 9 */
# define SAM_IRQ_PE10 (SAM_IRQ_GPIOE_PINS+10) /* GPIOE, PIN 10 */
# define SAM_IRQ_PE11 (SAM_IRQ_GPIOE_PINS+11) /* GPIOE, PIN 11 */
# define SAM_IRQ_PE12 (SAM_IRQ_GPIOE_PINS+12) /* GPIOE, PIN 12 */
# define SAM_IRQ_PE13 (SAM_IRQ_GPIOE_PINS+13) /* GPIOE, PIN 13 */
# define SAM_IRQ_PE14 (SAM_IRQ_GPIOE_PINS+14) /* GPIOE, PIN 14 */
# define SAM_IRQ_PE15 (SAM_IRQ_GPIOE_PINS+15) /* GPIOE, PIN 15 */
# define SAM_IRQ_PE16 (SAM_IRQ_GPIOE_PINS+16) /* GPIOE, PIN 16 */
# define SAM_IRQ_PE17 (SAM_IRQ_GPIOE_PINS+17) /* GPIOE, PIN 17 */
# define SAM_IRQ_PE18 (SAM_IRQ_GPIOE_PINS+18) /* GPIOE, PIN 18 */
# define SAM_IRQ_PE19 (SAM_IRQ_GPIOE_PINS+19) /* GPIOE, PIN 19 */
# define SAM_IRQ_PE20 (SAM_IRQ_GPIOE_PINS+20) /* GPIOE, PIN 20 */
# define SAM_IRQ_PE21 (SAM_IRQ_GPIOE_PINS+21) /* GPIOE, PIN 21 */
# define SAM_IRQ_PE22 (SAM_IRQ_GPIOE_PINS+22) /* GPIOE, PIN 22 */
# define SAM_IRQ_PE23 (SAM_IRQ_GPIOE_PINS+23) /* GPIOE, PIN 23 */
# define SAM_IRQ_PE24 (SAM_IRQ_GPIOE_PINS+24) /* GPIOE, PIN 24 */
# define SAM_IRQ_PE25 (SAM_IRQ_GPIOE_PINS+25) /* GPIOE, PIN 25 */
# define SAM_IRQ_PE26 (SAM_IRQ_GPIOE_PINS+26) /* GPIOE, PIN 26 */
# define SAM_IRQ_PE27 (SAM_IRQ_GPIOE_PINS+27) /* GPIOE, PIN 27 */
# define SAM_IRQ_PE28 (SAM_IRQ_GPIOE_PINS+28) /* GPIOE, PIN 28 */
# define SAM_IRQ_PE29 (SAM_IRQ_GPIOE_PINS+29) /* GPIOE, PIN 29 */
# define SAM_IRQ_PE30 (SAM_IRQ_GPIOE_PINS+30) /* GPIOE, PIN 30 */
# define SAM_IRQ_PE31 (SAM_IRQ_GPIOE_PINS+31) /* GPIOE, PIN 31 */
# define SAM_NGPIOEIRQS 32
#else
# define SAM_NGPIOEIRQS 0
#endif
#ifdef CONFIG_SAM34_GPIOF_IRQ
# define SAM_IRQ_GPIOF_PINS (SAM_IRQ_EXTINT + SAM_IRQ_NEXTINT + SAM_NGPIOAIRQS + \
SAM_NGPIOBIRQS + SAM_NGPIOCIRQS + SAM_NGPIODIRQS + \
SAM_NGPIOEIRQS)
# define SAM_IRQ_PF0 (SAM_IRQ_GPIOF_PINS+0) /* GPIOF, PIN 0 */
# define SAM_IRQ_PF1 (SAM_IRQ_GPIOF_PINS+1) /* GPIOF, PIN 1 */
# define SAM_IRQ_PF2 (SAM_IRQ_GPIOF_PINS+2) /* GPIOF, PIN 2 */
# define SAM_IRQ_PF3 (SAM_IRQ_GPIOF_PINS+3) /* GPIOF, PIN 3 */
# define SAM_IRQ_PF4 (SAM_IRQ_GPIOF_PINS+4) /* GPIOF, PIN 4 */
# define SAM_IRQ_PF5 (SAM_IRQ_GPIOF_PINS+5) /* GPIOF, PIN 5 */
# define SAM_IRQ_PF6 (SAM_IRQ_GPIOF_PINS+6) /* GPIOF, PIN 6 */
# define SAM_IRQ_PF7 (SAM_IRQ_GPIOF_PINS+7) /* GPIOF, PIN 7 */
# define SAM_IRQ_PF8 (SAM_IRQ_GPIOF_PINS+8) /* GPIOF, PIN 8 */
# define SAM_IRQ_PF9 (SAM_IRQ_GPIOF_PINS+9) /* GPIOF, PIN 9 */
# define SAM_IRQ_PF10 (SAM_IRQ_GPIOF_PINS+10) /* GPIOF, PIN 10 */
# define SAM_IRQ_PF11 (SAM_IRQ_GPIOF_PINS+11) /* GPIOF, PIN 11 */
# define SAM_IRQ_PF12 (SAM_IRQ_GPIOF_PINS+12) /* GPIOF, PIN 12 */
# define SAM_IRQ_PF13 (SAM_IRQ_GPIOF_PINS+13) /* GPIOF, PIN 13 */
# define SAM_IRQ_PF14 (SAM_IRQ_GPIOF_PINS+14) /* GPIOF, PIN 14 */
# define SAM_IRQ_PF15 (SAM_IRQ_GPIOF_PINS+15) /* GPIOF, PIN 15 */
# define SAM_IRQ_PF16 (SAM_IRQ_GPIOF_PINS+16) /* GPIOF, PIN 16 */
# define SAM_IRQ_PF17 (SAM_IRQ_GPIOF_PINS+17) /* GPIOF, PIN 17 */
# define SAM_IRQ_PF18 (SAM_IRQ_GPIOF_PINS+18) /* GPIOF, PIN 18 */
# define SAM_IRQ_PF19 (SAM_IRQ_GPIOF_PINS+19) /* GPIOF, PIN 19 */
# define SAM_IRQ_PF20 (SAM_IRQ_GPIOF_PINS+20) /* GPIOF, PIN 20 */
# define SAM_IRQ_PF21 (SAM_IRQ_GPIOF_PINS+21) /* GPIOF, PIN 21 */
# define SAM_IRQ_PF22 (SAM_IRQ_GPIOF_PINS+22) /* GPIOF, PIN 22 */
# define SAM_IRQ_PF23 (SAM_IRQ_GPIOF_PINS+23) /* GPIOF, PIN 23 */
# define SAM_IRQ_PF24 (SAM_IRQ_GPIOF_PINS+24) /* GPIOF, PIN 24 */
# define SAM_IRQ_PF25 (SAM_IRQ_GPIOF_PINS+25) /* GPIOF, PIN 25 */
# define SAM_IRQ_PF26 (SAM_IRQ_GPIOF_PINS+26) /* GPIOF, PIN 26 */
# define SAM_IRQ_PF27 (SAM_IRQ_GPIOF_PINS+27) /* GPIOF, PIN 27 */
# define SAM_IRQ_PF28 (SAM_IRQ_GPIOF_PINS+28) /* GPIOF, PIN 28 */
# define SAM_IRQ_PF29 (SAM_IRQ_GPIOF_PINS+29) /* GPIOF, PIN 29 */
# define SAM_IRQ_PF30 (SAM_IRQ_GPIOF_PINS+30) /* GPIOF, PIN 30 */
# define SAM_IRQ_PF31 (SAM_IRQ_GPIOF_PINS+31) /* GPIOF, PIN 31 */
# define SAM_NGPIOFIRQS 32
#else
# define SAM_NGPIOFIRQS 0
#endif
/* Total number of IRQ numbers */
#define NR_VECTORS SAM_IRQ_NIRQS
#define NR_IRQS (SAM_IRQ_EXTINT + SAM_IRQ_NEXTINT + \
SAM_NGPIOAIRQS + SAM_NGPIOBIRQS + SAM_NGPIOCIRQS + \
SAM_NGPIODIRQS + SAM_NGPIOEIRQS + SAM_NGPIOFIRQS)
/****************************************************************************************
* Public Types
****************************************************************************************/
/****************************************************************************************
* Inline functions
****************************************************************************************/
/****************************************************************************************
* Public Variables
****************************************************************************************/
/****************************************************************************************
* Public Function Prototypes
****************************************************************************************/
#ifndef __ASSEMBLY__
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif
#endif /* __ARCH_ARM_INCLUDE_SAM34_SAM3X_IRQ_H */

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arch/arm/include/sam34/sam4cm_irq.h
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@ -1,305 +0,0 @@
/****************************************************************************************
* arch/arm/include/sam34/sam4cm_irq.h
*
* Copyright (C) 2014 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************************/
/* This file should never be included directed but, rather, only indirectly through
* nuttx/irq.h
*/
#ifndef __ARCH_ARM_INCLUDE_SAM34_SAM4CM_IRQ_H
#define __ARCH_ARM_INCLUDE_SAM34_SAM4CM_IRQ_H
/****************************************************************************************
* Included Files
****************************************************************************************/
/****************************************************************************************
* Pre-processor Definitions
****************************************************************************************/
/* SAM4CM Peripheral Identifiers */
#define SAM_PID_SUPC (0) /* Supply Controller */
#define SAM_PID_RSTC (1) /* Reset Controller */
#define SAM_PID_RTC (2) /* Real Time Clock */
#define SAM_PID_RTT (3) /* Real Time Timer */
#define SAM_PID_WDT (4) /* Watchdog Timer */
#define SAM_PID_PMC (5) /* Power Management Controller */
#define SAM_PID_EEFC0 (6) /* Enhanced Embedded Flash Controller 0 */
#define SAM_PID_RESERVED_7 (7) /* Reserved */
#define SAM_PID_UART0 (8) /* Universal Asynchronous Receiver Transmitter 0 */
#define SAM_PID_RESERVED_9 (9) /* Reserved */
#define SAM_PID_SMC (10) /* Static Memory Controller */
#define SAM_PID_PIOA (11) /* Parallel I/O Controller A */
#define SAM_PID_PIOB (12) /* Parallel I/O Controller B */
#define SAM_PID_RESERVED_13 (13) /* Reserved */
#define SAM_PID_USART0 (14) /* USART 0 */
#define SAM_PID_USART1 (15) /* USART 1 */
#define SAM_PID_USART2 (16) /* USART 2 */
#define SAM_PID_USART3 (17) /* USART 3 */
#define SAM_PID_RESERVED_18 (18) /* Reserved */
#define SAM_PID_TWI0 (19) /* Two-Wire Interface 0 */
#define SAM_PID_TWI1 (20) /* Two-Wire Interface 1 */
#define SAM_PID_SPI0 (21) /* Serial Peripheral Interface */
#define SAM_PID_RESERVED_22 (22) /* Reserved */
#define SAM_PID_TC0 (23) /* Timer Counter 0 */
#define SAM_PID_TC1 (24) /* Timer Counter 1 */
#define SAM_PID_TC2 (25) /* Timer Counter 2 */
#define SAM_PID_TC3 (26) /* Timer Counter 3 */
#define SAM_PID_TC4 (27) /* Timer Counter 4 */
#define SAM_PID_TC5 (28) /* Timer Counter 5 */
#define SAM_PID_ADC (29) /* Analog To Digital Converter */
#define SAM_PID_ARM (30) /* FPU signals (only on CM4P1 core): FPIXC, FPOFC, FPUFC, FPIOC, FPDZC, FPIDC, FPIXC */
#define SAM_PID_IPC0 (31) /* Interprocessor communication 0 */
#define SAM_PID_SLCDC (32) /* Segment LCD Controller */
#define SAM_PID_TRNG (33) /* True Random Generator */
#define SAM_PID_ICM (34) /* Integrity Check Module */
#define SAM_PID_CPKCC (35) /* Classical Public Key Cryptography Controller */
#define SAM_PID_AES (36) /* Advanced Enhanced Standard */
#define SAM_PID_PIOC (37) /* Parallel I/O Controller C */
#define SAM_PID_UART1 (38) /* Universal Asynchronous Receiver Transmitter 1 */
#define SAM_PID_IPC1 (39) /* Interprocessor communication 1 */
#define SAM_PID_RESERVED_40 (40) /* Reserved */
#define SAM_PID_PWM (41) /* Pulse Width Modulation */
#define SAM_PID_SRAM (42) /* SRAM1 (I/D Code bus of CM4P1), SRAM2 (Systembus of CM4P1) */
#define SAM_PID_SMC1 (43) /* Static Memory Controller 1 */
#define NR_PIDS (44) /* Number of peripheral identifiers */
/* External interrupts (vectors >= 16) */
#define SAM_IRQ_SUPC (SAM_IRQ_EXTINT+SAM_PID_SUPC) /* PID 0: Supply Controller */
#define SAM_IRQ_RSTC (SAM_IRQ_EXTINT+SAM_PID_RSTC) /* PID 1: Reset Controller */
#define SAM_IRQ_RTC (SAM_IRQ_EXTINT+SAM_PID_RTC) /* PID 2: Real Time Clock */
#define SAM_IRQ_RTT (SAM_IRQ_EXTINT+SAM_PID_RTT) /* PID 3: Real Time Timer */
#define SAM_IRQ_WDT (SAM_IRQ_EXTINT+SAM_PID_WDT) /* PID 4: Watchdog Timer */
#define SAM_IRQ_PMC (SAM_IRQ_EXTINT+SAM_PID_PMC) /* PID 5: Power Management Controller */
#define SAM_IRQ_EEFC0 (SAM_IRQ_EXTINT+SAM_PID_EEFC0) /* PID 6: Enhanced Embedded Flash Controller 0 */
#define SAM_IRQ_RESERVED_7 (SAM_IRQ_EXTINT+SAM_PID_RESERVED_7) /* PID 7: Reserved */
#define SAM_IRQ_UART0 (SAM_IRQ_EXTINT+SAM_PID_UART0) /* PID 8: Universal Asynchronous Receiver Transmitter 0 */
#define SAM_IRQ_RESERVED_9 (SAM_IRQ_EXTINT+SAM_PID_RESERVED_9) /* PID 9: Reserved */
#define SAM_IRQ_SMC (SAM_IRQ_EXTINT+SAM_PID_SMC) /* PID 10: Static Memory Controller */
#define SAM_IRQ_PIOA (SAM_IRQ_EXTINT+SAM_PID_PIOA) /* PID 11: Parallel I/O Controller A */
#define SAM_IRQ_PIOB (SAM_IRQ_EXTINT+SAM_PID_PIOB) /* PID 12: Parallel I/O Controller B */
#define SAM_IRQ_RESERVED_13 (SAM_IRQ_EXTINT+SAM_PID_RESERVED_13) /* PID 13: Reserved */
#define SAM_IRQ_USART0 (SAM_IRQ_EXTINT+SAM_PID_USART0) /* PID 14: USART 0 */
#define SAM_IRQ_USART1 (SAM_IRQ_EXTINT+SAM_PID_USART1) /* PID 15: USART 1 */
#define SAM_IRQ_USART2 (SAM_IRQ_EXTINT+SAM_PID_USART2) /* PID 16: USART 2 */
#define SAM_IRQ_USART3 (SAM_IRQ_EXTINT+SAM_PID_USART3) /* PID 17: USART 3 */
#define SAM_IRQ_RESERVED_18 (SAM_IRQ_EXTINT+SAM_PID_RESERVED_18) /* PID 18: Reserved */
#define SAM_IRQ_TWI0 (SAM_IRQ_EXTINT+SAM_PID_TWI0) /* PID 19: Two-Wire Interface 0 */
#define SAM_IRQ_TWI1 (SAM_IRQ_EXTINT+SAM_PID_TWI1) /* PID 20: Two-Wire Interface 1 */
#define SAM_IRQ_SPI0 (SAM_IRQ_EXTINT+SAM_PID_SPI0) /* PIC 21: Serial Peripheral Interface */
#define SAM_IRQ_RESERVED_22 (SAM_IRQ_EXTINT+SAM_PID_RESERVED_22) /* PID 22: Reserved */
#define SAM_IRQ_TC0 (SAM_IRQ_EXTINT+SAM_PID_TC0) /* PID 23: Timer Counter 0 */
#define SAM_IRQ_TC1 (SAM_IRQ_EXTINT+SAM_PID_TC1) /* PID 24: Timer Counter 1 */
#define SAM_IRQ_TC2 (SAM_IRQ_EXTINT+SAM_PID_TC2) /* PID 25: Timer Counter 2 */
#define SAM_IRQ_TC3 (SAM_IRQ_EXTINT+SAM_PID_TC3) /* PID 26: Timer Counter 3 */
#define SAM_IRQ_TC4 (SAM_IRQ_EXTINT+SAM_PID_TC4) /* PID 27: Timer Counter 4 */
#define SAM_IRQ_TC5 (SAM_IRQ_EXTINT+SAM_PID_TC5) /* PID 28: Timer Counter 5 */
#define SAM_IRQ_ADC (SAM_IRQ_EXTINT+SAM_PID_ADC) /* PID 29: Analog To Digital Converter */
#define SAM_IRQ_ARM (SAM_IRQ_EXTINT+SAM_PID_ARM) /* PID 30: FPU signals (only on CM4P1 core): FPIXC, FPOFC, FPUFC, FPIOC, FPDZC, FPIDC, FPIXC */
#define SAM_IRQ_IPC0 (SAM_IRQ_EXTINT+SAM_PID_IPC0) /* PID 31: Interprocessor communication 0 */
#define SAM_IRQ_SLCDC (SAM_IRQ_EXTINT+SAM_PID_SLCDC) /* PID 32: Segment LCD Controller */
#define SAM_IRQ_TRNG (SAM_IRQ_EXTINT+SAM_PID_TRNG) /* PID 33: True Random Generator */
#define SAM_IRQ_ICM (SAM_IRQ_EXTINT+SAM_PID_ICM) /* PID 34: Integrity Check Module */
#define SAM_IRQ_CPKCC (SAM_IRQ_EXTINT+SAM_PID_CPKCC) /* PID 35: Classical Public Key Cryptography Controller */
#define SAM_IRQ_AES (SAM_IRQ_EXTINT+SAM_PID_AES) /* PID 36: Advanced Enhanced Standard */
#define SAM_IRQ_PIOC (SAM_IRQ_EXTINT+SAM_PID_PIOC) /* PID 37: Parallel I/O Controller C */
#define SAM_IRQ_UART1 (SAM_IRQ_EXTINT+SAM_PID_UART1) /* PID 38: Universal Asynchronous Receiver Transmitter 1 */
#define SAM_IRQ_IPC1 (SAM_IRQ_EXTINT+SAM_PID_IPC1) /* PID 39: Interprocessor communication 1 */
#define SAM_IRQ_RESERVED_40 (SAM_IRQ_EXTINT+SAM_PID_RESERVED_40) /* PID 40: Reserved */
#define SAM_IRQ_PWM (SAM_IRQ_EXTINT+SAM_PID_PWM) /* PID 41: Pulse Width Modulation */
#define SAM_IRQ_SRAM (SAM_IRQ_EXTINT+SAM_PID_SRAM) /* PID 42: SRAM1 (I/D Code bus of CM4P1), SRAM2 (Systembus of CM4P1) */
#define SAM_IRQ_SMC1 (SAM_IRQ_EXTINT+SAM_PID_SMC1) /* PID 43: Static Memory Controller 1 */
#define SAM_IRQ_NEXTINT NR_PIDS /* Total number of external interrupt numbers */
#define SAM_IRQ_NIRQS (SAM_IRQ_EXTINT + NR_PIDS) /* The number of real IRQs */
/* GPIO interrupts (derived from SAM_IRQ_PIOA/B/C) */
#ifdef CONFIG_GPIOA_IRQ
# define SAM_IRQ_GPIOA_PINS (SAM_IRQ_EXTINT + SAM_IRQ_NEXTINT)
# define SAM_IRQ_PA0 (SAM_IRQ_GPIOA_PINS+0) /* GPIOA, PIN 0 */
# define SAM_IRQ_PA1 (SAM_IRQ_GPIOA_PINS+1) /* GPIOA, PIN 1 */
# define SAM_IRQ_PA2 (SAM_IRQ_GPIOA_PINS+2) /* GPIOA, PIN 2 */
# define SAM_IRQ_PA3 (SAM_IRQ_GPIOA_PINS+3) /* GPIOA, PIN 3 */
# define SAM_IRQ_PA4 (SAM_IRQ_GPIOA_PINS+4) /* GPIOA, PIN 4 */
# define SAM_IRQ_PA5 (SAM_IRQ_GPIOA_PINS+5) /* GPIOA, PIN 5 */
# define SAM_IRQ_PA6 (SAM_IRQ_GPIOA_PINS+6) /* GPIOA, PIN 6 */
# define SAM_IRQ_PA7 (SAM_IRQ_GPIOA_PINS+7) /* GPIOA, PIN 7 */
# define SAM_IRQ_PA8 (SAM_IRQ_GPIOA_PINS+8) /* GPIOA, PIN 8 */
# define SAM_IRQ_PA9 (SAM_IRQ_GPIOA_PINS+9) /* GPIOA, PIN 9 */
# define SAM_IRQ_PA10 (SAM_IRQ_GPIOA_PINS+10) /* GPIOA, PIN 10 */
# define SAM_IRQ_PA11 (SAM_IRQ_GPIOA_PINS+11) /* GPIOA, PIN 11 */
# define SAM_IRQ_PA12 (SAM_IRQ_GPIOA_PINS+12) /* GPIOA, PIN 12 */
# define SAM_IRQ_PA13 (SAM_IRQ_GPIOA_PINS+13) /* GPIOA, PIN 13 */
# define SAM_IRQ_PA14 (SAM_IRQ_GPIOA_PINS+14) /* GPIOA, PIN 14 */
# define SAM_IRQ_PA15 (SAM_IRQ_GPIOA_PINS+15) /* GPIOA, PIN 15 */
# define SAM_IRQ_PA16 (SAM_IRQ_GPIOA_PINS+16) /* GPIOA, PIN 16 */
# define SAM_IRQ_PA17 (SAM_IRQ_GPIOA_PINS+17) /* GPIOA, PIN 17 */
# define SAM_IRQ_PA18 (SAM_IRQ_GPIOA_PINS+18) /* GPIOA, PIN 18 */
# define SAM_IRQ_PA19 (SAM_IRQ_GPIOA_PINS+19) /* GPIOA, PIN 19 */
# define SAM_IRQ_PA20 (SAM_IRQ_GPIOA_PINS+20) /* GPIOA, PIN 20 */
# define SAM_IRQ_PA21 (SAM_IRQ_GPIOA_PINS+21) /* GPIOA, PIN 21 */
# define SAM_IRQ_PA22 (SAM_IRQ_GPIOA_PINS+22) /* GPIOA, PIN 22 */
# define SAM_IRQ_PA23 (SAM_IRQ_GPIOA_PINS+23) /* GPIOA, PIN 23 */
# define SAM_IRQ_PA24 (SAM_IRQ_GPIOA_PINS+24) /* GPIOA, PIN 24 */
# define SAM_IRQ_PA25 (SAM_IRQ_GPIOA_PINS+25) /* GPIOA, PIN 25 */
# define SAM_IRQ_PA26 (SAM_IRQ_GPIOA_PINS+26) /* GPIOA, PIN 26 */
# define SAM_IRQ_PA27 (SAM_IRQ_GPIOA_PINS+27) /* GPIOA, PIN 27 */
# define SAM_IRQ_PA28 (SAM_IRQ_GPIOA_PINS+28) /* GPIOA, PIN 28 */
# define SAM_IRQ_PA29 (SAM_IRQ_GPIOA_PINS+29) /* GPIOA, PIN 29 */
# define SAM_IRQ_PA30 (SAM_IRQ_GPIOA_PINS+30) /* GPIOA, PIN 30 */
# define SAM_IRQ_PA31 (SAM_IRQ_GPIOA_PINS+31) /* GPIOA, PIN 31 */
# define SAM_NGPIOAIRQS 32
#else
# define SAM_NGPIOAIRQS 0
#endif
#ifdef CONFIG_GPIOB_IRQ
# define SAM_IRQ_GPIOB_PINS (SAM_IRQ_EXTINT + SAM_IRQ_NEXTINT + SAM_NGPIOAIRQS)
# define SAM_IRQ_PB0 (SAM_IRQ_GPIOB_PINS+0) /* GPIOB, PIN 0 */
# define SAM_IRQ_PB1 (SAM_IRQ_GPIOB_PINS+1) /* GPIOB, PIN 1 */
# define SAM_IRQ_PB2 (SAM_IRQ_GPIOB_PINS+2) /* GPIOB, PIN 2 */
# define SAM_IRQ_PB3 (SAM_IRQ_GPIOB_PINS+3) /* GPIOB, PIN 3 */
# define SAM_IRQ_PB4 (SAM_IRQ_GPIOB_PINS+4) /* GPIOB, PIN 4 */
# define SAM_IRQ_PB5 (SAM_IRQ_GPIOB_PINS+5) /* GPIOB, PIN 5 */
# define SAM_IRQ_PB6 (SAM_IRQ_GPIOB_PINS+6) /* GPIOB, PIN 6 */
# define SAM_IRQ_PB7 (SAM_IRQ_GPIOB_PINS+7) /* GPIOB, PIN 7 */
# define SAM_IRQ_PB8 (SAM_IRQ_GPIOB_PINS+8) /* GPIOB, PIN 8 */
# define SAM_IRQ_PB9 (SAM_IRQ_GPIOB_PINS+9) /* GPIOB, PIN 9 */
# define SAM_IRQ_PB10 (SAM_IRQ_GPIOB_PINS+10) /* GPIOB, PIN 10 */
# define SAM_IRQ_PB11 (SAM_IRQ_GPIOB_PINS+11) /* GPIOB, PIN 11 */
# define SAM_IRQ_PB12 (SAM_IRQ_GPIOB_PINS+12) /* GPIOB, PIN 12 */
# define SAM_IRQ_PB13 (SAM_IRQ_GPIOB_PINS+13) /* GPIOB, PIN 13 */
# define SAM_IRQ_PB14 (SAM_IRQ_GPIOB_PINS+14) /* GPIOB, PIN 14 */
# define SAM_IRQ_PB15 (SAM_IRQ_GPIOB_PINS+15) /* GPIOB, PIN 15 */
# define SAM_IRQ_PB16 (SAM_IRQ_GPIOB_PINS+16) /* GPIOB, PIN 16 */
# define SAM_IRQ_PB17 (SAM_IRQ_GPIOB_PINS+17) /* GPIOB, PIN 17 */
# define SAM_IRQ_PB18 (SAM_IRQ_GPIOB_PINS+18) /* GPIOB, PIN 18 */
# define SAM_IRQ_PB19 (SAM_IRQ_GPIOB_PINS+19) /* GPIOB, PIN 19 */
# define SAM_IRQ_PB20 (SAM_IRQ_GPIOB_PINS+20) /* GPIOB, PIN 20 */
# define SAM_IRQ_PB21 (SAM_IRQ_GPIOB_PINS+21) /* GPIOB, PIN 21 */
# define SAM_IRQ_PB22 (SAM_IRQ_GPIOB_PINS+22) /* GPIOB, PIN 22 */
# define SAM_IRQ_PB23 (SAM_IRQ_GPIOB_PINS+23) /* GPIOB, PIN 23 */
# define SAM_IRQ_PB24 (SAM_IRQ_GPIOB_PINS+24) /* GPIOB, PIN 24 */
# define SAM_IRQ_PB25 (SAM_IRQ_GPIOB_PINS+25) /* GPIOB, PIN 25 */
# define SAM_IRQ_PB26 (SAM_IRQ_GPIOB_PINS+26) /* GPIOB, PIN 26 */
# define SAM_IRQ_PB27 (SAM_IRQ_GPIOB_PINS+27) /* GPIOB, PIN 27 */
# define SAM_IRQ_PB28 (SAM_IRQ_GPIOB_PINS+28) /* GPIOB, PIN 28 */
# define SAM_IRQ_PB29 (SAM_IRQ_GPIOB_PINS+29) /* GPIOB, PIN 29 */
# define SAM_IRQ_PB30 (SAM_IRQ_GPIOB_PINS+30) /* GPIOB, PIN 30 */
# define SAM_IRQ_PB31 (SAM_IRQ_GPIOB_PINS+31) /* GPIOB, PIN 31 */
# define SAM_NGPIOBIRQS 32
#else
# define SAM_NGPIOBIRQS 0
#endif
#ifdef CONFIG_GPIOC_IRQ
# define SAM_IRQ_GPIOC_PINS (SAM_IRQ_EXTINT + SAM_IRQ_NEXTINT + SAM_NGPIOAIRQS + SAM_NGPIOBIRQS)
# define SAM_IRQ_PC0 (SAM_IRQ_GPIOC_PINS+0) /* GPIOC, PIN 0 */
# define SAM_IRQ_PC1 (SAM_IRQ_GPIOC_PINS+1) /* GPIOC, PIN 1 */
# define SAM_IRQ_PC2 (SAM_IRQ_GPIOC_PINS+2) /* GPIOC, PIN 2 */
# define SAM_IRQ_PC3 (SAM_IRQ_GPIOC_PINS+3) /* GPIOC, PIN 3 */
# define SAM_IRQ_PC4 (SAM_IRQ_GPIOC_PINS+4) /* GPIOC, PIN 4 */
# define SAM_IRQ_PC5 (SAM_IRQ_GPIOC_PINS+5) /* GPIOC, PIN 5 */
# define SAM_IRQ_PC6 (SAM_IRQ_GPIOC_PINS+6) /* GPIOC, PIN 6 */
# define SAM_IRQ_PC7 (SAM_IRQ_GPIOC_PINS+7) /* GPIOC, PIN 7 */
# define SAM_IRQ_PC8 (SAM_IRQ_GPIOC_PINS+8) /* GPIOC, PIN 8 */
# define SAM_IRQ_PC9 (SAM_IRQ_GPIOC_PINS+9) /* GPIOC, PIN 9 */
# define SAM_IRQ_PC10 (SAM_IRQ_GPIOC_PINS+10) /* GPIOC, PIN 10 */
# define SAM_IRQ_PC11 (SAM_IRQ_GPIOC_PINS+11) /* GPIOC, PIN 11 */
# define SAM_IRQ_PC12 (SAM_IRQ_GPIOC_PINS+12) /* GPIOC, PIN 12 */
# define SAM_IRQ_PC13 (SAM_IRQ_GPIOC_PINS+13) /* GPIOC, PIN 13 */
# define SAM_IRQ_PC14 (SAM_IRQ_GPIOC_PINS+14) /* GPIOC, PIN 14 */
# define SAM_IRQ_PC15 (SAM_IRQ_GPIOC_PINS+15) /* GPIOC, PIN 15 */
# define SAM_IRQ_PC16 (SAM_IRQ_GPIOC_PINS+16) /* GPIOC, PIN 16 */
# define SAM_IRQ_PC17 (SAM_IRQ_GPIOC_PINS+17) /* GPIOC, PIN 17 */
# define SAM_IRQ_PC18 (SAM_IRQ_GPIOC_PINS+18) /* GPIOC, PIN 18 */
# define SAM_IRQ_PC19 (SAM_IRQ_GPIOC_PINS+19) /* GPIOC, PIN 19 */
# define SAM_IRQ_PC20 (SAM_IRQ_GPIOC_PINS+20) /* GPIOC, PIN 20 */
# define SAM_IRQ_PC21 (SAM_IRQ_GPIOC_PINS+21) /* GPIOC, PIN 21 */
# define SAM_IRQ_PC22 (SAM_IRQ_GPIOC_PINS+22) /* GPIOC, PIN 22 */
# define SAM_IRQ_PC23 (SAM_IRQ_GPIOC_PINS+23) /* GPIOC, PIN 23 */
# define SAM_IRQ_PC24 (SAM_IRQ_GPIOC_PINS+24) /* GPIOC, PIN 24 */
# define SAM_IRQ_PC25 (SAM_IRQ_GPIOC_PINS+25) /* GPIOC, PIN 25 */
# define SAM_IRQ_PC26 (SAM_IRQ_GPIOC_PINS+26) /* GPIOC, PIN 26 */
# define SAM_IRQ_PC27 (SAM_IRQ_GPIOC_PINS+27) /* GPIOC, PIN 27 */
# define SAM_IRQ_PC28 (SAM_IRQ_GPIOC_PINS+28) /* GPIOC, PIN 28 */
# define SAM_IRQ_PC29 (SAM_IRQ_GPIOC_PINS+29) /* GPIOC, PIN 29 */
# define SAM_IRQ_PC30 (SAM_IRQ_GPIOC_PINS+30) /* GPIOC, PIN 30 */
# define SAM_IRQ_PC31 (SAM_IRQ_GPIOC_PINS+31) /* GPIOC, PIN 31 */
# define SAM_NGPIOCIRQS 32
#else
# define SAM_NGPIOCIRQS 0
#endif
/* Total number of IRQ numbers */
#define NR_VECTORS SAM_IRQ_NIRQS
#define NR_IRQS (SAM_IRQ_EXTINT + SAM_IRQ_NEXTINT + \
SAM_NGPIOAIRQS + SAM_NGPIOBIRQS + SAM_NGPIOCIRQS)
/****************************************************************************************
* Public Types
****************************************************************************************/
/****************************************************************************************
* Inline functions
****************************************************************************************/
/****************************************************************************************
* Public Variables
****************************************************************************************/
#ifndef __ASSEMBLY__
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************************
* Public Function Prototypes
****************************************************************************************/
#undef EXTERN
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_INCLUDE_SAM34_SAM4CM_IRQ_H */

339
arch/arm/include/sam34/sam4e_irq.h
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@ -1,339 +0,0 @@
/****************************************************************************************
* arch/arm/include/sam34/sam4e_irq.h
*
* Copyright (C) 2013-2014 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************************/
/* This file should never be included directed but, rather, only indirectly through
* nuttx/irq.h
*/
#ifndef __ARCH_ARM_INCLUDE_SAM34_SAM4E_IRQ_H
#define __ARCH_ARM_INCLUDE_SAM34_SAM4E_IRQ_H
/****************************************************************************************
* Included Files
****************************************************************************************/
/****************************************************************************************
* Pre-processor Definitions
****************************************************************************************/
/* SAM4E Peripheral Identifiers */
#define SAM_PID_SUPC (0) /* Supply Controller */
#define SAM_PID_RSTC (1) /* Reset Controller */
#define SAM_PID_RTC (2) /* Real Time Clock */
#define SAM_PID_RTT (3) /* Real Time Timer */
#define SAM_PID_WDT (4) /* Watchdog Timer */
#define SAM_PID_PMC (5) /* Power Management Controller */
#define SAM_PID_EEFC0 (6) /* Enhanced Embedded Flash Controller */
#define SAM_PID_UART0 (7) /* Universal Asynchronous Receiver Transmitter 0 */
#define SAM_PID_SMC (8) /* Static Memory Controller */
#define SAM_PID_PIOA (9) /* Parallel I/O Controller A */
#define SAM_PID_PIOB (10) /* Parallel I/O Controller B */
#define SAM_PID_PIOC (11) /* Parallel I/O Controller C */
#define SAM_PID_PIOD (12) /* Parallel I/O Controller D */
#define SAM_PID_PIOE (13) /* Parallel I/O Controller E */
#define SAM_PID_USART0 (14) /* USART 0 */
#define SAM_PID_USART1 (15) /* USART 1 */
#define SAM_PID_HSMCI (16) /* High Speed Multimedia Card Interface */
#define SAM_PID_TWI0 (17) /* Two-Wire Interface 0 */
#define SAM_PID_TWI1 (18) /* Two-Wire Interface 1 */
#define SAM_PID_SPI0 (19) /* Serial Peripheral Interface */
#define SAM_PID_DMAC (20) /* DMAC */
#define SAM_PID_TC0 (21) /* Timer Counter 0 */
#define SAM_PID_TC1 (22) /* Timer Counter 1 */
#define SAM_PID_TC2 (23) /* Timer Counter 2 */
#define SAM_PID_TC3 (24) /* Timer Counter 3 */
#define SAM_PID_TC4 (25) /* Timer Counter 4 */
#define SAM_PID_TC5 (26) /* Timer Counter 5 */
#define SAM_PID_TC6 (27) /* Timer Counter 6 */
#define SAM_PID_TC7 (28) /* Timer Counter 7 */
#define SAM_PID_TC8 (29) /* Timer Counter 8 */
#define SAM_PID_AFEC0 (30) /* Analog Front End 0 */
#define SAM_PID_AFEC1 (31) /* Analog Front End 1 */
#define SAM_PID_DACC (32) /* Digital to Analog Converter */
#define SAM_PID_ACC (33) /* Analog Comparator */
#define SAM_PID_ARM (34) /* FPU signals: FPIXC, FPOFC, FPUFC, FPIOC, FPDZC,FPIDC, FPIXC */
#define SAM_PID_UDP (35) /* USB Device */
#define SAM_PID_PWM (36) /* PWM */
#define SAM_PID_CAN0 (37) /* CAN0 */
#define SAM_PID_CAN1 (38) /* CAN1 */
#define SAM_PID_AES (39) /* AES */
/* 40-43: Reserved */
#define SAM_PID_EMAC (44) /* EMAC */
#define SAM_PID_UART1 (45) /* UART */
/* 46: Reserved */
#define NR_PIDS (47) /* Number of peripheral identifiers */
/* External interrupts (priority levels >= 256*/
#define SAM_IRQ_SUPC (SAM_IRQ_EXTINT+SAM_PID_SUPC) /* Supply Controller */
#define SAM_IRQ_RSTC (SAM_IRQ_EXTINT+SAM_PID_RSTC) /* Reset Controller */
#define SAM_IRQ_RTC (SAM_IRQ_EXTINT+SAM_PID_RTC) /* Real Time Clock */
#define SAM_IRQ_RTT (SAM_IRQ_EXTINT+SAM_PID_RTT) /* Real Time Timer */
#define SAM_IRQ_WDT (SAM_IRQ_EXTINT+SAM_PID_WDT) /* Watchdog Timer */
#define SAM_IRQ_PMC (SAM_IRQ_EXTINT+SAM_PID_PMC) /* Power Management Controller */
#define SAM_IRQ_EEFC0 (SAM_IRQ_EXTINT+SAM_PID_EEFC0) /* Enhanced Embedded Flash Controller */
#define SAM_IRQ_UART0 (SAM_IRQ_EXTINT+SAM_PID_UART0) /* Universal Asynchronous Receiver Transmitter 0 */
#define SAM_IRQ_PIOA (SAM_IRQ_EXTINT+SAM_PID_PIOA) /* Parallel I/O Controller A */
#define SAM_IRQ_PIOB (SAM_IRQ_EXTINT+SAM_PID_PIOB) /* Parallel I/O Controller B */
#define SAM_IRQ_PIOC (SAM_IRQ_EXTINT+SAM_PID_PIOC) /* Parallel I/O Controller C */
#define SAM_IRQ_PIOD (SAM_IRQ_EXTINT+SAM_PID_PIOD) /* Parallel I/O Controller D */
#define SAM_IRQ_PIOE (SAM_IRQ_EXTINT+SAM_PID_PIOE) /* Parallel I/O Controller E */
#define SAM_IRQ_USART0 (SAM_IRQ_EXTINT+SAM_PID_USART0) /* USART 0 */
#define SAM_IRQ_USART1 (SAM_IRQ_EXTINT+SAM_PID_USART1) /* USART 1 */
#define SAM_IRQ_HSMCI (SAM_IRQ_EXTINT+SAM_PID_HSMCI) /* High Speed Multimedia Card Interface */
#define SAM_IRQ_TWI0 (SAM_IRQ_EXTINT+SAM_PID_TWI0) /* Two-Wire Interface 0 */
#define SAM_IRQ_TWI1 (SAM_IRQ_EXTINT+SAM_PID_TWI1) /* Two-Wire Interface 1 */
#define SAM_IRQ_SPI0 (SAM_IRQ_EXTINT+SAM_PID_SPI0) /* Serial Peripheral Interface */
#define SAM_IRQ_DMAC (SAM_IRQ_EXTINT+SAM_PID_DMAC) /* DMAC */
#define SAM_IRQ_TC0 (SAM_IRQ_EXTINT+SAM_PID_TC0) /* Timer Counter 0 */
#define SAM_IRQ_TC1 (SAM_IRQ_EXTINT+SAM_PID_TC1) /* Timer Counter 1 */
#define SAM_IRQ_TC2 (SAM_IRQ_EXTINT+SAM_PID_TC2) /* Timer Counter 2 */
#define SAM_IRQ_TC3 (SAM_IRQ_EXTINT+SAM_PID_TC3) /* Timer Counter 3 */
#define SAM_IRQ_TC4 (SAM_IRQ_EXTINT+SAM_PID_TC4) /* Timer Counter 4 */
#define SAM_IRQ_TC5 (SAM_IRQ_EXTINT+SAM_PID_TC5) /* Timer Counter 5 */
#define SAM_IRQ_TC6 (SAM_IRQ_EXTINT+SAM_PID_TC6) /* Timer Counter 6 */
#define SAM_IRQ_TC7 (SAM_IRQ_EXTINT+SAM_PID_TC7) /* Timer Counter 7 */
#define SAM_IRQ_TC8 (SAM_IRQ_EXTINT+SAM_PID_TC8) /* Timer Counter 8 */
#define SAM_IRQ_AFEC0 (SAM_IRQ_EXTINT+SAM_PID_AFEC0) /* Analog Front End 0 */
#define SAM_IRQ_AFEC1 (SAM_IRQ_EXTINT+SAM_PID_AFEC1) /* Analog Front End 1 */
#define SAM_IRQ_DACC (SAM_IRQ_EXTINT+SAM_PID_DACC) /* Digital to Analog Converter */
#define SAM_IRQ_ACC (SAM_IRQ_EXTINT+SAM_PID_ACC) /* Analog Comparator */
#define SAM_IRQ_ARM (SAM_IRQ_EXTINT+SAM_PID_ARM) /* FPU signals: FPIXC, FPOFC, FPUFC, FPIOC, FPDZC,FPIDC, FPIXC */
#define SAM_IRQ_UDP (SAM_IRQ_EXTINT+SAM_PID_UDP) /* USB Device */
#define SAM_IRQ_PWM (SAM_IRQ_EXTINT+SAM_PID_PWM) /* PWM */
#define SAM_IRQ_CAN0 (SAM_IRQ_EXTINT+SAM_PID_CAN0) /* CAN0 */
#define SAM_IRQ_CAN1 (SAM_IRQ_EXTINT+SAM_PID_CAN1) /* CAN1 */
#define SAM_IRQ_AES (SAM_IRQ_EXTINT+SAM_PID_AES) /* AES */
#define SAM_IRQ_EMAC (SAM_IRQ_EXTINT+SAM_PID_EMAC) /* EMAC */
#define SAM_IRQ_UART1 (SAM_IRQ_EXTINT+SAM_PID_UART1) /* UART1 */
#define SAM_IRQ_NEXTINT NR_PIDS /* Total number of external interrupt numbers */
#define SAM_IRQ_NIRQS (SAM_IRQ_EXTINT+NR_PIDS) /* The number of real IRQs */
/* GPIO interrupts (derived from SAM_IRQ_PIOA/B/C) */
#ifdef CONFIG_SAM34_GPIOA_IRQ
# define SAM_IRQ_GPIOA_PINS (SAM_IRQ_EXTINT + SAM_IRQ_NEXTINT)
# define SAM_IRQ_PA0 (SAM_IRQ_GPIOA_PINS+0) /* GPIOA, PIN 0 */
# define SAM_IRQ_PA1 (SAM_IRQ_GPIOA_PINS+1) /* GPIOA, PIN 1 */
# define SAM_IRQ_PA2 (SAM_IRQ_GPIOA_PINS+2) /* GPIOA, PIN 2 */
# define SAM_IRQ_PA3 (SAM_IRQ_GPIOA_PINS+3) /* GPIOA, PIN 3 */
# define SAM_IRQ_PA4 (SAM_IRQ_GPIOA_PINS+4) /* GPIOA, PIN 4 */
# define SAM_IRQ_PA5 (SAM_IRQ_GPIOA_PINS+5) /* GPIOA, PIN 5 */
# define SAM_IRQ_PA6 (SAM_IRQ_GPIOA_PINS+6) /* GPIOA, PIN 6 */
# define SAM_IRQ_PA7 (SAM_IRQ_GPIOA_PINS+7) /* GPIOA, PIN 7 */
# define SAM_IRQ_PA8 (SAM_IRQ_GPIOA_PINS+8) /* GPIOA, PIN 8 */
# define SAM_IRQ_PA9 (SAM_IRQ_GPIOA_PINS+9) /* GPIOA, PIN 9 */
# define SAM_IRQ_PA10 (SAM_IRQ_GPIOA_PINS+10) /* GPIOA, PIN 10 */
# define SAM_IRQ_PA11 (SAM_IRQ_GPIOA_PINS+11) /* GPIOA, PIN 11 */
# define SAM_IRQ_PA12 (SAM_IRQ_GPIOA_PINS+12) /* GPIOA, PIN 12 */
# define SAM_IRQ_PA13 (SAM_IRQ_GPIOA_PINS+13) /* GPIOA, PIN 13 */
# define SAM_IRQ_PA14 (SAM_IRQ_GPIOA_PINS+14) /* GPIOA, PIN 14 */
# define SAM_IRQ_PA15 (SAM_IRQ_GPIOA_PINS+15) /* GPIOA, PIN 15 */
# define SAM_IRQ_PA16 (SAM_IRQ_GPIOA_PINS+16) /* GPIOA, PIN 16 */
# define SAM_IRQ_PA17 (SAM_IRQ_GPIOA_PINS+17) /* GPIOA, PIN 17 */
# define SAM_IRQ_PA18 (SAM_IRQ_GPIOA_PINS+18) /* GPIOA, PIN 18 */
# define SAM_IRQ_PA19 (SAM_IRQ_GPIOA_PINS+19) /* GPIOA, PIN 19 */
# define SAM_IRQ_PA20 (SAM_IRQ_GPIOA_PINS+20) /* GPIOA, PIN 20 */
# define SAM_IRQ_PA21 (SAM_IRQ_GPIOA_PINS+21) /* GPIOA, PIN 21 */
# define SAM_IRQ_PA22 (SAM_IRQ_GPIOA_PINS+22) /* GPIOA, PIN 22 */
# define SAM_IRQ_PA23 (SAM_IRQ_GPIOA_PINS+23) /* GPIOA, PIN 23 */
# define SAM_IRQ_PA24 (SAM_IRQ_GPIOA_PINS+24) /* GPIOA, PIN 24 */
# define SAM_IRQ_PA25 (SAM_IRQ_GPIOA_PINS+25) /* GPIOA, PIN 25 */
# define SAM_IRQ_PA26 (SAM_IRQ_GPIOA_PINS+26) /* GPIOA, PIN 26 */
# define SAM_IRQ_PA27 (SAM_IRQ_GPIOA_PINS+27) /* GPIOA, PIN 27 */
# define SAM_IRQ_PA28 (SAM_IRQ_GPIOA_PINS+28) /* GPIOA, PIN 28 */
# define SAM_IRQ_PA29 (SAM_IRQ_GPIOA_PINS+29) /* GPIOA, PIN 29 */
# define SAM_IRQ_PA30 (SAM_IRQ_GPIOA_PINS+30) /* GPIOA, PIN 30 */
# define SAM_IRQ_PA31 (SAM_IRQ_GPIOA_PINS+31) /* GPIOA, PIN 31 */
# define SAM_NGPIOAIRQS 32
#else
# define SAM_NGPIOAIRQS 0
#endif
#ifdef CONFIG_SAM34_GPIOB_IRQ
# define SAM_IRQ_GPIOB_PINS (SAM_IRQ_EXTINT + SAM_IRQ_NEXTINT + SAM_NGPIOAIRQS)
# define SAM_IRQ_PB0 (SAM_IRQ_GPIOB_PINS+0) /* GPIOB, PIN 0 */
# define SAM_IRQ_PB1 (SAM_IRQ_GPIOB_PINS+1) /* GPIOB, PIN 1 */
# define SAM_IRQ_PB2 (SAM_IRQ_GPIOB_PINS+2) /* GPIOB, PIN 2 */
# define SAM_IRQ_PB3 (SAM_IRQ_GPIOB_PINS+3) /* GPIOB, PIN 3 */
# define SAM_IRQ_PB4 (SAM_IRQ_GPIOB_PINS+4) /* GPIOB, PIN 4 */
# define SAM_IRQ_PB5 (SAM_IRQ_GPIOB_PINS+5) /* GPIOB, PIN 5 */
# define SAM_IRQ_PB6 (SAM_IRQ_GPIOB_PINS+6) /* GPIOB, PIN 6 */
# define SAM_IRQ_PB7 (SAM_IRQ_GPIOB_PINS+7) /* GPIOB, PIN 7 */
# define SAM_IRQ_PB8 (SAM_IRQ_GPIOB_PINS+8) /* GPIOB, PIN 8 */
# define SAM_IRQ_PB9 (SAM_IRQ_GPIOB_PINS+9) /* GPIOB, PIN 9 */
# define SAM_IRQ_PB10 (SAM_IRQ_GPIOB_PINS+10) /* GPIOB, PIN 10 */
# define SAM_IRQ_PB11 (SAM_IRQ_GPIOB_PINS+11) /* GPIOB, PIN 11 */
# define SAM_IRQ_PB12 (SAM_IRQ_GPIOB_PINS+12) /* GPIOB, PIN 12 */
# define SAM_IRQ_PB13 (SAM_IRQ_GPIOB_PINS+13) /* GPIOB, PIN 13 */
# define SAM_IRQ_PB14 (SAM_IRQ_GPIOB_PINS+14) /* GPIOB, PIN 14 */
# define SAM_NGPIOBIRQS 15
#else
# define SAM_NGPIOBIRQS 0
#endif
#ifdef CONFIG_SAM34_GPIOC_IRQ
# define SAM_IRQ_GPIOC_PINS (SAM_IRQ_EXTINT + SAM_IRQ_NEXTINT + SAM_NGPIOAIRQS + SAM_NGPIOBIRQS)
# define SAM_IRQ_PC0 (SAM_IRQ_GPIOC_PINS+0) /* GPIOC, PIN 0 */
# define SAM_IRQ_PC1 (SAM_IRQ_GPIOC_PINS+1) /* GPIOC, PIN 1 */
# define SAM_IRQ_PC2 (SAM_IRQ_GPIOC_PINS+2) /* GPIOC, PIN 2 */
# define SAM_IRQ_PC3 (SAM_IRQ_GPIOC_PINS+3) /* GPIOC, PIN 3 */
# define SAM_IRQ_PC4 (SAM_IRQ_GPIOC_PINS+4) /* GPIOC, PIN 4 */
# define SAM_IRQ_PC5 (SAM_IRQ_GPIOC_PINS+5) /* GPIOC, PIN 5 */
# define SAM_IRQ_PC6 (SAM_IRQ_GPIOC_PINS+6) /* GPIOC, PIN 6 */
# define SAM_IRQ_PC7 (SAM_IRQ_GPIOC_PINS+7) /* GPIOC, PIN 7 */
# define SAM_IRQ_PC8 (SAM_IRQ_GPIOC_PINS+8) /* GPIOC, PIN 8 */
# define SAM_IRQ_PC9 (SAM_IRQ_GPIOC_PINS+9) /* GPIOC, PIN 9 */
# define SAM_IRQ_PC10 (SAM_IRQ_GPIOC_PINS+10) /* GPIOC, PIN 10 */
# define SAM_IRQ_PC11 (SAM_IRQ_GPIOC_PINS+11) /* GPIOC, PIN 11 */
# define SAM_IRQ_PC12 (SAM_IRQ_GPIOC_PINS+12) /* GPIOC, PIN 12 */
# define SAM_IRQ_PC13 (SAM_IRQ_GPIOC_PINS+13) /* GPIOC, PIN 13 */
# define SAM_IRQ_PC14 (SAM_IRQ_GPIOC_PINS+14) /* GPIOC, PIN 14 */
# define SAM_IRQ_PC15 (SAM_IRQ_GPIOC_PINS+15) /* GPIOC, PIN 15 */
# define SAM_IRQ_PC16 (SAM_IRQ_GPIOC_PINS+16) /* GPIOC, PIN 16 */
# define SAM_IRQ_PC17 (SAM_IRQ_GPIOC_PINS+17) /* GPIOC, PIN 17 */
# define SAM_IRQ_PC18 (SAM_IRQ_GPIOC_PINS+18) /* GPIOC, PIN 18 */
# define SAM_IRQ_PC19 (SAM_IRQ_GPIOC_PINS+19) /* GPIOC, PIN 19 */
# define SAM_IRQ_PC20 (SAM_IRQ_GPIOC_PINS+20) /* GPIOC, PIN 20 */
# define SAM_IRQ_PC21 (SAM_IRQ_GPIOC_PINS+21) /* GPIOC, PIN 21 */
# define SAM_IRQ_PC22 (SAM_IRQ_GPIOC_PINS+22) /* GPIOC, PIN 22 */
# define SAM_IRQ_PC23 (SAM_IRQ_GPIOC_PINS+23) /* GPIOC, PIN 23 */
# define SAM_IRQ_PC24 (SAM_IRQ_GPIOC_PINS+24) /* GPIOC, PIN 24 */
# define SAM_IRQ_PC25 (SAM_IRQ_GPIOC_PINS+25) /* GPIOC, PIN 25 */
# define SAM_IRQ_PC26 (SAM_IRQ_GPIOC_PINS+26) /* GPIOC, PIN 26 */
# define SAM_IRQ_PC27 (SAM_IRQ_GPIOC_PINS+27) /* GPIOC, PIN 27 */
# define SAM_IRQ_PC28 (SAM_IRQ_GPIOC_PINS+28) /* GPIOC, PIN 28 */
# define SAM_IRQ_PC29 (SAM_IRQ_GPIOC_PINS+29) /* GPIOC, PIN 29 */
# define SAM_IRQ_PC30 (SAM_IRQ_GPIOC_PINS+30) /* GPIOC, PIN 30 */
# define SAM_IRQ_PC31 (SAM_IRQ_GPIOC_PINS+31) /* GPIOC, PIN 31 */
# define SAM_NGPIOCIRQS 32
#else
# define SAM_NGPIOCIRQS 0
#endif
#ifdef CONFIG_SAM34_GPIOD_IRQ
# define SAM_IRQ_GPIOD_PINS (SAM_IRQ_EXTINT + SAM_IRQ_NEXTINT + SAM_NGPIOAIRQS + SAM_NGPIOBIRQS)
# define SAM_IRQ_PD0 (SAM_IRQ_GPIOD_PINS+0) /* GPIOD, PIN 0 */
# define SAM_IRQ_PD1 (SAM_IRQ_GPIOD_PINS+1) /* GPIOD, PIN 1 */
# define SAM_IRQ_PD2 (SAM_IRQ_GPIOD_PINS+2) /* GPIOD, PIN 2 */
# define SAM_IRQ_PD3 (SAM_IRQ_GPIOD_PINS+3) /* GPIOD, PIN 3 */
# define SAM_IRQ_PD4 (SAM_IRQ_GPIOD_PINS+4) /* GPIOD, PIN 4 */
# define SAM_IRQ_PD5 (SAM_IRQ_GPIOD_PINS+5) /* GPIOD, PIN 5 */
# define SAM_IRQ_PD6 (SAM_IRQ_GPIOD_PINS+6) /* GPIOD, PIN 6 */
# define SAM_IRQ_PD7 (SAM_IRQ_GPIOD_PINS+7) /* GPIOD, PIN 7 */
# define SAM_IRQ_PD8 (SAM_IRQ_GPIOD_PINS+8) /* GPIOD, PIN 8 */
# define SAM_IRQ_PD9 (SAM_IRQ_GPIOD_PINS+9) /* GPIOD, PIN 9 */
# define SAM_IRQ_PD10 (SAM_IRQ_GPIOD_PINS+10) /* GPIOD, PIN 10 */
# define SAM_IRQ_PD11 (SAM_IRQ_GPIOD_PINS+11) /* GPIOD, PIN 11 */
# define SAM_IRQ_PD12 (SAM_IRQ_GPIOD_PINS+12) /* GPIOD, PIN 12 */
# define SAM_IRQ_PD13 (SAM_IRQ_GPIOD_PINS+13) /* GPIOD, PIN 13 */
# define SAM_IRQ_PD14 (SAM_IRQ_GPIOD_PINS+14) /* GPIOD, PIN 14 */
# define SAM_IRQ_PD15 (SAM_IRQ_GPIOD_PINS+15) /* GPIOD, PIN 15 */
# define SAM_IRQ_PD16 (SAM_IRQ_GPIOD_PINS+16) /* GPIOD, PIN 16 */
# define SAM_IRQ_PD17 (SAM_IRQ_GPIOD_PINS+17) /* GPIOD, PIN 17 */
# define SAM_IRQ_PD18 (SAM_IRQ_GPIOD_PINS+18) /* GPIOD, PIN 18 */
# define SAM_IRQ_PD19 (SAM_IRQ_GPIOD_PINS+19) /* GPIOD, PIN 19 */
# define SAM_IRQ_PD20 (SAM_IRQ_GPIOD_PINS+20) /* GPIOD, PIN 20 */
# define SAM_IRQ_PD21 (SAM_IRQ_GPIOD_PINS+21) /* GPIOD, PIN 21 */
# define SAM_IRQ_PD22 (SAM_IRQ_GPIOD_PINS+22) /* GPIOD, PIN 22 */
# define SAM_IRQ_PD23 (SAM_IRQ_GPIOD_PINS+23) /* GPIOD, PIN 23 */
# define SAM_IRQ_PD24 (SAM_IRQ_GPIOD_PINS+24) /* GPIOD, PIN 24 */
# define SAM_IRQ_PD25 (SAM_IRQ_GPIOD_PINS+25) /* GPIOD, PIN 25 */
# define SAM_IRQ_PD26 (SAM_IRQ_GPIOD_PINS+26) /* GPIOD, PIN 26 */
# define SAM_IRQ_PD27 (SAM_IRQ_GPIOD_PINS+27) /* GPIOD, PIN 27 */
# define SAM_IRQ_PD28 (SAM_IRQ_GPIOD_PINS+28) /* GPIOD, PIN 28 */
# define SAM_IRQ_PD29 (SAM_IRQ_GPIOD_PINS+29) /* GPIOD, PIN 29 */
# define SAM_IRQ_PD30 (SAM_IRQ_GPIOD_PINS+30) /* GPIOD, PIN 30 */
# define SAM_IRQ_PD31 (SAM_IRQ_GPIOD_PINS+31) /* GPIOD, PIN 31 */
# define SAM_NGPIODIRQS 32
#else
# define SAM_NGPIODIRQS 0
#endif
#ifdef CONFIG_SAM34_GPIOE_IRQ
# define SAM_IRQ_GPIOE_PINS (SAM_IRQ_EXTINT + SAM_IRQ_NEXTINT + SAM_NGPIOAIRQS + SAM_NGPIOBIRQS)
# define SAM_IRQ_PE0 (SAM_IRQ_GPIOE_PINS+0) /* GPIOE, PIN 0 */
# define SAM_IRQ_PE1 (SAM_IRQ_GPIOE_PINS+1) /* GPIOE, PIN 1 */
# define SAM_IRQ_PE2 (SAM_IRQ_GPIOE_PINS+2) /* GPIOE, PIN 2 */
# define SAM_IRQ_PE3 (SAM_IRQ_GPIOE_PINS+3) /* GPIOE, PIN 3 */
# define SAM_IRQ_PE4 (SAM_IRQ_GPIOE_PINS+4) /* GPIOE, PIN 4 */
# define SAM_IRQ_PE5 (SAM_IRQ_GPIOE_PINS+5) /* GPIOE, PIN 5 */
# define SAM_NGPIOEIRQS 6
#else
# define SAM_NGPIOEIRQS 0
#endif
/* Total number of IRQ numbers */
#define NR_VECTORS SAM_IRQ_NIRQS
#define NR_IRQS (SAM_IRQ_EXTINT + SAM_IRQ_NEXTINT + \
SAM_NGPIOAIRQS + SAM_NGPIOBIRQS + SAM_NGPIOCIRQS + \
SAM_NGPIODIRQS + SAM_NGPIOEIRQS)
/****************************************************************************************
* Public Types
****************************************************************************************/
/****************************************************************************************
* Inline functions
****************************************************************************************/
/****************************************************************************************
* Public Variables
****************************************************************************************/
/****************************************************************************************
* Public Function Prototypes
****************************************************************************************/
#ifndef __ASSEMBLY__
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif
#endif /* __ARCH_ARM_INCLUDE_SAM34_SAM4E_IRQ_H */

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arch/arm/include/sam34/sam4l_irq.h
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@ -1,338 +0,0 @@
/****************************************************************************************
* arch/arm/include/sam34/sam4l_irq.h
*
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************************/
/* This file should never be included directed but, rather, only indirectly through
* nuttx/irq.h
*/
#ifndef __ARCH_ARM_INCLUDE_SAM34_SAM4L_IRQ_H
#define __ARCH_ARM_INCLUDE_SAM34_SAM4L_IRQ_H
/****************************************************************************************
* Included Files
****************************************************************************************/
/****************************************************************************************
* Pre-processor Definitions
****************************************************************************************/
/* SAM4L Peripheral Identifiers. NOTE: Interrupts are not tied to the DMA peripheral
* identifiers in the SAM4L as they were with the SAM3U. However, for consistency, those
* peripheral identifiers are defined in this file as well.
*/
#define SAM_PID_USART0_RHR (0) /* DIR=RX REGISTER: USART0 RHR */
#define SAM_PID_USART1_RHR (1) /* DIR=RX REGISTER: USART1 RHR */
#define SAM_PID_USART2_RHR (2) /* DIR=RX REGISTER: USART2 RHR */
#define SAM_PID_USART3_RHR (3) /* DIR=RX REGISTER: USART3 RHR */
#define SAM_PID_SPI0_RDR (4) /* DIR=RX REGISTER: SPI RDR */
#define SAM_PID_TWIM0_RHR (5) /* DIR=RX REGISTER: TWIM0 RHR */
#define SAM_PID_TWIM1_RHR (6) /* DIR=RX REGISTER: TWIM1 RHR */
#define SAM_PID_TWIM2_RHR (7) /* DIR=RX REGISTER: TWIM2 RHR */
#define SAM_PID_TWIM3_RHR (8) /* DIR=RX REGISTER: TWIM3 RHR */
#define SAM_PID_TWIS0_RHR (9) /* DIR=RX REGISTER: TWIS0 RHR */
#define SAM_PID_TWIS1_RHR (10) /* DIR=RX REGISTER: TWIS1 RHR */
#define SAM_PID_ADCIFE_LCV (11) /* DIR=RX REGISTER: ADCIFE LCV */
#define SAM_PID_CATB_RX (12) /* DIR=RX REGISTER: CATB Multiple */
/* 13: Reserved */
#define SAM_PID_IISC0_RHR (14) /* DIR=RX REGISTER: IISC RHR (CH0) */
#define SAM_PID_IISC1_RHR (15) /* DIR=RX REGISTER: IISC RHR (CH1) */
#define SAM_PID_PARC_RHR (16) /* DIR=RX REGISTER: PARC RHR */
#define SAM_PID_AESA_ODATA (17) /* DIR=RX REGISTER: AESA ODATA */
#define SAM_PID_USART0_THR (18) /* DIR=TX REGISTER: USART0 THR */
#define SAM_PID_USART1_THR (19) /* DIR=TX REGISTER: USART1 THR */
#define SAM_PID_USART2_THR (20) /* DIR=TX REGISTER: USART2 THR */
#define SAM_PID_USART3_THR (21) /* DIR=TX REGISTER: USART3 THR */
#define SAM_PID_SPI0_TDR (22) /* DIR=TX REGISTER: SPI TDR */
#define SAM_PID_TWIM0_THR (23) /* DIR=TX REGISTER: TWIM0 THR */
#define SAM_PID_TWIM1_THR (24) /* DIR=TX REGISTER: TWIM1 THR */
#define SAM_PID_TWIM2_THR (25) /* DIR=TX REGISTER: TWIM2 THR */
#define SAM_PID_TWIM3_THR (26) /* DIR=TX REGISTER: TWIM3 THR */
#define SAM_PID_TWIS0_THR (27) /* DIR=TX REGISTER: TWIS0 THR */
#define SAM_PID_TWIS1_THR (28) /* DIR=TX REGISTER: TWIS1 THR */
#define SAM_PID_ADCIFE_CDMA (29) /* DIR=TX REGISTER: ADCIFE CDMA */
#define SAM_PID_CATB_TX (30) /* DIR=TX REGISTER: CATB Multiple */
#define SAM_PID_ABDACB_SDR0 (31) /* DIR=TX REGISTER: ABDACB SDR0 */
#define SAM_PID_ABDACB_SDR1 (32) /* DIR=TX REGISTER: ABDACB SDR1 */
#define SAM_PID_IISC0_THR (33) /* DIR=TX REGISTER: IISC THR (CH0) */
#define SAM_PID_IISC1_THR (34) /* DIR=TX REGISTER: IISC THR (CH1) */
#define SAM_PID_DACC_CDR (35) /* DIR=TX REGISTER: DACC CDR */
#define SAM_PID_AESA_IDATA (36) /* DIR=TX REGISTER: AESA IDATA */
#define SAM_PID_LCDCA_ACMDR (37) /* DIR=TX REGISTER: LCDCA ACMDR */
#define SAM_PID_LCDCA_ABMDR (38) /* DIR=TX REGISTER: LCDCA ABMDR */
/* External interrupts (vectors >= 16) */
#define SAM_IRQ_HFLASHC (SAM_IRQ_EXTINT+0) /* 0 Flash Controller */
#define SAM_IRQ_PDCA0 (SAM_IRQ_EXTINT+1) /* 1 Peripheral DMA Controller 0 */
#define SAM_IRQ_PDCA1 (SAM_IRQ_EXTINT+2) /* 2 Peripheral DMA Controller 1 */
#define SAM_IRQ_PDCA2 (SAM_IRQ_EXTINT+3) /* 3 Peripheral DMA Controller 2 */
#define SAM_IRQ_PDCA3 (SAM_IRQ_EXTINT+4) /* 4 Peripheral DMA Controller 3 */
#define SAM_IRQ_PDCA4 (SAM_IRQ_EXTINT+5) /* 5 Peripheral DMA Controller 4 */
#define SAM_IRQ_PDCA5 (SAM_IRQ_EXTINT+6) /* 6 Peripheral DMA Controller 5 */
#define SAM_IRQ_PDCA6 (SAM_IRQ_EXTINT+7) /* 7 Peripheral DMA Controller 6 */
#define SAM_IRQ_PDCA7 (SAM_IRQ_EXTINT+8) /* 8 Peripheral DMA Controller 7 */
#define SAM_IRQ_PDCA8 (SAM_IRQ_EXTINT+9) /* 9 Peripheral DMA Controller 8 */
#define SAM_IRQ_PDCA9 (SAM_IRQ_EXTINT+10) /* 10 Peripheral DMA Controller 9 */
#define SAM_IRQ_PDCA10 (SAM_IRQ_EXTINT+11) /* 11 Peripheral DMA Controller 10 */
#define SAM_IRQ_PDCA11 (SAM_IRQ_EXTINT+12) /* 12 Peripheral DMA Controller 11 */
#define SAM_IRQ_PDCA12 (SAM_IRQ_EXTINT+13) /* 13 Peripheral DMA Controller 12 */
#define SAM_IRQ_PDCA13 (SAM_IRQ_EXTINT+14) /* 14 Peripheral DMA Controller 13 */
#define SAM_IRQ_PDCA14 (SAM_IRQ_EXTINT+15) /* 15 Peripheral DMA Controller 14 */
#define SAM_IRQ_PDCA15 (SAM_IRQ_EXTINT+16) /* 16 Peripheral DMA Controller 15 */
#define SAM_IRQ_CRCCU (SAM_IRQ_EXTINT+17) /* 17 CRC Calculation Unit */
#define SAM_IRQ_USBC (SAM_IRQ_EXTINT+18) /* 18 USB 2.0 Interface */
#define SAM_IRQ_PEVC_TR (SAM_IRQ_EXTINT+19) /* 19 Peripheral Event Controller TR */
#define SAM_IRQ_PEVC_OV (SAM_IRQ_EXTINT+20) /* 20 Peripheral Event Controller OV */
#define SAM_IRQ_AESA (SAM_IRQ_EXTINT+21) /* 21 Advanced Encryption Standard AESA */
#define SAM_IRQ_PM (SAM_IRQ_EXTINT+22) /* 22 Power Manager */
#define SAM_IRQ_SCIF (SAM_IRQ_EXTINT+23) /* 23 System Control Interface */
#define SAM_IRQ_FREQM (SAM_IRQ_EXTINT+24) /* 24 Frequency Meter */
#define SAM_IRQ_GPIO0 (SAM_IRQ_EXTINT+25) /* 25 General-Purpose Input/Output Controller 0 */
#define SAM_IRQ_GPIO1 (SAM_IRQ_EXTINT+26) /* 26 General-Purpose Input/Output Controller 1 */
#define SAM_IRQ_GPIO2 (SAM_IRQ_EXTINT+27) /* 27 General-Purpose Input/Output Controller 2 */
#define SAM_IRQ_GPIO3 (SAM_IRQ_EXTINT+28) /* 28 General-Purpose Input/Output Controller 3 */
#define SAM_IRQ_GPIO4 (SAM_IRQ_EXTINT+29) /* 29 General-Purpose Input/Output Controller 4 */
#define SAM_IRQ_GPIO5 (SAM_IRQ_EXTINT+30) /* 30 General-Purpose Input/Output Controller 5 */
#define SAM_IRQ_GPIO6 (SAM_IRQ_EXTINT+31) /* 31 General-Purpose Input/Output Controller 6 */
#define SAM_IRQ_GPIO7 (SAM_IRQ_EXTINT+32) /* 32 General-Purpose Input/Output Controller 7 */
#define SAM_IRQ_GPIO8 (SAM_IRQ_EXTINT+33) /* 33 General-Purpose Input/Output Controller 8 */
#define SAM_IRQ_GPIO9 (SAM_IRQ_EXTINT+34) /* 34 General-Purpose Input/Output Controller 9 */
#define SAM_IRQ_GPIO10 (SAM_IRQ_EXTINT+35) /* 35 General-Purpose Input/Output Controller 10 */
#define SAM_IRQ_GPIO11 (SAM_IRQ_EXTINT+36) /* 36 General-Purpose Input/Output Controller 11 */
#define SAM_IRQ_BPM (SAM_IRQ_EXTINT+37) /* 37 Backup Power Manager */
#define SAM_IRQ_BSCIF (SAM_IRQ_EXTINT+38) /* 38 Backup System Control Interface */
#define SAM_IRQ_AST_ALARM (SAM_IRQ_EXTINT+39) /* 39 Asynchronous Timer ALARM */
#define SAM_IRQ_AST_PER (SAM_IRQ_EXTINT+40) /* 40 Asynchronous Timer PER */
#define SAM_IRQ_AST_OVF (SAM_IRQ_EXTINT+41) /* 41 Asynchronous Timer OVF */
#define SAM_IRQ_AST_READY (SAM_IRQ_EXTINT+42) /* 42 Asynchronous Timer READY */
#define SAM_IRQ_AST_CLKREADY (SAM_IRQ_EXTINT+43) /* 43 Asynchronous Timer CLKREADY */
#define SAM_IRQ_WDT (SAM_IRQ_EXTINT+44) /* 44 Watchdog Timer */
#define SAM_IRQ_EIC1 (SAM_IRQ_EXTINT+45) /* 45 External Interrupt Controller 1 */
#define SAM_IRQ_EIC2 (SAM_IRQ_EXTINT+46) /* 46 External Interrupt Controller 2 */
#define SAM_IRQ_EIC3 (SAM_IRQ_EXTINT+47) /* 47 External Interrupt Controller 3 */
#define SAM_IRQ_EIC4 (SAM_IRQ_EXTINT+48) /* 48 External Interrupt Controller 4 */
#define SAM_IRQ_EIC5 (SAM_IRQ_EXTINT+49) /* 49 External Interrupt Controller 5 */
#define SAM_IRQ_EIC6 (SAM_IRQ_EXTINT+50) /* 50 External Interrupt Controller 6 */
#define SAM_IRQ_EIC7 (SAM_IRQ_EXTINT+51) /* 51 External Interrupt Controller 7 */
#define SAM_IRQ_EIC8 (SAM_IRQ_EXTINT+52) /* 52 External Interrupt Controller 8 */
#define SAM_IRQ_IISC (SAM_IRQ_EXTINT+53) /* 53 Inter-IC Sound (I2S) Controller */
#define SAM_IRQ_SPI0 (SAM_IRQ_EXTINT+54) /* 54 Serial Peripheral Interface */
#define SAM_IRQ_TC00 (SAM_IRQ_EXTINT+55) /* 55 Timer/Counter 0 */
#define SAM_IRQ_TC01 (SAM_IRQ_EXTINT+56) /* 56 Timer/Counter 1 */
#define SAM_IRQ_TC02 (SAM_IRQ_EXTINT+57) /* 57 Timer/Counter 2 */
#define SAM_IRQ_TC10 (SAM_IRQ_EXTINT+58) /* 58 Timer/Counter 10 */
#define SAM_IRQ_TC11 (SAM_IRQ_EXTINT+59) /* 59 Timer/Counter 11 */
#define SAM_IRQ_TC12 (SAM_IRQ_EXTINT+60) /* 60 Timer/Counter 12 */
#define SAM_IRQ_TWIM0 (SAM_IRQ_EXTINT+61) /* 61 Two-wire Master Interface TWIM0 */
#define SAM_IRQ_TWIS0 (SAM_IRQ_EXTINT+62) /* 62 Two-wire Slave Interface TWIS0 */
#define SAM_IRQ_TWIM1 (SAM_IRQ_EXTINT+63) /* 63 Two-wire Master Interface TWIM1 */
#define SAM_IRQ_TWIS1 (SAM_IRQ_EXTINT+64) /* 64 Two-wire Slave Interface TWIS1 */
#define SAM_IRQ_USART0 (SAM_IRQ_EXTINT+65) /* 65 USART0 */
#define SAM_IRQ_USART1 (SAM_IRQ_EXTINT+66) /* 66 USART1 */
#define SAM_IRQ_USART2 (SAM_IRQ_EXTINT+67) /* 67 USART2 */
#define SAM_IRQ_USART3 (SAM_IRQ_EXTINT+68) /* 68 USART3 */
#define SAM_IRQ_ADCIFE (SAM_IRQ_EXTINT+69) /* 69 ADC controller interface */
#define SAM_IRQ_DACC (SAM_IRQ_EXTINT+70) /* 70 DAC Controller */
#define SAM_IRQ_ACIFC (SAM_IRQ_EXTINT+71) /* 71 Analog Comparator Interface */
#define SAM_IRQ_ABDACB (SAM_IRQ_EXTINT+72) /* 72 Audio Bitstream DAC */
#define SAM_IRQ_TRNG (SAM_IRQ_EXTINT+73) /* 73 True Random Number Generator */
#define SAM_IRQ_PARC (SAM_IRQ_EXTINT+74) /* 74 Parallel Capture */
#define SAM_IRQ_CATB (SAM_IRQ_EXTINT+75) /* 75 Capacitive Touch Module B */
#define SAM_IRQ_TWIM2 (SAM_IRQ_EXTINT+77) /* 77 Two-wire Master Interface */
#define SAM_IRQ_TWIM3 (SAM_IRQ_EXTINT+78) /* 78 Two-wire Master Interface */
#define SAM_IRQ_LCDCA (SAM_IRQ_EXTINT+79) /* 79 LCD Controller A */
#define SAM_IRQ_NEXTINT 80 /* Total number of external interrupt numbers */
#define SAM_IRQ_NIRQS (SAM_IRQ_EXTINT+SAM_IRQ_NEXTINT) /* The number of real IRQs */
/* GPIO interrupts (derived from SAM_IRQ_PIOA/B/C) */
#ifdef CONFIG_SAM34_GPIOA_IRQ
# define SAM_IRQ_GPIOA_PINS (SAM_IRQ_EXTINT + SAM_IRQ_NEXTINT)
# define SAM_IRQ_PA0 (SAM_IRQ_GPIOA_PINS+0) /* GPIOA, PIN 0 */
# define SAM_IRQ_PA1 (SAM_IRQ_GPIOA_PINS+1) /* GPIOA, PIN 1 */
# define SAM_IRQ_PA2 (SAM_IRQ_GPIOA_PINS+2) /* GPIOA, PIN 2 */
# define SAM_IRQ_PA3 (SAM_IRQ_GPIOA_PINS+3) /* GPIOA, PIN 3 */
# define SAM_IRQ_PA4 (SAM_IRQ_GPIOA_PINS+4) /* GPIOA, PIN 4 */
# define SAM_IRQ_PA5 (SAM_IRQ_GPIOA_PINS+5) /* GPIOA, PIN 5 */
# define SAM_IRQ_PA6 (SAM_IRQ_GPIOA_PINS+6) /* GPIOA, PIN 6 */
# define SAM_IRQ_PA7 (SAM_IRQ_GPIOA_PINS+7) /* GPIOA, PIN 7 */
# define SAM_IRQ_PA8 (SAM_IRQ_GPIOA_PINS+8) /* GPIOA, PIN 8 */
# define SAM_IRQ_PA9 (SAM_IRQ_GPIOA_PINS+9) /* GPIOA, PIN 9 */
# define SAM_IRQ_PA10 (SAM_IRQ_GPIOA_PINS+10) /* GPIOA, PIN 10 */
# define SAM_IRQ_PA11 (SAM_IRQ_GPIOA_PINS+11) /* GPIOA, PIN 11 */
# define SAM_IRQ_PA12 (SAM_IRQ_GPIOA_PINS+12) /* GPIOA, PIN 12 */
# define SAM_IRQ_PA13 (SAM_IRQ_GPIOA_PINS+13) /* GPIOA, PIN 13 */
# define SAM_IRQ_PA14 (SAM_IRQ_GPIOA_PINS+14) /* GPIOA, PIN 14 */
# define SAM_IRQ_PA15 (SAM_IRQ_GPIOA_PINS+15) /* GPIOA, PIN 15 */
# define SAM_IRQ_PA16 (SAM_IRQ_GPIOA_PINS+16) /* GPIOA, PIN 16 */
# define SAM_IRQ_PA17 (SAM_IRQ_GPIOA_PINS+17) /* GPIOA, PIN 17 */
# define SAM_IRQ_PA18 (SAM_IRQ_GPIOA_PINS+18) /* GPIOA, PIN 18 */
# define SAM_IRQ_PA19 (SAM_IRQ_GPIOA_PINS+19) /* GPIOA, PIN 19 */
# define SAM_IRQ_PA20 (SAM_IRQ_GPIOA_PINS+20) /* GPIOA, PIN 20 */
# define SAM_IRQ_PA21 (SAM_IRQ_GPIOA_PINS+21) /* GPIOA, PIN 21 */
# define SAM_IRQ_PA22 (SAM_IRQ_GPIOA_PINS+22) /* GPIOA, PIN 22 */
# define SAM_IRQ_PA23 (SAM_IRQ_GPIOA_PINS+23) /* GPIOA, PIN 23 */
# define SAM_IRQ_PA24 (SAM_IRQ_GPIOA_PINS+24) /* GPIOA, PIN 24 */
# define SAM_IRQ_PA25 (SAM_IRQ_GPIOA_PINS+25) /* GPIOA, PIN 25 */
# define SAM_IRQ_PA26 (SAM_IRQ_GPIOA_PINS+26) /* GPIOA, PIN 26 */
# define SAM_IRQ_PA27 (SAM_IRQ_GPIOA_PINS+27) /* GPIOA, PIN 27 */
# define SAM_IRQ_PA28 (SAM_IRQ_GPIOA_PINS+28) /* GPIOA, PIN 28 */
# define SAM_IRQ_PA29 (SAM_IRQ_GPIOA_PINS+29) /* GPIOA, PIN 29 */
# define SAM_IRQ_PA30 (SAM_IRQ_GPIOA_PINS+30) /* GPIOA, PIN 30 */
# define SAM_IRQ_PA31 (SAM_IRQ_GPIOA_PINS+31) /* GPIOA, PIN 31 */
# define SAM_NGPIOAIRQS 32
#else
# define SAM_NGPIOAIRQS 0
#endif
#ifdef CONFIG_SAM34_GPIOB_IRQ
# define SAM_IRQ_GPIOB_PINS (SAM_IRQ_EXTINT + SAM_IRQ_NEXTINT + SAM_NGPIOAIRQS)
# define SAM_IRQ_PB0 (SAM_IRQ_GPIOB_PINS+0) /* GPIOB, PIN 0 */
# define SAM_IRQ_PB1 (SAM_IRQ_GPIOB_PINS+1) /* GPIOB, PIN 1 */
# define SAM_IRQ_PB2 (SAM_IRQ_GPIOB_PINS+2) /* GPIOB, PIN 2 */
# define SAM_IRQ_PB3 (SAM_IRQ_GPIOB_PINS+3) /* GPIOB, PIN 3 */
# define SAM_IRQ_PB4 (SAM_IRQ_GPIOB_PINS+4) /* GPIOB, PIN 4 */
# define SAM_IRQ_PB5 (SAM_IRQ_GPIOB_PINS+5) /* GPIOB, PIN 5 */
# define SAM_IRQ_PB6 (SAM_IRQ_GPIOB_PINS+6) /* GPIOB, PIN 6 */
# define SAM_IRQ_PB7 (SAM_IRQ_GPIOB_PINS+7) /* GPIOB, PIN 7 */
# define SAM_IRQ_PB8 (SAM_IRQ_GPIOB_PINS+8) /* GPIOB, PIN 8 */
# define SAM_IRQ_PB9 (SAM_IRQ_GPIOB_PINS+9) /* GPIOB, PIN 9 */
# define SAM_IRQ_PB10 (SAM_IRQ_GPIOB_PINS+10) /* GPIOB, PIN 10 */
# define SAM_IRQ_PB11 (SAM_IRQ_GPIOB_PINS+11) /* GPIOB, PIN 11 */
# define SAM_IRQ_PB12 (SAM_IRQ_GPIOB_PINS+12) /* GPIOB, PIN 12 */
# define SAM_IRQ_PB13 (SAM_IRQ_GPIOB_PINS+13) /* GPIOB, PIN 13 */
# define SAM_IRQ_PB14 (SAM_IRQ_GPIOB_PINS+14) /* GPIOB, PIN 14 */
# define SAM_IRQ_PB15 (SAM_IRQ_GPIOB_PINS+15) /* GPIOB, PIN 15 */
# define SAM_IRQ_PB16 (SAM_IRQ_GPIOB_PINS+16) /* GPIOB, PIN 16 */
# define SAM_IRQ_PB17 (SAM_IRQ_GPIOB_PINS+17) /* GPIOB, PIN 17 */
# define SAM_IRQ_PB18 (SAM_IRQ_GPIOB_PINS+18) /* GPIOB, PIN 18 */
# define SAM_IRQ_PB19 (SAM_IRQ_GPIOB_PINS+19) /* GPIOB, PIN 19 */
# define SAM_IRQ_PB20 (SAM_IRQ_GPIOB_PINS+20) /* GPIOB, PIN 20 */
# define SAM_IRQ_PB21 (SAM_IRQ_GPIOB_PINS+21) /* GPIOB, PIN 21 */
# define SAM_IRQ_PB22 (SAM_IRQ_GPIOB_PINS+22) /* GPIOB, PIN 22 */
# define SAM_IRQ_PB23 (SAM_IRQ_GPIOB_PINS+23) /* GPIOB, PIN 23 */
# define SAM_IRQ_PB24 (SAM_IRQ_GPIOB_PINS+24) /* GPIOB, PIN 24 */
# define SAM_IRQ_PB25 (SAM_IRQ_GPIOB_PINS+25) /* GPIOB, PIN 25 */
# define SAM_IRQ_PB26 (SAM_IRQ_GPIOB_PINS+26) /* GPIOB, PIN 26 */
# define SAM_IRQ_PB27 (SAM_IRQ_GPIOB_PINS+27) /* GPIOB, PIN 27 */
# define SAM_IRQ_PB28 (SAM_IRQ_GPIOB_PINS+28) /* GPIOB, PIN 28 */
# define SAM_IRQ_PB29 (SAM_IRQ_GPIOB_PINS+29) /* GPIOB, PIN 29 */
# define SAM_IRQ_PB30 (SAM_IRQ_GPIOB_PINS+30) /* GPIOB, PIN 30 */
# define SAM_IRQ_PB31 (SAM_IRQ_GPIOB_PINS+31) /* GPIOB, PIN 31 */
# define SAM_NGPIOBIRQS 32
#else
# define SAM_NGPIOBIRQS 0
#endif
#ifdef CONFIG_SAM34_GPIOC_IRQ
# define SAM_IRQ_GPIOC_PINS (SAM_IRQ_EXTINT + SAM_IRQ_NEXTINT + SAM_NGPIOAIRQS + SAM_NGPIOBIRQS)
# define SAM_IRQ_PC0 (SAM_IRQ_GPIOC_PINS+0) /* GPIOC, PIN 0 */
# define SAM_IRQ_PC1 (SAM_IRQ_GPIOC_PINS+1) /* GPIOC, PIN 1 */
# define SAM_IRQ_PC2 (SAM_IRQ_GPIOC_PINS+2) /* GPIOC, PIN 2 */
# define SAM_IRQ_PC3 (SAM_IRQ_GPIOC_PINS+3) /* GPIOC, PIN 3 */
# define SAM_IRQ_PC4 (SAM_IRQ_GPIOC_PINS+4) /* GPIOC, PIN 4 */
# define SAM_IRQ_PC5 (SAM_IRQ_GPIOC_PINS+5) /* GPIOC, PIN 5 */
# define SAM_IRQ_PC6 (SAM_IRQ_GPIOC_PINS+6) /* GPIOC, PIN 6 */
# define SAM_IRQ_PC7 (SAM_IRQ_GPIOC_PINS+7) /* GPIOC, PIN 7 */
# define SAM_IRQ_PC8 (SAM_IRQ_GPIOC_PINS+8) /* GPIOC, PIN 8 */
# define SAM_IRQ_PC9 (SAM_IRQ_GPIOC_PINS+9) /* GPIOC, PIN 9 */
# define SAM_IRQ_PC10 (SAM_IRQ_GPIOC_PINS+10) /* GPIOC, PIN 10 */
# define SAM_IRQ_PC11 (SAM_IRQ_GPIOC_PINS+11) /* GPIOC, PIN 11 */
# define SAM_IRQ_PC12 (SAM_IRQ_GPIOC_PINS+12) /* GPIOC, PIN 12 */
# define SAM_IRQ_PC13 (SAM_IRQ_GPIOC_PINS+13) /* GPIOC, PIN 13 */
# define SAM_IRQ_PC14 (SAM_IRQ_GPIOC_PINS+14) /* GPIOC, PIN 14 */
# define SAM_IRQ_PC15 (SAM_IRQ_GPIOC_PINS+15) /* GPIOC, PIN 15 */
# define SAM_IRQ_PC16 (SAM_IRQ_GPIOC_PINS+16) /* GPIOC, PIN 16 */
# define SAM_IRQ_PC17 (SAM_IRQ_GPIOC_PINS+17) /* GPIOC, PIN 17 */
# define SAM_IRQ_PC18 (SAM_IRQ_GPIOC_PINS+18) /* GPIOC, PIN 18 */
# define SAM_IRQ_PC19 (SAM_IRQ_GPIOC_PINS+19) /* GPIOC, PIN 19 */
# define SAM_IRQ_PC20 (SAM_IRQ_GPIOC_PINS+20) /* GPIOC, PIN 20 */
# define SAM_IRQ_PC21 (SAM_IRQ_GPIOC_PINS+21) /* GPIOC, PIN 21 */
# define SAM_IRQ_PC22 (SAM_IRQ_GPIOC_PINS+22) /* GPIOC, PIN 22 */
# define SAM_IRQ_PC23 (SAM_IRQ_GPIOC_PINS+23) /* GPIOC, PIN 23 */
# define SAM_IRQ_PC24 (SAM_IRQ_GPIOC_PINS+24) /* GPIOC, PIN 24 */
# define SAM_IRQ_PC25 (SAM_IRQ_GPIOC_PINS+25) /* GPIOC, PIN 25 */
# define SAM_IRQ_PC26 (SAM_IRQ_GPIOC_PINS+26) /* GPIOC, PIN 26 */
# define SAM_IRQ_PC27 (SAM_IRQ_GPIOC_PINS+27) /* GPIOC, PIN 27 */
# define SAM_IRQ_PC28 (SAM_IRQ_GPIOC_PINS+28) /* GPIOC, PIN 28 */
# define SAM_IRQ_PC29 (SAM_IRQ_GPIOC_PINS+29) /* GPIOC, PIN 29 */
# define SAM_IRQ_PC30 (SAM_IRQ_GPIOC_PINS+30) /* GPIOC, PIN 30 */
# define SAM_IRQ_PC31 (SAM_IRQ_GPIOC_PINS+31) /* GPIOC, PIN 31 */
# define SAM_NGPIOCIRQS 32
#else
# define SAM_NGPIOCIRQS 0
#endif
/* Total number of IRQ numbers */
#define NR_VECTORS SAM_IRQ_NIRQS
#define NR_IRQS (SAM_IRQ_EXTINT + SAM_IRQ_NEXTINT + \
SAM_NGPIOAIRQS + SAM_NGPIOBIRQS + SAM_NGPIOCIRQS)
/****************************************************************************************
* Public Types
****************************************************************************************/
/****************************************************************************************
* Inline functions
****************************************************************************************/
/****************************************************************************************
* Public Variables
****************************************************************************************/
/****************************************************************************************
* Public Function Prototypes
****************************************************************************************/
#ifndef __ASSEMBLY__
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif
#endif /* __ARCH_ARM_INCLUDE_SAM34_SAM4L_IRQ_H */

288
arch/arm/include/sam34/sam4s_irq.h
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@ -1,288 +0,0 @@
/****************************************************************************************
* arch/arm/include/sam34/sam4s_irq.h
*
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************************/
/* This file should never be included directed but, rather, only indirectly through
* nuttx/irq.h
*/
#ifndef __ARCH_ARM_INCLUDE_SAM34_SAM4S_IRQ_H
#define __ARCH_ARM_INCLUDE_SAM34_SAM4S_IRQ_H
/****************************************************************************************
* Included Files
****************************************************************************************/
/****************************************************************************************
* Pre-processor Definitions
****************************************************************************************/
/* SAM4S Peripheral Identifiers */
#define SAM_PID_SUPC (0) /* Supply Controller */
#define SAM_PID_RSTC (1) /* Reset Controller */
#define SAM_PID_RTC (2) /* Real Time Clock */
#define SAM_PID_RTT (3) /* Real Time Timer */
#define SAM_PID_WDT (4) /* Watchdog Timer */
#define SAM_PID_PMC (5) /* Power Management Controller */
#define SAM_PID_EEFC0 (6) /* Enhanced Embedded Flash Controller 0 */
#define SAM_PID_EEFC1 (7) /* Enhanced Embedded Flash Controller 1 */
#define SAM_PID_UART0 (8) /* Universal Asynchronous Receiver Transmitter 0 */
#define SAM_PID_UART1 (9) /* Universal Asynchronous Receiver Transmitter 1 */
#define SAM_PID_SMC (10) /* Static Memory Controller */
#define SAM_PID_PIOA (11) /* Parallel I/O Controller A */
#define SAM_PID_PIOB (12) /* Parallel I/O Controller B */
#define SAM_PID_PIOC (13) /* Parallel I/O Controller C */
#define SAM_PID_USART0 (14) /* USART 0 */
#define SAM_PID_USART1 (15) /* USART 1 */
#define SAM_PID_RESERVED_16 (16) /* Reserved */
#define SAM_PID_RESERVED_17 (17) /* Reserved */
#define SAM_PID_HSMCI (18) /* High Speed Multimedia Card Interface */
#define SAM_PID_TWI0 (19) /* Two-Wire Interface 0 */
#define SAM_PID_TWI1 (20) /* Two-Wire Interface 1 */
#define SAM_PID_SPI0 (21) /* Serial Peripheral Interface */
#define SAM_PID_SSC (22) /* Synchronous Serial Controller */
#define SAM_PID_TC0 (23) /* Timer Counter 0 */
#define SAM_PID_TC1 (24) /* Timer Counter 1 */
#define SAM_PID_TC2 (25) /* Timer Counter 2 */
#define SAM_PID_TC3 (26) /* Timer Counter 3 */
#define SAM_PID_TC4 (27) /* Timer Counter 4 */
#define SAM_PID_TC5 (28) /* Timer Counter 5 */
#define SAM_PID_ADC (29) /* Analog To Digital Converter */
#define SAM_PID_DACC (30) /* Digital To Analog Converter */
#define SAM_PID_PWM (31) /* Pulse Width Modulation */
#define SAM_PID_CRCCU (32) /* CRC Calculation Unit */
#define SAM_PID_ACC (33) /* Analog Comparator */
#define SAM_PID_UDP (34) /* USB Device Port */
#define NR_PIDS (35) /* Number of peripheral identifiers */
/* External interrupts (vectors >= 16) */
#define SAM_IRQ_SUPC (SAM_IRQ_EXTINT+SAM_PID_SUPC) /* PID 0: Supply Controller */
#define SAM_IRQ_RSTC (SAM_IRQ_EXTINT+SAM_PID_RSTC) /* PID 1: Reset Controller */
#define SAM_IRQ_RTC (SAM_IRQ_EXTINT+SAM_PID_RTC) /* PID 2: Real Time Clock */
#define SAM_IRQ_RTT (SAM_IRQ_EXTINT+SAM_PID_RTT) /* PID 3: Real Time Timer */
#define SAM_IRQ_WDT (SAM_IRQ_EXTINT+SAM_PID_WDT) /* PID 4: Watchdog Timer */
#define SAM_IRQ_PMC (SAM_IRQ_EXTINT+SAM_PID_PMC) /* PID 5: Power Management Controller */
#define SAM_IRQ_EEFC0 (SAM_IRQ_EXTINT+SAM_PID_EEFC0) /* PID 6: Enhanced Embedded Flash Controller 0 */
#define SAM_IRQ_EEFC1 (SAM_IRQ_EXTINT+SAM_PID_EEFC1) /* PID 7: Enhanced Embedded Flash Controller 1 */
#define SAM_IRQ_UART0 (SAM_IRQ_EXTINT+SAM_PID_UART0) /* PID 8: Universal Asynchronous Receiver Transmitter 0 */
#define SAM_IRQ_UART1 (SAM_IRQ_EXTINT+SAM_PID_UART1) /* PID 9: Universal Asynchronous Receiver Transmitter 1 */
#define SAM_IRQ_SMC (SAM_IRQ_EXTINT+SAM_PID_SMC) /* PID 10: Static Memory Controller */
#define SAM_IRQ_PIOA (SAM_IRQ_EXTINT+SAM_PID_PIOA) /* PID 11: Parallel I/O Controller A */
#define SAM_IRQ_PIOB (SAM_IRQ_EXTINT+SAM_PID_PIOB) /* PID 12: Parallel I/O Controller B */
#define SAM_IRQ_PIOC (SAM_IRQ_EXTINT+SAM_PID_PIOC) /* PID 13: Parallel I/O Controller C */
#define SAM_IRQ_USART0 (SAM_IRQ_EXTINT+SAM_PID_USART0) /* PID 14: USART 0 */
#define SAM_IRQ_USART1 (SAM_IRQ_EXTINT+SAM_PID_USART1) /* PID 15: USART 1 */
#define SAM_IRQ_RESERVED_16 (SAM_IRQ_EXTINT+SAM_PID_RESERVED_16) /* PID 16: Reserved */
#define SAM_IRQ_RESERVED_17 (SAM_IRQ_EXTINT+SAM_PID_RESERVED_17) /* PID 17: Reserved */
#define SAM_IRQ_HSMCI (SAM_IRQ_EXTINT+SAM_PID_HSMCI) /* PID 18: High Speed Multimedia Card Interface */
#define SAM_IRQ_TWI0 (SAM_IRQ_EXTINT+SAM_PID_TWI0) /* PID 19: Two-Wire Interface 0 */
#define SAM_IRQ_TWI1 (SAM_IRQ_EXTINT+SAM_PID_TWI1) /* PID 20: Two-Wire Interface 1 */
#define SAM_IRQ_SPI0 (SAM_IRQ_EXTINT+SAM_PID_SPI0) /* PIC 21: Serial Peripheral Interface */
#define SAM_IRQ_SSC (SAM_IRQ_EXTINT+SAM_PID_SSC) /* PID 22: Synchronous Serial Controller */
#define SAM_IRQ_TC0 (SAM_IRQ_EXTINT+SAM_PID_TC0) /* PID 23: Timer Counter 0 */
#define SAM_IRQ_TC1 (SAM_IRQ_EXTINT+SAM_PID_TC1) /* PID 24: Timer Counter 1 */
#define SAM_IRQ_TC2 (SAM_IRQ_EXTINT+SAM_PID_TC2) /* PID 25: Timer Counter 2 */
#define SAM_IRQ_TC3 (SAM_IRQ_EXTINT+SAM_PID_TC3) /* PID 26: Timer Counter 3 */
#define SAM_IRQ_TC4 (SAM_IRQ_EXTINT+SAM_PID_TC4) /* PID 27: Timer Counter 4 */
#define SAM_IRQ_TC5 (SAM_IRQ_EXTINT+SAM_PID_TC5) /* PID 28: Timer Counter 5 */
#define SAM_IRQ_ADC (SAM_IRQ_EXTINT+SAM_PID_ADC) /* PID 29: Analog To Digital Converter */
#define SAM_IRQ_DACC (SAM_IRQ_EXTINT+SAM_PID_DACC) /* PID 30: Digital To Analog Converter */
#define SAM_IRQ_PWM (SAM_IRQ_EXTINT+SAM_PID_PWM) /* PID 31: Pulse Width Modulation */
#define SAM_IRQ_CRCCU (SAM_IRQ_EXTINT+SAM_PID_CRCCU) /* PID 32: CRC Calculation Unit */
#define SAM_IRQ_ACC (SAM_IRQ_EXTINT+SAM_PID_ACC) /* PID 33: Analog Comparator */
#define SAM_IRQ_UDP (SAM_IRQ_EXTINT+SAM_PID_UDP) /* PID 34: USB Device Port */
#define SAM_IRQ_NEXTINT NR_PIDS /* Total number of external interrupt numbers */
#define SAM_IRQ_NIRQS (SAM_IRQ_EXTINT + NR_PIDS) /* The number of real IRQs */
/* GPIO interrupts (derived from SAM_IRQ_PIOA/B/C) */
#ifdef CONFIG_SAM34_GPIOA_IRQ
# define SAM_IRQ_GPIOA_PINS (SAM_IRQ_EXTINT + SAM_IRQ_NEXTINT)
# define SAM_IRQ_PA0 (SAM_IRQ_GPIOA_PINS+0) /* GPIOA, PIN 0 */
# define SAM_IRQ_PA1 (SAM_IRQ_GPIOA_PINS+1) /* GPIOA, PIN 1 */
# define SAM_IRQ_PA2 (SAM_IRQ_GPIOA_PINS+2) /* GPIOA, PIN 2 */
# define SAM_IRQ_PA3 (SAM_IRQ_GPIOA_PINS+3) /* GPIOA, PIN 3 */
# define SAM_IRQ_PA4 (SAM_IRQ_GPIOA_PINS+4) /* GPIOA, PIN 4 */
# define SAM_IRQ_PA5 (SAM_IRQ_GPIOA_PINS+5) /* GPIOA, PIN 5 */
# define SAM_IRQ_PA6 (SAM_IRQ_GPIOA_PINS+6) /* GPIOA, PIN 6 */
# define SAM_IRQ_PA7 (SAM_IRQ_GPIOA_PINS+7) /* GPIOA, PIN 7 */
# define SAM_IRQ_PA8 (SAM_IRQ_GPIOA_PINS+8) /* GPIOA, PIN 8 */
# define SAM_IRQ_PA9 (SAM_IRQ_GPIOA_PINS+9) /* GPIOA, PIN 9 */
# define SAM_IRQ_PA10 (SAM_IRQ_GPIOA_PINS+10) /* GPIOA, PIN 10 */
# define SAM_IRQ_PA11 (SAM_IRQ_GPIOA_PINS+11) /* GPIOA, PIN 11 */
# define SAM_IRQ_PA12 (SAM_IRQ_GPIOA_PINS+12) /* GPIOA, PIN 12 */
# define SAM_IRQ_PA13 (SAM_IRQ_GPIOA_PINS+13) /* GPIOA, PIN 13 */
# define SAM_IRQ_PA14 (SAM_IRQ_GPIOA_PINS+14) /* GPIOA, PIN 14 */
# define SAM_IRQ_PA15 (SAM_IRQ_GPIOA_PINS+15) /* GPIOA, PIN 15 */
# define SAM_IRQ_PA16 (SAM_IRQ_GPIOA_PINS+16) /* GPIOA, PIN 16 */
# define SAM_IRQ_PA17 (SAM_IRQ_GPIOA_PINS+17) /* GPIOA, PIN 17 */
# define SAM_IRQ_PA18 (SAM_IRQ_GPIOA_PINS+18) /* GPIOA, PIN 18 */
# define SAM_IRQ_PA19 (SAM_IRQ_GPIOA_PINS+19) /* GPIOA, PIN 19 */
# define SAM_IRQ_PA20 (SAM_IRQ_GPIOA_PINS+20) /* GPIOA, PIN 20 */
# define SAM_IRQ_PA21 (SAM_IRQ_GPIOA_PINS+21) /* GPIOA, PIN 21 */
# define SAM_IRQ_PA22 (SAM_IRQ_GPIOA_PINS+22) /* GPIOA, PIN 22 */
# define SAM_IRQ_PA23 (SAM_IRQ_GPIOA_PINS+23) /* GPIOA, PIN 23 */
# define SAM_IRQ_PA24 (SAM_IRQ_GPIOA_PINS+24) /* GPIOA, PIN 24 */
# define SAM_IRQ_PA25 (SAM_IRQ_GPIOA_PINS+25) /* GPIOA, PIN 25 */
# define SAM_IRQ_PA26 (SAM_IRQ_GPIOA_PINS+26) /* GPIOA, PIN 26 */
# define SAM_IRQ_PA27 (SAM_IRQ_GPIOA_PINS+27) /* GPIOA, PIN 27 */
# define SAM_IRQ_PA28 (SAM_IRQ_GPIOA_PINS+28) /* GPIOA, PIN 28 */
# define SAM_IRQ_PA29 (SAM_IRQ_GPIOA_PINS+29) /* GPIOA, PIN 29 */
# define SAM_IRQ_PA30 (SAM_IRQ_GPIOA_PINS+30) /* GPIOA, PIN 30 */
# define SAM_IRQ_PA31 (SAM_IRQ_GPIOA_PINS+31) /* GPIOA, PIN 31 */
# define SAM_NGPIOAIRQS 32
#else
# define SAM_NGPIOAIRQS 0
#endif
#ifdef CONFIG_SAM34_GPIOB_IRQ
# define SAM_IRQ_GPIOB_PINS (SAM_IRQ_EXTINT + SAM_IRQ_NEXTINT + SAM_NGPIOAIRQS)
# define SAM_IRQ_PB0 (SAM_IRQ_GPIOB_PINS+0) /* GPIOB, PIN 0 */
# define SAM_IRQ_PB1 (SAM_IRQ_GPIOB_PINS+1) /* GPIOB, PIN 1 */
# define SAM_IRQ_PB2 (SAM_IRQ_GPIOB_PINS+2) /* GPIOB, PIN 2 */
# define SAM_IRQ_PB3 (SAM_IRQ_GPIOB_PINS+3) /* GPIOB, PIN 3 */
# define SAM_IRQ_PB4 (SAM_IRQ_GPIOB_PINS+4) /* GPIOB, PIN 4 */
# define SAM_IRQ_PB5 (SAM_IRQ_GPIOB_PINS+5) /* GPIOB, PIN 5 */
# define SAM_IRQ_PB6 (SAM_IRQ_GPIOB_PINS+6) /* GPIOB, PIN 6 */
# define SAM_IRQ_PB7 (SAM_IRQ_GPIOB_PINS+7) /* GPIOB, PIN 7 */
# define SAM_IRQ_PB8 (SAM_IRQ_GPIOB_PINS+8) /* GPIOB, PIN 8 */
# define SAM_IRQ_PB9 (SAM_IRQ_GPIOB_PINS+9) /* GPIOB, PIN 9 */
# define SAM_IRQ_PB10 (SAM_IRQ_GPIOB_PINS+10) /* GPIOB, PIN 10 */
# define SAM_IRQ_PB11 (SAM_IRQ_GPIOB_PINS+11) /* GPIOB, PIN 11 */
# define SAM_IRQ_PB12 (SAM_IRQ_GPIOB_PINS+12) /* GPIOB, PIN 12 */
# define SAM_IRQ_PB13 (SAM_IRQ_GPIOB_PINS+13) /* GPIOB, PIN 13 */
# define SAM_IRQ_PB14 (SAM_IRQ_GPIOB_PINS+14) /* GPIOB, PIN 14 */
# define SAM_IRQ_PB15 (SAM_IRQ_GPIOB_PINS+15) /* GPIOB, PIN 15 */
# define SAM_IRQ_PB16 (SAM_IRQ_GPIOB_PINS+16) /* GPIOB, PIN 16 */
# define SAM_IRQ_PB17 (SAM_IRQ_GPIOB_PINS+17) /* GPIOB, PIN 17 */
# define SAM_IRQ_PB18 (SAM_IRQ_GPIOB_PINS+18) /* GPIOB, PIN 18 */
# define SAM_IRQ_PB19 (SAM_IRQ_GPIOB_PINS+19) /* GPIOB, PIN 19 */
# define SAM_IRQ_PB20 (SAM_IRQ_GPIOB_PINS+20) /* GPIOB, PIN 20 */
# define SAM_IRQ_PB21 (SAM_IRQ_GPIOB_PINS+21) /* GPIOB, PIN 21 */
# define SAM_IRQ_PB22 (SAM_IRQ_GPIOB_PINS+22) /* GPIOB, PIN 22 */
# define SAM_IRQ_PB23 (SAM_IRQ_GPIOB_PINS+23) /* GPIOB, PIN 23 */
# define SAM_IRQ_PB24 (SAM_IRQ_GPIOB_PINS+24) /* GPIOB, PIN 24 */
# define SAM_IRQ_PB25 (SAM_IRQ_GPIOB_PINS+25) /* GPIOB, PIN 25 */
# define SAM_IRQ_PB26 (SAM_IRQ_GPIOB_PINS+26) /* GPIOB, PIN 26 */
# define SAM_IRQ_PB27 (SAM_IRQ_GPIOB_PINS+27) /* GPIOB, PIN 27 */
# define SAM_IRQ_PB28 (SAM_IRQ_GPIOB_PINS+28) /* GPIOB, PIN 28 */
# define SAM_IRQ_PB29 (SAM_IRQ_GPIOB_PINS+29) /* GPIOB, PIN 29 */
# define SAM_IRQ_PB30 (SAM_IRQ_GPIOB_PINS+30) /* GPIOB, PIN 30 */
# define SAM_IRQ_PB31 (SAM_IRQ_GPIOB_PINS+31) /* GPIOB, PIN 31 */
# define SAM_NGPIOBIRQS 32
#else
# define SAM_NGPIOBIRQS 0
#endif
#ifdef CONFIG_SAM34_GPIOC_IRQ
# define SAM_IRQ_GPIOC_PINS (SAM_IRQ_EXTINT + SAM_IRQ_NEXTINT + SAM_NGPIOAIRQS + SAM_NGPIOBIRQS)
# define SAM_IRQ_PC0 (SAM_IRQ_GPIOC_PINS+0) /* GPIOC, PIN 0 */
# define SAM_IRQ_PC1 (SAM_IRQ_GPIOC_PINS+1) /* GPIOC, PIN 1 */
# define SAM_IRQ_PC2 (SAM_IRQ_GPIOC_PINS+2) /* GPIOC, PIN 2 */
# define SAM_IRQ_PC3 (SAM_IRQ_GPIOC_PINS+3) /* GPIOC, PIN 3 */
# define SAM_IRQ_PC4 (SAM_IRQ_GPIOC_PINS+4) /* GPIOC, PIN 4 */
# define SAM_IRQ_PC5 (SAM_IRQ_GPIOC_PINS+5) /* GPIOC, PIN 5 */
# define SAM_IRQ_PC6 (SAM_IRQ_GPIOC_PINS+6) /* GPIOC, PIN 6 */
# define SAM_IRQ_PC7 (SAM_IRQ_GPIOC_PINS+7) /* GPIOC, PIN 7 */
# define SAM_IRQ_PC8 (SAM_IRQ_GPIOC_PINS+8) /* GPIOC, PIN 8 */
# define SAM_IRQ_PC9 (SAM_IRQ_GPIOC_PINS+9) /* GPIOC, PIN 9 */
# define SAM_IRQ_PC10 (SAM_IRQ_GPIOC_PINS+10) /* GPIOC, PIN 10 */
# define SAM_IRQ_PC11 (SAM_IRQ_GPIOC_PINS+11) /* GPIOC, PIN 11 */
# define SAM_IRQ_PC12 (SAM_IRQ_GPIOC_PINS+12) /* GPIOC, PIN 12 */
# define SAM_IRQ_PC13 (SAM_IRQ_GPIOC_PINS+13) /* GPIOC, PIN 13 */
# define SAM_IRQ_PC14 (SAM_IRQ_GPIOC_PINS+14) /* GPIOC, PIN 14 */
# define SAM_IRQ_PC15 (SAM_IRQ_GPIOC_PINS+15) /* GPIOC, PIN 15 */
# define SAM_IRQ_PC16 (SAM_IRQ_GPIOC_PINS+16) /* GPIOC, PIN 16 */
# define SAM_IRQ_PC17 (SAM_IRQ_GPIOC_PINS+17) /* GPIOC, PIN 17 */
# define SAM_IRQ_PC18 (SAM_IRQ_GPIOC_PINS+18) /* GPIOC, PIN 18 */
# define SAM_IRQ_PC19 (SAM_IRQ_GPIOC_PINS+19) /* GPIOC, PIN 19 */
# define SAM_IRQ_PC20 (SAM_IRQ_GPIOC_PINS+20) /* GPIOC, PIN 20 */
# define SAM_IRQ_PC21 (SAM_IRQ_GPIOC_PINS+21) /* GPIOC, PIN 21 */
# define SAM_IRQ_PC22 (SAM_IRQ_GPIOC_PINS+22) /* GPIOC, PIN 22 */
# define SAM_IRQ_PC23 (SAM_IRQ_GPIOC_PINS+23) /* GPIOC, PIN 23 */
# define SAM_IRQ_PC24 (SAM_IRQ_GPIOC_PINS+24) /* GPIOC, PIN 24 */
# define SAM_IRQ_PC25 (SAM_IRQ_GPIOC_PINS+25) /* GPIOC, PIN 25 */
# define SAM_IRQ_PC26 (SAM_IRQ_GPIOC_PINS+26) /* GPIOC, PIN 26 */
# define SAM_IRQ_PC27 (SAM_IRQ_GPIOC_PINS+27) /* GPIOC, PIN 27 */
# define SAM_IRQ_PC28 (SAM_IRQ_GPIOC_PINS+28) /* GPIOC, PIN 28 */
# define SAM_IRQ_PC29 (SAM_IRQ_GPIOC_PINS+29) /* GPIOC, PIN 29 */
# define SAM_IRQ_PC30 (SAM_IRQ_GPIOC_PINS+30) /* GPIOC, PIN 30 */
# define SAM_IRQ_PC31 (SAM_IRQ_GPIOC_PINS+31) /* GPIOC, PIN 31 */
# define SAM_NGPIOCIRQS 32
#else
# define SAM_NGPIOCIRQS 0
#endif
/* Total number of IRQ numbers */
#define NR_VECTORS SAM_IRQ_NIRQS
#define NR_IRQS (SAM_IRQ_EXTINT + SAM_IRQ_NEXTINT + \
SAM_NGPIOAIRQS + SAM_NGPIOBIRQS + SAM_NGPIOCIRQS)
/****************************************************************************************
* Public Types
****************************************************************************************/
/****************************************************************************************
* Inline functions
****************************************************************************************/
/****************************************************************************************
* Public Variables
****************************************************************************************/
/****************************************************************************************
* Public Function Prototypes
****************************************************************************************/
#ifndef __ASSEMBLY__
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif
#endif /* __ARCH_ARM_INCLUDE_SAM34_SAM4S_IRQ_H */

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arch/arm/include/sama5/chip.h
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@ -1,166 +0,0 @@
/****************************************************************************************************
* arch/arm/include/sama5/chip.h
*
* Copyright (C) 2013-2014 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************************************/
#ifndef __ARCH_ARM_INCLUDE_SAMA5_CHIP_H
#define __ARCH_ARM_INCLUDE_SAMA5_CHIP_H
/****************************************************************************************************
* Included Files
****************************************************************************************************/
#include <nuttx/config.h>
/****************************************************************************************************
* Pre-processor Definitions
****************************************************************************************************/
/* SAMA5D3 Family
*
* ATSAMA5D31 ATSAMA5D33 ATSAMA5D34 ATSAMA5D35 ATSAMA5D36
* ------------------------- ------------- ------------- ------------- ------------- -------------
* Pin Count 324 324 324 324 324
* Max. Operating Frequency 536 MHz 536 MHz 536 MHz 536 MHz 536 MHz
* CPU Cortex-A5 Cortex-A5 Cortex-A5 Cortex-A5 Cortex-A5
* Max I/O Pins 160 160 160 160 160
* Ext Interrupts 160 160 160 160 160
* USB Transceiver 3 3 3 3 3
* USB Speed Hi-Speed Hi-Speed Hi-Speed Hi-Speed Hi-Speed
* USB Interface Host, Device Host, Device Host, Device Host, Device Host, Device
* SPI 6 6 6 6 6
* TWI (I2C) 3 3 3 3 3
* UART 7 5 5 7 7
* CAN - - 2 2 2
* LIN 4 4 4 4 4
* SSC 2 2 2 2 2
* Ethernet 1 1 1 2 2
* SD / eMMC 3 2 3 2 3
* Graphic LCD Yes Yes Yes - Yes
* Camera Interface Yes Yes Yes Yes Yes
* ADC channels 12 12 12 12 12
* ADC Resolution (bits) 12 12 12 12 12
* ADC Speed (ksps) 440 440 440 440 1000
* Resistive Touch Screen Yes Yes Yes Yes Yes
* Crypto Engine AES/DES/ AES/DES/ AES/DES/ AES/DES/ AES/DES/
* SHA/TRNG SHA/TRNG SHA/TRNG SHA/TRNG SHA/TRNG
* SRAM (Kbytes) 128 128 128 128 128
* External Bus Interface 1 1 1 1 1
* DRAM Memory DDR2/LPDDR, DDR2/LPDDR, DDR2/LPDDR, DDR2/LPDDR, DDR2/LPDDR,
* SDRAM/LPSDR SDRAM/LPSDR DDR2/LPDDR, DDR2/LPDDR, DDR2/LPDDR,
* NAND Interface Yes Yes Yes Yes Yes
* Temp. Range (deg C) -40 to 85 -40 to 85 -40 to 85 -40 to 85 -40 to 105
* I/O Supply Class 1.8/3.3 1.8/3.3 1.8/3.3 1.8/3.3 1.8/3.3
* Operating Voltage (Vcc) 1.08 to 1.32 1.08 to 1.32 1.08 to 1.32 1.08 to 1.322 1.08 to 1.32
* FPU Yes Yes Yes Yes Yes
* MPU / MMU No/Yes No/Yes No/Yes No/Yes No/Yes
* Timers 5 5 5 6 6
* Output Compare channels 6 6 6 6 6
* Input Capture Channels 6 6 6 6 6
* PWM Channels 4 4 4 4 4
* 32kHz RTC Yes Yes Yes Yes Yes
* Packages LFBGA324_A LFBGA324_A LFBGA324_A LFBGA324_A LFBGA324_A
*/
#if defined(CONFIG_ARCH_CHIP_ATSAMA5D31)
# define ATSAMA5D3 1 /* SAMA5D3 family */
# undef ATSAMA5D4 /* Not SAMA5D4 family */
# define SAM_ISRAM0_SIZE (64*1024) /* 128KB of SRAM in two banks */
# define SAM_ISRAM1_SIZE (64*1024)
# define SAM_NDMAC 2 /* (2) DMA controllers */
# define SAM_NDMACHAN 8 /* (8) DMA channels per DMA controller */
#elif defined(CONFIG_ARCH_CHIP_ATSAMA5D33)
# define ATSAMA5D3 1 /* SAMA5D3 family */
# undef ATSAMA5D4 /* Not SAMA5D4 family */
# define SAM_ISRAM0_SIZE (64*1024) /* 128KB of SRAM in two banks */
# define SAM_ISRAM1_SIZE (64*1024)
# define SAM_NDMAC 2 /* (2) DMA controllers */
# define SAM_NDMACHAN 8 /* (8) DMA channels per DMA controller */
#elif defined(CONFIG_ARCH_CHIP_ATSAMA5D34)
# define ATSAMA5D3 1 /* SAMA5D3 family */
# undef ATSAMA5D4 /* Not SAMA5D4 family */
# define SAM_ISRAM0_SIZE (64*1024) /* 128KB of SRAM in two banks */
# define SAM_ISRAM1_SIZE (64*1024)
# define SAM_NDMAC 2 /* (2) DMA controllers */
# define SAM_NDMACHAN 8 /* (8) DMA channels per DMA controller */
#elif defined(CONFIG_ARCH_CHIP_ATSAMA5D35)
# define ATSAMA5D3 1 /* SAMA5D3 family */
# undef ATSAMA5D4 /* Not SAMA5D4 family */
# define SAM_ISRAM0_SIZE (64*1024) /* 128KB of SRAM in two banks */
# define SAM_ISRAM1_SIZE (64*1024)
# define SAM_NDMAC 2 /* (2) DMA controllers */
# define SAM_NDMACHAN 8 /* (8) DMA channels per DMA controller */
#elif defined(CONFIG_ARCH_CHIP_ATSAMA5D36)
# define ATSAMA5D3 1 /* SAMA5D3 family */
# undef ATSAMA5D4 /* Not SAMA5D4 family */
# define SAM_ISRAM0_SIZE (64*1024) /* 128KB of SRAM in two banks */
# define SAM_ISRAM1_SIZE (64*1024)
# define SAM_NDMAC 2 /* (2) DMA controllers */
# define SAM_NDMACHAN 8 /* (8) DMA channels per DMA controller */
/* The SAMA5D4 series devices are similar to the SAMA5D3 family except that:
*
* - Some parts support a 32-bit DDR data path (SAMA5D42 and SAMA5D44)
* - Some parts support a Video Decoder (SAMA5D43 and SAMA5D44)
* - Includes an L2 data cache, NEON FPU, and TrustZone
* - New XDMAC DMA controller
* - There are few differences in the support peripherals. As examples:
* Gigbit Ethernet is not supported, for example; 10/100Base-T Ethernet
* is different. Additional instances of peripherals: USART4, TWI3,
* and SPI2.
*/
#elif defined(CONFIG_ARCH_CHIP_ATSAMA5D41) || defined(CONFIG_ARCH_CHIP_ATSAMA5D42) || \
defined(CONFIG_ARCH_CHIP_ATSAMA5D43) || defined(CONFIG_ARCH_CHIP_ATSAMA5D44)
# undef ATSAMA5D3 /* Not SAMA5D3 family */
# define ATSAMA5D4 1 /* SAMA5D4 family */
# define SAM_ISRAM0_SIZE (64*1024) /* 128KB of SRAM in two banks */
# define SAM_ISRAM1_SIZE (64*1024)
# define SAM_NDMAC 2 /* (2) XDMA controllers */
# define SAM_NDMACHAN 16 /* (16) DMA channels per XDMA controller */
#else
# error Unrecognized SAMAD5 chip
#endif
/****************************************************************************************************
* Public Types
****************************************************************************************************/
/****************************************************************************************************
* Public Data
****************************************************************************************************/
/****************************************************************************************************
* Public Functions
****************************************************************************************************/
#endif /* __ARCH_ARM_INCLUDE_SAMA5_CHIP_H */

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arch/arm/include/sama5/irq.h
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@ -1,93 +0,0 @@
/****************************************************************************************
* arch/arm/include/sama5/irq.h
*
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************************/
/* This file should never be included directed but, rather, only indirectly through
* nuttx/irq.h
*/
#ifndef __ARCH_ARM_INCLUDE_SAMA5_IRQ_H
#define __ARCH_ARM_INCLUDE_SAMA5_IRQ_H
/****************************************************************************************
* Included Files
****************************************************************************************/
#include <nuttx/config.h>
#include <arch/sama5/chip.h>
/****************************************************************************************
* Pre-processor Definitions
****************************************************************************************/
/* Chip-Specific External interrupts */
#if defined(ATSAMA5D3)
# include <arch/sama5/sama5d3_irq.h>
#elif defined(ATSAMA5D4)
# include <arch/sama5/sama5d4_irq.h>
#else
# error Unrecognized SAMA5 family
#endif
/****************************************************************************************
* Public Types
****************************************************************************************/
#ifndef __ASSEMBLY__
/****************************************************************************************
* Public Data
****************************************************************************************/
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************************
* Public Function Prototypes
****************************************************************************************/
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif
#endif /* __ARCH_ARM_INCLUDE_SAMA5_IRQ_H */

396
arch/arm/include/sama5/sama5d3_irq.h
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@ -1,396 +0,0 @@
/****************************************************************************************
* arch/arm/include/sama5/sama5d3_irq.h
*
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************************/
/* This file should never be included directed but, rather, only indirectly through
* nuttx/irq.h
*/
#ifndef __ARCH_ARM_INCLUDE_SAMA5_SAMA5D3_IRQ_H
#define __ARCH_ARM_INCLUDE_SAMA5_SAMA5D3_IRQ_H
/****************************************************************************************
* Included Files
****************************************************************************************/
/****************************************************************************************
* Pre-processor Definitions
****************************************************************************************/
/* SAMA5D3 Peripheral Identifiers */
#define SAM_PID_FIQ (0) /* Advanced Interrupt Controller FIQ */
#define SAM_PID_SYS (1) /* System Controller Interrupt PMC */
#define SAM_PID_DBGU (2) /* Debug Unit Interrupt */
#define SAM_PID_PIT (3) /* Periodic Interval Timer Interrupt */
#define SAM_PID_WDT (4) /* Watchdog timer Interrupt */
#define SAM_PID_HSMC (5) /* Multi-bit ECC Interrupt */
#define SAM_PID_PIOA (6) /* Parallel I/O Controller A */
#define SAM_PID_PIOB (7) /* Parallel I/O Controller B */
#define SAM_PID_PIOC (8) /* Parallel I/O Controller C */
#define SAM_PID_PIOD (9) /* Parallel I/O Controller D */
#define SAM_PID_PIOE (10) /* Parallel I/O Controller E */
#define SAM_PID_SMD (11) /* SMD Soft Modem */
#define SAM_PID_USART0 (12) /* USART 0 */
#define SAM_PID_USART1 (13) /* USART 1 */
#define SAM_PID_USART2 (14) /* USART 2 */
#define SAM_PID_USART3 (15) /* USART 3 */
#define SAM_PID_UART0 (16) /* UART 0 */
#define SAM_PID_UART1 (17) /* UART 1 */
#define SAM_PID_TWI0 (18) /* Two-Wire Interface 0 */
#define SAM_PID_TWI1 (19) /* Two-Wire Interface 1 */
#define SAM_PID_TWI2 (20) /* Two-Wire Interface 2 */
#define SAM_PID_HSMCI0 (21) /* High Speed Multimedia Card Interface 0 */
#define SAM_PID_HSMCI1 (22) /* High Speed Multimedia Card Interface 1 */
#define SAM_PID_HSMCI2 (23) /* High Speed Multimedia Card Interface 2 */
#define SAM_PID_SPI0 (24) /* Serial Peripheral Interface 0 */
#define SAM_PID_SPI1 (25) /* Serial Peripheral Interface 1 */
#define SAM_PID_TC0 (26) /* Timer Counter 0 (ch. 0, 1, 2) */
#define SAM_PID_TC1 (27) /* Timer Counter 1 (ch. 3, 4, 5) */
#define SAM_PID_PWM (28) /* Pulse Width Modulation Controller */
#define SAM_PID_ADC (29) /* Touch Screen ADC Controller */
#define SAM_PID_DMAC0 (30) /* DMA Controller 0 */
#define SAM_PID_DMAC1 (31) /* DMA Controller 1 */
#define SAM_PID_UHPHS (32) /* USB Host High Speed */
#define SAM_PID_UDPHS (33) /* USB Device High Speed */
#define SAM_PID_GMAC (34) /* Gigabit Ethernet MAC */
#define SAM_PID_EMAC (35) /* Ethernet MAC */
#define SAM_PID_LCDC (36) /* LCD Controller */
#define SAM_PID_ISI (37) /* Image Sensor Interface */
#define SAM_PID_SSC0 (38) /* Synchronous Serial Controller 0 */
#define SAM_PID_SSC1 (39) /* Synchronous Serial Controller 1 */
#define SAM_PID_CAN0 (40) /* CAN controller 0 */
#define SAM_PID_CAN1 (41) /* CAN controller 1 */
#define SAM_PID_SHA (42) /* Secure Hash Algorithm */
#define SAM_PID_AES (43) /* Advanced Encryption Standard */
#define SAM_PID_TDES (44) /* Triple Data Encryption Standard */
#define SAM_PID_TRNG (45) /* True Random Number Generator */
#define SAM_PID_ARM (46) /* Performance Monitor Unit */
#define SAM_PID_AIC (47) /* Advanced Interrupt Controller IRQ */
#define SAM_PID_FUSE (48) /* Fuse Controller */
#define SAM_PID_MPDDRC (49) /* MPDDR controller */
/* 50-63 Reserved */
/* External interrupts vectors numbers (same as peripheral ID) */
#define SAM_IRQ_FIQ SAM_PID_FIQ /* Advanced Interrupt Controller FIQ */
#define SAM_IRQ_SYS SAM_PID_SYS /* System Controller Interrupt PMC */
#define SAM_IRQ_DBGU SAM_PID_DBGU /* Debug Unit Interrupt */
#define SAM_IRQ_PIT SAM_PID_PIT /* Periodic Interval Timer Interrupt */
#define SAM_IRQ_WDT SAM_PID_WDT /* Watchdog timer Interrupt */
#define SAM_IRQ_HSMC SAM_PID_HSMC /* Multi-bit ECC Interrupt */
#define SAM_IRQ_PIOA SAM_PID_PIOA /* Parallel I/O Controller A */
#define SAM_IRQ_PIOB SAM_PID_PIOB /* Parallel I/O Controller B */
#define SAM_IRQ_PIOC SAM_PID_PIOC /* Parallel I/O Controller C */
#define SAM_IRQ_PIOD SAM_PID_PIOD /* Parallel I/O Controller D */
#define SAM_IRQ_PIOE SAM_PID_PIOE /* Parallel I/O Controller E */
#define SAM_IRQ_SMD SAM_PID_SMD /* SMD Soft Modem */
#define SAM_IRQ_USART0 SAM_PID_USART0 /* USART 0 */
#define SAM_IRQ_USART1 SAM_PID_USART1 /* USART 1 */
#define SAM_IRQ_USART2 SAM_PID_USART2 /* USART 2 */
#define SAM_IRQ_USART3 SAM_PID_USART3 /* USART 3 */
#define SAM_IRQ_UART0 SAM_PID_UART0 /* UART 0 */
#define SAM_IRQ_UART1 SAM_PID_UART1 /* UART 1 */
#define SAM_IRQ_TWI0 SAM_PID_TWI0 /* Two-Wire Interface 0 */
#define SAM_IRQ_TWI1 SAM_PID_TWI1 /* Two-Wire Interface 1 */
#define SAM_IRQ_TWI2 SAM_PID_TWI2 /* Two-Wire Interface 2 */
#define SAM_IRQ_HSMCI0 SAM_PID_HSMCI0 /* High Speed Multimedia Card Interface 0 */
#define SAM_IRQ_HSMCI1 SAM_PID_HSMCI1 /* High Speed Multimedia Card Interface 1 */
#define SAM_IRQ_HSMCI2 SAM_PID_HSMCI2 /* High Speed Multimedia Card Interface 2 */
#define SAM_IRQ_SPI0 SAM_PID_SPI0 /* Serial Peripheral Interface 0 */
#define SAM_IRQ_SPI1 SAM_PID_SPI1 /* Serial Peripheral Interface 1 */
#define SAM_IRQ_TC0 SAM_PID_TC0 /* Timer Counter 0 (ch. 0, 1, 2) */
#define SAM_IRQ_TC1 SAM_PID_TC1 /* Timer Counter 1 (ch. 3, 4, 5) */
#define SAM_IRQ_PWM SAM_PID_PWM /* Pulse Width Modulation Controller */
#define SAM_IRQ_ADC SAM_PID_ADC /* Touch Screen ADC Controller */
#define SAM_IRQ_DMAC0 SAM_PID_DMAC0 /* DMA Controller 0 */
#define SAM_IRQ_DMAC1 SAM_PID_DMAC1 /* DMA Controller 1 */
#define SAM_IRQ_UHPHS SAM_PID_UHPHS /* USB Host High Speed */
#define SAM_IRQ_UDPHS SAM_PID_UDPHS /* USB Device High Speed */
#define SAM_IRQ_GMAC SAM_PID_GMAC /* Gigabit Ethernet MAC */
#define SAM_IRQ_EMAC SAM_PID_EMAC /* Ethernet MAC */
#define SAM_IRQ_LCDC SAM_PID_LCDC /* LCD Controller */
#define SAM_IRQ_ISI SAM_PID_ISI /* Image Sensor Interface */
#define SAM_IRQ_SSC0 SAM_PID_SSC0 /* Synchronous Serial Controller 0 */
#define SAM_IRQ_SSC1 SAM_PID_SSC1 /* Synchronous Serial Controller 1 */
#define SAM_IRQ_CAN0 SAM_PID_CAN0 /* CAN controller 0 */
#define SAM_IRQ_CAN1 SAM_PID_CAN1 /* CAN controller 1 */
#define SAM_IRQ_SHA SAM_PID_SHA /* Secure Hash Algorithm */
#define SAM_IRQ_AES SAM_PID_AES /* Advanced Encryption Standard */
#define SAM_IRQ_TDES SAM_PID_TDES /* Triple Data Encryption Standard */
#define SAM_IRQ_TRNG SAM_PID_TRNG /* True Random Number Generator */
#define SAM_IRQ_ARM SAM_PID_ARM /* Performance Monitor Unit */
#define SAM_IRQ_AIC SAM_PID_AIC /* Advanced Interrupt Controller IRQ */
#define SAM_IRQ_FUSE SAM_PID_FUSE /* Fuse Controller */
#define SAM_IRQ_MPDDRC SAM_PID_MPDDRC /* MPDDR controller */
#define SAM_IRQ_NINT (SAM_PID_MPDDRC + 1)
/* PIO interrupts (derived from SAM_IRQ_PIOA/B/C/D/E/F) */
#ifdef CONFIG_SAMA5_PIOA_IRQ
# define SAM_IRQ_PIOA_PINS (SAM_IRQ_NINT)
# define SAM_IRQ_PA0 (SAM_IRQ_PIOA_PINS+0) /* PIOA, PIN 0 */
# define SAM_IRQ_PA1 (SAM_IRQ_PIOA_PINS+1) /* PIOA, PIN 1 */
# define SAM_IRQ_PA2 (SAM_IRQ_PIOA_PINS+2) /* PIOA, PIN 2 */
# define SAM_IRQ_PA3 (SAM_IRQ_PIOA_PINS+3) /* PIOA, PIN 3 */
# define SAM_IRQ_PA4 (SAM_IRQ_PIOA_PINS+4) /* PIOA, PIN 4 */
# define SAM_IRQ_PA5 (SAM_IRQ_PIOA_PINS+5) /* PIOA, PIN 5 */
# define SAM_IRQ_PA6 (SAM_IRQ_PIOA_PINS+6) /* PIOA, PIN 6 */
# define SAM_IRQ_PA7 (SAM_IRQ_PIOA_PINS+7) /* PIOA, PIN 7 */
# define SAM_IRQ_PA8 (SAM_IRQ_PIOA_PINS+8) /* PIOA, PIN 8 */
# define SAM_IRQ_PA9 (SAM_IRQ_PIOA_PINS+9) /* PIOA, PIN 9 */
# define SAM_IRQ_PA10 (SAM_IRQ_PIOA_PINS+10) /* PIOA, PIN 10 */
# define SAM_IRQ_PA11 (SAM_IRQ_PIOA_PINS+11) /* PIOA, PIN 11 */
# define SAM_IRQ_PA12 (SAM_IRQ_PIOA_PINS+12) /* PIOA, PIN 12 */
# define SAM_IRQ_PA13 (SAM_IRQ_PIOA_PINS+13) /* PIOA, PIN 13 */
# define SAM_IRQ_PA14 (SAM_IRQ_PIOA_PINS+14) /* PIOA, PIN 14 */
# define SAM_IRQ_PA15 (SAM_IRQ_PIOA_PINS+15) /* PIOA, PIN 15 */
# define SAM_IRQ_PA16 (SAM_IRQ_PIOA_PINS+16) /* PIOA, PIN 16 */
# define SAM_IRQ_PA17 (SAM_IRQ_PIOA_PINS+17) /* PIOA, PIN 17 */
# define SAM_IRQ_PA18 (SAM_IRQ_PIOA_PINS+18) /* PIOA, PIN 18 */
# define SAM_IRQ_PA19 (SAM_IRQ_PIOA_PINS+19) /* PIOA, PIN 19 */
# define SAM_IRQ_PA20 (SAM_IRQ_PIOA_PINS+20) /* PIOA, PIN 20 */
# define SAM_IRQ_PA21 (SAM_IRQ_PIOA_PINS+21) /* PIOA, PIN 21 */
# define SAM_IRQ_PA22 (SAM_IRQ_PIOA_PINS+22) /* PIOA, PIN 22 */
# define SAM_IRQ_PA23 (SAM_IRQ_PIOA_PINS+23) /* PIOA, PIN 23 */
# define SAM_IRQ_PA24 (SAM_IRQ_PIOA_PINS+24) /* PIOA, PIN 24 */
# define SAM_IRQ_PA25 (SAM_IRQ_PIOA_PINS+25) /* PIOA, PIN 25 */
# define SAM_IRQ_PA26 (SAM_IRQ_PIOA_PINS+26) /* PIOA, PIN 26 */
# define SAM_IRQ_PA27 (SAM_IRQ_PIOA_PINS+27) /* PIOA, PIN 27 */
# define SAM_IRQ_PA28 (SAM_IRQ_PIOA_PINS+28) /* PIOA, PIN 28 */
# define SAM_IRQ_PA29 (SAM_IRQ_PIOA_PINS+29) /* PIOA, PIN 29 */
# define SAM_IRQ_PA30 (SAM_IRQ_PIOA_PINS+30) /* PIOA, PIN 30 */
# define SAM_IRQ_PA31 (SAM_IRQ_PIOA_PINS+31) /* PIOA, PIN 31 */
# define SAM_NPIOAIRQS 32
#else
# define SAM_NPIOAIRQS 0
#endif
#ifdef CONFIG_SAMA5_PIOB_IRQ
# define SAM_IRQ_PIOB_PINS (SAM_IRQ_NINT + SAM_NPIOAIRQS)
# define SAM_IRQ_PB0 (SAM_IRQ_PIOB_PINS+0) /* PIOB, PIN 0 */
# define SAM_IRQ_PB1 (SAM_IRQ_PIOB_PINS+1) /* PIOB, PIN 1 */
# define SAM_IRQ_PB2 (SAM_IRQ_PIOB_PINS+2) /* PIOB, PIN 2 */
# define SAM_IRQ_PB3 (SAM_IRQ_PIOB_PINS+3) /* PIOB, PIN 3 */
# define SAM_IRQ_PB4 (SAM_IRQ_PIOB_PINS+4) /* PIOB, PIN 4 */
# define SAM_IRQ_PB5 (SAM_IRQ_PIOB_PINS+5) /* PIOB, PIN 5 */
# define SAM_IRQ_PB6 (SAM_IRQ_PIOB_PINS+6) /* PIOB, PIN 6 */
# define SAM_IRQ_PB7 (SAM_IRQ_PIOB_PINS+7) /* PIOB, PIN 7 */
# define SAM_IRQ_PB8 (SAM_IRQ_PIOB_PINS+8) /* PIOB, PIN 8 */
# define SAM_IRQ_PB9 (SAM_IRQ_PIOB_PINS+9) /* PIOB, PIN 9 */
# define SAM_IRQ_PB10 (SAM_IRQ_PIOB_PINS+10) /* PIOB, PIN 10 */
# define SAM_IRQ_PB11 (SAM_IRQ_PIOB_PINS+11) /* PIOB, PIN 11 */
# define SAM_IRQ_PB12 (SAM_IRQ_PIOB_PINS+12) /* PIOB, PIN 12 */
# define SAM_IRQ_PB13 (SAM_IRQ_PIOB_PINS+13) /* PIOB, PIN 13 */
# define SAM_IRQ_PB14 (SAM_IRQ_PIOB_PINS+14) /* PIOB, PIN 14 */
# define SAM_IRQ_PB15 (SAM_IRQ_PIOB_PINS+15) /* PIOB, PIN 15 */
# define SAM_IRQ_PB16 (SAM_IRQ_PIOB_PINS+16) /* PIOB, PIN 16 */
# define SAM_IRQ_PB17 (SAM_IRQ_PIOB_PINS+17) /* PIOB, PIN 17 */
# define SAM_IRQ_PB18 (SAM_IRQ_PIOB_PINS+18) /* PIOB, PIN 18 */
# define SAM_IRQ_PB19 (SAM_IRQ_PIOB_PINS+19) /* PIOB, PIN 19 */
# define SAM_IRQ_PB20 (SAM_IRQ_PIOB_PINS+20) /* PIOB, PIN 20 */
# define SAM_IRQ_PB21 (SAM_IRQ_PIOB_PINS+21) /* PIOB, PIN 21 */
# define SAM_IRQ_PB22 (SAM_IRQ_PIOB_PINS+22) /* PIOB, PIN 22 */
# define SAM_IRQ_PB23 (SAM_IRQ_PIOB_PINS+23) /* PIOB, PIN 23 */
# define SAM_IRQ_PB24 (SAM_IRQ_PIOB_PINS+24) /* PIOB, PIN 24 */
# define SAM_IRQ_PB25 (SAM_IRQ_PIOB_PINS+25) /* PIOB, PIN 25 */
# define SAM_IRQ_PB26 (SAM_IRQ_PIOB_PINS+26) /* PIOB, PIN 26 */
# define SAM_IRQ_PB27 (SAM_IRQ_PIOB_PINS+27) /* PIOB, PIN 27 */
# define SAM_IRQ_PB28 (SAM_IRQ_PIOB_PINS+28) /* PIOB, PIN 28 */
# define SAM_IRQ_PB29 (SAM_IRQ_PIOB_PINS+29) /* PIOB, PIN 29 */
# define SAM_IRQ_PB30 (SAM_IRQ_PIOB_PINS+30) /* PIOB, PIN 30 */
# define SAM_IRQ_PB31 (SAM_IRQ_PIOB_PINS+31) /* PIOB, PIN 31 */
# define SAM_NPIOBIRQS 32
#else
# define SAM_NPIOBIRQS 0
#endif
#ifdef CONFIG_SAMA5_PIOC_IRQ
# define SAM_IRQ_PIOC_PINS (SAM_IRQ_NINT + SAM_NPIOAIRQS + SAM_NPIOBIRQS)
# define SAM_IRQ_PC0 (SAM_IRQ_PIOC_PINS+0) /* PIOC, PIN 0 */
# define SAM_IRQ_PC1 (SAM_IRQ_PIOC_PINS+1) /* PIOC, PIN 1 */
# define SAM_IRQ_PC2 (SAM_IRQ_PIOC_PINS+2) /* PIOC, PIN 2 */
# define SAM_IRQ_PC3 (SAM_IRQ_PIOC_PINS+3) /* PIOC, PIN 3 */
# define SAM_IRQ_PC4 (SAM_IRQ_PIOC_PINS+4) /* PIOC, PIN 4 */
# define SAM_IRQ_PC5 (SAM_IRQ_PIOC_PINS+5) /* PIOC, PIN 5 */
# define SAM_IRQ_PC6 (SAM_IRQ_PIOC_PINS+6) /* PIOC, PIN 6 */
# define SAM_IRQ_PC7 (SAM_IRQ_PIOC_PINS+7) /* PIOC, PIN 7 */
# define SAM_IRQ_PC8 (SAM_IRQ_PIOC_PINS+8) /* PIOC, PIN 8 */
# define SAM_IRQ_PC9 (SAM_IRQ_PIOC_PINS+9) /* PIOC, PIN 9 */
# define SAM_IRQ_PC10 (SAM_IRQ_PIOC_PINS+10) /* PIOC, PIN 10 */
# define SAM_IRQ_PC11 (SAM_IRQ_PIOC_PINS+11) /* PIOC, PIN 11 */
# define SAM_IRQ_PC12 (SAM_IRQ_PIOC_PINS+12) /* PIOC, PIN 12 */
# define SAM_IRQ_PC13 (SAM_IRQ_PIOC_PINS+13) /* PIOC, PIN 13 */
# define SAM_IRQ_PC14 (SAM_IRQ_PIOC_PINS+14) /* PIOC, PIN 14 */
# define SAM_IRQ_PC15 (SAM_IRQ_PIOC_PINS+15) /* PIOC, PIN 15 */
# define SAM_IRQ_PC16 (SAM_IRQ_PIOC_PINS+16) /* PIOC, PIN 16 */
# define SAM_IRQ_PC17 (SAM_IRQ_PIOC_PINS+17) /* PIOC, PIN 17 */
# define SAM_IRQ_PC18 (SAM_IRQ_PIOC_PINS+18) /* PIOC, PIN 18 */
# define SAM_IRQ_PC19 (SAM_IRQ_PIOC_PINS+19) /* PIOC, PIN 19 */
# define SAM_IRQ_PC20 (SAM_IRQ_PIOC_PINS+20) /* PIOC, PIN 20 */
# define SAM_IRQ_PC21 (SAM_IRQ_PIOC_PINS+21) /* PIOC, PIN 21 */
# define SAM_IRQ_PC22 (SAM_IRQ_PIOC_PINS+22) /* PIOC, PIN 22 */
# define SAM_IRQ_PC23 (SAM_IRQ_PIOC_PINS+23) /* PIOC, PIN 23 */
# define SAM_IRQ_PC24 (SAM_IRQ_PIOC_PINS+24) /* PIOC, PIN 24 */
# define SAM_IRQ_PC25 (SAM_IRQ_PIOC_PINS+25) /* PIOC, PIN 25 */
# define SAM_IRQ_PC26 (SAM_IRQ_PIOC_PINS+26) /* PIOC, PIN 26 */
# define SAM_IRQ_PC27 (SAM_IRQ_PIOC_PINS+27) /* PIOC, PIN 27 */
# define SAM_IRQ_PC28 (SAM_IRQ_PIOC_PINS+28) /* PIOC, PIN 28 */
# define SAM_IRQ_PC29 (SAM_IRQ_PIOC_PINS+29) /* PIOC, PIN 29 */
# define SAM_IRQ_PC30 (SAM_IRQ_PIOC_PINS+30) /* PIOC, PIN 30 */
# define SAM_IRQ_PC31 (SAM_IRQ_PIOC_PINS+31) /* PIOC, PIN 31 */
# define SAM_NPIOCIRQS 32
#else
# define SAM_NPIOCIRQS 0
#endif
#ifdef CONFIG_SAMA5_PIOD_IRQ
# define SAM_IRQ_PIOD_PINS (SAM_IRQ_NINT + SAM_NPIOAIRQS + SAM_NPIOBIRQS + \
SAM_NPIOCIRQS)
# define SAM_IRQ_PD0 (SAM_IRQ_PIOD_PINS+0) /* PIOD, PIN 0 */
# define SAM_IRQ_PD1 (SAM_IRQ_PIOD_PINS+1) /* PIOD, PIN 1 */
# define SAM_IRQ_PD2 (SAM_IRQ_PIOD_PINS+2) /* PIOD, PIN 2 */
# define SAM_IRQ_PD3 (SAM_IRQ_PIOD_PINS+3) /* PIOD, PIN 3 */
# define SAM_IRQ_PD4 (SAM_IRQ_PIOD_PINS+4) /* PIOD, PIN 4 */
# define SAM_IRQ_PD5 (SAM_IRQ_PIOD_PINS+5) /* PIOD, PIN 5 */
# define SAM_IRQ_PD6 (SAM_IRQ_PIOD_PINS+6) /* PIOD, PIN 6 */
# define SAM_IRQ_PD7 (SAM_IRQ_PIOD_PINS+7) /* PIOD, PIN 7 */
# define SAM_IRQ_PD8 (SAM_IRQ_PIOD_PINS+8) /* PIOD, PIN 8 */
# define SAM_IRQ_PD9 (SAM_IRQ_PIOD_PINS+9) /* PIOD, PIN 9 */
# define SAM_IRQ_PD10 (SAM_IRQ_PIOD_PINS+10) /* PIOD, PIN 10 */
# define SAM_IRQ_PD11 (SAM_IRQ_PIOD_PINS+11) /* PIOD, PIN 11 */
# define SAM_IRQ_PD12 (SAM_IRQ_PIOD_PINS+12) /* PIOD, PIN 12 */
# define SAM_IRQ_PD13 (SAM_IRQ_PIOD_PINS+13) /* PIOD, PIN 13 */
# define SAM_IRQ_PD14 (SAM_IRQ_PIOD_PINS+14) /* PIOD, PIN 14 */
# define SAM_IRQ_PD15 (SAM_IRQ_PIOD_PINS+15) /* PIOD, PIN 15 */
# define SAM_IRQ_PD16 (SAM_IRQ_PIOD_PINS+16) /* PIOD, PIN 16 */
# define SAM_IRQ_PD17 (SAM_IRQ_PIOD_PINS+17) /* PIOD, PIN 17 */
# define SAM_IRQ_PD18 (SAM_IRQ_PIOD_PINS+18) /* PIOD, PIN 18 */
# define SAM_IRQ_PD19 (SAM_IRQ_PIOD_PINS+19) /* PIOD, PIN 19 */
# define SAM_IRQ_PD20 (SAM_IRQ_PIOD_PINS+20) /* PIOD, PIN 20 */
# define SAM_IRQ_PD21 (SAM_IRQ_PIOD_PINS+21) /* PIOD, PIN 21 */
# define SAM_IRQ_PD22 (SAM_IRQ_PIOD_PINS+22) /* PIOD, PIN 22 */
# define SAM_IRQ_PD23 (SAM_IRQ_PIOD_PINS+23) /* PIOD, PIN 23 */
# define SAM_IRQ_PD24 (SAM_IRQ_PIOD_PINS+24) /* PIOD, PIN 24 */
# define SAM_IRQ_PD25 (SAM_IRQ_PIOD_PINS+25) /* PIOD, PIN 25 */
# define SAM_IRQ_PD26 (SAM_IRQ_PIOD_PINS+26) /* PIOD, PIN 26 */
# define SAM_IRQ_PD27 (SAM_IRQ_PIOD_PINS+27) /* PIOD, PIN 27 */
# define SAM_IRQ_PD28 (SAM_IRQ_PIOD_PINS+28) /* PIOD, PIN 28 */
# define SAM_IRQ_PD29 (SAM_IRQ_PIOD_PINS+29) /* PIOD, PIN 29 */
# define SAM_IRQ_PD30 (SAM_IRQ_PIOD_PINS+30) /* PIOD, PIN 30 */
# define SAM_IRQ_PD31 (SAM_IRQ_PIOD_PINS+31) /* PIOD, PIN 31 */
# define SAM_NPIODIRQS 32
#else
# define SAM_NPIODIRQS 0
#endif
#ifdef CONFIG_SAMA5_PIOE_IRQ
# define SAM_IRQ_PIOE_PINS (SAM_IRQ_NINT + SAM_NPIOAIRQS + \
SAM_NPIOBIRQS + SAM_NPIOCIRQS + SAM_NPIODIRQS)
# define SAM_IRQ_PE0 (SAM_IRQ_PIOE_PINS+0) /* PIOE, PIN 0 */
# define SAM_IRQ_PE1 (SAM_IRQ_PIOE_PINS+1) /* PIOE, PIN 1 */
# define SAM_IRQ_PE2 (SAM_IRQ_PIOE_PINS+2) /* PIOE, PIN 2 */
# define SAM_IRQ_PE3 (SAM_IRQ_PIOE_PINS+3) /* PIOE, PIN 3 */
# define SAM_IRQ_PE4 (SAM_IRQ_PIOE_PINS+4) /* PIOE, PIN 4 */
# define SAM_IRQ_PE5 (SAM_IRQ_PIOE_PINS+5) /* PIOE, PIN 5 */
# define SAM_IRQ_PE6 (SAM_IRQ_PIOE_PINS+6) /* PIOE, PIN 6 */
# define SAM_IRQ_PE7 (SAM_IRQ_PIOE_PINS+7) /* PIOE, PIN 7 */
# define SAM_IRQ_PE8 (SAM_IRQ_PIOE_PINS+8) /* PIOE, PIN 8 */
# define SAM_IRQ_PE9 (SAM_IRQ_PIOE_PINS+9) /* PIOE, PIN 9 */
# define SAM_IRQ_PE10 (SAM_IRQ_PIOE_PINS+10) /* PIOE, PIN 10 */
# define SAM_IRQ_PE11 (SAM_IRQ_PIOE_PINS+11) /* PIOE, PIN 11 */
# define SAM_IRQ_PE12 (SAM_IRQ_PIOE_PINS+12) /* PIOE, PIN 12 */
# define SAM_IRQ_PE13 (SAM_IRQ_PIOE_PINS+13) /* PIOE, PIN 13 */
# define SAM_IRQ_PE14 (SAM_IRQ_PIOE_PINS+14) /* PIOE, PIN 14 */
# define SAM_IRQ_PE15 (SAM_IRQ_PIOE_PINS+15) /* PIOE, PIN 15 */
# define SAM_IRQ_PE16 (SAM_IRQ_PIOE_PINS+16) /* PIOE, PIN 16 */
# define SAM_IRQ_PE17 (SAM_IRQ_PIOE_PINS+17) /* PIOE, PIN 17 */
# define SAM_IRQ_PE18 (SAM_IRQ_PIOE_PINS+18) /* PIOE, PIN 18 */
# define SAM_IRQ_PE19 (SAM_IRQ_PIOE_PINS+19) /* PIOE, PIN 19 */
# define SAM_IRQ_PE20 (SAM_IRQ_PIOE_PINS+20) /* PIOE, PIN 20 */
# define SAM_IRQ_PE21 (SAM_IRQ_PIOE_PINS+21) /* PIOE, PIN 21 */
# define SAM_IRQ_PE22 (SAM_IRQ_PIOE_PINS+22) /* PIOE, PIN 22 */
# define SAM_IRQ_PE23 (SAM_IRQ_PIOE_PINS+23) /* PIOE, PIN 23 */
# define SAM_IRQ_PE24 (SAM_IRQ_PIOE_PINS+24) /* PIOE, PIN 24 */
# define SAM_IRQ_PE25 (SAM_IRQ_PIOE_PINS+25) /* PIOE, PIN 25 */
# define SAM_IRQ_PE26 (SAM_IRQ_PIOE_PINS+26) /* PIOE, PIN 26 */
# define SAM_IRQ_PE27 (SAM_IRQ_PIOE_PINS+27) /* PIOE, PIN 27 */
# define SAM_IRQ_PE28 (SAM_IRQ_PIOE_PINS+28) /* PIOE, PIN 28 */
# define SAM_IRQ_PE29 (SAM_IRQ_PIOE_PINS+29) /* PIOE, PIN 29 */
# define SAM_IRQ_PE30 (SAM_IRQ_PIOE_PINS+30) /* PIOE, PIN 30 */
# define SAM_IRQ_PE31 (SAM_IRQ_PIOE_PINS+31) /* PIOE, PIN 31 */
# define SAM_NPIOEIRQS 32
#else
# define SAM_NPIOEIRQS 0
#endif
/* Total number of IRQ numbers */
#define NR_IRQS (SAM_IRQ_NINT + \
SAM_NPIOAIRQS + SAM_NPIOBIRQS + SAM_NPIOCIRQS + \
SAM_NPIODIRQS + SAM_NPIOEIRQS )
/****************************************************************************************
* Public Types
****************************************************************************************/
/****************************************************************************************
* Inline functions
****************************************************************************************/
/****************************************************************************************
* Public Variables
****************************************************************************************/
/****************************************************************************************
* Public Function Prototypes
****************************************************************************************/
#ifndef __ASSEMBLY__
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif
#endif /* __ARCH_ARM_INCLUDE_SAMA5_SAMA5D3_IRQ_H */

439
arch/arm/include/sama5/sama5d4_irq.h
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@ -1,439 +0,0 @@
/****************************************************************************************
* arch/arm/include/sama5/sama5d4x_irq.h
*
* Copyright (C) 2014 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************************/
/* This file should never be included directed but, rather, only indirectly through
* nuttx/irq.h
*/
#ifndef __ARCH_ARM_INCLUDE_SAMA5_SAMA5D4X_IRQ_H
#define __ARCH_ARM_INCLUDE_SAMA5_SAMA5D4X_IRQ_H
/****************************************************************************************
* Included Files
****************************************************************************************/
/****************************************************************************************
* Pre-processor Definitions
****************************************************************************************/
/* SAMA5D3 Peripheral Identifiers */
#define SAM_PID_FIQ (0) /* Advanced Interrupt Controller FIQ */
#define SAM_PID_SYS (1) /* System Controller Interrupt PMC */
#define SAM_PID_ARM (2) /* Performance Monitor Unit */
#define SAM_PID_PIT (3) /* Periodic Interval Timer Interrupt */
#define SAM_PID_WDT (4) /* Watchdog timer Interrupt */
#define SAM_PID_PIOD (5) /* Parallel I/O Controller D */
#define SAM_PID_USART0 (6) /* USART 0 */
#define SAM_PID_USART1 (7) /* USART 1 */
#define SAM_PID_XDMAC0 (8) /* DMA Controller 0 */
#define SAM_PID_ICM (9) /* Integrity Check Monitor */
#define SAM_PID_CPKCC (10) /* Classic Public Key Crypto Controller */
/* 11 Undefined */
#define SAM_PID_AES (12) /* Advanced Encryption Standard */
#define SAM_PID_AESB (13) /* AES bridge */
#define SAM_PID_TDES (14) /* Triple Data Encryption Standard */
#define SAM_PID_SHA (15) /* Secure Hash Algorithm */
#define SAM_PID_MPDDRC (16) /* MPDDR controller */
#define SAM_PID_MATRIX1 (17) /* H32MX, 32-bit AHB Matrix */
#define SAM_PID_MATRIX0 (18) /* H64MX, 64-bit AHB Matrix */
#define SAM_PID_VDEC (19) /* Video Decoder */
#define SAM_PID_SBM (20) /* Secure Box Module */
/* 21 Undefined */
#define SAM_PID_HSMC (22) /* Multi-bit ECC Interrupt */
#define SAM_PID_PIOA (23) /* Parallel I/O Controller A */
#define SAM_PID_PIOB (24) /* Parallel I/O Controller B */
#define SAM_PID_PIOC (25) /* Parallel I/O Controller C */
#define SAM_PID_PIOE (26) /* Parallel I/O Controller E */
#define SAM_PID_UART0 (27) /* UART 0 */
#define SAM_PID_UART1 (28) /* UART 1 */
#define SAM_PID_USART2 (29) /* USART 2 */
#define SAM_PID_USART3 (30) /* USART 3 */
#define SAM_PID_USART4 (31) /* USART 4 */
#define SAM_PID_TWI0 (32) /* Two-Wire Interface 0 */
#define SAM_PID_TWI1 (33) /* Two-Wire Interface 1 */
#define SAM_PID_TWI2 (34) /* Two-Wire Interface 2 */
#define SAM_PID_HSMCI0 (35) /* High Speed Multimedia Card Interface 0 */
#define SAM_PID_HSMCI1 (36) /* High Speed Multimedia Card Interface 1 */
#define SAM_PID_SPI0 (37) /* Serial Peripheral Interface 0 */
#define SAM_PID_SPI1 (38) /* Serial Peripheral Interface 1 */
#define SAM_PID_SPI2 (39) /* Serial Peripheral Interface 2 */
#define SAM_PID_TC0 (40) /* Timer Counter 0 (ch. 0, 1, 2) */
#define SAM_PID_TC1 (41) /* Timer Counter 1 (ch. 3, 4, 5) */
#define SAM_PID_TC2 (42) /* Timer Counter 2 (ch. 6, 7, 8) */
#define SAM_PID_PWM (43) /* Pulse Width Modulation Controller */
#define SAM_PID_ADC (44) /* Touch Screen ADC Controller */
#define SAM_PID_DBGU (45) /* Debug Unit Interrupt */
#define SAM_PID_UHPHS (46) /* USB Host High Speed */
#define SAM_PID_UDPHS (47) /* USB Device High Speed */
#define SAM_PID_SSC0 (48) /* Synchronous Serial Controller 0 */
#define SAM_PID_SSC1 (49) /* Synchronous Serial Controller 1 */
#define SAM_PID_XDMAC1 (50) /* DMA Controller 1 */
#define SAM_PID_LCDC (51) /* LCD Controller */
#define SAM_PID_ISI (52) /* Image Sensor Interface */
#define SAM_PID_TRNG (53) /* True Random Number Generator */
#define SAM_PID_EMAC0 (54) /* Ethernet MAC 0 */
#define SAM_PID_EMAC1 (55) /* Ethernet MAC 1 */
#define SAM_PID_AICID (56) /* IRQ Interrupt ID */
#define SAM_PID_SFC (57) /* Fuse Controller */
/* 58 Reserved */
#define SAM_PID_SECURAM (59) /* Secured RAM */
/* 60 Undefined */
#define SAM_PID_SMD (61) /* SMD Soft Modem */
#define SAM_PID_TWI3 (62) /* Two-Wire Interface 3 */
#define SAM_PID_CATB (63) /* Capacitive Touch Module */
#define SAM_PID_SFR (64) /* Special Function Register */
#define SAM_PID_AIC (65) /* Advanced Interrupt Controller */
#define SAM_PID_SAIC (66) /* Secured Advanced Interrupt Controller */
#define SAM_PID_L2CC (67) /* L2 Cache Controller */
/* External interrupts vectors numbers (same as peripheral ID) */
#define SAM_IRQ_FIQ SAM_PID_FIQ /* Advanced Interrupt Controller FIQ */
#define SAM_IRQ_SYS SAM_PID_SYS /* System Controller Interrupt PMC */
#define SAM_IRQ_ARM SAM_PID_ARM /* Performance Monitor Unit */
#define SAM_IRQ_PIT SAM_PID_PIT /* Periodic Interval Timer Interrupt */
#define SAM_IRQ_WDT SAM_PID_WDT /* Watchdog timer Interrupt */
#define SAM_IRQ_PIOD SAM_PID_PIOD /* Parallel I/O Controller D */
#define SAM_IRQ_USART0 SAM_PID_USART0 /* USART 0 */
#define SAM_IRQ_USART1 SAM_PID_USART1 /* USART 1 */
#define SAM_IRQ_XDMAC0 SAM_PID_XDMAC0 /* DMA Controller 0 */
#define SAM_IRQ_ICM SAM_PID_ICM /* Integrity Check Monitor */
#define SAM_IRQ_CPKCC SAM_PID_CPKCC /* Classic Public Key Crypto Controller */
#define SAM_IRQ_AES SAM_PID_AES /* Advanced Encryption Standard */
#define SAM_IRQ_AESB SAM_PID_AESB /* AES bridge */
#define SAM_IRQ_TDES SAM_PID_TDES /* Triple Data Encryption Standard */
#define SAM_IRQ_SHA SAM_PID_SHA /* Secure Hash Algorithm */
#define SAM_IRQ_MPDDRC SAM_PID_MPDDRC /* MPDDR controller */
#define SAM_IRQ_MATRIX1 SAM_PID_MATRIX1 /* H32MX, 32-bit AHB Matrix */
#define SAM_IRQ_MATRIX0 SAM_PID_MATRIX0 /* H64MX, 64-bit AHB Matrix */
#define SAM_IRQ_VDEC SAM_PID_VDEC /* Video Decoder */
#define SAM_IRQ_SBM SAM_PID_SBM /* Secure Box Module */
#define SAM_IRQ_HSMC SAM_PID_HSMC /* Multi-bit ECC Interrupt */
#define SAM_IRQ_PIOA SAM_PID_PIOA /* Parallel I/O Controller A */
#define SAM_IRQ_PIOB SAM_PID_PIOB /* Parallel I/O Controller B */
#define SAM_IRQ_PIOC SAM_PID_PIOC /* Parallel I/O Controller C */
#define SAM_IRQ_PIOE SAM_PID_PIOE /* Parallel I/O Controller E */
#define SAM_IRQ_UART0 SAM_PID_UART0 /* UART 0 */
#define SAM_IRQ_UART1 SAM_PID_UART1 /* UART 1 */
#define SAM_IRQ_USART2 SAM_PID_USART2 /* USART 2 */
#define SAM_IRQ_USART3 SAM_PID_USART3 /* USART 3 */
#define SAM_IRQ_USART4 SAM_PID_USART4 /* USART 4 */
#define SAM_IRQ_TWI0 SAM_PID_TWI0 /* Two-Wire Interface 0 */
#define SAM_IRQ_TWI1 SAM_PID_TWI1 /* Two-Wire Interface 1 */
#define SAM_IRQ_TWI2 SAM_PID_TWI2 /* Two-Wire Interface 2 */
#define SAM_IRQ_HSMCI0 SAM_PID_HSMCI0 /* High Speed Multimedia Card Interface 0 */
#define SAM_IRQ_HSMCI1 SAM_PID_HSMCI1 /* High Speed Multimedia Card Interface 1 */
#define SAM_IRQ_SPI0 SAM_PID_SPI0 /* Serial Peripheral Interface 0 */
#define SAM_IRQ_SPI1 SAM_PID_SPI1 /* Serial Peripheral Interface 1 */
#define SAM_IRQ_SPI2 SAM_PID_SPI2 /* Serial Peripheral Interface 2 */
#define SAM_IRQ_TC0 SAM_PID_TC0 /* Timer Counter 0 (ch. 0, 1, 2) */
#define SAM_IRQ_TC1 SAM_PID_TC1 /* Timer Counter 1 (ch. 3, 4, 5) */
#define SAM_IRQ_TC2 SAM_PID_TC2 /* Timer Counter 2 (ch. 6, 7, 8) */
#define SAM_IRQ_PWM SAM_PID_PWM /* Pulse Width Modulation Controller */
#define SAM_IRQ_ADC SAM_PID_ADC /* Touch Screen ADC Controller */
#define SAM_IRQ_DBGU SAM_PID_DBGU /* Debug Unit Interrupt */
#define SAM_IRQ_UHPHS SAM_PID_UHPHS /* USB Host High Speed */
#define SAM_IRQ_UDPHS SAM_PID_UDPHS /* USB Device High Speed */
#define SAM_IRQ_SSC0 SAM_PID_SSC0 /* Synchronous Serial Controller 0 */
#define SAM_IRQ_SSC1 SAM_PID_SSC1 /* Synchronous Serial Controller 1 */
#define SAM_IRQ_XDMAC1 SAM_PID_XDMAC1 /* DMA Controller 1 */
#define SAM_IRQ_LCDC SAM_PID_LCDC /* LCD Controller */
#define SAM_IRQ_ISI SAM_PID_ISI /* Image Sensor Interface */
#define SAM_IRQ_TRNG SAM_PID_TRNG /* True Random Number Generator */
#define SAM_IRQ_EMAC0 SAM_PID_EMAC0 /* Ethernet MAC 0 */
#define SAM_IRQ_EMAC1 SAM_PID_EMAC1 /* Ethernet MAC 1 */
#define SAM_IRQ_AICID SAM_PID_AICID /* IRQ Interrupt ID */
#define SAM_IRQ_SFC SAM_PID_SFC /* Fuse Controller */
#define SAM_IRQ_SECURAM SAM_PID_SECURAM /* Secured RAM */
#define SAM_IRQ_SMD SAM_PID_SMD /* SMD Soft Modem */
#define SAM_IRQ_TWI3 SAM_PID_TWI3 /* Two-Wire Interface 3 */
#define SAM_IRQ_CATB SAM_PID_CATB /* Capacitive Touch Module */
#define SAM_IRQ_SFR SAM_PID_SFR /* Special Function Register */
#define SAM_IRQ_AIC SAM_PID_AIC /* Advanced Interrupt Controller */
#define SAM_IRQ_SAIC SAM_PID_SAIC /* Secured Advanced Interrupt Controller */
#define SAM_IRQ_L2CC SAM_PID_L2CC /* L2 Cache Controller */
#define SAM_IRQ_NINT (SAM_PID_L2CC + 1)
/* PIO interrupts (derived from SAM_IRQ_PIOA/B/C/D/E/F) */
#ifdef CONFIG_SAMA5_PIOA_IRQ
# define SAM_IRQ_PIOA_PINS (SAM_IRQ_NINT)
# define SAM_IRQ_PA0 (SAM_IRQ_PIOA_PINS+0) /* PIOA, PIN 0 */
# define SAM_IRQ_PA1 (SAM_IRQ_PIOA_PINS+1) /* PIOA, PIN 1 */
# define SAM_IRQ_PA2 (SAM_IRQ_PIOA_PINS+2) /* PIOA, PIN 2 */
# define SAM_IRQ_PA3 (SAM_IRQ_PIOA_PINS+3) /* PIOA, PIN 3 */
# define SAM_IRQ_PA4 (SAM_IRQ_PIOA_PINS+4) /* PIOA, PIN 4 */
# define SAM_IRQ_PA5 (SAM_IRQ_PIOA_PINS+5) /* PIOA, PIN 5 */
# define SAM_IRQ_PA6 (SAM_IRQ_PIOA_PINS+6) /* PIOA, PIN 6 */
# define SAM_IRQ_PA7 (SAM_IRQ_PIOA_PINS+7) /* PIOA, PIN 7 */
# define SAM_IRQ_PA8 (SAM_IRQ_PIOA_PINS+8) /* PIOA, PIN 8 */
# define SAM_IRQ_PA9 (SAM_IRQ_PIOA_PINS+9) /* PIOA, PIN 9 */
# define SAM_IRQ_PA10 (SAM_IRQ_PIOA_PINS+10) /* PIOA, PIN 10 */
# define SAM_IRQ_PA11 (SAM_IRQ_PIOA_PINS+11) /* PIOA, PIN 11 */
# define SAM_IRQ_PA12 (SAM_IRQ_PIOA_PINS+12) /* PIOA, PIN 12 */
# define SAM_IRQ_PA13 (SAM_IRQ_PIOA_PINS+13) /* PIOA, PIN 13 */
# define SAM_IRQ_PA14 (SAM_IRQ_PIOA_PINS+14) /* PIOA, PIN 14 */
# define SAM_IRQ_PA15 (SAM_IRQ_PIOA_PINS+15) /* PIOA, PIN 15 */
# define SAM_IRQ_PA16 (SAM_IRQ_PIOA_PINS+16) /* PIOA, PIN 16 */
# define SAM_IRQ_PA17 (SAM_IRQ_PIOA_PINS+17) /* PIOA, PIN 17 */
# define SAM_IRQ_PA18 (SAM_IRQ_PIOA_PINS+18) /* PIOA, PIN 18 */
# define SAM_IRQ_PA19 (SAM_IRQ_PIOA_PINS+19) /* PIOA, PIN 19 */
# define SAM_IRQ_PA20 (SAM_IRQ_PIOA_PINS+20) /* PIOA, PIN 20 */
# define SAM_IRQ_PA21 (SAM_IRQ_PIOA_PINS+21) /* PIOA, PIN 21 */
# define SAM_IRQ_PA22 (SAM_IRQ_PIOA_PINS+22) /* PIOA, PIN 22 */
# define SAM_IRQ_PA23 (SAM_IRQ_PIOA_PINS+23) /* PIOA, PIN 23 */
# define SAM_IRQ_PA24 (SAM_IRQ_PIOA_PINS+24) /* PIOA, PIN 24 */
# define SAM_IRQ_PA25 (SAM_IRQ_PIOA_PINS+25) /* PIOA, PIN 25 */
# define SAM_IRQ_PA26 (SAM_IRQ_PIOA_PINS+26) /* PIOA, PIN 26 */
# define SAM_IRQ_PA27 (SAM_IRQ_PIOA_PINS+27) /* PIOA, PIN 27 */
# define SAM_IRQ_PA28 (SAM_IRQ_PIOA_PINS+28) /* PIOA, PIN 28 */
# define SAM_IRQ_PA29 (SAM_IRQ_PIOA_PINS+29) /* PIOA, PIN 29 */
# define SAM_IRQ_PA30 (SAM_IRQ_PIOA_PINS+30) /* PIOA, PIN 30 */
# define SAM_IRQ_PA31 (SAM_IRQ_PIOA_PINS+31) /* PIOA, PIN 31 */
# define SAM_NPIOAIRQS 32
#else
# define SAM_NPIOAIRQS 0
#endif
#ifdef CONFIG_SAMA5_PIOB_IRQ
# define SAM_IRQ_PIOB_PINS (SAM_IRQ_NINT + SAM_NPIOAIRQS)
# define SAM_IRQ_PB0 (SAM_IRQ_PIOB_PINS+0) /* PIOB, PIN 0 */
# define SAM_IRQ_PB1 (SAM_IRQ_PIOB_PINS+1) /* PIOB, PIN 1 */
# define SAM_IRQ_PB2 (SAM_IRQ_PIOB_PINS+2) /* PIOB, PIN 2 */
# define SAM_IRQ_PB3 (SAM_IRQ_PIOB_PINS+3) /* PIOB, PIN 3 */
# define SAM_IRQ_PB4 (SAM_IRQ_PIOB_PINS+4) /* PIOB, PIN 4 */
# define SAM_IRQ_PB5 (SAM_IRQ_PIOB_PINS+5) /* PIOB, PIN 5 */
# define SAM_IRQ_PB6 (SAM_IRQ_PIOB_PINS+6) /* PIOB, PIN 6 */
# define SAM_IRQ_PB7 (SAM_IRQ_PIOB_PINS+7) /* PIOB, PIN 7 */
# define SAM_IRQ_PB8 (SAM_IRQ_PIOB_PINS+8) /* PIOB, PIN 8 */
# define SAM_IRQ_PB9 (SAM_IRQ_PIOB_PINS+9) /* PIOB, PIN 9 */
# define SAM_IRQ_PB10 (SAM_IRQ_PIOB_PINS+10) /* PIOB, PIN 10 */
# define SAM_IRQ_PB11 (SAM_IRQ_PIOB_PINS+11) /* PIOB, PIN 11 */
# define SAM_IRQ_PB12 (SAM_IRQ_PIOB_PINS+12) /* PIOB, PIN 12 */
# define SAM_IRQ_PB13 (SAM_IRQ_PIOB_PINS+13) /* PIOB, PIN 13 */
# define SAM_IRQ_PB14 (SAM_IRQ_PIOB_PINS+14) /* PIOB, PIN 14 */
# define SAM_IRQ_PB15 (SAM_IRQ_PIOB_PINS+15) /* PIOB, PIN 15 */
# define SAM_IRQ_PB16 (SAM_IRQ_PIOB_PINS+16) /* PIOB, PIN 16 */
# define SAM_IRQ_PB17 (SAM_IRQ_PIOB_PINS+17) /* PIOB, PIN 17 */
# define SAM_IRQ_PB18 (SAM_IRQ_PIOB_PINS+18) /* PIOB, PIN 18 */
# define SAM_IRQ_PB19 (SAM_IRQ_PIOB_PINS+19) /* PIOB, PIN 19 */
# define SAM_IRQ_PB20 (SAM_IRQ_PIOB_PINS+20) /* PIOB, PIN 20 */
# define SAM_IRQ_PB21 (SAM_IRQ_PIOB_PINS+21) /* PIOB, PIN 21 */
# define SAM_IRQ_PB22 (SAM_IRQ_PIOB_PINS+22) /* PIOB, PIN 22 */
# define SAM_IRQ_PB23 (SAM_IRQ_PIOB_PINS+23) /* PIOB, PIN 23 */
# define SAM_IRQ_PB24 (SAM_IRQ_PIOB_PINS+24) /* PIOB, PIN 24 */
# define SAM_IRQ_PB25 (SAM_IRQ_PIOB_PINS+25) /* PIOB, PIN 25 */
# define SAM_IRQ_PB26 (SAM_IRQ_PIOB_PINS+26) /* PIOB, PIN 26 */
# define SAM_IRQ_PB27 (SAM_IRQ_PIOB_PINS+27) /* PIOB, PIN 27 */
# define SAM_IRQ_PB28 (SAM_IRQ_PIOB_PINS+28) /* PIOB, PIN 28 */
# define SAM_IRQ_PB29 (SAM_IRQ_PIOB_PINS+29) /* PIOB, PIN 29 */
# define SAM_IRQ_PB30 (SAM_IRQ_PIOB_PINS+30) /* PIOB, PIN 30 */
# define SAM_IRQ_PB31 (SAM_IRQ_PIOB_PINS+31) /* PIOB, PIN 31 */
# define SAM_NPIOBIRQS 32
#else
# define SAM_NPIOBIRQS 0
#endif
#ifdef CONFIG_SAMA5_PIOC_IRQ
# define SAM_IRQ_PIOC_PINS (SAM_IRQ_NINT + SAM_NPIOAIRQS + SAM_NPIOBIRQS)
# define SAM_IRQ_PC0 (SAM_IRQ_PIOC_PINS+0) /* PIOC, PIN 0 */
# define SAM_IRQ_PC1 (SAM_IRQ_PIOC_PINS+1) /* PIOC, PIN 1 */
# define SAM_IRQ_PC2 (SAM_IRQ_PIOC_PINS+2) /* PIOC, PIN 2 */
# define SAM_IRQ_PC3 (SAM_IRQ_PIOC_PINS+3) /* PIOC, PIN 3 */
# define SAM_IRQ_PC4 (SAM_IRQ_PIOC_PINS+4) /* PIOC, PIN 4 */
# define SAM_IRQ_PC5 (SAM_IRQ_PIOC_PINS+5) /* PIOC, PIN 5 */
# define SAM_IRQ_PC6 (SAM_IRQ_PIOC_PINS+6) /* PIOC, PIN 6 */
# define SAM_IRQ_PC7 (SAM_IRQ_PIOC_PINS+7) /* PIOC, PIN 7 */
# define SAM_IRQ_PC8 (SAM_IRQ_PIOC_PINS+8) /* PIOC, PIN 8 */
# define SAM_IRQ_PC9 (SAM_IRQ_PIOC_PINS+9) /* PIOC, PIN 9 */
# define SAM_IRQ_PC10 (SAM_IRQ_PIOC_PINS+10) /* PIOC, PIN 10 */
# define SAM_IRQ_PC11 (SAM_IRQ_PIOC_PINS+11) /* PIOC, PIN 11 */
# define SAM_IRQ_PC12 (SAM_IRQ_PIOC_PINS+12) /* PIOC, PIN 12 */
# define SAM_IRQ_PC13 (SAM_IRQ_PIOC_PINS+13) /* PIOC, PIN 13 */
# define SAM_IRQ_PC14 (SAM_IRQ_PIOC_PINS+14) /* PIOC, PIN 14 */
# define SAM_IRQ_PC15 (SAM_IRQ_PIOC_PINS+15) /* PIOC, PIN 15 */
# define SAM_IRQ_PC16 (SAM_IRQ_PIOC_PINS+16) /* PIOC, PIN 16 */
# define SAM_IRQ_PC17 (SAM_IRQ_PIOC_PINS+17) /* PIOC, PIN 17 */
# define SAM_IRQ_PC18 (SAM_IRQ_PIOC_PINS+18) /* PIOC, PIN 18 */
# define SAM_IRQ_PC19 (SAM_IRQ_PIOC_PINS+19) /* PIOC, PIN 19 */
# define SAM_IRQ_PC20 (SAM_IRQ_PIOC_PINS+20) /* PIOC, PIN 20 */
# define SAM_IRQ_PC21 (SAM_IRQ_PIOC_PINS+21) /* PIOC, PIN 21 */
# define SAM_IRQ_PC22 (SAM_IRQ_PIOC_PINS+22) /* PIOC, PIN 22 */
# define SAM_IRQ_PC23 (SAM_IRQ_PIOC_PINS+23) /* PIOC, PIN 23 */
# define SAM_IRQ_PC24 (SAM_IRQ_PIOC_PINS+24) /* PIOC, PIN 24 */
# define SAM_IRQ_PC25 (SAM_IRQ_PIOC_PINS+25) /* PIOC, PIN 25 */
# define SAM_IRQ_PC26 (SAM_IRQ_PIOC_PINS+26) /* PIOC, PIN 26 */
# define SAM_IRQ_PC27 (SAM_IRQ_PIOC_PINS+27) /* PIOC, PIN 27 */
# define SAM_IRQ_PC28 (SAM_IRQ_PIOC_PINS+28) /* PIOC, PIN 28 */
# define SAM_IRQ_PC29 (SAM_IRQ_PIOC_PINS+29) /* PIOC, PIN 29 */
# define SAM_IRQ_PC30 (SAM_IRQ_PIOC_PINS+30) /* PIOC, PIN 30 */
# define SAM_IRQ_PC31 (SAM_IRQ_PIOC_PINS+31) /* PIOC, PIN 31 */
# define SAM_NPIOCIRQS 32
#else
# define SAM_NPIOCIRQS 0
#endif
#ifdef CONFIG_SAMA5_PIOD_IRQ
# define SAM_IRQ_PIOD_PINS (SAM_IRQ_NINT + SAM_NPIOAIRQS + SAM_NPIOBIRQS + \
SAM_NPIOCIRQS)
# define SAM_IRQ_PD0 (SAM_IRQ_PIOD_PINS+0) /* PIOD, PIN 0 */
# define SAM_IRQ_PD1 (SAM_IRQ_PIOD_PINS+1) /* PIOD, PIN 1 */
# define SAM_IRQ_PD2 (SAM_IRQ_PIOD_PINS+2) /* PIOD, PIN 2 */
# define SAM_IRQ_PD3 (SAM_IRQ_PIOD_PINS+3) /* PIOD, PIN 3 */
# define SAM_IRQ_PD4 (SAM_IRQ_PIOD_PINS+4) /* PIOD, PIN 4 */
# define SAM_IRQ_PD5 (SAM_IRQ_PIOD_PINS+5) /* PIOD, PIN 5 */
# define SAM_IRQ_PD6 (SAM_IRQ_PIOD_PINS+6) /* PIOD, PIN 6 */
# define SAM_IRQ_PD7 (SAM_IRQ_PIOD_PINS+7) /* PIOD, PIN 7 */
# define SAM_IRQ_PD8 (SAM_IRQ_PIOD_PINS+8) /* PIOD, PIN 8 */
# define SAM_IRQ_PD9 (SAM_IRQ_PIOD_PINS+9) /* PIOD, PIN 9 */
# define SAM_IRQ_PD10 (SAM_IRQ_PIOD_PINS+10) /* PIOD, PIN 10 */
# define SAM_IRQ_PD11 (SAM_IRQ_PIOD_PINS+11) /* PIOD, PIN 11 */
# define SAM_IRQ_PD12 (SAM_IRQ_PIOD_PINS+12) /* PIOD, PIN 12 */
# define SAM_IRQ_PD13 (SAM_IRQ_PIOD_PINS+13) /* PIOD, PIN 13 */
# define SAM_IRQ_PD14 (SAM_IRQ_PIOD_PINS+14) /* PIOD, PIN 14 */
# define SAM_IRQ_PD15 (SAM_IRQ_PIOD_PINS+15) /* PIOD, PIN 15 */
# define SAM_IRQ_PD16 (SAM_IRQ_PIOD_PINS+16) /* PIOD, PIN 16 */
# define SAM_IRQ_PD17 (SAM_IRQ_PIOD_PINS+17) /* PIOD, PIN 17 */
# define SAM_IRQ_PD18 (SAM_IRQ_PIOD_PINS+18) /* PIOD, PIN 18 */
# define SAM_IRQ_PD19 (SAM_IRQ_PIOD_PINS+19) /* PIOD, PIN 19 */
# define SAM_IRQ_PD20 (SAM_IRQ_PIOD_PINS+20) /* PIOD, PIN 20 */
# define SAM_IRQ_PD21 (SAM_IRQ_PIOD_PINS+21) /* PIOD, PIN 21 */
# define SAM_IRQ_PD22 (SAM_IRQ_PIOD_PINS+22) /* PIOD, PIN 22 */
# define SAM_IRQ_PD23 (SAM_IRQ_PIOD_PINS+23) /* PIOD, PIN 23 */
# define SAM_IRQ_PD24 (SAM_IRQ_PIOD_PINS+24) /* PIOD, PIN 24 */
# define SAM_IRQ_PD25 (SAM_IRQ_PIOD_PINS+25) /* PIOD, PIN 25 */
# define SAM_IRQ_PD26 (SAM_IRQ_PIOD_PINS+26) /* PIOD, PIN 26 */
# define SAM_IRQ_PD27 (SAM_IRQ_PIOD_PINS+27) /* PIOD, PIN 27 */
# define SAM_IRQ_PD28 (SAM_IRQ_PIOD_PINS+28) /* PIOD, PIN 28 */
# define SAM_IRQ_PD29 (SAM_IRQ_PIOD_PINS+29) /* PIOD, PIN 29 */
# define SAM_IRQ_PD30 (SAM_IRQ_PIOD_PINS+30) /* PIOD, PIN 30 */
# define SAM_IRQ_PD31 (SAM_IRQ_PIOD_PINS+31) /* PIOD, PIN 31 */
# define SAM_NPIODIRQS 32
#else
# define SAM_NPIODIRQS 0
#endif
#ifdef CONFIG_SAMA5_PIOE_IRQ
# define SAM_IRQ_PIOE_PINS (SAM_IRQ_NINT + SAM_NPIOAIRQS + \
SAM_NPIOBIRQS + SAM_NPIOCIRQS + SAM_NPIODIRQS)
# define SAM_IRQ_PE0 (SAM_IRQ_PIOE_PINS+0) /* PIOE, PIN 0 */
# define SAM_IRQ_PE1 (SAM_IRQ_PIOE_PINS+1) /* PIOE, PIN 1 */
# define SAM_IRQ_PE2 (SAM_IRQ_PIOE_PINS+2) /* PIOE, PIN 2 */
# define SAM_IRQ_PE3 (SAM_IRQ_PIOE_PINS+3) /* PIOE, PIN 3 */
# define SAM_IRQ_PE4 (SAM_IRQ_PIOE_PINS+4) /* PIOE, PIN 4 */
# define SAM_IRQ_PE5 (SAM_IRQ_PIOE_PINS+5) /* PIOE, PIN 5 */
# define SAM_IRQ_PE6 (SAM_IRQ_PIOE_PINS+6) /* PIOE, PIN 6 */
# define SAM_IRQ_PE7 (SAM_IRQ_PIOE_PINS+7) /* PIOE, PIN 7 */
# define SAM_IRQ_PE8 (SAM_IRQ_PIOE_PINS+8) /* PIOE, PIN 8 */
# define SAM_IRQ_PE9 (SAM_IRQ_PIOE_PINS+9) /* PIOE, PIN 9 */
# define SAM_IRQ_PE10 (SAM_IRQ_PIOE_PINS+10) /* PIOE, PIN 10 */
# define SAM_IRQ_PE11 (SAM_IRQ_PIOE_PINS+11) /* PIOE, PIN 11 */
# define SAM_IRQ_PE12 (SAM_IRQ_PIOE_PINS+12) /* PIOE, PIN 12 */
# define SAM_IRQ_PE13 (SAM_IRQ_PIOE_PINS+13) /* PIOE, PIN 13 */
# define SAM_IRQ_PE14 (SAM_IRQ_PIOE_PINS+14) /* PIOE, PIN 14 */
# define SAM_IRQ_PE15 (SAM_IRQ_PIOE_PINS+15) /* PIOE, PIN 15 */
# define SAM_IRQ_PE16 (SAM_IRQ_PIOE_PINS+16) /* PIOE, PIN 16 */
# define SAM_IRQ_PE17 (SAM_IRQ_PIOE_PINS+17) /* PIOE, PIN 17 */
# define SAM_IRQ_PE18 (SAM_IRQ_PIOE_PINS+18) /* PIOE, PIN 18 */
# define SAM_IRQ_PE19 (SAM_IRQ_PIOE_PINS+19) /* PIOE, PIN 19 */
# define SAM_IRQ_PE20 (SAM_IRQ_PIOE_PINS+20) /* PIOE, PIN 20 */
# define SAM_IRQ_PE21 (SAM_IRQ_PIOE_PINS+21) /* PIOE, PIN 21 */
# define SAM_IRQ_PE22 (SAM_IRQ_PIOE_PINS+22) /* PIOE, PIN 22 */
# define SAM_IRQ_PE23 (SAM_IRQ_PIOE_PINS+23) /* PIOE, PIN 23 */
# define SAM_IRQ_PE24 (SAM_IRQ_PIOE_PINS+24) /* PIOE, PIN 24 */
# define SAM_IRQ_PE25 (SAM_IRQ_PIOE_PINS+25) /* PIOE, PIN 25 */
# define SAM_IRQ_PE26 (SAM_IRQ_PIOE_PINS+26) /* PIOE, PIN 26 */
# define SAM_IRQ_PE27 (SAM_IRQ_PIOE_PINS+27) /* PIOE, PIN 27 */
# define SAM_IRQ_PE28 (SAM_IRQ_PIOE_PINS+28) /* PIOE, PIN 28 */
# define SAM_IRQ_PE29 (SAM_IRQ_PIOE_PINS+29) /* PIOE, PIN 29 */
# define SAM_IRQ_PE30 (SAM_IRQ_PIOE_PINS+30) /* PIOE, PIN 30 */
# define SAM_IRQ_PE31 (SAM_IRQ_PIOE_PINS+31) /* PIOE, PIN 31 */
# define SAM_NPIOEIRQS 32
#else
# define SAM_NPIOEIRQS 0
#endif
/* Total number of IRQ numbers */
#define NR_IRQS (SAM_IRQ_NINT + \
SAM_NPIOAIRQS + SAM_NPIOBIRQS + SAM_NPIOCIRQS + \
SAM_NPIODIRQS + SAM_NPIOEIRQS )
/****************************************************************************************
* Public Types
****************************************************************************************/
/****************************************************************************************
* Inline functions
****************************************************************************************/
/****************************************************************************************
* Public Variables
****************************************************************************************/
/****************************************************************************************
* Public Function Prototypes
****************************************************************************************/
#ifndef __ASSEMBLY__
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif
#endif /* __ARCH_ARM_INCLUDE_SAMA5_SAMA5D4X_IRQ_H */

993
arch/arm/include/samdl/chip.h
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@ -1,993 +0,0 @@
/************************************************************************************
* arch/arm/include/samdl/chip.h
*
* Copyright (C) 2014-2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_INCLUDE_SAMDL_CHIP_H
#define __ARCH_ARM_INCLUDE_SAMDL_CHIP_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Get customizations for each supported chip */
/* SAMD20 Family ********************************************************************/
/* FEATURE SAM D20J SAM D20G SAM D20E
* ------------------- ------------------ ------------------ --------
* No. of pins 64 48 32
* Flash 256/128/64/32/16KB 256/128/64/32/16KB 256/128/64/32/16KB
* SRAM 32/16/8/4/2KB 32/16/8/4/2KB 32/16/8/4/2KB
* Max. Freq. 48MHz 48MHz 48MHz
* Event channels 8 8 8
* Timer/counters 8 6 6
* TC output channels 2 2 2
* SERCOM 6 6 4
* ADC channels 20 14 10
* Comparators 2 2 2
* DAC channels 1 1 1
* RTC Yes Yes Yes
* RTC alarms 1 1 1
* RTC compare 1 32-bit/2 16-bit 1 32-bit/2 16-bit 1 32-bit/2 16-bit
* External interrupts 16 16 16
* PTC X an Y 16x16 12x10 10x6
* Packages QFN/TQFP QFN/TQFP QFN/TQFP
* Oscillators XOSC32, XOSC, OSC32K, OSCULP32K, OSC8M, and DFLL48M
* SW Debug interface Yes Yes Yes
* Watchdog timer Yes Yes Yes
*/
#if defined(CONFIG_ARCH_CHIP_SAMD20E14)
# define SAMD20 1 /* SAMD20 family */
# define SAMD20E 1 /* SAMD20E */
# undef SAMD20G
# undef SAMD20J
/* Internal memory */
# define SAMDL_FLASH_SIZE (16*1024) /* 16KB */
# define SAMDL_SRAM0_SIZE (2*1024) /* 2KB */
# define SAMDL_LPRAM_SIZE (0*1024) /* None */
#elif defined(CONFIG_ARCH_CHIP_SAMD20E15)
# define SAMD20 1 /* SAMD20 family */
# define SAMD20E 1 /* SAMD20E */
# undef SAMD20G
# undef SAMD20J
/* Internal memory */
# define SAMDL_FLASH_SIZE (32*1024) /* 32KB */
# define SAMDL_SRAM0_SIZE (4*1024) /* 4KB */
# define SAMDL_LPRAM_SIZE (0*1024) /* None */
#elif defined(CONFIG_ARCH_CHIP_SAMD20E16)
# define SAMD20 1 /* SAMD20 family */
# define SAMD20E 1 /* SAMD20E */
# undef SAMD20G
# undef SAMD20J
/* Internal memory */
# define SAMDL_FLASH_SIZE (64*1024) /* 64KB */
# define SAMDL_SRAM0_SIZE (8*1024) /* 8KB */
# define SAMDL_LPRAM_SIZE (0*1024) /* None */
#elif defined(CONFIG_ARCH_CHIP_SAMD20E17)
# define SAMD20 1 /* SAMD20 family */
# define SAMD20E 1 /* SAMD20E */
# undef SAMD20G
# undef SAMD20J
/* Internal memory */
# define SAMDL_FLASH_SIZE (128*1024) /* 128KB */
# define SAMDL_SRAM0_SIZE (16*1024) /* 16KB */
# define SAMDL_LPRAM_SIZE (0*1024) /* None */
#elif defined(CONFIG_ARCH_CHIP_SAMD20E18)
# define SAMD20 1 /* SAMD20 family */
# define SAMD20E 1 /* SAMD20E */
# undef SAMD20G
# undef SAMD20J
/* Internal memory */
# define SAMDL_FLASH_SIZE (256*1024) /* 256KB */
# define SAMDL_SRAM0_SIZE (32*1024) /* 32KB */
# define SAMDL_LPRAM_SIZE (0*1024) /* None */
#elif defined(CONFIG_ARCH_CHIP_SAMD20G14)
# define SAMD20 1 /* SAMD20 family */
# undef SAMD20E
# define SAMD20G 1 /* SAMD20G */
# undef SAMD20J
/* Internal memory */
# define SAMDL_FLASH_SIZE (16*1024) /* 16KB */
# define SAMDL_SRAM0_SIZE (2*1024) /* 2KB */
# define SAMDL_LPRAM_SIZE (0*1024) /* None */
#elif defined(CONFIG_ARCH_CHIP_SAMD20G15)
# define SAMD20 1 /* SAMD20 family */
# undef SAMD20E
# define SAMD20G 1 /* SAMD20G */
# undef SAMD20J
/* Internal memory */
# define SAMDL_FLASH_SIZE (32*1024) /* 32KB */
# define SAMDL_SRAM0_SIZE (4*1024) /* 4KB */
# define SAMDL_LPRAM_SIZE (0*1024) /* None */
#elif defined(CONFIG_ARCH_CHIP_SAMD20G16)
# define SAMD20 1 /* SAMD20 family */
# undef SAMD20E
# define SAMD20G 1 /* SAMD20G */
# undef SAMD20J
/* Internal memory */
# define SAMDL_FLASH_SIZE (64*1024) /* 64KB */
# define SAMDL_SRAM0_SIZE (8*1024) /* 8KB */
# define SAMDL_LPRAM_SIZE (0*1024) /* None */
#elif defined(CONFIG_ARCH_CHIP_SAMD20G17)
# define SAMD20 1 /* SAMD20 family */
# undef SAMD20E
# define SAMD20G 1 /* SAMD20G */
# undef SAMD20J
/* Internal memory */
# define SAMDL_FLASH_SIZE (128*1024) /* 128KB */
# define SAMDL_SRAM0_SIZE (16*1024) /* 16KB */
# define SAMDL_LPRAM_SIZE (0*1024) /* None */
#elif defined(CONFIG_ARCH_CHIP_SAMD20G18)
# define SAMD20 1 /* SAMD20 family */
# undef SAMD20E
# define SAMD20G 1 /* SAMD20G */
# undef SAMD20J
/* Internal memory */
# define SAMDL_FLASH_SIZE (256*1024) /* 256KB */
# define SAMDL_SRAM0_SIZE (32*1024) /* 32KB */
# define SAMDL_LPRAM_SIZE (0*1024) /* None */
#elif defined(CONFIG_ARCH_CHIP_SAMD20J14)
# define SAMD20 1 /* SAMD20 family */
# undef SAMD20E
# undef SAMD20G
# define SAMD20J 1 /* SAMD20J */
/* Internal memory */
# define SAMDL_FLASH_SIZE (16*1024) /* 16KB */
# define SAMDL_SRAM0_SIZE (2*1024) /* 2KB */
# define SAMDL_LPRAM_SIZE (0*1024) /* None */
#elif defined(CONFIG_ARCH_CHIP_SAMD20J15)
# define SAMD20 1 /* SAMD20 family */
# undef SAMD20E
# undef SAMD20G
# define SAMD20J 1 /* SAMD20J */
/* Internal memory */
# define SAMDL_FLASH_SIZE (32*1024) /* 32KB */
# define SAMDL_SRAM0_SIZE (4*1024) /* 4KB */
# define SAMDL_LPRAM_SIZE (0*1024) /* None */
#elif defined(CONFIG_ARCH_CHIP_SAMD20J16)
# define SAMD20 1 /* SAMD20 family */
# undef SAMD20E
# undef SAMD20G
# define SAMD20J 1 /* SAMD20J */
/* Internal memory */
# define SAMDL_FLASH_SIZE (64*1024) /* 64KB */
# define SAMDL_SRAM0_SIZE (8*1024) /* 8KB */
# define SAMDL_LPRAM_SIZE (0*1024) /* None */
#elif defined(CONFIG_ARCH_CHIP_SAMD20J17)
# define SAMD20 1 /* SAMD20 family */
# undef SAMD20E
# undef SAMD20G
# define SAMD20J 1 /* SAMD20J */
/* Internal memory */
# define SAMDL_FLASH_SIZE (128*1024) /* 128KB */
# define SAMDL_SRAM0_SIZE (16*1024) /* 16KB */
# define SAMDL_LPRAM_SIZE (0*1024) /* None */
#elif defined(CONFIG_ARCH_CHIP_SAMD20J18)
# define SAMD20 1 /* SAMD20 family */
# undef SAMD20E
# undef SAMD20G
# define SAMD20J 1 /* SAMD20J */
/* Internal memory */
# define SAMDL_FLASH_SIZE (256*1024) /* 256KB */
# define SAMDL_SRAM0_SIZE (32*1024) /* 32KB */
# define SAMDL_LPRAM_SIZE (0*1024) /* None */
#else
# undef SAMD20 /* Not SAMD20 family */
# undef SAMD20E
# undef SAMD20G
# undef SAMD20J
#endif
/* SAMD20 Peripherals */
#if defined(SAMD20E)
# define SAMDL_NEVENTS 8 /* 8 event channels */
# define SAMDL_NTC 6 /* 6 Timer/counters */
# define SAMDL_NTCOUT 2 /* 2 TC output channels */
# define SAMDL_NTCC 0 /* No TC control channels */
# define SAMDL_NTCCOUT 0 /* No TCC output channels */
# define SAMDL_NDMACHAN 0 /* No DMA channels */
# define SAMDL_NUSBIF 0 /* No USB interface */
# define SAMDL_NAES 0 /* No AES engine */
# define SAMDL_NCCL 0 /* No Counfigurable Custom Logic */
# define SAMDL_NTRNG 0 /* No True random number generator */
# define SAMDL_NSERCOM 4 /* 4 SERCOM */
# define SAMDL_NI2S 0 /* No I2S */
# define SAMDL_NADC 10 /* 10 ADC channels */
# define SAMDL_NCMP 2 /* 2 Comparators */
# define SAMDL_NDAC 1 /* 1 DAC channel */
# define SAMCL_NOPAMP 0 /* No OpAmps */
# define SAMDL_RTC 1 /* Have RTC */
# define SAMDL_NALARMS 1 /* 1 RTC alarm */
# define SAMDL_NRTCMP 1 /* RTC compare: 1 32-bit/2 16-bit */
# define SAMDL_NEXTINT 16 /* 16 External interrupts */
# define SAMDL_NPTCX 10 /* PTC X */
# define SAMDL_NPTCY 6 /* PTC Y */
# define SAMDL_WDT 1 /* Have watchdog timer */
#elif defined(SAMD20G)
# define SAMDL_NEVENTS 8 /* 8 event channels */
# define SAMDL_NTC 6 /* 6 Timer/counters */
# define SAMDL_NTCOUT 2 /* 2 TC output channels */
# define SAMDL_NTCC 0 /* No TC control channels */
# define SAMDL_NTCCOUT 0 /* No TCC output channels */
# define SAMDL_NDMACHAN 0 /* No DMA channels */
# define SAMDL_NUSBIF 0 /* No USB interface */
# define SAMDL_NAES 0 /* No AES engine */
# define SAMDL_NCCL 0 /* No Counfigurable Custom Logic */
# define SAMDL_NTRNG 0 /* No True random number generator */
# define SAMDL_NSERCOM 6 /* 6 SERCOM */
# define SAMDL_NI2S 0 /* No I2S */
# define SAMDL_NADC 15 /* 14 ADC channels */
# define SAMDL_NCMP 2 /* 2 Comparators */
# define SAMDL_NDAC 1 /* 1 DAC channel */
# define SAMCL_NOPAMP 0 /* No OpAmps */
# define SAMDL_RTC 1 /* Have RTC */
# define SAMDL_NALARMS 1 /* 1 RTC alarm */
# define SAMDL_NRTCMP 1 /* RTC compare: 1 32-bit/2 16-bit */
# define SAMDL_NEXTINT 16 /* 16 External interrupts */
# define SAMDL_NPTCX 12 /* PTC X */
# define SAMDL_NPTCY 10 /* PTC Y */
# define SAMDL_WDT 1 /* Have watchdog timer */
#elif defined(SAMD20J)
# define SAMDL_NEVENTS 8 /* 8 event channels */
# define SAMDL_NTC 8 /* 8 Timer/counters */
# define SAMDL_NTCOUT 2 /* 2 TC output channels */
# define SAMDL_NTCC 0 /* No TC control channels */
# define SAMDL_NTCCOUT 0 /* No TCC output channels */
# define SAMDL_NDMACHAN 0 /* No DMA channels */
# define SAMDL_NUSBIF 0 /* No USB interface */
# define SAMDL_NAES 0 /* No AES engine */
# define SAMDL_NCCL 0 /* No Counfigurable Custom Logic */
# define SAMDL_NTRNG 0 /* No True random number generator */
# define SAMDL_NSERCOM 6 /* 6 SERCOM */
# define SAMDL_NI2S 0 /* No I2S */
# define SAMDL_NADC 20 /* 20 ADC channels */
# define SAMDL_NCMP 2 /* 2 Comparators */
# define SAMDL_NDAC 1 /* 1 DAC channel */
# define SAMCL_NOPAMP 0 /* No OpAmps */
# define SAMDL_RTC 1 /* Have RTC */
# define SAMDL_NALARMS 1 /* 1 RTC alarm */
# define SAMDL_NRTCMP 1 /* RTC compare: 1 32-bit/2 16-bit */
# define SAMDL_NEXTINT 16 /* 16 External interrupts */
# define SAMDL_NPTCX 16 /* PTC X */
# define SAMDL_NPTCY 16 /* PTC Y */
# define SAMDL_WDT 1 /* Have watchdog timer */
#endif
/* SAMD21 Family ********************************************************************/
/* FEATURE SAM D21J SAM D21G SAM D21E
* ------------------- ------------------ ------------------ --------
* No. of pins 64 48 32
* Flash 256/128/64/32/16KB 256/128/64/32KB 256/128/64/32KB
* SRAM 32/16/8/4/2KB 32/16/8/4/2KB 32/16/8/4KB
* Max. Freq. 48MHz 48MHz 48MHz
* Event channels 12 12 12
* Timer/counters 5 3 3
* TC output channels 2 2 2
* T/C Control 3 3 3
* TCC output channels 2 2 2
* TCC waveform output 8/4/2 8/4/2 6/4/2
* DMA channels 12 12 12
* USB interface 1 1 1
* SERCOM 6 6 4
* I2S 1 1 1
* ADC channels 20 14 10
* Comparators 2 2 2
* DAC channels 1 1 1
* RTC Yes Yes Yes
* RTC alarms 1 1 1
* RTC compare 1 32-bit/2 16-bit 1 32-bit/2 16-bit 1 32-bit/2 16-bit
* External interrupts 16 16 16
* PTC X an Y 16x16 12x10 10x6
* Packages QFN/TQFP QFN/TQFP/WLCSP QFN/TQFP/UFBGA
* Oscillators XOSC32, XOSC, OSC32K, OSCULP32K, OSC8M, DFLL48M, and FDPLL96M
* SW Debug interface Yes Yes Yes
* Watchdog timer Yes Yes Yes
*/
#if defined(CONFIG_ARCH_CHIP_SAMD21E15A) || defined(CONFIG_ARCH_CHIP_SAMD21E15B)
# define SAMD21 1 /* SAMD21 family */
# define SAMD21E 1 /* SAMD21E */
# undef SAMD21G
# undef SAMD21J
/* Internal memory */
# define SAMDL_FLASH_SIZE (32*1024) /* 32KB */
# define SAMDL_SRAM0_SIZE (4*1024) /* 4KB */
# define SAMDL_LPRAM_SIZE (0*1024) /* None */
# if defined(CONFIG_ARCH_CHIP_SAMD21E15A)
# define SAMDL_FLASHRWW_SIZE (0*1024) /* None */
# else
# define SAMDL_FLASHRWW_SIZE (1*1024) /* 1KB */
# endif
#elif defined(CONFIG_ARCH_CHIP_SAMD21E16A) || defined(CONFIG_ARCH_CHIP_SAMD21E16B)
# define SAMD21 1 /* SAMD21 family */
# define SAMD21E 1 /* SAMD21E */
# undef SAMD21G
# undef SAMD21J
/* Internal memory */
# define SAMDL_FLASH_SIZE (64*1024) /* 64KB */
# define SAMDL_SRAM0_SIZE (8*1024) /* 8KB */
# define SAMDL_LPRAM_SIZE (0*1024) /* None */
# if defined(CONFIG_ARCH_CHIP_SAMD21E16A)
# define SAMDL_FLASHRWW_SIZE (0*1024) /* None */
# else
# define SAMDL_FLASHRWW_SIZE (2*1024) /* 2KB */
# endif
#elif defined(CONFIG_ARCH_CHIP_SAMD21E17A)
# define SAMD21 1 /* SAMD21 family */
# define SAMD21E 1 /* SAMD21E */
# undef SAMD21G
# undef SAMD21J
/* Internal memory */
# define SAMDL_FLASH_SIZE (128*1024) /* 128KB */
# define SAMDL_FLASHRWW_SIZE (0*1024) /* None */
# define SAMDL_SRAM0_SIZE (16*1024) /* 16KB */
# define SAMDL_LPRAM_SIZE (0*1024) /* None */
#elif defined(CONFIG_ARCH_CHIP_SAMD21E18A)
# define SAMD21 1 /* SAMD21 family */
# define SAMD21E 1 /* SAMD21E */
# undef SAMD21G
# undef SAMD21J
/* Internal memory */
# define SAMDL_FLASH_SIZE (256*1024) /* 256KB */
# define SAMDL_FLASHRWW_SIZE (0*1024) /* None */
# define SAMDL_SRAM0_SIZE (32*1024) /* 32KB */
# define SAMDL_LPRAM_SIZE (0*1024) /* None */
#elif defined(CONFIG_ARCH_CHIP_SAMD21G15A) || defined(CONFIG_ARCH_CHIP_SAMD21G15B)
# define SAMD21 1 /* SAMD21 family */
# undef SAMD21E
# define SAMD21G 1 /* SAMD21G */
# undef SAMD21J
/* Internal memory */
# define SAMDL_FLASH_SIZE (32*1024) /* 32KB */
# define SAMDL_SRAM0_SIZE (4*1024) /* 4KB */
# define SAMDL_LPRAM_SIZE (0*1024) /* None */
# if defined(CONFIG_ARCH_CHIP_SAMD21G15A)
# define SAMDL_FLASHRWW_SIZE (0*1024) /* None */
# else
# define SAMDL_FLASHRWW_SIZE (1*1024) /* 1KB */
# endif
#elif defined(CONFIG_ARCH_CHIP_SAMD21G16A) || defined(CONFIG_ARCH_CHIP_SAMD21G16B)
# define SAMD21 1 /* SAMD21 family */
# undef SAMD21E
# define SAMD21G 1 /* SAMD21G */
# undef SAMD21J
/* Internal memory */
# define SAMDL_FLASH_SIZE (64*1024) /* 64KB */
# define SAMDL_SRAM0_SIZE (8*1024) /* 8KB */
# define SAMDL_LPRAM_SIZE (0*1024) /* None */
# if defined(CONFIG_ARCH_CHIP_SAMD21G16A)
# define SAMDL_FLASHRWW_SIZE (0*1024) /* None */
# else
# define SAMDL_FLASHRWW_SIZE (2*1024) /* 2KB */
# endif
#elif defined(CONFIG_ARCH_CHIP_SAMD21G17A)
# define SAMD21 1 /* SAMD21 family */
# undef SAMD21E
# define SAMD21G 1 /* SAMD21G */
# undef SAMD21J
/* Internal memory */
# define SAMDL_FLASH_SIZE (128*1024) /* 128KB */
# define SAMDL_FLASHRWW_SIZE (0*1024) /* None */
# define SAMDL_SRAM0_SIZE (16*1024) /* 16KB */
# define SAMDL_LPRAM_SIZE (0*1024) /* None */
#elif defined(CONFIG_ARCH_CHIP_SAMD21G18A)
# define SAMD21 1 /* SAMD21 family */
# undef SAMD21E
# define SAMD21G 1 /* SAMD21G */
# undef SAMD21J
/* Internal memory */
# define SAMDL_FLASH_SIZE (256*1024) /* 256KB */
# define SAMDL_FLASHRWW_SIZE (0*1024) /* None */
# define SAMDL_SRAM0_SIZE (32*1024) /* 32KB */
# define SAMDL_LPRAM_SIZE (0*1024) /* None */
#elif defined(CONFIG_ARCH_CHIP_SAMD21J15A) || defined(CONFIG_ARCH_CHIP_SAMD21J15B)
# define SAMD21 1 /* SAMD21 family */
# undef SAMD21E
# undef SAMD21G
# define SAMD21J 1 /* SAMD21J */
/* Internal memory */
# define SAMDL_FLASH_SIZE (32*1024) /* 32KB */
# define SAMDL_SRAM0_SIZE (4*1024) /* 4KB */
# define SAMDL_LPRAM_SIZE (0*1024) /* None */
# if defined(CONFIG_ARCH_CHIP_SAMD21J15A)
# define SAMDL_FLASHRWW_SIZE (0*1024) /* None */
# else
# define SAMDL_FLASHRWW_SIZE (1*1024) /* 1KB */
# endif
#elif defined(CONFIG_ARCH_CHIP_SAMD21J16A) || defined(CONFIG_ARCH_CHIP_SAMD21J16B)
# define SAMD21 1 /* SAMD21 family */
# undef SAMD21E
# undef SAMD21G
# define SAMD21J 1 /* SAMD21J */
/* Internal memory */
# define SAMDL_FLASH_SIZE (64*1024) /* 64KB */
# define SAMDL_SRAM0_SIZE (8*1024) /* 8KB */
# define SAMDL_LPRAM_SIZE (0*1024) /* None */
# if defined(CONFIG_ARCH_CHIP_SAMD21J16A)
# define SAMDL_FLASHRWW_SIZE (0*1024) /* None */
# else
# define SAMDL_FLASHRWW_SIZE (2*1024) /* 2KB */
# endif
#elif defined(CONFIG_ARCH_CHIP_SAMD21J17A)
# define SAMD21 1 /* SAMD21 family */
# undef SAMD21E
# undef SAMD21G
# define SAMD21J 1 /* SAMD21J */
/* Internal memory */
# define SAMDL_FLASH_SIZE (128*1024) /* 128KB */
# define SAMDL_FLASHRWW_SIZE (0*1024) /* None */
# define SAMDL_SRAM0_SIZE (16*1024) /* 16KB */
# define SAMDL_LPRAM_SIZE (0*1024) /* None */
#elif defined(CONFIG_ARCH_CHIP_SAMD21J18A)
# define SAMD21 1 /* SAMD21 family */
# undef SAMD21E
# undef SAMD21G
# define SAMD21J 1 /* SAMD21J */
/* Internal memory */
# define SAMDL_FLASH_SIZE (256*1024) /* 256KB */
# define SAMDL_FLASHRWW_SIZE (0*1024) /* None */
# define SAMDL_SRAM0_SIZE (32*1024) /* 32KB */
# define SAMDL_LPRAM_SIZE (0*1024) /* None */
#else
# undef SAMD21 /* Not SAMD21 family */
# undef SAMD21E
# undef SAMD21G
# undef SAMD21J
#endif
#if defined(SAMD21E)
# define SAMDL_NEVENTS 12 /* 12 event channels */
# define SAMDL_NTC 3 /* 3 Timer/counters */
# define SAMDL_NTCOUT 2 /* 2 TC output channels */
# define SAMDL_NTCC 3 /* 3 TC control channels */
# define SAMDL_NTCCOUT 2 /* 2 TCC output channels */
# define SAMDL_TCC_NWAVEFORMS 8 /* Each TCC has a different number of outputs */
# define SAMDL_NDMACHAN 12 /* 12 DMA channels */
# define SAMDL_NUSBIF 1 /* 1 USB interface */
# define SAMDL_NAES 1 /* 1 AES engine */
# define SAMDL_NCCL 4 /* 4 Counfigurable Custom Logic */
# define SAMDL_NTRNG 1 /* 1 True random number generator */
# define SAMDL_NSERCOM 4 /* 4 SERCOM */
# define SAMDL_NI2S 1 /* 1 I2S */
# define SAMDL_NADC 10 /* 10 ADC channels */
# define SAMDL_NCMP 2 /* 2 Comparators */
# define SAMDL_NDAC 1 /* 1 DAC channel */
# define SAMCL_NOPAMP 3 /* 3 OpAmps */
# define SAMDL_RTC 1 /* Have RTC */
# define SAMDL_NALARMS 1 /* 1 RTC alarm */
# define SAMDL_NRTCMP 1 /* RTC compare: 1 32-bit/2 16-bit */
# define SAMDL_NEXTINT 16 /* 16 External interrupts */
# define SAMDL_NPTCX 10 /* 10x6 */
# define SAMDL_NPTCY 6 /* 10x6*/
# define SAMDL_WDT 1 /* Have watchdog timer */
#elif defined(SAMD21G)
# define SAMDL_NEVENTS 12 /* 12 event channels */
# define SAMDL_NTC 3 /* 3 Timer/counters */
# define SAMDL_NTCOUT 2 /* 2 TC output channels */
# define SAMDL_NTCC 3 /* 3 TC control channels */
# define SAMDL_NTCCOUT 2 /* 2 TCC output channels */
# define SAMDL_TCC_NWAVEFORMS 8 /* Each TCC has a different number of outputs */
# define SAMDL_NDMACHAN 12 /* 12 DMA channels */
# define SAMDL_NUSBIF 1 /* 1 USB interface */
# define SAMDL_NAES 1 /* 1 AES engine */
# define SAMDL_NCCL 4 /* 4 Counfigurable Custom Logic */
# define SAMDL_NTRNG 1 /* 1 True random number generator */
# define SAMDL_NSERCOM 6 /* 6 SERCOM */
# define SAMDL_NI2S 1 /* 1 I2S */
# define SAMDL_NADC 14 /* 14 ADC channels */
# define SAMDL_NCMP 2 /* 2 Comparators */
# define SAMDL_NDAC 1 /* 1 DAC channel */
# define SAMCL_NOPAMP 3 /* 3 OpAmps */
# define SAMDL_RTC 1 /* Have RTC */
# define SAMDL_NALARMS 1 /* 1 RTC alarm */
# define SAMDL_NRTCMP 1 /* RTC compare: 1 32-bit/2 16-bit */
# define SAMDL_NEXTINT 16 /* 16 External interrupts */
# define SAMDL_NPTCX 12 /* 12x10 */
# define SAMDL_NPTCY 10 /* 12x10 */
# define SAMDL_WDT 1 /* Have watchdog timer */
#elif defined(SAMD21J)
# define SAMDL_NEVENTS 12 /* 12 event channels */
# define SAMDL_NTC 5 /* 5 Timer/counters */
# define SAMDL_NTCOUT 2 /* 2 TC output channels */
# define SAMDL_NTCC 3 /* 3 TC control channels */
# define SAMDL_NTCCOUT 2 /* 2 TCC output channels */
# define SAMDL_TCC_NWAVEFORMS 8 /* Each TCC has a different number of outputs */
# define SAMDL_NDMACHAN 12 /* 12 DMA channels */
# define SAMDL_NUSBIF 1 /* 1 USB interface */
# define SAMDL_NAES 1 /* 1 AES engine */
# define SAMDL_NCCL 4 /* 4 Counfigurable Custom Logic */
# define SAMDL_NTRNG 1 /* 1 True random number generator */
# define SAMDL_NSERCOM 6 /* 6 SERCOM */
# define SAMDL_NI2S 1 /* 1 I2S */
# define SAMDL_NADC 20 /* 20 ADC channels */
# define SAMDL_NCMP 2 /* 2 Comparators */
# define SAMDL_NDAC 1 /* 1 DAC channel */
# define SAMCL_NOPAMP 3 /* 3 OpAmps */
# define SAMDL_RTC 1 /* Have RTC */
# define SAMDL_NALARMS 1 /* 1 RTC alarm */
# define SAMDL_NRTCMP 1 /* RTC compare: 1 32-bit/2 16-bit */
# define SAMDL_NEXTINT 16 /* 16 External interrupts */
# define SAMDL_NPTCX 16 /* 16x16 */
# define SAMDL_NPTCY 16 /* 16x16*/
# define SAMDL_WDT 1 /* Have watchdog timer */
#endif
/* SAML21 Family ********************************************************************/
/* FEATURE SAM L21J SAM L21G SAM L21E
* ------------------- ------------------ ------------------ --------
* No. of pins 64 48 32
* Flash 256/128/64KB 256/128/64KB 256/128/64/32KB
* Flash RWW 8/4/2KB 8/4/2KB 8/4/2/1KB
* SRAM 32/16/8KB 32/16/8KB 32/16/8/4KB
* Max. Freq. 48MHz 48MHz 48MHz
* Event channels 12 12 12
* Timer/counters 5 3 3
* TC output channels 2 2 2
* T/C Control 3 3 3
* TCC output channels 2 2 2
* TCC waveform output 8/4/2 8/4/2 6/4/2
* DMA channels 16 16 16
* USB interface 1 1 1
* AES engine 1 1 1
* CCLs 4 4 4
* TRNG 1 1 1
* SERCOM 6 6 4
* ADC channels 20 14 10
* Comparators 2 2 2
* DAC channels 2 2 2
* OPAMP 3 3 3
* RTC Yes Yes Yes
* RTC alarms 1 1 1
* RTC compare 1 32-bit/2 16-bit 1 32-bit/2 16-bit 1 32-bit/2 16-bit
* External interrupts 16 16 16
* PTC X an Y 12x16 8x12 6x10
* 16x12 12x8 10x6
* Packages QFN/TQFP QFN/TQFP QFN/TQFP
* Oscillators XOSC32, XOSC, OSC32K, OSCULP32K, OSC16M, DFLL48M, and FDPLL96M
* SW Debug interface Yes Yes Yes
* Watchdog timer Yes Yes Yes
*/
#if defined(CONFIG_ARCH_CHIP_SAML21E15)
# define SAML21 1 /* SAML21 family */
# define SAML21E 1 /* SAML21E */
# undef SAML21G
# undef SAML21J
/* Internal memory */
# define SAMDL_FLASH_SIZE (32*1024) /* 32KB */
# define SAMDL_FLASHRWW_SIZE (1*1024) /* 1KB */
# define SAMDL_SRAM0_SIZE (4*1024) /* 4KB */
# define SAMDL_LPRAM_SIZE (2*1024) /* 2KB */
/* TCC waveform outputs */
# define SAMDL_TCC_NWAVEFORMS 2 /* 2 TCC waveform outputs */
#elif defined(CONFIG_ARCH_CHIP_SAML21E16)
# define SAML21 1 /* SAML21 family */
# define SAML21E 1 /* SAML21E */
# undef SAML21G
# undef SAML21J
/* Internal memory */
# define SAMDL_FLASH_SIZE (64*1024) /* 64KB */
# define SAMDL_FLASHRWW_SIZE (2*1024) /* 2KB */
# define SAMDL_SRAM0_SIZE (8*1024) /* 8KB */
# define SAMDL_LPRAM_SIZE (4*1024) /* 4KB */
/* TCC waveform outputs */
# define SAMDL_TCC_NWAVEFORMS 2 /* 2 TCC waveform outputs */
#elif defined(CONFIG_ARCH_CHIP_SAML21E17)
# define SAML21 1 /* SAML21 family */
# define SAML21E 1 /* SAML21E */
# undef SAML21G
# undef SAML21J
/* Internal memory */
# define SAMDL_FLASH_SIZE (128*1024) /* 128KB */
# define SAMDL_FLASHRWW_SIZE (4*1024) /* 4KB */
# define SAMDL_SRAM0_SIZE (16*1024) /* 16KB */
# define SAMDL_LPRAM_SIZE (8*1024) /* 8KB */
/* TCC waveform outputs */
# define SAMDL_TCC_NWAVEFORMS 4 /* 4 TCC waveform outputs */
#elif defined(CONFIG_ARCH_CHIP_SAML21E18)
# define SAML21 1 /* SAML21 family */
# define SAML21E 1 /* SAML21E */
# undef SAML21G
# undef SAML21J
/* Internal memory */
# define SAMDL_FLASH_SIZE (256*1024) /* 256KB */
# define SAMDL_FLASHRWW_SIZE (8*1024) /* 8KB */
# define SAMDL_SRAM0_SIZE (32*1024) /* 32KB */
# define SAMDL_LPRAM_SIZE (8*1024) /* 8KB */
/* TCC waveform outputs */
# define SAMDL_TCC_NWAVEFORMS 6 /* 6 TCC waveform outputs */
#elif defined(CONFIG_ARCH_CHIP_SAML21G16)
# define SAML21 1 /* SAML21 family */
# undef SAML21E
# define SAML21G 1 /* SAML21G */
# undef SAML21J
/* Internal memory */
# define SAMDL_FLASH_SIZE (64*1024) /* 64KB */
# define SAMDL_FLASHRWW_SIZE (2*1024) /* 2KB */
# define SAMDL_SRAM0_SIZE (8*1024) /* 8KB */
# define SAMDL_LPRAM_SIZE (4*1024) /* 4KB */
/* TCC waveform outputs */
# define SAMDL_TCC_NWAVEFORMS 2 /* 2 TCC waveform outputs */
#elif defined(CONFIG_ARCH_CHIP_SAML21G17)
# define SAML21 1 /* SAML21 family */
# undef SAML21E
# define SAML21G 1 /* SAML21G */
# undef SAML21J
/* Internal memory */
# define SAMDL_FLASH_SIZE (128*1024) /* 128KB */
# define SAMDL_FLASHRWW_SIZE (4*1024) /* 4KB */
# define SAMDL_SRAM0_SIZE (16*1024) /* 16KB */
# define SAMDL_LPRAM_SIZE (8*1024) /* 8KB */
/* TCC waveform outputs */
# define SAMDL_TCC_NWAVEFORMS 4 /* 4 TCC waveform outputs */
#elif defined(CONFIG_ARCH_CHIP_SAML21G18)
# define SAML21 1 /* SAML21 family */
# undef SAML21E
# define SAML21G 1 /* SAML21G */
# undef SAML21J
/* Internal memory */
# define SAMDL_FLASH_SIZE (256*1024) /* 256KB */
# define SAMDL_FLASHRWW_SIZE (8*1024) /* 8KB */
# define SAMDL_SRAM0_SIZE (32*1024) /* 32KB */
# define SAMDL_LPRAM_SIZE (8*1024) /* 8KB */
/* TCC waveform outputs */
# define SAMDL_TCC_NWAVEFORMS 8 /* 8 TCC waveform outputs */
#elif defined(CONFIG_ARCH_CHIP_SAML21J16)
# define SAML21 1 /* SAML21 family */
# undef SAML21E
# undef SAML21G
# define SAML21J 1 /* SAML21J */
/* Internal memory */
# define SAMDL_FLASH_SIZE (64*1024) /* 64KB */
# define SAMDL_FLASHRWW_SIZE (2*1024) /* 2KB */
# define SAMDL_SRAM0_SIZE (8*1024) /* 8KB */
# define SAMDL_LPRAM_SIZE (8*1024) /* 4KB */
/* TCC waveform outputs */
# define SAMDL_TCC_NWAVEFORMS 2 /* 2 TCC waveform outputs */
#elif defined(CONFIG_ARCH_CHIP_SAML21J17)
# define SAML21 1 /* SAML21 family */
# undef SAML21E
# undef SAML21G
# define SAML21J 1 /* SAML21J */
/* Internal memory */
# define SAMDL_FLASH_SIZE (128*1024) /* 128KB */
# define SAMDL_FLASHRWW_SIZE (4*1024) /* 4KB */
# define SAMDL_SRAM0_SIZE (16*1024) /* 16KB */
# define SAMDL_LPRAM_SIZE (8*1024) /* 8KB */
/* TCC waveform outputs */
# define SAMDL_TCC_NWAVEFORMS 4 /* 4 TCC waveform outputs */
#elif defined(CONFIG_ARCH_CHIP_SAML21J18)
# define SAML21 1 /* SAML21 family */
# undef SAML21E
# undef SAML21G
# define SAML21J 1 /* SAML21J */
/* Internal memory */
# define SAMDL_FLASH_SIZE (256*1024) /* 256KB */
# define SAMDL_FLASHRWW_SIZE (8*1024) /* 8KB */
# define SAMDL_SRAM0_SIZE (32*1024) /* 32KB */
# define SAMDL_LPRAM_SIZE (8*1024) /* 8KB */
/* TCC waveform outputs */
# define SAMDL_TCC_NWAVEFORMS 8 /* 8 TCC waveform outputs */
#else
# undef SAML21 /* Not SAML21 family */
# undef SAML21E
# undef SAML21G
# undef SAML21J
#endif
#if defined(SAML21E)
# define SAMDL_NEVENTS 12 /* 12 event channels */
# define SAMDL_NTC 3 /* 3 Timer/counters */
# define SAMDL_NTCOUT 2 /* 2 TC output channels */
# define SAMDL_NTCC 3 /* 3 TC control channels */
# define SAMDL_NTCCOUT 2 /* 2 TCC output channels */
# define SAMDL_NDMACHAN 16 /* 16 DMA channels */
# define SAMDL_NUSBIF 1 /* 1 USB interface */
# define SAMDL_NAES 1 /* 1 AES engine */
# define SAMDL_NCCL 4 /* 4 Counfigurable Custom Logic */
# define SAMDL_NTRNG 1 /* 1 True random number generator */
# define SAMDL_NSERCOM 4 /* 4 SERCOM */
# define SAMDL_NI2S 0 /* No I2S */
# define SAMDL_NADC 10 /* 10 ADC channels */
# define SAMDL_NCMP 2 /* 2 Comparators */
# define SAMDL_NDAC 2 /* 2 DAC channels */
# define SAMCL_NOPAMP 3 /* 3 OpAmps */
# define SAMDL_RTC 1 /* Have RTC */
# define SAMDL_NALARMS 1 /* 1 RTC alarm */
# define SAMDL_NRTCMP 1 /* RTC compare: 1 32-bit/2 16-bit */
# define SAMDL_NEXTINT 16 /* 16 External interrupts */
# define SAMDL_NPTCX 10 /* PTC X 6 or 10 */
# define SAMDL_NPTCY 10 /* PTC Y 6 or 10*/
# define SAMDL_WDT 1 /* Have watchdog timer */
#elif defined(SAML21G)
# define SAMDL_NEVENTS 12 /* 12 event channels */
# define SAMDL_NTC 3 /* 3 Timer/counters */
# define SAMDL_NTCOUT 2 /* 2 TC output channels */
# define SAMDL_NTCC 3 /* 3 TC control channels */
# define SAMDL_NTCCOUT 2 /* 2 TCC output channels */
# define SAMDL_NDMACHAN 16 /* 16 DMA channels */
# define SAMDL_NUSBIF 1 /* 1 USB interface */
# define SAMDL_NAES 1 /* 1 AES engine */
# define SAMDL_NCCL 4 /* 4 Counfigurable Custom Logic */
# define SAMDL_NTRNG 1 /* 1 True random number generator */
# define SAMDL_NSERCOM 6 /* 6 SERCOM */
# define SAMDL_NI2S 0 /* No I2S */
# define SAMDL_NADC 14 /* 14 ADC channels */
# define SAMDL_NCMP 2 /* 2 Comparators */
# define SAMDL_NDAC 2 /* 2 DAC channels */
# define SAMCL_NOPAMP 3 /* 3 OpAmps */
# define SAMDL_RTC 1 /* Have RTC */
# define SAMDL_NALARMS 1 /* 1 RTC alarm */
# define SAMDL_NRTCMP 1 /* RTC compare: 1 32-bit/2 16-bit */
# define SAMDL_NEXTINT 16 /* 16 External interrupts */
# define SAMDL_NPTCX 12 /* PTC X 8 or 12 */
# define SAMDL_NPTCY 12 /* PTC Y 8 or 12*/
# define SAMDL_WDT 1 /* Have watchdog timer */
#elif defined(SAML21J)
# define SAMDL_NEVENTS 12 /* 12 event channels */
# define SAMDL_NTC 5 /* 5 Timer/counters */
# define SAMDL_NTCOUT 2 /* 2 TC output channels */
# define SAMDL_NTCC 3 /* 3 TC control channels */
# define SAMDL_NTCCOUT 2 /* 2 TCC output channels */
# define SAMDL_NDMACHAN 16 /* 16 DMA channels */
# define SAMDL_NUSBIF 1 /* 1 USB interface */
# define SAMDL_NAES 1 /* 1 AES engine */
# define SAMDL_NCCL 4 /* 4 Counfigurable Custom Logic */
# define SAMDL_NTRNG 1 /* 1 True random number generator */
# define SAMDL_NSERCOM 6 /* 6 SERCOM */
# define SAMDL_NI2S 0 /* No I2S */
# define SAMDL_NADC 20 /* 20 ADC channels */
# define SAMDL_NCMP 2 /* 2 Comparators */
# define SAMDL_NDAC 2 /* 2 DAC channels */
# define SAMCL_NOPAMP 3 /* 3 OpAmps */
# define SAMDL_RTC 1 /* Have RTC */
# define SAMDL_NALARMS 1 /* 1 RTC alarm */
# define SAMDL_NRTCMP 1 /* RTC compare: 1 32-bit/2 16-bit */
# define SAMDL_NEXTINT 16 /* 16 External interrupts */
# define SAMDL_NPTCX 16 /* PTC X 12 or 16 */
# define SAMDL_NPTCY 16 /* PTC Y 12 or 16*/
# define SAMDL_WDT 1 /* Have watchdog timer */
#endif
/* NVIC priority levels *************************************************************/
/* Each priority field holds a priority value, 0-3. The lower the value, the greater
* the priority of the corresponding interrupt. The processor implements only
* bits[7:6] of each field, bits[5:0] read as zero and ignore writes.
*/
#define NVIC_SYSH_PRIORITY_MIN 0xc0 /* All bits[7:3] set is minimum priority */
#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */
#define NVIC_SYSH_PRIORITY_STEP 0x40 /* Five bits of interrupt priority used */
/************************************************************************************
* Public Types
************************************************************************************/
/************************************************************************************
* Public Data
************************************************************************************/
/************************************************************************************
* Public Functions
************************************************************************************/
#endif /* __ARCH_ARM_INCLUDE_SAMDL_CHIP_H */

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@ -1,116 +0,0 @@
/****************************************************************************************
* arch/arm/include/samdl/irq.h
*
* Copyright (C) 2014-2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************************/
/* This file should never be included directed but, rather, only indirectly through
* nuttx/irq.h
*/
#ifndef __ARCH_ARM_INCLUDE_SAMDL_IRQ_H
#define __ARCH_ARM_INCLUDE_SAMDL_IRQ_H
/****************************************************************************************
* Included Files
****************************************************************************************/
#include <nuttx/config.h>
#include <arch/samdl/chip.h>
/****************************************************************************************
* Pre-processor Definitions
****************************************************************************************/
/* IRQ numbers. The IRQ number corresponds vector number and hence map directly to
* bits in the NVIC. This does, however, waste several words of memory in the IRQ
* to handle mapping tables.
*/
/* Processor Exceptions (vectors 0-15) */
#define SAM_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG) */
/* Vector 0: Reset stack pointer value */
/* Vector 1: Reset (not handler as an IRQ) */
#define SAM_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */
#define SAM_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */
/* Vector 4-10: Reserved */
#define SAM_IRQ_SVCALL (11) /* Vector 11: SVC call */
/* Vector 12-13: Reserved */
#define SAM_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */
#define SAM_IRQ_SYSTICK (15) /* Vector 15: System tick */
/* External interrupts (vectors >= 16). These definitions are chip-specific */
#define SAM_IRQ_INTERRUPT (16) /* Vector number of the first external interrupt */
/* Chip-Specific External interrupts */
#if defined(CONFIG_ARCH_FAMILY_SAMD20)
# include <arch/samdl/samd20_irq.h>
#elif defined(CONFIG_ARCH_FAMILY_SAMD21)
# include <arch/samdl/samd21_irq.h>
#elif defined(CONFIG_ARCH_FAMILY_SAML21)
# include <arch/samdl/saml21_irq.h>
#else
# error Unrecognized SAMD/L architecture
#endif
/****************************************************************************************
* Public Types
****************************************************************************************/
#ifndef __ASSEMBLY__
/****************************************************************************************
* Public Data
****************************************************************************************/
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************************
* Public Function Prototypes
****************************************************************************************/
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif
#endif /* __ARCH_ARM_INCLUDE_SAMDL_IRQ_H */

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@ -1,142 +0,0 @@
/****************************************************************************************
* arch/arm/include/samd/samd20_irq.h
*
* Copyright (C) 2014 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************************/
/* This file should never be included directed but, rather, only indirectly through
* nuttx/irq.h
*/
#ifndef __ARCH_ARM_INCLUDE_SAMDL_SAMD20_IRQ_H
#define __ARCH_ARM_INCLUDE_SAMDL_SAMD20_IRQ_H
/****************************************************************************************
* Included Files
****************************************************************************************/
/****************************************************************************************
* Pre-processor Definitions
****************************************************************************************/
/* External interrupts */
#define SAM_IRQ_PM (SAM_IRQ_INTERRUPT+0) /* Power Manager */
#define SAM_IRQ_SYSCTRL (SAM_IRQ_INTERRUPT+1) /* System Controller */
#define SAM_IRQ_WDT (SAM_IRQ_INTERRUPT+2) /* Watchdog Timer */
#define SAM_IRQ_RTC (SAM_IRQ_INTERRUPT+3) /* Real Time Counter */
#define SAM_IRQ_EIC (SAM_IRQ_INTERRUPT+4) /* External Interrupt Controller */
#define SAM_IRQ_NVMCTRL (SAM_IRQ_INTERRUPT+5) /* Non-Volatile Memory Controller */
#define SAM_IRQ_EVSYS (SAM_IRQ_INTERRUPT+6) /* Event System */
#define SAM_IRQ_SERCOM0 (SAM_IRQ_INTERRUPT+7) /* Serial Communication Interface 0 */
#define SAM_IRQ_SERCOM1 (SAM_IRQ_INTERRUPT+8) /* Serial Communication Interface 1 */
#define SAM_IRQ_SERCOM2 (SAM_IRQ_INTERRUPT+9) /* Serial Communication Interface 2 */
#define SAM_IRQ_SERCOM3 (SAM_IRQ_INTERRUPT+10) /* Serial Communication Interface 3 */
#define SAM_IRQ_SERCOM4 (SAM_IRQ_INTERRUPT+11) /* Serial Communication Interface 4 */
#define SAM_IRQ_SERCOM5 (SAM_IRQ_INTERRUPT+12) /* Serial Communication Interface 5 */
#define SAM_IRQ_TC0 (SAM_IRQ_INTERRUPT+13) /* Timer/Counter 0 */
#define SAM_IRQ_TC1 (SAM_IRQ_INTERRUPT+14) /* Timer/Counter 1 */
#define SAM_IRQ_TC2 (SAM_IRQ_INTERRUPT+15) /* Timer/Counter 2 */
#define SAM_IRQ_TC3 (SAM_IRQ_INTERRUPT+16) /* Timer/Counter 3 */
#define SAM_IRQ_TC4 (SAM_IRQ_INTERRUPT+17) /* Timer/Counter 4 */
#define SAM_IRQ_TC5 (SAM_IRQ_INTERRUPT+18) /* Timer/Counter 5 */
#define SAM_IRQ_TC6 (SAM_IRQ_INTERRUPT+19) /* Timer/Counter 6 */
#define SAM_IRQ_TC7 (SAM_IRQ_INTERRUPT+20) /* Timer/Counter 7 */
#define SAM_IRQ_ADC (SAM_IRQ_INTERRUPT+21) /* Analog-to-Digital Converter */
#define SAM_IRQ_AC (SAM_IRQ_INTERRUPT+22) /* Analog Comparator */
#define SAM_IRQ_DAC (SAM_IRQ_INTERRUPT+23) /* Digital-to-Analog Converter */
#define SAM_IRQ_PTC (SAM_IRQ_INTERRUPT+24) /* Peripheral Touch Controller*/
#define SAM_IRQ_NINTS (25) /* Total number of interrupts */
#define SAM_IRQ_NIRQS (SAM_IRQ_INTERRUPT+25) /* The number of real interrupts */
/* GPIO interrupts. Up to 16 pins may be configured to support interrupts */
#ifdef CONFIG_GPIO_IRQ
# define SAM_IRQ_EXTINT0 (SAM_IRQ_NIRQS+0) /* External interrupt 0 */
# define SAM_IRQ_EXTINT1 (SAM_IRQ_NIRQS+1) /* External interrupt 1 */
# define SAM_IRQ_EXTINT2 (SAM_IRQ_NIRQS+2) /* External interrupt 2 */
# define SAM_IRQ_EXTINT3 (SAM_IRQ_NIRQS+3) /* External interrupt 3 */
# define SAM_IRQ_EXTINT4 (SAM_IRQ_NIRQS+4) /* External interrupt 4 */
# define SAM_IRQ_EXTINT5 (SAM_IRQ_NIRQS+5) /* External interrupt 5 */
# define SAM_IRQ_EXTINT6 (SAM_IRQ_NIRQS+6) /* External interrupt 6 */
# define SAM_IRQ_EXTINT7 (SAM_IRQ_NIRQS+7) /* External interrupt 7 */
# define SAM_IRQ_EXTINT8 (SAM_IRQ_NIRQS+8) /* External interrupt 8 */
# define SAM_IRQ_EXTINT9 (SAM_IRQ_NIRQS+9) /* External interrupt 9 */
# define SAM_IRQ_EXTINT10 (SAM_IRQ_NIRQS+10) /* External interrupt 10 */
# define SAM_IRQ_EXTINT11 (SAM_IRQ_NIRQS+11) /* External interrupt 11 */
# define SAM_IRQ_EXTINT12 (SAM_IRQ_NIRQS+12) /* External interrupt 12 */
# define SAM_IRQ_EXTINT13 (SAM_IRQ_NIRQS+13) /* External interrupt 13 */
# define SAM_IRQ_EXTINT14 (SAM_IRQ_NIRQS+14) /* External interrupt 14 */
# define SAM_IRQ_EXTINT15 (SAM_IRQ_NIRQS+15) /* External interrupt 15 */
# define SAM_IRQ_NEXTINTS 16
#else
# define SAM_IRQ_NEXTINTS 0
#endif
/* Total number of IRQ numbers */
#define NR_VECTORS SAM_IRQ_NIRQS
#define NR_IRQS (SAM_IRQ_INTERRUPT + SAM_IRQ_NINTS + SAM_IRQ_NEXTINTS)
/****************************************************************************************
* Public Types
****************************************************************************************/
/****************************************************************************************
* Inline functions
****************************************************************************************/
/****************************************************************************************
* Public Variables
****************************************************************************************/
/****************************************************************************************
* Public Function Prototypes
****************************************************************************************/
#ifndef __ASSEMBLY__
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif
#endif /* __ARCH_ARM_INCLUDE_SAMDL_SAMD20_IRQ_H */

149
arch/arm/include/samdl/samd21_irq.h
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@ -1,149 +0,0 @@
/****************************************************************************************
* arch/arm/include/samd/samd21_irq.h
*
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* References:
* "Atmel SAM D21E / SAM D21G / SAM D21J SMART ARM-Based Microcontroller
* Datasheet", Atmel-42181E–SAM-D21_Datasheet–02/2015
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************************/
/* This file should never be included directed but, rather, only indirectly through
* nuttx/irq.h
*/
#ifndef __ARCH_ARM_INCLUDE_SAMDL_SAMD21_IRQ_H
#define __ARCH_ARM_INCLUDE_SAMDL_SAMD21_IRQ_H
/****************************************************************************************
* Included Files
****************************************************************************************/
/****************************************************************************************
* Pre-processor Definitions
****************************************************************************************/
/* External interrupts */
#define SAM_IRQ_PM (SAM_IRQ_INTERRUPT+0) /* Power Manager */
#define SAM_IRQ_SYSCTRL (SAM_IRQ_INTERRUPT+1) /* System Controller */
#define SAM_IRQ_WDT (SAM_IRQ_INTERRUPT+2) /* Watchdog Timer */
#define SAM_IRQ_RTC (SAM_IRQ_INTERRUPT+3) /* Real Time Counter */
#define SAM_IRQ_EIC (SAM_IRQ_INTERRUPT+4) /* External Interrupt Controller */
#define SAM_IRQ_NVMCTRL (SAM_IRQ_INTERRUPT+5) /* Non-Volatile Memory Controller */
#define SAM_IRQ_DMAC (SAM_IRQ_INTERRUPT+6) /* Direct Memory Access Controller */
#define SAM_IRQ_USB (SAM_IRQ_INTERRUPT+7) /* Universal Serial Bus */
#define SAM_IRQ_EVSYS (SAM_IRQ_INTERRUPT+8) /* Event System */
#define SAM_IRQ_SERCOM0 (SAM_IRQ_INTERRUPT+9) /* Serial Communication Interface 0 */
#define SAM_IRQ_SERCOM1 (SAM_IRQ_INTERRUPT+10) /* Serial Communication Interface 1 */
#define SAM_IRQ_SERCOM2 (SAM_IRQ_INTERRUPT+11) /* Serial Communication Interface 2 */
#define SAM_IRQ_SERCOM3 (SAM_IRQ_INTERRUPT+12) /* Serial Communication Interface 3 */
#define SAM_IRQ_SERCOM4 (SAM_IRQ_INTERRUPT+13) /* Serial Communication Interface 4 */
#define SAM_IRQ_SERCOM5 (SAM_IRQ_INTERRUPT+14) /* Serial Communication Interface 5 */
#define SAM_IRQ_TCC0 (SAM_IRQ_INTERRUPT+15) /* Timer/Counter for Control 0 */
#define SAM_IRQ_TCC1 (SAM_IRQ_INTERRUPT+16) /* Timer/Counter for Control 1 */
#define SAM_IRQ_TCC2 (SAM_IRQ_INTERRUPT+17) /* Timer/Counter for Control 2 */
#define SAM_IRQ_TC3 (SAM_IRQ_INTERRUPT+18) /* Timer/Counter 3 */
#define SAM_IRQ_TC4 (SAM_IRQ_INTERRUPT+19) /* Timer/Counter 4 */
#define SAM_IRQ_TC5 (SAM_IRQ_INTERRUPT+20) /* Timer/Counter 5 */
#define SAM_IRQ_TC6 (SAM_IRQ_INTERRUPT+21) /* Timer/Counter 6 */
#define SAM_IRQ_TC7 (SAM_IRQ_INTERRUPT+22) /* Timer/Counter 7 */
#define SAM_IRQ_ADC (SAM_IRQ_INTERRUPT+23) /* Analog-to-Digital Converter */
#define SAM_IRQ_AC (SAM_IRQ_INTERRUPT+24) /* Analog Comparator */
#define SAM_IRQ_DAC (SAM_IRQ_INTERRUPT+25) /* Digital-to-Analog Converter */
#define SAM_IRQ_PTC (SAM_IRQ_INTERRUPT+26) /* Peripheral Touch Controller */
#define SAM_IRQ_I2S (SAM_IRQ_INTERRUPT+27) /* Inter IC Sound */
#define SAM_IRQ_NINTS (28) /* Total number of interrupts */
#define SAM_IRQ_NIRQS (SAM_IRQ_INTERRUPT+28) /* The number of real interrupts */
/* GPIO interrupts. Up to 16 pins may be configured to support interrupts */
#ifdef CONFIG_GPIO_IRQ
# define SAM_IRQ_EXTINT0 (SAM_IRQ_NIRQS+0) /* External interrupt 0 */
# define SAM_IRQ_EXTINT1 (SAM_IRQ_NIRQS+1) /* External interrupt 1 */
# define SAM_IRQ_EXTINT2 (SAM_IRQ_NIRQS+2) /* External interrupt 2 */
# define SAM_IRQ_EXTINT3 (SAM_IRQ_NIRQS+3) /* External interrupt 3 */
# define SAM_IRQ_EXTINT4 (SAM_IRQ_NIRQS+4) /* External interrupt 4 */
# define SAM_IRQ_EXTINT5 (SAM_IRQ_NIRQS+5) /* External interrupt 5 */
# define SAM_IRQ_EXTINT6 (SAM_IRQ_NIRQS+6) /* External interrupt 6 */
# define SAM_IRQ_EXTINT7 (SAM_IRQ_NIRQS+7) /* External interrupt 7 */
# define SAM_IRQ_EXTINT8 (SAM_IRQ_NIRQS+8) /* External interrupt 8 */
# define SAM_IRQ_EXTINT9 (SAM_IRQ_NIRQS+9) /* External interrupt 9 */
# define SAM_IRQ_EXTINT10 (SAM_IRQ_NIRQS+10) /* External interrupt 10 */
# define SAM_IRQ_EXTINT11 (SAM_IRQ_NIRQS+11) /* External interrupt 11 */
# define SAM_IRQ_EXTINT12 (SAM_IRQ_NIRQS+12) /* External interrupt 12 */
# define SAM_IRQ_EXTINT13 (SAM_IRQ_NIRQS+13) /* External interrupt 13 */
# define SAM_IRQ_EXTINT14 (SAM_IRQ_NIRQS+14) /* External interrupt 14 */
# define SAM_IRQ_EXTINT15 (SAM_IRQ_NIRQS+15) /* External interrupt 15 */
# define SAM_IRQ_NEXTINTS 16
#else
# define SAM_IRQ_NEXTINTS 0
#endif
/* Total number of IRQ numbers */
#define NR_VECTORS SAM_IRQ_NIRQS
#define NR_IRQS (SAM_IRQ_INTERRUPT + SAM_IRQ_NINTS + SAM_IRQ_NEXTINTS)
/****************************************************************************************
* Public Types
****************************************************************************************/
/****************************************************************************************
* Inline Functions
****************************************************************************************/
/****************************************************************************************
* Public Data
****************************************************************************************/
#ifndef __ASSEMBLY__
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************************
* Public Function Prototypes
****************************************************************************************/
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif
#endif /* __ARCH_ARM_INCLUDE_SAMDL_SAMD21_IRQ_H */

150
arch/arm/include/samdl/saml21_irq.h
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@ -1,150 +0,0 @@
/****************************************************************************************
* arch/arm/include/samd/saml21_irq.h
*
* Copyright (C) 2014 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************************/
/* This file should never be included directed but, rather, only indirectly through
* nuttx/irq.h
*/
#ifndef __ARCH_ARM_INCLUDE_SAMDL_SAML21_IRQ_H
#define __ARCH_ARM_INCLUDE_SAMDL_SAML21_IRQ_H
/****************************************************************************************
* Included Files
****************************************************************************************/
/****************************************************************************************
* Pre-processor Definitions
****************************************************************************************/
/* External interrupts */
#define SAM_IRQ_PM (SAM_IRQ_INTERRUPT+0) /* Power Manager */
#define SAM_IRQ_MCLK (SAM_IRQ_INTERRUPT+0) /* Main Clock */
#define SAM_IRQ_OSCCTRL (SAM_IRQ_INTERRUPT+0) /* Oscillators Controller */
#define SAM_IRQ_OSC32KCTRL (SAM_IRQ_INTERRUPT+0) /* 32KHz scillators Controller */
#define SAM_IRQ_SUPC (SAM_IRQ_INTERRUPT+0) /* Supply Controller */
#define SAM_IRQ_PACC (SAM_IRQ_INTERRUPT+0) /* Protection Access Controller */
#define SAM_IRQ_WDT (SAM_IRQ_INTERRUPT+1) /* Watchdog Timer */
#define SAM_IRQ_RTC (SAM_IRQ_INTERRUPT+2) /* Real Time Counter */
#define SAM_IRQ_EIC (SAM_IRQ_INTERRUPT+3) /* External Interrupt Controller */
#define SAM_IRQ_NVMCTRL (SAM_IRQ_INTERRUPT+4) /* Non-Volatile Memory Controller */
#define SAM_IRQ_DMAC (SAM_IRQ_INTERRUPT+5) /* Direct Memory Access Controller */
#define SAM_IRQ_USB (SAM_IRQ_INTERRUPT+6) /* Universal Serial Bus */
#define SAM_IRQ_EVSYS (SAM_IRQ_INTERRUPT+7) /* Event System */
#define SAM_IRQ_SERCOM0 (SAM_IRQ_INTERRUPT+8) /* Serial Communication Interface 0 */
#define SAM_IRQ_SERCOM1 (SAM_IRQ_INTERRUPT+9) /* Serial Communication Interface 1 */
#define SAM_IRQ_SERCOM2 (SAM_IRQ_INTERRUPT+10) /* Serial Communication Interface 2 */
#define SAM_IRQ_SERCOM3 (SAM_IRQ_INTERRUPT+11) /* Serial Communication Interface 3 */
#define SAM_IRQ_SERCOM4 (SAM_IRQ_INTERRUPT+12) /* Serial Communication Interface 4 */
#define SAM_IRQ_SERCOM5 (SAM_IRQ_INTERRUPT+13) /* Serial Communication Interface 5 */
#define SAM_IRQ_TCC0 (SAM_IRQ_INTERRUPT+14) /* Timer/Counter for Control 0 */
#define SAM_IRQ_TCC1 (SAM_IRQ_INTERRUPT+15) /* Timer/Counter for Control 1 */
#define SAM_IRQ_TCC2 (SAM_IRQ_INTERRUPT+16) /* Timer/Counter for Control 2 */
#define SAM_IRQ_TC0 (SAM_IRQ_INTERRUPT+17) /* Timer/Counter 0 */
#define SAM_IRQ_TC1 (SAM_IRQ_INTERRUPT+18) /* Timer/Counter 1 */
#define SAM_IRQ_TC2 (SAM_IRQ_INTERRUPT+19) /* Timer/Counter 2 */
#define SAM_IRQ_TC3 (SAM_IRQ_INTERRUPT+20) /* Timer/Counter 3 */
#define SAM_IRQ_TC4 (SAM_IRQ_INTERRUPT+21) /* Timer/Counter 4 */
#define SAM_IRQ_ADC (SAM_IRQ_INTERRUPT+22) /* Analog-to-Digital Converter */
#define SAM_IRQ_AC (SAM_IRQ_INTERRUPT+23) /* Analog Comparator */
#define SAM_IRQ_DAC (SAM_IRQ_INTERRUPT+24) /* Digital-to-Analog Converter */
#define SAM_IRQ_PTC (SAM_IRQ_INTERRUPT+25) /* Peripheral Touch Controller */
#define SAM_IRQ_AES (SAM_IRQ_INTERRUPT+26) /* Advanced Encryption Standard Module */
#define SAM_IRQ_TRNG (SAM_IRQ_INTERRUPT+27) /* True Random Number Generator */
#define SAM_IRQ_NINTS (28) /* Total number of interrupts */
#define SAM_IRQ_NIRQS (SAM_IRQ_INTERRUPT+28) /* The number of real interrupts */
/* GPIO interrupts. Up to 16 pins may be configured to support interrupts */
#ifdef CONFIG_GPIO_IRQ
# define SAM_IRQ_EXTINT0 (SAM_IRQ_NIRQS+0) /* External interrupt 0 */
# define SAM_IRQ_EXTINT1 (SAM_IRQ_NIRQS+1) /* External interrupt 1 */
# define SAM_IRQ_EXTINT2 (SAM_IRQ_NIRQS+2) /* External interrupt 2 */
# define SAM_IRQ_EXTINT3 (SAM_IRQ_NIRQS+3) /* External interrupt 3 */
# define SAM_IRQ_EXTINT4 (SAM_IRQ_NIRQS+4) /* External interrupt 4 */
# define SAM_IRQ_EXTINT5 (SAM_IRQ_NIRQS+5) /* External interrupt 5 */
# define SAM_IRQ_EXTINT6 (SAM_IRQ_NIRQS+6) /* External interrupt 6 */
# define SAM_IRQ_EXTINT7 (SAM_IRQ_NIRQS+7) /* External interrupt 7 */
# define SAM_IRQ_EXTINT8 (SAM_IRQ_NIRQS+8) /* External interrupt 8 */
# define SAM_IRQ_EXTINT9 (SAM_IRQ_NIRQS+9) /* External interrupt 9 */
# define SAM_IRQ_EXTINT10 (SAM_IRQ_NIRQS+10) /* External interrupt 10 */
# define SAM_IRQ_EXTINT11 (SAM_IRQ_NIRQS+11) /* External interrupt 11 */
# define SAM_IRQ_EXTINT12 (SAM_IRQ_NIRQS+12) /* External interrupt 12 */
# define SAM_IRQ_EXTINT13 (SAM_IRQ_NIRQS+13) /* External interrupt 13 */
# define SAM_IRQ_EXTINT14 (SAM_IRQ_NIRQS+14) /* External interrupt 14 */
# define SAM_IRQ_EXTINT15 (SAM_IRQ_NIRQS+15) /* External interrupt 15 */
# define SAM_IRQ_NEXTINTS 16
#else
# define SAM_IRQ_NEXTINTS 0
#endif
/* Total number of IRQ numbers */
#define NR_VECTORS SAM_IRQ_NIRQS
#define NR_IRQS (SAM_IRQ_INTERRUPT + SAM_IRQ_NINTS + SAM_IRQ_NEXTINTS)
/****************************************************************************************
* Public Types
****************************************************************************************/
/****************************************************************************************
* Inline Functions
****************************************************************************************/
/****************************************************************************************
* Public Data
****************************************************************************************/
#ifndef __ASSEMBLY__
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************************
* Public Function Prototypes
****************************************************************************************/
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif
#endif /* __ARCH_ARM_INCLUDE_SAMDL_SAML21_IRQ_H */

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arch/arm/include/samv7/chip.h
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@ -1,295 +0,0 @@
/************************************************************************************
* arch/arm/include/samv7/chip.h
*
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_INCLUDE_SAMV7_CHIP_H
#define __ARCH_ARM_INCLUDE_SAMV7_CHIP_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Get customizations for each supported chip */
/* SAMV71Q19 - 512 Kbytes FLASH / 256 Kbytes SRAM
* SAMV71Q20 - 1024 Kbytes FLASH / 384 Kbytes SRAM
* SAMV71Q21 - 2048 Kbytes FLASH / 384 Kbytes SRAM
*
* LQFP144 and LFBGA144 packaging
*/
#if defined(CONFIG_ARCH_CHIP_SAMV71Q19) || defined(CONFIG_ARCH_CHIP_SAMV71Q20) || \
defined(CONFIG_ARCH_CHIP_SAMV71Q21)
/* Internal memory */
#if defined(CONFIG_ARCH_CHIP_SAMV71Q19)
# define SAMV7_FLASH_SIZE (512*1024) /* 512KB */
# define SAMV7_SRAM_SIZE (256*1024) /* 256KB */
#elif defined(CONFIG_ARCH_CHIP_SAMV71Q20)
# define SAMV7_FLASH_SIZE (1024*1024) /* 1024KB */
# define SAMV7_SRAM_SIZE (384*1024) /* 384KB */
#else /* if defined(CONFIG_ARCH_CHIP_SAMV71Q21) */
# define SAMV7_FLASH_SIZE (2048*1024) /* 2048KB */
# define SAMV7_SRAM_SIZE (384*1024) /* 384KB */
#endif
#define SAMV7_BSRAM_SIZE (1*1024) /* 1KB */
/* Peripherals */
# define SAMV7_NPIO 5 /* 5 PIO ports A-E */
# define SAMV7_NEBI 1 /* Have External Bus Interface (EBI) */
# define SAMV7_NSDRAMC 1 /* Have SDRAM controller (SDRAMC) */
# define SAMV7_NMLB 1 /* Have MediaLB interface (MLB) */
# define SAMV7_NDMACHAN 24 /* 24 Central DMA Channels */
# define SAMV7_NADC12 24 /* 24 12-bit ADC channels */
# define SAMV7_NDAC12 2 /* 2 12-bit DAC channels */
# define SAMV7_NTCCH 12 /* 12 Timer/counter channels */
# define SAMV7_NTCCHIO 36 /* 12 Timer/counter channels I/O */
# define SAMV7_NUSART 3 /* 3 USARTs */
# define SAMV7_NUART 5 /* 5 UARTs */
# define SAMV7_NQSPI 5 /* 1 Quad SPI */
# define SAMV7_NSPI 2 /* 2 SPI, SPI0-1 */
# define SAMV7_NTWIHS 3 /* 3 TWIHS */
# define SAMV7_NHSMCI4 1 /* 1 4-bit HSMCI port */
# define SAMV7_NCAN 2 /* 2 CAN ports */
# define SAMV7_NEMAC 1 /* 1 Ethernet MAC (GMAC) */
# define SAMV7_NEMACMII 1 /* 1 Ethernet MAC MII interface */
# define SAMV7_NEMACRMII 1 /* 1 Ethernet MAC RMII interface */
# define SAMV7_NISI12 1 /* 1 12-bit ISI interface */
# define SAMV7_NISI8 0 /* No 8-bit ISI interface */
# define SAMV7_NSSC 1 /* 1 SSC */
# define SAMV7_NUDPHS 1 /* 1 USB high speed device */
# define SAMV7_NUHPHS 1 /* 1 USB high speed embedded Mini-Host */
# define SAMV7_NUDPFS 0 /* No USB full speed device */
# define SAMV7_NUHPFS 0 /* No USB full speed embedded host */
# define SAMV7_NACC 1 /* 1 Analog comparator */
# define SAMV7_NETM 1 /* 1 Embedded Trace Macrocell (ETM) */
/* SAMV71N19 - 512 Kbytes FLASH / 256 Kbytes SRAM
* SAMV71N20 - 1024 Kbytes FLASH / 384 Kbytes SRAM
* SAMV71N21 - 2048 Kbytes FLASH / 384 Kbytes SRAM
*
* LQFP100 and TFBGA100 packaging
*/
#elif defined(CONFIG_ARCH_CHIP_SAMV71N19) || defined(CONFIG_ARCH_CHIP_SAMV71N20) || \
defined(CONFIG_ARCH_CHIP_SAMV71N21)
/* Internal memory */
#if defined(CONFIG_ARCH_CHIP_SAMV71N19)
# define SAMV7_FLASH_SIZE (512*1024) /* 512KB */
# define SAMV7_SRAM_SIZE (256*1024) /* 256KB */
#elif defined(CONFIG_ARCH_CHIP_SAMV71N20)
# define SAMV7_FLASH_SIZE (1024*1024) /* 1024KB */
# define SAMV7_SRAM_SIZE (384*1024) /* 384KB */
#else /* if defined(CONFIG_ARCH_CHIP_SAMV71N21) */
# define SAMV7_FLASH_SIZE (2048*1024) /* 2048KB */
# define SAMV7_SRAM_SIZE (384*1024) /* 384KB */
#endif
#define SAMV7_BSRAM_SIZE (1*1024) /* 1KB */
/* Peripherals */
# define SAMV7_NPIO 5 /* 5 PIO ports A-E */
# define SAMV7_NEBI 0 /* No External Bus Interface (EBI) */
# define SAMV7_NSDRAMC 0 /* No SDRAM controller (SDRAMC) */
# define SAMV7_NMLB 1 /* Have MediaLB interface (MLB) */
# define SAMV7_NDMACHAN 24 /* 24 Central DMA Channels */
# define SAMV7_NADC12 10 /* 10 12-bit ADC channels */
# define SAMV7_NDAC12 2 /* 2 12-bit DAC channels */
# define SAMV7_NTCCH 12 /* 12 Timer/counter channels */
# define SAMV7_NTCCHIO 9 /* 12 Timer/counter channels I/O */
# define SAMV7_NUSART 3 /* 3 USARTs */
# define SAMV7_NUART 5 /* 5 UARTs */
# define SAMV7_NQSPI 5 /* 1 Quad SPI */
# define SAMV7_NSPI 1 /* 1 SPI, SPI0 */
# define SAMV7_NTWIHS 3 /* 3 TWIHS */
# define SAMV7_NHSMCI4 1 /* 1 4-bit HSMCI port */
# define SAMV7_NCAN 2 /* 2 CAN ports */
# define SAMV7_NEMAC 1 /* 1 Ethernet MAC (GMAC) */
# define SAMV7_NEMACMII 1 /* 1 Ethernet MAC MII interface */
# define SAMV7_NEMACRMII 1 /* 1 Ethernet MAC RMII interface */
# define SAMV7_NISI12 1 /* 1 12-bit ISI interface */
# define SAMV7_NISI8 0 /* No 8-bit ISI interface */
# define SAMV7_NSSC 1 /* 1 SSC */
# define SAMV7_NUDPHS 1 /* 1 USB high speed device */
# define SAMV7_NUHPHS 1 /* 1 USB high speed embedded Mini-Host */
# define SAMV7_NUDPFS 0 /* No USB full speed device */
# define SAMV7_NUHPFS 0 /* No USB full speed embedded host */
# define SAMV7_NACC 1 /* 1 Analog comparator */
# define SAMV7_NETM 1 /* 1 Embedded Trace Macrocell (ETM) */
/* SAMV71J19 - 512 Kbytes FLASH / 256 Kbytes SRAM
* SAMV71J20 - 1024 Kbytes FLASH / 384 Kbytes SRAM
* SAMV71J21 - 2048 Kbytes FLASH / 384 Kbytes SRAM
*
* LQFP64, TFBGA64, and QFN64 packaging
*/
#elif defined(CONFIG_ARCH_CHIP_SAMV71J19) || defined(CONFIG_ARCH_CHIP_SAMV71J20) || \
defined(CONFIG_ARCH_CHIP_SAMV71J21)
/* Internal memory */
#if defined(CONFIG_ARCH_CHIP_SAMV71J19)
# define SAMV7_FLASH_SIZE (512*1024) /* 512KB */
# define SAMV7_SRAM_SIZE (256*1024) /* 256KB */
#elif defined(CONFIG_ARCH_CHIP_SAMV71J20)
# define SAMV7_FLASH_SIZE (1024*1024) /* 1024KB */
# define SAMV7_SRAM_SIZE (384*1024) /* 384KB */
#else /* if defined(CONFIG_ARCH_CHIP_SAMV71J21) */
# define SAMV7_FLASH_SIZE (2048*1024) /* 2048KB */
# define SAMV7_SRAM_SIZE (384*1024) /* 384KB */
#endif
#define SAMV7_BSRAM_SIZE (1*1024) /* 1KB */
/* Peripherals */
# define SAMV7_NPIO 5 /* 5 PIO ports A-E */
# define SAMV7_NEBI 0 /* No External Bus Interface (EBI) */
# define SAMV7_NSDRAMC 0 /* No SDRAM controller (SDRAMC) */
# define SAMV7_NMLB 1 /* Have MediaLB interface (MLB) */
# define SAMV7_NDMACHAN 24 /* 24 Central DMA Channels */
# define SAMV7_NADC12 5 /* 5 12-bit ADC channels */
# define SAMV7_NDAC12 1 /* 1 12-bit DAC channels */
# define SAMV7_NTCCH 12 /* 12 Timer/counter channels */
# define SAMV7_NTCCHIO 3 /* 12 Timer/counter channels I/O */
# define SAMV7_NUSART 0 /* No USARTs */
# define SAMV7_NUART 5 /* 5 UARTs */
# define SAMV7_NQSPI 0 /* No Quad SPI */
# define SAMV7_NSPI 1 /* 1 SPI, QSPI functions in SPI mode only */
# define SAMV7_NTWIHS 2 /* 2 TWIHS */
# define SAMV7_NHSMCI4 0 /* No 4-bit HSMCI port */
# define SAMV7_NCAN 1 /* 1 CAN port */
# define SAMV7_NEMAC 1 /* 1 Ethernet MAC (GMAC) */
# define SAMV7_NEMACMII 0 /* No Ethernet MAC MII interface */
# define SAMV7_NEMACRMII 1 /* 1 Ethernet MAC RMII interface */
# define SAMV7_NISI12 0 /* No 12-bit ISI interface */
# define SAMV7_NISI8 1 /* 1 8-bit ISI interface */
# define SAMV7_NSSC 1 /* 1 SSC */
# define SAMV7_NUDPHS 0 /* No USB high speed device */
# define SAMV7_NUHPHS 0 /* No USB high speed embedded Mini-Host */
# define SAMV7_NUDPFS 1 /* 1 USB full speed device */
# define SAMV7_NUHPFS 1 /* 1 USB full speed embedded host */
# define SAMV7_NACC 1 /* 1 Analog comparator */
# define SAMV7_NETM 1 /* 1 Embedded Trace Macrocell (ETM) */
#else
# error "Unknown SAMV7 chip type"
#endif
/* NVIC priority levels *************************************************************/
/* Each priority field holds a priority value, 0-15. The lower the value, the greater
* the priority of the corresponding interrupt. The processor implements only
* bits[7:4] of each field, bits[3:0] read as zero and ignore writes.
*/
#define NVIC_SYSH_PRIORITY_MIN 0xc0 /* All bits[7:6] set is minimum priority */
#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */
#define NVIC_SYSH_PRIORITY_STEP 0x40 /* Two bits of interrupt priority used */
/* If CONFIG_ARMV7M_USEBASEPRI is selected, then interrupts will be disabled
* by setting the BASEPRI register to NVIC_SYSH_DISABLE_PRIORITY so that most
* interrupts will not have execution priority. SVCall must have execution
* priority in all cases.
*
* In the normal cases, interrupts are not nest-able and all interrupts run
* at an execution priority between NVIC_SYSH_PRIORITY_MIN and
* NVIC_SYSH_PRIORITY_MAX (with NVIC_SYSH_PRIORITY_MAX reserved for SVCall).
*
* If, in addition, CONFIG_ARCH_HIPRI_INTERRUPT is defined, then special
* high priority interrupts are supported. These are not "nested" in the
* normal sense of the word. These high priority interrupts can interrupt
* normal processing but execute outside of OS (although they can "get back
* into the game" via a PendSV interrupt).
*
* In the normal course of things, interrupts must occasionally be disabled
* using the irqsave() inline function to prevent contention in use of
* resources that may be shared between interrupt level and non-interrupt
* level logic. Now the question arises, if CONFIG_ARCH_HIPRI_INTERRUPT,
* do we disable all interrupts (except SVCall), or do we only disable the
* "normal" interrupts. Since the high priority interrupts cannot interact
* with the OS, you may want to permit the high priority interrupts even if
* interrupts are disabled. The setting CONFIG_ARCH_INT_DISABLEALL can be
* used to select either behavior:
*
* ----------------------------+--------------+----------------------------
* CONFIG_ARCH_HIPRI_INTERRUPT | NO | YES
* ----------------------------+--------------+--------------+-------------
* CONFIG_ARCH_INT_DISABLEALL | N/A | YES | NO
* ----------------------------+--------------+--------------+-------------
* | | | SVCall
* | SVCall | SVCall | HIGH
* Disable here and below --------> MAXNORMAL ---> HIGH --------> MAXNORMAL
* | | MAXNORMAL |
* ----------------------------+--------------+--------------+-------------
*/
#if defined(CONFIG_ARCH_HIPRI_INTERRUPT) && defined(CONFIG_ARCH_INT_DISABLEALL)
# define NVIC_SYSH_MAXNORMAL_PRIORITY (NVIC_SYSH_PRIORITY_MAX + 2*NVIC_SYSH_PRIORITY_STEP)
# define NVIC_SYSH_HIGH_PRIORITY (NVIC_SYSH_PRIORITY_MAX + NVIC_SYSH_PRIORITY_STEP)
# define NVIC_SYSH_DISABLE_PRIORITY NVIC_SYSH_HIGH_PRIORITY
# define NVIC_SYSH_SVCALL_PRIORITY NVIC_SYSH_PRIORITY_MAX
#else
# define NVIC_SYSH_MAXNORMAL_PRIORITY (NVIC_SYSH_PRIORITY_MAX + NVIC_SYSH_PRIORITY_STEP)
# define NVIC_SYSH_HIGH_PRIORITY NVIC_SYSH_PRIORITY_MAX
# define NVIC_SYSH_DISABLE_PRIORITY NVIC_SYSH_MAXNORMAL_PRIORITY
# define NVIC_SYSH_SVCALL_PRIORITY NVIC_SYSH_PRIORITY_MAX
#endif
/************************************************************************************
* Public Types
************************************************************************************/
/************************************************************************************
* Public Data
************************************************************************************/
/************************************************************************************
* Public Functions
************************************************************************************/
#endif /* __ARCH_ARM_INCLUDE_SAMV7_CHIP_H */

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@ -1,114 +0,0 @@
/****************************************************************************************
* arch/arm/include/samv7/irq.h
*
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************************/
/* This file should never be included directed but, rather, only indirectly through
* nuttx/irq.h
*/
#ifndef __ARCH_ARM_INCLUDE_SAMV7_IRQ_H
#define __ARCH_ARM_INCLUDE_SAMV7_IRQ_H
/****************************************************************************************
* Included Files
****************************************************************************************/
#include <nuttx/config.h>
#include <arch/samv7/chip.h>
/****************************************************************************************
* Pre-processor Definitions
****************************************************************************************/
/* IRQ numbers. The IRQ number corresponds vector number and hence map directly to
* bits in the NVIC. This does, however, waste several words of memory in the IRQ
* to handle mapping tables.
*/
/* Common Processor Exceptions (vectors 0-15) */
#define SAM_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG) */
/* Vector 0: Reset stack pointer value */
/* Vector 1: Reset (not handler as an IRQ) */
#define SAM_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */
#define SAM_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */
#define SAM_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */
#define SAM_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */
#define SAM_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */
/* Vectors 7-10: Reserved */
#define SAM_IRQ_SVCALL (11) /* Vector 11: SVC call */
#define SAM_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */
/* Vector 13: Reserved */
#define SAM_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */
#define SAM_IRQ_SYSTICK (15) /* Vector 15: System tick */
/* Chip-Specific External interrupts */
#define SAM_IRQ_EXTINT (16) /* Vector number of the first external interrupt */
#if defined(CONFIG_ARCH_CHIP_SAMV71)
# include <arch/samv7/samv71_irq.h>
#else
# error Unrecognized SAMV7 architecture
#endif
/****************************************************************************************
* Public Types
****************************************************************************************/
#ifndef __ASSEMBLY__
/****************************************************************************************
* Public Data
****************************************************************************************/
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************************
* Public Function Prototypes
****************************************************************************************/
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif
#endif /* __ARCH_ARM_INCLUDE_SAMV7_IRQ_H */

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@ -1,435 +0,0 @@
/****************************************************************************************
* arch/arm/include/samv7/sam4e_irq.h
*
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************************/
/* This file should never be included directed but, rather, only indirectly through
* nuttx/irq.h
*/
#ifndef __ARCH_ARM_INCLUDE_SAMV7_SAMV71_IRQ_H
#define __ARCH_ARM_INCLUDE_SAMV7_SAMV71_IRQ_H
/****************************************************************************************
* Included Files
****************************************************************************************/
/****************************************************************************************
* Pre-processor Definitions
****************************************************************************************/
/* SAMV71 Peripheral Identifiers */
#define SAM_PID_SUPC (0) /* Supply Controller */
#define SAM_PID_RSTC (1) /* Reset Controller */
#define SAM_PID_RTC (2) /* Real Time Clock */
#define SAM_PID_RTT (3) /* Real Time Timer */
#define SAM_PID_WDT0 (4) /* Watchdog Timer 0 */
#define SAM_PID_PMC (5) /* Power Management Controller */
#define SAM_PID_EFC (6) /* Embedded Flash Controller */
#define SAM_PID_UART0 (7) /* Universal Asynchronous Receiver Transmitter 0 */
#define SAM_PID_UART1 (8) /* Universal Asynchronous Receiver Transmitter 1 */
#define SAM_PID_SMC (9) /* Static Memory Controller */
#define SAM_PID_PIOA (10) /* Parallel I/O Controller A */
#define SAM_PID_PIOB (11) /* Parallel I/O Controller B */
#define SAM_PID_PIOC (12) /* Parallel I/O Controller C */
#define SAM_PID_USART0 (13) /* USART 0 */
#define SAM_PID_USART1 (14) /* USART 1 */
#define SAM_PID_USART2 (15) /* USART 2 */
#define SAM_PID_PIOD (16) /* Parallel I/O Controller D */
#define SAM_PID_PIOE (17) /* Parallel I/O Controller E */
#define SAM_PID_HSMCI0 (18) /* High Speed Multimedia Card Interface */
#define SAM_PID_TWIHS0 (19) /* Two-Wire Interface 0 */
#define SAM_PID_TWIHS1 (20) /* Two-Wire Interface 1 */
#define SAM_PID_SPI0 (21) /* Serial Peripheral Interface 0 */
#define SAM_PID_SSC0 (22) /* Synchronous Serial Controller */
#define SAM_PID_TC0 (23) /* Timer Counter 0 */
#define SAM_PID_TC1 (24) /* Timer Counter 1 */
#define SAM_PID_TC2 (25) /* Timer Counter 2 */
#define SAM_PID_TC3 (26) /* Timer Counter 3 */
#define SAM_PID_TC4 (27) /* Timer Counter 4 */
#define SAM_PID_TC5 (28) /* Timer Counter 5 */
#define SAM_PID_AFEC0 (29) /* Analog Front End 0 */
#define SAM_PID_DACC (30) /* Digital to Analog Converter */
#define SAM_PID_PWM0 (31) /* Pulse Width Modulation Controller 0 */
#define SAM_PID_ICM (32) /* Integrity Check Monitor */
#define SAM_PID_ACC (33) /* Analog Comparator */
#define SAM_PID_USBHS (34) /* USB Host / Device Controller */
#define SAM_PID_MCAN00 (35) /* CAN0 IRQ line 0 */
#define SAM_PID_MCAN01 (36) /* CAN0 IRQ line 1 */
#define SAM_PID_MCAN10 (37) /* CAN1 IRQ line 0 */
#define SAM_PID_MCAN11 (38) /* CAN1 IRQ line 1 */
#define SAM_PID_EMAC0 (39) /* Ethernet MAC */
#define SAM_PID_AFEC1 (40) /* Analog Front End 1 */
#define SAM_PID_TWIHS2 (41) /* Two-Wire Interface 2 */
#define SAM_PID_SPI1 (42) /* Serial Peripheral Interface 1 */
#define SAM_PID_QSPI (43) /* Quad I/O Serial Peripheral Interface */
#define SAM_PID_UART2 (44) /* Universal Asynchronous Receiver Transmitter 2 */
#define SAM_PID_UART3 (45) /* Universal Asynchronous Receiver Transmitter 3 */
#define SAM_PID_UART4 (46) /* Universal Asynchronous Receiver Transmitter 4 */
#define SAM_PID_TC6 (47) /* Timer Counter 6 */
#define SAM_PID_TC7 (48) /* Timer Counter 7 */
#define SAM_PID_TC8 (49) /* Timer Counter 8 */
#define SAM_PID_TC9 (50) /* Timer Counter 9 */
#define SAM_PID_TC10 (51) /* Timer Counter 10 */
#define SAM_PID_TC11 (52) /* Timer Counter 11 */
#define SAM_PID_MLB0 (53) /* MediaLB IRQ 0 */
#define SAM_PID_MLB1 (54) /* MediaLB IRQ 1 */
#define SAM_PID_RESERVED55 (55) /* Reserved */
#define SAM_PID_AES (56) /* Advanced Encryption Standard */
#define SAM_PID_TRNG (57) /* True Random Number Generator */
#define SAM_PID_XDMAC (58) /* Central DMA Controller */
#define SAM_PID_ISI (59) /* Image Sensor Interface */
#define SAM_PID_PWM1 (60) /* Pulse Width Modulation Controller 1 */
#define SAM_PID_FPU (61) /* ARM Floating Point Unit interrupt */
#define SAM_PID_SDRAMC (62) /* SDRAM Controller */
#define SAM_PID_WDT1 (63) /* Watchdog Timer 1 */
#define SAM_PID_CCW (64) /* ARM Cache ECC Warning */
#define SAM_PID_CCF (65) /* ARM Cache ECC Fault */
#define SAM_PID_EMACQ1 (66) /* EMAC Queue 1 Interrupt */
#define SAM_PID_EMACQ2 (67) /* EMAC Queue 2 Interrupt */
#define SAM_PID_FPIXC (68) /* ARM Cache ECC Warning */
#define NR_PIDS (69) /* Number of peripheral identifiers */
/* External interrupts (priority levels >= 256*/
#define SAM_IRQ_SUPC (SAM_IRQ_EXTINT+SAM_PID_SUPC) /* Supply Controller */
#define SAM_IRQ_RSTC (SAM_IRQ_EXTINT+SAM_PID_RSTC) /* Reset Controller */
#define SAM_IRQ_RTC (SAM_IRQ_EXTINT+SAM_PID_RTC) /* Real Time Clock */
#define SAM_IRQ_RTT (SAM_IRQ_EXTINT+SAM_PID_RTT) /* Real Time Timer */
#define SAM_IRQ_WDT0 (SAM_IRQ_EXTINT+SAM_PID_WDT0) /* Watchdog Timer 0 */
#define SAM_IRQ_PMC (SAM_IRQ_EXTINT+SAM_PID_PMC) /* Power Management Controller */
#define SAM_IRQ_EEFC0 (SAM_IRQ_EXTINT+SAM_PID_EFC) /* Embedded Flash Controller */
#define SAM_IRQ_UART0 (SAM_IRQ_EXTINT+SAM_PID_UART0) /* Universal Asynchronous Receiver Transmitter 0 */
#define SAM_IRQ_UART1 (SAM_IRQ_EXTINT+SAM_PID_UART1) /* Universal Asynchronous Receiver Transmitter 1 */
#define SAM_IRQ_SMC (SAM_IRQ_EXTINT+SAM_PID_SMC) /* Static Memory Controller */
#define SAM_IRQ_PIOA (SAM_IRQ_EXTINT+SAM_PID_PIOA) /* Parallel I/O Controller A */
#define SAM_IRQ_PIOB (SAM_IRQ_EXTINT+SAM_PID_PIOB) /* Parallel I/O Controller B */
#define SAM_IRQ_PIOC (SAM_IRQ_EXTINT+SAM_PID_PIOC) /* Parallel I/O Controller C */
#define SAM_IRQ_USART0 (SAM_IRQ_EXTINT+SAM_PID_USART0) /* USART 0 */
#define SAM_IRQ_USART1 (SAM_IRQ_EXTINT+SAM_PID_USART1) /* USART 1 */
#define SAM_IRQ_USART2 (SAM_IRQ_EXTINT+SAM_PID_USART2) /* USART 2 */
#define SAM_IRQ_PIOD (SAM_IRQ_EXTINT+SAM_PID_PIOD) /* Parallel I/O Controller D */
#define SAM_IRQ_PIOE (SAM_IRQ_EXTINT+SAM_PID_PIOE) /* Parallel I/O Controller E */
#define SAM_IRQ_HSMCI0 (SAM_IRQ_EXTINT+SAM_PID_HSMCI0) /* High Speed Multimedia Card Interface */
#define SAM_IRQ_TWIHS0 (SAM_IRQ_EXTINT+SAM_PID_TWIHS0) /* Two-Wire Interface 0 */
#define SAM_IRQ_TWIHS1 (SAM_IRQ_EXTINT+SAM_PID_TWIHS1) /* Two-Wire Interface 1 */
#define SAM_IRQ_SPI0 (SAM_IRQ_EXTINT+SAM_PID_SPI0) /* Serial Peripheral Interface 0 */
#define SAM_IRQ_SSC0 (SAM_IRQ_EXTINT+SAM_PID_SSC0) /* Synchronous Serial Controller */
#define SAM_IRQ_TC0 (SAM_IRQ_EXTINT+SAM_PID_TC0) /* Timer Counter 0 */
#define SAM_IRQ_TC1 (SAM_IRQ_EXTINT+SAM_PID_TC1) /* Timer Counter 1 */
#define SAM_IRQ_TC2 (SAM_IRQ_EXTINT+SAM_PID_TC2) /* Timer Counter 2 */
#define SAM_IRQ_TC3 (SAM_IRQ_EXTINT+SAM_PID_TC3) /* Timer Counter 3 */
#define SAM_IRQ_TC4 (SAM_IRQ_EXTINT+SAM_PID_TC4) /* Timer Counter 4 */
#define SAM_IRQ_TC5 (SAM_IRQ_EXTINT+SAM_PID_TC5) /* Timer Counter 5 */
#define SAM_IRQ_AFEC0 (SAM_IRQ_EXTINT+SAM_PID_AFEC0) /* Analog Front End 0 */
#define SAM_IRQ_DACC (SAM_IRQ_EXTINT+SAM_PID_DACC) /* Digital to Analog Converter */
#define SAM_IRQ_PWM0 (SAM_IRQ_EXTINT+SAM_PID_PWM0) /* Pulse Width Modulation Controller 0 */
#define SAM_IRQ_ICM (SAM_IRQ_EXTINT+SAM_PID_ICM) /* Integrity Check Monitor */
#define SAM_IRQ_ACC (SAM_IRQ_EXTINT+SAM_PID_ACC) /* Analog Comparator */
#define SAM_IRQ_USBHS (SAM_IRQ_EXTINT+SAM_PID_USBHS) /* USB Host / Device Controller */
#define SAM_IRQ_MCAN00 (SAM_IRQ_EXTINT+SAM_PID_MCAN00) /* CAN0 IRQ line 0 */
#define SAM_IRQ_MCAN01 (SAM_IRQ_EXTINT+SAM_PID_MCAN01) /* CAN0 IRQ line 1 */
#define SAM_IRQ_MCAN10 (SAM_IRQ_EXTINT+SAM_PID_MCAN10) /* CAN1 IRQ line 0 */
#define SAM_IRQ_MCAN11 (SAM_IRQ_EXTINT+SAM_PID_MCAN11) /* CAN1 IRQ line 1 */
#define SAM_IRQ_EMAC0 (SAM_IRQ_EXTINT+SAM_PID_EMAC0) /* Ethernet MAC */
#define SAM_IRQ_AFEC1 (SAM_IRQ_EXTINT+SAM_PID_AFEC1) /* Analog Front End 1 */
#define SAM_IRQ_TWIHS2 (SAM_IRQ_EXTINT+SAM_PID_TWIHS2) /* Two-Wire Interface 2 */
#define SAM_IRQ_SPI1 (SAM_IRQ_EXTINT+SAM_PID_SPI1) /* Serial Peripheral Interface 1 */
#define SAM_IRQ_QSPI (SAM_IRQ_EXTINT+SAM_PID_QSPI) /* Quad I/O Serial Peripheral Interface */
#define SAM_IRQ_UART2 (SAM_IRQ_EXTINT+SAM_PID_UART2) /* Universal Asynchronous Receiver Transmitter 2 */
#define SAM_IRQ_UART3 (SAM_IRQ_EXTINT+SAM_PID_UART3) /* Universal Asynchronous Receiver Transmitter 3 */
#define SAM_IRQ_UART4 (SAM_IRQ_EXTINT+SAM_PID_UART4) /* Universal Asynchronous Receiver Transmitter 4 */
#define SAM_IRQ_TC6 (SAM_IRQ_EXTINT+SAM_PID_TC6) /* Timer Counter 6 */
#define SAM_IRQ_TC7 (SAM_IRQ_EXTINT+SAM_PID_TC7) /* Timer Counter 7 */
#define SAM_IRQ_TC8 (SAM_IRQ_EXTINT+SAM_PID_TC8) /* Timer Counter 8 */
#define SAM_IRQ_TC9 (SAM_IRQ_EXTINT+SAM_PID_TC9) /* Timer Counter 9 */
#define SAM_IRQ_TC10 (SAM_IRQ_EXTINT+SAM_PID_TC10) /* Timer Counter 10 */
#define SAM_IRQ_TC11 (SAM_IRQ_EXTINT+SAM_PID_TC11) /* Timer Counter 11 */
#define SAM_IRQ_MLB0 (SAM_IRQ_EXTINT+SAM_PID_MLB0) /* MediaLB IRQ 0 */
#define SAM_IRQ_MLB1 (SAM_IRQ_EXTINT+SAM_PID_MLB1) /* MediaLB IRQ 1 */
#define SAM_IRQ_RESERVED55 (SAM_IRQ_EXTINT+SAM_PID_RESERVED55) /* Reserved */
#define SAM_IRQ_AES (SAM_IRQ_EXTINT+SAM_PID_AES) /* AES */
#define SAM_IRQ_TRNG (SAM_IRQ_EXTINT+SAM_PID_TRNG) /* True Random Number Generator */
#define SAM_IRQ_XDMAC (SAM_IRQ_EXTINT+SAM_PID_XDMAC) /* Central DMA Controller */
#define SAM_IRQ_ISI (SAM_IRQ_EXTINT+SAM_PID_ISI) /* Image Sensor Interface */
#define SAM_IRQ_PWM1 (SAM_IRQ_EXTINT+SAM_PID_PWM1) /* Pulse Width Modulation Controller 1 */
#define SAM_IRQ_FPU (SAM_IRQ_EXTINT+SAM_PID_FPU) /* ARM Floating Point Unit interrupt */
#define SAM_IRQ_SDRAMC (SAM_IRQ_EXTINT+SAM_PID_SDRAMC) /* SDRAM Controller */
#define SAM_IRQ_WDT1 (SAM_IRQ_EXTINT+SAM_PID_WDT1) /* Watchdog Timer 1 */
#define SAM_IRQ_CCW (SAM_IRQ_EXTINT+SAM_PID_CCW) /* ARM Cache ECC Warning */
#define SAM_IRQ_CCF (SAM_IRQ_EXTINT+SAM_PID_CCF) /* ARM Cache ECC Fault */
#define SAM_IRQ_EMACQ1 (SAM_IRQ_EXTINT+SAM_PID_EMACQ1) /* EMAC Queue 1 Interrupt */
#define SAM_IRQ_EMACQ2 (SAM_IRQ_EXTINT+SAM_PID_EMACQ2) /* EMAC Queue 2 Interrupt */
#define SAM_IRQ_FPIXC (SAM_IRQ_EXTINTSAM_PID_FPIXC+) /* ARM Cache ECC Warning */
#define SAM_IRQ_NEXTINT NR_PIDS /* Total number of external interrupt numbers */
#define SAM_IRQ_NIRQS (SAM_IRQ_EXTINT+NR_PIDS) /* The number of real IRQs */
/* GPIO interrupts (derived from SAM_IRQ_PIOA..E) */
#ifdef CONFIG_SAMV7_GPIOA_IRQ
# define SAM_IRQ_GPIOA_PINS (SAM_IRQ_EXTINT + SAM_IRQ_NEXTINT)
# define SAM_IRQ_PA0 (SAM_IRQ_GPIOA_PINS+0) /* GPIOA, PIN 0 */
# define SAM_IRQ_PA1 (SAM_IRQ_GPIOA_PINS+1) /* GPIOA, PIN 1 */
# define SAM_IRQ_PA2 (SAM_IRQ_GPIOA_PINS+2) /* GPIOA, PIN 2 */
# define SAM_IRQ_PA3 (SAM_IRQ_GPIOA_PINS+3) /* GPIOA, PIN 3 */
# define SAM_IRQ_PA4 (SAM_IRQ_GPIOA_PINS+4) /* GPIOA, PIN 4 */
# define SAM_IRQ_PA5 (SAM_IRQ_GPIOA_PINS+5) /* GPIOA, PIN 5 */
# define SAM_IRQ_PA6 (SAM_IRQ_GPIOA_PINS+6) /* GPIOA, PIN 6 */
# define SAM_IRQ_PA7 (SAM_IRQ_GPIOA_PINS+7) /* GPIOA, PIN 7 */
# define SAM_IRQ_PA8 (SAM_IRQ_GPIOA_PINS+8) /* GPIOA, PIN 8 */
# define SAM_IRQ_PA9 (SAM_IRQ_GPIOA_PINS+9) /* GPIOA, PIN 9 */
# define SAM_IRQ_PA10 (SAM_IRQ_GPIOA_PINS+10) /* GPIOA, PIN 10 */
# define SAM_IRQ_PA11 (SAM_IRQ_GPIOA_PINS+11) /* GPIOA, PIN 11 */
# define SAM_IRQ_PA12 (SAM_IRQ_GPIOA_PINS+12) /* GPIOA, PIN 12 */
# define SAM_IRQ_PA13 (SAM_IRQ_GPIOA_PINS+13) /* GPIOA, PIN 13 */
# define SAM_IRQ_PA14 (SAM_IRQ_GPIOA_PINS+14) /* GPIOA, PIN 14 */
# define SAM_IRQ_PA15 (SAM_IRQ_GPIOA_PINS+15) /* GPIOA, PIN 15 */
# define SAM_IRQ_PA16 (SAM_IRQ_GPIOA_PINS+16) /* GPIOA, PIN 16 */
# define SAM_IRQ_PA17 (SAM_IRQ_GPIOA_PINS+17) /* GPIOA, PIN 17 */
# define SAM_IRQ_PA18 (SAM_IRQ_GPIOA_PINS+18) /* GPIOA, PIN 18 */
# define SAM_IRQ_PA19 (SAM_IRQ_GPIOA_PINS+19) /* GPIOA, PIN 19 */
# define SAM_IRQ_PA20 (SAM_IRQ_GPIOA_PINS+20) /* GPIOA, PIN 20 */
# define SAM_IRQ_PA21 (SAM_IRQ_GPIOA_PINS+21) /* GPIOA, PIN 21 */
# define SAM_IRQ_PA22 (SAM_IRQ_GPIOA_PINS+22) /* GPIOA, PIN 22 */
# define SAM_IRQ_PA23 (SAM_IRQ_GPIOA_PINS+23) /* GPIOA, PIN 23 */
# define SAM_IRQ_PA24 (SAM_IRQ_GPIOA_PINS+24) /* GPIOA, PIN 24 */
# define SAM_IRQ_PA25 (SAM_IRQ_GPIOA_PINS+25) /* GPIOA, PIN 25 */
# define SAM_IRQ_PA26 (SAM_IRQ_GPIOA_PINS+26) /* GPIOA, PIN 26 */
# define SAM_IRQ_PA27 (SAM_IRQ_GPIOA_PINS+27) /* GPIOA, PIN 27 */
# define SAM_IRQ_PA28 (SAM_IRQ_GPIOA_PINS+28) /* GPIOA, PIN 28 */
# define SAM_IRQ_PA29 (SAM_IRQ_GPIOA_PINS+29) /* GPIOA, PIN 29 */
# define SAM_IRQ_PA30 (SAM_IRQ_GPIOA_PINS+30) /* GPIOA, PIN 30 */
# define SAM_IRQ_PA31 (SAM_IRQ_GPIOA_PINS+31) /* GPIOA, PIN 31 */
# define SAM_NGPIOAIRQS 32
#else
# define SAM_NGPIOAIRQS 0
#endif
#ifdef CONFIG_SAMV7_GPIOB_IRQ
# define SAM_IRQ_GPIOB_PINS (SAM_IRQ_EXTINT + SAM_IRQ_NEXTINT + SAM_NGPIOAIRQS)
# define SAM_IRQ_PB0 (SAM_IRQ_GPIOB_PINS+0) /* GPIOB, PIN 0 */
# define SAM_IRQ_PB1 (SAM_IRQ_GPIOB_PINS+1) /* GPIOB, PIN 1 */
# define SAM_IRQ_PB2 (SAM_IRQ_GPIOB_PINS+2) /* GPIOB, PIN 2 */
# define SAM_IRQ_PB3 (SAM_IRQ_GPIOB_PINS+3) /* GPIOB, PIN 3 */
# define SAM_IRQ_PB4 (SAM_IRQ_GPIOB_PINS+4) /* GPIOB, PIN 4 */
# define SAM_IRQ_PB5 (SAM_IRQ_GPIOB_PINS+5) /* GPIOB, PIN 5 */
# define SAM_IRQ_PB6 (SAM_IRQ_GPIOB_PINS+6) /* GPIOB, PIN 6 */
# define SAM_IRQ_PB7 (SAM_IRQ_GPIOB_PINS+7) /* GPIOB, PIN 7 */
# define SAM_IRQ_PB8 (SAM_IRQ_GPIOB_PINS+8) /* GPIOB, PIN 8 */
# define SAM_IRQ_PB9 (SAM_IRQ_GPIOB_PINS+9) /* GPIOB, PIN 9 */
# define SAM_IRQ_PB10 (SAM_IRQ_GPIOB_PINS+10) /* GPIOB, PIN 10 */
# define SAM_IRQ_PB11 (SAM_IRQ_GPIOB_PINS+11) /* GPIOB, PIN 11 */
# define SAM_IRQ_PB12 (SAM_IRQ_GPIOB_PINS+12) /* GPIOB, PIN 12 */
# define SAM_IRQ_PB13 (SAM_IRQ_GPIOB_PINS+13) /* GPIOB, PIN 13 */
# define SAM_IRQ_PB14 (SAM_IRQ_GPIOB_PINS+14) /* GPIOB, PIN 14 */
# define SAM_IRQ_PB15 (SAM_IRQ_GPIOB_PINS+15) /* GPIOB, PIN 15 */
# define SAM_IRQ_PB16 (SAM_IRQ_GPIOB_PINS+16) /* GPIOB, PIN 16 */
# define SAM_IRQ_PB17 (SAM_IRQ_GPIOB_PINS+17) /* GPIOB, PIN 17 */
# define SAM_IRQ_PB18 (SAM_IRQ_GPIOB_PINS+18) /* GPIOB, PIN 18 */
# define SAM_IRQ_PB19 (SAM_IRQ_GPIOB_PINS+19) /* GPIOB, PIN 19 */
# define SAM_IRQ_PB20 (SAM_IRQ_GPIOB_PINS+20) /* GPIOB, PIN 20 */
# define SAM_IRQ_PB21 (SAM_IRQ_GPIOB_PINS+21) /* GPIOB, PIN 21 */
# define SAM_IRQ_PB22 (SAM_IRQ_GPIOB_PINS+22) /* GPIOB, PIN 22 */
# define SAM_IRQ_PB23 (SAM_IRQ_GPIOB_PINS+23) /* GPIOB, PIN 23 */
# define SAM_IRQ_PB24 (SAM_IRQ_GPIOB_PINS+24) /* GPIOB, PIN 24 */
# define SAM_IRQ_PB25 (SAM_IRQ_GPIOB_PINS+25) /* GPIOB, PIN 25 */
# define SAM_IRQ_PB26 (SAM_IRQ_GPIOB_PINS+26) /* GPIOB, PIN 26 */
# define SAM_IRQ_PB27 (SAM_IRQ_GPIOB_PINS+27) /* GPIOB, PIN 27 */
# define SAM_IRQ_PB28 (SAM_IRQ_GPIOB_PINS+28) /* GPIOB, PIN 28 */
# define SAM_IRQ_PB29 (SAM_IRQ_GPIOB_PINS+29) /* GPIOB, PIN 29 */
# define SAM_IRQ_PB30 (SAM_IRQ_GPIOB_PINS+30) /* GPIOB, PIN 30 */
# define SAM_IRQ_PB31 (SAM_IRQ_GPIOB_PINS+31) /* GPIOB, PIN 31 */
# define SAM_NGPIOBIRQS 32
#else
# define SAM_NGPIOBIRQS 0
#endif
#ifdef CONFIG_SAMV7_GPIOC_IRQ
# define SAM_IRQ_GPIOC_PINS (SAM_IRQ_EXTINT + SAM_IRQ_NEXTINT + SAM_NGPIOAIRQS + SAM_NGPIOBIRQS)
# define SAM_IRQ_PC0 (SAM_IRQ_GPIOC_PINS+0) /* GPIOC, PIN 0 */
# define SAM_IRQ_PC1 (SAM_IRQ_GPIOC_PINS+1) /* GPIOC, PIN 1 */
# define SAM_IRQ_PC2 (SAM_IRQ_GPIOC_PINS+2) /* GPIOC, PIN 2 */
# define SAM_IRQ_PC3 (SAM_IRQ_GPIOC_PINS+3) /* GPIOC, PIN 3 */
# define SAM_IRQ_PC4 (SAM_IRQ_GPIOC_PINS+4) /* GPIOC, PIN 4 */
# define SAM_IRQ_PC5 (SAM_IRQ_GPIOC_PINS+5) /* GPIOC, PIN 5 */
# define SAM_IRQ_PC6 (SAM_IRQ_GPIOC_PINS+6) /* GPIOC, PIN 6 */
# define SAM_IRQ_PC7 (SAM_IRQ_GPIOC_PINS+7) /* GPIOC, PIN 7 */
# define SAM_IRQ_PC8 (SAM_IRQ_GPIOC_PINS+8) /* GPIOC, PIN 8 */
# define SAM_IRQ_PC9 (SAM_IRQ_GPIOC_PINS+9) /* GPIOC, PIN 9 */
# define SAM_IRQ_PC10 (SAM_IRQ_GPIOC_PINS+10) /* GPIOC, PIN 10 */
# define SAM_IRQ_PC11 (SAM_IRQ_GPIOC_PINS+11) /* GPIOC, PIN 11 */
# define SAM_IRQ_PC12 (SAM_IRQ_GPIOC_PINS+12) /* GPIOC, PIN 12 */
# define SAM_IRQ_PC13 (SAM_IRQ_GPIOC_PINS+13) /* GPIOC, PIN 13 */
# define SAM_IRQ_PC14 (SAM_IRQ_GPIOC_PINS+14) /* GPIOC, PIN 14 */
# define SAM_IRQ_PC15 (SAM_IRQ_GPIOC_PINS+15) /* GPIOC, PIN 15 */
# define SAM_IRQ_PC16 (SAM_IRQ_GPIOC_PINS+16) /* GPIOC, PIN 16 */
# define SAM_IRQ_PC17 (SAM_IRQ_GPIOC_PINS+17) /* GPIOC, PIN 17 */
# define SAM_IRQ_PC18 (SAM_IRQ_GPIOC_PINS+18) /* GPIOC, PIN 18 */
# define SAM_IRQ_PC19 (SAM_IRQ_GPIOC_PINS+19) /* GPIOC, PIN 19 */
# define SAM_IRQ_PC20 (SAM_IRQ_GPIOC_PINS+20) /* GPIOC, PIN 20 */
# define SAM_IRQ_PC21 (SAM_IRQ_GPIOC_PINS+21) /* GPIOC, PIN 21 */
# define SAM_IRQ_PC22 (SAM_IRQ_GPIOC_PINS+22) /* GPIOC, PIN 22 */
# define SAM_IRQ_PC23 (SAM_IRQ_GPIOC_PINS+23) /* GPIOC, PIN 23 */
# define SAM_IRQ_PC24 (SAM_IRQ_GPIOC_PINS+24) /* GPIOC, PIN 24 */
# define SAM_IRQ_PC25 (SAM_IRQ_GPIOC_PINS+25) /* GPIOC, PIN 25 */
# define SAM_IRQ_PC26 (SAM_IRQ_GPIOC_PINS+26) /* GPIOC, PIN 26 */
# define SAM_IRQ_PC27 (SAM_IRQ_GPIOC_PINS+27) /* GPIOC, PIN 27 */
# define SAM_IRQ_PC28 (SAM_IRQ_GPIOC_PINS+28) /* GPIOC, PIN 28 */
# define SAM_IRQ_PC29 (SAM_IRQ_GPIOC_PINS+29) /* GPIOC, PIN 29 */
# define SAM_IRQ_PC30 (SAM_IRQ_GPIOC_PINS+30) /* GPIOC, PIN 30 */
# define SAM_IRQ_PC31 (SAM_IRQ_GPIOC_PINS+31) /* GPIOC, PIN 31 */
# define SAM_NGPIOCIRQS 32
#else
# define SAM_NGPIOCIRQS 0
#endif
#ifdef CONFIG_SAMV7_GPIOD_IRQ
# define SAM_IRQ_GPIOD_PINS (SAM_IRQ_EXTINT + SAM_IRQ_NEXTINT + SAM_NGPIOAIRQS + SAM_NGPIOBIRQS)
# define SAM_IRQ_PD0 (SAM_IRQ_GPIOD_PINS+0) /* GPIOD, PIN 0 */
# define SAM_IRQ_PD1 (SAM_IRQ_GPIOD_PINS+1) /* GPIOD, PIN 1 */
# define SAM_IRQ_PD2 (SAM_IRQ_GPIOD_PINS+2) /* GPIOD, PIN 2 */
# define SAM_IRQ_PD3 (SAM_IRQ_GPIOD_PINS+3) /* GPIOD, PIN 3 */
# define SAM_IRQ_PD4 (SAM_IRQ_GPIOD_PINS+4) /* GPIOD, PIN 4 */
# define SAM_IRQ_PD5 (SAM_IRQ_GPIOD_PINS+5) /* GPIOD, PIN 5 */
# define SAM_IRQ_PD6 (SAM_IRQ_GPIOD_PINS+6) /* GPIOD, PIN 6 */
# define SAM_IRQ_PD7 (SAM_IRQ_GPIOD_PINS+7) /* GPIOD, PIN 7 */
# define SAM_IRQ_PD8 (SAM_IRQ_GPIOD_PINS+8) /* GPIOD, PIN 8 */
# define SAM_IRQ_PD9 (SAM_IRQ_GPIOD_PINS+9) /* GPIOD, PIN 9 */
# define SAM_IRQ_PD10 (SAM_IRQ_GPIOD_PINS+10) /* GPIOD, PIN 10 */
# define SAM_IRQ_PD11 (SAM_IRQ_GPIOD_PINS+11) /* GPIOD, PIN 11 */
# define SAM_IRQ_PD12 (SAM_IRQ_GPIOD_PINS+12) /* GPIOD, PIN 12 */
# define SAM_IRQ_PD13 (SAM_IRQ_GPIOD_PINS+13) /* GPIOD, PIN 13 */
# define SAM_IRQ_PD14 (SAM_IRQ_GPIOD_PINS+14) /* GPIOD, PIN 14 */
# define SAM_IRQ_PD15 (SAM_IRQ_GPIOD_PINS+15) /* GPIOD, PIN 15 */
# define SAM_IRQ_PD16 (SAM_IRQ_GPIOD_PINS+16) /* GPIOD, PIN 16 */
# define SAM_IRQ_PD17 (SAM_IRQ_GPIOD_PINS+17) /* GPIOD, PIN 17 */
# define SAM_IRQ_PD18 (SAM_IRQ_GPIOD_PINS+18) /* GPIOD, PIN 18 */
# define SAM_IRQ_PD19 (SAM_IRQ_GPIOD_PINS+19) /* GPIOD, PIN 19 */
# define SAM_IRQ_PD20 (SAM_IRQ_GPIOD_PINS+20) /* GPIOD, PIN 20 */
# define SAM_IRQ_PD21 (SAM_IRQ_GPIOD_PINS+21) /* GPIOD, PIN 21 */
# define SAM_IRQ_PD22 (SAM_IRQ_GPIOD_PINS+22) /* GPIOD, PIN 22 */
# define SAM_IRQ_PD23 (SAM_IRQ_GPIOD_PINS+23) /* GPIOD, PIN 23 */
# define SAM_IRQ_PD24 (SAM_IRQ_GPIOD_PINS+24) /* GPIOD, PIN 24 */
# define SAM_IRQ_PD25 (SAM_IRQ_GPIOD_PINS+25) /* GPIOD, PIN 25 */
# define SAM_IRQ_PD26 (SAM_IRQ_GPIOD_PINS+26) /* GPIOD, PIN 26 */
# define SAM_IRQ_PD27 (SAM_IRQ_GPIOD_PINS+27) /* GPIOD, PIN 27 */
# define SAM_IRQ_PD28 (SAM_IRQ_GPIOD_PINS+28) /* GPIOD, PIN 28 */
# define SAM_IRQ_PD29 (SAM_IRQ_GPIOD_PINS+29) /* GPIOD, PIN 29 */
# define SAM_IRQ_PD30 (SAM_IRQ_GPIOD_PINS+30) /* GPIOD, PIN 30 */
# define SAM_IRQ_PD31 (SAM_IRQ_GPIOD_PINS+31) /* GPIOD, PIN 31 */
# define SAM_NGPIODIRQS 32
#else
# define SAM_NGPIODIRQS 0
#endif
#ifdef CONFIG_SAMV7_GPIOE_IRQ
# define SAM_IRQ_GPIOE_PINS (SAM_IRQ_EXTINT + SAM_IRQ_NEXTINT + SAM_NGPIOAIRQS + SAM_NGPIOBIRQS)
# define SAM_IRQ_PE0 (SAM_IRQ_GPIOE_PINS+0) /* GPIOE, PIN 0 */
# define SAM_IRQ_PE1 (SAM_IRQ_GPIOE_PINS+1) /* GPIOE, PIN 1 */
# define SAM_IRQ_PE2 (SAM_IRQ_GPIOE_PINS+2) /* GPIOE, PIN 2 */
# define SAM_IRQ_PE3 (SAM_IRQ_GPIOE_PINS+3) /* GPIOE, PIN 3 */
# define SAM_IRQ_PE4 (SAM_IRQ_GPIOE_PINS+4) /* GPIOE, PIN 4 */
# define SAM_IRQ_PE5 (SAM_IRQ_GPIOE_PINS+5) /* GPIOE, PIN 5 */
# define SAM_IRQ_PE6 (SAM_IRQ_GPIOE_PINS+6) /* GPIOE, PIN 6 */
# define SAM_IRQ_PE7 (SAM_IRQ_GPIOE_PINS+7) /* GPIOE, PIN 7 */
# define SAM_IRQ_PE8 (SAM_IRQ_GPIOE_PINS+8) /* GPIOE, PIN 8 */
# define SAM_IRQ_PE9 (SAM_IRQ_GPIOE_PINS+9) /* GPIOE, PIN 9 */
# define SAM_IRQ_PE10 (SAM_IRQ_GPIOE_PINS+10) /* GPIOE, PIN 10 */
# define SAM_IRQ_PE11 (SAM_IRQ_GPIOE_PINS+11) /* GPIOE, PIN 11 */
# define SAM_IRQ_PE12 (SAM_IRQ_GPIOE_PINS+12) /* GPIOE, PIN 12 */
# define SAM_IRQ_PE13 (SAM_IRQ_GPIOE_PINS+13) /* GPIOE, PIN 13 */
# define SAM_IRQ_PE14 (SAM_IRQ_GPIOE_PINS+14) /* GPIOE, PIN 14 */
# define SAM_IRQ_PE15 (SAM_IRQ_GPIOE_PINS+15) /* GPIOE, PIN 15 */
# define SAM_IRQ_PE16 (SAM_IRQ_GPIOE_PINS+16) /* GPIOE, PIN 16 */
# define SAM_IRQ_PE17 (SAM_IRQ_GPIOE_PINS+17) /* GPIOE, PIN 17 */
# define SAM_IRQ_PE18 (SAM_IRQ_GPIOE_PINS+18) /* GPIOE, PIN 18 */
# define SAM_IRQ_PE19 (SAM_IRQ_GPIOE_PINS+19) /* GPIOE, PIN 19 */
# define SAM_IRQ_PE20 (SAM_IRQ_GPIOE_PINS+20) /* GPIOE, PIN 20 */
# define SAM_IRQ_PE21 (SAM_IRQ_GPIOE_PINS+21) /* GPIOE, PIN 21 */
# define SAM_IRQ_PE22 (SAM_IRQ_GPIOE_PINS+22) /* GPIOE, PIN 22 */
# define SAM_IRQ_PE23 (SAM_IRQ_GPIOE_PINS+23) /* GPIOE, PIN 23 */
# define SAM_IRQ_PE24 (SAM_IRQ_GPIOE_PINS+24) /* GPIOE, PIN 24 */
# define SAM_IRQ_PE25 (SAM_IRQ_GPIOE_PINS+25) /* GPIOE, PIN 25 */
# define SAM_IRQ_PE26 (SAM_IRQ_GPIOE_PINS+26) /* GPIOE, PIN 26 */
# define SAM_IRQ_PE27 (SAM_IRQ_GPIOE_PINS+27) /* GPIOE, PIN 27 */
# define SAM_IRQ_PE28 (SAM_IRQ_GPIOE_PINS+28) /* GPIOE, PIN 28 */
# define SAM_IRQ_PE29 (SAM_IRQ_GPIOE_PINS+29) /* GPIOE, PIN 29 */
# define SAM_IRQ_PE30 (SAM_IRQ_GPIOE_PINS+30) /* GPIOE, PIN 30 */
# define SAM_IRQ_PE31 (SAM_IRQ_GPIOE_PINS+31) /* GPIOE, PIN 31 */
# define SAM_NGPIOEIRQS 32
#else
# define SAM_NGPIOEIRQS 0
#endif
/* Total number of IRQ numbers */
#define NR_VECTORS SAM_IRQ_NIRQS
#define NR_IRQS (SAM_IRQ_EXTINT + SAM_IRQ_NEXTINT + \
SAM_NGPIOAIRQS + SAM_NGPIOBIRQS + SAM_NGPIOCIRQS + \
SAM_NGPIODIRQS + SAM_NGPIOEIRQS)
/****************************************************************************************
* Public Types
****************************************************************************************/
/****************************************************************************************
* Inline functions
****************************************************************************************/
/****************************************************************************************
* Public Variables
****************************************************************************************/
/****************************************************************************************
* Public Function Prototypes
****************************************************************************************/
#ifndef __ASSEMBLY__
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif
#endif /* __ARCH_ARM_INCLUDE_SAMV7_SAMV71_IRQ_H */

58
arch/arm/include/serial.h
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@ -1,58 +0,0 @@
/****************************************************************************
* arch/arm/include/serial.h
*
* Copyright (C) 2007-2009, 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
#ifndef __ARCH_ARM_INCLUDE_SERIAL_H
#define __ARCH_ARM_INCLUDE_SERIAL_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <sys/types.h>
#include <nuttx/fs/ioctl.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/
#endif /* __ARCH_ARM_INCLUDE_SERIAL_H */

59
arch/arm/include/stdarg.h
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@ -1,59 +0,0 @@
/****************************************************************************
* arch/arm/include/stdarg.h
*
* Copyright (C) 2012 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
#ifndef __ARCH_ARM_INCLUDE_STDARG_H
#define __ARCH_ARM_INCLUDE_STDARG_H
/****************************************************************************
* Included Files
****************************************************************************/
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* This should work with any modern gcc (newer than 3.4 or so) */
#define va_start(v,l) __builtin_va_start(v,l)
#define va_end(v) __builtin_va_end(v)
#define va_arg(v,l) __builtin_va_arg(v,l)
#define va_copy(d,s) __builtin_va_copy(d,s)
/****************************************************************************
* Public Types
****************************************************************************/
typedef __builtin_va_list va_list;
#endif /* __ARCH_ARM_INCLUDE_STDARG_H */

2236
arch/arm/include/stm32/chip.h
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File diff suppressed because it is too large Load diff

415
arch/arm/include/stm32/dma2d.h
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@ -1,415 +0,0 @@
/*******************************************************************************
* arch/arm/src/include/stm32/dma2d.h
*
* Copyright (C) 2015 Marco Krahl. All rights reserved.
* Author: Marco Krahl <ocram.lhark@gmail.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
#ifndef __ARCH_ARM_INCLUDE_STM32_DMA2D_H
#define __ARCH_ARM_INCLUDE_STM32_DMA2D_H
/*******************************************************************************
* Included Files
******************************************************************************/
#include <nuttx/config.h>
#include <stdbool.h>
#include <nuttx/video/fb.h>
/*******************************************************************************
* Pre-processor Definitions
******************************************************************************/
/*******************************************************************************
* Public Types
******************************************************************************/
struct ltdc_area_s; /* see arch/chip/ltdc.h */
/* Blend mode definitions */
enum dma2d_blend_e
{
DMA2D_BLEND_NONE = 0, /* Disable all blend operation */
DMA2D_BLEND_ALPHA = 0x1, /* Enable alpha blending */
DMA2D_BLEND_PIXELALPHA = 0x2, /* Enable alpha blending from pixel color */
};
/* The layer is controlled through the following structure */
struct dma2d_layer_s
{
/* Name: getvideoinfo
*
* Description:
* Get video information about the layer
*
* Parameter:
* layer - Reference to the layer control structure
* vinfo - Reference to the video info structure
*
* Return:
* On success - OK
* On error - -EINVAL
*/
int (*getvideoinfo)(FAR struct dma2d_layer_s *layer,
FAR struct fb_videoinfo_s *vinfo);
/* Name: getplaneinfo
*
* Description:
* Get plane information about the layer
*
* Parameter:
* layer - Reference to the layer control structure
* planeno - Number of the plane
* pinfo - Reference to the plane info structure
*
* Return:
* On success - OK
* On error - -EINVAL
*/
int (*getplaneinfo)(FAR struct dma2d_layer_s *layer, int planeno,
FAR struct fb_planeinfo_s *pinfo);
/* Name: getlid
*
* Description:
* Get a specific layer identifier.
*
* Parameter:
* layer - Reference to the layer structure
* lid - Reference to store the layer id
*
* Return:
* On success - OK
* On error - -EINVAL
*/
int (*getlid)(FAR struct dma2d_layer_s *layer, int *lid);
#ifdef CONFIG_STM32_DMA2D_L8
/* Name: setclut
*
* Description:
* Configure layer clut (color lookup table).
* Non clut is defined during initializing.
*
* Parameter:
* layer - Reference to the layer structure
* cmap - color lookup table with up the 256 entries
*
* Return:
* On success - OK
* On error - -EINVAL
*/
int (*setclut)(FAR struct dma2d_layer_s *layer,
const FAR struct fb_cmap_s *cmap);
/* Name: getclut
*
* Description:
* Get configured layer clut (color lookup table).
*
* Parameter:
* layer - Reference to the layer structure
* cmap - Reference to valid color lookup table accept up the 256 color
* entries
*
* Return:
* On success - OK
* On error - -EINVAL
*/
int (*getclut)(FAR struct dma2d_layer_s *layer, FAR struct fb_cmap_s *cmap);
#endif
/* Name: setalpha
*
* Description:
* Configure layer alpha value factor into blend operation.
* During the layer blend operation the source alpha value is multiplied
* with this alpha value. If the source color format doesn't support alpha
* channel (e.g. non ARGB8888) this alpha value will be used as constant
* alpha value for blend operation.
* Default value during initializing: 0xff
*
* Parameter:
* layer - Reference to the layer structure
* alpha - Alpha value
*
* Return:
* On success - OK
* On error - -EINVAL
*/
int (*setalpha)(FAR struct dma2d_layer_s *layer, uint8_t alpha);
/* Name: getalpha
*
* Description:
* Get configured layer alpha value factor for blend operation.
*
* Parameter:
* layer - Reference to the layer structure
* alpha - Reference to store the alpha value
*
* Return:
* On success - OK
* On error - -EINVAL
*/
int (*getalpha)(FAR struct dma2d_layer_s *layer, uint8_t *alpha);
/* Name: setblendmode
*
* Description:
* Configure blend mode of the layer.
* Default mode during initializing: DMA2D_BLEND_NONE
* Blendmode is active after next update.
*
* Parameter:
* layer - Reference to the layer structure
* mode - Blend mode (see DMA2D_BLEND_*)
*
* Return:
* On success - OK
* On error - -EINVAL
*
* Procedure information:
* DMA2D_BLEND_NONE:
* Informs the driver to disable all blend operation for the given layer.
* That means the layer is opaque.
*
* DMA2D_BLEND_ALPHA:
* Informs the driver to enable alpha blending for the given layer.
*
* DMA2D_BLEND_PIXELALPHA:
* Informs the driver to use the pixel alpha value of the layer instead
* the constant alpha value. This is only useful for ARGB8888
* color format.
*/
int (*setblendmode)(FAR struct dma2d_layer_s *layer, uint32_t mode);
/* Name: getblendmode
*
* Description:
* Get configured blend mode of the layer.
*
* Parameter:
* layer - Reference to the layer structure
* mode - Reference to store the blend mode
*
* Return:
* On success - OK
* On error - -EINVAL
*/
int (*getblendmode)(FAR struct dma2d_layer_s *layer, uint32_t *mode);
/* Name: blit
*
* Description:
* Copy selected area from a source layer to selected position of the
* destination layer.
*
* Parameter:
* dest - Reference to the destination layer
* destxpos - Selected x target position of the destination layer
* destypos - Selected y target position of the destination layer
* src - Reference to the source layer
* srcarea - Reference to the selected area of the source layer
*
* Return:
* OK - On success
* -EINVAL - If one of the parameter invalid or if the size of the
* selected source area outside the visible area of the
* destination layer. (The visible area usually represents the
* display size)
* -ECANCELED - Operation cancelled, something goes wrong.
*/
int (*blit)(FAR struct dma2d_layer_s *dest,
fb_coord_t destxpos, fb_coord_t destypos,
FAR const struct dma2d_layer_s *src,
FAR const struct ltdc_area_s *srcarea);
/* Name: blend
*
* Description:
* Blends the selected area from a background layer with selected position
* of the foreground layer. Copies the result to the selected position of
* the destination layer. Note! The content of the foreground and background
* layer keeps unchanged as long destination layer is unequal to the
* foreground and background layer.
*
* Parameter:
* dest - Reference to the destination layer
* fore - Reference to the foreground layer
* forexpos - Selected x target position of the foreground layer
* foreypos - Selected y target position of the foreground layer
* back - Reference to the background layer
* backarea - Reference to the selected area of the background layer
*
* Return:
* OK - On success
* -EINVAL - If one of the parameter invalid or if the size of the
* selected source area outside the visible area of the
* destination layer. (The visible area usually represents the
* display size)
* -ECANCELED - Operation cancelled, something goes wrong.
*/
int (*blend)(FAR struct dma2d_layer_s *dest,
fb_coord_t destxpos, fb_coord_t destypos,
FAR const struct dma2d_layer_s *fore,
fb_coord_t forexpos, fb_coord_t foreypos,
FAR const struct dma2d_layer_s *back,
FAR const struct ltdc_area_s *backarea);
/* Name: fillarea
*
* Description:
* Fill the selected area of the whole layer with a specific color.
*
* Parameter:
* layer - Reference to the layer structure
* area - Reference to the valid area structure select the area
* color - Color to fill the selected area. Color must be formatted
* according to the layer pixel format.
*
* Return:
* OK - On success
* -EINVAL - If one of the parameter invalid or if the size of the
* selected area outside the visible area of the layer.
* -ECANCELED - Operation cancelled, something goes wrong.
*/
int (*fillarea)(FAR struct dma2d_layer_s *layer,
FAR const struct ltdc_area_s *area,
uint32_t color);
};
/*******************************************************************************
* Public Data
******************************************************************************/
/*******************************************************************************
* Public Functions
******************************************************************************/
/*******************************************************************************
* Name: up_dma2dgetlayer
*
* Description:
* Get a dma2d layer structure by the layer identifier
*
* Parameter:
* lid - Layer identifier
*
* Return:
* Reference to the dma2d layer control structure on success or Null if no
* related exist.
*
******************************************************************************/
FAR struct dma2d_layer_s * up_dma2dgetlayer(int lid);
/******************************************************************************
* Name: up_dma2dcreatelayer
*
* Description:
* Create a new dma2d layer object to interact with the dma2d controller
*
* Parameter:
* width - Layer width
* height - Layer height
* fmt - Pixel format of the layer
*
* Return:
* On success - A valid dma2d layer reference
* On error - NULL and errno is set to
* -EINVAL if one of the parameter is invalid
* -ENOMEM if no memory available or exceeds
* CONFIG_STM32_DMA2D_NLAYERS
*
******************************************************************************/
FAR struct dma2d_layer_s *up_dma2dcreatelayer(fb_coord_t width,
fb_coord_t height,
uint8_t fmt);
/******************************************************************************
* Name: up_dma2dremovelayer
*
* Description:
* Remove and deallocate the dma2d layer
*
* Parameter:
* layer - Reference to the layer to remove
*
* Return:
* On success - OK
* On error - -EINVAL
*
*****************************************************************************/
int up_dma2dremovelayer(FAR struct dma2d_layer_s *layer);
/******************************************************************************
* Name: up_dma2dinitialize
*
* Description:
* Initialize the dma2d controller
*
* Return:
* OK - On success
* An error if initializing failed.
*
******************************************************************************/
int up_dma2dinitialize(void);
/******************************************************************************
* Name: up_dma2duninitialize
*
* Description:
* Uninitialize the dma2d controller
*
******************************************************************************/
void up_dma2duninitialize(void);
#endif /* __ARCH_ARM_INCLUDE_STM32_DMA2D_H */

128
arch/arm/include/stm32/irq.h
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@ -1,128 +0,0 @@
/************************************************************************************
* arch/arm/include/stm32s/irq.h
*
* Copyright (C) 2009, 2012 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
/* This file should never be included directed but, rather,
* only indirectly through nuttx/irq.h
*/
#ifndef __ARCH_ARM_INCLUDE_STM32_IRQ_H
#define __ARCH_ARM_INCLUDE_STM32_IRQ_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include <nuttx/irq.h>
#include <arch/stm32/chip.h>
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* IRQ numbers. The IRQ number corresponds vector number and hence map directly to
* bits in the NVIC. This does, however, waste several words of memory in the IRQ
* to handle mapping tables.
*/
/* Processor Exceptions (vectors 0-15) */
#define STM32_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG) */
/* Vector 0: Reset stack pointer value */
/* Vector 1: Reset (not handler as an IRQ) */
#define STM32_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */
#define STM32_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */
#define STM32_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */
#define STM32_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */
#define STM32_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */
#define STM32_IRQ_SVCALL (11) /* Vector 11: SVC call */
#define STM32_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */
/* Vector 13: Reserved */
#define STM32_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */
#define STM32_IRQ_SYSTICK (15) /* Vector 15: System tick */
/* External interrupts (vectors >= 16). These definitions are chip-specific */
#define STM32_IRQ_FIRST (16) /* Vector number of the first external interrupt */
#if defined(CONFIG_STM32_STM32L15XX)
# include <arch/stm32/stm32l15xxx_irq.h>
#elif defined(CONFIG_STM32_STM32F10XX)
# include <arch/stm32/stm32f10xxx_irq.h>
#elif defined(CONFIG_STM32_STM32F20XX)
# include <arch/stm32/stm32f20xxx_irq.h>
#elif defined(CONFIG_STM32_STM32F30XX)
# include <arch/stm32/stm32f30xxx_irq.h>
#elif defined(CONFIG_STM32_STM32F37XX)
# include <arch/stm32/stm32f37xxx_irq.h>
#elif defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429)
# include <arch/stm32/stm32f42xxx_irq.h>
#elif defined(CONFIG_STM32_STM32F446)
# include <arch/stm32/stm32f44xxx_irq.h>
#elif defined(CONFIG_STM32_STM32F40XX)
# include <arch/stm32/stm32f40xxx_irq.h>
#else
# error "Unsupported STM32 chip"
#endif
/************************************************************************************
* Public Types
************************************************************************************/
/************************************************************************************
* Public Data
************************************************************************************/
#ifndef __ASSEMBLY__
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/************************************************************************************
* Public Functions
************************************************************************************/
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif
#endif /* __ARCH_ARM_INCLUDE_STM32_IRQ_H */

592
arch/arm/include/stm32/ltdc.h
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@ -1,592 +0,0 @@
/*******************************************************************************
* arch/arm/src/include/stm32/ltdc.h
*
* Copyright (C) 2014-2015 Marco Krahl. All rights reserved.
* Author: Marco Krahl <ocram.lhark@gmail.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
#ifndef __ARCH_ARM_INCLUDE_STM32_LTDC_H
#define __ARCH_ARM_INCLUDE_STM32_LTDC_H
/*******************************************************************************
* Included Files
******************************************************************************/
#include <nuttx/config.h>
#include <stdbool.h>
#include <nuttx/video/fb.h>
#ifdef CONFIG_STM32_LTDC
/*******************************************************************************
* Pre-processor Definitions
******************************************************************************/
/*******************************************************************************
* Public Types
******************************************************************************/
struct dma2d_layer_s; /* see arch/chip/dma2d.h */
/* Blend mode definitions */
enum ltdc_blend_e
{
LTDC_BLEND_NONE = 0, /* Disable all blend operation */
LTDC_BLEND_ALPHA = 0x1, /* Enable alpha blending */
LTDC_BLEND_PIXELALPHA = 0x2, /* Enable alpha blending from pixel color */
LTDC_BLEND_COLORKEY = 0x4, /* Enable colorkey */
LTDC_BLEND_ALPHAINV = 0x8, /* Inverse alpha blending of source */
LTDC_BLEND_PIXELALPHAINV = 0x10 /* Invers pixel alpha blending of source */
};
/* layer control definitions */
enum ltdc_layer_e
{
LTDC_LAYER_OWN = 0, /* The given layer */
LTDC_LAYER_TOP = 0x1, /* The initialized top layer */
LTDC_LAYER_BOTTOM = 0x2, /* the initialized bottom layer */
LTDC_LAYER_ACTIVE = 0x4, /* The current visible flip layer */
LTDC_LAYER_INACTIVE = 0x8 /* The current invisible flip layer */
#ifdef CONFIG_STM32_DMA2D
,LTDC_LAYER_DMA2D = 0x10 /* The dma2d interface layer id */
#endif
};
/* Update operation flag */
enum ltdc_update_e
{
LTDC_UPDATE_NONE = 0, /* Update given layer only */
LTDC_UPDATE_SIM = 0x1, /* Update both layer simultaneous */
LTDC_UPDATE_FLIP = 0x2, /* Perform flip operation */
LTDC_UPDATE_ACTIVATE = 0x4 /* Set the given layer to the active layer */
};
/* sync mode definitions */
enum ltdc_sync_e
{
LTDC_SYNC_NONE = 0, /* Immediately */
LTDC_SYNC_VBLANK = 0x100, /* Upon vertical sync */
LTDC_SYNC_WAIT = 0x200 /* Waits upon vertical sync */
};
/* Definition of the visible layer position and size */
struct ltdc_area_s
{
fb_coord_t xpos; /* X position in pixel */
fb_coord_t ypos; /* Y position in pixel */
fb_coord_t xres; /* X resolution in pixel */
fb_coord_t yres; /* Y resolution in pixel */
};
/* The layer is controlled through the following structure */
struct ltdc_layer_s
{
/*
* Name: getvideoinfo
*
* Description:
* Get video information about the layer
*
* Parameter:
* layer - Reference to the layer control structure
* vinfo - Reference to the video info structure
*
* Return:
* On success - OK
* On error - -EINVAL
*
*/
int (*getvideoinfo)(FAR struct ltdc_layer_s *layer,
FAR struct fb_videoinfo_s *vinfo);
/*
* Name: getplaneinfo
*
* Description:
* Get plane information about the layer
*
* Parameter:
* layer - Reference to the layer control structure
* planeno - Number of the plane
* pinfo - Reference to the plane info structure
*
* Return:
* On success - OK
* On error - -EINVAL
*
*/
int (*getplaneinfo)(FAR struct ltdc_layer_s *layer, int planeno,
FAR struct fb_planeinfo_s *pinfo);
/*
* Name: getlid
*
* Description:
* Get a specific layer identifier.
*
* Parameter:
* layer - Reference to the layer structure
* lid - Reference to store the layer id
* flag - Operation flag describe the layer identifier
* e.g. get the current active or inactive layer.
* See LTDC_LAYER_* for possible values
*
* Return:
* On success - OK
* On error - -EINVAL
*
*/
int (*getlid)(FAR struct ltdc_layer_s *layer, int *lid, uint32_t flag);
#ifdef CONFIG_FB_CMAP
/*
* Name: setclut
*
* Description:
* Configure layer clut (color lookup table).
* Non clut is defined during initializing.
* Clut is active during next vertical blank period. Do not need an update.
*
* Parameter:
* layer - Reference to the layer structure
* cmap - color lookup table with up the 256 entries
* enable - Enable or disable clut support (if false cmap is ignored and can
* be NULL)
*
* Return:
* On success - OK
* On error - -EINVAL
*
*/
int (*setclut)(FAR struct ltdc_layer_s *layer,
const FAR struct fb_cmap_s *cmap);
/*
* Name: getclut
*
* Description:
* Get configured layer clut (color lookup table).
*
* Parameter:
* layer - Reference to the layer structure
* cmap - Reference to valid color lookup table accept up the 256 color
* entries
*
* Return:
* On success - OK
* On error - -EINVAL
*
*/
int (*getclut)(FAR struct ltdc_layer_s *layer, FAR struct fb_cmap_s *cmap);
#endif
/*
* Name: setcolor
*
* Description:
* Configure layer color for the non active layer area.
* Default value during initializing: 0x00000000
* Color is active after next update.
*
* Parameter:
* layer - Reference to the layer structure
* argb - ARGB8888 color value
*
* Return:
* On success - OK
* On error - -EINVAL
*
*/
int (*setcolor)(FAR struct ltdc_layer_s *layer, uint32_t argb);
/*
* Name: getcolor
*
* Description:
* Get configured layer color for the non active layer area.
*
* Parameter:
* layer - Reference to the layer structure
* argb - Reference to store the ARGB8888 color value
*
* Return:
* On success - OK
* On error - -EINVAL
*
*/
int (*getcolor)(FAR struct ltdc_layer_s *layer, uint32_t *argb);
/*
* Name: setcolorkey
*
* Description:
* Configure the layer color key (chromakey) for transparence.
* Default value during initializing: 0x00000000
* Colorkey is active after next update.
*
* Parameter:
* layer - Reference to the layer structure
* rgb - RGB888 color key
*
* Return:
* On success - OK
* On error - -EINVAL
*
*/
int (*setcolorkey)(FAR struct ltdc_layer_s *layer, uint32_t rgb);
/*
* Name: getcolorkey
*
* Description:
* Get the configured layer color key (chromakey) for transparence.
*
* Parameter:
* layer - Reference to the layer structure
* rgb - Reference to store the RGB888 color key
*
* Return:
* On success - OK
* On error - -EINVAL
*
*/
int (*getcolorkey)(FAR struct ltdc_layer_s *layer, uint32_t *rgb);
/*
* Name: setalpha
*
* Description:
* Configure layer alpha value factor into blend operation.
* During the layer blend operation the source alpha value is multiplied
* with this alpha value. If the source color format doesn't support alpha
* channel (e.g. non ARGB8888) this alpha value will be used as constant
* alpha value for blend operation.
* Default value during initializing: 0xff
* Alpha is active after next update.
*
* Parameter:
* layer - Reference to the layer structure
* alpha - Alpha value
*
* Return:
* On success - OK
* On error - -EINVAL
*
*/
int (*setalpha)(FAR struct ltdc_layer_s *layer, uint8_t alpha);
/*
* Name: getalpha
*
* Description:
* Get configured layer alpha value factor for blend operation.
*
* Parameter:
* layer - Reference to the layer structure
* alpha - Reference to store the alpha value
*
* Return:
* On success - OK
* On error - -EINVAL
*
*/
int (*getalpha)(FAR struct ltdc_layer_s *layer, uint8_t *alpha);
/*
* Name: setblendmode
*
* Description:
* Configure blend mode of the layer.
* Default mode during initializing: LTDC_BLEND_NONE
* Blendmode is active after next update.
*
* Parameter:
* layer - Reference to the layer structure
* mode - Blend mode (see LTDC_BLEND_*)
*
* Return:
* On success - OK
* On error - -EINVAL
*
* Procedure information:
* LTDC_BLEND_NONE:
* Informs the driver to disable all blend operation for the given layer.
* That means the layer is opaque. Note this has no effect on the
* colorkey settings.
*
* LTDC_BLEND_ALPHA:
* Informs the driver to enable alpha blending for the given layer.
*
* LTDC_BLEND_COLORKEY:
* Informs the driver to enable colorkeying for the given layer.
*
* LTDC_BLEND_SRCPIXELALPHA:
* Informs the driver to use the pixel alpha value of the layer instead
* the constant alpha value. This is only useful for ARGB8888
* color format.
*
* LTDC_BLEND_DESTPIXELALPHA:
* Informs the driver to use the pixel alpha value of the subjacent layer
* instead the constant alpha value. This is only useful for ARGB8888
* color format.
*
*/
int (*setblendmode)(FAR struct ltdc_layer_s *layer, uint32_t mode);
/*
* Name: getblendmode
*
* Description:
* Get configured blend mode of the layer.
*
* Parameter:
* layer - Reference to the layer structure
* mode - Reference to store the blend mode
*
* Return:
* On success - OK
* On error - -EINVAL
*
*/
int (*getblendmode)(FAR struct ltdc_layer_s *layer, uint32_t *mode);
/*
* Name: setarea
*
* Description:
* Configure visible layer area and the reference position of the first
* pixel of the whole layer which is the first visible top left pixel in
* the active area.
* Default value during initializing:
* xpos = 0
* ypos = 0
* xres = display x resolution
* yres = display y resolution
*
* Area is active after next update.
*
* Parameter:
* layer - Reference to the layer control structure
* area - Reference to the valid area structure for the new active area
* srcxpos - x position of the visible pixel of the whole layer
* srcypos - y position of the visible pixel of the whole layer
*
* Return:
* On success - OK
* On error - -EINVAL
*
* Procedure Information:
* If the srcxpos and srcypos unequal the the xpos and ypos of the coord
* structure this acts like moving the visible area to another position on
* the screen during the next update operation.
*
*/
int (*setarea)(FAR struct ltdc_layer_s *layer,
FAR const struct ltdc_area_s *area,
fb_coord_t srcxpos,
fb_coord_t srcypos);
/*
* Name: getarea
*
* Description:
* Get configured visible layer area.
*
* Parameter:
* layer - Reference to the layer control structure
* area - Reference to the area structure to store the active area
* srcxpos - Reference to store the referenced x position of the whole layer
* srcypos - Reference to store the reterenced y position of the whole layer
*
* Return:
* On success - OK
* On error - -EINVAL
*
*/
int (*getarea)(FAR struct ltdc_layer_s *layer,
FAR struct ltdc_area_s *area,
fb_coord_t *srcxpos,
fb_coord_t *srcypos);
/*
* Name: update
*
* Description:
* Update current layer settings and make changes visible.
*
* Parameter:
* layer - Reference to the layer structure
* mode - operation mode (see LTDC_UPDATE_*)
*
* Return:
* OK - On success
* -EINVAL - If one of the parameter invalid
* -ECANCELED - Operation cancelled, something goes wrong
*
* Procedure information:
* LTDC_UPDATE_SIM:
* Informs the driver to update both ltdc layers simultaneously. Otherwise
* update the given layer only.
*
* LTDC_UPDATE_FLIP:
* Informs the driver to perform a flip operation.
* This only effects the ltdc layer 1 and 2 and can be useful for double
* buffering. Each flip operation changed the active layer ot the inactive
* and vice versa. In the context of the ltdc that means, the inactive layer
* is complete disabled. So the subjacent layer is the background layer
* (background color). To reactivate both layer and their settings perform
* an update without LTDC_UPDATE_FLIP flag.
*
* LTDC_UPDATE_ACTIVATE:
* Informs the driver that the given layer should be the active layer when
* the operation is complete.
*
* LTDC_SYNC_VBLANK:
* Informs the driver to update the layer upon vertical blank. Otherwise
* immediately.
*
*/
int (*update)(FAR struct ltdc_layer_s *layer, uint32_t mode);
#ifdef CONFIG_STM32_DMA2D
/*
* Name: blit
*
* Description:
* Copy selected area from a source layer to selected position of the
* destination layer.
*
* Parameter:
* dest - Reference to the destination layer
* destxpos - Selected x position of the destination layer
* destypos - Selected y position of the destination layer
* src - Reference to the source layer
* srcarea - Reference to the selected area of the source layer
*
* Return:
* OK - On success
* -EINVAL - If one of the parameter invalid or if the size of the selected
* source area outside the visible area of the destination layer.
* (The visible area usually represents the display size)
*
*/
int (*blit)(FAR struct ltdc_layer_s *dest,
fb_coord_t destxpos, fb_coord_t destypos,
FAR const struct dma2d_layer_s *src,
FAR const struct ltdc_area_s *srcarea);
/*
*
* Name: blend
*
* Description:
* Blends the selected area from a foreground layer with selected position
* of the background layer. Copy the result to the destination layer. Note!
* The content of the foreground and background layer is not changed.
*
* Parameter:
* dest - Reference to the destination layer
* destxpos - Selected x position of the destination layer
* destypos - Selected y position of the destination layer
* fore - Reference to the foreground layer
* forexpos - Selected x position of the foreground layer
* foreypos - Selected y position of the foreground layer
* back - Reference to the background layer
* backarea - Reference to the selected area of the background layer
*
* Return:
* OK - On success
* -EINVAL - If one of the parameter invalid or if the size of the selected
* source area outside the visible area of the destination layer.
* (The visible area usually represents the display size)
*
*/
int (*blend)(FAR struct ltdc_layer_s *dest,
fb_coord_t destxpos, fb_coord_t destypos,
FAR const struct dma2d_layer_s *fore,
fb_coord_t forexpos, fb_coord_t foreypos,
FAR const struct dma2d_layer_s *back,
FAR const struct ltdc_area_s *backarea);
/*
* Name: fillarea
*
* Description:
* Fill the selected area of the whole layer with a specific color.
*
* Parameter:
* layer - Reference to the layer structure
* area - Reference to the valid area structure select the area
* color - Color to fill the selected area. Color must be formatted
* according to the layer pixel format.
*
* Return:
* OK - On success
* -EINVAL - If one of the parameter invalid or if the size of the selected
* area outside the visible area of the layer.
*
*/
int (*fillarea)(FAR struct ltdc_layer_s *layer,
FAR const struct ltdc_area_s *area,
uint32_t color);
#endif
};
/*******************************************************************************
* Public Data
******************************************************************************/
/*******************************************************************************
* Public Functions
******************************************************************************/
/*******************************************************************************
* Name: up_ltdcgetlayer
*
* Description:
* Get the ltdc layer structure to perform hardware layer operation
*
* Parameter:
* lid - Layer identifier
*
* Return:
* Reference to the layer control structure on success or Null if parameter
* invalid.
*
******************************************************************************/
FAR struct ltdc_layer_s *up_ltdcgetlayer(int lid);
#endif /* CONFIG_STM32_LTDC */
#endif /* __ARCH_ARM_INCLUDE_STM32_LTDC_H */

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arch/arm/include/stm32/stm32f10xxx_irq.h
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@ -1,313 +0,0 @@
/************************************************************************************
* arch/arm/include/stm32s/stm32f10xxx_irq.h
*
* Copyright (C) 2009, 2012 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
/* This file should never be included directed but, rather,
* only indirectly through nuttx/irq.h
*/
#ifndef __ARCH_ARM_INCLUDE_STM32_STM32F10XXX_IRQ_H
#define __ARCH_ARM_INCLUDE_STM32_STM32F10XXX_IRQ_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include <nuttx/irq.h>
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* IRQ numbers. The IRQ number corresponds vector number and hence map directly to
* bits in the NVIC. This does, however, waste several words of memory in the IRQ
* to handle mapping tables.
*
* Processor Exceptions (vectors 0-15). These common definitions can be found
* in nuttx/arch/arm/include/stm32/irq.h
*
* External interrupts (vectors >= 16)
*/
/* Value line devices */
#if defined(CONFIG_STM32_VALUELINE)
# define STM32_IRQ_WWDG (16) /* 0: Window Watchdog interrupt */
# define STM32_IRQ_PVD (17) /* 1: PVD through EXTI Line detection interrupt */
# define STM32_IRQ_TAMPER (18) /* 2: Tamper interrupt */
# define STM32_IRQ_RTC (19) /* 3: RTC Wakeup through EXTI line interrupt */
# define STM32_IRQ_FLASH (20) /* 4: Flash global interrupt */
# define STM32_IRQ_RCC (21) /* 5: RCC global interrupt */
# define STM32_IRQ_EXTI0 (22) /* 6: EXTI Line 0 interrupt */
# define STM32_IRQ_EXTI1 (23) /* 7: EXTI Line 1 interrupt */
# define STM32_IRQ_EXTI2 (24) /* 8: EXTI Line 2 interrupt */
# define STM32_IRQ_EXTI3 (25) /* 9: EXTI Line 3 interrupt */
# define STM32_IRQ_EXTI4 (26) /* 10: EXTI Line 4 interrupt */
# define STM32_IRQ_DMA1CH1 (27) /* 11: DMA1 Channel 1 global interrupt */
# define STM32_IRQ_DMA1CH2 (28) /* 12: DMA1 Channel 2 global interrupt */
# define STM32_IRQ_DMA1CH3 (29) /* 13: DMA1 Channel 3 global interrupt */
# define STM32_IRQ_DMA1CH4 (30) /* 14: DMA1 Channel 4 global interrupt */
# define STM32_IRQ_DMA1CH5 (31) /* 15: DMA1 Channel 5 global interrupt */
# define STM32_IRQ_DMA1CH6 (32) /* 16: DMA1 Channel 6 global interrupt */
# define STM32_IRQ_DMA1CH7 (33) /* 17: DMA1 Channel 7 global interrupt */
# define STM32_IRQ_ADC1 (34) /* 18: ADC1 global interrupt */
# define STM32_IRQ_RESERVED0 (35) /* 19: Reserved 0 */
# define STM32_IRQ_RESERVED1 (36) /* 20: Reserved 1 */
# define STM32_IRQ_RESERVED2 (37) /* 21: Reserved 2 */
# define STM32_IRQ_RESERVED3 (38) /* 22: Reserved 3 */
# define STM32_IRQ_EXTI95 (39) /* 23: EXTI Line[9:5] interrupts */
# define STM32_IRQ_TIM1BRK (40) /* 24: TIM1 Break interrupt */
# define STM32_IRQ_TIM15 (40) /* TIM15 global interrupt */
# define STM32_IRQ_TIM1UP (41) /* 25: TIM1 Update interrupt */
# define STM32_IRQ_TIM16 (41) /* TIM16 global interrupt */
# define STM32_IRQ_TIM1TRGCOM (42) /* 26: TIM1 Trigger and Commutation interrupts */
# define STM32_IRQ_TIM17 (42) /* TIM17 global interrupt */
# define STM32_IRQ_TIM1CC (43) /* 27: TIM1 Capture Compare interrupt */
# define STM32_IRQ_TIM2 (44) /* 28: TIM2 global interrupt */
# define STM32_IRQ_TIM3 (45) /* 29: TIM3 global interrupt */
# define STM32_IRQ_TIM4 (46) /* 30: TIM4 global interrupt */
# define STM32_IRQ_I2C1EV (47) /* 31: I2C1 event interrupt */
# define STM32_IRQ_I2C1ER (48) /* 32: I2C1 error interrupt */
# define STM32_IRQ_I2C2EV (49) /* 33: I2C2 event interrupt */
# define STM32_IRQ_I2C2ER (50) /* 34: I2C2 error interrupt */
# define STM32_IRQ_SPI1 (51) /* 35: SPI1 global interrupt */
# define STM32_IRQ_SPI2 (52) /* 36: SPI2 global interrupt */
# define STM32_IRQ_USART1 (53) /* 37: USART1 global interrupt */
# define STM32_IRQ_USART2 (54) /* 38: USART2 global interrupt */
# define STM32_IRQ_USART3 (55) /* 39: USART3 global interrupt */
# define STM32_IRQ_EXTI1510 (56) /* 40: EXTI Line[15:10] interrupts */
# define STM32_IRQ_RTCALR (57) /* 41: RTC alarms (A and B) through EXTI line interrupt */
# define STM32_IRQ_CEC (58) /* 42: CEC global interrupt */
# define STM32_IRQ_TIM12 (59) /* 43: TIM12 global interrupt */
# define STM32_IRQ_TIM13 (60) /* 44: TIM13 global interrupt */
# define STM32_IRQ_TIM14 (61) /* 45: TIM14 global interrupt */
# define STM32_IRQ_RESERVED4 (62) /* 46: Reserved 4 */
# define STM32_IRQ_RESERVED5 (63) /* 47: Reserved 5 */
# define STM32_IRQ_FSMC (64) /* 48: FSMC global interrupt */
# define STM32_IRQ_RESERVED6 (65) /* 49: Reserved 6 */
# define STM32_IRQ_TIM5 (66) /* 50: TIM5 global interrupt */
# define STM32_IRQ_SPI3 (67) /* 51: SPI3 global interrupt */
# define STM32_IRQ_UART4 (68) /* 52: USART2 global interrupt */
# define STM32_IRQ_UART5 (69) /* 53: USART5 global interrupt */
# define STM32_IRQ_TIM6 (70) /* 54: TIM6 global interrupt */
# define STM32_IRQ_TIM7 (71) /* 55: TIM7 global interrupt */
# define STM32_IRQ_DMA2CH1 (72) /* 56: DMA2 Channel 1 global interrupt */
# define STM32_IRQ_DMA2CH2 (73) /* 57: DMA2 Channel 2 global interrupt */
# define STM32_IRQ_DMA2CH3 (74) /* 58: DMA2 Channel 3 global interrupt */
# define STM32_IRQ_DMA2CH45 (75) /* 59: DMA2 Channel 4 and 5 global interrupt */
# define STM32_IRQ_DMA2CH5 (76) /* 60: DMA2 Channel 5 global interrupt */
# define NR_VECTORS (77)
# define NR_IRQS (77)
/* Connectivity Line Devices */
#elif defined(CONFIG_STM32_CONNECTIVITYLINE)
# define STM32_IRQ_WWDG (16) /* 0: Window Watchdog interrupt */
# define STM32_IRQ_PVD (17) /* 1: PVD through EXTI Line detection interrupt */
# define STM32_IRQ_TAMPER (18) /* 2: Tamper interrupt */
# define STM32_IRQ_RTC (19) /* 3: RTC global interrupt */
# define STM32_IRQ_FLASH (20) /* 4: Flash global interrupt */
# define STM32_IRQ_RCC (21) /* 5: RCC global interrupt */
# define STM32_IRQ_EXTI0 (22) /* 6: EXTI Line 0 interrupt */
# define STM32_IRQ_EXTI1 (23) /* 7: EXTI Line 1 interrupt */
# define STM32_IRQ_EXTI2 (24) /* 8: EXTI Line 2 interrupt */
# define STM32_IRQ_EXTI3 (25) /* 9: EXTI Line 3 interrupt */
# define STM32_IRQ_EXTI4 (26) /* 10: EXTI Line 4 interrupt */
# define STM32_IRQ_DMA1CH1 (27) /* 11: DMA1 Channel 1 global interrupt */
# define STM32_IRQ_DMA1CH2 (28) /* 12: DMA1 Channel 2 global interrupt */
# define STM32_IRQ_DMA1CH3 (29) /* 13: DMA1 Channel 3 global interrupt */
# define STM32_IRQ_DMA1CH4 (30) /* 14: DMA1 Channel 4 global interrupt */
# define STM32_IRQ_DMA1CH5 (31) /* 15: DMA1 Channel 5 global interrupt */
# define STM32_IRQ_DMA1CH6 (32) /* 16: DMA1 Channel 6 global interrupt */
# define STM32_IRQ_DMA1CH7 (33) /* 17: DMA1 Channel 7 global interrupt */
# define STM32_IRQ_ADC12 (34) /* 18: ADC1 and ADC2 global interrupt */
# define STM32_IRQ_CAN1TX (35) /* 19: CAN1 TX interrupts */
# define STM32_IRQ_CAN1RX0 (36) /* 20: CAN1 RX0 interrupts */
# define STM32_IRQ_CAN1RX1 (37) /* 21: CAN1 RX1 interrupt */
# define STM32_IRQ_CAN1SCE (38) /* 22: CAN1 SCE interrupt */
# define STM32_IRQ_EXTI95 (39) /* 23: EXTI Line[9:5] interrupts */
# define STM32_IRQ_TIM1BRK (40) /* 24: TIM1 Break interrupt */
# define STM32_IRQ_TIM1UP (41) /* 25: TIM1 Update interrupt */
# define STM32_IRQ_TIM1TRGCOM (42) /* 26: TIM1 Trigger and Commutation interrupts */
# define STM32_IRQ_TIM1CC (43) /* 27: TIM1 Capture Compare interrupt */
# define STM32_IRQ_TIM2 (44) /* 28: TIM2 global interrupt */
# define STM32_IRQ_TIM3 (45) /* 29: TIM3 global interrupt */
# define STM32_IRQ_TIM4 (46) /* 30: TIM4 global interrupt */
# define STM32_IRQ_I2C1EV (47) /* 31: I2C1 event interrupt */
# define STM32_IRQ_I2C1ER (48) /* 32: I2C1 error interrupt */
# define STM32_IRQ_I2C2EV (49) /* 33: I2C2 event interrupt */
# define STM32_IRQ_I2C2ER (50) /* 34: I2C2 error interrupt */
# define STM32_IRQ_SPI1 (51) /* 35: SPI1 global interrupt */
# define STM32_IRQ_SPI2 (52) /* 36: SPI2 global interrupt */
# define STM32_IRQ_USART1 (53) /* 37: USART1 global interrupt */
# define STM32_IRQ_USART2 (54) /* 38: USART2 global interrupt */
# define STM32_IRQ_USART3 (55) /* 39: USART3 global interrupt */
# define STM32_IRQ_EXTI1510 (56) /* 40: EXTI Line[15:10] interrupts */
# define STM32_IRQ_RTCALRM (57) /* 41: RTC alarm through EXTI line interrupt */
# define STM32_IRQ_OTGFSWKUP (58) /* 42: USB On-The-Go FS Wakeup through EXTI line interrupt */
# define STM32_IRQ_RESERVED0 (59) /* 43: Reserved 0 */
# define STM32_IRQ_RESERVED1 (60) /* 44: Reserved 1 */
# define STM32_IRQ_RESERVED2 (61) /* 45: Reserved 2 */
# define STM32_IRQ_RESERVED3 (62) /* 46: Reserved 3 */
# define STM32_IRQ_RESERVED4 (63) /* 47: Reserved 4 */
# define STM32_IRQ_RESERVED5 (64) /* 48: Reserved 5 */
# define STM32_IRQ_RESERVED6 (65) /* 49: Reserved 6 */
# define STM32_IRQ_TIM5 (66) /* 50: TIM5 global interrupt */
# define STM32_IRQ_SPI3 (67) /* 51: SPI3 global interrupt */
# define STM32_IRQ_UART4 (68) /* 52: UART4 global interrupt */
# define STM32_IRQ_UART5 (69) /* 53: UART5 global interrupt */
# define STM32_IRQ_TIM6 (70) /* 54: TIM6 global interrupt */
# define STM32_IRQ_TIM7 (71) /* 55: TIM7 global interrupt */
# define STM32_IRQ_DMA2CH1 (72) /* 56: DMA2 Channel 1 global interrupt */
# define STM32_IRQ_DMA2CH2 (73) /* 57: DMA2 Channel 2 global interrupt */
# define STM32_IRQ_DMA2CH3 (74) /* 58: DMA2 Channel 3 global interrupt */
# define STM32_IRQ_DMA2CH4 (75) /* 59: DMA2 Channel 4 global interrupt */
# define STM32_IRQ_DMA2CH5 (76) /* 60: DMA2 Channel 5 global interrupt */
# define STM32_IRQ_ETH (77) /* 61: Ethernet global interrupt */
# define STM32_IRQ_ETHWKUP (78) /* 62: Ethernet Wakeup through EXTI line interrupt */
# define STM32_IRQ_CAN2TX (79) /* 63: CAN2 TX interrupts */
# define STM32_IRQ_CAN2RX0 (70) /* 64: CAN2 RX0 interrupts */
# define STM32_IRQ_CAN2RX1 (81) /* 65: CAN2 RX1 interrupt */
# define STM32_IRQ_CAN2SCE (82) /* 66: CAN2 SCE interrupt */
# define STM32_IRQ_OTGFS (83) /* 67: USB On The Go FS global interrupt */
# define NR_VECTORS (84)
# define NR_IRQS (84)
/* Medium and High Density Devices */
#else
# define STM32_IRQ_WWDG (16) /* 0: Window Watchdog interrupt */
# define STM32_IRQ_PVD (17) /* 1: PVD through EXTI Line detection interrupt */
# define STM32_IRQ_TAMPER (18) /* 2: Tamper interrupt */
# define STM32_IRQ_RTC (19) /* 3: RTC global interrupt */
# define STM32_IRQ_FLASH (20) /* 4: Flash global interrupt */
# define STM32_IRQ_RCC (21) /* 5: RCC global interrupt */
# define STM32_IRQ_EXTI0 (22) /* 6: EXTI Line 0 interrupt */
# define STM32_IRQ_EXTI1 (23) /* 7: EXTI Line 1 interrupt */
# define STM32_IRQ_EXTI2 (24) /* 8: EXTI Line 2 interrupt */
# define STM32_IRQ_EXTI3 (25) /* 9: EXTI Line 3 interrupt */
# define STM32_IRQ_EXTI4 (26) /* 10: EXTI Line 4 interrupt */
# define STM32_IRQ_DMA1CH1 (27) /* 11: DMA1 Channel 1 global interrupt */
# define STM32_IRQ_DMA1CH2 (28) /* 12: DMA1 Channel 2 global interrupt */
# define STM32_IRQ_DMA1CH3 (29) /* 13: DMA1 Channel 3 global interrupt */
# define STM32_IRQ_DMA1CH4 (30) /* 14: DMA1 Channel 4 global interrupt */
# define STM32_IRQ_DMA1CH5 (31) /* 15: DMA1 Channel 5 global interrupt */
# define STM32_IRQ_DMA1CH6 (32) /* 16: DMA1 Channel 6 global interrupt */
# define STM32_IRQ_DMA1CH7 (33) /* 17: DMA1 Channel 7 global interrupt */
# define STM32_IRQ_ADC12 (34) /* 18: ADC1 and ADC2 global interrupt */
# define STM32_IRQ_USBHPCANTX (35) /* 19: USB High Priority or CAN TX interrupts*/
# define STM32_IRQ_USBLPCANRX0 (36) /* 20: USB Low Priority or CAN RX0 interrupts*/
# define STM32_IRQ_CAN1RX1 (37) /* 21: CAN1 RX1 interrupt */
# define STM32_IRQ_CAN1SCE (38) /* 22: CAN1 SCE interrupt */
# define STM32_IRQ_EXTI95 (39) /* 23: EXTI Line[9:5] interrupts */
# define STM32_IRQ_TIM1BRK (40) /* 24: TIM1 Break interrupt */
# define STM32_IRQ_TIM1UP (41) /* 25: TIM1 Update interrupt */
# define STM32_IRQ_TIM1TRGCOM (42) /* 26: TIM1 Trigger and Commutation interrupts */
# define STM32_IRQ_TIM1CC (43) /* 27: TIM1 Capture Compare interrupt */
# define STM32_IRQ_TIM2 (44) /* 28: TIM2 global interrupt */
# define STM32_IRQ_TIM3 (45) /* 29: TIM3 global interrupt */
# define STM32_IRQ_TIM4 (46) /* 30: TIM4 global interrupt */
# define STM32_IRQ_I2C1EV (47) /* 31: I2C1 event interrupt */
# define STM32_IRQ_I2C1ER (48) /* 32: I2C1 error interrupt */
# define STM32_IRQ_I2C2EV (49) /* 33: I2C2 event interrupt */
# define STM32_IRQ_I2C2ER (50) /* 34: I2C2 error interrupt */
# define STM32_IRQ_SPI1 (51) /* 35: SPI1 global interrupt */
# define STM32_IRQ_SPI2 (52) /* 36: SPI2 global interrupt */
# define STM32_IRQ_USART1 (53) /* 37: USART1 global interrupt */
# define STM32_IRQ_USART2 (54) /* 38: USART2 global interrupt */
# define STM32_IRQ_USART3 (55) /* 39: USART3 global interrupt */
# define STM32_IRQ_EXTI1510 (56) /* 40: EXTI Line[15:10] interrupts */
# define STM32_IRQ_RTCALRM (57) /* 41: RTC alarm through EXTI line interrupt */
# define STM32_IRQ_USBWKUP (58) /* 42: USB wakeup from suspend through EXTI line interrupt*/
# define STM32_IRQ_TIM8BRK (59) /* 43: TIM8 Break interrupt */
# define STM32_IRQ_TIM8UP (60) /* 44: TIM8 Update interrupt */
# define STM32_IRQ_TIM8TRGCOM (61) /* 45: TIM8 Trigger and Commutation interrupts */
# define STM32_IRQ_TIM8CC (62) /* 46: TIM8 Capture Compare interrupt */
# define STM32_IRQ_ADC3 (63) /* 47: ADC3 global interrupt */
# define STM32_IRQ_FSMC (64) /* 48: FSMC global interrupt */
# define STM32_IRQ_SDIO (65) /* 49: SDIO global interrupt */
# define STM32_IRQ_TIM5 (66) /* 50: TIM5 global interrupt */
# define STM32_IRQ_SPI3 (67) /* 51: SPI3 global interrupt */
# define STM32_IRQ_UART4 (68) /* 52: UART4 global interrupt */
# define STM32_IRQ_UART5 (69) /* 53: UART5 global interrupt */
# define STM32_IRQ_TIM6 (70) /* 54: TIM6 global interrupt */
# define STM32_IRQ_TIM7 (71) /* 55: TIM7 global interrupt */
# define STM32_IRQ_DMA2CH1 (72) /* 56: DMA2 Channel 1 global interrupt */
# define STM32_IRQ_DMA2CH2 (73) /* 57: DMA2 Channel 2 global interrupt */
# define STM32_IRQ_DMA2CH3 (74) /* 58: DMA2 Channel 3 global interrupt */
# define STM32_IRQ_DMA2CH45 (75) /* 59: DMA2 Channel 4&5 global interrupt */
# define NR_VECTORS (76)
# define NR_IRQS (76)
/* Convenience definitions for interrupts with multiple functions */
# define STM32_IRQ_USBHP STM32_IRQ_USBHPCANTX
# define STM32_IRQ_CAN1TX STM32_IRQ_USBHPCANTX
# define STM32_IRQ_USBLP STM32_IRQ_USBLPCANRX0
# define STM32_IRQ_CAN1RX0 STM32_IRQ_USBLPCANRX0
#endif
/************************************************************************************
* Public Types
************************************************************************************/
/************************************************************************************
* Public Data
************************************************************************************/
#ifndef __ASSEMBLY__
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/************************************************************************************
* Public Functions
************************************************************************************/
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif
#endif /* __ARCH_ARM_INCLUDE_STM32_STM32F10XXX_IRQ_H */

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@ -1,184 +0,0 @@
/****************************************************************************************************
* arch/arm/include/stm32s/stm32f20xxx_irq.h
*
* Copyright (C) 2012 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************************************/
/* This file should never be included directed but, rather, only indirectly through nuttx/irq.h */
#ifndef __ARCH_ARM_INCLUDE_STM32_STM32F20XXX_IRQ_H
#define __ARCH_ARM_INCLUDE_STM32_STM32F20XXX_IRQ_H
/****************************************************************************************************
* Included Files
****************************************************************************************************/
#include <nuttx/config.h>
#include <nuttx/irq.h>
/****************************************************************************************************
* Pre-processor Definitions
****************************************************************************************************/
/* IRQ numbers. The IRQ number corresponds vector number and hence map directly to
* bits in the NVIC. This does, however, waste several words of memory in the IRQ
* to handle mapping tables.
*
* Processor Exceptions (vectors 0-15). These common definitions can be found
* in nuttx/arch/arm/include/stm32/irq.h
*
* External interrupts (vectors >= 16)
*/
#define STM32_IRQ_WWDG (STM32_IRQ_FIRST+0) /* 0: Window Watchdog interrupt */
#define STM32_IRQ_PVD (STM32_IRQ_FIRST+1) /* 1: PVD through EXTI Line detection interrupt */
#define STM32_IRQ_TAMPER (STM32_IRQ_FIRST+2) /* 2: Tamper and time stamp interrupts */
#define STM32_IRQ_TIMESTAMP (STM32_IRQ_FIRST+2) /* 2: Tamper and time stamp interrupts */
#define STM32_IRQ_RTC_WKUP (STM32_IRQ_FIRST+3) /* 3: RTC global interrupt */
#define STM32_IRQ_FLASH (STM32_IRQ_FIRST+4) /* 4: Flash global interrupt */
#define STM32_IRQ_RCC (STM32_IRQ_FIRST+5) /* 5: RCC global interrupt */
#define STM32_IRQ_EXTI0 (STM32_IRQ_FIRST+6) /* 6: EXTI Line 0 interrupt */
#define STM32_IRQ_EXTI1 (STM32_IRQ_FIRST+7) /* 7: EXTI Line 1 interrupt */
#define STM32_IRQ_EXTI2 (STM32_IRQ_FIRST+8) /* 8: EXTI Line 2 interrupt */
#define STM32_IRQ_EXTI3 (STM32_IRQ_FIRST+9) /* 9: EXTI Line 3 interrupt */
#define STM32_IRQ_EXTI4 (STM32_IRQ_FIRST+10) /* 10: EXTI Line 4 interrupt */
#define STM32_IRQ_DMA1S0 (STM32_IRQ_FIRST+11) /* 11: DMA1 Stream 0 global interrupt */
#define STM32_IRQ_DMA1S1 (STM32_IRQ_FIRST+12) /* 12: DMA1 Stream 1 global interrupt */
#define STM32_IRQ_DMA1S2 (STM32_IRQ_FIRST+13) /* 13: DMA1 Stream 2 global interrupt */
#define STM32_IRQ_DMA1S3 (STM32_IRQ_FIRST+14) /* 14: DMA1 Stream 3 global interrupt */
#define STM32_IRQ_DMA1S4 (STM32_IRQ_FIRST+15) /* 15: DMA1 Stream 4 global interrupt */
#define STM32_IRQ_DMA1S5 (STM32_IRQ_FIRST+16) /* 16: DMA1 Stream 5 global interrupt */
#define STM32_IRQ_DMA1S6 (STM32_IRQ_FIRST+17) /* 17: DMA1 Stream 6 global interrupt */
#define STM32_IRQ_ADC (STM32_IRQ_FIRST+18) /* 18: ADC1, ADC2, and ADC3 global interrupt */
#define STM32_IRQ_CAN1TX (STM32_IRQ_FIRST+19) /* 19: CAN1 TX interrupts */
#define STM32_IRQ_CAN1RX0 (STM32_IRQ_FIRST+20) /* 20: CAN1 RX0 interrupts */
#define STM32_IRQ_CAN1RX1 (STM32_IRQ_FIRST+21) /* 21: CAN1 RX1 interrupt */
#define STM32_IRQ_CAN1SCE (STM32_IRQ_FIRST+22) /* 22: CAN1 SCE interrupt */
#define STM32_IRQ_EXTI95 (STM32_IRQ_FIRST+23) /* 23: EXTI Line[9:5] interrupts */
#define STM32_IRQ_TIM1BRK (STM32_IRQ_FIRST+24) /* 24: TIM1 Break interrupt */
#define STM32_IRQ_TIM9 (STM32_IRQ_FIRST+24) /* 24: TIM9 global interrupt */
#define STM32_IRQ_TIM1UP (STM32_IRQ_FIRST+25) /* 25: TIM1 Update interrupt */
#define STM32_IRQ_TIM10 (STM32_IRQ_FIRST+25) /* 25: TIM10 global interrupt */
#define STM32_IRQ_TIM1TRGCOM (STM32_IRQ_FIRST+26) /* 26: TIM1 Trigger and Commutation interrupts */
#define STM32_IRQ_TIM11 (STM32_IRQ_FIRST+26) /* 26: TIM11 global interrupt */
#define STM32_IRQ_TIM1CC (STM32_IRQ_FIRST+27) /* 27: TIM1 Capture Compare interrupt */
#define STM32_IRQ_TIM2 (STM32_IRQ_FIRST+28) /* 28: TIM2 global interrupt */
#define STM32_IRQ_TIM3 (STM32_IRQ_FIRST+29) /* 29: TIM3 global interrupt */
#define STM32_IRQ_TIM4 (STM32_IRQ_FIRST+30) /* 30: TIM4 global interrupt */
#define STM32_IRQ_I2C1EV (STM32_IRQ_FIRST+31) /* 31: I2C1 event interrupt */
#define STM32_IRQ_I2C1ER (STM32_IRQ_FIRST+32) /* 32: I2C1 error interrupt */
#define STM32_IRQ_I2C2EV (STM32_IRQ_FIRST+33) /* 33: I2C2 event interrupt */
#define STM32_IRQ_I2C2ER (STM32_IRQ_FIRST+34) /* 34: I2C2 error interrupt */
#define STM32_IRQ_SPI1 (STM32_IRQ_FIRST+35) /* 35: SPI1 global interrupt */
#define STM32_IRQ_SPI2 (STM32_IRQ_FIRST+36) /* 36: SPI2 global interrupt */
#define STM32_IRQ_USART1 (STM32_IRQ_FIRST+37) /* 37: USART1 global interrupt */
#define STM32_IRQ_USART2 (STM32_IRQ_FIRST+38) /* 38: USART2 global interrupt */
#define STM32_IRQ_USART3 (STM32_IRQ_FIRST+39) /* 39: USART3 global interrupt */
#define STM32_IRQ_EXTI1510 (STM32_IRQ_FIRST+40) /* 40: EXTI Line[15:10] interrupts */
#define STM32_IRQ_RTCALRM (STM32_IRQ_FIRST+41) /* 41: RTC alarm through EXTI line interrupt */
#define STM32_IRQ_OTGFSWKUP (STM32_IRQ_FIRST+42) /* 42: USB On-The-Go FS Wakeup through EXTI line interrupt */
#define STM32_IRQ_TIM8BRK (STM32_IRQ_FIRST+43) /* 43: TIM8 Break interrupt */
#define STM32_IRQ_TIM12 (STM32_IRQ_FIRST+43) /* 43: TIM12 global interrupt */
#define STM32_IRQ_TIM8UP (STM32_IRQ_FIRST+44) /* 44: TIM8 Update interrupt */
#define STM32_IRQ_TIM13 (STM32_IRQ_FIRST+44) /* 44: TIM13 global interrupt */
#define STM32_IRQ_TIM8TRGCOM (STM32_IRQ_FIRST+45) /* 45: TIM8 Trigger and Commutation interrupts */
#define STM32_IRQ_TIM14 (STM32_IRQ_FIRST+45) /* 45: TIM14 global interrupt */
#define STM32_IRQ_TIM8CC (STM32_IRQ_FIRST+46) /* 46: TIM8 Capture Compare interrupt */
#define STM32_IRQ_DMA1S7 (STM32_IRQ_FIRST+47) /* 47: DMA1 Stream 7 global interrupt */
#define STM32_IRQ_FSMC (STM32_IRQ_FIRST+48) /* 48: FSMC global interrupt */
#define STM32_IRQ_SDIO (STM32_IRQ_FIRST+49) /* 49: SDIO global interrupt */
#define STM32_IRQ_TIM5 (STM32_IRQ_FIRST+50) /* 50: TIM5 global interrupt */
#define STM32_IRQ_SPI3 (STM32_IRQ_FIRST+51) /* 51: SPI3 global interrupt */
#define STM32_IRQ_UART4 (STM32_IRQ_FIRST+52) /* 52: UART4 global interrupt */
#define STM32_IRQ_UART5 (STM32_IRQ_FIRST+53) /* 53: UART5 global interrupt */
#define STM32_IRQ_TIM6 (STM32_IRQ_FIRST+54) /* 54: TIM6 global interrupt */
#define STM32_IRQ_DAC (STM32_IRQ_FIRST+54) /* 54: DAC1 and DAC2 underrun error interrupts */
#define STM32_IRQ_TIM7 (STM32_IRQ_FIRST+55) /* 55: TIM7 global interrupt */
#define STM32_IRQ_DMA2S0 (STM32_IRQ_FIRST+56) /* 56: DMA2 Stream 0 global interrupt */
#define STM32_IRQ_DMA2S1 (STM32_IRQ_FIRST+57) /* 57: DMA2 Stream 1 global interrupt */
#define STM32_IRQ_DMA2S2 (STM32_IRQ_FIRST+58) /* 58: DMA2 Stream 2 global interrupt */
#define STM32_IRQ_DMA2S3 (STM32_IRQ_FIRST+59) /* 59: DMA2 Stream 3 global interrupt */
#define STM32_IRQ_DMA2S4 (STM32_IRQ_FIRST+60) /* 60: DMA2 Stream 4 global interrupt */
#define STM32_IRQ_ETH (STM32_IRQ_FIRST+61) /* 61: Ethernet global interrupt */
#define STM32_IRQ_ETHWKUP (STM32_IRQ_FIRST+62) /* 62: Ethernet Wakeup through EXTI line interrupt */
#define STM32_IRQ_CAN2TX (STM32_IRQ_FIRST+63) /* 63: CAN2 TX interrupts */
#define STM32_IRQ_CAN2RX0 (STM32_IRQ_FIRST+64) /* 64: CAN2 RX0 interrupts */
#define STM32_IRQ_CAN2RX1 (STM32_IRQ_FIRST+65) /* 65: CAN2 RX1 interrupt */
#define STM32_IRQ_CAN2SCE (STM32_IRQ_FIRST+66) /* 66: CAN2 SCE interrupt */
#define STM32_IRQ_OTGFS (STM32_IRQ_FIRST+67) /* 67: USB On The Go FS global interrupt */
#define STM32_IRQ_DMA2S5 (STM32_IRQ_FIRST+68) /* 68: DMA2 Stream 5 global interrupt */
#define STM32_IRQ_DMA2S6 (STM32_IRQ_FIRST+69) /* 69: DMA2 Stream 6 global interrupt */
#define STM32_IRQ_DMA2S7 (STM32_IRQ_FIRST+70) /* 70: DMA2 Stream 7 global interrupt */
#define STM32_IRQ_USART6 (STM32_IRQ_FIRST+71) /* 71: USART6 global interrupt */
#define STM32_IRQ_I2C3EV (STM32_IRQ_FIRST+72) /* 72: I2C3 event interrupt */
#define STM32_IRQ_I2C3ER (STM32_IRQ_FIRST+73) /* 73: I2C3 error interrupt */
#define STM32_IRQ_OTGHSEP1OUT (STM32_IRQ_FIRST+74) /* 74: USB On The Go HS End Point 1 Out global interrupt */
#define STM32_IRQ_OTGHSEP1IN (STM32_IRQ_FIRST+75) /* 75: USB On The Go HS End Point 1 In global interrupt */
#define STM32_IRQ_OTGHSWKUP (STM32_IRQ_FIRST+76) /* 76: USB On The Go HS Wakeup through EXTI interrupt */
#define STM32_IRQ_OTGHS (STM32_IRQ_FIRST+77) /* 77: USB On The Go HS global interrupt */
#define STM32_IRQ_DCMI (STM32_IRQ_FIRST+78) /* 78: DCMI global interrupt */
#define STM32_IRQ_CRYP (STM32_IRQ_FIRST+79) /* 79: CRYP crypto global interrupt */
#define STM32_IRQ_HASH (STM32_IRQ_FIRST+80) /* 80: Hash and Rng global interrupt */
#define STM32_IRQ_RNG (STM32_IRQ_FIRST+80) /* 80: Hash and Rng global interrupt */
#define NR_VECTORS (STM32_IRQ_FIRST+81)
#define NR_IRQS (STM32_IRQ_FIRST+81)
/****************************************************************************************************
* Public Types
****************************************************************************************************/
/****************************************************************************************************
* Public Data
****************************************************************************************************/
#ifndef __ASSEMBLY__
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************************************
* Public Functions
****************************************************************************************************/
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif
#endif /* __ARCH_ARM_INCLUDE_STM32_STM32F20XXX_IRQ_H */

195
arch/arm/include/stm32/stm32f30xxx_irq.h
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@ -1,195 +0,0 @@
/****************************************************************************************************
* arch/arm/include/stm32s/stm32f30xxx_irq.h
*
* Copyright (C) 2012 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************************************/
/* This file should never be included directed but, rather, only indirectly through nuttx/irq.h */
#ifndef __ARCH_ARM_INCLUDE_STM32_STM32F30XXX_IRQ_H
#define __ARCH_ARM_INCLUDE_STM32_STM32F30XXX_IRQ_H
/****************************************************************************************************
* Included Files
****************************************************************************************************/
#include <nuttx/config.h>
#include <nuttx/irq.h>
/****************************************************************************************************
* Pre-processor Definitions
****************************************************************************************************/
/* IRQ numbers. The IRQ number corresponds vector number and hence map directly to
* bits in the NVIC. This does, however, waste several words of memory in the IRQ
* to handle mapping tables.
*
* Processor Exceptions (vectors 0-15). These common definitions can be found
* in nuttx/arch/arm/include/stm32/irq.h
*
* External interrupts (vectors >= 16)
*/
#define STM32_IRQ_WWDG (STM32_IRQ_FIRST+0) /* 0: Window Watchdog interrupt */
#define STM32_IRQ_PVD (STM32_IRQ_FIRST+1) /* 1: PVD through EXTI Line detection interrupt */
#define STM32_IRQ_TAMPER (STM32_IRQ_FIRST+2) /* 2: Tamper interrupt, or */
#define STM32_IRQ_TIMESTAMP (STM32_IRQ_FIRST+2) /* 2: Time stamp interrupt */
#define STM32_IRQ_RTC_WKUP (STM32_IRQ_FIRST+3) /* 3: RTC global interrupt */
#define STM32_IRQ_FLASH (STM32_IRQ_FIRST+4) /* 4: Flash global interrupt */
#define STM32_IRQ_RCC (STM32_IRQ_FIRST+5) /* 5: RCC global interrupt */
#define STM32_IRQ_EXTI0 (STM32_IRQ_FIRST+6) /* 6: EXTI Line 0 interrupt */
#define STM32_IRQ_EXTI1 (STM32_IRQ_FIRST+7) /* 7: EXTI Line 1 interrupt */
#define STM32_IRQ_EXTI2 (STM32_IRQ_FIRST+8) /* 8: EXTI Line 2 interrupt, or */
#define STM32_IRQ_TSC (STM32_IRQ_FIRST+8) /* 8: TSC interrupt */
#define STM32_IRQ_EXTI3 (STM32_IRQ_FIRST+9) /* 9: EXTI Line 3 interrupt */
#define STM32_IRQ_EXTI4 (STM32_IRQ_FIRST+10) /* 10: EXTI Line 4 interrupt */
#define STM32_IRQ_DMA1CH1 (STM32_IRQ_FIRST+11) /* 11: DMA1 channel 1 global interrupt */
#define STM32_IRQ_DMA1CH2 (STM32_IRQ_FIRST+12) /* 12: DMA1 channel 2 global interrupt */
#define STM32_IRQ_DMA1CH3 (STM32_IRQ_FIRST+13) /* 13: DMA1 channel 3 global interrupt */
#define STM32_IRQ_DMA1CH4 (STM32_IRQ_FIRST+14) /* 14: DMA1 channel 4 global interrupt */
#define STM32_IRQ_DMA1CH5 (STM32_IRQ_FIRST+15) /* 15: DMA1 channel 5 global interrupt */
#define STM32_IRQ_DMA1CH6 (STM32_IRQ_FIRST+16) /* 16: DMA1 channel 6 global interrupt */
#define STM32_IRQ_DMA1CH7 (STM32_IRQ_FIRST+17) /* 17: DMA1 channel 7 global interrupt */
#define STM32_IRQ_ADC12 (STM32_IRQ_FIRST+18) /* 18: ADC1/ADC2 global interrupt */
#define STM32_IRQ_USBHP_1 (STM32_IRQ_FIRST+19) /* 19: USB High Priority interrupts (not remapped) */
#define STM32_IRQ_CAN1TX (STM32_IRQ_FIRST+19) /* 19: CAN1 TX interrupts */
#define STM32_IRQ_USBLP_1 (STM32_IRQ_FIRST+20) /* 20: USB Low Priority interrupt (not remapped) */
#define STM32_IRQ_CAN1RX0 (STM32_IRQ_FIRST+20) /* 20: CAN1 RX0 interrupts*/
#define STM32_IRQ_CAN1RX1 (STM32_IRQ_FIRST+21) /* 21: CAN1 RX1 interrupt */
#define STM32_IRQ_CAN1SCE (STM32_IRQ_FIRST+22) /* 22: CAN1 SCE interrupt */
#define STM32_IRQ_EXTI95 (STM32_IRQ_FIRST+23) /* 23: EXTI Line[9:5] interrupts */
#define STM32_IRQ_TIM1BRK (STM32_IRQ_FIRST+24) /* 24: TIM1 Break interrupt, or */
#define STM32_IRQ_TIM15 (STM32_IRQ_FIRST+24) /* 24: TIM15 global interrupt */
#define STM32_IRQ_TIM1UP (STM32_IRQ_FIRST+25) /* 25: TIM1 Update interrupt, or */
#define STM32_IRQ_TIM16 (STM32_IRQ_FIRST+25) /* 25: TIM16 global interrupt */
#define STM32_IRQ_TIM1TRGCOM (STM32_IRQ_FIRST+26) /* 26: TIM1 Trigger and Commutation interrupts, or */
#define STM32_IRQ_TIM17 (STM32_IRQ_FIRST+26) /* 26: TIM17 global interrupt */
#define STM32_IRQ_TIM1CC (STM32_IRQ_FIRST+27) /* 27: TIM1 Capture Compare interrupt */
#define STM32_IRQ_TIM2 (STM32_IRQ_FIRST+28) /* 28: TIM2 global interrupt */
#define STM32_IRQ_TIM3 (STM32_IRQ_FIRST+29) /* 29: TIM3 global interrupt */
#define STM32_IRQ_TIM4 (STM32_IRQ_FIRST+30) /* 30: TIM4 global interrupt */
#define STM32_IRQ_I2C1EV (STM32_IRQ_FIRST+31) /* 31: I2C1 event interrupt, or */
#define STM32_IRQ_EXTI23 (STM32_IRQ_FIRST+31) /* 31: EXTI Line23 interrupt */
#define STM32_IRQ_I2C1ER (STM32_IRQ_FIRST+32) /* 32: I2C1 error interrupt */
#define STM32_IRQ_I2C2EV (STM32_IRQ_FIRST+33) /* 33: I2C2 event interrupt, or */
#define STM32_IRQ_EXTI24 (STM32_IRQ_FIRST+33) /* 33: EXTI Line24 interrupt */
#define STM32_IRQ_I2C2ER (STM32_IRQ_FIRST+34) /* 34: I2C2 error interrupt */
#define STM32_IRQ_SPI1 (STM32_IRQ_FIRST+35) /* 35: SPI1 global interrupt */
#define STM32_IRQ_SPI2 (STM32_IRQ_FIRST+36) /* 36: SPI2 global interrupt */
#define STM32_IRQ_USART1 (STM32_IRQ_FIRST+37) /* 37: USART1 global interrupt, or */
#define STM32_IRQ_EXTI25 (STM32_IRQ_FIRST+37) /* 37: EXTI Line 25 interrupt */
#define STM32_IRQ_USART2 (STM32_IRQ_FIRST+38) /* 38: USART2 global interrupt, or */
#define STM32_IRQ_EXTI26 (STM32_IRQ_FIRST+38) /* 38: EXTI Line 26 interrupt */
#define STM32_IRQ_USART3 (STM32_IRQ_FIRST+39) /* 39: USART3 global interrupt, or */
#define STM32_IRQ_EXTI28 (STM32_IRQ_FIRST+39) /* 39: EXTI Line 28 interrupt */
#define STM32_IRQ_EXTI1510 (STM32_IRQ_FIRST+40) /* 40: EXTI Line[15:10] interrupts */
#define STM32_IRQ_RTCALRM (STM32_IRQ_FIRST+41) /* 41: RTC alarm through EXTI line interrupt */
#define STM32_IRQ_USBWKUP_1 (STM32_IRQ_FIRST+42) /* 42: USB wakeup from suspend through EXTI line interrupt */
#define STM32_IRQ_EXT18 (STM32_IRQ_FIRST+42) /* 42: EXTI Line 18 interrupt */
#define STM32_IRQ_TIM8BRK (STM32_IRQ_FIRST+43) /* 43: TIM8 Break interrupt */
#define STM32_IRQ_TIM8UP (STM32_IRQ_FIRST+44) /* 44: TIM8 Update interrupt */
#define STM32_IRQ_TIM8TRGCOM (STM32_IRQ_FIRST+45) /* 45: TIM8 Trigger and Commutation interrupts */
#define STM32_IRQ_TIM8CC (STM32_IRQ_FIRST+46) /* 46: TIM8 Capture Compare interrupt */
#define STM32_IRQ_ADC3 (STM32_IRQ_FIRST+47) /* 47: ADC3 global interrupt */
#define STM32_IRQ_RESERVED48 (STM32_IRQ_FIRST+48) /* 48: Reserved */
#define STM32_IRQ_RESERVED49 (STM32_IRQ_FIRST+49) /* 49: Reserved */
#define STM32_IRQ_RESERVED50 (STM32_IRQ_FIRST+50) /* 50: Reserved */
#define STM32_IRQ_SPI3 (STM32_IRQ_FIRST+51) /* 51: SPI3 global interrupt */
#define STM32_IRQ_UART4 (STM32_IRQ_FIRST+52) /* 52: UART4 global interrupt, or */
#define STM32_IRQ_EXTI34 (STM32_IRQ_FIRST+52) /* 52: EXTI Line 34 interrupt */
#define STM32_IRQ_UART5 (STM32_IRQ_FIRST+53) /* 53: UART5 global interrupt, or */
#define STM32_IRQ_EXTI35 (STM32_IRQ_FIRST+53) /* 53: EXTI Line 35 interrupt */
#define STM32_IRQ_TIM6 (STM32_IRQ_FIRST+54) /* 54: TIM6 global interrupt, or */
#define STM32_IRQ_DAC (STM32_IRQ_FIRST+54) /* 54: DAC1 and DAC2 underrun error interrupts */
#define STM32_IRQ_TIM7 (STM32_IRQ_FIRST+55) /* 55: TIM7 global interrupt */
#define STM32_IRQ_DMA2CH1 (STM32_IRQ_FIRST+56) /* 56: DMA2 channel 1 global interrupt */
#define STM32_IRQ_DMA2CH2 (STM32_IRQ_FIRST+57) /* 57: DMA2 channel 2 global interrupt */
#define STM32_IRQ_DMA2CH3 (STM32_IRQ_FIRST+58) /* 58: DMA2 channel 3 global interrupt */
#define STM32_IRQ_DMA2CH4 (STM32_IRQ_FIRST+59) /* 59: DMA2 channel 4 global interrupt */
#define STM32_IRQ_DMA2CH5 (STM32_IRQ_FIRST+60) /* 60: DMA2 channel 5 global interrupt */
#define STM32_IRQ_ADC4 (STM32_IRQ_FIRST+61) /* 61: ADC4 global interrupt */
#define STM32_IRQ_RESERVED62 (STM32_IRQ_FIRST+62) /* 62: Reserved */
#define STM32_IRQ_RESERVED63 (STM32_IRQ_FIRST+63) /* 63: Reserved */
#define STM32_IRQ_COMP123 (STM32_IRQ_FIRST+64) /* 64: COMP1 & COMP2 & COMP3 interrupts, or */
#define STM32_IRQ_EXTI2129 (STM32_IRQ_FIRST+64) /* 64: EXTI Lines 21, 22 and 29 interrupts */
#define STM32_IRQ_COMP456 (STM32_IRQ_FIRST+65) /* 65: COMP4 & COMP5 & COMP6 interrupts, or */
#define STM32_IRQ_EXTI3012 (STM32_IRQ_FIRST+65) /* 65: EXTI Lines 30, 31 and 32 interrupts */
#define STM32_IRQ_COMP7 (STM32_IRQ_FIRST+66) /* 66: COMP7 interrupt, or */
#define STM32_IRQ_EXTI33 (STM32_IRQ_FIRST+66) /* 66: EXTI Line 33 interrupt */
#define STM32_IRQ_RESERVED67 (STM32_IRQ_FIRST+67) /* 67: Reserved */
#define STM32_IRQ_RESERVED68 (STM32_IRQ_FIRST+68) /* 68: Reserved */
#define STM32_IRQ_RESERVED69 (STM32_IRQ_FIRST+69) /* 69: Reserved */
#define STM32_IRQ_RESERVED70 (STM32_IRQ_FIRST+70) /* 70: Reserved */
#define STM32_IRQ_RESERVED71 (STM32_IRQ_FIRST+71) /* 71: Reserved */
#define STM32_IRQ_RESERVED72 (STM32_IRQ_FIRST+72) /* 72: Reserved */
#define STM32_IRQ_RESERVED73 (STM32_IRQ_FIRST+73) /* 73: Reserved */
#define STM32_IRQ_USBHP_2 (STM32_IRQ_FIRST+74) /* 74: USB High priority interrupt (remapped) */
#define STM32_IRQ_USBLP_2 (STM32_IRQ_FIRST+75) /* 75: USB Low priority interrupt remapped) */
#define STM32_IRQ_USBWKUP_2 (STM32_IRQ_FIRST+76) /* 76: USB wakeup from suspend remapped) */
#define STM32_IRQ_RESERVED77 (STM32_IRQ_FIRST+77) /* 77: Reserved */
#define STM32_IRQ_RESERVED78 (STM32_IRQ_FIRST+78) /* 78: Reserved */
#define STM32_IRQ_RESERVED79 (STM32_IRQ_FIRST+79) /* 79: Reserved */
#define STM32_IRQ_RESERVED80 (STM32_IRQ_FIRST+80) /* 80: Reserved */
#define STM32_IRQ_FPU (STM32_IRQ_FIRST+81) /* 81: FPU global interrupt */
#define NR_VECTORS (STM32_IRQ_FIRST+82)
#define NR_IRQS (STM32_IRQ_FIRST+82)
/****************************************************************************************************
* Public Types
****************************************************************************************************/
/****************************************************************************************************
* Public Data
****************************************************************************************************/
#ifndef __ASSEMBLY__
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************************************
* Public Functions
****************************************************************************************************/
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif
#endif /* __ARCH_ARM_INCLUDE_STM32_STM32F30XXX_IRQ_H */

181
arch/arm/include/stm32/stm32f37xxx_irq.h
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@ -1,181 +0,0 @@
/****************************************************************************************************
* arch/arm/include/stm32s/stm32f37xxx_irq.h
*
* Copyright (C) 2012 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
* Modified for STM32F373 by Marten Svanfeldt <marten@svanfeldt.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************************************/
/* This file should never be included directed but, rather, only indirectly through nuttx/irq.h */
#ifndef __ARCH_ARM_INCLUDE_STM32_STM32F37XXX_IRQ_H
#define __ARCH_ARM_INCLUDE_STM32_STM32F37XXX_IRQ_H
/****************************************************************************************************
* Included Files
****************************************************************************************************/
#include <nuttx/config.h>
#include <nuttx/irq.h>
/****************************************************************************************************
* Pre-processor Definitions
****************************************************************************************************/
/* IRQ numbers. The IRQ number corresponds vector number and hence map directly to
* bits in the NVIC. This does, however, waste several words of memory in the IRQ
* to handle mapping tables.
*
* Processor Exceptions (vectors 0-15). These common definitions can be found
* in nuttx/arch/arm/include/stm32/irq.h
*
* External interrupts (vectors >= 16)
*/
#define STM32_IRQ_WWDG (STM32_IRQ_FIRST+0) /* 0: Window Watchdog interrupt */
#define STM32_IRQ_PVD (STM32_IRQ_FIRST+1) /* 1: PVD through EXTI Line detection interrupt */
#define STM32_IRQ_TAMPER (STM32_IRQ_FIRST+2) /* 2: Tamper interrupt, or */
#define STM32_IRQ_TIMESTAMP (STM32_IRQ_FIRST+2) /* 2: Time stamp interrupt */
#define STM32_IRQ_RTC_WKUP (STM32_IRQ_FIRST+3) /* 3: RTC global interrupt */
#define STM32_IRQ_FLASH (STM32_IRQ_FIRST+4) /* 4: Flash global interrupt */
#define STM32_IRQ_RCC (STM32_IRQ_FIRST+5) /* 5: RCC global interrupt */
#define STM32_IRQ_EXTI0 (STM32_IRQ_FIRST+6) /* 6: EXTI Line 0 interrupt */
#define STM32_IRQ_EXTI1 (STM32_IRQ_FIRST+7) /* 7: EXTI Line 1 interrupt */
#define STM32_IRQ_EXTI2 (STM32_IRQ_FIRST+8) /* 8: EXTI Line 2 interrupt, or */
#define STM32_IRQ_TSC (STM32_IRQ_FIRST+8) /* 8: TSC interrupt */
#define STM32_IRQ_EXTI3 (STM32_IRQ_FIRST+9) /* 9: EXTI Line 3 interrupt */
#define STM32_IRQ_EXTI4 (STM32_IRQ_FIRST+10) /* 10: EXTI Line 4 interrupt */
#define STM32_IRQ_DMA1CH1 (STM32_IRQ_FIRST+11) /* 11: DMA1 channel 1 global interrupt */
#define STM32_IRQ_DMA1CH2 (STM32_IRQ_FIRST+12) /* 12: DMA1 channel 2 global interrupt */
#define STM32_IRQ_DMA1CH3 (STM32_IRQ_FIRST+13) /* 13: DMA1 channel 3 global interrupt */
#define STM32_IRQ_DMA1CH4 (STM32_IRQ_FIRST+14) /* 14: DMA1 channel 4 global interrupt */
#define STM32_IRQ_DMA1CH5 (STM32_IRQ_FIRST+15) /* 15: DMA1 channel 5 global interrupt */
#define STM32_IRQ_DMA1CH6 (STM32_IRQ_FIRST+16) /* 16: DMA1 channel 6 global interrupt */
#define STM32_IRQ_DMA1CH7 (STM32_IRQ_FIRST+17) /* 17: DMA1 channel 7 global interrupt */
#define STM32_IRQ_ADC1 (STM32_IRQ_FIRST+18) /* 18: ADC1 global interrupt */
#define STM32_IRQ_CAN1TX (STM32_IRQ_FIRST+19) /* 19: CAN1 TX interrupts */
#define STM32_IRQ_CAN1RX0 (STM32_IRQ_FIRST+20) /* 20: CAN1 RX0 interrupts*/
#define STM32_IRQ_CAN1RX1 (STM32_IRQ_FIRST+21) /* 21: CAN1 RX1 interrupt */
#define STM32_IRQ_CAN1SCE (STM32_IRQ_FIRST+22) /* 22: CAN1 SCE interrupt */
#define STM32_IRQ_EXTI95 (STM32_IRQ_FIRST+23) /* 23: EXTI Line[9:5] interrupts */
#define STM32_IRQ_TIM15 (STM32_IRQ_FIRST+24) /* 24: TIM15 global interrupt */
#define STM32_IRQ_TIM16 (STM32_IRQ_FIRST+25) /* 25: TIM16 global interrupt */
#define STM32_IRQ_TIM17 (STM32_IRQ_FIRST+26) /* 26: TIM17 global interrupt */
#define STM32_IRQ_TIM18 (STM32_IRQ_FIRST+27) /* 27: TIM18 global interrupt, or */
#define STM32_IRQ_DAC2 (STM32_IRQ_FIRST+27) /* 27: DAC2 global interrupt */
#define STM32_IRQ_TIM2 (STM32_IRQ_FIRST+28) /* 28: TIM2 global interrupt */
#define STM32_IRQ_TIM3 (STM32_IRQ_FIRST+29) /* 29: TIM3 global interrupt */
#define STM32_IRQ_TIM4 (STM32_IRQ_FIRST+30) /* 30: TIM4 global interrupt */
#define STM32_IRQ_I2C1EV (STM32_IRQ_FIRST+31) /* 31: I2C1 event interrupt */
#define STM32_IRQ_I2C1ER (STM32_IRQ_FIRST+32) /* 32: I2C1 error interrupt */
#define STM32_IRQ_I2C2EV (STM32_IRQ_FIRST+33) /* 33: I2C2 event interrupt */
#define STM32_IRQ_I2C2ER (STM32_IRQ_FIRST+34) /* 34: I2C2 error interrupt */
#define STM32_IRQ_SPI1 (STM32_IRQ_FIRST+35) /* 35: SPI1 global interrupt */
#define STM32_IRQ_SPI2 (STM32_IRQ_FIRST+36) /* 36: SPI2 global interrupt */
#define STM32_IRQ_USART1 (STM32_IRQ_FIRST+37) /* 37: USART1 global interrupt */
#define STM32_IRQ_USART2 (STM32_IRQ_FIRST+38) /* 38: USART2 global interrupt */
#define STM32_IRQ_USART3 (STM32_IRQ_FIRST+39) /* 39: USART3 global interrupt */
#define STM32_IRQ_EXTI1510 (STM32_IRQ_FIRST+40) /* 40: EXTI Line[15:10] interrupts */
#define STM32_IRQ_RTCALRM (STM32_IRQ_FIRST+41) /* 41: RTC alarm through EXTI line interrupt */
#define STM32_IRQ_CEC (STM32_IRQ_FIRST+42) /* 42: CEC Interrupt */
#define STM32_IRQ_TIM12 (STM32_IRQ_FIRST+43) /* 43: TIM12 global interrupt */
#define STM32_IRQ_TIM13 (STM32_IRQ_FIRST+44) /* 44: TIM13 global interrupt */
#define STM32_IRQ_TIM14 (STM32_IRQ_FIRST+45) /* 45: TIM14 global interrupt */
#define STM32_IRQ_RESERVED46 (STM32_IRQ_FIRST+46) /* 46: Reserved */
#define STM32_IRQ_RESERVED47 (STM32_IRQ_FIRST+47) /* 47: Reserved */
#define STM32_IRQ_RESERVED48 (STM32_IRQ_FIRST+48) /* 48: Reserved */
#define STM32_IRQ_RESERVED49 (STM32_IRQ_FIRST+49) /* 49: Reserved */
#define STM32_IRQ_RESERVED50 (STM32_IRQ_FIRST+50) /* 50: Reserved */
#define STM32_IRQ_SPI3 (STM32_IRQ_FIRST+51) /* 51: SPI3 global interrupt */
#define STM32_IRQ_RESERVED52 (STM32_IRQ_FIRST+52) /* 52: Reserved */
#define STM32_IRQ_RESERVED53 (STM32_IRQ_FIRST+53) /* 53: Reserved */
#define STM32_IRQ_TIM6 (STM32_IRQ_FIRST+54) /* 54: TIM6 global interrupt, or */
#define STM32_IRQ_DAC1 (STM32_IRQ_FIRST+54) /* 54: DAC1 underrun error interrupts */
#define STM32_IRQ_TIM7 (STM32_IRQ_FIRST+55) /* 55: TIM7 global interrupt */
#define STM32_IRQ_DMA2CH1 (STM32_IRQ_FIRST+56) /* 56: DMA2 channel 1 global interrupt */
#define STM32_IRQ_DMA2CH2 (STM32_IRQ_FIRST+57) /* 57: DMA2 channel 2 global interrupt */
#define STM32_IRQ_DMA2CH3 (STM32_IRQ_FIRST+58) /* 58: DMA2 channel 3 global interrupt */
#define STM32_IRQ_DMA2CH4 (STM32_IRQ_FIRST+59) /* 59: DMA2 channel 4 global interrupt */
#define STM32_IRQ_DMA2CH5 (STM32_IRQ_FIRST+60) /* 60: DMA2 channel 5 global interrupt */
#define STM32_IRQ_SDADC1 (STM32_IRQ_FIRST+61) /* 61: ADC Sigma Delta 1 global interrupt */
#define STM32_IRQ_SDADC2 (STM32_IRQ_FIRST+62) /* 62: ADC Sigma Delta 2 global interrupt */
#define STM32_IRQ_SDADC3 (STM32_IRQ_FIRST+63) /* 63: ADC Sigma Delta 3 global interrupt */
#define STM32_IRQ_COMP12 (STM32_IRQ_FIRST+64) /* 64: COMP1 & COMP2 interrupts*/
#define STM32_IRQ_RESERVED65 (STM32_IRQ_FIRST+65) /* 65: Reserved */
#define STM32_IRQ_RESERVED66 (STM32_IRQ_FIRST+66) /* 66: Reserved */
#define STM32_IRQ_RESERVED67 (STM32_IRQ_FIRST+67) /* 67: Reserved */
#define STM32_IRQ_RESERVED68 (STM32_IRQ_FIRST+68) /* 68: Reserved */
#define STM32_IRQ_RESERVED69 (STM32_IRQ_FIRST+69) /* 69: Reserved */
#define STM32_IRQ_RESERVED70 (STM32_IRQ_FIRST+70) /* 70: Reserved */
#define STM32_IRQ_RESERVED71 (STM32_IRQ_FIRST+71) /* 71: Reserved */
#define STM32_IRQ_RESERVED72 (STM32_IRQ_FIRST+72) /* 72: Reserved */
#define STM32_IRQ_RESERVED73 (STM32_IRQ_FIRST+73) /* 73: Reserved */
#define STM32_IRQ_USBHP (STM32_IRQ_FIRST+74) /* 74: USB High priority interrupt */
#define STM32_IRQ_USBLP (STM32_IRQ_FIRST+75) /* 75: USB Low priority interrupt */
#define STM32_IRQ_USBWKUP (STM32_IRQ_FIRST+76) /* 76: USB wakeup from suspend */
#define STM32_IRQ_RESERVED77 (STM32_IRQ_FIRST+77) /* 77: Reserved */
#define STM32_IRQ_RESERVED78 (STM32_IRQ_FIRST+78) /* 78: Reserved */
#define STM32_IRQ_RESERVED79 (STM32_IRQ_FIRST+79) /* 79: Reserved */
#define STM32_IRQ_RESERVED80 (STM32_IRQ_FIRST+80) /* 80: Reserved */
#define STM32_IRQ_FPU (STM32_IRQ_FIRST+81) /* 81: FPU global interrupt */
#define NR_VECTORS (STM32_IRQ_FIRST+82)
#define NR_IRQS (STM32_IRQ_FIRST+82)
/****************************************************************************************************
* Public Types
****************************************************************************************************/
/****************************************************************************************************
* Public Data
****************************************************************************************************/
#ifndef __ASSEMBLY__
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************************************
* Public Functions
****************************************************************************************************/
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif
#endif /* __ARCH_ARM_INCLUDE_STM32F30XXX_IRQ_H */

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arch/arm/include/stm32/stm32f40xxx_irq.h
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@ -1,187 +0,0 @@
/****************************************************************************************************
* arch/arm/include/stm32s/stm32f40xxx_irq.h
*
* Copyright (C) 2009, 2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************************************/
/* This file should never be included directed but, rather,
* only indirectly through nuttx/irq.h
*/
#ifndef __ARCH_ARM_INCLUDE_STM32_STM32F40XXX_IRQ_H
#define __ARCH_ARM_INCLUDE_STM32_STM32F40XXX_IRQ_H
/****************************************************************************************************
* Included Files
****************************************************************************************************/
#include <nuttx/config.h>
#include <nuttx/irq.h>
/****************************************************************************************************
* Pre-processor Definitions
****************************************************************************************************/
/* IRQ numbers. The IRQ number corresponds vector number and hence map directly to
* bits in the NVIC. This does, however, waste several words of memory in the IRQ
* to handle mapping tables.
*
* Processor Exceptions (vectors 0-15). These common definitions can be found
* in nuttx/arch/arm/include/stm32/irq.h
*
* External interrupts (vectors >= 16)
*/
#define STM32_IRQ_WWDG (STM32_IRQ_FIRST+0) /* 0: Window Watchdog interrupt */
#define STM32_IRQ_PVD (STM32_IRQ_FIRST+1) /* 1: PVD through EXTI Line detection interrupt */
#define STM32_IRQ_TAMPER (STM32_IRQ_FIRST+2) /* 2: Tamper and time stamp interrupts */
#define STM32_IRQ_TIMESTAMP (STM32_IRQ_FIRST+2) /* 2: Tamper and time stamp interrupts */
#define STM32_IRQ_RTC_WKUP (STM32_IRQ_FIRST+3) /* 3: RTC global interrupt */
#define STM32_IRQ_FLASH (STM32_IRQ_FIRST+4) /* 4: Flash global interrupt */
#define STM32_IRQ_RCC (STM32_IRQ_FIRST+5) /* 5: RCC global interrupt */
#define STM32_IRQ_EXTI0 (STM32_IRQ_FIRST+6) /* 6: EXTI Line 0 interrupt */
#define STM32_IRQ_EXTI1 (STM32_IRQ_FIRST+7) /* 7: EXTI Line 1 interrupt */
#define STM32_IRQ_EXTI2 (STM32_IRQ_FIRST+8) /* 8: EXTI Line 2 interrupt */
#define STM32_IRQ_EXTI3 (STM32_IRQ_FIRST+9) /* 9: EXTI Line 3 interrupt */
#define STM32_IRQ_EXTI4 (STM32_IRQ_FIRST+10) /* 10: EXTI Line 4 interrupt */
#define STM32_IRQ_DMA1S0 (STM32_IRQ_FIRST+11) /* 11: DMA1 Stream 0 global interrupt */
#define STM32_IRQ_DMA1S1 (STM32_IRQ_FIRST+12) /* 12: DMA1 Stream 1 global interrupt */
#define STM32_IRQ_DMA1S2 (STM32_IRQ_FIRST+13) /* 13: DMA1 Stream 2 global interrupt */
#define STM32_IRQ_DMA1S3 (STM32_IRQ_FIRST+14) /* 14: DMA1 Stream 3 global interrupt */
#define STM32_IRQ_DMA1S4 (STM32_IRQ_FIRST+15) /* 15: DMA1 Stream 4 global interrupt */
#define STM32_IRQ_DMA1S5 (STM32_IRQ_FIRST+16) /* 16: DMA1 Stream 5 global interrupt */
#define STM32_IRQ_DMA1S6 (STM32_IRQ_FIRST+17) /* 17: DMA1 Stream 6 global interrupt */
#define STM32_IRQ_ADC (STM32_IRQ_FIRST+18) /* 18: ADC1, ADC2, and ADC3 global interrupt */
#define STM32_IRQ_CAN1TX (STM32_IRQ_FIRST+19) /* 19: CAN1 TX interrupts */
#define STM32_IRQ_CAN1RX0 (STM32_IRQ_FIRST+20) /* 20: CAN1 RX0 interrupts */
#define STM32_IRQ_CAN1RX1 (STM32_IRQ_FIRST+21) /* 21: CAN1 RX1 interrupt */
#define STM32_IRQ_CAN1SCE (STM32_IRQ_FIRST+22) /* 22: CAN1 SCE interrupt */
#define STM32_IRQ_EXTI95 (STM32_IRQ_FIRST+23) /* 23: EXTI Line[9:5] interrupts */
#define STM32_IRQ_TIM1BRK (STM32_IRQ_FIRST+24) /* 24: TIM1 Break interrupt */
#define STM32_IRQ_TIM9 (STM32_IRQ_FIRST+24) /* 24: TIM9 global interrupt */
#define STM32_IRQ_TIM1UP (STM32_IRQ_FIRST+25) /* 25: TIM1 Update interrupt */
#define STM32_IRQ_TIM10 (STM32_IRQ_FIRST+25) /* 25: TIM10 global interrupt */
#define STM32_IRQ_TIM1TRGCOM (STM32_IRQ_FIRST+26) /* 26: TIM1 Trigger and Commutation interrupts */
#define STM32_IRQ_TIM11 (STM32_IRQ_FIRST+26) /* 26: TIM11 global interrupt */
#define STM32_IRQ_TIM1CC (STM32_IRQ_FIRST+27) /* 27: TIM1 Capture Compare interrupt */
#define STM32_IRQ_TIM2 (STM32_IRQ_FIRST+28) /* 28: TIM2 global interrupt */
#define STM32_IRQ_TIM3 (STM32_IRQ_FIRST+29) /* 29: TIM3 global interrupt */
#define STM32_IRQ_TIM4 (STM32_IRQ_FIRST+30) /* 30: TIM4 global interrupt */
#define STM32_IRQ_I2C1EV (STM32_IRQ_FIRST+31) /* 31: I2C1 event interrupt */
#define STM32_IRQ_I2C1ER (STM32_IRQ_FIRST+32) /* 32: I2C1 error interrupt */
#define STM32_IRQ_I2C2EV (STM32_IRQ_FIRST+33) /* 33: I2C2 event interrupt */
#define STM32_IRQ_I2C2ER (STM32_IRQ_FIRST+34) /* 34: I2C2 error interrupt */
#define STM32_IRQ_SPI1 (STM32_IRQ_FIRST+35) /* 35: SPI1 global interrupt */
#define STM32_IRQ_SPI2 (STM32_IRQ_FIRST+36) /* 36: SPI2 global interrupt */
#define STM32_IRQ_USART1 (STM32_IRQ_FIRST+37) /* 37: USART1 global interrupt */
#define STM32_IRQ_USART2 (STM32_IRQ_FIRST+38) /* 38: USART2 global interrupt */
#define STM32_IRQ_USART3 (STM32_IRQ_FIRST+39) /* 39: USART3 global interrupt */
#define STM32_IRQ_EXTI1510 (STM32_IRQ_FIRST+40) /* 40: EXTI Line[15:10] interrupts */
#define STM32_IRQ_RTCALRM (STM32_IRQ_FIRST+41) /* 41: RTC alarm through EXTI line interrupt */
#define STM32_IRQ_OTGFSWKUP (STM32_IRQ_FIRST+42) /* 42: USB On-The-Go FS Wakeup through EXTI line interrupt */
#define STM32_IRQ_TIM8BRK (STM32_IRQ_FIRST+43) /* 43: TIM8 Break interrupt */
#define STM32_IRQ_TIM12 (STM32_IRQ_FIRST+43) /* 43: TIM12 global interrupt */
#define STM32_IRQ_TIM8UP (STM32_IRQ_FIRST+44) /* 44: TIM8 Update interrupt */
#define STM32_IRQ_TIM13 (STM32_IRQ_FIRST+44) /* 44: TIM13 global interrupt */
#define STM32_IRQ_TIM8TRGCOM (STM32_IRQ_FIRST+45) /* 45: TIM8 Trigger and Commutation interrupts */
#define STM32_IRQ_TIM14 (STM32_IRQ_FIRST+45) /* 45: TIM14 global interrupt */
#define STM32_IRQ_TIM8CC (STM32_IRQ_FIRST+46) /* 46: TIM8 Capture Compare interrupt */
#define STM32_IRQ_DMA1S7 (STM32_IRQ_FIRST+47) /* 47: DMA1 Stream 7 global interrupt */
#define STM32_IRQ_FSMC (STM32_IRQ_FIRST+48) /* 48: FSMC global interrupt */
#define STM32_IRQ_SDIO (STM32_IRQ_FIRST+49) /* 49: SDIO global interrupt */
#define STM32_IRQ_TIM5 (STM32_IRQ_FIRST+50) /* 50: TIM5 global interrupt */
#define STM32_IRQ_SPI3 (STM32_IRQ_FIRST+51) /* 51: SPI3 global interrupt */
#define STM32_IRQ_UART4 (STM32_IRQ_FIRST+52) /* 52: UART4 global interrupt */
#define STM32_IRQ_UART5 (STM32_IRQ_FIRST+53) /* 53: UART5 global interrupt */
#define STM32_IRQ_TIM6 (STM32_IRQ_FIRST+54) /* 54: TIM6 global interrupt */
#define STM32_IRQ_DAC (STM32_IRQ_FIRST+54) /* 54: DAC1 and DAC2 underrun error interrupts */
#define STM32_IRQ_TIM7 (STM32_IRQ_FIRST+55) /* 55: TIM7 global interrupt */
#define STM32_IRQ_DMA2S0 (STM32_IRQ_FIRST+56) /* 56: DMA2 Stream 0 global interrupt */
#define STM32_IRQ_DMA2S1 (STM32_IRQ_FIRST+57) /* 57: DMA2 Stream 1 global interrupt */
#define STM32_IRQ_DMA2S2 (STM32_IRQ_FIRST+58) /* 58: DMA2 Stream 2 global interrupt */
#define STM32_IRQ_DMA2S3 (STM32_IRQ_FIRST+59) /* 59: DMA2 Stream 3 global interrupt */
#define STM32_IRQ_DMA2S4 (STM32_IRQ_FIRST+60) /* 60: DMA2 Stream 4 global interrupt */
#define STM32_IRQ_ETH (STM32_IRQ_FIRST+61) /* 61: Ethernet global interrupt */
#define STM32_IRQ_ETHWKUP (STM32_IRQ_FIRST+62) /* 62: Ethernet Wakeup through EXTI line interrupt */
#define STM32_IRQ_CAN2TX (STM32_IRQ_FIRST+63) /* 63: CAN2 TX interrupts */
#define STM32_IRQ_CAN2RX0 (STM32_IRQ_FIRST+64) /* 64: CAN2 RX0 interrupts */
#define STM32_IRQ_CAN2RX1 (STM32_IRQ_FIRST+65) /* 65: CAN2 RX1 interrupt */
#define STM32_IRQ_CAN2SCE (STM32_IRQ_FIRST+66) /* 66: CAN2 SCE interrupt */
#define STM32_IRQ_OTGFS (STM32_IRQ_FIRST+67) /* 67: USB On The Go FS global interrupt */
#define STM32_IRQ_DMA2S5 (STM32_IRQ_FIRST+68) /* 68: DMA2 Stream 5 global interrupt */
#define STM32_IRQ_DMA2S6 (STM32_IRQ_FIRST+69) /* 69: DMA2 Stream 6 global interrupt */
#define STM32_IRQ_DMA2S7 (STM32_IRQ_FIRST+70) /* 70: DMA2 Stream 7 global interrupt */
#define STM32_IRQ_USART6 (STM32_IRQ_FIRST+71) /* 71: USART6 global interrupt */
#define STM32_IRQ_I2C3EV (STM32_IRQ_FIRST+72) /* 72: I2C3 event interrupt */
#define STM32_IRQ_I2C3ER (STM32_IRQ_FIRST+73) /* 73: I2C3 error interrupt */
#define STM32_IRQ_OTGHSEP1OUT (STM32_IRQ_FIRST+74) /* 74: USB On The Go HS End Point 1 Out global interrupt */
#define STM32_IRQ_OTGHSEP1IN (STM32_IRQ_FIRST+75) /* 75: USB On The Go HS End Point 1 In global interrupt */
#define STM32_IRQ_OTGHSWKUP (STM32_IRQ_FIRST+76) /* 76: USB On The Go HS Wakeup through EXTI interrupt */
#define STM32_IRQ_OTGHS (STM32_IRQ_FIRST+77) /* 77: USB On The Go HS global interrupt */
#define STM32_IRQ_DCMI (STM32_IRQ_FIRST+78) /* 78: DCMI global interrupt */
#define STM32_IRQ_CRYP (STM32_IRQ_FIRST+79) /* 79: CRYP crypto global interrupt */
#define STM32_IRQ_HASH (STM32_IRQ_FIRST+80) /* 80: Hash and Rng global interrupt */
#define STM32_IRQ_RNG (STM32_IRQ_FIRST+80) /* 80: Hash and Rng global interrupt */
#define STM32_IRQ_FPU (STM32_IRQ_FIRST+81) /* 81: FPU global interrupt */
#define NR_VECTORS (STM32_IRQ_FIRST+82)
#define NR_IRQS (STM32_IRQ_FIRST+82)
/****************************************************************************************************
* Public Types
****************************************************************************************************/
/****************************************************************************************************
* Public Data
****************************************************************************************************/
#ifndef __ASSEMBLY__
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************************************
* Public Functions
****************************************************************************************************/
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif
#endif /* __ARCH_ARM_INCLUDE_STM32_STM32F40XXX_IRQ_H */

208
arch/arm/include/stm32/stm32f42xxx_irq.h
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@ -1,208 +0,0 @@
/****************************************************************************************************
* arch/arm/include/stm32s/stm32f42xxx_irq.h
*
* Copyright (C) 2014-2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************************************/
/* This file should never be included directed but, rather,
* only indirectly through nuttx/irq.h
*/
#ifndef __ARCH_ARM_INCLUDE_STM32_STM32F40XXX_IRQ_H
#define __ARCH_ARM_INCLUDE_STM32_STM32F40XXX_IRQ_H
/****************************************************************************************************
* Included Files
****************************************************************************************************/
#include <nuttx/config.h>
#include <nuttx/irq.h>
#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429)
/****************************************************************************************************
* Pre-processor Definitions
****************************************************************************************************/
/* IRQ numbers. The IRQ number corresponds vector number and hence map directly to
* bits in the NVIC. This does, however, waste several words of memory in the IRQ
* to handle mapping tables.
*
* Processor Exceptions (vectors 0-15). These common definitions can be found
* in nuttx/arch/arm/include/stm32/irq.h
*
* External interrupts (vectors >= 16)
*/
#define STM32_IRQ_WWDG (STM32_IRQ_FIRST+0) /* 0: Window Watchdog interrupt */
#define STM32_IRQ_PVD (STM32_IRQ_FIRST+1) /* 1: PVD through EXTI Line detection interrupt */
#define STM32_IRQ_TAMPER (STM32_IRQ_FIRST+2) /* 2: Tamper and time stamp interrupts */
#define STM32_IRQ_TIMESTAMP (STM32_IRQ_FIRST+2) /* 2: Tamper and time stamp interrupts */
#define STM32_IRQ_RTC_WKUP (STM32_IRQ_FIRST+3) /* 3: RTC global interrupt */
#define STM32_IRQ_FLASH (STM32_IRQ_FIRST+4) /* 4: Flash global interrupt */
#define STM32_IRQ_RCC (STM32_IRQ_FIRST+5) /* 5: RCC global interrupt */
#define STM32_IRQ_EXTI0 (STM32_IRQ_FIRST+6) /* 6: EXTI Line 0 interrupt */
#define STM32_IRQ_EXTI1 (STM32_IRQ_FIRST+7) /* 7: EXTI Line 1 interrupt */
#define STM32_IRQ_EXTI2 (STM32_IRQ_FIRST+8) /* 8: EXTI Line 2 interrupt */
#define STM32_IRQ_EXTI3 (STM32_IRQ_FIRST+9) /* 9: EXTI Line 3 interrupt */
#define STM32_IRQ_EXTI4 (STM32_IRQ_FIRST+10) /* 10: EXTI Line 4 interrupt */
#define STM32_IRQ_DMA1S0 (STM32_IRQ_FIRST+11) /* 11: DMA1 Stream 0 global interrupt */
#define STM32_IRQ_DMA1S1 (STM32_IRQ_FIRST+12) /* 12: DMA1 Stream 1 global interrupt */
#define STM32_IRQ_DMA1S2 (STM32_IRQ_FIRST+13) /* 13: DMA1 Stream 2 global interrupt */
#define STM32_IRQ_DMA1S3 (STM32_IRQ_FIRST+14) /* 14: DMA1 Stream 3 global interrupt */
#define STM32_IRQ_DMA1S4 (STM32_IRQ_FIRST+15) /* 15: DMA1 Stream 4 global interrupt */
#define STM32_IRQ_DMA1S5 (STM32_IRQ_FIRST+16) /* 16: DMA1 Stream 5 global interrupt */
#define STM32_IRQ_DMA1S6 (STM32_IRQ_FIRST+17) /* 17: DMA1 Stream 6 global interrupt */
#define STM32_IRQ_ADC (STM32_IRQ_FIRST+18) /* 18: ADC1, ADC2, and ADC3 global interrupt */
#define STM32_IRQ_CAN1TX (STM32_IRQ_FIRST+19) /* 19: CAN1 TX interrupts */
#define STM32_IRQ_CAN1RX0 (STM32_IRQ_FIRST+20) /* 20: CAN1 RX0 interrupts */
#define STM32_IRQ_CAN1RX1 (STM32_IRQ_FIRST+21) /* 21: CAN1 RX1 interrupt */
#define STM32_IRQ_CAN1SCE (STM32_IRQ_FIRST+22) /* 22: CAN1 SCE interrupt */
#define STM32_IRQ_EXTI95 (STM32_IRQ_FIRST+23) /* 23: EXTI Line[9:5] interrupts */
#define STM32_IRQ_TIM1BRK (STM32_IRQ_FIRST+24) /* 24: TIM1 Break interrupt */
#define STM32_IRQ_TIM9 (STM32_IRQ_FIRST+24) /* 24: TIM9 global interrupt */
#define STM32_IRQ_TIM1UP (STM32_IRQ_FIRST+25) /* 25: TIM1 Update interrupt */
#define STM32_IRQ_TIM10 (STM32_IRQ_FIRST+25) /* 25: TIM10 global interrupt */
#define STM32_IRQ_TIM1TRGCOM (STM32_IRQ_FIRST+26) /* 26: TIM1 Trigger and Commutation interrupts */
#define STM32_IRQ_TIM11 (STM32_IRQ_FIRST+26) /* 26: TIM11 global interrupt */
#define STM32_IRQ_TIM1CC (STM32_IRQ_FIRST+27) /* 27: TIM1 Capture Compare interrupt */
#define STM32_IRQ_TIM2 (STM32_IRQ_FIRST+28) /* 28: TIM2 global interrupt */
#define STM32_IRQ_TIM3 (STM32_IRQ_FIRST+29) /* 29: TIM3 global interrupt */
#define STM32_IRQ_TIM4 (STM32_IRQ_FIRST+30) /* 30: TIM4 global interrupt */
#define STM32_IRQ_I2C1EV (STM32_IRQ_FIRST+31) /* 31: I2C1 event interrupt */
#define STM32_IRQ_I2C1ER (STM32_IRQ_FIRST+32) /* 32: I2C1 error interrupt */
#define STM32_IRQ_I2C2EV (STM32_IRQ_FIRST+33) /* 33: I2C2 event interrupt */
#define STM32_IRQ_I2C2ER (STM32_IRQ_FIRST+34) /* 34: I2C2 error interrupt */
#define STM32_IRQ_SPI1 (STM32_IRQ_FIRST+35) /* 35: SPI1 global interrupt */
#define STM32_IRQ_SPI2 (STM32_IRQ_FIRST+36) /* 36: SPI2 global interrupt */
#define STM32_IRQ_USART1 (STM32_IRQ_FIRST+37) /* 37: USART1 global interrupt */
#define STM32_IRQ_USART2 (STM32_IRQ_FIRST+38) /* 38: USART2 global interrupt */
#define STM32_IRQ_USART3 (STM32_IRQ_FIRST+39) /* 39: USART3 global interrupt */
#define STM32_IRQ_EXTI1510 (STM32_IRQ_FIRST+40) /* 40: EXTI Line[15:10] interrupts */
#define STM32_IRQ_RTCALRM (STM32_IRQ_FIRST+41) /* 41: RTC alarm through EXTI line interrupt */
#define STM32_IRQ_OTGFSWKUP (STM32_IRQ_FIRST+42) /* 42: USB On-The-Go FS Wakeup through EXTI line interrupt */
#define STM32_IRQ_TIM8BRK (STM32_IRQ_FIRST+43) /* 43: TIM8 Break interrupt */
#define STM32_IRQ_TIM12 (STM32_IRQ_FIRST+43) /* 43: TIM12 global interrupt */
#define STM32_IRQ_TIM8UP (STM32_IRQ_FIRST+44) /* 44: TIM8 Update interrupt */
#define STM32_IRQ_TIM13 (STM32_IRQ_FIRST+44) /* 44: TIM13 global interrupt */
#define STM32_IRQ_TIM8TRGCOM (STM32_IRQ_FIRST+45) /* 45: TIM8 Trigger and Commutation interrupts */
#define STM32_IRQ_TIM14 (STM32_IRQ_FIRST+45) /* 45: TIM14 global interrupt */
#define STM32_IRQ_TIM8CC (STM32_IRQ_FIRST+46) /* 46: TIM8 Capture Compare interrupt */
#define STM32_IRQ_DMA1S7 (STM32_IRQ_FIRST+47) /* 47: DMA1 Stream 7 global interrupt */
#define STM32_IRQ_FSMC (STM32_IRQ_FIRST+48) /* 48: FSMC global interrupt */
#define STM32_IRQ_SDIO (STM32_IRQ_FIRST+49) /* 49: SDIO global interrupt */
#define STM32_IRQ_TIM5 (STM32_IRQ_FIRST+50) /* 50: TIM5 global interrupt */
#define STM32_IRQ_SPI3 (STM32_IRQ_FIRST+51) /* 51: SPI3 global interrupt */
#define STM32_IRQ_UART4 (STM32_IRQ_FIRST+52) /* 52: UART4 global interrupt */
#define STM32_IRQ_UART5 (STM32_IRQ_FIRST+53) /* 53: UART5 global interrupt */
#define STM32_IRQ_TIM6 (STM32_IRQ_FIRST+54) /* 54: TIM6 global interrupt */
#define STM32_IRQ_DAC (STM32_IRQ_FIRST+54) /* 54: DAC1 and DAC2 underrun error interrupts */
#define STM32_IRQ_TIM7 (STM32_IRQ_FIRST+55) /* 55: TIM7 global interrupt */
#define STM32_IRQ_DMA2S0 (STM32_IRQ_FIRST+56) /* 56: DMA2 Stream 0 global interrupt */
#define STM32_IRQ_DMA2S1 (STM32_IRQ_FIRST+57) /* 57: DMA2 Stream 1 global interrupt */
#define STM32_IRQ_DMA2S2 (STM32_IRQ_FIRST+58) /* 58: DMA2 Stream 2 global interrupt */
#define STM32_IRQ_DMA2S3 (STM32_IRQ_FIRST+59) /* 59: DMA2 Stream 3 global interrupt */
#define STM32_IRQ_DMA2S4 (STM32_IRQ_FIRST+60) /* 60: DMA2 Stream 4 global interrupt */
#define STM32_IRQ_ETH (STM32_IRQ_FIRST+61) /* 61: Ethernet global interrupt */
#define STM32_IRQ_ETHWKUP (STM32_IRQ_FIRST+62) /* 62: Ethernet Wakeup through EXTI line interrupt */
#define STM32_IRQ_CAN2TX (STM32_IRQ_FIRST+63) /* 63: CAN2 TX interrupts */
#define STM32_IRQ_CAN2RX0 (STM32_IRQ_FIRST+64) /* 64: CAN2 RX0 interrupts */
#define STM32_IRQ_CAN2RX1 (STM32_IRQ_FIRST+65) /* 65: CAN2 RX1 interrupt */
#define STM32_IRQ_CAN2SCE (STM32_IRQ_FIRST+66) /* 66: CAN2 SCE interrupt */
#define STM32_IRQ_OTGFS (STM32_IRQ_FIRST+67) /* 67: USB On The Go FS global interrupt */
#define STM32_IRQ_DMA2S5 (STM32_IRQ_FIRST+68) /* 68: DMA2 Stream 5 global interrupt */
#define STM32_IRQ_DMA2S6 (STM32_IRQ_FIRST+69) /* 69: DMA2 Stream 6 global interrupt */
#define STM32_IRQ_DMA2S7 (STM32_IRQ_FIRST+70) /* 70: DMA2 Stream 7 global interrupt */
#define STM32_IRQ_USART6 (STM32_IRQ_FIRST+71) /* 71: USART6 global interrupt */
#define STM32_IRQ_I2C3EV (STM32_IRQ_FIRST+72) /* 72: I2C3 event interrupt */
#define STM32_IRQ_I2C3ER (STM32_IRQ_FIRST+73) /* 73: I2C3 error interrupt */
#define STM32_IRQ_OTGHSEP1OUT (STM32_IRQ_FIRST+74) /* 74: USB On The Go HS End Point 1 Out global interrupt */
#define STM32_IRQ_OTGHSEP1IN (STM32_IRQ_FIRST+75) /* 75: USB On The Go HS End Point 1 In global interrupt */
#define STM32_IRQ_OTGHSWKUP (STM32_IRQ_FIRST+76) /* 76: USB On The Go HS Wakeup through EXTI interrupt */
#define STM32_IRQ_OTGHS (STM32_IRQ_FIRST+77) /* 77: USB On The Go HS global interrupt */
#define STM32_IRQ_DCMI (STM32_IRQ_FIRST+78) /* 78: DCMI global interrupt */
#define STM32_IRQ_CRYP (STM32_IRQ_FIRST+79) /* 79: CRYP crypto global interrupt */
#define STM32_IRQ_HASH (STM32_IRQ_FIRST+80) /* 80: Hash and Rng global interrupt */
#define STM32_IRQ_RNG (STM32_IRQ_FIRST+80) /* 80: Hash and Rng global interrupt */
#define STM32_IRQ_FPU (STM32_IRQ_FIRST+81) /* 81: FPU global interrupt */
#define STM32_IRQ_UART7 (STM32_IRQ_FIRST+82) /* 82: UART7 interrupt */
#define STM32_IRQ_UART8 (STM32_IRQ_FIRST+83) /* 83: UART8 interrupt */
#define STM32_IRQ_SPI4 (STM32_IRQ_FIRST+84) /* 84: SPI4 interrupt */
#define STM32_IRQ_SPI5 (STM32_IRQ_FIRST+85) /* 85: SPI5 interrupt */
#define STM32_IRQ_SPI6 (STM32_IRQ_FIRST+86) /* 86: SPI6 interrupt */
#if defined(CONFIG_STM32_STM32F429)
# define STM32_IRQ_SAI1 (STM32_IRQ_FIRST+87) /* 87: SAI1 interrupt */
# define STM32_IRQ_LTDCINT (STM32_IRQ_FIRST+88) /* 88: LTDCINT interrupt */
# define STM32_IRQ_LTDCERRINT (STM32_IRQ_FIRST+89) /* 89: LTDCERRINT interrupt */
# define STM32_IRQ_DMA2D (STM32_IRQ_FIRST+90) /* 90: DMA2D interrupt */
# define NR_VECTORS (STM32_IRQ_FIRST+91)
# define NR_IRQS (STM32_IRQ_FIRST+91)
#else /* if defined(CONFIG_STM32_STM32F427) */
# define NR_VECTORS (STM32_IRQ_FIRST+87)
# define NR_IRQS (STM32_IRQ_FIRST+87)
#endif
/****************************************************************************************************
* Public Types
****************************************************************************************************/
/****************************************************************************************************
* Public Data
****************************************************************************************************/
#ifndef __ASSEMBLY__
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************************************
* Public Functions
****************************************************************************************************/
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif
#endif /* CONFIG_STM32_STM32F427 || CONFIG_STM32_STM32F429 */
#endif /* __ARCH_ARM_INCLUDE_STM32_STM32F40XXX_IRQ_H */

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arch/arm/include/stm32/stm32f44xxx_irq.h
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@ -1,205 +0,0 @@
/****************************************************************************************************
* arch/arm/include/stm32s/stm32f44xxx_irq.h
*
* Copyright (C) 2014-2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
* David Sidrane <david_s5@nscdg.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************************************/
/* This file should never be included directed but, rather,
* only indirectly through nuttx/irq.h
*/
#ifndef __ARCH_ARM_INCLUDE_STM32F44XXX_IRQ_H
#define __ARCH_ARM_INCLUDE_STM32F44XXX_IRQ_H
/****************************************************************************************************
* Included Files
****************************************************************************************************/
#include <nuttx/config.h>
#include <nuttx/irq.h>
#if defined(CONFIG_STM32_STM32F446)
/****************************************************************************************************
* Pre-processor Definitions
****************************************************************************************************/
/* IRQ numbers. The IRQ number corresponds vector number and hence map directly to
* bits in the NVIC. This does, however, waste several words of memory in the IRQ
* to handle mapping tables.
*
* Processor Exceptions (vectors 0-15). These common definitions can be found
* in nuttx/arch/arm/include/stm32/irq.h
*
* External interrupts (vectors >= 16)
*/
#define STM32_IRQ_WWDG (STM32_IRQ_FIRST+0) /* 0: Window Watchdog interrupt */
#define STM32_IRQ_PVD (STM32_IRQ_FIRST+1) /* 1: PVD through EXTI Line detection interrupt */
#define STM32_IRQ_TAMPER (STM32_IRQ_FIRST+2) /* 2: Tamper and time stamp interrupts */
#define STM32_IRQ_TIMESTAMP (STM32_IRQ_FIRST+2) /* 2: Tamper and time stamp interrupts */
#define STM32_IRQ_RTC_WKUP (STM32_IRQ_FIRST+3) /* 3: RTC global interrupt */
#define STM32_IRQ_FLASH (STM32_IRQ_FIRST+4) /* 4: Flash global interrupt */
#define STM32_IRQ_RCC (STM32_IRQ_FIRST+5) /* 5: RCC global interrupt */
#define STM32_IRQ_EXTI0 (STM32_IRQ_FIRST+6) /* 6: EXTI Line 0 interrupt */
#define STM32_IRQ_EXTI1 (STM32_IRQ_FIRST+7) /* 7: EXTI Line 1 interrupt */
#define STM32_IRQ_EXTI2 (STM32_IRQ_FIRST+8) /* 8: EXTI Line 2 interrupt */
#define STM32_IRQ_EXTI3 (STM32_IRQ_FIRST+9) /* 9: EXTI Line 3 interrupt */
#define STM32_IRQ_EXTI4 (STM32_IRQ_FIRST+10) /* 10: EXTI Line 4 interrupt */
#define STM32_IRQ_DMA1S0 (STM32_IRQ_FIRST+11) /* 11: DMA1 Stream 0 global interrupt */
#define STM32_IRQ_DMA1S1 (STM32_IRQ_FIRST+12) /* 12: DMA1 Stream 1 global interrupt */
#define STM32_IRQ_DMA1S2 (STM32_IRQ_FIRST+13) /* 13: DMA1 Stream 2 global interrupt */
#define STM32_IRQ_DMA1S3 (STM32_IRQ_FIRST+14) /* 14: DMA1 Stream 3 global interrupt */
#define STM32_IRQ_DMA1S4 (STM32_IRQ_FIRST+15) /* 15: DMA1 Stream 4 global interrupt */
#define STM32_IRQ_DMA1S5 (STM32_IRQ_FIRST+16) /* 16: DMA1 Stream 5 global interrupt */
#define STM32_IRQ_DMA1S6 (STM32_IRQ_FIRST+17) /* 17: DMA1 Stream 6 global interrupt */
#define STM32_IRQ_ADC (STM32_IRQ_FIRST+18) /* 18: ADC1, ADC2, and ADC3 global interrupt */
#define STM32_IRQ_CAN1TX (STM32_IRQ_FIRST+19) /* 19: CAN1 TX interrupts */
#define STM32_IRQ_CAN1RX0 (STM32_IRQ_FIRST+20) /* 20: CAN1 RX0 interrupts */
#define STM32_IRQ_CAN1RX1 (STM32_IRQ_FIRST+21) /* 21: CAN1 RX1 interrupt */
#define STM32_IRQ_CAN1SCE (STM32_IRQ_FIRST+22) /* 22: CAN1 SCE interrupt */
#define STM32_IRQ_EXTI95 (STM32_IRQ_FIRST+23) /* 23: EXTI Line[9:5] interrupts */
#define STM32_IRQ_TIM1BRK (STM32_IRQ_FIRST+24) /* 24: TIM1 Break interrupt */
#define STM32_IRQ_TIM9 (STM32_IRQ_FIRST+24) /* 24: TIM9 global interrupt */
#define STM32_IRQ_TIM1UP (STM32_IRQ_FIRST+25) /* 25: TIM1 Update interrupt */
#define STM32_IRQ_TIM10 (STM32_IRQ_FIRST+25) /* 25: TIM10 global interrupt */
#define STM32_IRQ_TIM1TRGCOM (STM32_IRQ_FIRST+26) /* 26: TIM1 Trigger and Commutation interrupts */
#define STM32_IRQ_TIM11 (STM32_IRQ_FIRST+26) /* 26: TIM11 global interrupt */
#define STM32_IRQ_TIM1CC (STM32_IRQ_FIRST+27) /* 27: TIM1 Capture Compare interrupt */
#define STM32_IRQ_TIM2 (STM32_IRQ_FIRST+28) /* 28: TIM2 global interrupt */
#define STM32_IRQ_TIM3 (STM32_IRQ_FIRST+29) /* 29: TIM3 global interrupt */
#define STM32_IRQ_TIM4 (STM32_IRQ_FIRST+30) /* 30: TIM4 global interrupt */
#define STM32_IRQ_I2C1EV (STM32_IRQ_FIRST+31) /* 31: I2C1 event interrupt */
#define STM32_IRQ_I2C1ER (STM32_IRQ_FIRST+32) /* 32: I2C1 error interrupt */
#define STM32_IRQ_I2C2EV (STM32_IRQ_FIRST+33) /* 33: I2C2 event interrupt */
#define STM32_IRQ_I2C2ER (STM32_IRQ_FIRST+34) /* 34: I2C2 error interrupt */
#define STM32_IRQ_SPI1 (STM32_IRQ_FIRST+35) /* 35: SPI1 global interrupt */
#define STM32_IRQ_SPI2 (STM32_IRQ_FIRST+36) /* 36: SPI2 global interrupt */
#define STM32_IRQ_USART1 (STM32_IRQ_FIRST+37) /* 37: USART1 global interrupt */
#define STM32_IRQ_USART2 (STM32_IRQ_FIRST+38) /* 38: USART2 global interrupt */
#define STM32_IRQ_USART3 (STM32_IRQ_FIRST+39) /* 39: USART3 global interrupt */
#define STM32_IRQ_EXTI1510 (STM32_IRQ_FIRST+40) /* 40: EXTI Line[15:10] interrupts */
#define STM32_IRQ_RTCALRM (STM32_IRQ_FIRST+41) /* 41: RTC alarm through EXTI line interrupt */
#define STM32_IRQ_OTGFSWKUP (STM32_IRQ_FIRST+42) /* 42: USB On-The-Go FS Wakeup through EXTI line interrupt */
#define STM32_IRQ_TIM8BRK (STM32_IRQ_FIRST+43) /* 43: TIM8 Break interrupt */
#define STM32_IRQ_TIM12 (STM32_IRQ_FIRST+43) /* 43: TIM12 global interrupt */
#define STM32_IRQ_TIM8UP (STM32_IRQ_FIRST+44) /* 44: TIM8 Update interrupt */
#define STM32_IRQ_TIM13 (STM32_IRQ_FIRST+44) /* 44: TIM13 global interrupt */
#define STM32_IRQ_TIM8TRGCOM (STM32_IRQ_FIRST+45) /* 45: TIM8 Trigger and Commutation interrupts */
#define STM32_IRQ_TIM14 (STM32_IRQ_FIRST+45) /* 45: TIM14 global interrupt */
#define STM32_IRQ_TIM8CC (STM32_IRQ_FIRST+46) /* 46: TIM8 Capture Compare interrupt */
#define STM32_IRQ_DMA1S7 (STM32_IRQ_FIRST+47) /* 47: DMA1 Stream 7 global interrupt */
#define STM32_IRQ_FSMC (STM32_IRQ_FIRST+48) /* 48: FSMC global interrupt */
#define STM32_IRQ_SDIO (STM32_IRQ_FIRST+49) /* 49: SDIO global interrupt */
#define STM32_IRQ_TIM5 (STM32_IRQ_FIRST+50) /* 50: TIM5 global interrupt */
#define STM32_IRQ_SPI3 (STM32_IRQ_FIRST+51) /* 51: SPI3 global interrupt */
#define STM32_IRQ_UART4 (STM32_IRQ_FIRST+52) /* 52: UART4 global interrupt */
#define STM32_IRQ_UART5 (STM32_IRQ_FIRST+53) /* 53: UART5 global interrupt */
#define STM32_IRQ_TIM6 (STM32_IRQ_FIRST+54) /* 54: TIM6 global interrupt */
#define STM32_IRQ_DAC (STM32_IRQ_FIRST+54) /* 54: DAC1 and DAC2 underrun error interrupts */
#define STM32_IRQ_TIM7 (STM32_IRQ_FIRST+55) /* 55: TIM7 global interrupt */
#define STM32_IRQ_DMA2S0 (STM32_IRQ_FIRST+56) /* 56: DMA2 Stream 0 global interrupt */
#define STM32_IRQ_DMA2S1 (STM32_IRQ_FIRST+57) /* 57: DMA2 Stream 1 global interrupt */
#define STM32_IRQ_DMA2S2 (STM32_IRQ_FIRST+58) /* 58: DMA2 Stream 2 global interrupt */
#define STM32_IRQ_DMA2S3 (STM32_IRQ_FIRST+59) /* 59: DMA2 Stream 3 global interrupt */
#define STM32_IRQ_DMA2S4 (STM32_IRQ_FIRST+60) /* 60: DMA2 Stream 4 global interrupt */
#define STM32_IRQ_RES01 (STM32_IRQ_FIRST+61) /* 61: 1st Reserved (Ethernet global) interrupt */
#define STM32_IRQ_RES02 (STM32_IRQ_FIRST+62) /* 62: 2nd Reserved (Ethernet Wakeup through EXTI line) interrupt */
#define STM32_IRQ_CAN2TX (STM32_IRQ_FIRST+63) /* 63: CAN2 TX interrupts */
#define STM32_IRQ_CAN2RX0 (STM32_IRQ_FIRST+64) /* 64: CAN2 RX0 interrupts */
#define STM32_IRQ_CAN2RX1 (STM32_IRQ_FIRST+65) /* 65: CAN2 RX1 interrupt */
#define STM32_IRQ_CAN2SCE (STM32_IRQ_FIRST+66) /* 66: CAN2 SCE interrupt */
#define STM32_IRQ_OTGFS (STM32_IRQ_FIRST+67) /* 67: USB On The Go FS global interrupt */
#define STM32_IRQ_DMA2S5 (STM32_IRQ_FIRST+68) /* 68: DMA2 Stream 5 global interrupt */
#define STM32_IRQ_DMA2S6 (STM32_IRQ_FIRST+69) /* 69: DMA2 Stream 6 global interrupt */
#define STM32_IRQ_DMA2S7 (STM32_IRQ_FIRST+70) /* 70: DMA2 Stream 7 global interrupt */
#define STM32_IRQ_USART6 (STM32_IRQ_FIRST+71) /* 71: USART6 global interrupt */
#define STM32_IRQ_I2C3EV (STM32_IRQ_FIRST+72) /* 72: I2C3 event interrupt */
#define STM32_IRQ_I2C3ER (STM32_IRQ_FIRST+73) /* 73: I2C3 error interrupt */
#define STM32_IRQ_OTGHSEP1OUT (STM32_IRQ_FIRST+74) /* 74: USB On The Go HS End Point 1 Out global interrupt */
#define STM32_IRQ_OTGHSEP1IN (STM32_IRQ_FIRST+75) /* 75: USB On The Go HS End Point 1 In global interrupt */
#define STM32_IRQ_OTGHSWKUP (STM32_IRQ_FIRST+76) /* 76: USB On The Go HS Wakeup through EXTI interrupt */
#define STM32_IRQ_OTGHS (STM32_IRQ_FIRST+77) /* 77: USB On The Go HS global interrupt */
#define STM32_IRQ_DCMI (STM32_IRQ_FIRST+78) /* 78: DCMI global interrupt */
#define STM32_IRQ_RES03 (STM32_IRQ_FIRST+79) /* 79: 3rd Reserved (CRYP crypto global) interrupt */
#define STM32_IRQ_RES04 (STM32_IRQ_FIRST+80) /* 80: 4th Reserved (Hash and Rng global) interrupt */
#define STM32_IRQ_FPU (STM32_IRQ_FIRST+81) /* 81: FPU global interrupt */
#define STM32_IRQ_RES05 (STM32_IRQ_FIRST+82) /* 82: 5th Reserved (UART7)interrupt */
#define STM32_IRQ_RES06 (STM32_IRQ_FIRST+83) /* 83: 6th Reserved (UART8) interrupt */
#define STM32_IRQ_SPI4 (STM32_IRQ_FIRST+84) /* 84: SPI4 interrupt */
#define STM32_IRQ_RES07 (STM32_IRQ_FIRST+85) /* 85: 7th Reserved (SPI5) interrupt */
#define STM32_IRQ_RES08 (STM32_IRQ_FIRST+86) /* 86: 8th Reserved (SPI6) interrupt */
#define STM32_IRQ_SAI1 (STM32_IRQ_FIRST+87) /* 87: SAI1 interrupt */
#define STM32_IRQ_RES09 (STM32_IRQ_FIRST+88) /* 88: 9th Reserved (LTDCINT interrupt */
#define STM32_IRQ_RES10 (STM32_IRQ_FIRST+89) /* 89: 10th Reserved (LTDCERRINT) interrupt */
#define STM32_IRQ_RES11 (STM32_IRQ_FIRST+90) /* 90: 11th Reserved (DMA2D) interrupt */
#define STM32_IRQ_SAI2 (STM32_IRQ_FIRST+91) /* 91: SAI2 Global interrupt */
#define STM32_IRQ_QUADSPI (STM32_IRQ_FIRST+92) /* 92: QuadSPI Global interrupt */
#define STM32_IRQ_HDMICEC (STM32_IRQ_FIRST+93) /* 93: HDMI-CEC Global interrupt */
#define STM32_IRQ_SPDIFRX (STM32_IRQ_FIRST+94) /* 94: SPDIF-Rx Global interrupt */
#define STM32_IRQ_FMPI2C1 (STM32_IRQ_FIRST+95) /* 95: FMPI2C1 event interrupt */
#define STM32_IRQ_FMPI2C1ERR (STM32_IRQ_FIRST+96) /* 96: FMPI2C1 Error event interrupt */
#define NR_VECTORS (STM32_IRQ_FIRST+97)
#define NR_IRQS (STM32_IRQ_FIRST+97)
/****************************************************************************************************
* Public Types
****************************************************************************************************/
/****************************************************************************************************
* Public Data
****************************************************************************************************/
#ifndef __ASSEMBLY__
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************************************
* Public Functions
****************************************************************************************************/
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif
#endif /* CONFIG_STM32_STM32F446 */
#endif /* __ARCH_ARM_INCLUDE_STM32F44XXX_IRQ_H */

274
arch/arm/include/stm32/stm32l15xxx_irq.h
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@ -1,274 +0,0 @@
/****************************************************************************************************
* arch/arm/include/stm32s/stm32l15xxx_irq.h
* For STM32L100xx, STM32L151xx, STM32L152xx and STM32L162xx advanced ARM-based 32-bit MCUs
*
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************************************/
/* This file should never be included directed but, rather, only indirectly through nuttx/irq.h */
#ifndef __ARCH_ARM_INCLUDE_STM32_STM32FL15XXX_IRQ_H
#define __ARCH_ARM_INCLUDE_STM32_STM32FL15XXX_IRQ_H
/****************************************************************************************************
* Included Files
****************************************************************************************************/
#include <nuttx/config.h>
#include <nuttx/irq.h>
/****************************************************************************************************
* Pre-processor Definitions
****************************************************************************************************/
/* IRQ numbers. The IRQ number corresponds vector number and hence map directly to
* bits in the NVIC. This does, however, waste several words of memory in the IRQ
* to handle mapping tables.
*
* Processor Exceptions (vectors 0-15). These common definitions can be found
* in nuttx/arch/arm/include/stm32/irq.h
*
* External interrupts (vectors >= 16) for low and medium density devices
*/
#if defined(CONFIG_STM32_LOWDENSITY) || defined(CONFIG_STM32_MEDIUMDENSITY)
# define STM32_IRQ_WWDG (STM32_IRQ_FIRST+0) /* 0: Window Watchdog interrupt */
# define STM32_IRQ_PVD (STM32_IRQ_FIRST+1) /* 1: PVD through EXTI Line detection interrupt */
# define STM32_IRQ_TAMPER (STM32_IRQ_FIRST+2) /* 2: Tamper through EXTI line interrupt, or */
# define STM32_IRQ_TIMESTAMP (STM32_IRQ_FIRST+2) /* 2: Time stamp through EXTI line interrupt */
# define STM32_IRQ_RTC_WKUP (STM32_IRQ_FIRST+3) /* 3: RTC Wakeup through EXTI line interrupt */
# define STM32_IRQ_FLASH (STM32_IRQ_FIRST+4) /* 4: Flash global interrupt */
# define STM32_IRQ_RCC (STM32_IRQ_FIRST+5) /* 5: RCC global interrupt */
# define STM32_IRQ_EXTI0 (STM32_IRQ_FIRST+6) /* 6: EXTI Line 0 interrupt */
# define STM32_IRQ_EXTI1 (STM32_IRQ_FIRST+7) /* 7: EXTI Line 1 interrupt */
# define STM32_IRQ_EXTI2 (STM32_IRQ_FIRST+8) /* 8: EXTI Line 2 interrupt */
# define STM32_IRQ_EXTI3 (STM32_IRQ_FIRST+9) /* 9: EXTI Line 3 interrupt */
# define STM32_IRQ_EXTI4 (STM32_IRQ_FIRST+10) /* 10: EXTI Line 4 interrupt */
# define STM32_IRQ_DMA1CH1 (STM32_IRQ_FIRST+11) /* 11: DMA1 channel 1 global interrupt */
# define STM32_IRQ_DMA1CH2 (STM32_IRQ_FIRST+12) /* 12: DMA1 channel 2 global interrupt */
# define STM32_IRQ_DMA1CH3 (STM32_IRQ_FIRST+13) /* 13: DMA1 channel 3 global interrupt */
# define STM32_IRQ_DMA1CH4 (STM32_IRQ_FIRST+14) /* 14: DMA1 channel 4 global interrupt */
# define STM32_IRQ_DMA1CH5 (STM32_IRQ_FIRST+15) /* 15: DMA1 channel 5 global interrupt */
# define STM32_IRQ_DMA1CH6 (STM32_IRQ_FIRST+16) /* 16: DMA1 channel 6 global interrupt */
# define STM32_IRQ_DMA1CH7 (STM32_IRQ_FIRST+17) /* 17: DMA1 channel 7 global interrupt */
# define STM32_IRQ_ADC1 (STM32_IRQ_FIRST+18) /* 18: ADC1 global interrupt */
# define STM32_IRQ_USBHP (STM32_IRQ_FIRST+19) /* 19: USB High Priority interrupts */
# define STM32_IRQ_USBLP (STM32_IRQ_FIRST+20) /* 20: USB Low Priority interrupt */
# define STM32_IRQ_DAC (STM32_IRQ_FIRST+21) /* 21: DAC interrupt */
# define STM32_IRQ_COMP (STM32_IRQ_FIRST+22) /* 22: Comparator wakeup through EXTI interrupt */
# define STM32_IRQ_EXTI95 (STM32_IRQ_FIRST+23) /* 23: EXTI Line[9:5] interrupts */
# define STM32_IRQ_LDC (STM32_IRQ_FIRST+24) /* 24: LCD global interrupt */
# define STM32_IRQ_TIM9 (STM32_IRQ_FIRST+25) /* 25: TIM9 global interrupt */
# define STM32_IRQ_TIM10 (STM32_IRQ_FIRST+26) /* 26: TIM10 global interrupt */
# define STM32_IRQ_TIM11 (STM32_IRQ_FIRST+27) /* 27: TIM11 global interrupt */
# define STM32_IRQ_TIM2 (STM32_IRQ_FIRST+28) /* 28: TIM2 global interrupt */
# define STM32_IRQ_TIM3 (STM32_IRQ_FIRST+29) /* 29: TIM3 global interrupt */
# define STM32_IRQ_TIM4 (STM32_IRQ_FIRST+30) /* 30: TIM4 global interrupt */
# define STM32_IRQ_I2C1EV (STM32_IRQ_FIRST+31) /* 31: I2C1 event interrupt */
# define STM32_IRQ_I2C1ER (STM32_IRQ_FIRST+32) /* 32: I2C1 error interrupt */
# define STM32_IRQ_I2C2EV (STM32_IRQ_FIRST+33) /* 33: I2C2 event interrupt */
# define STM32_IRQ_I2C2ER (STM32_IRQ_FIRST+34) /* 34: I2C2 error interrupt */
# define STM32_IRQ_SPI1 (STM32_IRQ_FIRST+35) /* 35: SPI1 global interrupt */
# define STM32_IRQ_SPI2 (STM32_IRQ_FIRST+36) /* 36: SPI2 global interrupt */
# define STM32_IRQ_USART1 (STM32_IRQ_FIRST+37) /* 37: USART1 global interrupt */
# define STM32_IRQ_USART2 (STM32_IRQ_FIRST+38) /* 38: USART2 global interrupt */
# define STM32_IRQ_USART3 (STM32_IRQ_FIRST+39) /* 39: USART3 global interrupt */
# define STM32_IRQ_EXTI1510 (STM32_IRQ_FIRST+40) /* 40: EXTI Line[15:10] interrupts */
# define STM32_IRQ_RTCALRM (STM32_IRQ_FIRST+41) /* 41: RTC alarm through EXTI line interrupt */
# define STM32_IRQ_USBWKUP (STM32_IRQ_FIRST+42) /* 42: USB wakeup from suspend through EXTI line interrupt */
# define STM32_IRQ_TIM6 (STM32_IRQ_FIRST+43) /* 43: TIM6 global interrupt */
# define STM32_IRQ_TIM7 (STM32_IRQ_FIRST+44) /* 44: TIM7 global interrupt */
# define NR_VECTORS (STM32_IRQ_FIRST+45)
# define NR_IRQS (STM32_IRQ_FIRST+45)
/* External interrupts (vectors >= 16) medium+ density devices */
#elif defined(CONFIG_STM32_MEDIUMPLUSDENSITY)
# define STM32_IRQ_WWDG (STM32_IRQ_FIRST+0) /* 0: Window Watchdog interrupt */
# define STM32_IRQ_PVD (STM32_IRQ_FIRST+1) /* 1: PVD through EXTI Line detection interrupt */
# define STM32_IRQ_TAMPER (STM32_IRQ_FIRST+2) /* 2: Tamper through EXTI line interrupt, or */
# define STM32_IRQ_TIMESTAMP (STM32_IRQ_FIRST+2) /* 2: Time stamp through EXTI line interrupt */
# define STM32_IRQ_RTC_WKUP (STM32_IRQ_FIRST+3) /* 3: RTC Wakeup through EXTI line interrupt */
# define STM32_IRQ_FLASH (STM32_IRQ_FIRST+4) /* 4: Flash global interrupt */
# define STM32_IRQ_RCC (STM32_IRQ_FIRST+5) /* 5: RCC global interrupt */
# define STM32_IRQ_EXTI0 (STM32_IRQ_FIRST+6) /* 6: EXTI Line 0 interrupt */
# define STM32_IRQ_EXTI1 (STM32_IRQ_FIRST+7) /* 7: EXTI Line 1 interrupt */
# define STM32_IRQ_EXTI2 (STM32_IRQ_FIRST+8) /* 8: EXTI Line 2 interrupt */
# define STM32_IRQ_EXTI3 (STM32_IRQ_FIRST+9) /* 9: EXTI Line 3 interrupt */
# define STM32_IRQ_EXTI4 (STM32_IRQ_FIRST+10) /* 10: EXTI Line 4 interrupt */
# define STM32_IRQ_DMA1CH1 (STM32_IRQ_FIRST+11) /* 11: DMA1 channel 1 global interrupt */
# define STM32_IRQ_DMA1CH2 (STM32_IRQ_FIRST+12) /* 12: DMA1 channel 2 global interrupt */
# define STM32_IRQ_DMA1CH3 (STM32_IRQ_FIRST+13) /* 13: DMA1 channel 3 global interrupt */
# define STM32_IRQ_DMA1CH4 (STM32_IRQ_FIRST+14) /* 14: DMA1 channel 4 global interrupt */
# define STM32_IRQ_DMA1CH5 (STM32_IRQ_FIRST+15) /* 15: DMA1 channel 5 global interrupt */
# define STM32_IRQ_DMA1CH6 (STM32_IRQ_FIRST+16) /* 16: DMA1 channel 6 global interrupt */
# define STM32_IRQ_DMA1CH7 (STM32_IRQ_FIRST+17) /* 17: DMA1 channel 7 global interrupt */
# define STM32_IRQ_ADC1 (STM32_IRQ_FIRST+18) /* 18: ADC1 global interrupt */
# define STM32_IRQ_USBHP (STM32_IRQ_FIRST+19) /* 19: USB High Priority interrupts */
# define STM32_IRQ_USBLP (STM32_IRQ_FIRST+20) /* 20: USB Low Priority interrupt */
# define STM32_IRQ_DAC (STM32_IRQ_FIRST+21) /* 21: DAC interrupt */
# define STM32_IRQ_COMP (STM32_IRQ_FIRST+22) /* 22: Comparator wakeup through EXTI interrupt, or */
# define STM32_IRQ_CA (STM32_IRQ_FIRST+22) /* 22: Channel acquisition interrupt */
# define STM32_IRQ_EXTI95 (STM32_IRQ_FIRST+23) /* 23: EXTI Line[9:5] interrupts */
# define STM32_IRQ_LDC (STM32_IRQ_FIRST+24) /* 24: LCD global interrupt */
# define STM32_IRQ_TIM9 (STM32_IRQ_FIRST+25) /* 25: TIM9 global interrupt */
# define STM32_IRQ_TIM10 (STM32_IRQ_FIRST+26) /* 26: TIM10 global interrupt */
# define STM32_IRQ_TIM11 (STM32_IRQ_FIRST+27) /* 27: TIM11 global interrupt */
# define STM32_IRQ_TIM2 (STM32_IRQ_FIRST+28) /* 28: TIM2 global interrupt */
# define STM32_IRQ_TIM3 (STM32_IRQ_FIRST+29) /* 29: TIM3 global interrupt */
# define STM32_IRQ_TIM4 (STM32_IRQ_FIRST+30) /* 30: TIM4 global interrupt */
# define STM32_IRQ_I2C1EV (STM32_IRQ_FIRST+31) /* 31: I2C1 event interrupt */
# define STM32_IRQ_I2C1ER (STM32_IRQ_FIRST+32) /* 32: I2C1 error interrupt */
# define STM32_IRQ_I2C2EV (STM32_IRQ_FIRST+33) /* 33: I2C2 event interrupt */
# define STM32_IRQ_I2C2ER (STM32_IRQ_FIRST+34) /* 34: I2C2 error interrupt */
# define STM32_IRQ_SPI1 (STM32_IRQ_FIRST+35) /* 35: SPI1 global interrupt */
# define STM32_IRQ_SPI2 (STM32_IRQ_FIRST+36) /* 36: SPI2 global interrupt */
# define STM32_IRQ_USART1 (STM32_IRQ_FIRST+37) /* 37: USART1 global interrupt */
# define STM32_IRQ_USART2 (STM32_IRQ_FIRST+38) /* 38: USART2 global interrupt */
# define STM32_IRQ_USART3 (STM32_IRQ_FIRST+39) /* 39: USART3 global interrupt */
# define STM32_IRQ_EXTI1510 (STM32_IRQ_FIRST+40) /* 40: EXTI Line[15:10] interrupts */
# define STM32_IRQ_RTCALRM (STM32_IRQ_FIRST+41) /* 41: RTC alarm through EXTI line interrupt */
# define STM32_IRQ_USBWKUP (STM32_IRQ_FIRST+42) /* 42: USB wakeup from suspend through EXTI line interrupt */
# define STM32_IRQ_TIM6 (STM32_IRQ_FIRST+43) /* 43: TIM6 global interrupt */
# define STM32_IRQ_TIM7 (STM32_IRQ_FIRST+44) /* 44: TIM7 global interrupt */
# define STM32_IRQ_TIM5 (STM32_IRQ_FIRST+45) /* 45: TIM5 global interrupt */
# define STM32_IRQ_SPI3 (STM32_IRQ_FIRST+46) /* 46: SPI3 global interrupt */
# define STM32_IRQ_DMA2CH1 (STM32_IRQ_FIRST+47) /* 47: DMA2 channel 1 global interrupt */
# define STM32_IRQ_DMA2CH2 (STM32_IRQ_FIRST+48) /* 48: DMA2 channel 2 global interrupt */
# define STM32_IRQ_DMA2CH3 (STM32_IRQ_FIRST+49) /* 49: DMA2 channel 3 global interrupt */
# define STM32_IRQ_DMA2CH4 (STM32_IRQ_FIRST+50) /* 50: DMA2 channel 4 global interrupt */
# define STM32_IRQ_DMA2CH5 (STM32_IRQ_FIRST+51) /* 51: DMA2 channel 5 global interrupt */
# define STM32_IRQ_AES (STM32_IRQ_FIRST+52) /* 52: AES global interrupt */
# define STM32_IRQ_COMPACQ (STM32_IRQ_FIRST+53) /* 53: Comparator Channel Acquisition Interrupt */
# define NR_VECTORS (STM32_IRQ_FIRST+54)
# define NR_IRQS (STM32_IRQ_FIRST+54)
/* External interrupts (vectors >= 16) high density devices */
#elif defined(CONFIG_STM32_HIGHDENSITY)
# define STM32_IRQ_WWDG (STM32_IRQ_FIRST+0) /* 0: Window Watchdog interrupt */
# define STM32_IRQ_PVD (STM32_IRQ_FIRST+1) /* 1: PVD through EXTI Line detection interrupt */
# define STM32_IRQ_TAMPER (STM32_IRQ_FIRST+2) /* 2: Tamper through EXTI line interrupt, or */
# define STM32_IRQ_TIMESTAMP (STM32_IRQ_FIRST+2) /* 2: Time stamp through EXTI line interrupt */
# define STM32_IRQ_RTC_WKUP (STM32_IRQ_FIRST+3) /* 3: RTC Wakeup through EXTI line interrupt */
# define STM32_IRQ_FLASH (STM32_IRQ_FIRST+4) /* 4: Flash global interrupt */
# define STM32_IRQ_RCC (STM32_IRQ_FIRST+5) /* 5: RCC global interrupt */
# define STM32_IRQ_EXTI0 (STM32_IRQ_FIRST+6) /* 6: EXTI Line 0 interrupt */
# define STM32_IRQ_EXTI1 (STM32_IRQ_FIRST+7) /* 7: EXTI Line 1 interrupt */
# define STM32_IRQ_EXTI2 (STM32_IRQ_FIRST+8) /* 8: EXTI Line 2 interrupt */
# define STM32_IRQ_EXTI3 (STM32_IRQ_FIRST+9) /* 9: EXTI Line 3 interrupt */
# define STM32_IRQ_EXTI4 (STM32_IRQ_FIRST+10) /* 10: EXTI Line 4 interrupt */
# define STM32_IRQ_DMA1CH1 (STM32_IRQ_FIRST+11) /* 11: DMA1 channel 1 global interrupt */
# define STM32_IRQ_DMA1CH2 (STM32_IRQ_FIRST+12) /* 12: DMA1 channel 2 global interrupt */
# define STM32_IRQ_DMA1CH3 (STM32_IRQ_FIRST+13) /* 13: DMA1 channel 3 global interrupt */
# define STM32_IRQ_DMA1CH4 (STM32_IRQ_FIRST+14) /* 14: DMA1 channel 4 global interrupt */
# define STM32_IRQ_DMA1CH5 (STM32_IRQ_FIRST+15) /* 15: DMA1 channel 5 global interrupt */
# define STM32_IRQ_DMA1CH6 (STM32_IRQ_FIRST+16) /* 16: DMA1 channel 6 global interrupt */
# define STM32_IRQ_DMA1CH7 (STM32_IRQ_FIRST+17) /* 17: DMA1 channel 7 global interrupt */
# define STM32_IRQ_ADC1 (STM32_IRQ_FIRST+18) /* 18: ADC1 global interrupt */
# define STM32_IRQ_USBHP (STM32_IRQ_FIRST+19) /* 19: USB High Priority interrupts */
# define STM32_IRQ_USBLP (STM32_IRQ_FIRST+20) /* 20: USB Low Priority interrupt */
# define STM32_IRQ_DAC (STM32_IRQ_FIRST+21) /* 21: DAC interrupt */
# define STM32_IRQ_COMP (STM32_IRQ_FIRST+22) /* 22: Comparator wakeup through EXTI interrupt, or */
# define STM32_IRQ_CA (STM32_IRQ_FIRST+22) /* 22: Channel acquisition interrupt */
# define STM32_IRQ_EXTI95 (STM32_IRQ_FIRST+23) /* 23: EXTI Line[9:5] interrupts */
# define STM32_IRQ_LDC (STM32_IRQ_FIRST+24) /* 24: LCD global interrupt */
# define STM32_IRQ_TIM9 (STM32_IRQ_FIRST+25) /* 25: TIM9 global interrupt */
# define STM32_IRQ_TIM10 (STM32_IRQ_FIRST+26) /* 26: TIM10 global interrupt */
# define STM32_IRQ_TIM11 (STM32_IRQ_FIRST+27) /* 27: TIM11 global interrupt */
# define STM32_IRQ_TIM2 (STM32_IRQ_FIRST+28) /* 28: TIM2 global interrupt */
# define STM32_IRQ_TIM3 (STM32_IRQ_FIRST+29) /* 29: TIM3 global interrupt */
# define STM32_IRQ_TIM4 (STM32_IRQ_FIRST+30) /* 30: TIM4 global interrupt */
# define STM32_IRQ_I2C1EV (STM32_IRQ_FIRST+31) /* 31: I2C1 event interrupt */
# define STM32_IRQ_I2C1ER (STM32_IRQ_FIRST+32) /* 32: I2C1 error interrupt */
# define STM32_IRQ_I2C2EV (STM32_IRQ_FIRST+33) /* 33: I2C2 event interrupt */
# define STM32_IRQ_I2C2ER (STM32_IRQ_FIRST+34) /* 34: I2C2 error interrupt */
# define STM32_IRQ_SPI1 (STM32_IRQ_FIRST+35) /* 35: SPI1 global interrupt */
# define STM32_IRQ_SPI2 (STM32_IRQ_FIRST+36) /* 36: SPI2 global interrupt */
# define STM32_IRQ_USART1 (STM32_IRQ_FIRST+37) /* 37: USART1 global interrupt */
# define STM32_IRQ_USART2 (STM32_IRQ_FIRST+38) /* 38: USART2 global interrupt */
# define STM32_IRQ_USART3 (STM32_IRQ_FIRST+39) /* 39: USART3 global interrupt */
# define STM32_IRQ_EXTI1510 (STM32_IRQ_FIRST+40) /* 40: EXTI Line[15:10] interrupts */
# define STM32_IRQ_RTCALRM (STM32_IRQ_FIRST+41) /* 41: RTC alarm through EXTI line interrupt */
# define STM32_IRQ_USBWKUP (STM32_IRQ_FIRST+42) /* 42: USB wakeup from suspend through EXTI line interrupt */
# define STM32_IRQ_TIM6 (STM32_IRQ_FIRST+43) /* 43: TIM6 global interrupt */
# define STM32_IRQ_TIM7 (STM32_IRQ_FIRST+44) /* 44: TIM7 global interrupt */
# define STM32_IRQ_SDIO (STM32_IRQ_FIRST+45) /* 45: SDIO Global interrupt */
# define STM32_IRQ_TIM5 (STM32_IRQ_FIRST+46) /* 46: TIM5 global interrupt */
# define STM32_IRQ_SPI3 (STM32_IRQ_FIRST+47) /* 47: SPI3 global interrupt */
# define STM32_IRQ_UART4 (STM32_IRQ_FIRST+48) /* 48: UART4 global interrupt */
# define STM32_IRQ_UART5 (STM32_IRQ_FIRST+49) /* 49: UART5 global interrupt */
# define STM32_IRQ_DMA2CH1 (STM32_IRQ_FIRST+50) /* 50: DMA2 channel 1 global interrupt */
# define STM32_IRQ_DMA2CH2 (STM32_IRQ_FIRST+51) /* 51: DMA2 channel 2 global interrupt */
# define STM32_IRQ_DMA2CH3 (STM32_IRQ_FIRST+52) /* 52: DMA2 channel 3 global interrupt */
# define STM32_IRQ_DMA2CH4 (STM32_IRQ_FIRST+53) /* 53: DMA2 channel 4 global interrupt */
# define STM32_IRQ_DMA2CH5 (STM32_IRQ_FIRST+54) /* 54: DMA2 channel 5 global interrupt */
# define STM32_IRQ_AES (STM32_IRQ_FIRST+55) /* 55: AES global interrupt */
# define STM32_IRQ_COMPACQ (STM32_IRQ_FIRST+56) /* 56: Comparator Channel Acquisition Interrupt */
# define NR_VECTORS (STM32_IRQ_FIRST+57)
# define NR_IRQS (STM32_IRQ_FIRST+57)
#else
# error "Unknown STM32L density"
#endif
/****************************************************************************************************
* Public Types
****************************************************************************************************/
/****************************************************************************************************
* Public Data
****************************************************************************************************/
#ifndef __ASSEMBLY__
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************************************
* Public Functions
****************************************************************************************************/
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif
#endif /* __ARCH_ARM_INCLUDE_STM32_STM32FL15XXX_IRQ_H */

200
arch/arm/include/stm32f7/chip.h
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@ -1,200 +0,0 @@
/************************************************************************************
* arch/arm/include/stm32f7/chip.h
*
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_INCLUDE_STM32F7_CHIP_H
#define __ARCH_ARM_INCLUDE_STM32F7_CHIP_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* STM32F745xx, STM32F746xx, and STM32F56xx. Differences between family members:
*
* ----------- ---------------- ----- -------- ------------ --------
* PART PACKAGE GPIOs SPI/I2S ADC CHANNELS LCD-TFT?
* ----------- ---------------- ----- -------- ------------ --------
* STM32F745Vx LQFP100 82 4/3 16 No
* STM32F745Zx WLCSP143/LQFP144 114 6/3 24 No
* STM32F745Ix UFBGA176/LQFP176 140 6/3 24 No
* STM32F745Bx LQFP208 168 6/3 24 No
* STM32F745Nx TFBGA216 68 6/3 24 No
*
* STM32F746Vx LQFP100 82 4/3 16 Yes
* STM32F746Zx WLCSP143/LQFP144 114 6/3 24 Yes
* STM32F746Ix UFBGA176/LQFP176 140 6/3 24 Yes
* STM32F746Bx LQFP208 168 6/3 24 Yes
* STM32F746Nx TFBGA216 168 6/3 24 Yes
*
* STM32F756Vx LQFP100 82 4/3 16 Yes
* STM32F756Zx WLCSP143/LQFP144 114 6/3 24 Yes
* STM32F756Ix UFBGA176/LQFP176 140 6/3 24 Yes
* STM32F756Bx LQFP208 168 6/3 24 Yes
* STM32F756Nx TFBGA216 168 6/3 24 Yes
* ----------- ---------------- ----- -------- ------------ --------
*
* Parts STM32F74xxE have 512Kb of FLASH
* Parts STM32F74xxG have 1024Kb of FLASH
*
* The correct FLASH size must be set with a CONFIG_STM32F7_FLASH_*KB
* selection.
*/
#if defined(CONFIG_ARCH_CHIP_STM32F745) || defined(CONFIG_ARCH_CHIP_STM32F746) || \
defined(CONFIG_ARCH_CHIP_STM32F756)
#if defined(CONFIG_ARCH_CHIP_STM32F745)
# define STM32F7_STM32F745XX 1 /* STM32F745xx family */
# undef STM32F7_STM32F746XX /* Not STM32F746xx family */
# undef STM32F7_STM32F756XX /* Not STM32F756xx family */
# define STM32F7_NLCDTFT 0 /* No LCD-TFT */
#elif defined(CONFIG_ARCH_CHIP_STM32F746)
# undef STM32F7_STM32F745XX /* Not STM32F745xx family */
# define STM32F7_STM32F746XX 1 /* STM32F746xx family */
# undef STM32F7_STM32F756XX /* Not STM32F756xx family */
# define STM32F7_NLCDTFT 1 /* One LCD-TFT */
#else /* if defined(CONFIG_ARCH_CHIP_STM32F746) */
# undef STM32F7_STM32F745XX /* Not STM32F745xx family */
# undef STM32F7_STM32F746XX /* Not STM32F746xx family */
# define STM32F7_STM32F756XX 1 /* STM32F756xx family */
# define STM32F7_NLCDTFT 1 /* One LCD-TFT */
#endif
# define STM32F7_SRAM1_SIZE (240*1024) /* 240Kb SRAM1 on AHB bus Matrix */
# define STM32F7_SRAM2_SIZE (16*1024) /* 16Kb SRAM2 on AHB bus Matrix */
# define STM32F7_DTCM_SRAM_SIZE (64*1024) /* 64Kb DTCM SRAM on TCM inerface */
# define STM32F7_ITCM_SRAM_SIZE (16*1024) /* 16Kb ITCM SRAM on TCM inerface */
# define STM32F7_NFSMC 1 /* Have FSMC memory controller */
# define STM32F7_NETHERNET 1 /* 100/100 Ethernet MAC */
# define STM32F7_NATIM 2 /* Two advanced timers TIM1 and 8 */
# define STM32F7_NGTIM32 2 /* 32-bit general timers TIM2 and 5 with DMA */
# define STM32F7_NGTIM16 2 /* 16-bit general timers TIM3 and 4 with DMA */
# define STM32F7_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */
# define STM32F7_NBTIM 2 /* Two basic timers, TIM6-7 */
# define STM32F7_NRNG 1 /* Random number generator (RNG) */
# define STM32F7_NUART 4 /* UART 4-5 and 7-8 */
# define STM32F7_NUSART 4 /* USART1-3 and 6 */
# define STM32F7_NSPI 6 /* SPI1-6 (Except V series) */
# define STM32F7_NI2S 3 /* I2S1-2 (multiplexed with SPI1-3) */
# define STM32F7_NI2C 4 /* I2C1-4 */
# define STM32F7_NUSBOTGFS 1 /* USB OTG FS */
# define STM32F7_NUSBOTGHS 1 /* USB OTG HS */
# define STM32F7_NCAN 2 /* CAN1-2 */
# define STM32F7_NSAI 2 /* SAI1-2 */
# define STM32F7_NSPDIFRX 4 /* 4 SPDIFRX inputs */
# define STM32F7_NSDMMC 1 /* SDMMC interface */
# define STM32F7_NDCMI 1 /* Digital camera interface (DCMI) */
# define STM32F7_NDMA 2 /* DMA1-2 */
# define STM32F7_NDMA2D 1 /* DChrom-ART Accelerator™ (DMA2D) */
# define STM32F7_NGPIO 11 /* 11 GPIO ports, GPIOA-K */
# define STM32F7_NADC 3 /* 12-bit ADC1-3, 24 channels *except V series) */
# define STM32F7_NDAC 2 /* 12-bit DAC1-2 */
# define STM32F7_NCAPSENSE 0 /* No capacitive sensing channels */
# define STM32F7_NCRC 1 /* CRC */
#else
# error STM32 F7 chip not identified
#endif
/* NVIC priority levels *************************************************************/
/* 16 Programmable interrupt levels */
#define NVIC_SYSH_PRIORITY_MIN 0xf0 /* All bits set in minimum priority */
#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */
#define NVIC_SYSH_PRIORITY_STEP 0x10 /* Four bits of interrupt priority used */
/* If CONFIG_ARMV7M_USEBASEPRI is selected, then interrupts will be disabled
* by setting the BASEPRI register to NVIC_SYSH_DISABLE_PRIORITY so that most
* interrupts will not have execution priority. SVCall must have execution
* priority in all cases.
*
* In the normal cases, interrupts are not nest-able and all interrupts run
* at an execution priority between NVIC_SYSH_PRIORITY_MIN and
* NVIC_SYSH_PRIORITY_MAX (with NVIC_SYSH_PRIORITY_MAX reserved for SVCall).
*
* If, in addition, CONFIG_ARCH_HIPRI_INTERRUPT is defined, then special
* high priority interrupts are supported. These are not "nested" in the
* normal sense of the word. These high priority interrupts can interrupt
* normal processing but execute outside of OS (although they can "get back
* into the game" via a PendSV interrupt).
*
* In the normal course of things, interrupts must occasionally be disabled
* using the irqsave() inline function to prevent contention in use of
* resources that may be shared between interrupt level and non-interrupt
* level logic. Now the question arises, if CONFIG_ARCH_HIPRI_INTERRUPT,
* do we disable all interrupts (except SVCall), or do we only disable the
* "normal" interrupts. Since the high priority interrupts cannot interact
* with the OS, you may want to permit the high priority interrupts even if
* interrupts are disabled. The setting CONFIG_ARCH_INT_DISABLEALL can be
* used to select either behavior:
*
* ----------------------------+--------------+----------------------------
* CONFIG_ARCH_HIPRI_INTERRUPT | NO | YES
* ----------------------------+--------------+--------------+-------------
* CONFIG_ARCH_INT_DISABLEALL | N/A | YES | NO
* ----------------------------+--------------+--------------+-------------
* | | | SVCall
* | SVCall | SVCall | HIGH
* Disable here and below --------> MAXNORMAL ---> HIGH --------> MAXNORMAL
* | | MAXNORMAL |
* ----------------------------+--------------+--------------+-------------
*/
#if defined(CONFIG_ARCH_HIPRI_INTERRUPT) && defined(CONFIG_ARCH_INT_DISABLEALL)
# define NVIC_SYSH_MAXNORMAL_PRIORITY (NVIC_SYSH_PRIORITY_MAX + 2*NVIC_SYSH_PRIORITY_STEP)
# define NVIC_SYSH_HIGH_PRIORITY (NVIC_SYSH_PRIORITY_MAX + NVIC_SYSH_PRIORITY_STEP)
# define NVIC_SYSH_DISABLE_PRIORITY NVIC_SYSH_HIGH_PRIORITY
# define NVIC_SYSH_SVCALL_PRIORITY NVIC_SYSH_PRIORITY_MAX
#else
# define NVIC_SYSH_MAXNORMAL_PRIORITY (NVIC_SYSH_PRIORITY_MAX + NVIC_SYSH_PRIORITY_STEP)
# define NVIC_SYSH_HIGH_PRIORITY NVIC_SYSH_PRIORITY_MAX
# define NVIC_SYSH_DISABLE_PRIORITY NVIC_SYSH_MAXNORMAL_PRIORITY
# define NVIC_SYSH_SVCALL_PRIORITY NVIC_SYSH_PRIORITY_MAX
#endif
#endif /* __ARCH_ARM_INCLUDE_STM32F7_CHIP_H */

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arch/arm/include/stm32f7/irq.h
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@ -1,113 +0,0 @@
/************************************************************************************
* arch/arm/include/stm32f7/irq.h
*
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
/* This file should never be included directed but, rather,
* only indirectly through nuttx/irq.h
*/
#ifndef __ARCH_ARM_INCLUDE_STM32F7_IRQ_H
#define __ARCH_ARM_INCLUDE_STM32F7_IRQ_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* IRQ numbers. The IRQ number corresponds vector number and hence map directly to
* bits in the NVIC. This does, however, waste several words of memory in the IRQ
* to handle mapping tables.
*/
/* Processor Exceptions (vectors 0-15) */
#define STM32_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG) */
/* Vector 0: Reset stack pointer value */
/* Vector 1: Reset (not handler as an IRQ) */
#define STM32_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */
#define STM32_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */
#define STM32_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */
#define STM32_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */
#define STM32_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */
/* Vectors 7-10: Reserved */
#define STM32_IRQ_SVCALL (11) /* Vector 11: SVC call */
#define STM32_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */
/* Vector 13: Reserved */
#define STM32_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */
#define STM32_IRQ_SYSTICK (15) /* Vector 15: System tick */
/* External interrupts (vectors >= 16). These definitions are chip-specific */
#define STM32_IRQ_FIRST (16) /* Vector number of the first external interrupt */
#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
# include <arch/stm32f7/stm32f74xx75xx_irq.h>
#else
# error "Unsupported STM32 F7 chip"
#endif
/************************************************************************************
* Public Types
************************************************************************************/
/************************************************************************************
* Public Data
************************************************************************************/
#ifndef __ASSEMBLY__
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/************************************************************************************
* Public Functions
************************************************************************************/
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif
#endif /* __ARCH_ARM_INCLUDE_STM32F7_IRQ_H */

203
arch/arm/include/stm32f7/stm32f74xx75xx_irq.h
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@ -1,203 +0,0 @@
/****************************************************************************************************
* arch/arm/include/stm32f7/stm32f74xx75xx_irq.h.h
*
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************************************/
/* This file should never be included directed but, rather, only indirectly through arch/irq.h */
#ifndef __ARCH_ARM_INCLUDE_STM32F7_STM32F74XX75XX_IRQ_H
#define __ARCH_ARM_INCLUDE_STM32F7_STM32F74XX75XX_IRQ_H
/****************************************************************************************************
* Included Files
****************************************************************************************************/
#include <nuttx/config.h>
/****************************************************************************************************
* Pre-processor Definitions
****************************************************************************************************/
/* IRQ numbers. The IRQ number corresponds vector number and hence map directly to bits in the
* NVIC. This does, however, waste several words of memory in the IRQ to handle mapping tables.
*
* Processor Exceptions (vectors 0-15). These common definitions can be found in the file
* nuttx/arch/arm/include/stm32f7/irq.h which includes this file
*
* External interrupts (vectors >= 16)
*/
#define STM32_IRQ_WWDG (STM32_IRQ_FIRST+0) /* 0: Window Watchdog interrupt */
#define STM32_IRQ_PVD (STM32_IRQ_FIRST+1) /* 1: PVD through EXTI Line detection interrupt */
#define STM32_IRQ_TAMPER (STM32_IRQ_FIRST+2) /* 2: Tamper and time stamp interrupts */
#define STM32_IRQ_TIMESTAMP (STM32_IRQ_FIRST+2) /* 2: Tamper and time stamp interrupts */
#define STM32_IRQ_RTC_WKUP (STM32_IRQ_FIRST+3) /* 3: RTC global interrupt */
#define STM32_IRQ_FLASH (STM32_IRQ_FIRST+4) /* 4: Flash global interrupt */
#define STM32_IRQ_RCC (STM32_IRQ_FIRST+5) /* 5: RCC global interrupt */
#define STM32_IRQ_EXTI0 (STM32_IRQ_FIRST+6) /* 6: EXTI Line 0 interrupt */
#define STM32_IRQ_EXTI1 (STM32_IRQ_FIRST+7) /* 7: EXTI Line 1 interrupt */
#define STM32_IRQ_EXTI2 (STM32_IRQ_FIRST+8) /* 8: EXTI Line 2 interrupt */
#define STM32_IRQ_EXTI3 (STM32_IRQ_FIRST+9) /* 9: EXTI Line 3 interrupt */
#define STM32_IRQ_EXTI4 (STM32_IRQ_FIRST+10) /* 10: EXTI Line 4 interrupt */
#define STM32_IRQ_DMA1S0 (STM32_IRQ_FIRST+11) /* 11: DMA1 Stream 0 global interrupt */
#define STM32_IRQ_DMA1S1 (STM32_IRQ_FIRST+12) /* 12: DMA1 Stream 1 global interrupt */
#define STM32_IRQ_DMA1S2 (STM32_IRQ_FIRST+13) /* 13: DMA1 Stream 2 global interrupt */
#define STM32_IRQ_DMA1S3 (STM32_IRQ_FIRST+14) /* 14: DMA1 Stream 3 global interrupt */
#define STM32_IRQ_DMA1S4 (STM32_IRQ_FIRST+15) /* 15: DMA1 Stream 4 global interrupt */
#define STM32_IRQ_DMA1S5 (STM32_IRQ_FIRST+16) /* 16: DMA1 Stream 5 global interrupt */
#define STM32_IRQ_DMA1S6 (STM32_IRQ_FIRST+17) /* 17: DMA1 Stream 6 global interrupt */
#define STM32_IRQ_ADC (STM32_IRQ_FIRST+18) /* 18: ADC1, ADC2, and ADC3 global interrupt */
#define STM32_IRQ_CAN1TX (STM32_IRQ_FIRST+19) /* 19: CAN1 TX interrupts */
#define STM32_IRQ_CAN1RX0 (STM32_IRQ_FIRST+20) /* 20: CAN1 RX0 interrupts */
#define STM32_IRQ_CAN1RX1 (STM32_IRQ_FIRST+21) /* 21: CAN1 RX1 interrupt */
#define STM32_IRQ_CAN1SCE (STM32_IRQ_FIRST+22) /* 22: CAN1 SCE interrupt */
#define STM32_IRQ_EXTI95 (STM32_IRQ_FIRST+23) /* 23: EXTI Line[9:5] interrupts */
#define STM32_IRQ_TIM1BRK (STM32_IRQ_FIRST+24) /* 24: TIM1 Break interrupt */
#define STM32_IRQ_TIM9 (STM32_IRQ_FIRST+24) /* 24: TIM9 global interrupt */
#define STM32_IRQ_TIM1UP (STM32_IRQ_FIRST+25) /* 25: TIM1 Update interrupt */
#define STM32_IRQ_TIM10 (STM32_IRQ_FIRST+25) /* 25: TIM10 global interrupt */
#define STM32_IRQ_TIM1TRGCOM (STM32_IRQ_FIRST+26) /* 26: TIM1 Trigger and Commutation interrupts */
#define STM32_IRQ_TIM11 (STM32_IRQ_FIRST+26) /* 26: TIM11 global interrupt */
#define STM32_IRQ_TIM1CC (STM32_IRQ_FIRST+27) /* 27: TIM1 Capture Compare interrupt */
#define STM32_IRQ_TIM2 (STM32_IRQ_FIRST+28) /* 28: TIM2 global interrupt */
#define STM32_IRQ_TIM3 (STM32_IRQ_FIRST+29) /* 29: TIM3 global interrupt */
#define STM32_IRQ_TIM4 (STM32_IRQ_FIRST+30) /* 30: TIM4 global interrupt */
#define STM32_IRQ_I2C1EV (STM32_IRQ_FIRST+31) /* 31: I2C1 event interrupt */
#define STM32_IRQ_I2C1ER (STM32_IRQ_FIRST+32) /* 32: I2C1 error interrupt */
#define STM32_IRQ_I2C2EV (STM32_IRQ_FIRST+33) /* 33: I2C2 event interrupt */
#define STM32_IRQ_I2C2ER (STM32_IRQ_FIRST+34) /* 34: I2C2 error interrupt */
#define STM32_IRQ_SPI1 (STM32_IRQ_FIRST+35) /* 35: SPI1 global interrupt */
#define STM32_IRQ_SPI2 (STM32_IRQ_FIRST+36) /* 36: SPI2 global interrupt */
#define STM32_IRQ_USART1 (STM32_IRQ_FIRST+37) /* 37: USART1 global interrupt */
#define STM32_IRQ_USART2 (STM32_IRQ_FIRST+38) /* 38: USART2 global interrupt */
#define STM32_IRQ_USART3 (STM32_IRQ_FIRST+39) /* 39: USART3 global interrupt */
#define STM32_IRQ_EXTI1510 (STM32_IRQ_FIRST+40) /* 40: EXTI Line[15:10] interrupts */
#define STM32_IRQ_RTCALRM (STM32_IRQ_FIRST+41) /* 41: RTC alarm through EXTI line interrupt */
#define STM32_IRQ_OTGFSWKUP (STM32_IRQ_FIRST+42) /* 42: USB On-The-Go FS Wakeup through EXTI line interrupt */
#define STM32_IRQ_TIM8BRK (STM32_IRQ_FIRST+43) /* 43: TIM8 Break interrupt */
#define STM32_IRQ_TIM12 (STM32_IRQ_FIRST+43) /* 43: TIM12 global interrupt */
#define STM32_IRQ_TIM8UP (STM32_IRQ_FIRST+44) /* 44: TIM8 Update interrupt */
#define STM32_IRQ_TIM13 (STM32_IRQ_FIRST+44) /* 44: TIM13 global interrupt */
#define STM32_IRQ_TIM8TRGCOM (STM32_IRQ_FIRST+45) /* 45: TIM8 Trigger and Commutation interrupts */
#define STM32_IRQ_TIM14 (STM32_IRQ_FIRST+45) /* 45: TIM14 global interrupt */
#define STM32_IRQ_TIM8CC (STM32_IRQ_FIRST+46) /* 46: TIM8 Capture Compare interrupt */
#define STM32_IRQ_DMA1S7 (STM32_IRQ_FIRST+47) /* 47: DMA1 Stream 7 global interrupt */
#define STM32_IRQ_FSMC (STM32_IRQ_FIRST+48) /* 48: FSMC global interrupt */
#define STM32_IRQ_SDMMC1 (STM32_IRQ_FIRST+49) /* 49: SDMMC1 global interrupt */
#define STM32_IRQ_TIM5 (STM32_IRQ_FIRST+50) /* 50: TIM5 global interrupt */
#define STM32_IRQ_SPI3 (STM32_IRQ_FIRST+51) /* 51: SPI3 global interrupt */
#define STM32_IRQ_UART4 (STM32_IRQ_FIRST+52) /* 52: UART4 global interrupt */
#define STM32_IRQ_UART5 (STM32_IRQ_FIRST+53) /* 53: UART5 global interrupt */
#define STM32_IRQ_TIM6 (STM32_IRQ_FIRST+54) /* 54: TIM6 global interrupt */
#define STM32_IRQ_DAC (STM32_IRQ_FIRST+54) /* 54: DAC1 and DAC2 underrun error interrupts */
#define STM32_IRQ_TIM7 (STM32_IRQ_FIRST+55) /* 55: TIM7 global interrupt */
#define STM32_IRQ_DMA2S0 (STM32_IRQ_FIRST+56) /* 56: DMA2 Stream 0 global interrupt */
#define STM32_IRQ_DMA2S1 (STM32_IRQ_FIRST+57) /* 57: DMA2 Stream 1 global interrupt */
#define STM32_IRQ_DMA2S2 (STM32_IRQ_FIRST+58) /* 58: DMA2 Stream 2 global interrupt */
#define STM32_IRQ_DMA2S3 (STM32_IRQ_FIRST+59) /* 59: DMA2 Stream 3 global interrupt */
#define STM32_IRQ_DMA2S4 (STM32_IRQ_FIRST+60) /* 60: DMA2 Stream 4 global interrupt */
#define STM32_IRQ_ETH (STM32_IRQ_FIRST+61) /* 61: Ethernet global interrupt */
#define STM32_IRQ_ETHWKUP (STM32_IRQ_FIRST+62) /* 62: Ethernet Wakeup through EXTI line interrupt */
#define STM32_IRQ_CAN2TX (STM32_IRQ_FIRST+63) /* 63: CAN2 TX interrupts */
#define STM32_IRQ_CAN2RX0 (STM32_IRQ_FIRST+64) /* 64: CAN2 RX0 interrupts */
#define STM32_IRQ_CAN2RX1 (STM32_IRQ_FIRST+65) /* 65: CAN2 RX1 interrupt */
#define STM32_IRQ_CAN2SCE (STM32_IRQ_FIRST+66) /* 66: CAN2 SCE interrupt */
#define STM32_IRQ_OTGFS (STM32_IRQ_FIRST+67) /* 67: USB On The Go FS global interrupt */
#define STM32_IRQ_DMA2S5 (STM32_IRQ_FIRST+68) /* 68: DMA2 Stream 5 global interrupt */
#define STM32_IRQ_DMA2S6 (STM32_IRQ_FIRST+69) /* 69: DMA2 Stream 6 global interrupt */
#define STM32_IRQ_DMA2S7 (STM32_IRQ_FIRST+70) /* 70: DMA2 Stream 7 global interrupt */
#define STM32_IRQ_USART6 (STM32_IRQ_FIRST+71) /* 71: USART6 global interrupt */
#define STM32_IRQ_I2C3EV (STM32_IRQ_FIRST+72) /* 72: I2C3 event interrupt */
#define STM32_IRQ_I2C3ER (STM32_IRQ_FIRST+73) /* 73: I2C3 error interrupt */
#define STM32_IRQ_OTGHSEP1OUT (STM32_IRQ_FIRST+74) /* 74: USB On The Go HS End Point 1 Out global interrupt */
#define STM32_IRQ_OTGHSEP1IN (STM32_IRQ_FIRST+75) /* 75: USB On The Go HS End Point 1 In global interrupt */
#define STM32_IRQ_OTGHSWKUP (STM32_IRQ_FIRST+76) /* 76: USB On The Go HS Wakeup through EXTI interrupt */
#define STM32_IRQ_OTGHS (STM32_IRQ_FIRST+77) /* 77: USB On The Go HS global interrupt */
#define STM32_IRQ_DCMI (STM32_IRQ_FIRST+78) /* 78: DCMI global interrupt */
#define STM32_IRQ_CRYP (STM32_IRQ_FIRST+79) /* 79: CRYP crypto global interrupt */
#define STM32_IRQ_HASH (STM32_IRQ_FIRST+80) /* 80: Hash and Rng global interrupt */
#define STM32_IRQ_RNG (STM32_IRQ_FIRST+80) /* 80: Hash and Rng global interrupt */
#define STM32_IRQ_FPU (STM32_IRQ_FIRST+81) /* 81: FPU global interrupt */
#define STM32_IRQ_UART7 (STM32_IRQ_FIRST+82) /* 82: UART7 global interrupt */
#define STM32_IRQ_UART8 (STM32_IRQ_FIRST+83) /* 83: UART8 global interrupt */
#define STM32_IRQ_SPI4 (STM32_IRQ_FIRST+84) /* 84: SPI4 global interrupt */
#define STM32_IRQ_SPI5 (STM32_IRQ_FIRST+85) /* 85: SPI5 global interrupt */
#define STM32_IRQ_SPI6 (STM32_IRQ_FIRST+86) /* 86: SPI6 global interrupt */
#define STM32_IRQ_SAI1 (STM32_IRQ_FIRST+87) /* 87: SAI1 global interrupt */
#define STM32_IRQ_LTDCINT (STM32_IRQ_FIRST+88) /* 88: LCD-TFT global interrupt */
#define STM32_IRQ_LTDCERRINT (STM32_IRQ_FIRST+89) /* 89: LCD-TFT global Error interrupt */
#define STM32_IRQ_DMA2D (STM32_IRQ_FIRST+90) /* 90: DMA2D global interrupt */
#define STM32_IRQ_SAI1 (STM32_IRQ_FIRST+91) /* 91: SAI2 global interrupt */
#define STM32_IRQ_QUADSPI (STM32_IRQ_FIRST+92) /* 92: QuadSPI global interrupt */
#define STM32_IRQ_LPTIMER1 (STM32_IRQ_FIRST+93) /* 93: LP Timer1 global interrupt */
#define STM32_IRQ_HDMICEC (STM32_IRQ_FIRST+94) /* 94: HDMI-CEC global interrupt */
#define STM32_IRQ_I2C4EV (STM32_IRQ_FIRST+95) /* 95: I2C4 event interrupt */
#define STM32_IRQ_I2C4ER (STM32_IRQ_FIRST+96) /* 96: I2C4 Error interrupt */
#define STM32_IRQ_SPDIFRX (STM32_IRQ_FIRST+97) /* 97: SPDIFRX global interrupt */
#define NR_INTERRUPTS 98
#define NR_VECTORS (STM32_IRQ_FIRST+NR_INTERRUPTS)
/* EXTI interrupts (Do not use IRQ numbers) */
#define NR_IRQS NR_VECTORS
/****************************************************************************************************
* Public Types
****************************************************************************************************/
/****************************************************************************************************
* Public Data
****************************************************************************************************/
#ifndef __ASSEMBLY__
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************************************
* Public Functions
****************************************************************************************************/
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif
#endif /* __ARCH_ARM_INCLUDE_STM32F7_STM32F74XX75XX_IRQ_H */

152
arch/arm/include/str71x/irq.h
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@ -1,152 +0,0 @@
/************************************************************************************
* arch/arm/include/str71x/irq.h
*
* Copyright (C) 2008-2010 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
/* This file should never be included directed but, rather,
* only indirectly through nuttx/irq.h
*/
#ifndef __ARCH_ARM_INCLUDE_STR71X_IRQ_H
#define __ARCH_ARM_INCLUDE_STR71X_IRQ_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* IRQ channels */
#define STR71X_IRQ_T0TIMI (0) /* IRQ 0: T0.EFTI Timer 0 global interrupt */
#define STR71X_IRQ_FLASH (1) /* IRQ 1: FLASH FLASH global interrupt */
#define STR71X_IRQ_RCCU (2) /* IRQ 2: PRCCU PRCCU global interrupt */
#define STR71X_IRQ_RTC (3) /* IRQ 3: RTC Real Time Clock global interrupt */
#define STR71X_IRQ_WDG (4) /* IRQ 4: WDG.IRQ Watchdog timer interrupt */
#define STR71X_IRQ_XTI (5) /* IRQ 5: XTI.IRQ XTI external interrupt */
#define STR71X_IRQ_USBHP (6) /* IRQ 6: USB.HPIRQ USB high priority event interrupt */
#define STR71X_IRQ_I2C0ITERR (7) /* IRQ 7: I2C0.ITERR I2C 0 error interrupt */
#define STR71X_IRQ_I2C1ITERR (8) /* IRQ 8: I2C1.ITERR I2C 1 error interrupt */
#define STR71X_IRQ_UART0 (9) /* IRQ 9: UART0.IRQ UART 0 global interrupt */
#define STR71X_IRQ_UART1 (10) /* IRQ 10: UART1.IRQ UART 1 global interrupt */
#define STR71X_IRQ_UART2 (11) /* IRQ 11: UART2.IRQ UART 2 global interrupt */
#define STR71X_IRQ_UART3 (12) /* IRQ 12: UART3.IRQ UART 3 global interrupt */
#define STR71X_IRQ_SPI0 (13) /* IRQ 13: BSPI0.IRQ BSPI 0 global interrupt */
#define STR71X_IRQ_SPI1 (14) /* IRQ 14: BSPI1.IRQ BSPI 1 global interrupt */
#define STR71X_IRQ_I2C0 (15) /* IRQ 15: I2C0.IRQ I2C 0 tx/rx interrupt */
#define STR71X_IRQ_I2C1 (16) /* IRQ 16: I2C1.IRQ I2C 1 tx/rx interrupt */
#define STR71X_IRQ_CAN (17) /* IRQ 17: CAN.IRQ CAN module global interrupt */
#define STR71X_IRQ_ADC (18) /* IRQ 18: ADC.IRQ ADC sample ready interrupt */
#define STR71X_IRQ_T1TIMI (19) /* IRQ 19: T1.GI Timer 1 global interrupt */
#define STR71X_IRQ_T2TIMI (20) /* IRQ 20: T2.GI Timer 2 global interrupt */
#define STR71X_IRQ_T3TIMI (21) /* IRQ 21: T3.GI Timer 3 global interrupt */
/* IRQ 22-24: Reserved */
#define STR71X_IRQ_HDLC (25) /* IRQ 25: HDLC.IRQ HDLC global interrupt */
#define STR71X_IRQ_USBLP (26) /* IRQ 26: USB.LPIRQ USB low priority event interrupt */
/* IRQ 27-28: Reserved */
#define STR71X_IRQ_T0TOI (29) /* IRQ 29: T0.TOI Timer 0 Overflow interrupt */
#define STR71X_IRQ_T0OC1 (30) /* IRQ 30: T0.OCMPA Timer 0 Output Compare A interrupt */
#define STR71X_IRQ_T0OC2 (31) /* IRQ 31: T0.OCMPB Timer 0 Output Compare B interrupt */
#define STR71X_NBASEIRQS (32)
#ifdef CONFIG_STR71X_XTI
# define STR71X_IRQ_FIRSTXTI (32)
# define STR71X_IRQ_SW (32) /* Line 0: SW interrupt - no HW connection */
# define STR71X_IRQ_USBWKUP (33) /* Line 1: USB wake-up event: generated while exiting
* from suspend mode */
# define STR71X_IRQ_PORT2p8 (34) /* Line 2: Port 2.8 - External Interrupt */
# define STR71X_IRQ_PORT2p9 (35) /* Line 3: Port 2.9 - External Interrupt */
# define STR71X_IRQ_PORT2p10 (36) /* Line 4: Port 2.10 - External Interrupt */
# define STR71X_IRQ_PORT2p11 (37) /* Line 5: Port 2.11 - External Interrupt */
# define STR71X_IRQ_PORT1p11 (38) /* Line 6: Port 1.11 - CAN module receive pin (CANRX). */
# define STR71X_IRQ_PORT1p13 (39) /* Line 7: Port 1.13 - HDLC clock (HCLK) or I2C.0 Clock
* (I0.SCL) */
# define STR71X_IRQ_PORT1p14 (40) /* Line 8: Port 1.14 - HDLC receive pin (HRXD) or I2C.0
* Data (SDA) */
# define STR71X_IRQ_PORT0p1 (41) /* Line 9: Port 0.1 - BSPI0 Slave Input data (S0.MOSI)
* or UART3 Receive Data Input (U3.Rx) */
# define STR71X_IRQ_PORT0p2 (42) /* Line 10: Port 0.2 - BSPI0 Slave Input serial clock
* (S0.SCLK) or I2C.1 Clock (I1.SCL) */
# define STR71X_IRQ_PORT0p6 (43) /* Line 11: Port 0.6 - BSPI1 Slave Input serial clock
* (S1.SCLK) */
# define STR71X_IRQ_PORT0p8 (44) /* Line 12: Port 0.8 - UART0 Receive Data Input (U0.Rx) */
# define STR71X_IRQ_PORT0p10 (45) /* Line 13: Port 0.10 - UART1 Receive Data Input (U1.Rx) */
# define STR71X_IRQ_PORT0p13 (46) /* Line 14: Port 0.13 - UART2 Receive Data Input (U2.Rx) */
# define STR71X_IRQ_PORT0p15 (47) /* Line 15: Port 0.15 - WAKEUP pin or RTC ALARM */
# define NR_IRQS (48)
#else
# define NR_IRQS (32)
#endif
#define STR71X_IRQ_SYSTIMER STR71X_IRQ_T0TIMI
/* FIQ channels */
#define STR71X_FIQ_T0TIMI (0X00000001)
#define STR71X_FIQ_WDG (0X00000002)
#define STR71X_FIQ_WDGT0TIMIS (0X00000003)
/************************************************************************************
* Public Types
************************************************************************************/
/************************************************************************************
* Public Data
************************************************************************************/
#ifndef __ASSEMBLY__
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/************************************************************************************
* Public Functions
************************************************************************************/
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_INCLUDE_STR71X_IRQ_H */

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arch/arm/include/syscall.h
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@ -1,96 +0,0 @@
/****************************************************************************
* arch/arm/include/syscall.h
*
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/* This file should never be included directed but, rather, only indirectly
* through include/syscall.h or include/sys/sycall.h
*/
#ifndef __ARCH_ARM_INCLUDE_SYSCALL_H
#define __ARCH_ARM_INCLUDE_SYSCALL_H
/****************************************************************************
* Included Files
****************************************************************************/
/* Include ARM architecture-specific syscall macros */
#if defined(CONFIG_ARCH_CORTEXA5) || defined(CONFIG_ARCH_CORTEXA8)
# include <arch/armv7-a/syscall.h>
#elif defined(CONFIG_ARCH_CORTEXM3) || defined(CONFIG_ARCH_CORTEXM4) || \
defined(CONFIG_ARCH_CORTEXM7)
# include <arch/armv7-m/syscall.h>
#elif defined(CONFIG_ARCH_CORTEXM0)
# include <arch/armv6-m/syscall.h>
#else
# include <arch/arm/syscall.h>
#endif
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Inline functions
****************************************************************************/
/****************************************************************************
* Public Variables
****************************************************************************/
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#ifndef __ASSEMBLY__
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif
#endif /* __ARCH_ARM_INCLUDE_SYSCALL_H */

299
arch/arm/include/tiva/cc3200_irq.h
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@ -1,299 +0,0 @@
/************************************************************************************
* arch/arm/include/tiva/cc3200_irq.h
*
* Copyright (C) 2014 Droidifi LLC.
* Author: Jim Ewing <jim@droidifi.com>
*
* Adapted for the cc3200 from code:
*
* Copyright (C) 2011-2012 Gregory Nutt.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name Droidifi nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_INCLUDE_TIVA_CC3200_IRQ_H
#define __ARCH_ARM_INCLUDE_TIVA_CC3200_IRQ_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* IRQ numbers. The IRQ number corresponds vector number and hence map directly to
* bits in the NVIC. This does, however, waste several words of memory in the IRQ
* to handle mapping tables.
*/
/* External interrupts (vectors >= 16) */
#define TIVA_IRQ_INTERRUPTS (16) /* Vector number of the first external interrupt */
#if defined(CONFIG_ARCH_CHIP_CC3200)
# define TIVA_IRQ_GPIOA (16) /* Vector 16: GPIO Port A */
# define TIVA_IRQ_GPIOB (17) /* Vector 17: GPIO Port B */
# define TIVA_IRQ_GPIOC (18) /* Vector 18: GPIO Port C */
# define TIVA_IRQ_GPIOD (19) /* Vector 19: GPIO Port D */
# define TIVA_RESERVED_20 (20) /* Vector 20: Reserved */
# define TIVA_IRQ_UART0 (21) /* Vector 21: UART 0 */
# define TIVA_IRQ_UART1 (22) /* Vector 22: UART 1 */
# define TIVA_RESERVED_23 (23) /* Vector 23: Reserved */
# define TIVA_IRQ_I2C0 (24) /* Vector 24: I2C 0 */
# define TIVA_RESERVED_25 (25) /* Vector 25: Reserved */
# define TIVA_RESERVED_26 (26) /* Vector 26: Reserved */
# define TIVA_RESERVED_27 (27) /* Vector 27: Reserved */
# define TIVA_RESERVED_28 (28) /* Vector 28: Reserved */
# define TIVA_RESERVED_29 (29) /* Vector 29: Reserved */
# define TIVA_IRQ_ADC0 (30) /* Vector 30: ADC Sequence 0 */
# define TIVA_IRQ_ADC1 (31) /* Vector 31: ADC Sequence 1 */
# define TIVA_IRQ_ADC2 (32) /* Vector 32: ADC Sequence 2 */
# define TIVA_IRQ_ADC3 (33) /* Vector 33: ADC Sequence 3 */
# define TIVA_IRQ_WDOG (34) /* Vector 34: Watchdog Timers 0 and 1 */
# define TIVA_IRQ_TIMER0A (35) /* Vector 35: 16/32-Bit Timer 0 A */
# define TIVA_IRQ_TIMER0B (36) /* Vector 36: 16/32-Bit Timer 0 B */
# define TIVA_IRQ_TIMER1A (37) /* Vector 37: 16/32-Bit Timer 1 A */
# define TIVA_IRQ_TIMER1B (38) /* Vector 38: 16/32-Bit Timer 1 B */
# define TIVA_IRQ_TIMER2A (39) /* Vector 39: 16/32-Bit Timer 2 A */
# define TIVA_IRQ_TIMER2B (40) /* Vector 40: 16/32-Bit Timer 2 B */
# define TIVA_RESERVED_41 (41) /* Vector 41: Reserved */
# define TIVA_RESERVED_42 (42) /* Vector 42: Reserved */
# define TIVA_RESERVED_43 (43) /* Vector 43: Reserved */
# define TIVA_IRQ_SYSCON (44) /* Vector 44: System Control */
# define TIVA_IRQ_FLASHCON (45) /* Vector 45: FLASH and EEPROM Control */
# define TIVA_RESERVED_46 (46) /* Vector 46: Reserved */
# define TIVA_RESERVED_47 (47) /* Vector 47: Reserved */
# define TIVA_RESERVED_48 (48) /* Vector 48: Reserved */
# define TIVA_RESERVED_49 (49) /* Vector 49: Reserved */
# define TIVA_RESERVED_50 (50) /* Vector 50: Reserved */
# define TIVA_IRQ_TIMER3A (51) /* Vector 51: 16/32-Bit Timer 3 A */
# define TIVA_IRQ_TIMER3B (52) /* Vector 52: 16/32-Bit Timer 3 B */
# define TIVA_RESERVED_53 (53) /* Vector 53: Reserved */
# define TIVA_RESERVED_54 (54) /* Vector 54: Reserved */
# define TIVA_RESERVED_55 (55) /* Vector 55: Reserved */
# define TIVA_RESERVED_56 (56) /* Vector 56: Reserved */
# define TIVA_RESERVED_57 (57) /* Vector 57: Reserved */
# define TIVA_RESERVED_58 (58) /* Vector 58: Reserved */
# define TIVA_IRQ_HIBERNATE (59) /* Vector 59: Hibernation Module */
# define TIVA_RESERVED_60 (60) /* Vector 60: Reserved */
# define TIVA_RESERVED_61 (61) /* Vector 61: Reserved */
# define TIVA_IRQ_UDMASOFT (62) /* Vector 62: uDMA Software */
# define TIVA_IRQ_UDMAERROR (63) /* Vector 63: uDMA Error */
# define TIVA_IRQ_ADC1_0 (64) /* Vector 64: ADC1 Sequence 0 */
# define TIVA_IRQ_ADC1_1 (65) /* Vector 65: ADC1 Sequence 1 */
# define TIVA_IRQ_ADC1_2 (66) /* Vector 66: ADC1 Sequence 2 */
# define TIVA_IRQ_ADC1_3 (67) /* Vector 67: ADC1 Sequence 3 */
# define TIVA_IRQ_I2S0 (68) /* Vector 68: I2S0 */
# define TIVA_IRQ_EPI (69) /* Vector 69: EPI */
# define TIVA_RESERVED_70 (70) /* Vector 70: Reserved */
# define TIVA_RESERVED_71 (71) /* Vector 71: Reserved */
# define TIVA_RESERVED_72 (72) /* Vector 72: Reserved */
# define TIVA_RESERVED_73 (73) /* Vector 73: Reserved */
# define TIVA_RESERVED_74 (74) /* Vector 74: Reserved */
# define TIVA_RESERVED_75 (75) /* Vector 75: Reserved */
# define TIVA_RESERVED_76 (76) /* Vector 76: Reserved */
# define TIVA_RESERVED_77 (77) /* Vector 77: Reserved */
# define TIVA_RESERVED_78 (78) /* Vector 78: Reserved */
# define TIVA_RESERVED_79 (79) /* Vector 79: Reserved */
# define TIVA_RESERVED_80 (80) /* Vector 80: Reserved */
# define TIVA_RESERVED_81 (81) /* Vector 81: Reserved */
# define TIVA_RESERVED_82 (82) /* Vector 82: Reserved */
# define TIVA_RESERVED_83 (83) /* Vector 83: Reserved */
# define TIVA_RESERVED_84 (84) /* Vector 84: Reserved */
# define TIVA_RESERVED_85 (85) /* Vector 85: Reserved */
# define TIVA_RESERVED_86 (86) /* Vector 86: Reserved */
# define TIVA_RESERVED_87 (87) /* Vector 87: Reserved */
# define TIVA_RESERVED_88 (88) /* Vector 88: Reserved */
# define TIVA_RESERVED_89 (89) /* Vector 89: Reserved */
# define TIVA_RESERVED_90 (90) /* Vector 90: Reserved */
# define TIVA_RESERVED_91 (91) /* Vector 91: Reserved */
# define TIVA_RESERVED_92 (92) /* Vector 92: Reserved */
# define TIVA_RESERVED_93 (93) /* Vector 93: Reserved */
# define TIVA_RESERVED_94 (94) /* Vector 94: Reserved */
# define TIVA_RESERVED_95 (95) /* Vector 95: Reserved */
# define TIVA_RESERVED_96 (96) /* Vector 96: Reserved */
# define TIVA_RESERVED_97 (97) /* Vector 97: Reserved */
# define TIVA_RESERVED_98 (98) /* Vector 98: Reserved */
# define TIVA_RESERVED_99 (99) /* Vector 99: Reserved */
# define TIVA_RESERVED_100 (100) /* Vector 100: Reserved */
# define TIVA_RESERVED_101 (101) /* Vector 101: Reserved */
# define TIVA_RESERVED_102 (102) /* Vector 102: Reserved */
# define TIVA_RESERVED_103 (103) /* Vector 103: Reserved */
# define TIVA_RESERVED_104 (104) /* Vector 104: Reserved */
# define TIVA_RESERVED_105 (105) /* Vector 105: Reserved */
# define TIVA_RESERVED_106 (106) /* Vector 106: Reserved */
# define TIVA_RESERVED_107 (107) /* Vector 107: Reserved */
# define TIVA_RESERVED_108 (108) /* Vector 108: Reserved */
# define TIVA_RESERVED_109 (109) /* Vector 109: Reserved */
# define TIVA_RESERVED_110 (110) /* Vector 110: Reserved */
# define TIVA_RESERVED_111 (111) /* Vector 111: Reserved */
# define TIVA_RESERVED_112 (112) /* Vector 112: Reserved */
# define TIVA_RESERVED_113 (113) /* Vector 113: Reserved */
# define TIVA_RESERVED_114 (114) /* Vector 114: Reserved */
# define TIVA_RESERVED_115 (115) /* Vector 115: Reserved */
# define TIVA_RESERVED_116 (116) /* Vector 116: Reserved */
# define TIVA_RESERVED_117 (117) /* Vector 117: Reserved */
# define TIVA_RESERVED_118 (118) /* Vector 118: Reserved */
# define TIVA_RESERVED_119 (119) /* Vector 119: Reserved */
# define TIVA_RESERVED_120 (120) /* Vector 120: Reserved */
# define TIVA_RESERVED_121 (121) /* Vector 121: Reserved */
# define TIVA_IRQ_SYSTEM (122) /* Vector 122: System Exception (imprecise) */
# define TIVA_RESERVED_123 (123) /* Vector 123: Reserved */
# define TIVA_RESERVED_124 (124) /* Vector 124: Reserved */
# define TIVA_RESERVED_125 (125) /* Vector 125: Reserved */
# define TIVA_RESERVED_126 (126) /* Vector 126: Reserved */
# define TIVA_RESERVED_127 (127) /* Vector 127: Reserved */
# define TIVA_RESERVED_128 (128) /* Vector 128: Reserved */
# define TIVA_RESERVED_129 (129) /* Vector 129: Reserved */
# define TIVA_RESERVED_130 (130) /* Vector 130: Reserved */
# define TIVA_RESERVED_131 (131) /* Vector 131: Reserved */
# define TIVA_RESERVED_132 (132) /* Vector 132: Reserved */
# define TIVA_RESERVED_133 (133) /* Vector 133: Reserved */
# define TIVA_RESERVED_134 (134) /* Vector 134: Reserved */
# define TIVA_RESERVED_135 (135) /* Vector 135: Reserved */
# define TIVA_RESERVED_136 (136) /* Vector 136: Reserved */
# define TIVA_RESERVED_137 (137) /* Vector 137: Reserved */
# define TIVA_RESERVED_138 (138) /* Vector 138: Reserved */
# define TIVA_RESERVED_139 (139) /* Vector 139: Reserved */
# define TIVA_RESERVED_140 (140) /* Vector 140: Reserved */
# define TIVA_RESERVED_141 (141) /* Vector 141: Reserved */
# define TIVA_RESERVED_142 (142) /* Vector 142: Reserved */
# define TIVA_RESERVED_143 (143) /* Vector 143: Reserved */
# define TIVA_RESERVED_144 (144) /* Vector 144: Reserved */
# define TIVA_RESERVED_145 (145) /* Vector 145: Reserved */
# define TIVA_RESERVED_146 (146) /* Vector 146: Reserved */
# define TIVA_RESERVED_147 (147) /* Vector 147: Reserved */
# define TIVA_RESERVED_148 (148) /* Vector 148: Reserved */
# define TIVA_RESERVED_149 (149) /* Vector 149: Reserved */
# define TIVA_RESERVED_150 (150) /* Vector 150: Reserved */
# define TIVA_RESERVED_151 (151) /* Vector 151: Reserved */
# define TIVA_RESERVED_152 (152) /* Vector 152: Reserved */
# define TIVA_RESERVED_153 (153) /* Vector 153: Reserved */
# define TIVA_RESERVED_154 (154) /* Vector 154: Reserved */
# define TIVA_RESERVED_155 (155) /* Vector 155: Reserved */
# define TIVA_RESERVED_156 (156) /* Vector 156: Reserved */
# define TIVA_RESERVED_157 (157) /* Vector 157: Reserved */
# define TIVA_RESERVED_158 (158) /* Vector 158: Reserved */
# define TIVA_RESERVED_159 (159) /* Vector 159: Reserved */
# define TIVA_RESERVED_160 (160) /* Vector 160: Reserved */
# define TIVA_RESERVED_161 (161) /* Vector 161: Reserved */
# define TIVA_RESERVED_162 (162) /* Vector 162: Reserved */
# define TIVA_RESERVED_163 (163) /* Vector 162: Reserved */
# define TIVA_IRQ_SHA (164) /* Vector 162: SHA HW */
# define TIVA_RESERVED_165 (165) /* Vector 165: Reserved */
# define TIVA_RESERVED_166 (166) /* Vector 166: Reserved */
# define TIVA_IRQ_AES (167) /* Vector 167: AES HW */
# define TIVA_RESERVED_168 (168) /* Vector 168: Reserved */
# define TIVA_IRQ_DES (169) /* Vector 169: DES HW */
# define TIVA_RESERVED_170 (170) /* Vector 170: Reserved */
# define TIVA_RESERVED_171 (171) /* Vector 171: Reserved */
# define TIVA_RESERVED_172 (172) /* Vector 172: Reserved */
# define TIVA_RESERVED_173 (173) /* Vector 173: Reserved */
# define TIVA_RESERVED_174 (174) /* Vector 174: Reserved */
# define TIVA_RESERVED_175 (175) /* Vector 175: Reserved */
# define TIVA_RESERVED_176 (176) /* Vector 176: Reserved */
# define TIVA_IRQ_MC_ASP_0 (177) /* Vector 177: McASP 0 */
# define TIVA_RESERVED_178 (178) /* Vector 178: Reserved */
# define TIVA_IRQ_CAM_0 (179) /* Vector 179: Camera A0 */
# define TIVA_RESERVED_180 (180) /* Vector 180: Reserved */
# define TIVA_RESERVED_181 (181) /* Vector 181: Reserved */
# define TIVA_RESERVED_182 (182) /* Vector 182: Reserved */
# define TIVA_RESERVED_183 (183) /* Vector 183: Reserved */
# define TIVA_IRQ_RAM_ERR (184) /* Vector 184: RAM Err */
# define TIVA_RESERVED_185 (185) /* Vector 185: Reserved */
# define TIVA_RESERVED_186 (186) /* Vector 186: Reserved */
# define TIVA_IRQ_NWPIC (187) /* Vector 187: NWP IC interocessor comm */
# define TIVA_IRQ_PRCM (188) /* Vector 188: Pwr, Rst, Clk */
# define TIVA_IRQ_TOPDIE (189) /* Vector 189: From Top Die */
# define TIVA_RESERVED_190 (190) /* Vector 190: Reserved */
# define TIVA_IRQ_MCSPI_S0 (191) /* Vector 191: SPI S0 */
# define TIVA_IRQ_MCSPI_A1 (192) /* Vector 191: SPI A0 */
# define TIVA_IRQ_MCSPI_A2 (193) /* Vector 191: SPI A1 */
# define TIVA_RESERVED_194 (194) /* Vector 194: Reserved */
# define NR_IRQS (195) /* (Really fewer because of reserved vectors) */
#else
# error "IRQ Numbers not known for this Tiva chip"
#endif
/************************************************************************************
* Public Types
************************************************************************************/
/************************************************************************************
* Public Data
************************************************************************************/
#ifndef __ASSEMBLY__
#ifdef __cplusplus
extern "C"
{
#endif
/************************************************************************************
* Public Functions
************************************************************************************/
#ifdef __cplusplus
}
#endif
#endif
#endif /* __ARCH_ARM_INCLUDE_TIVA_CC3200_IRQ_H */

391
arch/arm/include/tiva/chip.h
View file

@ -1,391 +0,0 @@
/************************************************************************************
* arch/arm/include/tiva/chip.h
*
* Copyright (C) 2009-2010, 2013-2014 Gregory Nutt. All rights reserved.
* Authors: Gregory Nutt <gnutt@nuttx.org>
* Jose Pablo Carballo <jcarballo@nx-engineering.com>
* Jim Ewing <jim@droidifi.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_INCLUDE_TIVA_CHIP_H
#define __ARCH_ARM_INCLUDE_TIVA_CHIP_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Get customizations for each supported chip (only the LM3S6918 and 65 right now) */
#if defined(CONFIG_ARCH_CHIP_LM3S6918)
# define LM3S 1 /* LM3S family */
# undef LM4F /* Not LM4F family */
# undef TM4C /* Not TM4C family */
# define TIVA_NTIMERS 4 /* Four 16/32-bit timers */
# define TIVA_NWIDETIMERS 0 /* No 32/64-bit timers */
# define TIVA_NWDT 1 /* One watchdog timer */
# define TIVA_NETHCONTROLLERS 1 /* One Ethernet controller */
# define TIVA_NLCD 0 /* No LCD controller */
# undef TIVA_ETHTS /* No timestamp register */
# define TIVA_NSSI 2 /* Two SSI modules */
# define TIVA_NUARTS 2 /* Two UART modules */
# define TIVA_NI2C 2 /* Two I2C modules */
# define TIVA_NADC 1 /* One ADC module */
# define TIVA_NPWM 0 /* No PWM generator modules */
# define TIVA_NQEI 0 /* No quadrature encoders */
# define TIVA_NPORTS 8 /* 8 Ports (GPIOA-H) 5-38 GPIOs */
# define TIVA_NCANCONTROLLER 0 /* No CAN controllers */
# define TIVA_NUSBOTGFS 0 /* No USB 2.0 OTG FS */
# define TIVA_NUSBOTGHS 0 /* No USB 2.0 OTG HS */
# define TIVA_NCRC 0 /* No CRC module */
# define TIVA_NAES 0 /* No AES module */
# define TIVA_NDES 0 /* No DES module */
# define TIVA_NHASH 0 /* No SHA1/MD5 hash module */
#elif defined(CONFIG_ARCH_CHIP_LM3S6432)
# define LM3S 1 /* LM3S family */
# undef LM4F /* Not LM4F family */
# undef TM4C /* Not TM4C family */
# define TIVA_NTIMERS 3 /* Three 16/32-bit timers */
# define TIVA_NWIDETIMERS 0 /* No 32/64-bit timers */
# define TIVA_NWDT 1 /* One watchdog timer */
# define TIVA_NETHCONTROLLERS 1 /* One Ethernet controller */
# define TIVA_NLCD 0 /* No LCD controller */
# undef TIVA_ETHTS /* No timestamp register */
# define TIVA_NSSI 1 /* One SSI module */
# define TIVA_NUARTS 2 /* Two UART modules */
# define TIVA_NI2C 1 /* Two I2C modules */
# define TIVA_NADC 1 /* One ADC module */
# define TIVA_NPWM 1 /* One PWM generator module */
# define TIVA_NQEI 0 /* No quadrature encoders */
# define TIVA_NPORTS 7 /* 7 Ports (GPIOA-G), 0-42 GPIOs */
# define TIVA_NCANCONTROLLER 0 /* No CAN controllers */
# define TIVA_NUSBOTGFS 0 /* No USB 2.0 OTG FS */
# define TIVA_NUSBOTGHS 0 /* No USB 2.0 OTG HS */
# define TIVA_NCRC 0 /* No CRC module */
# define TIVA_NAES 0 /* No AES module */
# define TIVA_NDES 0 /* No DES module */
# define TIVA_NHASH 0 /* No SHA1/MD5 hash module */
#elif defined(CONFIG_ARCH_CHIP_LM3S6965)
# define LM3S 1 /* LM3S family */
# undef LM4F /* Not LM4F family */
# undef TM4C /* Not TM4C family */
# define TIVA_NTIMERS 4 /* Four 16/32-bit timers */
# define TIVA_NWIDETIMERS 0 /* No 32/64-bit timers */
# define TIVA_NWDT 1 /* One watchdog timer */
# define TIVA_NETHCONTROLLERS 1 /* One Ethernet controller */
# define TIVA_NLCD 0 /* No LCD controller */
# undef TIVA_ETHTS /* No timestamp register */
# define TIVA_NSSI 1 /* One SSI module */
# define TIVA_NUARTS 3 /* Three UART modules */
# define TIVA_NI2C 2 /* Two I2C modules */
# define TIVA_NADC 1 /* One ADC module */
# define TIVA_NPWM 3 /* Three PWM generator modules */
# define TIVA_NQEI 2 /* Two quadrature encoders */
# define TIVA_NPORTS 7 /* 7 Ports (GPIOA-G), 0-42 GPIOs */
# define TIVA_NCANCONTROLLER 0 /* No CAN controllers */
# define TIVA_NUSBOTGFS 0 /* No USB 2.0 OTG FS */
# define TIVA_NUSBOTGHS 0 /* No USB 2.0 OTG HS */
# define TIVA_NCRC 0 /* No CRC module */
# define TIVA_NAES 0 /* No AES module */
# define TIVA_NDES 0 /* No DES module */
# define TIVA_NHASH 0 /* No SHA1/MD5 hash module */
#elif defined(CONFIG_ARCH_CHIP_LM3S9B96)
# define LM3S 1 /* LM3S family */
# undef LM4F /* Not LM4F family */
# undef TM4C /* Not TM4C family */
# define TIVA_NTIMERS 4 /* Four 16/32-bit timers */
# define TIVA_NWIDETIMERS 0 /* No 32/64-bit timers */
# define TIVA_NWDT 1 /* One watchdog timer */
# define TIVA_NETHCONTROLLERS 1 /* One Ethernet controller */
# define TIVA_NLCD 0 /* No LCD controller */
# undef TIVA_ETHTS /* No timestamp register */
# define TIVA_NSSI 2 /* Two SSI modules */
# define TIVA_NUARTS 3 /* Three UART modules */
# define TIVA_NI2C 2 /* Two I2C modules */
# define TIVA_NADC 2 /* Two ADC module */
# define TIVA_CAN 2 /* Two CAN module */
# define TIVA_NPWM 4 /* Four PWM generator modules */
# define TIVA_NQEI 2 /* Two quadrature encoders */
# define TIVA_NPORTS 9 /* 9 Ports (GPIOA-H,J) 0-65 GPIOs */
# define TIVA_NCANCONTROLLER 0 /* No CAN controllers */
# define TIVA_NUSBOTGFS 0 /* No USB 2.0 OTG FS */
# define TIVA_NUSBOTGHS 0 /* No USB 2.0 OTG HS */
# define TIVA_NCRC 0 /* No CRC module */
# define TIVA_NAES 0 /* No AES module */
# define TIVA_NDES 0 /* No DES module */
# define TIVA_NHASH 0 /* No SHA1/MD5 hash module */
#elif defined(CONFIG_ARCH_CHIP_LM3S8962)
# define LM3S 1 /* LM3S family */
# undef LM4F /* Not LM4F family */
# undef TM4C /* Not TM4C family */
# define TIVA_NTIMERS 6 /* Four 16/32-bit timers */
# define TIVA_NWIDETIMERS 0 /* No 32/64-bit timers */
# define TIVA_NWDT 1 /* One watchdog timer */
# define TIVA_NETHCONTROLLERS 1 /* One Ethernet controller */
# define TIVA_NLCD 0 /* No LCD controller */
# define TIVA_NSSI 1 /* One SSI module */
# define TIVA_NUARTS 3 /* Two UART modules */
# define TIVA_NI2C 2 /* One I2C module */
# define TIVA_NADC 1 /* One ADC module */
# define TIVA_NPWM 3 /* Three PWM generator modules */
# define TIVA_NQEI 2 /* Two quadrature encoders */
# define TIVA_NPORTS 7 /* 7 Ports (GPIOA-G), 5-42 GPIOs */
# define TIVA_NCANCONTROLLER 1 /* One CAN controller */
# define TIVA_NUSBOTGFS 0 /* No USB 2.0 OTG FS */
# define TIVA_NUSBOTGHS 0 /* No USB 2.0 OTG HS */
# define TIVA_NCRC 0 /* No CRC module */
# define TIVA_NAES 0 /* No AES module */
# define TIVA_NDES 0 /* No DES module */
# define TIVA_NHASH 0 /* No SHA1/MD5 hash module */
#elif defined(CONFIG_ARCH_CHIP_LM4F120)
# undef LM3S /* Not LM3S family */
# define LM4F 1 /* LM4F family */
# undef TM4C /* Not TM4C family */
# define TIVA_NTIMERS 6 /* Six 16/32-bit timers */
# define TIVA_NWIDETIMERS 6 /* Six 32/64-bit timers */
# define TIVA_NWDT 2 /* Two watchdog timer timers */
# define TIVA_NETHCONTROLLERS 0 /* No Ethernet controller */
# define TIVA_NLCD 0 /* No LCD controller */
# define TIVA_NSSI 4 /* Four SSI module */
# define TIVA_NUARTS 8 /* Eight UART modules */
# define TIVA_NI2C 4 /* Four I2C modules */
# define TIVA_NADC 2 /* Two ADC modules */
# define TIVA_NPWM 0 /* No PWM generator modules */
# define TIVA_NQEI 0 /* No quadrature encoders */
# define TIVA_NPORTS 6 /* 6 Ports (GPIOA-F), 0-43 GPIOs */
# define TIVA_NCANCONTROLLER 1 /* One CAN controller */
# define TIVA_NUSBOTGFS 0 /* No USB 2.0 OTG FS */
# define TIVA_NUSBOTGHS 0 /* No USB 2.0 OTG HS */
# define TIVA_NCRC 0 /* No CRC module */
# define TIVA_NAES 0 /* No AES module */
# define TIVA_NDES 0 /* No DES module */
# define TIVA_NHASH 0 /* No SHA1/MD5 hash module */
#elif defined(CONFIG_ARCH_CHIP_TM4C123GH6PGE) || defined(CONFIG_ARCH_CHIP_TM4C123GH6PZ) || \
defined(CONFIG_ARCH_CHIP_TM4C123GH6ZRB)
# undef LM3S /* Not LM3S family */
# undef LM4F /* Not LM4F family */
# define TM4C 1 /* TM4C family */
# define TIVA_NTIMERS 6 /* Six 16/32-bit timers */
# define TIVA_NWIDETIMERS 6 /* Six 32/64-bit timers */
# define TIVA_NWDT 2 /* Two watchdog timers */
# define TIVA_NETHCONTROLLERS 0 /* No Ethernet controller */
# define TIVA_NLCD 0 /* No LCD controller */
# define TIVA_NSSI 4 /* Four SSI module */
# define TIVA_NUARTS 8 /* Eight UART modules */
# define TIVA_NI2C 6 /* Six I2C modules */
# define TIVA_NADC 2 /* Two ADC modules */
# define TIVA_NPWM 2 /* Two PWM generator modules */
# define TIVA_NQEI 1 /* One quadrature encoders */
# define TIVA_NPORTS 15 /* Fifteen Ports (GPIOA-H, J-N, P-Q) */
# define TIVA_NCANCONTROLLER 2 /* Two CAN controllers */
# define TIVA_NUSBOTGFS 1 /* One USB 2.0 OTG FS */
# define TIVA_NUSBOTGHS 0 /* No USB 2.0 OTG HS */
# define TIVA_NCRC 0 /* No CRC module */
# define TIVA_NAES 0 /* No AES module */
# define TIVA_NDES 0 /* No DES module */
# define TIVA_NHASH 0 /* No SHA1/MD5 hash module */
#elif defined(CONFIG_ARCH_CHIP_TM4C123GH6PMI)
# undef LM3S /* Not LM3S family */
# undef LM4F /* Not LM4F family */
# define TM4C 1 /* TM4C family */
# define TIVA_NTIMERS 6 /* Six 16/32-bit timers */
# define TIVA_NWIDETIMERS 6 /* Six 32/64-bit timers */
# define TIVA_NWDT 2 /* Two watchdog timers */
# define TIVA_NETHCONTROLLERS 0 /* No Ethernet controller */
# define TIVA_NLCD 0 /* No LCD controller */
# define TIVA_NSSI 4 /* Four SSI module */
# define TIVA_NUARTS 8 /* Eight UART modules */
# define TIVA_NI2C 4 /* Four I2C modules */
# define TIVA_NADC 2 /* Two ADC modules */
# define TIVA_NPWM 2 /* Two PWM generator modules */
# define TIVA_NQEI 2 /* Two quadrature encoders */
# define TIVA_NPORTS 6 /* Six Ports (GPIOA-F) */
# define TIVA_NCANCONTROLLER 2 /* Two CAN controllers */
# define TIVA_NUSBOTGFS 1 /* One USB 2.0 OTG FS */
# define TIVA_NUSBOTGHS 0 /* No USB 2.0 OTG HS */
# define TIVA_NCRC 0 /* No CRC module */
# define TIVA_NAES 0 /* No AES module */
# define TIVA_NDES 0 /* No DES module */
# define TIVA_NHASH 0 /* No SHA1/MD5 hash module */
#elif defined(CONFIG_ARCH_CHIP_TM4C1294NC)
# undef LM3S /* Not LM3S family */
# undef LM4F /* Not LM4F family */
# define TM4C 1 /* TM4C family */
# define TIVA_NTIMERS 8 /* Eight Dual 16/32-bit timers A/B */
# define TIVA_NWIDETIMERS 0 /* No 32/64-bit timers */
# define TIVA_NWDT 2 /* Two watchdog timers */
# define TIVA_NETHCONTROLLERS 1 /* One 10/100Mbit Ethernet controller */
# define TIVA_NLCD 1 /* One LCD controller */
# define TIVA_NSSI 4 /* Four SSI modules */
# define TIVA_NUARTS 8 /* Eight UART modules */
# define TIVA_NI2C 10 /* Ten I2C modules */
# define TIVA_NADC 2 /* Two ADC modules */
# define TIVA_NPWM 4 /* Four PWM generator modules */
# define TIVA_NQEI 1 /* One quadrature encoders */
# define TIVA_NPORTS 15 /* Fifteen Ports (GPIOA-H, J-N, P-Q) */
# define TIVA_NCANCONTROLLER 2 /* Two CAN controllers */
# define TIVA_NUSBOTGFS 0 /* No USB 2.0 OTG FS */
# define TIVA_NUSBOTGHS 1 /* One USB 2.0 OTG HS */
# define TIVA_NCRC 1 /* One CRC module */
# define TIVA_NAES 0 /* No AES module */
# define TIVA_NDES 0 /* No DES module */
# define TIVA_NHASH 0 /* No SHA1/MD5 hash module */
#elif defined(CONFIG_ARCH_CHIP_TM4C129XNC)
# undef LM3S /* Not LM3S family */
# undef LM4F /* Not LM4F family */
# define TM4C 1 /* TM4C family */
# define TIVA_NTIMERS 8 /* Eight Dual 16/32-bit timers A/B */
# define TIVA_NWIDETIMERS 0 /* No 32/64-bit timers */
# define TIVA_NWDT 2 /* Two watchdog timers */
# define TIVA_NETHCONTROLLERS 1 /* One 10/100Mbit Ethernet controller */
# define TIVA_NLCD 1 /* One LCD controller */
# define TIVA_NSSI 4 /* Four SSI modules */
# define TIVA_NUARTS 8 /* Eight UART modules */
# define TIVA_NI2C 10 /* Ten I2C modules */
# define TIVA_NADC 2 /* Two ADC modules */
# define TIVA_NPWM 4 /* Four PWM generator modules */
# define TIVA_NQEI 1 /* One quadrature encoder module */
# define TIVA_NPORTS 18 /* Eighteen Ports (GPIOA-H, J-N, P-T) */
# define TIVA_NCANCONTROLLER 2 /* Two CAN controllers */
# define TIVA_NUSBOTGFS 0 /* No USB 2.0 OTG FS */
# define TIVA_NUSBOTGHS 1 /* One USB 2.0 OTG HS */
# define TIVA_NCRC 1 /* One CRC module */
# define TIVA_NAES 1 /* One AES module */
# define TIVA_NDES 1 /* One DES module */
# define TIVA_NHASH 1 /* One SHA1/MD5 hash module */
#elif defined(CONFIG_ARCH_CHIP_CC3200)
# undef LM3S /* Not LM3S family */
# undef LM4F /* Not LM4F family */
# define TM4C 1 /* TM4C family */
# define TIVA_NTIMERS 4 /* Four 16/32-bit timers */
# define TIVA_NWIDETIMERS 2 /* Two 32/64-bit timers */
# define TIVA_NETHCONTROLLERS 0 /* No Ethernet controller */
# define TIVA_NLCD 0 /* No LCD controller */
# define TIVA_NSSI 0 /* No SSI module */
# define TIVA_NUARTS 2 /* Two UART modules */
# define TIVA_NI2C 2 /* Two I2C modules */
# define TIVA_NADC 3 /* Three ADC modules */
# define TIVA_NPWM 0 /* No PWM generator modules */
# define TIVA_NQEI 0 /* No quadrature encoders */
# define TIVA_NPORTS 4 /* 4 Ports (GPIOA-D), 0-31 GPIOs */
# define TIVA_DES 1 /* 1 DES hw crypto */
# define TIVA_AES 1 /* 1 AES hw crypto */
# define TIVA_CRC 1 /* 1 CRC hw crypto */
# define TIVA_SHA 1 /* 1 SHA/MD5 hw crypto */
# define TIVA_SPI 2 /* Two SPI modules */
# define TIVA_NCANCONTROLLER 0 /* No CAN controllers */
# define TIVA_NCRC 0 /* No CRC module */
# define TIVA_NAES 0 /* No AES module */
# define TIVA_NDES 0 /* No DES module */
# define TIVA_NHASH 0 /* No SHA1/MD5 hash module */
#else
# error "Capabilities not specified for this TIVA/Stellaris chip"
#endif
/* The TIVA/Stellaris only supports 8 priority levels. The hardware priority
* mechanism will only look at the upper N bits of the 8-bit priority level
* (where N is 3 for the Tiva/Stellaris family), so any prioritization must be
* performed in those bits. The default priority level is set to the middle
* value
*/
#define NVIC_SYSH_PRIORITY_MIN 0xe0 /* Bits [5:7] set in minimum priority */
#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */
#define NVIC_SYSH_PRIORITY_STEP 0x20 /* Three bits of interrupt priority used */
/* If CONFIG_ARMV7M_USEBASEPRI is selected, then interrupts will be disabled
* by setting the BASEPRI register to NVIC_SYSH_DISABLE_PRIORITY so that most
* interrupts will not have execution priority. SVCall must have execution
* priority in all cases.
*
* In the normal cases, interrupts are not nest-able and all interrupts run
* at an execution priority between NVIC_SYSH_PRIORITY_MIN and
* NVIC_SYSH_PRIORITY_MAX (with NVIC_SYSH_PRIORITY_MAX reserved for SVCall).
*
* If, in addition, CONFIG_ARCH_HIPRI_INTERRUPT is defined, then special
* high priority interrupts are supported. These are not "nested" in the
* normal sense of the word. These high priority interrupts can interrupt
* normal processing but execute outside of OS (although they can "get back
* into the game" via a PendSV interrupt).
*
* In the normal course of things, interrupts must occasionally be disabled
* using the irqsave() inline function to prevent contention in use of
* resources that may be shared between interrupt level and non-interrupt
* level logic. Now the question arises, if CONFIG_ARCH_HIPRI_INTERRUPT,
* do we disable all interrupts (except SVCall), or do we only disable the
* "normal" interrupts. Since the high priority interrupts cannot interact
* with the OS, you may want to permit the high priority interrupts even if
* interrupts are disabled. The setting CONFIG_ARCH_INT_DISABLEALL can be
* used to select either behavior:
*
* ----------------------------+--------------+----------------------------
* CONFIG_ARCH_HIPRI_INTERRUPT | NO | YES
* ----------------------------+--------------+--------------+-------------
* CONFIG_ARCH_INT_DISABLEALL | N/A | YES | NO
* ----------------------------+--------------+--------------+-------------
* | | | SVCall
* | SVCall | SVCall | HIGH
* Disable here and below --------> MAXNORMAL ---> HIGH --------> MAXNORMAL
* | | MAXNORMAL |
* ----------------------------+--------------+--------------+-------------
*/
#if defined(CONFIG_ARCH_HIPRI_INTERRUPT) && defined(CONFIG_ARCH_INT_DISABLEALL)
# define NVIC_SYSH_MAXNORMAL_PRIORITY (NVIC_SYSH_PRIORITY_MAX + 2*NVIC_SYSH_PRIORITY_STEP)
# define NVIC_SYSH_HIGH_PRIORITY (NVIC_SYSH_PRIORITY_MAX + NVIC_SYSH_PRIORITY_STEP)
# define NVIC_SYSH_DISABLE_PRIORITY NVIC_SYSH_HIGH_PRIORITY
# define NVIC_SYSH_SVCALL_PRIORITY NVIC_SYSH_PRIORITY_MAX
#else
# define NVIC_SYSH_MAXNORMAL_PRIORITY (NVIC_SYSH_PRIORITY_MAX + NVIC_SYSH_PRIORITY_STEP)
# define NVIC_SYSH_HIGH_PRIORITY NVIC_SYSH_PRIORITY_MAX
# define NVIC_SYSH_DISABLE_PRIORITY NVIC_SYSH_MAXNORMAL_PRIORITY
# define NVIC_SYSH_SVCALL_PRIORITY NVIC_SYSH_PRIORITY_MAX
#endif
/************************************************************************************
* Public Types
************************************************************************************/
/************************************************************************************
* Public Data
************************************************************************************/
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_INCLUDE_TIVA_CHIP_H */

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arch/arm/include/tiva/irq.h
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@ -1,463 +0,0 @@
/************************************************************************************
* arch/arm/include/tiva/irq.h
*
* Copyright (C) 2009-2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_INCLUDE_TIVA_IRQ_H
#define __ARCH_ARM_INCLUDE_TIVA_IRQ_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include <arch/tiva/chip.h>
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
#if defined(CONFIG_ARCH_CHIP_LM3S) || defined(CONFIG_ARCH_CHIP_LM4F) || \
defined(CONFIG_ARCH_CHIP_CC3200)
/* I don't believe that any of these families support interrupts on port J. Many
* do not support interrupts on port H either.
*/
# undef CONFIG_TIVA_GPIOJ_IRQS
#elif defined(CONFIG_ARCH_CHIP_TM4C)
/* The TM4C123GH6PMI supports ports A-F of which any can support interrupts */
# if defined(CONFIG_ARCH_CHIP_TM4C123GH6PMI)
# undef CONFIG_TIVA_GPIOP_IRQS /* P-Q */
# undef CONFIG_TIVA_GPIOQ_IRQS
/* The TM4C123GH6PGE supports interrupts only on port P */
# elif defined(CONFIG_ARCH_CHIP_TM4C123GH6PGE)
# undef CONFIG_TIVA_GPIOA_IRQS /* A-F */
# undef CONFIG_TIVA_GPIOB_IRQS
# undef CONFIG_TIVA_GPIOC_IRQS
# undef CONFIG_TIVA_GPIOD_IRQS
# undef CONFIG_TIVA_GPIOE_IRQS
# undef CONFIG_TIVA_GPIOF_IRQS
# undef CONFIG_TIVA_GPIOQ_IRQS /* Q */
/* The TM4C123GH6ZRB and the TM4C129x support interrupts only on ports P and Q. */
# else
# undef CONFIG_TIVA_GPIOA_IRQS /* A-F */
# undef CONFIG_TIVA_GPIOB_IRQS
# undef CONFIG_TIVA_GPIOC_IRQS
# undef CONFIG_TIVA_GPIOD_IRQS
# undef CONFIG_TIVA_GPIOE_IRQS
# undef CONFIG_TIVA_GPIOF_IRQS
# endif
/* No supported architecture supports interrupts on ports G-N or R-T */
# undef CONFIG_TIVA_GPIOG_IRQS /* G-N */
# undef CONFIG_TIVA_GPIOH_IRQS
# undef CONFIG_TIVA_GPIOJ_IRQS
# undef CONFIG_TIVA_GPIOK_IRQS
# undef CONFIG_TIVA_GPIOL_IRQS
# undef CONFIG_TIVA_GPIOM_IRQS
# undef CONFIG_TIVA_GPION_IRQS
# undef CONFIG_TIVA_GPIOR_IRQS /* R-T */
# undef CONFIG_TIVA_GPIOS_IRQS
# undef CONFIG_TIVA_GPIOT_IRQS
#endif
/* Mark GPIO interrupts as disabled for non-existent GPIO ports. */
#if TIVA_NPORTS < 1
# undef CONFIG_TIVA_GPIOA_IRQS
#endif
#if TIVA_NPORTS < 2
# undef CONFIG_TIVA_GPIOB_IRQS
#endif
#if TIVA_NPORTS < 3
# undef CONFIG_TIVA_GPIOC_IRQS
#endif
#if TIVA_NPORTS < 4
# undef CONFIG_TIVA_GPIOD_IRQS
#endif
#if TIVA_NPORTS < 5
# undef CONFIG_TIVA_GPIOE_IRQS
#endif
#if TIVA_NPORTS < 6
# undef CONFIG_TIVA_GPIOF_IRQS
#endif
#if TIVA_NPORTS < 7
# undef CONFIG_TIVA_GPIOG_IRQS
#endif
#if TIVA_NPORTS < 8
# undef CONFIG_TIVA_GPIOH_IRQS
#endif
#if TIVA_NPORTS < 9
# undef CONFIG_TIVA_GPIOJ_IRQS
#endif
#if TIVA_NPORTS < 10
# undef CONFIG_TIVA_GPIOK_IRQS
#endif
#if TIVA_NPORTS < 11
# undef CONFIG_TIVA_GPIOL_IRQS
#endif
#if TIVA_NPORTS < 12
# undef CONFIG_TIVA_GPIOM_IRQS
#endif
#if TIVA_NPORTS < 13
# undef CONFIG_TIVA_GPION_IRQS
#endif
#if TIVA_NPORTS < 14
# undef CONFIG_TIVA_GPIOP_IRQS
#endif
#if TIVA_NPORTS < 15
# undef CONFIG_TIVA_GPIOQ_IRQS
#endif
#if TIVA_NPORTS < 16
# undef CONFIG_TIVA_GPIOQ_IRQS
#endif
#if TIVA_NPORTS < 17
# undef CONFIG_TIVA_GPIOQ_IRQS
#endif
#if TIVA_NPORTS < 18
# undef CONFIG_TIVA_GPIOQ_IRQS
#endif
/* Processor Exceptions (vectors 0-15) */
#define TIVA_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG) */
/* Vector 0: Reset stack pointer value */
/* Vector 1: Reset (not handler as an IRQ) */
#define TIVA_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */
#define TIVA_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */
#define TIVA_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */
#define TIVA_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */
#define TIVA_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */
#define TIVA_IRQ_SVCALL (11) /* Vector 11: SVC call */
#define TIVA_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */
/* Vector 13: Reserved */
#define TIVA_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */
#define TIVA_IRQ_SYSTICK (15) /* Vector 15: System tick */
#if defined(CONFIG_ARCH_CHIP_LM3S)
# include <arch/tiva/lm3s_irq.h>
#elif defined(CONFIG_ARCH_CHIP_LM4F)
# include <arch/tiva/lm4f_irq.h>
#elif defined(CONFIG_ARCH_CHIP_TM4C)
# include <arch/tiva/tm4c_irq.h>
#elif defined(CONFIG_ARCH_CHIP_CC3200)
# include <arch/tiva/cc3200_irq.h>
#else
# error "Unsupported Stellaris IRQ file"
#endif
#define NR_VECTORS (NR_IRQS - 16)
/* GPIO IRQs -- Note that support for individual GPIO ports can
* be disabled in order to reduce the size of the implementation.
*/
#if defined(CONFIG_TIVA_GPIOA_IRQS)
# define TIVA_IRQ_GPIOA_0 (NR_IRQS + 0)
# define TIVA_IRQ_GPIOA_1 (NR_IRQS + 1)
# define TIVA_IRQ_GPIOA_2 (NR_IRQS + 2)
# define TIVA_IRQ_GPIOA_3 (NR_IRQS + 3)
# define TIVA_IRQ_GPIOA_4 (NR_IRQS + 4)
# define TIVA_IRQ_GPIOA_5 (NR_IRQS + 5)
# define TIVA_IRQ_GPIOA_6 (NR_IRQS + 6)
# define TIVA_IRQ_GPIOA_7 (NR_IRQS + 7)
# define _NGPIOAIRQS (NR_IRQS + 8)
#else
# define _NGPIOAIRQS NR_IRQS
#endif
#if defined(CONFIG_TIVA_GPIOB_IRQS)
# define TIVA_IRQ_GPIOB_0 (_NGPIOAIRQS + 0)
# define TIVA_IRQ_GPIOB_1 (_NGPIOAIRQS + 1)
# define TIVA_IRQ_GPIOB_2 (_NGPIOAIRQS + 2)
# define TIVA_IRQ_GPIOB_3 (_NGPIOAIRQS + 3)
# define TIVA_IRQ_GPIOB_4 (_NGPIOAIRQS + 4)
# define TIVA_IRQ_GPIOB_5 (_NGPIOAIRQS + 5)
# define TIVA_IRQ_GPIOB_6 (_NGPIOAIRQS + 6)
# define TIVA_IRQ_GPIOB_7 (_NGPIOAIRQS + 7)
# define _NGPIOBIRQS (_NGPIOAIRQS + 8)
#else
# define _NGPIOBIRQS _NGPIOAIRQS
#endif
#if defined(CONFIG_TIVA_GPIOC_IRQS)
# define TIVA_IRQ_GPIOC_0 (_NGPIOBIRQS + 0)
# define TIVA_IRQ_GPIOC_1 (_NGPIOBIRQS + 1)
# define TIVA_IRQ_GPIOC_2 (_NGPIOBIRQS + 2)
# define TIVA_IRQ_GPIOC_3 (_NGPIOBIRQS + 3)
# define TIVA_IRQ_GPIOC_4 (_NGPIOBIRQS + 4)
# define TIVA_IRQ_GPIOC_5 (_NGPIOBIRQS + 5)
# define TIVA_IRQ_GPIOC_6 (_NGPIOBIRQS + 6)
# define TIVA_IRQ_GPIOC_7 (_NGPIOBIRQS + 7)
# define _NGPIOCIRQS (_NGPIOBIRQS + 8)
#else
# define _NGPIOCIRQS _NGPIOBIRQS
#endif
#if defined(CONFIG_TIVA_GPIOD_IRQS)
# define TIVA_IRQ_GPIOD_0 (_NGPIOCIRQS + 0)
# define TIVA_IRQ_GPIOD_1 (_NGPIOCIRQS + 1)
# define TIVA_IRQ_GPIOD_2 (_NGPIOCIRQS + 2)
# define TIVA_IRQ_GPIOD_3 (_NGPIOCIRQS + 3)
# define TIVA_IRQ_GPIOD_4 (_NGPIOCIRQS + 4)
# define TIVA_IRQ_GPIOD_5 (_NGPIOCIRQS + 5)
# define TIVA_IRQ_GPIOD_6 (_NGPIOCIRQS + 6)
# define TIVA_IRQ_GPIOD_7 (_NGPIOCIRQS + 7)
# define _NGPIODIRQS (_NGPIOCIRQS + 8)
#else
# define _NGPIODIRQS _NGPIOCIRQS
#endif
#if defined(CONFIG_TIVA_GPIOE_IRQS)
# define TIVA_IRQ_GPIOE_0 (_NGPIODIRQS + 0)
# define TIVA_IRQ_GPIOE_1 (_NGPIODIRQS + 1)
# define TIVA_IRQ_GPIOE_2 (_NGPIODIRQS + 2)
# define TIVA_IRQ_GPIOE_3 (_NGPIODIRQS + 3)
# define TIVA_IRQ_GPIOE_4 (_NGPIODIRQS + 4)
# define TIVA_IRQ_GPIOE_5 (_NGPIODIRQS + 5)
# define TIVA_IRQ_GPIOE_6 (_NGPIODIRQS + 6)
# define TIVA_IRQ_GPIOE_7 (_NGPIODIRQS + 7)
# define _NGPIOEIRQS (_NGPIODIRQS + 8)
#else
# define _NGPIOEIRQS _NGPIODIRQS
#endif
#if defined(CONFIG_TIVA_GPIOF_IRQS)
# define TIVA_IRQ_GPIOF_0 (_NGPIOEIRQS + 0)
# define TIVA_IRQ_GPIOF_1 (_NGPIOEIRQS + 1)
# define TIVA_IRQ_GPIOF_2 (_NGPIOEIRQS + 2)
# define TIVA_IRQ_GPIOF_3 (_NGPIOEIRQS + 3)
# define TIVA_IRQ_GPIOF_4 (_NGPIOEIRQS + 4)
# define TIVA_IRQ_GPIOF_5 (_NGPIOEIRQS + 5)
# define TIVA_IRQ_GPIOF_6 (_NGPIOEIRQS + 6)
# define TIVA_IRQ_GPIOF_7 (_NGPIOEIRQS + 7)
# define _NGPIOFIRQS (_NGPIOEIRQS + 8)
#else
# define _NGPIOFIRQS _NGPIOEIRQS
#endif
#if defined(CONFIG_TIVA_GPIOG_IRQS)
# define TIVA_IRQ_GPIOG_0 (_NGPIOFIRQS + 0)
# define TIVA_IRQ_GPIOG_1 (_NGPIOFIRQS + 1)
# define TIVA_IRQ_GPIOG_2 (_NGPIOFIRQS + 2)
# define TIVA_IRQ_GPIOG_3 (_NGPIOFIRQS + 3)
# define TIVA_IRQ_GPIOG_4 (_NGPIOFIRQS + 4)
# define TIVA_IRQ_GPIOG_5 (_NGPIOFIRQS + 5)
# define TIVA_IRQ_GPIOG_6 (_NGPIOFIRQS + 6)
# define TIVA_IRQ_GPIOG_7 (_NGPIOFIRQS + 7)
# define _NGPIOGIRQS (_NGPIOFIRQS + 8)
#else
# define _NGPIOGIRQS _NGPIOFIRQS
#endif
#if defined(CONFIG_TIVA_GPIOH_IRQS)
# define TIVA_IRQ_GPIOH_0 (_NGPIOGIRQS + 0)
# define TIVA_IRQ_GPIOH_1 (_NGPIOGIRQS + 1)
# define TIVA_IRQ_GPIOH_2 (_NGPIOGIRQS + 2)
# define TIVA_IRQ_GPIOH_3 (_NGPIOGIRQS + 3)
# define TIVA_IRQ_GPIOH_4 (_NGPIOGIRQS + 4)
# define TIVA_IRQ_GPIOH_5 (_NGPIOGIRQS + 5)
# define TIVA_IRQ_GPIOH_6 (_NGPIOGIRQS + 6)
# define TIVA_IRQ_GPIOH_7 (_NGPIOGIRQS + 7)
# define _NGPIOHIRQS (_NGPIOGIRQS + 8)
#else
# define _NGPIOHIRQS _NGPIOGIRQS
#endif
#if defined(CONFIG_TIVA_GPIOJ_IRQS)
# define TIVA_IRQ_GPIOJ_0 (_NGPIOHIRQS + 0)
# define TIVA_IRQ_GPIOJ_1 (_NGPIOHIRQS + 1)
# define TIVA_IRQ_GPIOJ_2 (_NGPIOHIRQS + 2)
# define TIVA_IRQ_GPIOJ_3 (_NGPIOHIRQS + 3)
# define TIVA_IRQ_GPIOJ_4 (_NGPIOHIRQS + 4)
# define TIVA_IRQ_GPIOJ_5 (_NGPIOHIRQS + 5)
# define TIVA_IRQ_GPIOJ_6 (_NGPIOHIRQS + 6)
# define TIVA_IRQ_GPIOJ_7 (_NGPIOHIRQS + 7)
# define _NGPIOJIRQS (_NGPIOHIRQS + 8)
#else
# define _NGPIOJIRQS _NGPIOHIRQS
#endif
#if defined(CONFIG_TIVA_GPIOK_IRQS)
# define TIVA_IRQ_GPIOK_0 (_NGPIOJIRQS + 0)
# define TIVA_IRQ_GPIOK_1 (_NGPIOJIRQS + 1)
# define TIVA_IRQ_GPIOK_2 (_NGPIOJIRQS + 2)
# define TIVA_IRQ_GPIOK_3 (_NGPIOJIRQS + 3)
# define TIVA_IRQ_GPIOK_4 (_NGPIOJIRQS + 4)
# define TIVA_IRQ_GPIOK_5 (_NGPIOJIRQS + 5)
# define TIVA_IRQ_GPIOK_6 (_NGPIOJIRQS + 6)
# define TIVA_IRQ_GPIOK_7 (_NGPIOJIRQS + 7)
# define _NGPIOKIRQS (_NGPIOJIRQS + 8)
#else
# define _NGPIOKIRQS _NGPIOJIRQS
#endif
#if defined(CONFIG_TIVA_GPIOL_IRQS)
# define TIVA_IRQ_GPIOL_0 (_NGPIOKIRQS + 0)
# define TIVA_IRQ_GPIOL_1 (_NGPIOKIRQS + 1)
# define TIVA_IRQ_GPIOL_2 (_NGPIOKIRQS + 2)
# define TIVA_IRQ_GPIOL_3 (_NGPIOKIRQS + 3)
# define TIVA_IRQ_GPIOL_4 (_NGPIOKIRQS + 4)
# define TIVA_IRQ_GPIOL_5 (_NGPIOKIRQS + 5)
# define TIVA_IRQ_GPIOL_6 (_NGPIOKIRQS + 6)
# define TIVA_IRQ_GPIOL_7 (_NGPIOKIRQS + 7)
# define _NGPIOLIRQS (_NGPIOKIRQS + 8)
#else
# define _NGPIOLIRQS _NGPIOKIRQS
#endif
#if defined(CONFIG_TIVA_GPIOM_IRQS)
# define TIVA_IRQ_GPIOM_0 (_NGPIOLIRQS + 0)
# define TIVA_IRQ_GPIOM_1 (_NGPIOLIRQS + 1)
# define TIVA_IRQ_GPIOM_2 (_NGPIOLIRQS + 2)
# define TIVA_IRQ_GPIOM_3 (_NGPIOLIRQS + 3)
# define TIVA_IRQ_GPIOM_4 (_NGPIOLIRQS + 4)
# define TIVA_IRQ_GPIOM_5 (_NGPIOLIRQS + 5)
# define TIVA_IRQ_GPIOM_6 (_NGPIOLIRQS + 6)
# define TIVA_IRQ_GPIOM_7 (_NGPIOLIRQS + 7)
# define _NGPIOMIRQS (_NGPIOLIRQS + 8)
#else
# define _NGPIOMIRQS _NGPIOLIRQS
#endif
#if defined(CONFIG_TIVA_GPION_IRQS)
# define TIVA_IRQ_GPION_0 (_NGPIOMIRQS + 0)
# define TIVA_IRQ_GPION_1 (_NGPIOMIRQS + 1)
# define TIVA_IRQ_GPION_2 (_NGPIOMIRQS + 2)
# define TIVA_IRQ_GPION_3 (_NGPIOMIRQS + 3)
# define TIVA_IRQ_GPION_4 (_NGPIOMIRQS + 4)
# define TIVA_IRQ_GPION_5 (_NGPIOMIRQS + 5)
# define TIVA_IRQ_GPION_6 (_NGPIOMIRQS + 6)
# define TIVA_IRQ_GPION_7 (_NGPIOMIRQS + 7)
# define _NGPIONIRQS (_NGPIOMIRQS + 8)
#else
# define _NGPIONIRQS _NGPIOMIRQS
#endif
#if defined(CONFIG_TIVA_GPIOP_IRQS)
# define TIVA_IRQ_GPIOP_0 (_NGPIONIRQS + 0)
# define TIVA_IRQ_GPIOP_1 (_NGPIONIRQS + 1)
# define TIVA_IRQ_GPIOP_2 (_NGPIONIRQS + 2)
# define TIVA_IRQ_GPIOP_3 (_NGPIONIRQS + 3)
# define TIVA_IRQ_GPIOP_4 (_NGPIONIRQS + 4)
# define TIVA_IRQ_GPIOP_5 (_NGPIONIRQS + 5)
# define TIVA_IRQ_GPIOP_6 (_NGPIONIRQS + 6)
# define TIVA_IRQ_GPIOP_7 (_NGPIONIRQS + 7)
# define _NGPIOPIRQS (_NGPIONIRQS + 8)
#else
# define _NGPIOPIRQS _NGPIONIRQS
#endif
#if defined(CONFIG_TIVA_GPIOQ_IRQS)
# define TIVA_IRQ_GPIOQ_0 (_NGPIOPIRQS + 0)
# define TIVA_IRQ_GPIOQ_1 (_NGPIOPIRQS + 1)
# define TIVA_IRQ_GPIOQ_2 (_NGPIOPIRQS + 2)
# define TIVA_IRQ_GPIOQ_3 (_NGPIOPIRQS + 3)
# define TIVA_IRQ_GPIOQ_4 (_NGPIOPIRQS + 4)
# define TIVA_IRQ_GPIOQ_5 (_NGPIOPIRQS + 5)
# define TIVA_IRQ_GPIOQ_6 (_NGPIOPIRQS + 6)
# define TIVA_IRQ_GPIOQ_7 (_NGPIOPIRQS + 7)
# define _NGPIOQIRQS (_NGPIOPIRQS + 8)
#else
# define _NGPIOQIRQS _NGPIOPIRQS
#endif
#if defined(CONFIG_TIVA_GPIOR_IRQS)
# define TIVA_IRQ_GPIOR_0 (_NGPIOQIRQS + 0)
# define TIVA_IRQ_GPIOR_1 (_NGPIOQIRQS + 1)
# define TIVA_IRQ_GPIOR_2 (_NGPIOQIRQS + 2)
# define TIVA_IRQ_GPIOR_3 (_NGPIOQIRQS + 3)
# define TIVA_IRQ_GPIOR_4 (_NGPIOQIRQS + 4)
# define TIVA_IRQ_GPIOR_5 (_NGPIOQIRQS + 5)
# define TIVA_IRQ_GPIOR_6 (_NGPIOQIRQS + 6)
# define TIVA_IRQ_GPIOR_7 (_NGPIOQIRQS + 7)
# define _NGPIORIRQS (_NGPIOQIRQS + 8)
#else
# define _NGPIORIRQS _NGPIOQIRQS
#endif
#if defined(CONFIG_TIVA_GPIOS_IRQS)
# define TIVA_IRQ_GPIOS_0 (_NGPIORIRQS + 0)
# define TIVA_IRQ_GPIOS_1 (_NGPIORIRQS + 1)
# define TIVA_IRQ_GPIOS_2 (_NGPIORIRQS + 2)
# define TIVA_IRQ_GPIOS_3 (_NGPIORIRQS + 3)
# define TIVA_IRQ_GPIOS_4 (_NGPIORIRQS + 4)
# define TIVA_IRQ_GPIOS_5 (_NGPIORIRQS + 5)
# define TIVA_IRQ_GPIOS_6 (_NGPIORIRQS + 6)
# define TIVA_IRQ_GPIOS_7 (_NGPIORIRQS + 7)
# define _NGPIOSIRQS (_NGPIORIRQS + 8)
#else
# define _NGPIOSIRQS _NGPIORIRQS
#endif
#if defined(CONFIG_TIVA_GPIOT_IRQS)
# define TIVA_IRQ_GPIOT_0 (_NGPIOSIRQS + 0)
# define TIVA_IRQ_GPIOT_1 (_NGPIOSIRQS + 1)
# define TIVA_IRQ_GPIOT_2 (_NGPIOSIRQS + 2)
# define TIVA_IRQ_GPIOT_3 (_NGPIOSIRQS + 3)
# define TIVA_IRQ_GPIOT_4 (_NGPIOSIRQS + 4)
# define TIVA_IRQ_GPIOT_5 (_NGPIOSIRQS + 5)
# define TIVA_IRQ_GPIOT_6 (_NGPIOSIRQS + 6)
# define TIVA_IRQ_GPIOT_7 (_NGPIOSIRQS + 7)
# define _NGPIOTIRQS (_NGPIOSIRQS + 8)
#else
# define _NGPIOTIRQS _NGPIOSIRQS
#endif
#define NR_GPIO_IRQS (_NGPIOTIRQS - NR_IRQS)
/************************************************************************************
* Public Types
************************************************************************************/
/************************************************************************************
* Public Data
************************************************************************************/
/************************************************************************************
* Public Functions
************************************************************************************/
#endif /* __ARCH_ARM_INCLUDE_TIVA_IRQ_H */

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arch/arm/include/tiva/lm3s_irq.h
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@ -1,411 +0,0 @@
/************************************************************************************
* arch/arm/include/tiva/lm3s_irq.h
*
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_INCLUDE_TIVA_LM3S_IRQ_H
#define __ARCH_ARM_INCLUDE_TIVA_LM3S_IRQ_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* IRQ numbers. The IRQ number corresponds vector number and hence map directly to
* bits in the NVIC. This does, however, waste several words of memory in the IRQ
* to handle mapping tables.
*/
/* External interrupts (vectors >= 16) */
#define TIVA_IRQ_INTERRUPTS (16) /* Vector number of the first external interrupt */
#if defined(CONFIG_ARCH_CHIP_LM3S6918)
# define TIVA_IRQ_GPIOA (16) /* Vector 16: GPIO Port A */
# define TIVA_IRQ_GPIOB (17) /* Vector 17: GPIO Port B */
# define TIVA_IRQ_GPIOC (18) /* Vector 18: GPIO Port C */
# define TIVA_IRQ_GPIOD (19) /* Vector 19: GPIO Port D */
# define TIVA_IRQ_GPIOE (20) /* Vector 20: GPIO Port E */
# define TIVA_IRQ_UART0 (21) /* Vector 21: UART 0 */
# define TIVA_IRQ_UART1 (22) /* Vector 22: UART 1 */
# define TIVA_IRQ_SSI0 (23) /* Vector 23: SSI 0 */
# define TIVA_IRQ_I2C0 (24) /* Vector 24: I2C 0 */
# define TIVA_RESERVED_25 (25) /* Vector 25: Reserved */
# define TIVA_RESERVED_26 (26) /* Vector 26: Reserved */
# define TIVA_RESERVED_27 (27) /* Vector 27: Reserved */
# define TIVA_RESERVED_28 (28) /* Vector 28: Reserved */
# define TIVA_RESERVED_29 (29) /* Vector 29: Reserved */
# define TIVA_IRQ_ADC0 (30) /* Vector 30: ADC Sequence 0 */
# define TIVA_IRQ_ADC1 (31) /* Vector 31: ADC Sequence 1 */
# define TIVA_IRQ_ADC2 (32) /* Vector 32: ADC Sequence 2 */
# define TIVA_IRQ_ADC3 (33) /* Vector 33: ADC Sequence 3 */
# define TIVA_IRQ_WDOG (34) /* Vector 34: Watchdog Timer */
# define TIVA_IRQ_TIMER0A (35) /* Vector 35: Timer 0 A */
# define TIVA_IRQ_TIMER0B (36) /* Vector 36: Timer 0 B */
# define TIVA_IRQ_TIMER1A (37) /* Vector 37: Timer 1 A */
# define TIVA_IRQ_TIMER1B (38) /* Vector 38: Timer 1 B */
# define TIVA_IRQ_TIMER2A (39) /* Vector 39: Timer 2 A */
# define TIVA_IRQ_TIMER2B (40) /* Vector 40: Timer 2 B */
# define TIVA_IRQ_COMPARE0 (41) /* Vector 41: Analog Comparator 0 */
# define TIVA_IRQ_COMPARE1 (42) /* Vector 42: Analog Comparator 1 */
# define TIVA_RESERVED_43 (43) /* Vector 43: Reserved */
# define TIVA_IRQ_SYSCON (44) /* Vector 44: System Control */
# define TIVA_IRQ_FLASHCON (45) /* Vector 45: FLASH Control */
# define TIVA_IRQ_GPIOF (46) /* Vector 46: GPIO Port F */
# define TIVA_IRQ_GPIOG (47) /* Vector 47: GPIO Port G */
# define TIVA_IRQ_GPIOH (48) /* Vector 48: GPIO Port H */
# define TIVA_RESERVED_49 (49) /* Vector 49: Reserved */
# define TIVA_IRQ_SSI1 (50) /* Vector 50: SSI 1 */
# define TIVA_IRQ_TIMER3A (51) /* Vector 51: Timer 3 A */
# define TIVA_IRQ_TIMER3B (52) /* Vector 52: Timer 3 B */
# define TIVA_IRQ_I2C1 (53) /* Vector 53: I2C 1 */
# define TIVA_RESERVED_54 (54) /* Vector 54: Reserved */
# define TIVA_RESERVED_55 (55) /* Vector 55: Reserved */
# define TIVA_RESERVED_56 (56) /* Vector 56: Reserved */
# define TIVA_RESERVED_57 (57) /* Vector 57: Reserved */
# define TIVA_IRQ_ETHCON (58) /* Vector 58: Ethernet Controller */
# define TIVA_IRQ_HIBERNATE (59) /* Vector 59: Hibernation Module */
# define TIVA_RESERVED_60 (60) /* Vector 60: Reserved */
# define TIVA_RESERVED_61 (61) /* Vector 61: Reserved */
# define TIVA_RESERVED_62 (62) /* Vector 62: Reserved */
# define TIVA_RESERVED_63 (63) /* Vector 63: Reserved */
# define TIVA_RESERVED_64 (64) /* Vector 64: Reserved */
# define TIVA_RESERVED_65 (65) /* Vector 65: Reserved */
# define TIVA_RESERVED_66 (66) /* Vector 66: Reserved */
# define TIVA_RESERVED_67 (67) /* Vector 67: Reserved */
# define TIVA_RESERVED_68 (68) /* Vector 68: Reserved */
# define TIVA_RESERVED_69 (69) /* Vector 69: Reserved */
# define TIVA_RESERVED_70 (70) /* Vector 70: Reserved */
# define NR_IRQS (71) /* (Really less because of reserved vectors) */
#elif defined(CONFIG_ARCH_CHIP_LM3S6432)
# define TIVA_IRQ_GPIOA (16) /* Vector 16: GPIO Port A */
# define TIVA_IRQ_GPIOB (17) /* Vector 17: GPIO Port B */
# define TIVA_IRQ_GPIOC (18) /* Vector 18: GPIO Port C */
# define TIVA_IRQ_GPIOD (19) /* Vector 19: GPIO Port D */
# define TIVA_IRQ_GPIOE (20) /* Vector 20: GPIO Port E */
# define TIVA_IRQ_UART0 (21) /* Vector 21: UART 0 */
# define TIVA_IRQ_UART1 (22) /* Vector 22: UART 1 */
# define TIVA_IRQ_SSI0 (23) /* Vector 23: SSI 0 */
# define TIVA_IRQ_I2C0 (24) /* Vector 24: I2C 0 */
# define TIVA_RESERVED_25 (25) /* Vector 25: Reserved */
# define TIVA_IRQ_PWM0 (26) /* Vector 26: PWM Generator 0 */
# define TIVA_RESERVED_27 (27) /* Vector 27: Reserved */
# define TIVA_RESERVED_28 (28) /* Vector 28: Reserved */
# define TIVA_RESERVED_29 (29) /* Vector 29: Reserved */
# define TIVA_IRQ_ADC0 (30) /* Vector 30: ADC Sequence 0 */
# define TIVA_IRQ_ADC1 (31) /* Vector 31: ADC Sequence 1 */
# define TIVA_IRQ_ADC2 (32) /* Vector 32: ADC Sequence 2 */
# define TIVA_IRQ_ADC3 (33) /* Vector 33: ADC Sequence 3 */
# define TIVA_IRQ_WDOG (34) /* Vector 34: Watchdog Timer */
# define TIVA_IRQ_TIMER0A (35) /* Vector 35: Timer 0 A */
# define TIVA_IRQ_TIMER0B (36) /* Vector 36: Timer 0 B */
# define TIVA_IRQ_TIMER1A (37) /* Vector 37: Timer 1 A */
# define TIVA_IRQ_TIMER1B (38) /* Vector 38: Timer 1 B */
# define TIVA_IRQ_TIMER2A (39) /* Vector 39: Timer 2 A */
# define TIVA_IRQ_TIMER2B (40) /* Vector 40: Timer 2 B */
# define TIVA_IRQ_COMPARE0 (41) /* Vector 41: Analog Comparator 0 */
# define TIVA_IRQ_COMPARE1 (42) /* Vector 42: Analog Comparator 1 */
# define TIVA_RESERVED_43 (43) /* Vector 43: Reserved */
# define TIVA_IRQ_SYSCON (44) /* Vector 44: System Control */
# define TIVA_IRQ_FLASHCON (45) /* Vector 45: FLASH Control */
# define TIVA_IRQ_GPIOF (46) /* Vector 46: GPIO Port F */
# define TIVA_IRQ_GPIOG (47) /* Vector 47: GPIO Port G */
# define TIVA_RESERVED_48 (48) /* Vector 48: Reserved */
# define TIVA_RESERVED_49 (49) /* Vector 49: Reserved */
# define TIVA_RESERVED_50 (50) /* Vector 50: Reserved */
# define TIVA_RESERVED_51 (51) /* Vector 51: Reserved */
# define TIVA_RESERVED_52 (52) /* Vector 52: Reserved */
# define TIVA_RESERVED_53 (53) /* Vector 53: Reserved */
# define TIVA_RESERVED_54 (54) /* Vector 54: Reserved */
# define TIVA_RESERVED_55 (55) /* Vector 55: Reserved */
# define TIVA_RESERVED_56 (56) /* Vector 56: Reserved */
# define TIVA_RESERVED_57 (57) /* Vector 57: Reserved */
# define TIVA_IRQ_ETHCON (58) /* Vector 58: Ethernet Controller */
# define TIVA_RESERVED_59 (59) /* Vector 59: Reserved */
# define TIVA_RESERVED_60 (60) /* Vector 60: Reserved */
# define TIVA_RESERVED_61 (61) /* Vector 61: Reserved */
# define TIVA_RESERVED_62 (62) /* Vector 62: Reserved */
# define TIVA_RESERVED_63 (63) /* Vector 63: Reserved */
# define TIVA_RESERVED_64 (64) /* Vector 64: Reserved */
# define TIVA_RESERVED_65 (65) /* Vector 65: Reserved */
# define TIVA_RESERVED_66 (66) /* Vector 66: Reserved */
# define TIVA_RESERVED_67 (67) /* Vector 67: Reserved */
# define TIVA_RESERVED_68 (68) /* Vector 68: Reserved */
# define TIVA_RESERVED_69 (69) /* Vector 69: Reserved */
# define TIVA_RESERVED_70 (70) /* Vector 70: Reserved */
# define NR_IRQS (71) /* (Really less because of reserved vectors) */
#elif defined(CONFIG_ARCH_CHIP_LM3S6965)
# define TIVA_IRQ_GPIOA (16) /* Vector 16: GPIO Port A */
# define TIVA_IRQ_GPIOB (17) /* Vector 17: GPIO Port B */
# define TIVA_IRQ_GPIOC (18) /* Vector 18: GPIO Port C */
# define TIVA_IRQ_GPIOD (19) /* Vector 19: GPIO Port D */
# define TIVA_IRQ_GPIOE (20) /* Vector 20: GPIO Port E */
# define TIVA_IRQ_UART0 (21) /* Vector 21: UART 0 */
# define TIVA_IRQ_UART1 (22) /* Vector 22: UART 1 */
# define TIVA_IRQ_SSI0 (23) /* Vector 23: SSI 0 */
# define TIVA_IRQ_I2C0 (24) /* Vector 24: I2C 0 */
# define TIVA_IRQ_PWMFAULT (25) /* Vector 25: PWM Fault */
# define TIVA_IRQ_PWM0 (26) /* Vector 26: PWM Generator 0 */
# define TIVA_IRQ_PWM1 (27) /* Vector 27: PWM Generator 1 */
# define TIVA_IRQ_PWM2 (28) /* Vector 28: PWM Generator 2 */
# define TIVA_IRQ_QEI0 (29) /* Vector 29: QEI0 */
# define TIVA_IRQ_ADC0 (30) /* Vector 30: ADC Sequence 0 */
# define TIVA_IRQ_ADC1 (31) /* Vector 31: ADC Sequence 1 */
# define TIVA_IRQ_ADC2 (32) /* Vector 32: ADC Sequence 2 */
# define TIVA_IRQ_ADC3 (33) /* Vector 33: ADC Sequence 3 */
# define TIVA_IRQ_WDOG (34) /* Vector 34: Watchdog Timer */
# define TIVA_IRQ_TIMER0A (35) /* Vector 35: Timer 0 A */
# define TIVA_IRQ_TIMER0B (36) /* Vector 36: Timer 0 B */
# define TIVA_IRQ_TIMER1A (37) /* Vector 37: Timer 1 A */
# define TIVA_IRQ_TIMER1B (38) /* Vector 38: Timer 1 B */
# define TIVA_IRQ_TIMER2A (39) /* Vector 39: Timer 2 A */
# define TIVA_IRQ_TIMER2B (40) /* Vector 40: Timer 2 B */
# define TIVA_IRQ_COMPARE0 (41) /* Vector 41: Analog Comparator 0 */
# define TIVA_IRQ_COMPARE1 (42) /* Vector 42: Analog Comparator 1 */
# define TIVA_RESERVED_43 (43) /* Vector 43: Reserved */
# define TIVA_IRQ_SYSCON (44) /* Vector 44: System Control */
# define TIVA_IRQ_FLASHCON (45) /* Vector 45: FLASH Control */
# define TIVA_IRQ_GPIOF (46) /* Vector 46: GPIO Port F */
# define TIVA_IRQ_GPIOG (47) /* Vector 47: GPIO Port G */
# define TIVA_RESERVED_48 (48) /* Vector 48: Reserved */
# define TIVA_IRQ_UART2 (49) /* Vector 49: UART 2 */
# define TIVA_RESERVED_50 (50) /* Vector 50: Reserved */
# define TIVA_IRQ_TIMER3A (51) /* Vector 51: Timer 3 A */
# define TIVA_IRQ_TIMER3B (52) /* Vector 52: Timer 3 B */
# define TIVA_IRQ_I2C1 (53) /* Vector 53: I2C 1 */
# define TIVA_IRQ_QEI1 (54) /* Vector 54: QEI1 */
# define TIVA_RESERVED_55 (55) /* Vector 55: Reserved */
# define TIVA_RESERVED_56 (56) /* Vector 56: Reserved */
# define TIVA_RESERVED_57 (57) /* Vector 57: Reserved */
# define TIVA_IRQ_ETHCON (58) /* Vector 58: Ethernet Controller */
# define TIVA_IRQ_HIBERNATE (59) /* Vector 59: Hibernation Module */
# define TIVA_RESERVED_60 (60) /* Vector 60: Reserved */
# define TIVA_RESERVED_61 (61) /* Vector 61: Reserved */
# define TIVA_RESERVED_62 (62) /* Vector 62: Reserved */
# define TIVA_RESERVED_63 (63) /* Vector 63: Reserved */
# define TIVA_RESERVED_64 (64) /* Vector 64: Reserved */
# define TIVA_RESERVED_65 (65) /* Vector 65: Reserved */
# define TIVA_RESERVED_66 (66) /* Vector 66: Reserved */
# define TIVA_RESERVED_67 (67) /* Vector 67: Reserved */
# define TIVA_RESERVED_68 (68) /* Vector 68: Reserved */
# define TIVA_RESERVED_69 (69) /* Vector 69: Reserved */
# define TIVA_RESERVED_70 (70) /* Vector 70: Reserved */
# define NR_IRQS (71) /* (Really less because of reserved vectors) */
#elif defined(CONFIG_ARCH_CHIP_LM3S9B96)
# define TIVA_IRQ_GPIOA (16) /* Vector 16: GPIO Port A */
# define TIVA_IRQ_GPIOB (17) /* Vector 17: GPIO Port B */
# define TIVA_IRQ_GPIOC (18) /* Vector 18: GPIO Port C */
# define TIVA_IRQ_GPIOD (19) /* Vector 19: GPIO Port D */
# define TIVA_IRQ_GPIOE (20) /* Vector 20: GPIO Port E */
# define TIVA_IRQ_UART0 (21) /* Vector 21: UART 0 */
# define TIVA_IRQ_UART1 (22) /* Vector 22: UART 1 */
# define TIVA_IRQ_SSI0 (23) /* Vector 23: SSI 0 */
# define TIVA_IRQ_I2C0 (24) /* Vector 24: I2C 0 */
# define TIVA_IRQ_PWMFAULT (25) /* Vector 25: PWM Fault */
# define TIVA_IRQ_PWM0 (26) /* Vector 26: PWM Generator 0 */
# define TIVA_IRQ_PWM1 (27) /* Vector 27: PWM Generator 1 */
# define TIVA_IRQ_PWM2 (28) /* Vector 28: PWM Generator 2 */
# define TIVA_IRQ_QEI0 (29) /* Vector 29: QEI0 */
# define TIVA_IRQ_ADC0 (30) /* Vector 30: ADC0 Sequence 0 */
# define TIVA_IRQ_ADC1 (31) /* Vector 31: ADC0 Sequence 1 */
# define TIVA_IRQ_ADC2 (32) /* Vector 32: ADC0 Sequence 2 */
# define TIVA_IRQ_ADC3 (33) /* Vector 33: ADC0 Sequence 3 */
# define TIVA_IRQ_WDOG (34) /* Vector 34: Watchdog Timer */
# define TIVA_IRQ_TIMER0A (35) /* Vector 35: Timer 0 A */
# define TIVA_IRQ_TIMER0B (36) /* Vector 36: Timer 0 B */
# define TIVA_IRQ_TIMER1A (37) /* Vector 37: Timer 1 A */
# define TIVA_IRQ_TIMER1B (38) /* Vector 38: Timer 1 B */
# define TIVA_IRQ_TIMER2A (39) /* Vector 39: Timer 2 A */
# define TIVA_IRQ_TIMER2B (40) /* Vector 40: Timer 2 B */
# define TIVA_IRQ_COMPARE0 (41) /* Vector 41: Analog Comparator 0 */
# define TIVA_IRQ_COMPARE1 (42) /* Vector 42: Analog Comparator 1 */
# define TIVA_IRQ_COMPARE2 (43) /* Vector 43: Analog Comparator 3 */
# define TIVA_IRQ_SYSCON (44) /* Vector 44: System Control */
# define TIVA_IRQ_FLASHCON (45) /* Vector 45: FLASH Control */
# define TIVA_IRQ_GPIOF (46) /* Vector 46: GPIO Port F */
# define TIVA_IRQ_GPIOG (47) /* Vector 47: GPIO Port G */
# define TIVA_IRQ_GPIOH (48) /* Vector 48: GPIO Port H */
# define TIVA_IRQ_UART2 (49) /* Vector 49: UART 2 */
# define TIVA_IRQ_SSI1 (50) /* Vector 50: SSI 1 */
# define TIVA_IRQ_TIMER3A (51) /* Vector 51: Timer 3 A */
# define TIVA_IRQ_TIMER3B (52) /* Vector 52: Timer 3 B */
# define TIVA_IRQ_I2C1 (53) /* Vector 53: I2C 1 */
# define TIVA_IRQ_QEI1 (54) /* Vector 54: QEI1 */
# define TIVA_IRQ_CAN0 (55) /* Vector 55: CAN 1 */
# define TIVA_IRQ_CAN1 (56) /* Vector 56: CAN 2 */
# define TIVA_RESERVED_57 (57) /* Vector 57: Reserved */
# define TIVA_IRQ_ETHCON (58) /* Vector 58: Ethernet Controller */
# define TIVA_RESERVED_59 (59) /* Vector 59: Reserved */
# define TIVA_IRQ_USB (60) /* Vector 60: USB */
# define TIVA_IRQ_PWM3 (61) /* Vector 61: PWM Generator 3 */
# define TIVA_IRQ_UDMASOFT (62) /* Vector 62: uDMA Software */
# define TIVA_IRQ_UDMAERROR (63) /* Vector 63: uDMA Error */
# define TIVA_IRQ_ADC1_0 (64) /* Vector 64: ADC1 Sequence 0 */
# define TIVA_IRQ_ADC1_1 (65) /* Vector 65: ADC1 Sequence 1 */
# define TIVA_IRQ_ADC1_2 (66) /* Vector 66: ADC1 Sequence 2 */
# define TIVA_IRQ_ADC1_3 (67) /* Vector 67: ADC1 Sequence 3 */
# define TIVA_IRQ_I2S0 (68) /* Vector 68: I2S0 */
# define TIVA_IRQ_EPI (69) /* Vector 69: EPI */
# define TIVA_IRQ_GPIOJ (70) /* Vector 70: GPIO Port J */
# define TIVA_RESERVED_71 (71) /* Vector 71: Reserved */
# define NR_IRQS (72) /* (Really less because of reserved vectors) */
#elif defined(CONFIG_ARCH_CHIP_LM3S8962)
# define TIVA_IRQ_GPIOA (16) /* Vector 16: GPIO Port A */
# define TIVA_IRQ_GPIOB (17) /* Vector 17: GPIO Port B */
# define TIVA_IRQ_GPIOC (18) /* Vector 18: GPIO Port C */
# define TIVA_IRQ_GPIOD (19) /* Vector 19: GPIO Port D */
# define TIVA_IRQ_GPIOE (20) /* Vector 20: GPIO Port E */
# define TIVA_IRQ_UART0 (21) /* Vector 21: UART 0 */
# define TIVA_IRQ_UART1 (22) /* Vector 22: UART 1 */
# define TIVA_IRQ_SSI0 (23) /* Vector 23: SSI 0 */
# define TIVA_IRQ_I2C0 (24) /* Vector 24: I2C 0 */
# define TIVA_IRQ_PWMFAULT (25) /* Vector 25: PWM Fault */
# define TIVA_IRQ_PWM0 (26) /* Vector 26: PWM Generator 0 */
# define TIVA_IRQ_PWM1 (27) /* Vector 27: PWM Generator 1 */
# define TIVA_IRQ_PWM2 (28) /* Vector 28: PWM Generator 2 */
# define TIVA_IRQ_QEI0 (29) /* Vector 29: QEI0 */
# define TIVA_IRQ_ADC0 (30) /* Vector 30: ADC Sequence 0 */
# define TIVA_IRQ_ADC1 (31) /* Vector 31: ADC Sequence 1 */
# define TIVA_IRQ_ADC2 (32) /* Vector 32: ADC Sequence 2 */
# define TIVA_IRQ_ADC3 (33) /* Vector 33: ADC Sequence 3 */
# define TIVA_IRQ_WDOG (34) /* Vector 34: Watchdog Timer */
# define TIVA_IRQ_TIMER0A (35) /* Vector 35: Timer 0 A */
# define TIVA_IRQ_TIMER0B (36) /* Vector 36: Timer 0 B */
# define TIVA_IRQ_TIMER1A (37) /* Vector 37: Timer 1 A */
# define TIVA_IRQ_TIMER1B (38) /* Vector 38: Timer 1 B */
# define TIVA_IRQ_TIMER2A (39) /* Vector 39: Timer 2 A */
# define TIVA_IRQ_TIMER2B (40) /* Vector 40: Timer 2 B */
# define TIVA_IRQ_COMPARE0 (41) /* Vector 41: Analog Comparator 0 */
# define TIVA_RESERVED_42 (42) /* Vector 42: Reserved */
# define TIVA_RESERVED_43 (43) /* Vector 43: Reserved */
# define TIVA_IRQ_SYSCON (44) /* Vector 44: System Control */
# define TIVA_IRQ_FLASHCON (45) /* Vector 45: FLASH Control */
# define TIVA_IRQ_GPIOF (46) /* Vector 46: GPIO Port F */
# define TIVA_IRQ_GPIOG (47) /* Vector 47: GPIO Port G */
# define TIVA_RESERVED_48 (48) /* Vector 48: Reserved */
# define TIVA_RESERVED_49 (49) /* Vector 49: Reserved */
# define TIVA_RESERVED_50 (50) /* Vector 50: Reserved */
# define TIVA_IRQ_TIMER3A (51) /* Vector 51: Timer 3 A */
# define TIVA_IRQ_TIMER3B (52) /* Vector 52: Timer 3 B */
# define TIVA_IRQ_I2C1 (53) /* Vector 53: I2C 1 */
# define TIVA_IRQ_QEI1 (54) /* Vector 54: QEI1 */
# define TIVA_IRQ_CAN0 (54) /* Vector 55: CAN0 */
# define TIVA_RESERVED_56 (56) /* Vector 56: Reserved */
# define TIVA_RESERVED_57 (57) /* Vector 57: Reserved */
# define TIVA_IRQ_ETHCON (58) /* Vector 58: Ethernet Controller */
# define TIVA_IRQ_HIBERNATE (59) /* Vector 59: Hibernation Module */
# define TIVA_RESERVED_60 (60) /* Vector 60: Reserved */
# define TIVA_RESERVED_61 (61) /* Vector 61: Reserved */
# define TIVA_RESERVED_62 (62) /* Vector 62: Reserved */
# define TIVA_RESERVED_63 (63) /* Vector 63: Reserved */
# define TIVA_RESERVED_64 (64) /* Vector 64: Reserved */
# define TIVA_RESERVED_65 (65) /* Vector 65: Reserved */
# define TIVA_RESERVED_66 (66) /* Vector 66: Reserved */
# define TIVA_RESERVED_67 (67) /* Vector 67: Reserved */
# define TIVA_RESERVED_68 (68) /* Vector 68: Reserved */
# define TIVA_RESERVED_69 (69) /* Vector 69: Reserved */
# define TIVA_RESERVED_70 (70) /* Vector 70: Reserved */
# define NR_IRQS (71) /* (Really less because of reserved vectors) */
#else
# error "IRQ Numbers not specified for this Stellaris chip"
#endif
/************************************************************************************
* Public Types
************************************************************************************/
/************************************************************************************
* Public Data
************************************************************************************/
#ifndef __ASSEMBLY__
#ifdef __cplusplus
extern "C"
{
#endif
/************************************************************************************
* Public Functions
************************************************************************************/
#ifdef __cplusplus
}
#endif
#endif
#endif /* __ARCH_ARM_INCLUDE_TIVA_LM3S_IRQ_H */

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