From e6af32c88fb7c011a09ca858939eb503fb7933cb Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Wed, 22 Apr 2020 13:55:46 -0600 Subject: [PATCH] Run nxstyle against all files modified by PR 848 --- arch/arm/include/armv7-m/irq.h | 45 +++---- arch/arm/include/armv7-m/irq_cmnvector.h | 123 ++++++++---------- arch/arm/include/armv7-m/irq_lazyfpu.h | 39 ++---- arch/arm/include/armv7-m/nvicpri.h | 40 ++---- arch/arm/include/armv7-m/spinlock.h | 39 ++---- arch/arm/include/armv7-m/syscall.h | 39 ++---- arch/arm/src/armv7-m/exc_return.h | 2 +- arch/arm/src/armv7-m/fpb.h | 14 +-- arch/arm/src/armv7-m/mpu.h | 132 ++++++++++---------- arch/arm/src/armv7-m/nvic.h | 3 + arch/arm/src/armv7-m/svcall.h | 1 + arch/arm/src/armv7-m/up_assert.c | 1 + arch/arm/src/armv7-m/up_doirq.c | 6 +- arch/arm/src/armv7-m/up_hardfault.c | 3 +- arch/arm/src/armv7-m/up_initialstate.c | 2 +- arch/arm/src/armv7-m/up_memfault.c | 8 +- arch/arm/src/armv7-m/up_releasepending.c | 5 +- arch/arm/src/armv7-m/up_reprioritizertr.c | 5 +- arch/arm/src/armv7-m/up_schedulesigaction.c | 29 ++--- arch/arm/src/armv7-m/up_svcall.c | 81 ++++++------ arch/arm/src/armv7-m/up_systemreset.c | 2 +- 21 files changed, 275 insertions(+), 344 deletions(-) diff --git a/arch/arm/include/armv7-m/irq.h b/arch/arm/include/armv7-m/irq.h index 8d4c39b3b1e..9520e6d5e1c 100644 --- a/arch/arm/include/armv7-m/irq.h +++ b/arch/arm/include/armv7-m/irq.h @@ -1,35 +1,20 @@ /**************************************************************************** * arch/arm/include/armv7-m/irq.h * - * Copyright (C) 2009, 2011-2012, 2014 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ @@ -64,8 +49,12 @@ /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ + /* Configuration ************************************************************/ -/* If this is a kernel build, how many nested system calls should we support? */ + +/* If this is a kernel build, how many nested system calls should we + * support? + */ #ifndef CONFIG_SYS_NNEST # define CONFIG_SYS_NNEST 2 diff --git a/arch/arm/include/armv7-m/irq_cmnvector.h b/arch/arm/include/armv7-m/irq_cmnvector.h index 47438051247..5117d8b759d 100644 --- a/arch/arm/include/armv7-m/irq_cmnvector.h +++ b/arch/arm/include/armv7-m/irq_cmnvector.h @@ -1,35 +1,20 @@ /**************************************************************************** * arch/arm/include/armv7-m/irq_cmnvector.h * - * Copyright (C) 2012 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ @@ -74,22 +59,22 @@ * that may save and overwrite them. */ -# define REG_S16 (SW_INT_REGS+0) /* S16 */ -# define REG_S17 (SW_INT_REGS+1) /* S17 */ -# define REG_S18 (SW_INT_REGS+2) /* S18 */ -# define REG_S19 (SW_INT_REGS+3) /* S19 */ -# define REG_S20 (SW_INT_REGS+4) /* S20 */ -# define REG_S21 (SW_INT_REGS+5) /* S21 */ -# define REG_S22 (SW_INT_REGS+6) /* S22 */ -# define REG_S23 (SW_INT_REGS+7) /* S23 */ -# define REG_S24 (SW_INT_REGS+8) /* S24 */ -# define REG_S25 (SW_INT_REGS+9) /* S25 */ -# define REG_S26 (SW_INT_REGS+10) /* S26 */ -# define REG_S27 (SW_INT_REGS+11) /* S27 */ -# define REG_S28 (SW_INT_REGS+12) /* S28 */ -# define REG_S29 (SW_INT_REGS+13) /* S29 */ -# define REG_S30 (SW_INT_REGS+14) /* S30 */ -# define REG_S31 (SW_INT_REGS+15) /* S31 */ +# define REG_S16 (SW_INT_REGS + 0) /* S16 */ +# define REG_S17 (SW_INT_REGS + 1) /* S17 */ +# define REG_S18 (SW_INT_REGS + 2) /* S18 */ +# define REG_S19 (SW_INT_REGS + 3) /* S19 */ +# define REG_S20 (SW_INT_REGS + 4) /* S20 */ +# define REG_S21 (SW_INT_REGS + 5) /* S21 */ +# define REG_S22 (SW_INT_REGS + 6) /* S22 */ +# define REG_S23 (SW_INT_REGS + 7) /* S23 */ +# define REG_S24 (SW_INT_REGS + 8) /* S24 */ +# define REG_S25 (SW_INT_REGS + 9) /* S25 */ +# define REG_S26 (SW_INT_REGS + 10) /* S26 */ +# define REG_S27 (SW_INT_REGS + 11) /* S27 */ +# define REG_S28 (SW_INT_REGS + 12) /* S28 */ +# define REG_S29 (SW_INT_REGS + 13) /* S29 */ +# define REG_S30 (SW_INT_REGS + 14) /* S30 */ +# define REG_S31 (SW_INT_REGS + 15) /* S31 */ # define SW_FPU_REGS (16) #else # define SW_FPU_REGS (0) @@ -104,14 +89,14 @@ * registers on the stack in this (address) order: */ -#define REG_R0 (SW_XCPT_REGS+0) /* R0 */ -#define REG_R1 (SW_XCPT_REGS+1) /* R1 */ -#define REG_R2 (SW_XCPT_REGS+2) /* R2 */ -#define REG_R3 (SW_XCPT_REGS+3) /* R3 */ -#define REG_R12 (SW_XCPT_REGS+4) /* R12 */ -#define REG_R14 (SW_XCPT_REGS+5) /* R14 = LR */ -#define REG_R15 (SW_XCPT_REGS+6) /* R15 = PC */ -#define REG_XPSR (SW_XCPT_REGS+7) /* xPSR */ +#define REG_R0 (SW_XCPT_REGS + 0) /* R0 */ +#define REG_R1 (SW_XCPT_REGS + 1) /* R1 */ +#define REG_R2 (SW_XCPT_REGS + 2) /* R2 */ +#define REG_R3 (SW_XCPT_REGS + 3) /* R3 */ +#define REG_R12 (SW_XCPT_REGS + 4) /* R12 */ +#define REG_R14 (SW_XCPT_REGS + 5) /* R14 = LR */ +#define REG_R15 (SW_XCPT_REGS + 6) /* R15 = PC */ +#define REG_XPSR (SW_XCPT_REGS + 7) /* xPSR */ #define HW_INT_REGS (8) #ifdef CONFIG_ARCH_FPU @@ -119,24 +104,24 @@ /* If the FPU is enabled, the hardware also saves the volatile FP registers. */ -# define REG_S0 (SW_XCPT_REGS+8) /* S0 */ -# define REG_S1 (SW_XCPT_REGS+9) /* S1 */ -# define REG_S2 (SW_XCPT_REGS+10) /* S2 */ -# define REG_S3 (SW_XCPT_REGS+11) /* S3 */ -# define REG_S4 (SW_XCPT_REGS+12) /* S4 */ -# define REG_S5 (SW_XCPT_REGS+13) /* S5 */ -# define REG_S6 (SW_XCPT_REGS+14) /* S6 */ -# define REG_S7 (SW_XCPT_REGS+15) /* S7 */ -# define REG_S8 (SW_XCPT_REGS+16) /* S8 */ -# define REG_S9 (SW_XCPT_REGS+17) /* S9 */ -# define REG_S10 (SW_XCPT_REGS+18) /* S10 */ -# define REG_S11 (SW_XCPT_REGS+19) /* S11 */ -# define REG_S12 (SW_XCPT_REGS+20) /* S12 */ -# define REG_S13 (SW_XCPT_REGS+21) /* S13 */ -# define REG_S14 (SW_XCPT_REGS+22) /* S14 */ -# define REG_S15 (SW_XCPT_REGS+23) /* S15 */ -# define REG_FPSCR (SW_XCPT_REGS+24) /* FPSCR */ -# define REG_FPReserved (SW_XCPT_REGS+25) /* Reserved */ +# define REG_S0 (SW_XCPT_REGS + 8) /* S0 */ +# define REG_S1 (SW_XCPT_REGS + 9) /* S1 */ +# define REG_S2 (SW_XCPT_REGS + 10) /* S2 */ +# define REG_S3 (SW_XCPT_REGS + 11) /* S3 */ +# define REG_S4 (SW_XCPT_REGS + 12) /* S4 */ +# define REG_S5 (SW_XCPT_REGS + 13) /* S5 */ +# define REG_S6 (SW_XCPT_REGS + 14) /* S6 */ +# define REG_S7 (SW_XCPT_REGS + 15) /* S7 */ +# define REG_S8 (SW_XCPT_REGS + 16) /* S8 */ +# define REG_S9 (SW_XCPT_REGS + 17) /* S9 */ +# define REG_S10 (SW_XCPT_REGS + 18) /* S10 */ +# define REG_S11 (SW_XCPT_REGS + 19) /* S11 */ +# define REG_S12 (SW_XCPT_REGS + 20) /* S12 */ +# define REG_S13 (SW_XCPT_REGS + 21) /* S13 */ +# define REG_S14 (SW_XCPT_REGS + 22) /* S14 */ +# define REG_S15 (SW_XCPT_REGS + 23) /* S15 */ +# define REG_FPSCR (SW_XCPT_REGS + 24) /* FPSCR */ +# define REG_FP_RESERVED (SW_XCPT_REGS + 25) /* Reserved */ # define HW_FPU_REGS (18) #else # define HW_FPU_REGS (0) diff --git a/arch/arm/include/armv7-m/irq_lazyfpu.h b/arch/arm/include/armv7-m/irq_lazyfpu.h index a50c68aa919..0837e7ca8ee 100644 --- a/arch/arm/include/armv7-m/irq_lazyfpu.h +++ b/arch/arm/include/armv7-m/irq_lazyfpu.h @@ -1,35 +1,20 @@ /**************************************************************************** * arch/arm/include/armv7-m/irq_lazyfpu.h * - * Copyright (C) 2009, 2011-2012 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/include/armv7-m/nvicpri.h b/arch/arm/include/armv7-m/nvicpri.h index c1fe4a8e26d..59c34fae355 100644 --- a/arch/arm/include/armv7-m/nvicpri.h +++ b/arch/arm/include/armv7-m/nvicpri.h @@ -1,36 +1,20 @@ /************************************************************************************ * arch/arm/include/armv7-m/nvicpri.h * - * Copyright (C) 2009, 2011-2014, 2017-2018 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * Dave Marples + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ************************************************************************************/ diff --git a/arch/arm/include/armv7-m/spinlock.h b/arch/arm/include/armv7-m/spinlock.h index 79a06b4173f..e48cca89b52 100644 --- a/arch/arm/include/armv7-m/spinlock.h +++ b/arch/arm/include/armv7-m/spinlock.h @@ -1,35 +1,20 @@ /**************************************************************************** * arch/arm/include/armv7-a/spinlock.h * - * Copyright (C) 2016 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/include/armv7-m/syscall.h b/arch/arm/include/armv7-m/syscall.h index 26b5d290a1e..6e9f57d2236 100644 --- a/arch/arm/include/armv7-m/syscall.h +++ b/arch/arm/include/armv7-m/syscall.h @@ -1,35 +1,20 @@ /**************************************************************************** * arch/arm/include/armv7-m/syscall.h * - * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: + * http://www.apache.org/licenses/LICENSE-2.0 * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ diff --git a/arch/arm/src/armv7-m/exc_return.h b/arch/arm/src/armv7-m/exc_return.h index 1aea9549fd2..2ba5db5dd01 100644 --- a/arch/arm/src/armv7-m/exc_return.h +++ b/arch/arm/src/armv7-m/exc_return.h @@ -97,7 +97,7 @@ EXC_RETURN_THREAD_MODE | EXC_RETURN_PROCESS_STACK) #endif -/************************Th************************************************************ +/************************************************************************************ * Inline Functions ************************************************************************************/ diff --git a/arch/arm/src/armv7-m/fpb.h b/arch/arm/src/armv7-m/fpb.h index d6b7978ed51..99358e6dc3d 100644 --- a/arch/arm/src/armv7-m/fpb.h +++ b/arch/arm/src/armv7-m/fpb.h @@ -21,17 +21,17 @@ #ifndef __ARCH_ARM_SRC_ARMV&-M_FPB_H #define __ARCH_ARM_SRC_ARMV&-M_FPB_H -/****************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ******************************************************************************/ + ****************************************************************************/ -/* Flash Patch and Breakpoint Unit FPB ***************************************/ +/* Flash Patch and Breakpoint Unit FPB **************************************/ -/* FPB Register Base Address *************************************************/ +/* FPB Register Base Address ************************************************/ #define FPB_BASE 0xe0002000 -/* FPB Register Offsets *******************************************************/ +/* FPB Register Offsets *****************************************************/ #define FPB_CTRL_OFFSET 0x0000 /* Control */ #define FPB_REMAP_OFFSET 0x0004 /* Remap */ @@ -44,7 +44,7 @@ #define FPB_COMP6_OFFSET 0x0020 /* Comparator 6 */ #define FPB_COMP7_OFFSET 0x0024 /* Comparator 7 */ -/* FPB Register Addresses *****************************************************/ +/* FPB Register Addresses ***************************************************/ #define FPB_CTRL (FPB_BASE + FPB_CTRL_OFFSET) #define FPB_REMAP (FPB_BASE + FPB_REMAP_OFFSET) @@ -57,7 +57,7 @@ #define FPB_COMP6 (FPB_BASE + FPB_COMP6_OFFSET) #define FPB_COMP7 (FPB_BASE + FPB_COMP7_OFFSET -/* FPB Register Bitfield Definitions ******************************************/ +/* FPB Register Bitfield Definitions ****************************************/ /* FPB_CTRL */ diff --git a/arch/arm/src/armv7-m/mpu.h b/arch/arm/src/armv7-m/mpu.h index 129f81a72f7..91c9a4850b1 100644 --- a/arch/arm/src/armv7-m/mpu.h +++ b/arch/arm/src/armv7-m/mpu.h @@ -1,4 +1,4 @@ -/***************************************************************************** +/********************************************************************************************* * arch/arm/src/armv7-m/mpu.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,14 +16,14 @@ * License for the specific language governing permissions and limitations * under the License. * - *****************************************************************************/ + *********************************************************************************************/ #ifndef __ARCH_ARM_SRC_ARMV7M_MPU_H #define __ARCH_ARM_SRC_ARMV7M_MPU_H -/***************************************************************************** +/********************************************************************************************* * Included Files - *****************************************************************************/ + *********************************************************************************************/ #include @@ -37,9 +37,9 @@ # include "up_arch.h" #endif -/***************************************************************************** +/********************************************************************************************* * Pre-processor Definitions - *****************************************************************************/ + *********************************************************************************************/ /* MPU Register Addresses */ @@ -86,18 +86,18 @@ /* MPU Region Base Address Register Bit Definitions */ -#define MPU_RBAR_REGION_SHIFT (0) /* Bits 0-3: MPU region */ +#define MPU_RBAR_REGION_SHIFT (0) /* Bits 0-3: MPU region */ #define MPU_RBAR_REGION_MASK (15 << MPU_RBAR_REGION_SHIFT) -#define MPU_RBAR_VALID (1 << 4) /* Bit 4: MPU Region Number valid */ -#define MPU_RBAR_ADDR_MASK 0xffffffe0 /* Bits N-31: Region base addrese */ +#define MPU_RBAR_VALID (1 << 4) /* Bit 4: MPU Region Number valid */ +#define MPU_RBAR_ADDR_MASK 0xffffffe0 /* Bits N-31: Region base addrese */ /* MPU Region Attributes and Size Register Bit Definitions */ -#define MPU_RASR_ENABLE (1 << 0) /* Bit 0: Region enable */ -#define MPU_RASR_SIZE_SHIFT (1) /* Bits 1-5: Size of the MPU protection region */ +#define MPU_RASR_ENABLE (1 << 0) /* Bit 0: Region enable */ +#define MPU_RASR_SIZE_SHIFT (1) /* Bits 1-5: Size of the MPU protection region */ #define MPU_RASR_SIZE_MASK (31 << MPU_RASR_SIZE_SHIFT) # define MPU_RASR_SIZE_LOG2(n) ((n-1) << MPU_RASR_SIZE_SHIFT) -#define MPU_RASR_SRD_SHIFT (8) /* Bits 8-15: Subregion disable */ +#define MPU_RASR_SRD_SHIFT (8) /* Bits 8-15: Subregion disable */ #define MPU_RASR_SRD_MASK (0xff << MPU_RASR_SRD_SHIFT) # define MPU_RASR_SRD_0 (0x01 << MPU_RASR_SRD_SHIFT) # define MPU_RASR_SRD_1 (0x02 << MPU_RASR_SRD_SHIFT) @@ -107,36 +107,36 @@ # define MPU_RASR_SRD_5 (0x20 << MPU_RASR_SRD_SHIFT) # define MPU_RASR_SRD_6 (0x40 << MPU_RASR_SRD_SHIFT) # define MPU_RASR_SRD_7 (0x80 << MPU_RASR_SRD_SHIFT) -#define MPU_RASR_ATTR_SHIFT (16) /* Bits 16-31: MPU Region Attribute field */ +#define MPU_RASR_ATTR_SHIFT (16) /* Bits 16-31: MPU Region Attribute field */ #define MPU_RASR_ATTR_MASK (0xffff << MPU_RASR_ATTR_SHIFT) -# define MPU_RASR_B (1 << 16) /* Bit 16: Bufferable */ -# define MPU_RASR_C (1 << 17) /* Bit 17: Cacheable */ -# define MPU_RASR_S (1 << 18) /* Bit 18: Shareable */ -# define MPU_RASR_TEX_SHIFT (19) /* Bits 19-21: TEX Address Permission */ +# define MPU_RASR_B (1 << 16) /* Bit 16: Bufferable */ +# define MPU_RASR_C (1 << 17) /* Bit 17: Cacheable */ +# define MPU_RASR_S (1 << 18) /* Bit 18: Shareable */ +# define MPU_RASR_TEX_SHIFT (19) /* Bits 19-21: TEX Address Permission */ # define MPU_RASR_TEX_MASK (7 << MPU_RASR_TEX_SHIFT) # define MPU_RASR_TEX_SO (0 << MPU_RASR_TEX_SHIFT) /* Strongly Ordered */ # define MPU_RASR_TEX_NOR (1 << MPU_RASR_TEX_SHIFT) /* Normal */ # define MPU_RASR_TEX_DEV (2 << MPU_RASR_TEX_SHIFT) /* Device */ -# define MPU_RASR_TEX_BB(bb) ((4|(bb)) << MPU_RASR_TEX_SHIFT) /* Normal BB AA */ -# define MPU_RASR_CP_NC (0) /* Non-cacheable */ -# define MPU_RASR_CP_WBRA (1) /* Write back, write and Read- Allocate */ -# define MPU_RASR_CP_WT (2) /* Write through, no Write-Allocate */ -# define MPU_RASR_CP_WB (4) /* Write back, no Write-Allocate */ -# define MPU_RASR_AP_SHIFT (24) /* Bits 24-26: Access permission */ +# define MPU_RASR_TEX_BB(bb) ((4|(bb)) << MPU_RASR_TEX_SHIFT) +# define MPU_RASR_CP_NC (0) /* Non-cacheable */ +# define MPU_RASR_CP_WBRA (1) /* Write back, write and Read- Allocate */ +# define MPU_RASR_CP_WT (2) /* Write through, no Write-Allocate */ +# define MPU_RASR_CP_WB (4) /* Write back, no Write-Allocate */ +# define MPU_RASR_AP_SHIFT (24) /* Bits 24-26: Access permission */ # define MPU_RASR_AP_MASK (7 << MPU_RASR_AP_SHIFT) -# define MPU_RASR_AP_NONO (0 << MPU_RASR_AP_SHIFT) /* P:None U:None */ -# define MPU_RASR_AP_RWNO (1 << MPU_RASR_AP_SHIFT) /* P:RW U:None */ -# define MPU_RASR_AP_RWRO (2 << MPU_RASR_AP_SHIFT) /* P:RW U:RO */ -# define MPU_RASR_AP_RWRW (3 << MPU_RASR_AP_SHIFT) /* P:RW U:RW */ -# define MPU_RASR_AP_RONO (5 << MPU_RASR_AP_SHIFT) /* P:RO U:None */ -# define MPU_RASR_AP_RORO (6 << MPU_RASR_AP_SHIFT) /* P:RO U:RO */ -# define MPU_RASR_XN (1 << 28) /* Bit 28: Instruction access disable */ +# define MPU_RASR_AP_NONO (0 << MPU_RASR_AP_SHIFT) /* P:None U:None */ +# define MPU_RASR_AP_RWNO (1 << MPU_RASR_AP_SHIFT) /* P:RW U:None */ +# define MPU_RASR_AP_RWRO (2 << MPU_RASR_AP_SHIFT) /* P:RW U:RO */ +# define MPU_RASR_AP_RWRW (3 << MPU_RASR_AP_SHIFT) /* P:RW U:RW */ +# define MPU_RASR_AP_RONO (5 << MPU_RASR_AP_SHIFT) /* P:RO U:None */ +# define MPU_RASR_AP_RORO (6 << MPU_RASR_AP_SHIFT) /* P:RO U:RO */ +# define MPU_RASR_XN (1 << 28) /* Bit 28: Instruction access disable */ #ifdef CONFIG_ARM_MPU -/***************************************************************************** +/********************************************************************************************* * Public Function Prototypes - *****************************************************************************/ + *********************************************************************************************/ #ifndef __ASSEMBLY__ #undef EXTERN @@ -148,17 +148,17 @@ extern "C" #define EXTERN extern #endif -/***************************************************************************** +/********************************************************************************************* * Name: mpu_allocregion * * Description: * Allocate the next region * - *****************************************************************************/ + *********************************************************************************************/ unsigned int mpu_allocregion(void); -/***************************************************************************** +/********************************************************************************************* * Name: mpu_log2regionceil * * Description: @@ -167,11 +167,11 @@ unsigned int mpu_allocregion(void); * * size <= (1 << l2size) * - *****************************************************************************/ + *********************************************************************************************/ uint8_t mpu_log2regionceil(size_t size); -/***************************************************************************** +/********************************************************************************************* * Name: mpu_log2regionfloor * * Description: @@ -180,11 +180,11 @@ uint8_t mpu_log2regionceil(size_t size); * * size >= (1 << l2size) * - *****************************************************************************/ + *********************************************************************************************/ uint8_t mpu_log2regionfloor(size_t size); -/***************************************************************************** +/********************************************************************************************* * Name: mpu_subregion * * Description: @@ -196,42 +196,42 @@ uint8_t mpu_log2regionfloor(size_t size); * l2size has the same properties as the return value from * mpu_log2regionceil() * - *****************************************************************************/ + *********************************************************************************************/ uint32_t mpu_subregion(uintptr_t base, size_t size, uint8_t l2size); -/***************************************************************************** +/********************************************************************************************* * Name: mpu_control * * Description: * Configure and enable (or disable) the MPU * - *****************************************************************************/ + *********************************************************************************************/ void mpu_control(bool enable, bool hfnmiena, bool privdefena); -/***************************************************************************** +/********************************************************************************************* * Name: mpu_configure_region * * Description: * Configure a region for privileged, strongly ordered memory * - *****************************************************************************/ + *********************************************************************************************/ void mpu_configure_region(uintptr_t base, size_t size, uint32_t flags); -/***************************************************************************** +/********************************************************************************************* * Inline Functions - *****************************************************************************/ + *********************************************************************************************/ -/***************************************************************************** +/********************************************************************************************* * Name: mpu_showtype * * Description: * Show the characteristics of the MPU * - *****************************************************************************/ + *********************************************************************************************/ #ifdef CONFIG_DEBUG_SCHED_INFO # define mpu_showtype() \ @@ -247,13 +247,13 @@ void mpu_configure_region(uintptr_t base, size_t size, # define mpu_showtype() do { } while (0) #endif -/***************************************************************************** +/********************************************************************************************* * Name: mpu_priv_stronglyordered * * Description: * Configure a region for privileged, strongly ordered memory * - *****************************************************************************/ + *********************************************************************************************/ #define mpu_priv_stronglyordered(base, size) \ do \ @@ -268,13 +268,13 @@ void mpu_configure_region(uintptr_t base, size_t size, /* Instruction access */); \ } while (0) -/***************************************************************************** +/********************************************************************************************* * Name: mpu_user_flash * * Description: * Configure a region for user program flash * - *****************************************************************************/ + *********************************************************************************************/ #define mpu_user_flash(base, size) \ do \ @@ -289,13 +289,13 @@ void mpu_configure_region(uintptr_t base, size_t size, /* Instruction access */); \ } while (0) -/***************************************************************************** +/********************************************************************************************* * Name: mpu_priv_flash * * Description: * Configure a region for privileged program flash * - *****************************************************************************/ + *********************************************************************************************/ #define mpu_priv_flash(base, size) \ do \ @@ -310,13 +310,13 @@ void mpu_configure_region(uintptr_t base, size_t size, /* Instruction access */); \ } while (0) -/***************************************************************************** +/********************************************************************************************* * Name: mpu_user_intsram * * Description: * Configure a region as user internal SRAM * - *****************************************************************************/ + *********************************************************************************************/ #define mpu_user_intsram(base, size) \ do \ @@ -331,13 +331,13 @@ void mpu_configure_region(uintptr_t base, size_t size, /* Instruction access */); \ } while (0) -/***************************************************************************** +/********************************************************************************************* * Name: mpu_priv_intsram * * Description: * Configure a region as privileged internal SRAM * - *****************************************************************************/ + *********************************************************************************************/ #define mpu_priv_intsram(base, size) \ do \ @@ -352,13 +352,13 @@ void mpu_configure_region(uintptr_t base, size_t size, /* Instruction access */); \ } while (0) -/***************************************************************************** +/********************************************************************************************* * Name: mpu_user_extsram * * Description: * Configure a region as user external SRAM * - *****************************************************************************/ + *********************************************************************************************/ #define mpu_user_extsram(base, size) \ do \ @@ -373,13 +373,13 @@ void mpu_configure_region(uintptr_t base, size_t size, /* Instruction access */); \ } while (0) -/***************************************************************************** +/********************************************************************************************* * Name: mpu_priv_extsram * * Description: * Configure a region as privileged external SRAM * - *****************************************************************************/ + *********************************************************************************************/ #define mpu_priv_extsram(base, size) \ do \ @@ -394,13 +394,13 @@ void mpu_configure_region(uintptr_t base, size_t size, /* Instruction access */); \ } while (0) -/***************************************************************************** +/********************************************************************************************* * Name: mpu_peripheral * * Description: * Configure a region as privileged peripheral address space * - *****************************************************************************/ + *********************************************************************************************/ #define mpu_peripheral(base, size) \ do \ @@ -415,13 +415,13 @@ void mpu_configure_region(uintptr_t base, size_t size, MPU_RASR_XN /* No Instruction access */); \ } while (0) -/***************************************************************************** +/********************************************************************************************* * Name: mpu_user_peripheral * * Description: * Configure a region as user peripheral address space * - *****************************************************************************/ + *********************************************************************************************/ #define mpu_user_peripheral(base, size) \ do \ diff --git a/arch/arm/src/armv7-m/nvic.h b/arch/arm/src/armv7-m/nvic.h index fbf4fec10f9..1886be1486a 100644 --- a/arch/arm/src/armv7-m/nvic.h +++ b/arch/arm/src/armv7-m/nvic.h @@ -34,6 +34,7 @@ /* Exception/interrupt vector numbers *******************************************************/ /* Vector 0: Reset stack pointer value */ + /* Vector 1: Reset */ #define NVIC_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */ #define NVIC_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */ @@ -489,6 +490,7 @@ #define NVIC_INTCTRL_VECTACTIVE_MASK (0x1ff << NVIC_INTCTRL_VECTACTIVE_SHIFT) /* System control register (SYSCON) */ + /* Bit 0: Reserved */ #define NVIC_SYSCON_SLEEPONEXIT (1 << 1) /* Bit 1: Sleep-on-exit (returning from Handler to Thread mode) */ #define NVIC_SYSCON_SLEEPDEEP (1 << 2) /* Bit 2: Use deep sleep in low power mode */ @@ -641,6 +643,7 @@ #define NVIC_DEMCR_TRCENA (1 << 24) /* Bit 24: Enable trace and debug blocks */ /* Instruction Tightly-Coupled Memory Control Register (ITCMCR) */ + /* Data Tightly-Coupled Memory Control Registers (DTCMCR */ #define NVIC_TCMCR_EN (1 << 0) /* Bit 9: TCM enable */ diff --git a/arch/arm/src/armv7-m/svcall.h b/arch/arm/src/armv7-m/svcall.h index bf6f8c1e772..536573b8932 100644 --- a/arch/arm/src/armv7-m/svcall.h +++ b/arch/arm/src/armv7-m/svcall.h @@ -36,6 +36,7 @@ ************************************************************************************/ /* Configuration ********************************************************************/ + /* This logic uses three system calls {0,1,2} for context switching and one for the * syscall return. So a minimum of four syscall values must be reserved. If * CONFIG_BUILD_PROTECTED is defined, then four more syscall values must be reserved. diff --git a/arch/arm/src/armv7-m/up_assert.c b/arch/arm/src/armv7-m/up_assert.c index d0eaf6622d0..d9b04cc5fe6 100644 --- a/arch/arm/src/armv7-m/up_assert.c +++ b/arch/arm/src/armv7-m/up_assert.c @@ -47,6 +47,7 @@ /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ + /* USB trace dumping */ #ifndef CONFIG_USBDEV_TRACE diff --git a/arch/arm/src/armv7-m/up_doirq.c b/arch/arm/src/armv7-m/up_doirq.c index 2606bd633e1..c40e16c4676 100644 --- a/arch/arm/src/armv7-m/up_doirq.c +++ b/arch/arm/src/armv7-m/up_doirq.c @@ -47,9 +47,9 @@ uint32_t *up_doirq(int irq, uint32_t *regs) #else uint32_t *savestate; - /* Nested interrupts are not supported in this implementation. If you want - * to implement nested interrupts, you would have to (1) change the way that - * CURRENT_REGS is handled and (2) the design associated with + /* Nested interrupts are not supported in this implementation. If you + * want to implement nested interrupts, you would have to (1) change the + * way that CURRENT_REGS is handled and (2) the design associated with * CONFIG_ARCH_INTERRUPTSTACK. The savestate variable will not work for * that purpose as implemented here because only the outermost nested * interrupt can result in a context switch. diff --git a/arch/arm/src/armv7-m/up_hardfault.c b/arch/arm/src/armv7-m/up_hardfault.c index 7ce664e70dc..59b6bc343f8 100644 --- a/arch/arm/src/armv7-m/up_hardfault.c +++ b/arch/arm/src/armv7-m/up_hardfault.c @@ -123,7 +123,8 @@ int up_hardfault(int irq, FAR void *context, FAR void *arg) hfalert(" IRQ: %d regs: %p\n", irq, context); hfalert(" BASEPRI: %08x PRIMASK: %08x IPSR: %08x CONTROL: %08x\n", getbasepri(), getprimask(), getipsr(), getcontrol()); - hfalert(" CFAULTS: %08x HFAULTS: %08x DFAULTS: %08x BFAULTADDR: %08x AFAULTS: %08x\n", + hfalert(" CFAULTS: %08x HFAULTS: %08x DFAULTS: %08x BFAULTADDR: %08x " + "AFAULTS: %08x\n", getreg32(NVIC_CFAULTS), getreg32(NVIC_HFAULTS), getreg32(NVIC_DFAULTS), getreg32(NVIC_BFAULT_ADDR), getreg32(NVIC_AFAULTS)); diff --git a/arch/arm/src/armv7-m/up_initialstate.c b/arch/arm/src/armv7-m/up_initialstate.c index 970230419a4..8b5263b8fc9 100644 --- a/arch/arm/src/armv7-m/up_initialstate.c +++ b/arch/arm/src/armv7-m/up_initialstate.c @@ -120,7 +120,7 @@ void up_initial_state(struct tcb_s *tcb) #if !defined(CONFIG_ARMV7M_LAZYFPU) && defined(CONFIG_ARCH_FPU) xcp->regs[REG_FPSCR] = 0; /* REVISIT: Initial FPSCR should be configurable */ - xcp->regs[REG_FPReserved] = 0; + xcp->regs[REG_FP_RESERVED] = 0; #endif /* !CONFIG_ARMV7M_LAZYFPU && CONFIG_ARCH_FPU */ diff --git a/arch/arm/src/armv7-m/up_memfault.c b/arch/arm/src/armv7-m/up_memfault.c index 2193fd48908..9c0a536c441 100644 --- a/arch/arm/src/armv7-m/up_memfault.c +++ b/arch/arm/src/armv7-m/up_memfault.c @@ -53,10 +53,10 @@ * Name: up_memfault * * Description: - * This is Memory Management Fault exception handler. Normally we get here - * when the Cortex M3 MPU is enabled and an MPU fault is detected. However, - * I understand that there are other error conditions that can also generate - * memory management faults. + * This is Memory Management Fault exception handler. Normally we get + * here when the Cortex M3 MPU is enabled and an MPU fault is detected. + * However, I understand that there are other error conditions that can + * also generate memory management faults. * ****************************************************************************/ diff --git a/arch/arm/src/armv7-m/up_releasepending.c b/arch/arm/src/armv7-m/up_releasepending.c index 6ccefee6e04..11e7fbec7d9 100644 --- a/arch/arm/src/armv7-m/up_releasepending.c +++ b/arch/arm/src/armv7-m/up_releasepending.c @@ -55,7 +55,10 @@ void up_release_pending(void) /* Merge the g_pendingtasks list into the ready-to-run task list */ - /* sched_lock(); */ +#if 0 + sched_lock(); +#endif + if (sched_mergepending()) { /* The currently active task has changed! We will need to switch diff --git a/arch/arm/src/armv7-m/up_reprioritizertr.c b/arch/arm/src/armv7-m/up_reprioritizertr.c index 271ed82a0d2..dda38640fec 100644 --- a/arch/arm/src/armv7-m/up_reprioritizertr.c +++ b/arch/arm/src/armv7-m/up_reprioritizertr.c @@ -164,8 +164,9 @@ void up_reprioritize_rtr(struct tcb_s *tcb, uint8_t priority) /* up_switchcontext forces a context switch to the task at the * head of the ready-to-run list. It does not 'return' in the - * normal sense. When it does return, it is because the blocked - * task is again ready to run and has execution priority. + * normal sense. When it does return, it is because the + * blocked task is again ready to run and has execution + * priority. */ } } diff --git a/arch/arm/src/armv7-m/up_schedulesigaction.c b/arch/arm/src/armv7-m/up_schedulesigaction.c index ed46524931b..d19adda3fc1 100644 --- a/arch/arm/src/armv7-m/up_schedulesigaction.c +++ b/arch/arm/src/armv7-m/up_schedulesigaction.c @@ -277,8 +277,9 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver) /* Now tcb on the other CPU can be accessed safely */ - /* Copy tcb->xcp.regs to tcp.xcp.saved. These will be restored - * by the signal trampoline after the signal has been delivered. + /* Copy tcb->xcp.regs to tcp.xcp.saved. These will be + * restored by the signal trampoline after the signal has + * been delivered. */ tcb->xcp.sigdeliver = (FAR void *)sigdeliver; @@ -313,10 +314,10 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver) { /* tcb is running on the same CPU */ - /* Save the return PC, CPSR and either the BASEPRI or PRIMASK - * registers (and perhaps also the LR). These will be - * restored by the signal trampoline after the signal has been - * delivered. + /* Save the return PC, CPSR and either the BASEPRI or + * PRIMASK registers (and perhaps also the LR). These + * will be restored by the signal trampoline after the + * signal has been delivered. */ tcb->xcp.sigdeliver = (FAR void *)sigdeliver; @@ -347,15 +348,15 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver) CURRENT_REGS[REG_LR] = EXC_RETURN_PRIVTHR; #endif - /* And make sure that the saved context in the TCB is the same - * as the interrupt return context. + /* And make sure that the saved context in the TCB is the + * same as the interrupt return context. */ up_savestate(tcb->xcp.regs); } - /* Increment the IRQ lock count so that when the task is restarted, - * it will hold the IRQ spinlock. + /* Increment the IRQ lock count so that when the task is + * restarted, it will hold the IRQ spinlock. */ DEBUGASSERT(tcb->irqcount < INT16_MAX); @@ -363,15 +364,15 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver) /* In an SMP configuration, the interrupt disable logic also * involves spinlocks that are configured per the TCB irqcount - * field. This is logically equivalent to enter_critical_section(). - * The matching call to leave_critical_section() will be - * performed in up_sigdeliver(). + * field. This is logically equivalent to + * enter_critical_section(). The matching call to + * leave_critical_section() will be performed in + * up_sigdeliver(). */ spin_setbit(&g_cpu_irqset, cpu, &g_cpu_irqsetlock, &g_cpu_irqlock); - /* RESUME the other CPU if it was PAUSED */ if (cpu != me) diff --git a/arch/arm/src/armv7-m/up_svcall.c b/arch/arm/src/armv7-m/up_svcall.c index ec87442aad8..5dcc57754c0 100644 --- a/arch/arm/src/armv7-m/up_svcall.c +++ b/arch/arm/src/armv7-m/up_svcall.c @@ -81,33 +81,34 @@ static void dispatch_syscall(void) naked_function; static void dispatch_syscall(void) { __asm__ __volatile__ - ( - /* Create a stack frame to hold 3 parameters + LR and SP adjustment value. - * Also, Ensure 8 bytes alignment. We use IP as a scratch. - * - * NOTE: new_SP = (orig_SP - 20) & ~7 - * = orig_SP - 20 - ((orig_SP - 20) & ~7) - */ - " mov ip, sp\n" /* Calculate (orig_SP - new_SP) */ - " sub ip, ip, #20\n" - " and ip, ip, #7\n" - " add ip, ip, #20\n" - " sub sp, sp, ip\n" - " str r4, [sp, #0]\n" /* Move parameter 4 (if any) into position */ - " str r5, [sp, #4]\n" /* Move parameter 5 (if any) into position */ - " str r6, [sp, #8]\n" /* Move parameter 6 (if any) into position */ - " str lr, [sp, #12]\n" /* Save lr in the stack frame */ - " str ip, [sp, #16]\n" /* Save (orig_SP - new_SP) value */ - " ldr ip, =g_stublookup\n" /* R12=The base of the stub lookup table */ - " ldr ip, [ip, r0, lsl #2]\n" /* R12=The address of the stub for this syscall */ - " blx ip\n" /* Call the stub (modifies lr) */ - " ldr lr, [sp, #12]\n" /* Restore lr */ - " ldr r2, [sp, #16]\n" /* Restore (orig_SP - new_SP) value */ - " add sp, sp, r2\n" /* Restore SP */ - " mov r2, r0\n" /* R2=Save return value in R2 */ - " mov r0, #3\n" /* R0=SYS_syscall_return */ - " svc 0" /* Return from the syscall */ - ); + ( + /* Create a stack frame to hold 3 parameters + LR and SP adjustment + * value. Also, Ensure 8 bytes alignment. We use IP as a scratch. + * + * NOTE: new_SP = (orig_SP - 20) & ~7 + * = orig_SP - 20 - ((orig_SP - 20) & ~7) + */ + + " mov ip, sp\n" /* Calculate (orig_SP - new_SP) */ + " sub ip, ip, #20\n" + " and ip, ip, #7\n" + " add ip, ip, #20\n" + " sub sp, sp, ip\n" + " str r4, [sp, #0]\n" /* Move parameter 4 (if any) into position */ + " str r5, [sp, #4]\n" /* Move parameter 5 (if any) into position */ + " str r6, [sp, #8]\n" /* Move parameter 6 (if any) into position */ + " str lr, [sp, #12]\n" /* Save lr in the stack frame */ + " str ip, [sp, #16]\n" /* Save (orig_SP - new_SP) value */ + " ldr ip, =g_stublookup\n" /* R12=The base of the stub lookup table */ + " ldr ip, [ip, r0, lsl #2]\n" /* R12=The address of the stub for this syscall */ + " blx ip\n" /* Call the stub (modifies lr) */ + " ldr lr, [sp, #12]\n" /* Restore lr */ + " ldr r2, [sp, #16]\n" /* Restore (orig_SP - new_SP) value */ + " add sp, sp, r2\n" /* Restore SP */ + " mov r2, r0\n" /* R2=Save return value in R2 */ + " mov r0, #3\n" /* R0=SYS_syscall_return */ + " svc 0" /* Return from the syscall */ + ); } #endif @@ -185,17 +186,19 @@ int up_svcall(int irq, FAR void *context, FAR void *arg) /* R0=SYS_restore_context: This a restore context command: * - * void up_fullcontextrestore(uint32_t *restoreregs) noreturn_function; + * void up_fullcontextrestore(uint32_t *restoreregs) + * noreturn_function; * * At this point, the following values are saved in context: * * R0 = SYS_restore_context * R1 = restoreregs * - * In this case, we simply need to set CURRENT_REGS to restore register - * area referenced in the saved R1. context == CURRENT_REGS is the normal - * exception return. By setting CURRENT_REGS = context[R1], we force - * the return to the saved context referenced in R1. + * In this case, we simply need to set CURRENT_REGS to restore + * register area referenced in the saved R1. context == CURRENT_REGS + * is the normal exception return. By setting CURRENT_REGS = + * context[R1], we force the return to the saved context referenced + * in R1. */ case SYS_restore_context: @@ -262,8 +265,8 @@ int up_svcall(int irq, FAR void *context, FAR void *arg) regs[REG_EXC_RETURN] = rtcb->xcp.syscall[index].excreturn; rtcb->xcp.nsyscalls = index; - /* The return value must be in R0-R1. dispatch_syscall() temporarily - * moved the value for R0 into R2. + /* The return value must be in R0-R1. dispatch_syscall() + * temporarily moved the value for R0 into R2. */ regs[REG_R0] = regs[REG_R2]; @@ -280,7 +283,8 @@ int up_svcall(int irq, FAR void *context, FAR void *arg) /* R0=SYS_task_start: This a user task start * - * void up_task_start(main_t taskentry, int argc, FAR char *argv[]) noreturn_function; + * void up_task_start(main_t taskentry, int argc, FAR char *argv[]) + * noreturn_function; * * At this point, the following values are saved in context: * @@ -313,7 +317,8 @@ int up_svcall(int irq, FAR void *context, FAR void *arg) /* R0=SYS_pthread_start: This a user pthread start * - * void up_pthread_start(pthread_startroutine_t entrypt, pthread_addr_t arg) noreturn_function; + * void up_pthread_start(pthread_startroutine_t entrypt, + * pthread_addr_t arg) noreturn_function; * * At this point, the following values are saved in context: * @@ -454,7 +459,9 @@ int up_svcall(int irq, FAR void *context, FAR void *arg) break; } - /* Report what happened. That might difficult in the case of a context switch */ + /* Report what happened. That might difficult in the case of a context + * switch. + */ #ifdef CONFIG_DEBUG_SYSCALL_INFO # ifndef CONFIG_DEBUG_SVCALL diff --git a/arch/arm/src/armv7-m/up_systemreset.c b/arch/arm/src/armv7-m/up_systemreset.c index 2181382d96a..956d49126d9 100644 --- a/arch/arm/src/armv7-m/up_systemreset.c +++ b/arch/arm/src/armv7-m/up_systemreset.c @@ -33,7 +33,7 @@ #include "nvic.h" /**************************************************************************** - * Public functions + * Public Functions ****************************************************************************/ /****************************************************************************