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Merged in jjlange/nuttx/lpc40xx (pull request #946)

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Add support for LPC40xx family chips

* Corrected a few peripheral definitions and pin functions for the LPC17xx family.
    Added configuration options, chip definitions, and additional pin functions for the LPC40xx family.
    Added board configurations for Embedded Artists LPC4088 Quickstart board and LPC4088 Developer's kit.  These configurations are still something of a work in progress.  In particular, the LCD functionality is untested.

* First pass rename in *.c and *.h files.

* Renamed LPC17XX to LPC17XX_40XX in config files

* Rplaced LPC17xx with LPC17xx/LPC40xx in .c files

* Replaced LPC17xx with LPC17xx/LPC40xx in .h files

* Updated some documentation

* Working on moving directories

* moved arch/arm/src/lpc17xx and arch/arm/include/lpc17xx to lpc17xx_40xx

* Renamed LPC17_* constants / configuration options to LPC17_40_*

* Updated chip family name defines

* Renamed some chip-specific files

* Updated references to renamed files

* Updated references to lpc17_ to lpc17_40_

* Renamed source files from lpc17_* to lpc17_40_*

* Clean up white space

Approved-by: Gregory Nutt <gnutt@nuttx.org>
This commit is contained in:
jjlange 2019-07-11 16:50:00 +00:00 • committed by Gregory Nutt
parent 8578ce9832
commit e5dfd805e6
400 changed files with 27550 additions and 16939 deletions
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388
arch/arm/include/lpc17xx/chip.h
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@ -1,388 +0,0 @@
/************************************************************************************
* arch/arm/include/lpc17xx/chip.h
*
* Copyright (C) 2010-2011, 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
* with LPC178x support from Rommel Marcelo
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_INCLUDE_LPC17XX_CHIP_H
#define __ARCH_ARM_INCLUDE_LPC17XX_CHIP_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Get customizations for each supported chip */
#if defined(CONFIG_ARCH_CHIP_LPC1751)
# define LPC176x 1 /* LPC175/6 family */
# undef LPC178x /* Not LPC177/8 family */
# define LPC17_FLASH_SIZE (32*1024) /* 32Kb */
# define LPC17_SRAM_SIZE (8*1024) /* 8Kb */
# define LPC17_CPUSRAM_SIZE (8*1024)
# undef LPC17_HAVE_BANK0 /* No AHB SRAM bank 0 */
# undef LPC17_HAVE_BANK1 /* No AHB SRAM bank 1 */
# define LPC17_NETHCONTROLLERS 0 /* No Ethernet controller */
# define LPC17_NUSBHOST 0 /* No USB host controller */
# define LPC17_NUSBOTG 0 /* No USB OTG controller */
# define LPC17_NUSBDEV 1 /* One USB device controller */
# define LPC17_NCAN 1 /* One CAN controller */
# define LPC17_NI2S 0 /* No I2S modules */
# define LPC17_NDAC 0 /* No DAC module */
#elif defined(CONFIG_ARCH_CHIP_LPC1752)
# define LPC176x 1 /* LPC175/6 family */
# undef LPC178x /* Not LPC177/8 family */
# define LPC17_FLASH_SIZE (64*1024) /* 65Kb */
# define LPC17_SRAM_SIZE (16*1024) /* 16Kb */
# define LPC17_CPUSRAM_SIZE (16*1024)
# undef LPC17_HAVE_BANK0 /* No AHB SRAM bank 0 */
# undef LPC17_HAVE_BANK1 /* No AHB SRAM bank 1 */
# define LPC17_NETHCONTROLLERS 0 /* No Ethernet controller */
# define LPC17_NUSBHOST 0 /* No USB host controller */
# define LPC17_NUSBOTG 0 /* No USB OTG controller */
# define LPC17_NUSBDEV 1 /* One USB device controller */
# define LPC17_NCAN 1 /* One CAN controller */
# define LPC17_NI2S 0 /* No I2S modules */
# define LPC17_NDAC 0 /* No DAC module */
#elif defined(CONFIG_ARCH_CHIP_LPC1754)
# define LPC176x 1 /* LPC175/6 family */
# undef LPC178x /* Not LPC177/8 family */
# define LPC17_FLASH_SIZE (128*1024) /* 128Kb */
# define LPC17_SRAM_SIZE (32*1024) /* 32Kb */
# define LPC17_CPUSRAM_SIZE (16*1024)
# define LPC17_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */
# undef LPC17_HAVE_BANK1 /* No AHB SRAM bank 1 */
# define LPC17_NETHCONTROLLERS 0 /* No Ethernet controller */
# define LPC17_NUSBHOST 1 /* One USB host controller */
# define LPC17_NUSBOTG 1 /* One USB OTG controller */
# define LPC17_NUSBDEV 1 /* One USB device controller */
# define LPC17_NCAN 1 /* One CAN controller */
# define LPC17_NI2S 0 /* No I2S modules */
# define LPC17_NDAC 1 /* One DAC module */
#elif defined(CONFIG_ARCH_CHIP_LPC1756)
# define LPC176x 1 /* LPC175/6 family */
# undef LPC178x /* Not LPC177/8 family */
# define LPC17_FLASH_SIZE (256*1024) /* 256Kb */
# define LPC17_SRAM_SIZE (32*1024) /* 32Kb */
# define LPC17_CPUSRAM_SIZE (16*1024)
# define LPC17_HAVE_BANK0 1 /* No AHB SRAM bank 0 */
# undef LPC17_HAVE_BANK1 /* No AHB SRAM bank 1 */
# define LPC17_NETHCONTROLLERS 0 /* No Ethernet controller */
# define LPC17_NUSBHOST 1 /* One USB host controller */
# define LPC17_NUSBOTG 1 /* One USB OTG controller */
# define LPC17_NUSBDEV 1 /* One USB device controller */
# define LPC17_NCAN 2 /* Two CAN controllers */
# define LPC17_NI2S 1 /* One I2S module */
# define LPC17_NDAC 1 /* One DAC module */
#elif defined(CONFIG_ARCH_CHIP_LPC1758)
# define LPC176x 1 /* LPC175/6 family */
# undef LPC178x /* Not LPC177/8 family */
# define LPC17_FLASH_SIZE (512*1024) /* 512Kb */
# define LPC17_SRAM_SIZE (64*1024) /* 64Kb */
# define LPC17_CPUSRAM_SIZE (32*1024)
# define LPC17_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */
# define LPC17_HAVE_BANK1 1 /* Have AHB SRAM bank 1 */
# define LPC17_NETHCONTROLLERS 1 /* One Ethernet controller */
# define LPC17_NUSBHOST 1 /* One USB host controller */
# define LPC17_NUSBOTG 1 /* One USB OTG controller */
# define LPC17_NUSBDEV 1 /* One USB device controller */
# define LPC17_NCAN 2 /* Two CAN controllers */
# define LPC17_NI2S 1 /* One I2S module */
# define LPC17_NDAC 1 /* One DAC module */
#elif defined(CONFIG_ARCH_CHIP_LPC1759)
# define LPC176x 1 /* LPC175/6 family */
# undef LPC178x /* Not LPC177/8 family */
# define LPC17_FLASH_SIZE (512*1024) /* 512Kb */
# define LPC17_SRAM_SIZE (64*1024) /* 64Kb */
# define LPC17_CPUSRAM_SIZE (32*1024)
# define LPC17_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */
# define LPC17_HAVE_BANK1 1 /* Have AHB SRAM bank 1 */
# define LPC17_NETHCONTROLLERS 0 /* No Ethernet controller */
# define LPC17_NUSBHOST 1 /* One USB host controller */
# define LPC17_NUSBOTG 1 /* One USB OTG controller */
# define LPC17_NUSBDEV 1 /* One USB device controller */
# define LPC17_NCAN 2 /* Two CAN controllers */
# define LPC17_NI2S 1 /* One I2S module */
# define LPC17_NDAC 1 /* One DAC module */
#elif defined(CONFIG_ARCH_CHIP_LPC1764)
# define LPC176x 1 /* LPC175/6 family */
# undef LPC178x /* Not LPC177/8 family */
# define LPC17_FLASH_SIZE (128*1024) /* 128Kb */
# define LPC17_SRAM_SIZE (32*1024) /* 32Kb */
# define LPC17_CPUSRAM_SIZE (16*1024)
# define LPC17_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */
# undef LPC17_HAVE_BANK1 /* No AHB SRAM bank 1 */
# define LPC17_NETHCONTROLLERS 1 /* One Ethernet controller */
# define LPC17_NUSBHOST 0 /* No USB host controller */
# define LPC17_NUSBOTG 0 /* No USB OTG controller */
# define LPC17_NUSBDEV 1 /* One USB device controller */
# define LPC17_NCAN 2 /* Two CAN controllers */
# define LPC17_NI2S 0 /* No I2S modules */
# define LPC17_NDAC 0 /* No DAC module */
#elif defined(CONFIG_ARCH_CHIP_LPC1765)
# define LPC176x 1 /* LPC175/6 family */
# undef LPC178x /* Not LPC177/8 family */
# define LPC17_FLASH_SIZE (256*1024) /* 256Kb */
# define LPC17_SRAM_SIZE (64*1024) /* 64Kb */
# define LPC17_CPUSRAM_SIZE (32*1024)
# define LPC17_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */
# define LPC17_HAVE_BANK1 1 /* Have AHB SRAM bank 1 */
# define LPC17_NETHCONTROLLERS 0 /* No Ethernet controller */
# define LPC17_NUSBHOST 1 /* One USB host controller */
# define LPC17_NUSBOTG 1 /* One USB OTG controller */
# define LPC17_NUSBDEV 1 /* One USB device controller */
# define LPC17_NCAN 2 /* Two CAN controllers */
# define LPC17_NI2S 1 /* One I2S module */
# define LPC17_NDAC 1 /* One DAC module */
#elif defined(CONFIG_ARCH_CHIP_LPC1766)
# define LPC176x 1 /* LPC175/6 family */
# undef LPC178x /* Not LPC177/8 family */
# define LPC17_FLASH_SIZE (256*1024) /* 256Kb */
# define LPC17_SRAM_SIZE (64*1024) /* 64Kb */
# define LPC17_CPUSRAM_SIZE (32*1024)
# define LPC17_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */
# define LPC17_HAVE_BANK1 1 /* Have AHB SRAM bank 1 */
# define LPC17_NETHCONTROLLERS 1 /* One Ethernet controller */
# define LPC17_NUSBHOST 1 /* One USB host controller */
# define LPC17_NUSBOTG 1 /* One USB OTG controller */
# define LPC17_NUSBDEV 1 /* One USB device controller */
# define LPC17_NCAN 2 /* Two CAN controllers */
# define LPC17_NI2S 1 /* One I2S module */
# define LPC17_NDAC 1 /* One DAC module */
#elif defined(CONFIG_ARCH_CHIP_LPC1767)
# define LPC176x 1 /* LPC175/6 family */
# undef LPC178x /* Not LPC177/8 family */
# define LPC17_FLASH_SIZE (512*1024) /* 512Kb */
# define LPC17_SRAM_SIZE (64*1024) /* 64Kb */
# define LPC17_CPUSRAM_SIZE (32*1024)
# define LPC17_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */
# define LPC17_HAVE_BANK1 1 /* Have AHB SRAM bank 1 */
# define LPC17_NETHCONTROLLERS 1 /* One Ethernet controller */
# define LPC17_NUSBHOST 0 /* No USB host controller */
# define LPC17_NUSBOTG 0 /* No USB OTG controller */
# define LPC17_NUSBDEV 0 /* No USB device controller */
# define LPC17_NCAN 0 /* No CAN controllers */
# define LPC17_NI2S 1 /* One I2S module */
# define LPC17_NDAC 1 /* One DAC module */
#elif defined(CONFIG_ARCH_CHIP_LPC1769) || defined(CONFIG_ARCH_CHIP_LPC1768)
# define LPC176x 1 /* LPC175/6 family */
# undef LPC178x /* Not LPC177/8 family */
# define LPC17_FLASH_SIZE (512*1024) /* 512Kb */
# define LPC17_SRAM_SIZE (64*1024) /* 64Kb */
# define LPC17_CPUSRAM_SIZE (32*1024)
# define LPC17_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */
# define LPC17_HAVE_BANK1 1 /* Have AHB SRAM bank 1 */
# define LPC17_NETHCONTROLLERS 1 /* One Ethernet controller */
# define LPC17_NUSBHOST 1 /* One USB host controller */
# define LPC17_NUSBOTG 1 /* One USB OTG controller */
# define LPC17_NUSBDEV 1 /* One USB device controller */
# define LPC17_NCAN 2 /* Two CAN controllers */
# define LPC17_NI2S 1 /* One I2S module */
# define LPC17_NDAC 1 /* One DAC module */
#elif defined(CONFIG_ARCH_CHIP_LPC1773)
# undef LPC176x /* Not LPC175/6 family */
# define LPC178x 1 /* LPC177/8 family */
# define LPC17_FLASH_SIZE (128*1024) /* 128Kb */
# define LPC17_SRAM_SIZE (40*1024) /* 40Kb */
# define LPC17_CPUSRAM_SIZE (32*1024)
# define LPC17_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0 */
# undef LPC17_HAVE_BANK1 /* No Peripheral SRAM bank 1 */
# define LPC17_NETHCONTROLLERS 1 /* One Ethernet controller */
# undef LPC17_NUSBHOST /* No USB host controller */
# undef LPC17_NUSBOTG /* No USB OTG controller */
# define LPC17_NUSBDEV 1 /* One USB device controller */
# define LPC17_HAVE_SPIFI 1 /* Have SPIFI interface */
# undef LPC17_HAVE_LCD /* No LCD controller */
# undef LPC17_HAVE_QEI /* No QEI interface */
# undef LPC17_HAVE_SD /* No SD controller */
#elif defined(CONFIG_ARCH_CHIP_LPC1774)
# undef LPC176x /* Not LPC175/6 family */
# define LPC178x 1 /* LPC177/8 family */
# define LPC17_FLASH_SIZE (128*1024) /* 128Kb */
# define LPC17_SRAM_SIZE (40*1024) /* 40Kb */
# define LPC17_CPUSRAM_SIZE (32*1024)
# define LPC17_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0*/
# undef LPC17_HAVE_BANK1 /* Have Peripheral SRAM bank 1 */
# define LPC17_NETHCONTROLLERS 1 /* One Ethernet controller */
# undef LPC17_NUSBHOST /* One USB host controller */
# undef LPC17_NUSBOTG /* One USB OTG controller */
# define LPC17_NUSBDEV 1 /* One USB device controller */
# undef LPC17_HAVE_SPIFI /* Have SPIFI interface */
# undef LPC17_HAVE_LCD /* One LCD controller */
# define LPC17_HAVE_QEI 1 /* One QEI interface */
# define LPC17_HAVE_SD 1 /* One SD controller */
#elif defined(CONFIG_ARCH_CHIP_LPC1776)
# undef LPC176x /* Not LPC175/6 family */
# define LPC178x 1 /* LPC177/8 family */
# define LPC17_FLASH_SIZE (256*1024) /* 256Kb */
# define LPC17_SRAM_SIZE (80*1024) /* 80Kb */
# define LPC17_CPUSRAM_SIZE (64*1024)
# define LPC17_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0 */
# undef LPC17_HAVE_BANK1 /* Have Peripheral SRAM bank 1 */
# define LPC17_NETHCONTROLLERS 1 /* One Ethernet controller */
# define LPC17_NUSBHOST 1 /* One USB host controller */
# define LPC17_NUSBOTG 1 /* One USB OTG controller */
# define LPC17_NUSBDEV 1 /* One USB device controller */
# undef LPC17_HAVE_SPIFI /* Have SPIFI interface */
# undef LPC17_HAVE_LCD /* One LCD controller */
# define LPC17_HAVE_QEI 1 /* One QEI interface */
# define LPC17_HAVE_SD 1 /* One SD controller */
#elif defined(CONFIG_ARCH_CHIP_LPC1777)
# undef LPC176x /* Not LPC175/6 family */
# define LPC178x 1 /* LPC177/8 family */
# define LPC17_FLASH_SIZE (512*1024) /* 512Kb */
# define LPC17_SRAM_SIZE (96*1024) /* 96Kb */
# define LPC17_CPUSRAM_SIZE (64*1024)
# define LPC17_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0 */
# define LPC17_HAVE_BANK1 1 /* Have Peripheral SRAM bank 1 */
# undef LPC17_NETHCONTROLLERS /* One Ethernet controller */
# define LPC17_NUSBHOST 1 /* One USB host controller */
# define LPC17_NUSBOTG 1 /* One USB OTG controller */
# define LPC17_NUSBDEV 1 /* One USB device controller */
# undef LPC17_HAVE_SPIFI /* Have SPIFI interface */
# undef LPC17_HAVE_LCD /* One LCD controller */
# define LPC17_HAVE_QEI 1 /* One QEI interface */
# define LPC17_HAVE_SD 1 /* One SD controller */
#elif defined(CONFIG_ARCH_CHIP_LPC1778)
# undef LPC176x /* Not LPC175/6 family */
# define LPC178x 1 /* LPC177/8 family */
# define LPC17_FLASH_SIZE (512*1024) /* 512Kb */
# define LPC17_SRAM_SIZE (96*1024) /* 64Kb */
# define LPC17_CPUSRAM_SIZE (64*1024)
# define LPC17_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0 */
# define LPC17_HAVE_BANK1 1 /* Have Peripheral SRAM bank 1 */
# define LPC17_NETHCONTROLLERS 1 /* One Ethernet controller */
# define LPC17_NUSBHOST 1 /* One USB host controller */
# define LPC17_NUSBOTG 1 /* One USB OTG controller */
# define LPC17_NUSBDEV 1 /* One USB device controller */
# undef LPC17_HAVE_SPIFI /* Have SPIFI interface */
# undef LPC17_HAVE_LCD /* One LCD controller */
# define LPC17_HAVE_QEI 1 /* One QEI interface */
# define LPC17_HAVE_SD 1 /* One SD controller */
#elif defined(CONFIG_ARCH_CHIP_LPC1785)
# undef LPC176x /* Not LPC175/6 family */
# define LPC178x 1 /* LPC177/8 family */
# define LPC17_FLASH_SIZE (256*1024) /* 256Kb */
# define LPC17_SRAM_SIZE (80*1024) /* 80Kb */
# define LPC17_CPUSRAM_SIZE (64*1024)
# define LPC17_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0 */
# undef LPC17_HAVE_BANK1 /* Have Peripheral SRAM bank 1 */
# undef LPC17_NETHCONTROLLERS /* One Ethernet controller */
# define LPC17_NUSBHOST 1 /* One USB host controller */
# define LPC17_NUSBOTG 1 /* One USB OTG controller */
# define LPC17_NUSBDEV 1 /* One USB device controller */
# undef LPC17_HAVE_SPIFI /* Have SPIFI interface */
# define LPC17_HAVE_LCD 1 /* One LCD controller */
# undef LPC17_HAVE_QEI /* One QEI interface */
# define LPC17_HAVE_SD 1 /* One SD controller */
#elif defined(CONFIG_ARCH_CHIP_LPC1786)
# undef LPC176x /* Not LPC175/6 family */
# define LPC178x 1 /* LPC177/8 family */
# define LPC17_FLASH_SIZE (256*1024) /* 256Kb */
# define LPC17_SRAM_SIZE (80*1024) /* 80Kb */
# define LPC17_CPUSRAM_SIZE (64*1024)
# define LPC17_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0 */
# undef LPC17_HAVE_BANK1 /* Have Peripheral SRAM bank 1 */
# define LPC17_NETHCONTROLLERS 1 /* One Ethernet controller */
# define LPC17_NUSBHOST 1 /* One USB host controller */
# define LPC17_NUSBOTG 1 /* One USB OTG controller */
# define LPC17_NUSBDEV 1 /* One USB device controller */
# undef LPC17_HAVE_SPIFI /* Have SPIFI interface */
# define LPC17_HAVE_LCD 1 /* One LCD controller */
# define LPC17_HAVE_QEI 1 /* One QEI interface */
# define LPC17_HAVE_SD 1 /* One SD controller */
#elif defined(CONFIG_ARCH_CHIP_LPC1787)
# undef LPC176x /* Not LPC175/6 family */
# define LPC178x 1 /* LPC177/8 family */
# define LPC17_FLASH_SIZE (512*1024) /* 512Kb */
# define LPC17_SRAM_SIZE (96*1024) /* 96Kb */
# define LPC17_CPUSRAM_SIZE (64*1024)
# define LPC17_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0 */
# define LPC17_HAVE_BANK1 1 /* Have Peripheral SRAM bank 1 */
# undef LPC17_NETHCONTROLLERS /* One Ethernet controller */
# define LPC17_NUSBHOST 1 /* One USB host controller */
# define LPC17_NUSBOTG 1 /* One USB OTG controller */
# define LPC17_NUSBDEV 1 /* One USB device controller */
# undef LPC17_HAVE_SPIFI /* Have SPIFI interface */
# define LPC17_HAVE_LCD 1 /* One LCD controller */
# define LPC17_HAVE_QEI 1 /* One QEI interface */
# define LPC17_HAVE_SD 1 /* One SD controller */
#elif defined(CONFIG_ARCH_CHIP_LPC1788)
# undef LPC176x /* Not LPC175/6 family */
# define LPC178x 1 /* LPC177/8 family */
# define LPC17_FLASH_SIZE (512*1024) /* 512Kb */
# define LPC17_SRAM_SIZE (96*1024) /* 96Kb */
# define LPC17_CPUSRAM_SIZE (64*1024)
# define LPC17_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0 */
# define LPC17_HAVE_BANK1 1 /* Have Peripheral SRAM bank 1 */
# define LPC17_NETHCONTROLLERS 1 /* One Ethernet controller */
# define LPC17_NUSBHOST 1 /* One USB host controller */
# define LPC17_NUSBOTG 1 /* One USB OTG controller */
# define LPC17_NUSBDEV 1 /* One USB device controller */
# undef LPC17_HAVE_SPIFI /* Have SPIFI interface */
# define LPC17_HAVE_LCD 1 /* One LCD controller */
# define LPC17_HAVE_QEI 1 /* One QEI interface */
# define LPC17_HAVE_SD 1 /* One SD controller */
#else
# error "Unsupported LPC17xx chip"
#endif
/* NVIC priority levels *************************************************************/
/* Each priority field holds a priority value, 0-31. The lower the value, the greater
* the priority of the corresponding interrupt. The processor implements only
* bits[7:3] of each field, bits[2:0] read as zero and ignore writes.
*/
#define NVIC_SYSH_PRIORITY_MIN 0xf8 /* All bits[7:3] set is minimum priority */
#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */
#define NVIC_SYSH_PRIORITY_STEP 0x08 /* Five bits of interrupt priority used */
/************************************************************************************
* Public Types
************************************************************************************/
/************************************************************************************
* Public Data
************************************************************************************/
/************************************************************************************
* Public Functions
************************************************************************************/
#endif /* __ARCH_ARM_INCLUDE_LPC17XX_CHIP_H */

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arch/arm/include/lpc17xx/lpc176x_irq.h
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@ -1,245 +0,0 @@
/****************************************************************************
* arch/lpc17xx/lpc176x_irq.h
*
* Copyright (C) 2010-2011, 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/* This file should never be included directed but, rather, only indirectly
* through nuttx/irq.h
*/
#ifndef __ARCH_ARM_INCLUDE_LPC17XX_LPC176X_IRQ_H
#define __ARCH_ARM_INCLUDE_LPC17XX_LPC176X_IRQ_H
/****************************************************************************
* Included Files
****************************************************************************/
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* IRQ numbers. The IRQ number corresponds vector number and hence map
* directly to bits in the NVIC. This does, however, waste several words of
* memory in the IRQ to handle mapping tables.
*/
/* External interrupts (vectors >= 16) */
#define LPC17_IRQ_WDT (LPC17_IRQ_EXTINT+0) /* WDT Watchdog Interrupt (WDINT) */
#define LPC17_IRQ_TMR0 (LPC17_IRQ_EXTINT+1) /* Timer 0 Match 0 - 1 (MR0, MR1)
* Capture 0 - 1 (CR0, CR1) */
#define LPC17_IRQ_TMR1 (LPC17_IRQ_EXTINT+2) /* Timer 1 Match 0 - 2 (MR0, MR1, MR2)
* Capture 0 - 1 (CR0, CR1) */
#define LPC17_IRQ_TMR2 (LPC17_IRQ_EXTINT+3) /* Timer 2 Match 0-3
* Capture 0-1 */
#define LPC17_IRQ_TMR3 (LPC17_IRQ_EXTINT+4) /* Timer 3 Match 0-3
* Capture 0-1 */
#define LPC17_IRQ_UART0 (LPC17_IRQ_EXTINT+5) /* UART 0 Rx Line Status (RLS)
* Transmit Holding Register Empty (THRE)
* Rx Data Available (RDA)
* Character Time-out Indicator (CTI)
* End of Auto-Baud (ABEO)
* Auto-Baud Time-Out (ABTO) */
#define LPC17_IRQ_UART1 (LPC17_IRQ_EXTINT+6) /* UART 1 Rx Line Status (RLS)
* Transmit Holding Register Empty (THRE)
* Rx Data Available (RDA)
* Character Time-out Indicator (CTI)
* Modem Control Change
* End of Auto-Baud (ABEO)
* Auto-Baud Time-Out (ABTO) */
#define LPC17_IRQ_UART2 (LPC17_IRQ_EXTINT+7) /* UART 2 Rx Line Status (RLS)
* Transmit Holding Register Empty (THRE)
* Rx Data Available (RDA)
* Character Time-out Indicator (CTI)
* End of Auto-Baud (ABEO)
* Auto-Baud Time-Out (ABTO) */
#define LPC17_IRQ_UART3 (LPC17_IRQ_EXTINT+8) /* UART 3 Rx Line Status (RLS)
* Transmit Holding Register Empty (THRE)
* Rx Data Available (RDA)
* Character Time-out Indicator (CTI)
* End of Auto-Baud (ABEO)
* Auto-Baud Time-Out (ABTO) */
#define LPC17_IRQ_PWM1 (LPC17_IRQ_EXTINT+9) /* PWM1 Match 0 - 6 of PWM1
* Capture 0-1 of PWM1 */
#define LPC17_IRQ_I2C0 (LPC17_IRQ_EXTINT+10) /* I2C0 SI (state change) */
#define LPC17_IRQ_I2C1 (LPC17_IRQ_EXTINT+11) /* I2C1 SI (state change) */
#define LPC17_IRQ_I2C2 (LPC17_IRQ_EXTINT+12) /* I2C2 SI (state change) */
#define LPC17_IRQ_SPIF (LPC17_IRQ_EXTINT+13) /* SPI SPI Interrupt Flag (SPIF)
* Mode Fault (MODF) */
#define LPC17_IRQ_SSP0 (LPC17_IRQ_EXTINT+14) /* SSP0 Tx FIFO half empty of SSP0
* Rx FIFO half full of SSP0
* Rx Timeout of SSP0
* Rx Overrun of SSP0 */
#define LPC17_IRQ_SSP1 (LPC17_IRQ_EXTINT+15) /* SSP 1 Tx FIFO half empty
* Rx FIFO half full
* Rx Timeout
* Rx Overrun */
#define LPC17_IRQ_PLL0 (LPC17_IRQ_EXTINT+16) /* PLL0 (Main PLL) PLL0 Lock (PLOCK0) */
#define LPC17_IRQ_RTC (LPC17_IRQ_EXTINT+17) /* RTC Counter Increment (RTCCIF)
* Alarm (RTCALF) */
#define LPC17_IRQ_EINT0 (LPC17_IRQ_EXTINT+18) /* External Interrupt 0 (EINT0) */
#define LPC17_IRQ_EINT1 (LPC17_IRQ_EXTINT+19) /* External Interrupt 1 (EINT1) */
#define LPC17_IRQ_EINT2 (LPC17_IRQ_EXTINT+20) /* External Interrupt 2 (EINT2) */
#define LPC17_IRQ_EINT3 (LPC17_IRQ_EXTINT+21) /* External Interrupt 3 (EINT3)
* Note: EINT3 channel is shared with GPIO interrupts */
#define LPC17_IRQ_ADC (LPC17_IRQ_EXTINT+22) /* ADC A/D Converter end of conversion */
#define LPC17_IRQ_BOD (LPC17_IRQ_EXTINT+23) /* BOD Brown Out detect */
#define LPC17_IRQ_USB (LPC17_IRQ_EXTINT+24) /* USB USB_INT_REQ_LP, USB_INT_REQ_HP,
* USB_INT_REQ_DMA */
#define LPC17_IRQ_CAN (LPC17_IRQ_EXTINT+25) /* CAN CAN Common, CAN 0 Tx, CAN 0 Rx,
* CAN 1 Tx, CAN 1 Rx */
#define LPC17_IRQ_GPDMA (LPC17_IRQ_EXTINT+26) /* GPDMA IntStatus of DMA channel 0,
* IntStatus of DMA channel 1 */
#define LPC17_IRQ_I2S (LPC17_IRQ_EXTINT+27) /* I2S irq, dmareq1, dmareq2 */
#define LPC17_IRQ_ETH (LPC17_IRQ_EXTINT+28) /* Ethernet WakeupInt, SoftInt, TxDoneInt,
* TxFinishedInt, TxErrorInt,* TxUnderrunInt,
* RxDoneInt, RxFinishedInt, RxErrorInt,
* RxOverrunInt */
#define LPC17_IRQ_RITINT (LPC17_IRQ_EXTINT+29) /* Repetitive Interrupt Timer (RITINT) */
#define LPC17_IRQ_MCPWM (LPC17_IRQ_EXTINT+30) /* Motor Control PWM IPER[2:0], IPW[2:0],
* ICAP[2:0], FES */
#define LPC17_IRQ_QEI (LPC17_IRQ_EXTINT+31) /* Quadrature Encoder INX_Int, TIM_Int, VELC_Int,
* DIR_Int, ERR_Int, ENCLK_Int, POS0_Int, POS1_Int
* POS2_Int, REV_Int, POS0REV_Int, OS1REV_Int,
* POS2REV_Int */
#define LPC17_IRQ_PLL1 (LPC17_IRQ_EXTINT+32) /* PLL1 (USB PLL) PLL1 Lock (PLOCK1) */
#define LPC17_IRQ_USBACT (LPC17_IRQ_EXTINT+33) /* USB Activity Interrupt USB_NEED_CLK */
#define LPC17_IRQ_CANACT (LPC17_IRQ_EXTINT+34) /* CAN Activity Interrupt CAN1WAKE, CAN2WAKE */
#define LPC17_IRQ_NEXTINT (35)
#define LPC17_IRQ_NIRQS (LPC17_IRQ_EXTINT+LPC17_IRQ_NEXTINT)
/* GPIO interrupts. The LPC17xx supports several interrupts on ports 0 and
* 2 (only). We go through some special efforts to keep the number of IRQs
* to a minimum in this sparse interrupt case.
*
* 28 interrupts on Port 0: p0.0 - p0.11, p0.15-p0.30
* 14 interrupts on Port 2: p2.0 - p2.13
* --
* 42
*/
#ifdef CONFIG_LPC17_GPIOIRQ
# define LPC17_VALID_GPIOINT0 (0x7fff8ffful) /* GPIO port 0 interrupt set */
# define LPC17_VALID_GPIOINT2 (0x00003ffful) /* GPIO port 2 interrupt set */
/* Set 1: 12 interrupts p0.0-p0.11 */
# define LPC17_VALID_GPIOINT0L (0x00000ffful)
# define LPC17_VALID_SHIFT0L (0)
# define LPC17_VALID_FIRST0L (LPC17_IRQ_EXTINT+LPC17_IRQ_NEXTINT)
# define LPC17_IRQ_P0p0 (LPC17_VALID_FIRST0L+0)
# define LPC17_IRQ_P0p1 (LPC17_VALID_FIRST0L+1)
# define LPC17_IRQ_P0p2 (LPC17_VALID_FIRST0L+2)
# define LPC17_IRQ_P0p3 (LPC17_VALID_FIRST0L+3)
# define LPC17_IRQ_P0p4 (LPC17_VALID_FIRST0L+4)
# define LPC17_IRQ_P0p5 (LPC17_VALID_FIRST0L+5)
# define LPC17_IRQ_P0p6 (LPC17_VALID_FIRST0L+6)
# define LPC17_IRQ_P0p7 (LPC17_VALID_FIRST0L+7)
# define LPC17_IRQ_P0p8 (LPC17_VALID_FIRST0L+8)
# define LPC17_IRQ_P0p9 (LPC17_VALID_FIRST0L+9)
# define LPC17_IRQ_P0p10 (LPC17_VALID_FIRST0L+10)
# define LPC17_IRQ_P0p11 (LPC17_VALID_FIRST0L+11)
# define LPC17_VALID_NIRQS0L (12)
/* Set 2: 16 interrupts p0.15-p0.30 */
# define LPC17_VALID_GPIOINT0H (0x7fff8000ull)
# define LPC17_VALID_SHIFT0H (15)
# define LPC17_VALID_FIRST0H (LPC17_VALID_FIRST0L+LPC17_VALID_NIRQS0L)
# define LPC17_IRQ_P0p15 (LPC17_VALID_FIRST0H+0)
# define LPC17_IRQ_P0p16 (LPC17_VALID_FIRST0H+1)
# define LPC17_IRQ_P0p17 (LPC17_VALID_FIRST0H+2)
# define LPC17_IRQ_P0p18 (LPC17_VALID_FIRST0H+3)
# define LPC17_IRQ_P0p19 (LPC17_VALID_FIRST0H+4)
# define LPC17_IRQ_P0p20 (LPC17_VALID_FIRST0H+5)
# define LPC17_IRQ_P0p21 (LPC17_VALID_FIRST0H+6)
# define LPC17_IRQ_P0p22 (LPC17_VALID_FIRST0H+7)
# define LPC17_IRQ_P0p23 (LPC17_VALID_FIRST0H+8)
# define LPC17_IRQ_P0p24 (LPC17_VALID_FIRST0H+9)
# define LPC17_IRQ_P0p25 (LPC17_VALID_FIRST0H+10)
# define LPC17_IRQ_P0p26 (LPC17_VALID_FIRST0H+11)
# define LPC17_IRQ_P0p27 (LPC17_VALID_FIRST0H+12)
# define LPC17_IRQ_P0p28 (LPC17_VALID_FIRST0H+13)
# define LPC17_IRQ_P0p29 (LPC17_VALID_FIRST0H+14)
# define LPC17_IRQ_P0p30 (LPC17_VALID_FIRST0H+15)
# define LPC17_VALID_NIRQS0H (16)
/* Set 3: 14 interrupts p2.0-p2.13 */
# define LPC17_VALID_GPIOINT2 (0x00003ffful)
# define LPC17_VALID_SHIFT2 (0)
# define LPC17_VALID_FIRST2 (LPC17_VALID_FIRST0H+LPC17_VALID_NIRQS0H)
# define LPC17_IRQ_P2p0 (LPC17_VALID_FIRST2+0)
# define LPC17_IRQ_P2p1 (LPC17_VALID_FIRST2+1)
# define LPC17_IRQ_P2p2 (LPC17_VALID_FIRST2+2)
# define LPC17_IRQ_P2p3 (LPC17_VALID_FIRST2+3)
# define LPC17_IRQ_P2p4 (LPC17_VALID_FIRST2+4)
# define LPC17_IRQ_P2p5 (LPC17_VALID_FIRST2+5)
# define LPC17_IRQ_P2p6 (LPC17_VALID_FIRST2+6)
# define LPC17_IRQ_P2p7 (LPC17_VALID_FIRST2+7)
# define LPC17_IRQ_P2p8 (LPC17_VALID_FIRST2+8)
# define LPC17_IRQ_P2p9 (LPC17_VALID_FIRST2+9)
# define LPC17_IRQ_P2p10 (LPC17_VALID_FIRST2+10)
# define LPC17_IRQ_P2p11 (LPC17_VALID_FIRST2+11)
# define LPC17_IRQ_P2p12 (LPC17_VALID_FIRST2+12)
# define LPC17_IRQ_P2p13 (LPC17_VALID_FIRST2+13)
# define LPC17_VALID_NIRQS2 (14)
# define LPC17_NGPIOAIRQS (LPC17_VALID_NIRQS0L+LPC17_VALID_NIRQS0H+LPC17_VALID_NIRQS2)
#else
# define LPC17_NGPIOAIRQS (0)
#endif
/* Total number of IRQ numbers */
#define NR_IRQS (LPC17_IRQ_EXTINT+LPC17_IRQ_NEXTINT+LPC17_NGPIOAIRQS)
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Inline functions
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_INCLUDE_LPC17XX_LPC176X_IRQ_H */

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@ -1,291 +0,0 @@
/****************************************************************************
* arch/arm/include/lpc17xxx/lpc178x_irq.h
*
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
* Authors: Rommel Marcelo
* Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/* This file should never be included directed but, rather,
* only indirectly through nuttx/irq.h
*/
#ifndef __ARCH_ARM_INCLUDE_LPC17XX_LPC178X_IRQ_H
#define __ARCH_ARM_INCLUDE_LPC17XX_LPC178X_IRQ_H
/****************************************************************************
* Included Files
****************************************************************************/
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* IRQ numbers. The IRQ number corresponds vector number and hence map
* directly to bits in the NVIC. This does, however, waste several words of
* memory in the IRQ to handle mapping tables.
*/
/* External interrupts (vectors >= 16) */
#define LPC17_IRQ_WDT (LPC17_IRQ_EXTINT+0) /* WDT Watchdog Interrupt (WDINT) */
#define LPC17_IRQ_TMR0 (LPC17_IRQ_EXTINT+1) /* Timer 0 Match 0 - 1 (MR0, MR1)
* Capture 0 - 1 (CR0, CR1) */
#define LPC17_IRQ_TMR1 (LPC17_IRQ_EXTINT+2) /* Timer 1 Match 0 - 2 (MR0, MR1, MR2)
* Capture 0 - 1 (CR0, CR1) */
#define LPC17_IRQ_TMR2 (LPC17_IRQ_EXTINT+3) /* Timer 2 Match 0-3
* Capture 0-1 */
#define LPC17_IRQ_TMR3 (LPC17_IRQ_EXTINT+4) /* Timer 3 Match 0-3
* Capture 0-1 */
#define LPC17_IRQ_UART0 (LPC17_IRQ_EXTINT+5) /* UART 0 Rx Line Status (RLS)
* Transmit Holding Register Empty (THRE)
* Rx Data Available (RDA)
* Character Time-out Indicator (CTI)
* End of Auto-Baud (ABEO)
* Auto-Baud Time-Out (ABTO) */
#define LPC17_IRQ_UART1 (LPC17_IRQ_EXTINT+6) /* UART 1 Rx Line Status (RLS)
* Transmit Holding Register Empty (THRE)
* Rx Data Available (RDA)
* Character Time-out Indicator (CTI)
* Modem Control Change
* End of Auto-Baud (ABEO)
* Auto-Baud Time-Out (ABTO) */
#define LPC17_IRQ_UART2 (LPC17_IRQ_EXTINT+7) /* UART 2 Rx Line Status (RLS)
* Transmit Holding Register Empty (THRE)
* Rx Data Available (RDA)
* Character Time-out Indicator (CTI)
* End of Auto-Baud (ABEO)
* Auto-Baud Time-Out (ABTO) */
#define LPC17_IRQ_UART3 (LPC17_IRQ_EXTINT+8) /* UART 3 Rx Line Status (RLS)
* Transmit Holding Register Empty (THRE)
* Rx Data Available (RDA)
* Character Time-out Indicator (CTI)
* End of Auto-Baud (ABEO)
* Auto-Baud Time-Out (ABTO) */
#define LPC17_IRQ_PWM1 (LPC17_IRQ_EXTINT+9) /* PWM1 Match 0 - 6 of PWM1
* Capture 0-1 of PWM1 */
#define LPC17_IRQ_I2C0 (LPC17_IRQ_EXTINT+10) /* I2C0 SI (state change) */
#define LPC17_IRQ_I2C1 (LPC17_IRQ_EXTINT+11) /* I2C1 SI (state change) */
#define LPC17_IRQ_I2C2 (LPC17_IRQ_EXTINT+12) /* I2C2 SI (state change) */
#define LPC17_IRQ_RESERVED29 (LPC17_IRQ_EXTINT+13) /* Unused */
#define LPC17_IRQ_SSP0 (LPC17_IRQ_EXTINT+14) /* SSP0 Tx FIFO half empty of SSP0
* Rx FIFO half full of SSP0
* Rx Timeout of SSP0
* Rx Overrun of SSP0 */
#define LPC17_IRQ_SSP1 (LPC17_IRQ_EXTINT+15) /* SSP 1 Tx FIFO half empty
* Rx FIFO half full
* Rx Timeout
* Rx Overrun */
#define LPC17_IRQ_PLL0 (LPC17_IRQ_EXTINT+16) /* PLL0 (Main PLL) PLL0 Lock (PLOCK0) */
#define LPC17_IRQ_RTC (LPC17_IRQ_EXTINT+17) /* RTC Counter Increment (RTCCIF)
* Alarm (RTCALF) */
#define LPC17_IRQ_EINT0 (LPC17_IRQ_EXTINT+18) /* External Interrupt 0 (EINT0) */
#define LPC17_IRQ_EINT1 (LPC17_IRQ_EXTINT+19) /* External Interrupt 1 (EINT1) */
#define LPC17_IRQ_EINT2 (LPC17_IRQ_EXTINT+20) /* External Interrupt 2 (EINT2) */
#define LPC17_IRQ_EINT3 (LPC17_IRQ_EXTINT+21) /* External Interrupt 3 (EINT3)
* Note: EINT3 channel is shared with GPIO interrupts */
#define LPC17_IRQ_ADC (LPC17_IRQ_EXTINT+22) /* ADC A/D Converter end of conversion */
#define LPC17_IRQ_BOD (LPC17_IRQ_EXTINT+23) /* BOD Brown Out detect */
#define LPC17_IRQ_USB (LPC17_IRQ_EXTINT+24) /* USB USB_INT_REQ_LP, USB_INT_REQ_HP,
* USB_INT_REQ_DMA */
#define LPC17_IRQ_CAN (LPC17_IRQ_EXTINT+25) /* CAN CAN Common, CAN 0 Tx, CAN 0 Rx,
* CAN 1 Tx, CAN 1 Rx */
#define LPC17_IRQ_GPDMA (LPC17_IRQ_EXTINT+26) /* GPDMA IntStatus of DMA channel 0,
* IntStatus of DMA channel 1 */
#define LPC17_IRQ_I2S (LPC17_IRQ_EXTINT+27) /* I2S irq, dmareq1, dmareq2 */
#define LPC17_IRQ_ETH (LPC17_IRQ_EXTINT+28) /* Ethernet WakeupInt, SoftInt, TxDoneInt,
* TxFinishedInt, TxErrorInt,* TxUnderrunInt,
* RxDoneInt, RxFinishedInt, RxErrorInt,
* RxOverrunInt */
#define LPC17_IRQ_MCI (LPC17_IRQ_EXTINT+29) /* MCI SD Card Interface */
#define LPC17_IRQ_MCPWM (LPC17_IRQ_EXTINT+30) /* Motor Control PWM IPER[2:0], IPW[2:0],
* ICAP[2:0], FES */
#define LPC17_IRQ_QEI (LPC17_IRQ_EXTINT+31) /* Quadrature Encoder INX_Int, TIM_Int, VELC_Int,
* DIR_Int, ERR_Int, ENCLK_Int, POS0_Int, POS1_Int
* POS2_Int, REV_Int, POS0REV_Int, OS1REV_Int,
* POS2REV_Int */
#define LPC17_IRQ_PLL1 (LPC17_IRQ_EXTINT+32) /* PLL1 (USB PLL) PLL1 Lock (PLOCK1) */
#define LPC17_IRQ_USBACT (LPC17_IRQ_EXTINT+33) /* USB Activity Interrupt USB_NEED_CLK */
#define LPC17_IRQ_CANACT (LPC17_IRQ_EXTINT+34) /* CAN Activity Interrupt CAN1WAKE, CAN2WAKE */
#define LPC17_IRQ_UART4 (LPC17_IRQ_EXTINT+35) /* UART 4 Rx Line Status (RLS)
* Transmit Holding Register Empty (THRE)
* Rx Data Available (RDA)
* Character Time-out Indicator (CTI)
* End of Auto-Baud (ABEO)
* Auto-Baud Time-Out (ABTO) */
#define LPC17_IRQ_SSP2 (LPC17_IRQ_EXTINT+36) /* SSP2 Tx FIFO half empty of SSP2
* Rx FIFO half full of SSP2
* Rx Timeout of SSP2
* Rx Overrun of SSP2 */
#define LPC17_IRQ_LCD (LPC17_IRQ_EXTINT+37) /* LCD interrupt
* BER, VCompI, LNBUI, FUFI, CrsrI */
#define LPC17_IRQ_GPIO (LPC17_IRQ_EXTINT+38) /* GPIO Interrupt
* P0xREI, P2xREI, P0xFEI, P2xFEI */
#define LPC17_IRQ_PWM0 (LPC17_IRQ_EXTINT+39) /* PWM0 Match 0 - 6 of PWM0
* Capture 0-1 of PWM0 */
#define LPC17_IRQ_EEPROM (LPC17_IRQ_EXTINT+40) /* EEPROM Interrupt
* EE_PROG_DONE, EE_RW_DONE */
#define LPC17_IRQ_NEXTINT (41)
#define LPC17_IRQ_NIRQS (LPC17_IRQ_EXTINT+LPC17_IRQ_NEXTINT)
/* GPIO interrupts. The LPC177x_8x supports several interrupts on ports 0 and
* 2 (only). We go through some special efforts to keep the number of IRQs
* to a minimum in this sparse interrupt case.
*
* 31 interrupts on Port 0: p0.0 - p0.30
* 31 interrupts on Port 2: p2.0 - p2.30
* --
* 42
*/
#ifdef CONFIG_LPC17_GPIOIRQ
# define LPC17_VALID_GPIOINT0 (0xfffffffful) /* GPIO port 0 interrupt set */
# define LPC17_VALID_GPIOINT2 (0xfffffffful) /* GPIO port 2 interrupt set */
/* Set 1: 16 interrupts p0.0-p0.15 */
# define LPC17_VALID_SHIFT0L (0)
# define LPC17_VALID_FIRST0L (LPC17_IRQ_EXTINT+LPC17_IRQ_NEXTINT)
# define LPC17_IRQ_P0p0 (LPC17_VALID_FIRST0L+0)
# define LPC17_IRQ_P0p1 (LPC17_VALID_FIRST0L+1)
# define LPC17_IRQ_P0p2 (LPC17_VALID_FIRST0L+2)
# define LPC17_IRQ_P0p3 (LPC17_VALID_FIRST0L+3)
# define LPC17_IRQ_P0p4 (LPC17_VALID_FIRST0L+4)
# define LPC17_IRQ_P0p5 (LPC17_VALID_FIRST0L+5)
# define LPC17_IRQ_P0p6 (LPC17_VALID_FIRST0L+6)
# define LPC17_IRQ_P0p7 (LPC17_VALID_FIRST0L+7)
# define LPC17_IRQ_P0p8 (LPC17_VALID_FIRST0L+8)
# define LPC17_IRQ_P0p9 (LPC17_VALID_FIRST0L+9)
# define LPC17_IRQ_P0p10 (LPC17_VALID_FIRST0L+10)
# define LPC17_IRQ_P0p11 (LPC17_VALID_FIRST0L+11)
# define LPC17_IRQ_P0p12 (LPC17_VALID_FIRST0L+12)
# define LPC17_IRQ_P0p13 (LPC17_VALID_FIRST0L+13)
# define LPC17_IRQ_P0p14 (LPC17_VALID_FIRST0L+14)
# define LPC17_IRQ_P0p15 (LPC17_VALID_FIRST0L+15)
# define LPC17_VALID_NIRQS0L (16)
/* Set 2: 16 interrupts p0.16-p0.31 */
# define LPC17_VALID_SHIFT0H (16)
# define LPC17_VALID_FIRST0H (LPC17_VALID_FIRST0L+LPC17_VALID_NIRQS0L)
# define LPC17_IRQ_P0p16 (LPC17_VALID_FIRST0H+0)
# define LPC17_IRQ_P0p17 (LPC17_VALID_FIRST0H+1)
# define LPC17_IRQ_P0p18 (LPC17_VALID_FIRST0H+2)
# define LPC17_IRQ_P0p19 (LPC17_VALID_FIRST0H+3)
# define LPC17_IRQ_P0p20 (LPC17_VALID_FIRST0H+4)
# define LPC17_IRQ_P0p21 (LPC17_VALID_FIRST0H+5)
# define LPC17_IRQ_P0p22 (LPC17_VALID_FIRST0H+6)
# define LPC17_IRQ_P0p23 (LPC17_VALID_FIRST0H+7)
# define LPC17_IRQ_P0p24 (LPC17_VALID_FIRST0H+8)
# define LPC17_IRQ_P0p25 (LPC17_VALID_FIRST0H+9)
# define LPC17_IRQ_P0p26 (LPC17_VALID_FIRST0H+10)
# define LPC17_IRQ_P0p27 (LPC17_VALID_FIRST0H+11)
# define LPC17_IRQ_P0p28 (LPC17_VALID_FIRST0H+12)
# define LPC17_IRQ_P0p29 (LPC17_VALID_FIRST0H+13)
# define LPC17_IRQ_P0p30 (LPC17_VALID_FIRST0H+14)
# define LPC17_IRQ_P0p31 (LPC17_VALID_FIRST0H+15)
# define LPC17_VALID_NIRQS0H (16)
/* Set 3: 16 interrupts p2.0-p2.15 */
# define LPC17_VALID_SHIFT2L (0)
# define LPC17_VALID_FIRST2L (LPC17_VALID_FIRST0H+LPC17_VALID_NIRQS0H)
# define LPC17_IRQ_P2p0 (LPC17_VALID_FIRST2L+0)
# define LPC17_IRQ_P2p1 (LPC17_VALID_FIRST2L+1)
# define LPC17_IRQ_P2p2 (LPC17_VALID_FIRST2L+2)
# define LPC17_IRQ_P2p3 (LPC17_VALID_FIRST2L+3)
# define LPC17_IRQ_P2p4 (LPC17_VALID_FIRST2L+4)
# define LPC17_IRQ_P2p5 (LPC17_VALID_FIRST2L+5)
# define LPC17_IRQ_P2p6 (LPC17_VALID_FIRST2L+6)
# define LPC17_IRQ_P2p7 (LPC17_VALID_FIRST2L+7)
# define LPC17_IRQ_P2p8 (LPC17_VALID_FIRST2L+8)
# define LPC17_IRQ_P2p9 (LPC17_VALID_FIRST2L+9)
# define LPC17_IRQ_P2p10 (LPC17_VALID_FIRST2L+10)
# define LPC17_IRQ_P2p11 (LPC17_VALID_FIRST2L+11)
# define LPC17_IRQ_P2p12 (LPC17_VALID_FIRST2L+12)
# define LPC17_IRQ_P2p13 (LPC17_VALID_FIRST2L+13)
# define LPC17_IRQ_P2p14 (LPC17_VALID_FIRST2L+14)
# define LPC17_IRQ_P2p15 (LPC17_VALID_FIRST2L+15)
# define LPC17_VALID_NIRQS2L (16)
/* Set 4: 16 interrupts p2.16 - p2.31 */
# define LPC17_VALID_SHIFT2H (16)
# define LPC17_VALID_FIRST2H (LPC17_VALID_FIRST2L+LPC17_VALID_NIRQS2L)
# define LPC17_IRQ_P2p16 (LPC17_VALID_FIRST2H+0)
# define LPC17_IRQ_P2p17 (LPC17_VALID_FIRST2H+1)
# define LPC17_IRQ_P2p18 (LPC17_VALID_FIRST2H+2)
# define LPC17_IRQ_P2p19 (LPC17_VALID_FIRST2H+3)
# define LPC17_IRQ_P2p20 (LPC17_VALID_FIRST2H+4)
# define LPC17_IRQ_P2p21 (LPC17_VALID_FIRST2H+5)
# define LPC17_IRQ_P2p22 (LPC17_VALID_FIRST2H+6)
# define LPC17_IRQ_P2p23 (LPC17_VALID_FIRST2H+7)
# define LPC17_IRQ_P2p24 (LPC17_VALID_FIRST2H+8)
# define LPC17_IRQ_P2p25 (LPC17_VALID_FIRST2H+9)
# define LPC17_IRQ_P2p26 (LPC17_VALID_FIRST2H+10)
# define LPC17_IRQ_P2p27 (LPC17_VALID_FIRST2H+11)
# define LPC17_IRQ_P2p28 (LPC17_VALID_FIRST2H+12)
# define LPC17_IRQ_P2p29 (LPC17_VALID_FIRST2H+13)
# define LPC17_IRQ_P2p30 (LPC17_VALID_FIRST2H+14)
# define LPC17_IRQ_P2p31 (LPC17_VALID_FIRST2H+15)
# define LPC17_VALID_NIRQS2H (16)
# define LPC17_NGPIOAIRQS (LPC17_VALID_NIRQS0L+LPC17_VALID_NIRQS0H+LPC17_VALID_NIRQS2L+LPC17_VALID_NIRQS2H)
#else
# define LPC17_NGPIOAIRQS (0)
#endif
/* Total number of IRQ numbers */
#define NR_IRQS (LPC17_IRQ_EXTINT+LPC17_IRQ_NEXTINT+LPC17_NGPIOAIRQS)
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Inline functions
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_INCLUDE_LPC17XX_LPC178X_IRQ_H */

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/************************************************************************************
* arch/arm/include/lpc17xx_40xx/chip.h
*
* Copyright (C) 2010-2011, 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
* with LPC178x support from Rommel Marcelo
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_INCLUDE_LPC17XX_40XX_CHIP_H
#define __ARCH_ARM_INCLUDE_LPC17XX_40XX_CHIP_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Get customizations for each supported chip */
#if defined(CONFIG_ARCH_CHIP_LPC1751)
# define LPC176x 1 /* LPC175/6 family */
# undef LPC178x_40xx /* Not LPC177/8 or LPC40xx family */
# define LPC17_40_FLASH_SIZE (32*1024) /* 32Kb */
# define LPC17_40_SRAM_SIZE (8*1024) /* 8Kb */
# define LPC17_40_CPUSRAM_SIZE (8*1024)
# undef LPC17_40_HAVE_BANK0 /* No AHB SRAM bank 0 */
# undef LPC17_40_HAVE_BANK1 /* No AHB SRAM bank 1 */
# define LPC17_40_NETHCONTROLLERS 0 /* No Ethernet controller */
# define LPC17_40_NUSBHOST 0 /* No USB host controller */
# define LPC17_40_NUSBOTG 0 /* No USB OTG controller */
# define LPC17_40_NUSBDEV 1 /* One USB device controller */
# define LPC17_40_NCAN 1 /* One CAN controller */
# define LPC17_40_NI2S 0 /* No I2S modules */
# define LPC17_40_NDAC 0 /* No DAC module */
#elif defined(CONFIG_ARCH_CHIP_LPC1752)
# define LPC176x 1 /* LPC175/6 family */
# undef LPC178x_40xx /* Not LPC177/8 or LPC40xx family */
# define LPC17_40_FLASH_SIZE (64*1024) /* 65Kb */
# define LPC17_40_SRAM_SIZE (16*1024) /* 16Kb */
# define LPC17_40_CPUSRAM_SIZE (16*1024)
# undef LPC17_40_HAVE_BANK0 /* No AHB SRAM bank 0 */
# undef LPC17_40_HAVE_BANK1 /* No AHB SRAM bank 1 */
# define LPC17_40_NETHCONTROLLERS 0 /* No Ethernet controller */
# define LPC17_40_NUSBHOST 0 /* No USB host controller */
# define LPC17_40_NUSBOTG 0 /* No USB OTG controller */
# define LPC17_40_NUSBDEV 1 /* One USB device controller */
# define LPC17_40_NCAN 1 /* One CAN controller */
# define LPC17_40_NI2S 0 /* No I2S modules */
# define LPC17_40_NDAC 0 /* No DAC module */
#elif defined(CONFIG_ARCH_CHIP_LPC1754)
# define LPC176x 1 /* LPC175/6 family */
# undef LPC178x_40xx /* Not LPC177/8 or LPC40xx family */
# define LPC17_40_FLASH_SIZE (128*1024) /* 128Kb */
# define LPC17_40_SRAM_SIZE (32*1024) /* 32Kb */
# define LPC17_40_CPUSRAM_SIZE (16*1024)
# define LPC17_40_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */
# undef LPC17_40_HAVE_BANK1 /* No AHB SRAM bank 1 */
# define LPC17_40_NETHCONTROLLERS 0 /* No Ethernet controller */
# define LPC17_40_NUSBHOST 1 /* One USB host controller */
# define LPC17_40_NUSBOTG 1 /* One USB OTG controller */
# define LPC17_40_NUSBDEV 1 /* One USB device controller */
# define LPC17_40_NCAN 1 /* One CAN controller */
# define LPC17_40_NI2S 0 /* No I2S modules */
# define LPC17_40_NDAC 1 /* One DAC module */
#elif defined(CONFIG_ARCH_CHIP_LPC1756)
# define LPC176x 1 /* LPC175/6 family */
# undef LPC178x_40xx /* Not LPC177/8 or LPC40xx family */
# define LPC17_40_FLASH_SIZE (256*1024) /* 256Kb */
# define LPC17_40_SRAM_SIZE (32*1024) /* 32Kb */
# define LPC17_40_CPUSRAM_SIZE (16*1024)
# define LPC17_40_HAVE_BANK0 1 /* No AHB SRAM bank 0 */
# undef LPC17_40_HAVE_BANK1 /* No AHB SRAM bank 1 */
# define LPC17_40_NETHCONTROLLERS 0 /* No Ethernet controller */
# define LPC17_40_NUSBHOST 1 /* One USB host controller */
# define LPC17_40_NUSBOTG 1 /* One USB OTG controller */
# define LPC17_40_NUSBDEV 1 /* One USB device controller */
# define LPC17_40_NCAN 2 /* Two CAN controllers */
# define LPC17_40_NI2S 1 /* One I2S module */
# define LPC17_40_NDAC 1 /* One DAC module */
#elif defined(CONFIG_ARCH_CHIP_LPC1758)
# define LPC176x 1 /* LPC175/6 family */
# undef LPC178x_40xx /* Not LPC177/8 or LPC40xx family */
# define LPC17_40_FLASH_SIZE (512*1024) /* 512Kb */
# define LPC17_40_SRAM_SIZE (64*1024) /* 64Kb */
# define LPC17_40_CPUSRAM_SIZE (32*1024)
# define LPC17_40_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */
# define LPC17_40_HAVE_BANK1 1 /* Have AHB SRAM bank 1 */
# define LPC17_40_NETHCONTROLLERS 1 /* One Ethernet controller */
# define LPC17_40_NUSBHOST 1 /* One USB host controller */
# define LPC17_40_NUSBOTG 1 /* One USB OTG controller */
# define LPC17_40_NUSBDEV 1 /* One USB device controller */
# define LPC17_40_NCAN 2 /* Two CAN controllers */
# define LPC17_40_NI2S 1 /* One I2S module */
# define LPC17_40_NDAC 1 /* One DAC module */
#elif defined(CONFIG_ARCH_CHIP_LPC1759)
# define LPC176x 1 /* LPC175/6 family */
# undef LPC178x_40xx /* Not LPC177/8 or LPC40xx family */
# define LPC17_40_FLASH_SIZE (512*1024) /* 512Kb */
# define LPC17_40_SRAM_SIZE (64*1024) /* 64Kb */
# define LPC17_40_CPUSRAM_SIZE (32*1024)
# define LPC17_40_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */
# define LPC17_40_HAVE_BANK1 1 /* Have AHB SRAM bank 1 */
# define LPC17_40_NETHCONTROLLERS 0 /* No Ethernet controller */
# define LPC17_40_NUSBHOST 1 /* One USB host controller */
# define LPC17_40_NUSBOTG 1 /* One USB OTG controller */
# define LPC17_40_NUSBDEV 1 /* One USB device controller */
# define LPC17_40_NCAN 2 /* Two CAN controllers */
# define LPC17_40_NI2S 1 /* One I2S module */
# define LPC17_40_NDAC 1 /* One DAC module */
#elif defined(CONFIG_ARCH_CHIP_LPC1764)
# define LPC176x 1 /* LPC175/6 family */
# undef LPC178x_40xx /* Not LPC177/8 or LPC40xx family */
# define LPC17_40_FLASH_SIZE (128*1024) /* 128Kb */
# define LPC17_40_SRAM_SIZE (32*1024) /* 32Kb */
# define LPC17_40_CPUSRAM_SIZE (16*1024)
# define LPC17_40_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */
# undef LPC17_40_HAVE_BANK1 /* No AHB SRAM bank 1 */
# define LPC17_40_NETHCONTROLLERS 1 /* One Ethernet controller */
# define LPC17_40_NUSBHOST 0 /* No USB host controller */
# define LPC17_40_NUSBOTG 0 /* No USB OTG controller */
# define LPC17_40_NUSBDEV 1 /* One USB device controller */
# define LPC17_40_NCAN 2 /* Two CAN controllers */
# define LPC17_40_NI2S 0 /* No I2S modules */
# define LPC17_40_NDAC 0 /* No DAC module */
#elif defined(CONFIG_ARCH_CHIP_LPC1765)
# define LPC176x 1 /* LPC175/6 family */
# undef LPC178x_40xx /* Not LPC177/8 or LPC40xx family */
# define LPC17_40_FLASH_SIZE (256*1024) /* 256Kb */
# define LPC17_40_SRAM_SIZE (64*1024) /* 64Kb */
# define LPC17_40_CPUSRAM_SIZE (32*1024)
# define LPC17_40_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */
# define LPC17_40_HAVE_BANK1 1 /* Have AHB SRAM bank 1 */
# define LPC17_40_NETHCONTROLLERS 0 /* No Ethernet controller */
# define LPC17_40_NUSBHOST 1 /* One USB host controller */
# define LPC17_40_NUSBOTG 1 /* One USB OTG controller */
# define LPC17_40_NUSBDEV 1 /* One USB device controller */
# define LPC17_40_NCAN 2 /* Two CAN controllers */
# define LPC17_40_NI2S 1 /* One I2S module */
# define LPC17_40_NDAC 1 /* One DAC module */
#elif defined(CONFIG_ARCH_CHIP_LPC1766)
# define LPC176x 1 /* LPC175/6 family */
# undef LPC178x_40xx /* Not LPC177/8 or LPC40xx family */
# define LPC17_40_FLASH_SIZE (256*1024) /* 256Kb */
# define LPC17_40_SRAM_SIZE (64*1024) /* 64Kb */
# define LPC17_40_CPUSRAM_SIZE (32*1024)
# define LPC17_40_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */
# define LPC17_40_HAVE_BANK1 1 /* Have AHB SRAM bank 1 */
# define LPC17_40_NETHCONTROLLERS 1 /* One Ethernet controller */
# define LPC17_40_NUSBHOST 1 /* One USB host controller */
# define LPC17_40_NUSBOTG 1 /* One USB OTG controller */
# define LPC17_40_NUSBDEV 1 /* One USB device controller */
# define LPC17_40_NCAN 2 /* Two CAN controllers */
# define LPC17_40_NI2S 1 /* One I2S module */
# define LPC17_40_NDAC 1 /* One DAC module */
#elif defined(CONFIG_ARCH_CHIP_LPC1767)
# define LPC176x 1 /* LPC175/6 family */
# undef LPC178x_40xx /* Not LPC177/8 or LPC40xx family */
# define LPC17_40_FLASH_SIZE (512*1024) /* 512Kb */
# define LPC17_40_SRAM_SIZE (64*1024) /* 64Kb */
# define LPC17_40_CPUSRAM_SIZE (32*1024)
# define LPC17_40_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */
# define LPC17_40_HAVE_BANK1 1 /* Have AHB SRAM bank 1 */
# define LPC17_40_NETHCONTROLLERS 1 /* One Ethernet controller */
# define LPC17_40_NUSBHOST 0 /* No USB host controller */
# define LPC17_40_NUSBOTG 0 /* No USB OTG controller */
# define LPC17_40_NUSBDEV 0 /* No USB device controller */
# define LPC17_40_NCAN 0 /* No CAN controllers */
# define LPC17_40_NI2S 1 /* One I2S module */
# define LPC17_40_NDAC 1 /* One DAC module */
#elif defined(CONFIG_ARCH_CHIP_LPC1769) || defined(CONFIG_ARCH_CHIP_LPC1768)
# define LPC176x 1 /* LPC175/6 family */
# undef LPC178x_40xx /* Not LPC177/8 or LPC40xx family */
# define LPC17_40_FLASH_SIZE (512*1024) /* 512Kb */
# define LPC17_40_SRAM_SIZE (64*1024) /* 64Kb */
# define LPC17_40_CPUSRAM_SIZE (32*1024)
# define LPC17_40_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */
# define LPC17_40_HAVE_BANK1 1 /* Have AHB SRAM bank 1 */
# define LPC17_40_NETHCONTROLLERS 1 /* One Ethernet controller */
# define LPC17_40_NUSBHOST 1 /* One USB host controller */
# define LPC17_40_NUSBOTG 1 /* One USB OTG controller */
# define LPC17_40_NUSBDEV 1 /* One USB device controller */
# define LPC17_40_NCAN 2 /* Two CAN controllers */
# define LPC17_40_NI2S 1 /* One I2S module */
# define LPC17_40_NDAC 1 /* One DAC module */
#elif defined(CONFIG_ARCH_CHIP_LPC1773)
# undef LPC176x /* Not LPC175/6 family */
# define LPC178x_40xx 1 /* LPC177/8 or LPC40xx family */
# define LPC17_40_FLASH_SIZE (128*1024) /* 128Kb */
# define LPC17_40_SRAM_SIZE (40*1024) /* 40Kb */
# define LPC17_40_CPUSRAM_SIZE (32*1024)
# define LPC17_40_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0 */
# undef LPC17_40_HAVE_BANK1 /* No Peripheral SRAM bank 1 */
# define LPC17_40_NETHCONTROLLERS 1 /* One Ethernet controller */
# undef LPC17_40_NUSBHOST /* No USB host controller */
# undef LPC17_40_NUSBOTG /* No USB OTG controller */
# define LPC17_40_NUSBDEV 1 /* One USB device controller */
# define LPC17_40_HAVE_SPIFI 1 /* Have SPIFI interface */
# undef LPC17_40_HAVE_LCD /* No LCD controller */
# undef LPC17_40_HAVE_QEI /* No QEI interface */
# undef LPC17_40_HAVE_SD /* No SD controller */
#elif defined(CONFIG_ARCH_CHIP_LPC1774)
# undef LPC176x /* Not LPC175/6 family */
# define LPC178x_40xx 1 /* LPC177/8 or LPC40xx family */
# define LPC17_40_FLASH_SIZE (128*1024) /* 128Kb */
# define LPC17_40_SRAM_SIZE (40*1024) /* 40Kb */
# define LPC17_40_CPUSRAM_SIZE (32*1024)
# define LPC17_40_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0*/
# undef LPC17_40_HAVE_BANK1 /* Have Peripheral SRAM bank 1 */
# define LPC17_40_NETHCONTROLLERS 1 /* One Ethernet controller */
# undef LPC17_40_NUSBHOST /* One USB host controller */
# undef LPC17_40_NUSBOTG /* One USB OTG controller */
# define LPC17_40_NUSBDEV 1 /* One USB device controller */
# undef LPC17_40_HAVE_SPIFI /* Have SPIFI interface */
# undef LPC17_40_HAVE_LCD /* No LCD controller */
# define LPC17_40_HAVE_QEI 1 /* One QEI interface */
# define LPC17_40_HAVE_SD 1 /* One SD controller */
#elif defined(CONFIG_ARCH_CHIP_LPC1776)
# undef LPC176x /* Not LPC175/6 family */
# define LPC178x_40xx 1 /* LPC177/8 or LPC40xx family */
# define LPC17_40_FLASH_SIZE (256*1024) /* 256Kb */
# define LPC17_40_SRAM_SIZE (80*1024) /* 80Kb */
# define LPC17_40_CPUSRAM_SIZE (64*1024)
# define LPC17_40_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0 */
# undef LPC17_40_HAVE_BANK1 /* Have Peripheral SRAM bank 1 */
# define LPC17_40_NETHCONTROLLERS 1 /* One Ethernet controller */
# define LPC17_40_NUSBHOST 1 /* One USB host controller */
# define LPC17_40_NUSBOTG 1 /* One USB OTG controller */
# define LPC17_40_NUSBDEV 1 /* One USB device controller */
# undef LPC17_40_HAVE_SPIFI /* Have SPIFI interface */
# undef LPC17_40_HAVE_LCD /* No LCD controller */
# define LPC17_40_HAVE_QEI 1 /* One QEI interface */
# define LPC17_40_HAVE_SD 1 /* One SD controller */
#elif defined(CONFIG_ARCH_CHIP_LPC1777)
# undef LPC176x /* Not LPC175/6 family */
# define LPC178x_40xx 1 /* LPC177/8 or LPC40xx family */
# define LPC17_40_FLASH_SIZE (512*1024) /* 512Kb */
# define LPC17_40_SRAM_SIZE (96*1024) /* 96Kb */
# define LPC17_40_CPUSRAM_SIZE (64*1024)
# define LPC17_40_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0 */
# define LPC17_40_HAVE_BANK1 1 /* Have Peripheral SRAM bank 1 */
# undef LPC17_40_NETHCONTROLLERS /* No Ethernet controller */
# define LPC17_40_NUSBHOST 1 /* One USB host controller */
# define LPC17_40_NUSBOTG 1 /* One USB OTG controller */
# define LPC17_40_NUSBDEV 1 /* One USB device controller */
# undef LPC17_40_HAVE_SPIFI /* Have SPIFI interface */
# undef LPC17_40_HAVE_LCD /* No LCD controller */
# define LPC17_40_HAVE_QEI 1 /* One QEI interface */
# define LPC17_40_HAVE_SD 1 /* One SD controller */
#elif defined(CONFIG_ARCH_CHIP_LPC1778)
# undef LPC176x /* Not LPC175/6 family */
# define LPC178x_40xx 1 /* LPC177/8 or LPC40xx family */
# define LPC17_40_FLASH_SIZE (512*1024) /* 512Kb */
# define LPC17_40_SRAM_SIZE (96*1024) /* 64Kb */
# define LPC17_40_CPUSRAM_SIZE (64*1024)
# define LPC17_40_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0 */
# define LPC17_40_HAVE_BANK1 1 /* Have Peripheral SRAM bank 1 */
# define LPC17_40_NETHCONTROLLERS 1 /* One Ethernet controller */
# define LPC17_40_NUSBHOST 1 /* One USB host controller */
# define LPC17_40_NUSBOTG 1 /* One USB OTG controller */
# define LPC17_40_NUSBDEV 1 /* One USB device controller */
# undef LPC17_40_HAVE_SPIFI /* Have SPIFI interface */
# undef LPC17_40_HAVE_LCD /* No LCD controller */
# define LPC17_40_HAVE_QEI 1 /* One QEI interface */
# define LPC17_40_HAVE_SD 1 /* One SD controller */
#elif defined(CONFIG_ARCH_CHIP_LPC1785)
# undef LPC176x /* Not LPC175/6 family */
# define LPC178x_40xx 1 /* LPC177/8 or LPC40xx family */
# define LPC17_40_FLASH_SIZE (256*1024) /* 256Kb */
# define LPC17_40_SRAM_SIZE (80*1024) /* 80Kb */
# define LPC17_40_CPUSRAM_SIZE (64*1024)
# define LPC17_40_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0 */
# undef LPC17_40_HAVE_BANK1 /* Have Peripheral SRAM bank 1 */
# undef LPC17_40_NETHCONTROLLERS /* No Ethernet controller */
# define LPC17_40_NUSBHOST 1 /* One USB host controller */
# define LPC17_40_NUSBOTG 1 /* One USB OTG controller */
# define LPC17_40_NUSBDEV 1 /* One USB device controller */
# undef LPC17_40_HAVE_SPIFI /* Have SPIFI interface */
# define LPC17_40_HAVE_LCD 1 /* One LCD controller */
# undef LPC17_40_HAVE_QEI /* One QEI interface */
# define LPC17_40_HAVE_SD 1 /* One SD controller */
#elif defined(CONFIG_ARCH_CHIP_LPC1786)
# undef LPC176x /* Not LPC175/6 family */
# define LPC178x_40xx 1 /* LPC177/8 or LPC40xx family */
# define LPC17_40_FLASH_SIZE (256*1024) /* 256Kb */
# define LPC17_40_SRAM_SIZE (80*1024) /* 80Kb */
# define LPC17_40_CPUSRAM_SIZE (64*1024)
# define LPC17_40_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0 */
# undef LPC17_40_HAVE_BANK1 /* Have Peripheral SRAM bank 1 */
# define LPC17_40_NETHCONTROLLERS 1 /* One Ethernet controller */
# define LPC17_40_NUSBHOST 1 /* One USB host controller */
# define LPC17_40_NUSBOTG 1 /* One USB OTG controller */
# define LPC17_40_NUSBDEV 1 /* One USB device controller */
# undef LPC17_40_HAVE_SPIFI /* Have SPIFI interface */
# define LPC17_40_HAVE_LCD 1 /* One LCD controller */
# define LPC17_40_HAVE_QEI 1 /* One QEI interface */
# define LPC17_40_HAVE_SD 1 /* One SD controller */
#elif defined(CONFIG_ARCH_CHIP_LPC1787)
# undef LPC176x /* Not LPC175/6 family */
# define LPC178x_40xx 1 /* LPC177/8 or LPC40xx family */
# define LPC17_40_FLASH_SIZE (512*1024) /* 512Kb */
# define LPC17_40_SRAM_SIZE (96*1024) /* 96Kb */
# define LPC17_40_CPUSRAM_SIZE (64*1024)
# define LPC17_40_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0 */
# define LPC17_40_HAVE_BANK1 1 /* Have Peripheral SRAM bank 1 */
# undef LPC17_40_NETHCONTROLLERS /* No Ethernet controller */
# define LPC17_40_NUSBHOST 1 /* One USB host controller */
# define LPC17_40_NUSBOTG 1 /* One USB OTG controller */
# define LPC17_40_NUSBDEV 1 /* One USB device controller */
# undef LPC17_40_HAVE_SPIFI /* Have SPIFI interface */
# define LPC17_40_HAVE_LCD 1 /* One LCD controller */
# define LPC17_40_HAVE_QEI 1 /* One QEI interface */
# define LPC17_40_HAVE_SD 1 /* One SD controller */
#elif defined(CONFIG_ARCH_CHIP_LPC1788)
# undef LPC176x /* Not LPC175/6 family */
# define LPC178x_40xx 1 /* LPC177/8 or LPC40xx family */
# define LPC17_40_FLASH_SIZE (512*1024) /* 512Kb */
# define LPC17_40_SRAM_SIZE (96*1024) /* 96Kb */
# define LPC17_40_CPUSRAM_SIZE (64*1024)
# define LPC17_40_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0 */
# define LPC17_40_HAVE_BANK1 1 /* Have Peripheral SRAM bank 1 */
# define LPC17_40_NETHCONTROLLERS 1 /* One Ethernet controller */
# define LPC17_40_NUSBHOST 1 /* One USB host controller */
# define LPC17_40_NUSBOTG 1 /* One USB OTG controller */
# define LPC17_40_NUSBDEV 1 /* One USB device controller */
# undef LPC17_40_HAVE_SPIFI /* Have SPIFI interface */
# define LPC17_40_HAVE_LCD 1 /* One LCD controller */
# define LPC17_40_HAVE_QEI 1 /* One QEI interface */
# define LPC17_40_HAVE_SD 1 /* One SD controller */
#elif defined(CONFIG_ARCH_CHIP_LPC4072)
# undef LPC176x /* Not LPC175/6 family */
# define LPC178x_40xx 1 /* LPC177/8 or LPC40xx family */
# define LPC17_40_FLASH_SIZE (64*1024) /* 64Kb */
# define LPC17_40_SRAM_SIZE (24*1024) /* 24Kb */
# define LPC17_40_CPUSRAM_SIZE (16*1024)
# define LPC17_40_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0 */
# undef LPC17_40_HAVE_BANK1 /* No Peripheral SRAM bank 1 */
# undef LPC17_40_NETHCONTROLLERS /* No Ethernet controller */
# undef LPC17_40_NUSBHOST /* No USB host controller */
# undef LPC17_40_NUSBOTG /* No USB OTG controller */
# define LPC17_40_NUSBDEV 1 /* One USB device controller */
# define LPC17_40_HAVE_SPIFI 1 /* Have SPIFI interface */
# undef LPC17_40_HAVE_LCD /* No LCD controller */
# undef LPC17_40_HAVE_QEI /* No QEI interface */
# undef LPC17_40_HAVE_SD /* No SD controller */
#elif defined(CONFIG_ARCH_CHIP_LPC4074)
# undef LPC176x /* Not LPC175/6 family */
# define LPC178x_40xx 1 /* LPC177/8 or LPC40xx family */
# define LPC17_40_FLASH_SIZE (128*1024) /* 128Kb */
# define LPC17_40_SRAM_SIZE (40*1024) /* 40Kb */
# define LPC17_40_CPUSRAM_SIZE (32*1024)
# define LPC17_40_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0*/
# undef LPC17_40_HAVE_BANK1 /* Have Peripheral SRAM bank 1 */
# undef LPC17_40_NETHCONTROLLERS 0 /* No Ethernet controller */
# undef LPC17_40_NUSBHOST /* No USB host controller */
# undef LPC17_40_NUSBOTG /* No USB OTG controller */
# define LPC17_40_NUSBDEV 1 /* One USB device controller */
# define LPC17_40_HAVE_SPIFI 1 /* Have SPIFI interface */
# undef LPC17_40_HAVE_LCD /* One LCD controller */
# undef LPC17_40_HAVE_QEI /* No QEI interface */
# undef LPC17_40_HAVE_SD /* No SD controller */
#elif defined(CONFIG_ARCH_CHIP_LPC4076)
# undef LPC176x /* Not LPC175/6 family */
# define LPC178x_40xx 1 /* LPC177/8 or LPC40xx family */
# define LPC17_40_FLASH_SIZE (256*1024) /* 256Kb */
# define LPC17_40_SRAM_SIZE (80*1024) /* 80Kb */
# define LPC17_40_CPUSRAM_SIZE (64*1024)
# define LPC17_40_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0 */
# undef LPC17_40_HAVE_BANK1 /* Have Peripheral SRAM bank 1 */
# define LPC17_40_NETHCONTROLLERS 1 /* One Ethernet controller */
# define LPC17_40_NUSBHOST 1 /* One USB host controller */
# define LPC17_40_NUSBOTG 1 /* One USB OTG controller */
# define LPC17_40_NUSBDEV 1 /* One USB device controller */
# define LPC17_40_HAVE_SPIFI 1 /* Have SPIFI interface */
# undef LPC17_40_HAVE_LCD /* No LCD controller */
# define LPC17_40_HAVE_QEI 1 /* One QEI interface */
# define LPC17_40_HAVE_SD 1 /* One SD controller */
#elif defined(CONFIG_ARCH_CHIP_LPC4078)
# undef LPC176x /* Not LPC175/6 family */
# define LPC178x_40xx 1 /* LPC177/8 or LPC40xx family */
# define LPC17_40_FLASH_SIZE (512*1024) /* 512Kb */
# define LPC17_40_SRAM_SIZE (96*1024) /* 96Kb */
# define LPC17_40_CPUSRAM_SIZE (64*1024)
# define LPC17_40_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0 */
# define LPC17_40_HAVE_BANK1 1 /* Have Peripheral SRAM bank 1 */
# define LPC17_40_NETHCONTROLLERS 1 /* One Ethernet controller */
# define LPC17_40_NUSBHOST 1 /* One USB host controller */
# define LPC17_40_NUSBOTG 1 /* One USB OTG controller */
# define LPC17_40_NUSBDEV 1 /* One USB device controller */
# define LPC17_40_HAVE_SPIFI 1 /* Have SPIFI interface */
# undef LPC17_40_HAVE_LCD /* No LCD controller */
# define LPC17_40_HAVE_QEI 1 /* One QEI interface */
# define LPC17_40_HAVE_SD 1 /* One SD controller */
#elif defined(CONFIG_ARCH_CHIP_LPC4088)
# undef LPC176x /* Not LPC175/6 family */
# define LPC178x_40xx 1 /* LPC177/8 or LPC40xx family */
# define LPC17_40_FLASH_SIZE (512*1024) /* 512Kb */
# define LPC17_40_SRAM_SIZE (96*1024) /* 64Kb */
# define LPC17_40_CPUSRAM_SIZE (64*1024)
# define LPC17_40_HAVE_BANK0 1 /* Have Peripheral SRAM bank 0 */
# define LPC17_40_HAVE_BANK1 1 /* Have Peripheral SRAM bank 1 */
# define LPC17_40_NETHCONTROLLERS 1 /* One Ethernet controller */
# define LPC17_40_NUSBHOST 1 /* One USB host controller */
# define LPC17_40_NUSBOTG 1 /* One USB OTG controller */
# define LPC17_40_NUSBDEV 1 /* One USB device controller */
# define LPC17_40_HAVE_SPIFI 1 /* Have SPIFI interface */
# define LPC17_40_HAVE_LCD 1 /* One LCD controller */
# define LPC17_40_HAVE_QEI 1 /* One QEI interface */
# define LPC17_40_HAVE_SD 1 /* One SD controller */
#else
# error "Unsupported LPC17xx/LPC40xx chip"
#endif
/* NVIC priority levels *************************************************************/
/* Each priority field holds a priority value, 0-31. The lower the value, the greater
* the priority of the corresponding interrupt. The processor implements only
* bits[7:3] of each field, bits[2:0] read as zero and ignore writes.
*/
#define NVIC_SYSH_PRIORITY_MIN 0xf8 /* All bits[7:3] set is minimum priority */
#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */
#define NVIC_SYSH_PRIORITY_STEP 0x08 /* Five bits of interrupt priority used */
/************************************************************************************
* Public Types
************************************************************************************/
/************************************************************************************
* Public Data
************************************************************************************/
/************************************************************************************
* Public Functions
************************************************************************************/
#endif /* __ARCH_ARM_INCLUDE_LPC17XX_40XX_CHIP_H */

46
arch/arm/include/lpc17xx/irq.h → arch/arm/include/lpc17xx_40xx/irq.h
View file

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/include/lpc17xxx/irq.h
* arch/arm/include/lpc17xx_40xxx/irq.h
*
* Copyright (C) 2010-2011, 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@ -37,8 +37,8 @@
* through nuttx/irq.h
*/
#ifndef __ARCH_ARM_INCLUDE_LPC17XX_IRQ_H
#define __ARCH_ARM_INCLUDE_LPC17XX_IRQ_H
#ifndef __ARCH_ARM_INCLUDE_LPC17XX_40XX_IRQ_H
#define __ARCH_ARM_INCLUDE_LPC17XX_40XX_IRQ_H
/****************************************************************************
* Included Files
@ -47,7 +47,7 @@
#ifndef __ASSEMBLY__
# include <stdint.h>
#endif
#include <arch/lpc17xx/chip.h>
#include <arch/lpc17xx_40xx/chip.h>
/****************************************************************************
* Pre-processor Definitions
@ -59,32 +59,32 @@
/* Common Processor Exceptions (vectors 0-15) */
#define LPC17_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */
/* Vector 0: Reset stack pointer value */
/* Vector 1: Reset (not handler as an IRQ) */
#define LPC17_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */
#define LPC17_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */
#define LPC17_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */
#define LPC17_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */
#define LPC17_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */
#define LPC17_IRQ_SVCALL (11) /* Vector 11: SVC call */
#define LPC17_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */
/* Vector 13: Reserved */
#define LPC17_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */
#define LPC17_IRQ_SYSTICK (15) /* Vector 15: System tick */
#define LPC17_40_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */
/* Vector 0: Reset stack pointer value */
/* Vector 1: Reset (not handler as an IRQ) */
#define LPC17_40_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */
#define LPC17_40_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */
#define LPC17_40_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */
#define LPC17_40_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */
#define LPC17_40_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */
#define LPC17_40_IRQ_SVCALL (11) /* Vector 11: SVC call */
#define LPC17_40_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */
/* Vector 13: Reserved */
#define LPC17_40_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */
#define LPC17_40_IRQ_SYSTICK (15) /* Vector 15: System tick */
/* External interrupts (vectors >= 16) */
#define LPC17_IRQ_EXTINT (16) /* Vector number of the first external interrupt */
#define LPC17_40_IRQ_EXTINT (16) /* Vector number of the first external interrupt */
/* Family Specfic Interrupts */
#if defined(LPC176x) /* LPC175/6 family */
# include <arch/lpc17xx/lpc176x_irq.h>
#elif defined(LPC178x) /* LPC177/8 family */
# include <arch/lpc17xx/lpc178x_irq.h>
# include <arch/lpc17xx_40xx/lpc176x_irq.h>
#elif defined(LPC178x_40xx) /* LPC177/8 or LPC40xx family */
# include <arch/lpc17xx_40xx/lpc178x_40xx_irq.h>
#else
# error "Unknown LPC17xx family"
# error "Unknown LPC17xx/LPC40xx family"
#endif
/****************************************************************************
@ -116,4 +116,4 @@ extern "C"
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_INCLUDE_LPC17XX_IRQ_H */
#endif /* __ARCH_ARM_INCLUDE_LPC17XX_40XX_IRQ_H */

245
arch/arm/include/lpc17xx_40xx/lpc176x_irq.h Normal file
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@ -0,0 +1,245 @@
/****************************************************************************
* arch/lpc17xx_40xx/lpc176x_irq.h
*
* Copyright (C) 2010-2011, 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/* This file should never be included directed but, rather, only indirectly
* through nuttx/irq.h
*/
#ifndef __ARCH_ARM_INCLUDE_LPC17XX_40XX_LPC176X_IRQ_H
#define __ARCH_ARM_INCLUDE_LPC17XX_40XX_LPC176X_IRQ_H
/****************************************************************************
* Included Files
****************************************************************************/
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* IRQ numbers. The IRQ number corresponds vector number and hence map
* directly to bits in the NVIC. This does, however, waste several words of
* memory in the IRQ to handle mapping tables.
*/
/* External interrupts (vectors >= 16) */
#define LPC17_40_IRQ_WDT (LPC17_40_IRQ_EXTINT+0) /* WDT Watchdog Interrupt (WDINT) */
#define LPC17_40_IRQ_TMR0 (LPC17_40_IRQ_EXTINT+1) /* Timer 0 Match 0 - 1 (MR0, MR1)
* Capture 0 - 1 (CR0, CR1) */
#define LPC17_40_IRQ_TMR1 (LPC17_40_IRQ_EXTINT+2) /* Timer 1 Match 0 - 2 (MR0, MR1, MR2)
* Capture 0 - 1 (CR0, CR1) */
#define LPC17_40_IRQ_TMR2 (LPC17_40_IRQ_EXTINT+3) /* Timer 2 Match 0-3
* Capture 0-1 */
#define LPC17_40_IRQ_TMR3 (LPC17_40_IRQ_EXTINT+4) /* Timer 3 Match 0-3
* Capture 0-1 */
#define LPC17_40_IRQ_UART0 (LPC17_40_IRQ_EXTINT+5) /* UART 0 Rx Line Status (RLS)
* Transmit Holding Register Empty (THRE)
* Rx Data Available (RDA)
* Character Time-out Indicator (CTI)
* End of Auto-Baud (ABEO)
* Auto-Baud Time-Out (ABTO) */
#define LPC17_40_IRQ_UART1 (LPC17_40_IRQ_EXTINT+6) /* UART 1 Rx Line Status (RLS)
* Transmit Holding Register Empty (THRE)
* Rx Data Available (RDA)
* Character Time-out Indicator (CTI)
* Modem Control Change
* End of Auto-Baud (ABEO)
* Auto-Baud Time-Out (ABTO) */
#define LPC17_40_IRQ_UART2 (LPC17_40_IRQ_EXTINT+7) /* UART 2 Rx Line Status (RLS)
* Transmit Holding Register Empty (THRE)
* Rx Data Available (RDA)
* Character Time-out Indicator (CTI)
* End of Auto-Baud (ABEO)
* Auto-Baud Time-Out (ABTO) */
#define LPC17_40_IRQ_UART3 (LPC17_40_IRQ_EXTINT+8) /* UART 3 Rx Line Status (RLS)
* Transmit Holding Register Empty (THRE)
* Rx Data Available (RDA)
* Character Time-out Indicator (CTI)
* End of Auto-Baud (ABEO)
* Auto-Baud Time-Out (ABTO) */
#define LPC17_40_IRQ_PWM1 (LPC17_40_IRQ_EXTINT+9) /* PWM1 Match 0 - 6 of PWM1
* Capture 0-1 of PWM1 */
#define LPC17_40_IRQ_I2C0 (LPC17_40_IRQ_EXTINT+10) /* I2C0 SI (state change) */
#define LPC17_40_IRQ_I2C1 (LPC17_40_IRQ_EXTINT+11) /* I2C1 SI (state change) */
#define LPC17_40_IRQ_I2C2 (LPC17_40_IRQ_EXTINT+12) /* I2C2 SI (state change) */
#define LPC17_40_IRQ_SPIF (LPC17_40_IRQ_EXTINT+13) /* SPI SPI Interrupt Flag (SPIF)
* Mode Fault (MODF) */
#define LPC17_40_IRQ_SSP0 (LPC17_40_IRQ_EXTINT+14) /* SSP0 Tx FIFO half empty of SSP0
* Rx FIFO half full of SSP0
* Rx Timeout of SSP0
* Rx Overrun of SSP0 */
#define LPC17_40_IRQ_SSP1 (LPC17_40_IRQ_EXTINT+15) /* SSP 1 Tx FIFO half empty
* Rx FIFO half full
* Rx Timeout
* Rx Overrun */
#define LPC17_40_IRQ_PLL0 (LPC17_40_IRQ_EXTINT+16) /* PLL0 (Main PLL) PLL0 Lock (PLOCK0) */
#define LPC17_40_IRQ_RTC (LPC17_40_IRQ_EXTINT+17) /* RTC Counter Increment (RTCCIF)
* Alarm (RTCALF) */
#define LPC17_40_IRQ_EINT0 (LPC17_40_IRQ_EXTINT+18) /* External Interrupt 0 (EINT0) */
#define LPC17_40_IRQ_EINT1 (LPC17_40_IRQ_EXTINT+19) /* External Interrupt 1 (EINT1) */
#define LPC17_40_IRQ_EINT2 (LPC17_40_IRQ_EXTINT+20) /* External Interrupt 2 (EINT2) */
#define LPC17_40_IRQ_EINT3 (LPC17_40_IRQ_EXTINT+21) /* External Interrupt 3 (EINT3)
* Note: EINT3 channel is shared with GPIO interrupts */
#define LPC17_40_IRQ_ADC (LPC17_40_IRQ_EXTINT+22) /* ADC A/D Converter end of conversion */
#define LPC17_40_IRQ_BOD (LPC17_40_IRQ_EXTINT+23) /* BOD Brown Out detect */
#define LPC17_40_IRQ_USB (LPC17_40_IRQ_EXTINT+24) /* USB USB_INT_REQ_LP, USB_INT_REQ_HP,
* USB_INT_REQ_DMA */
#define LPC17_40_IRQ_CAN (LPC17_40_IRQ_EXTINT+25) /* CAN CAN Common, CAN 0 Tx, CAN 0 Rx,
* CAN 1 Tx, CAN 1 Rx */
#define LPC17_40_IRQ_GPDMA (LPC17_40_IRQ_EXTINT+26) /* GPDMA IntStatus of DMA channel 0,
* IntStatus of DMA channel 1 */
#define LPC17_40_IRQ_I2S (LPC17_40_IRQ_EXTINT+27) /* I2S irq, dmareq1, dmareq2 */
#define LPC17_40_IRQ_ETH (LPC17_40_IRQ_EXTINT+28) /* Ethernet WakeupInt, SoftInt, TxDoneInt,
* TxFinishedInt, TxErrorInt,* TxUnderrunInt,
* RxDoneInt, RxFinishedInt, RxErrorInt,
* RxOverrunInt */
#define LPC17_40_IRQ_RITINT (LPC17_40_IRQ_EXTINT+29) /* Repetitive Interrupt Timer (RITINT) */
#define LPC17_40_IRQ_MCPWM (LPC17_40_IRQ_EXTINT+30) /* Motor Control PWM IPER[2:0], IPW[2:0],
* ICAP[2:0], FES */
#define LPC17_40_IRQ_QEI (LPC17_40_IRQ_EXTINT+31) /* Quadrature Encoder INX_Int, TIM_Int, VELC_Int,
* DIR_Int, ERR_Int, ENCLK_Int, POS0_Int, POS1_Int
* POS2_Int, REV_Int, POS0REV_Int, OS1REV_Int,
* POS2REV_Int */
#define LPC17_40_IRQ_PLL1 (LPC17_40_IRQ_EXTINT+32) /* PLL1 (USB PLL) PLL1 Lock (PLOCK1) */
#define LPC17_40_IRQ_USBACT (LPC17_40_IRQ_EXTINT+33) /* USB Activity Interrupt USB_NEED_CLK */
#define LPC17_40_IRQ_CANACT (LPC17_40_IRQ_EXTINT+34) /* CAN Activity Interrupt CAN1WAKE, CAN2WAKE */
#define LPC17_40_IRQ_NEXTINT (35)
#define LPC17_40_IRQ_NIRQS (LPC17_40_IRQ_EXTINT+LPC17_40_IRQ_NEXTINT)
/* GPIO interrupts. The LPC17xx/LPC40xx supports several interrupts on ports 0 and
* 2 (only). We go through some special efforts to keep the number of IRQs
* to a minimum in this sparse interrupt case.
*
* 28 interrupts on Port 0: p0.0 - p0.11, p0.15-p0.30
* 14 interrupts on Port 2: p2.0 - p2.13
* --
* 42
*/
#ifdef CONFIG_LPC17_40_GPIOIRQ
# define LPC17_40_VALID_GPIOINT0 (0x7fff8ffful) /* GPIO port 0 interrupt set */
# define LPC17_40_VALID_GPIOINT2 (0x00003ffful) /* GPIO port 2 interrupt set */
/* Set 1: 12 interrupts p0.0-p0.11 */
# define LPC17_40_VALID_GPIOINT0L (0x00000ffful)
# define LPC17_40_VALID_SHIFT0L (0)
# define LPC17_40_VALID_FIRST0L (LPC17_40_IRQ_EXTINT+LPC17_40_IRQ_NEXTINT)
# define LPC17_40_IRQ_P0p0 (LPC17_40_VALID_FIRST0L+0)
# define LPC17_40_IRQ_P0p1 (LPC17_40_VALID_FIRST0L+1)
# define LPC17_40_IRQ_P0p2 (LPC17_40_VALID_FIRST0L+2)
# define LPC17_40_IRQ_P0p3 (LPC17_40_VALID_FIRST0L+3)
# define LPC17_40_IRQ_P0p4 (LPC17_40_VALID_FIRST0L+4)
# define LPC17_40_IRQ_P0p5 (LPC17_40_VALID_FIRST0L+5)
# define LPC17_40_IRQ_P0p6 (LPC17_40_VALID_FIRST0L+6)
# define LPC17_40_IRQ_P0p7 (LPC17_40_VALID_FIRST0L+7)
# define LPC17_40_IRQ_P0p8 (LPC17_40_VALID_FIRST0L+8)
# define LPC17_40_IRQ_P0p9 (LPC17_40_VALID_FIRST0L+9)
# define LPC17_40_IRQ_P0p10 (LPC17_40_VALID_FIRST0L+10)
# define LPC17_40_IRQ_P0p11 (LPC17_40_VALID_FIRST0L+11)
# define LPC17_40_VALID_NIRQS0L (12)
/* Set 2: 16 interrupts p0.15-p0.30 */
# define LPC17_40_VALID_GPIOINT0H (0x7fff8000ull)
# define LPC17_40_VALID_SHIFT0H (15)
# define LPC17_40_VALID_FIRST0H (LPC17_40_VALID_FIRST0L+LPC17_40_VALID_NIRQS0L)
# define LPC17_40_IRQ_P0p15 (LPC17_40_VALID_FIRST0H+0)
# define LPC17_40_IRQ_P0p16 (LPC17_40_VALID_FIRST0H+1)
# define LPC17_40_IRQ_P0p17 (LPC17_40_VALID_FIRST0H+2)
# define LPC17_40_IRQ_P0p18 (LPC17_40_VALID_FIRST0H+3)
# define LPC17_40_IRQ_P0p19 (LPC17_40_VALID_FIRST0H+4)
# define LPC17_40_IRQ_P0p20 (LPC17_40_VALID_FIRST0H+5)
# define LPC17_40_IRQ_P0p21 (LPC17_40_VALID_FIRST0H+6)
# define LPC17_40_IRQ_P0p22 (LPC17_40_VALID_FIRST0H+7)
# define LPC17_40_IRQ_P0p23 (LPC17_40_VALID_FIRST0H+8)
# define LPC17_40_IRQ_P0p24 (LPC17_40_VALID_FIRST0H+9)
# define LPC17_40_IRQ_P0p25 (LPC17_40_VALID_FIRST0H+10)
# define LPC17_40_IRQ_P0p26 (LPC17_40_VALID_FIRST0H+11)
# define LPC17_40_IRQ_P0p27 (LPC17_40_VALID_FIRST0H+12)
# define LPC17_40_IRQ_P0p28 (LPC17_40_VALID_FIRST0H+13)
# define LPC17_40_IRQ_P0p29 (LPC17_40_VALID_FIRST0H+14)
# define LPC17_40_IRQ_P0p30 (LPC17_40_VALID_FIRST0H+15)
# define LPC17_40_VALID_NIRQS0H (16)
/* Set 3: 14 interrupts p2.0-p2.13 */
# define LPC17_40_VALID_GPIOINT2 (0x00003ffful)
# define LPC17_40_VALID_SHIFT2 (0)
# define LPC17_40_VALID_FIRST2 (LPC17_40_VALID_FIRST0H+LPC17_40_VALID_NIRQS0H)
# define LPC17_40_IRQ_P2p0 (LPC17_40_VALID_FIRST2+0)
# define LPC17_40_IRQ_P2p1 (LPC17_40_VALID_FIRST2+1)
# define LPC17_40_IRQ_P2p2 (LPC17_40_VALID_FIRST2+2)
# define LPC17_40_IRQ_P2p3 (LPC17_40_VALID_FIRST2+3)
# define LPC17_40_IRQ_P2p4 (LPC17_40_VALID_FIRST2+4)
# define LPC17_40_IRQ_P2p5 (LPC17_40_VALID_FIRST2+5)
# define LPC17_40_IRQ_P2p6 (LPC17_40_VALID_FIRST2+6)
# define LPC17_40_IRQ_P2p7 (LPC17_40_VALID_FIRST2+7)
# define LPC17_40_IRQ_P2p8 (LPC17_40_VALID_FIRST2+8)
# define LPC17_40_IRQ_P2p9 (LPC17_40_VALID_FIRST2+9)
# define LPC17_40_IRQ_P2p10 (LPC17_40_VALID_FIRST2+10)
# define LPC17_40_IRQ_P2p11 (LPC17_40_VALID_FIRST2+11)
# define LPC17_40_IRQ_P2p12 (LPC17_40_VALID_FIRST2+12)
# define LPC17_40_IRQ_P2p13 (LPC17_40_VALID_FIRST2+13)
# define LPC17_40_VALID_NIRQS2 (14)
# define LPC17_40_NGPIOAIRQS (LPC17_40_VALID_NIRQS0L+LPC17_40_VALID_NIRQS0H+LPC17_40_VALID_NIRQS2)
#else
# define LPC17_40_NGPIOAIRQS (0)
#endif
/* Total number of IRQ numbers */
#define NR_IRQS (LPC17_40_IRQ_EXTINT+LPC17_40_IRQ_NEXTINT+LPC17_40_NGPIOAIRQS)
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Inline functions
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_INCLUDE_LPC17XX_40XX_LPC176X_IRQ_H */

291
arch/arm/include/lpc17xx_40xx/lpc178x_40xx_irq.h Normal file
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@ -0,0 +1,291 @@
/****************************************************************************
* arch/arm/include/lpc17xx_40xxx/lpc178x_40xx_irq.h
*
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
* Authors: Rommel Marcelo
* Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
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****************************************************************************/
/* This file should never be included directed but, rather,
* only indirectly through nuttx/irq.h
*/
#ifndef __ARCH_ARM_INCLUDE_LPC17XX_40XX_LPC178X_IRQ_H
#define __ARCH_ARM_INCLUDE_LPC17XX_40XX_LPC178X_IRQ_H
/****************************************************************************
* Included Files
****************************************************************************/
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* IRQ numbers. The IRQ number corresponds vector number and hence map
* directly to bits in the NVIC. This does, however, waste several words of
* memory in the IRQ to handle mapping tables.
*/
/* External interrupts (vectors >= 16) */
#define LPC17_40_IRQ_WDT (LPC17_40_IRQ_EXTINT+0) /* WDT Watchdog Interrupt (WDINT) */
#define LPC17_40_IRQ_TMR0 (LPC17_40_IRQ_EXTINT+1) /* Timer 0 Match 0 - 1 (MR0, MR1)
* Capture 0 - 1 (CR0, CR1) */
#define LPC17_40_IRQ_TMR1 (LPC17_40_IRQ_EXTINT+2) /* Timer 1 Match 0 - 2 (MR0, MR1, MR2)
* Capture 0 - 1 (CR0, CR1) */
#define LPC17_40_IRQ_TMR2 (LPC17_40_IRQ_EXTINT+3) /* Timer 2 Match 0-3
* Capture 0-1 */
#define LPC17_40_IRQ_TMR3 (LPC17_40_IRQ_EXTINT+4) /* Timer 3 Match 0-3
* Capture 0-1 */
#define LPC17_40_IRQ_UART0 (LPC17_40_IRQ_EXTINT+5) /* UART 0 Rx Line Status (RLS)
* Transmit Holding Register Empty (THRE)
* Rx Data Available (RDA)
* Character Time-out Indicator (CTI)
* End of Auto-Baud (ABEO)
* Auto-Baud Time-Out (ABTO) */
#define LPC17_40_IRQ_UART1 (LPC17_40_IRQ_EXTINT+6) /* UART 1 Rx Line Status (RLS)
* Transmit Holding Register Empty (THRE)
* Rx Data Available (RDA)
* Character Time-out Indicator (CTI)
* Modem Control Change
* End of Auto-Baud (ABEO)
* Auto-Baud Time-Out (ABTO) */
#define LPC17_40_IRQ_UART2 (LPC17_40_IRQ_EXTINT+7) /* UART 2 Rx Line Status (RLS)
* Transmit Holding Register Empty (THRE)
* Rx Data Available (RDA)
* Character Time-out Indicator (CTI)
* End of Auto-Baud (ABEO)
* Auto-Baud Time-Out (ABTO) */
#define LPC17_40_IRQ_UART3 (LPC17_40_IRQ_EXTINT+8) /* UART 3 Rx Line Status (RLS)
* Transmit Holding Register Empty (THRE)
* Rx Data Available (RDA)
* Character Time-out Indicator (CTI)
* End of Auto-Baud (ABEO)
* Auto-Baud Time-Out (ABTO) */
#define LPC17_40_IRQ_PWM1 (LPC17_40_IRQ_EXTINT+9) /* PWM1 Match 0 - 6 of PWM1
* Capture 0-1 of PWM1 */
#define LPC17_40_IRQ_I2C0 (LPC17_40_IRQ_EXTINT+10) /* I2C0 SI (state change) */
#define LPC17_40_IRQ_I2C1 (LPC17_40_IRQ_EXTINT+11) /* I2C1 SI (state change) */
#define LPC17_40_IRQ_I2C2 (LPC17_40_IRQ_EXTINT+12) /* I2C2 SI (state change) */
#define LPC17_40_IRQ_RESERVED29 (LPC17_40_IRQ_EXTINT+13) /* Unused */
#define LPC17_40_IRQ_SSP0 (LPC17_40_IRQ_EXTINT+14) /* SSP0 Tx FIFO half empty of SSP0
* Rx FIFO half full of SSP0
* Rx Timeout of SSP0
* Rx Overrun of SSP0 */
#define LPC17_40_IRQ_SSP1 (LPC17_40_IRQ_EXTINT+15) /* SSP 1 Tx FIFO half empty
* Rx FIFO half full
* Rx Timeout
* Rx Overrun */
#define LPC17_40_IRQ_PLL0 (LPC17_40_IRQ_EXTINT+16) /* PLL0 (Main PLL) PLL0 Lock (PLOCK0) */
#define LPC17_40_IRQ_RTC (LPC17_40_IRQ_EXTINT+17) /* RTC Counter Increment (RTCCIF)
* Alarm (RTCALF) */
#define LPC17_40_IRQ_EINT0 (LPC17_40_IRQ_EXTINT+18) /* External Interrupt 0 (EINT0) */
#define LPC17_40_IRQ_EINT1 (LPC17_40_IRQ_EXTINT+19) /* External Interrupt 1 (EINT1) */
#define LPC17_40_IRQ_EINT2 (LPC17_40_IRQ_EXTINT+20) /* External Interrupt 2 (EINT2) */
#define LPC17_40_IRQ_EINT3 (LPC17_40_IRQ_EXTINT+21) /* External Interrupt 3 (EINT3)
* Note: EINT3 channel is shared with GPIO interrupts */
#define LPC17_40_IRQ_ADC (LPC17_40_IRQ_EXTINT+22) /* ADC A/D Converter end of conversion */
#define LPC17_40_IRQ_BOD (LPC17_40_IRQ_EXTINT+23) /* BOD Brown Out detect */
#define LPC17_40_IRQ_USB (LPC17_40_IRQ_EXTINT+24) /* USB USB_INT_REQ_LP, USB_INT_REQ_HP,
* USB_INT_REQ_DMA */
#define LPC17_40_IRQ_CAN (LPC17_40_IRQ_EXTINT+25) /* CAN CAN Common, CAN 0 Tx, CAN 0 Rx,
* CAN 1 Tx, CAN 1 Rx */
#define LPC17_40_IRQ_GPDMA (LPC17_40_IRQ_EXTINT+26) /* GPDMA IntStatus of DMA channel 0,
* IntStatus of DMA channel 1 */
#define LPC17_40_IRQ_I2S (LPC17_40_IRQ_EXTINT+27) /* I2S irq, dmareq1, dmareq2 */
#define LPC17_40_IRQ_ETH (LPC17_40_IRQ_EXTINT+28) /* Ethernet WakeupInt, SoftInt, TxDoneInt,
* TxFinishedInt, TxErrorInt,* TxUnderrunInt,
* RxDoneInt, RxFinishedInt, RxErrorInt,
* RxOverrunInt */
#define LPC17_40_IRQ_MCI (LPC17_40_IRQ_EXTINT+29) /* MCI SD Card Interface */
#define LPC17_40_IRQ_MCPWM (LPC17_40_IRQ_EXTINT+30) /* Motor Control PWM IPER[2:0], IPW[2:0],
* ICAP[2:0], FES */
#define LPC17_40_IRQ_QEI (LPC17_40_IRQ_EXTINT+31) /* Quadrature Encoder INX_Int, TIM_Int, VELC_Int,
* DIR_Int, ERR_Int, ENCLK_Int, POS0_Int, POS1_Int
* POS2_Int, REV_Int, POS0REV_Int, OS1REV_Int,
* POS2REV_Int */
#define LPC17_40_IRQ_PLL1 (LPC17_40_IRQ_EXTINT+32) /* PLL1 (USB PLL) PLL1 Lock (PLOCK1) */
#define LPC17_40_IRQ_USBACT (LPC17_40_IRQ_EXTINT+33) /* USB Activity Interrupt USB_NEED_CLK */
#define LPC17_40_IRQ_CANACT (LPC17_40_IRQ_EXTINT+34) /* CAN Activity Interrupt CAN1WAKE, CAN2WAKE */
#define LPC17_40_IRQ_UART4 (LPC17_40_IRQ_EXTINT+35) /* UART 4 Rx Line Status (RLS)
* Transmit Holding Register Empty (THRE)
* Rx Data Available (RDA)
* Character Time-out Indicator (CTI)
* End of Auto-Baud (ABEO)
* Auto-Baud Time-Out (ABTO) */
#define LPC17_40_IRQ_SSP2 (LPC17_40_IRQ_EXTINT+36) /* SSP2 Tx FIFO half empty of SSP2
* Rx FIFO half full of SSP2
* Rx Timeout of SSP2
* Rx Overrun of SSP2 */
#define LPC17_40_IRQ_LCD (LPC17_40_IRQ_EXTINT+37) /* LCD interrupt
* BER, VCompI, LNBUI, FUFI, CrsrI */
#define LPC17_40_IRQ_GPIO (LPC17_40_IRQ_EXTINT+38) /* GPIO Interrupt
* P0xREI, P2xREI, P0xFEI, P2xFEI */
#define LPC17_40_IRQ_PWM0 (LPC17_40_IRQ_EXTINT+39) /* PWM0 Match 0 - 6 of PWM0
* Capture 0-1 of PWM0 */
#define LPC17_40_IRQ_EEPROM (LPC17_40_IRQ_EXTINT+40) /* EEPROM Interrupt
* EE_PROG_DONE, EE_RW_DONE */
#define LPC17_40_IRQ_NEXTINT (41)
#define LPC17_40_IRQ_NIRQS (LPC17_40_IRQ_EXTINT+LPC17_40_IRQ_NEXTINT)
/* GPIO interrupts. The LPC177x_8x supports several interrupts on ports 0 and
* 2 (only). We go through some special efforts to keep the number of IRQs
* to a minimum in this sparse interrupt case.
*
* 31 interrupts on Port 0: p0.0 - p0.30
* 31 interrupts on Port 2: p2.0 - p2.30
* --
* 42
*/
#ifdef CONFIG_LPC17_40_GPIOIRQ
# define LPC17_40_VALID_GPIOINT0 (0xfffffffful) /* GPIO port 0 interrupt set */
# define LPC17_40_VALID_GPIOINT2 (0xfffffffful) /* GPIO port 2 interrupt set */
/* Set 1: 16 interrupts p0.0-p0.15 */
# define LPC17_40_VALID_SHIFT0L (0)
# define LPC17_40_VALID_FIRST0L (LPC17_40_IRQ_EXTINT+LPC17_40_IRQ_NEXTINT)
# define LPC17_40_IRQ_P0p0 (LPC17_40_VALID_FIRST0L+0)
# define LPC17_40_IRQ_P0p1 (LPC17_40_VALID_FIRST0L+1)
# define LPC17_40_IRQ_P0p2 (LPC17_40_VALID_FIRST0L+2)
# define LPC17_40_IRQ_P0p3 (LPC17_40_VALID_FIRST0L+3)
# define LPC17_40_IRQ_P0p4 (LPC17_40_VALID_FIRST0L+4)
# define LPC17_40_IRQ_P0p5 (LPC17_40_VALID_FIRST0L+5)
# define LPC17_40_IRQ_P0p6 (LPC17_40_VALID_FIRST0L+6)
# define LPC17_40_IRQ_P0p7 (LPC17_40_VALID_FIRST0L+7)
# define LPC17_40_IRQ_P0p8 (LPC17_40_VALID_FIRST0L+8)
# define LPC17_40_IRQ_P0p9 (LPC17_40_VALID_FIRST0L+9)
# define LPC17_40_IRQ_P0p10 (LPC17_40_VALID_FIRST0L+10)
# define LPC17_40_IRQ_P0p11 (LPC17_40_VALID_FIRST0L+11)
# define LPC17_40_IRQ_P0p12 (LPC17_40_VALID_FIRST0L+12)
# define LPC17_40_IRQ_P0p13 (LPC17_40_VALID_FIRST0L+13)
# define LPC17_40_IRQ_P0p14 (LPC17_40_VALID_FIRST0L+14)
# define LPC17_40_IRQ_P0p15 (LPC17_40_VALID_FIRST0L+15)
# define LPC17_40_VALID_NIRQS0L (16)
/* Set 2: 16 interrupts p0.16-p0.31 */
# define LPC17_40_VALID_SHIFT0H (16)
# define LPC17_40_VALID_FIRST0H (LPC17_40_VALID_FIRST0L+LPC17_40_VALID_NIRQS0L)
# define LPC17_40_IRQ_P0p16 (LPC17_40_VALID_FIRST0H+0)
# define LPC17_40_IRQ_P0p17 (LPC17_40_VALID_FIRST0H+1)
# define LPC17_40_IRQ_P0p18 (LPC17_40_VALID_FIRST0H+2)
# define LPC17_40_IRQ_P0p19 (LPC17_40_VALID_FIRST0H+3)
# define LPC17_40_IRQ_P0p20 (LPC17_40_VALID_FIRST0H+4)
# define LPC17_40_IRQ_P0p21 (LPC17_40_VALID_FIRST0H+5)
# define LPC17_40_IRQ_P0p22 (LPC17_40_VALID_FIRST0H+6)
# define LPC17_40_IRQ_P0p23 (LPC17_40_VALID_FIRST0H+7)
# define LPC17_40_IRQ_P0p24 (LPC17_40_VALID_FIRST0H+8)
# define LPC17_40_IRQ_P0p25 (LPC17_40_VALID_FIRST0H+9)
# define LPC17_40_IRQ_P0p26 (LPC17_40_VALID_FIRST0H+10)
# define LPC17_40_IRQ_P0p27 (LPC17_40_VALID_FIRST0H+11)
# define LPC17_40_IRQ_P0p28 (LPC17_40_VALID_FIRST0H+12)
# define LPC17_40_IRQ_P0p29 (LPC17_40_VALID_FIRST0H+13)
# define LPC17_40_IRQ_P0p30 (LPC17_40_VALID_FIRST0H+14)
# define LPC17_40_IRQ_P0p31 (LPC17_40_VALID_FIRST0H+15)
# define LPC17_40_VALID_NIRQS0H (16)
/* Set 3: 16 interrupts p2.0-p2.15 */
# define LPC17_40_VALID_SHIFT2L (0)
# define LPC17_40_VALID_FIRST2L (LPC17_40_VALID_FIRST0H+LPC17_40_VALID_NIRQS0H)
# define LPC17_40_IRQ_P2p0 (LPC17_40_VALID_FIRST2L+0)
# define LPC17_40_IRQ_P2p1 (LPC17_40_VALID_FIRST2L+1)
# define LPC17_40_IRQ_P2p2 (LPC17_40_VALID_FIRST2L+2)
# define LPC17_40_IRQ_P2p3 (LPC17_40_VALID_FIRST2L+3)
# define LPC17_40_IRQ_P2p4 (LPC17_40_VALID_FIRST2L+4)
# define LPC17_40_IRQ_P2p5 (LPC17_40_VALID_FIRST2L+5)
# define LPC17_40_IRQ_P2p6 (LPC17_40_VALID_FIRST2L+6)
# define LPC17_40_IRQ_P2p7 (LPC17_40_VALID_FIRST2L+7)
# define LPC17_40_IRQ_P2p8 (LPC17_40_VALID_FIRST2L+8)
# define LPC17_40_IRQ_P2p9 (LPC17_40_VALID_FIRST2L+9)
# define LPC17_40_IRQ_P2p10 (LPC17_40_VALID_FIRST2L+10)
# define LPC17_40_IRQ_P2p11 (LPC17_40_VALID_FIRST2L+11)
# define LPC17_40_IRQ_P2p12 (LPC17_40_VALID_FIRST2L+12)
# define LPC17_40_IRQ_P2p13 (LPC17_40_VALID_FIRST2L+13)
# define LPC17_40_IRQ_P2p14 (LPC17_40_VALID_FIRST2L+14)
# define LPC17_40_IRQ_P2p15 (LPC17_40_VALID_FIRST2L+15)
# define LPC17_40_VALID_NIRQS2L (16)
/* Set 4: 16 interrupts p2.16 - p2.31 */
# define LPC17_40_VALID_SHIFT2H (16)
# define LPC17_40_VALID_FIRST2H (LPC17_40_VALID_FIRST2L+LPC17_40_VALID_NIRQS2L)
# define LPC17_40_IRQ_P2p16 (LPC17_40_VALID_FIRST2H+0)
# define LPC17_40_IRQ_P2p17 (LPC17_40_VALID_FIRST2H+1)
# define LPC17_40_IRQ_P2p18 (LPC17_40_VALID_FIRST2H+2)
# define LPC17_40_IRQ_P2p19 (LPC17_40_VALID_FIRST2H+3)
# define LPC17_40_IRQ_P2p20 (LPC17_40_VALID_FIRST2H+4)
# define LPC17_40_IRQ_P2p21 (LPC17_40_VALID_FIRST2H+5)
# define LPC17_40_IRQ_P2p22 (LPC17_40_VALID_FIRST2H+6)
# define LPC17_40_IRQ_P2p23 (LPC17_40_VALID_FIRST2H+7)
# define LPC17_40_IRQ_P2p24 (LPC17_40_VALID_FIRST2H+8)
# define LPC17_40_IRQ_P2p25 (LPC17_40_VALID_FIRST2H+9)
# define LPC17_40_IRQ_P2p26 (LPC17_40_VALID_FIRST2H+10)
# define LPC17_40_IRQ_P2p27 (LPC17_40_VALID_FIRST2H+11)
# define LPC17_40_IRQ_P2p28 (LPC17_40_VALID_FIRST2H+12)
# define LPC17_40_IRQ_P2p29 (LPC17_40_VALID_FIRST2H+13)
# define LPC17_40_IRQ_P2p30 (LPC17_40_VALID_FIRST2H+14)
# define LPC17_40_IRQ_P2p31 (LPC17_40_VALID_FIRST2H+15)
# define LPC17_40_VALID_NIRQS2H (16)
# define LPC17_40_NGPIOAIRQS (LPC17_40_VALID_NIRQS0L+LPC17_40_VALID_NIRQS0H+LPC17_40_VALID_NIRQS2L+LPC17_40_VALID_NIRQS2H)
#else
# define LPC17_40_NGPIOAIRQS (0)
#endif
/* Total number of IRQ numbers */
#define NR_IRQS (LPC17_40_IRQ_EXTINT+LPC17_40_IRQ_NEXTINT+LPC17_40_NGPIOAIRQS)
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Inline functions
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_INCLUDE_LPC17XX_40XX_LPC178X_IRQ_H */