From e4e4e6316421a145b1e331d4e8dd067b8d0e7014 Mon Sep 17 00:00:00 2001 From: Alan Carvalho de Assis Date: Fri, 4 May 2018 18:19:36 -0600 Subject: [PATCH] arch/arm/src/nrf52: Add nRF52 Flash PROGMEM support --- arch/arm/src/nrf52/Kconfig | 13 + arch/arm/src/nrf52/Make.defs | 6 +- arch/arm/src/nrf52/chip/nrf52_ficr.h | 163 +++++++++ arch/arm/src/nrf52/chip/nrf52_nvmc.h | 99 +++++ arch/arm/src/nrf52/nrf52_flash.c | 213 +++++++++++ arch/arm/src/nrf52/nrf52_nvmc.c | 525 +++++++++++++++++++++++++++ arch/arm/src/nrf52/nrf52_nvmc.h | 329 +++++++++++++++++ arch/arm/src/nrf52/nrf52_start.c | 7 + 8 files changed, 1354 insertions(+), 1 deletion(-) create mode 100644 arch/arm/src/nrf52/chip/nrf52_ficr.h create mode 100644 arch/arm/src/nrf52/chip/nrf52_nvmc.h create mode 100644 arch/arm/src/nrf52/nrf52_flash.c create mode 100644 arch/arm/src/nrf52/nrf52_nvmc.c create mode 100644 arch/arm/src/nrf52/nrf52_nvmc.h diff --git a/arch/arm/src/nrf52/Kconfig b/arch/arm/src/nrf52/Kconfig index eb4d6818547..99990ec37b4 100644 --- a/arch/arm/src/nrf52/Kconfig +++ b/arch/arm/src/nrf52/Kconfig @@ -70,6 +70,19 @@ config NRF52_WDT endmenu # NRF52 Peripheral Selection +config NRF52_FLASH_PREFETCH + bool "Enable FLASH Pre-fetch" + default y + ---help--- + Enable FLASH prefetch + +config NRF52_PROGMEM + bool "FLASH program memory" + default n + select ARCH_HAVE_PROGMEM + ---help--- + Enable support FLASH interfaces as defined in include/nuttx/progmem.h + menu "GPIO Interrupt Configuration" config NRF52_GPIOIRQ diff --git a/arch/arm/src/nrf52/Make.defs b/arch/arm/src/nrf52/Make.defs index 763066f72b0..5f1a94f99fe 100644 --- a/arch/arm/src/nrf52/Make.defs +++ b/arch/arm/src/nrf52/Make.defs @@ -81,7 +81,7 @@ endif CHIP_ASRCS = CHIP_CSRCS = nrf52_start.c nrf52_clockconfig.c nrf52_irq.c nrf52_clrpend.c -CHIP_CSRCS += nrf52_allocateheap.c nrf52_lowputc.c nrf52_gpio.c +CHIP_CSRCS += nrf52_allocateheap.c nrf52_lowputc.c nrf52_gpio.c nrf52_nvmc.c ifneq ($(CONFIG_SCHED_TICKLESS),y) CHIP_CSRCS += nrf52_timerisr.c @@ -101,6 +101,10 @@ ifeq ($(CONFIG_NRF52_HAVE_UART),y) CHIP_CSRCS += nrf52_serial.c endif +ifeq ($(CONFIG_NRF52_PROGMEM),y) +CHIP_CSRCS += nrf52_flash.c +endif + ifeq ($(CONFIG_NRF52_WDT),y) CHIP_CSRCS += nrf52_wdt.c endif diff --git a/arch/arm/src/nrf52/chip/nrf52_ficr.h b/arch/arm/src/nrf52/chip/nrf52_ficr.h new file mode 100644 index 00000000000..04230049ed4 --- /dev/null +++ b/arch/arm/src/nrf52/chip/nrf52_ficr.h @@ -0,0 +1,163 @@ +/*************************************************************************************************** + * arch/arm/src/nrf52/chip/nrf52_ficr.h + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Alan Carvalho de Assis + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ***************************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_NRF52_CHIP_NRF52_FICR_H +#define __ARCH_ARM_SRC_NRF52_CHIP_NRF52_FICR_H + +/*************************************************************************************************** + * Included Files + ***************************************************************************************************/ + +#include +#include "chip/nrf52_memorymap.h" + +/*************************************************************************************************** + * Pre-processor Definitions + ***************************************************************************************************/ + +/* FICR Register Offsets ****************************************************************************/ + +/* Registers for the FICR */ + +#define NRF52_FICR_CODEPAGESIZE_OFFSET 0x010 /* Code memory page size */ +#define NRF52_FICR_CODESIZE_OFFSET 0x014 /* Code memory size */ + +#define NRF52_FICR_DEVICEID0_OFFSET 0x060 /* Device identifier */ +#define NRF52_FICR_DEVICEID1_OFFSET 0x064 /* Device identifier */ + +#define NRF52_FICR_ER0_OFFSET 0x080 /* Encryption Root, word 0 */ +#define NRF52_FICR_ER1_OFFSET 0x084 /* Encryption Root, word 1 */ +#define NRF52_FICR_ER2_OFFSET 0x088 /* Encryption Root, word 2 */ +#define NRF52_FICR_ER3_OFFSET 0x08c /* Encryption Root, word 3 */ +#define NRF52_FICR_IR0_OFFSET 0x090 /* Identity Root, word 0 */ +#define NRF52_FICR_IR1_OFFSET 0x094 /* Identity Root, word 1 */ +#define NRF52_FICR_IR2_OFFSET 0x098 /* Identity Root, word 2 */ +#define NRF52_FICR_IR3_OFFSET 0x09c /* Identity Root, word 3 */ +#define NRF52_FICR_DEVICEADDRTYPE_OFFSET 0x0a0 /* Device address type */ +#define NRF52_FICR_DEVICEADDR0_OFFSET 0x0a4 /* Device address 0 */ +#define NRF52_FICR_DEVICEADDR1_OFFSET 0x0a8 /* Device address 1 */ + +#define NRF52_FICR_INFO_PART_OFFSET 0x100 /* Part code */ +#define NRF52_FICR_INFO_VARIANT_OFFSET 0x104 /* Part Variant, Hardware version and Production configuration */ +#define NRF52_FICR_INFO_PACKAGE_OFFSET 0x108 /* Package option */ +#define NRF52_FICR_INFO_RAM_OFFSET 0x10c /* RAM variant */ +#define NRF52_FICR_INFO_FLASH_OFFSET 0x110 /* Flash variant */ + +#define NRF52_FICR_TEMP_A0_OFFSET 0x404 /* Slope definition A0 */ +#define NRF52_FICR_TEMP_A1_OFFSET 0x408 /* Slope definition A1 */ +#define NRF52_FICR_TEMP_A2_OFFSET 0x40c /* Slope definition A2 */ +#define NRF52_FICR_TEMP_A3_OFFSET 0x410 /* Slope definition A3 */ +#define NRF52_FICR_TEMP_A4_OFFSET 0x414 /* Slope definition A4 */ +#define NRF52_FICR_TEMP_A5_OFFSET 0x418 /* Slope definition A5 */ +#define NRF52_FICR_TEMP_B0_OFFSET 0x41c /* y-intercept B0 */ +#define NRF52_FICR_TEMP_B1_OFFSET 0x420 /* y-intercept B1 */ +#define NRF52_FICR_TEMP_B2_OFFSET 0x424 /* y-intercept B2 */ +#define NRF52_FICR_TEMP_B3_OFFSET 0x428 /* y-intercept B3 */ +#define NRF52_FICR_TEMP_B4_OFFSET 0x42c /* y-intercept B4 */ +#define NRF52_FICR_TEMP_B5_OFFSET 0x430 /* y-intercept B5 */ +#define NRF52_FICR_TEMP_T0_OFFSET 0x434 /* Segment end T0 */ +#define NRF52_FICR_TEMP_T1_OFFSET 0x438 /* Segment end T1 */ +#define NRF52_FICR_TEMP_T2_OFFSET 0x43c /* Segment end T2 */ +#define NRF52_FICR_TEMP_T3_OFFSET 0x440 /* Segment end T3 */ +#define NRF52_FICR_TEMP_T4_OFFSET 0x444 /* Segment end T4 */ + +#define NRF52_FICR_NFC_TAGHEADER0_OFFSET 0x450 /* Default header for NFC Tag */ +#define NRF52_FICR_NFC_TAGHEADER1_OFFSET 0x454 /* Default header for NFC Tag */ +#define NRF52_FICR_NFC_TAGHEADER2_OFFSET 0x458 /* Default header for NFC Tag */ +#define NRF52_FICR_NFC_TAGHEADER3_OFFSET 0x45c /* Default header for NFC Tag */ + +/* FICR Register Addresses **************************************************************************/ + +#define NRF52_FICR_CODEPAGESIZE (NRF52_FICR_BASE + NRF52_FICR_CODEPAGESIZE_OFFSET) +#define NRF52_FICR_CODESIZE (NRF52_FICR_BASE + NRF52_FICR_CODESIZE_OFFSET) + +#define NRF52_FICR_DEVICEID0 (NRF52_FICR_BASE + NRF52_FICR_DEVICEID0_OFFSET) +#define NRF52_FICR_DEVICEID1 (NRF52_FICR_BASE + NRF52_FICR_DEVICEID1_OFFSET) + +#define NRF52_FICR_ER0 (NRF52_FICR_BASE + NRF52_FICR_ER0_OFFSET) +#define NRF52_FICR_ER1 (NRF52_FICR_BASE + NRF52_FICR_ER1_OFFSET) +#define NRF52_FICR_ER2 (NRF52_FICR_BASE + NRF52_FICR_ER2_OFFSET) +#define NRF52_FICR_ER3 (NRF52_FICR_BASE + NRF52_FICR_ER3_OFFSET) +#define NRF52_FICR_IR0 (NRF52_FICR_BASE + NRF52_FICR_IR0_OFFSET) +#define NRF52_FICR_IR1 (NRF52_FICR_BASE + NRF52_FICR_IR1_OFFSET) +#define NRF52_FICR_IR2 (NRF52_FICR_BASE + NRF52_FICR_IR2_OFFSET) +#define NRF52_FICR_IR3 (NRF52_FICR_BASE + NRF52_FICR_IR3_OFFSET) +#define NRF52_FICR_DEVICEADDRTYPE (NRF52_FICR_BASE + NRF52_FICR_DEVICEADDRTYPE_OFFSET) +#define NRF52_FICR_DEVICEADDR0 (NRF52_FICR_BASE + NRF52_FICR_DEVICEADDR0_OFFSET) +#define NRF52_FICR_DEVICEADDR1 (NRF52_FICR_BASE + NRF52_FICR_DEVICEADDR1_OFFSET) + +#define NRF52_FICR_INFO_PART (NRF52_FICR_BASE + NRF52_FICR_INFO_PART_OFFSET) +#define NRF52_FICR_INFO_VARIANT (NRF52_FICR_BASE + NRF52_FICR_INFO_VARIANT_OFFSET) +#define NRF52_FICR_INFO_PACKAGE (NRF52_FICR_BASE + NRF52_FICR_INFO_PACKAGE_OFFSET) +#define NRF52_FICR_INFO_RAM (NRF52_FICR_BASE + NRF52_FICR_INFO_RAM_OFFSET) +#define NRF52_FICR_INFO_FLASH (NRF52_FICR_BASE + NRF52_FICR_INFO_FLASH_OFFSET) + +#define NRF52_FICR_TEMP_A0 (NRF52_FICR_BASE + NRF52_FICR_TEMP_A0_OFFSET) +#define NRF52_FICR_TEMP_A1 (NRF52_FICR_BASE + NRF52_FICR_TEMP_A1_OFFSET) +#define NRF52_FICR_TEMP_A2 (NRF52_FICR_BASE + NRF52_FICR_TEMP_A2_OFFSET) +#define NRF52_FICR_TEMP_A3 (NRF52_FICR_BASE + NRF52_FICR_TEMP_A3_OFFSET) +#define NRF52_FICR_TEMP_A4 (NRF52_FICR_BASE + NRF52_FICR_TEMP_A4_OFFSET) +#define NRF52_FICR_TEMP_A5 (NRF52_FICR_BASE + NRF52_FICR_TEMP_A5_OFFSET) +#define NRF52_FICR_TEMP_B0 (NRF52_FICR_BASE + NRF52_FICR_TEMP_B0_OFFSET) +#define NRF52_FICR_TEMP_B1 (NRF52_FICR_BASE + NRF52_FICR_TEMP_B1_OFFSET) +#define NRF52_FICR_TEMP_B2 (NRF52_FICR_BASE + NRF52_FICR_TEMP_B2_OFFSET) +#define NRF52_FICR_TEMP_B3 (NRF52_FICR_BASE + NRF52_FICR_TEMP_B3_OFFSET) +#define NRF52_FICR_TEMP_B4 (NRF52_FICR_BASE + NRF52_FICR_TEMP_B4_OFFSET) +#define NRF52_FICR_TEMP_B5 (NRF52_FICR_BASE + NRF52_FICR_TEMP_B5_OFFSET) +#define NRF52_FICR_TEMP_T0 (NRF52_FICR_BASE + NRF52_FICR_TEMP_T0_OFFSET) +#define NRF52_FICR_TEMP_T1 (NRF52_FICR_BASE + NRF52_FICR_TEMP_T1_OFFSET) +#define NRF52_FICR_TEMP_T2 (NRF52_FICR_BASE + NRF52_FICR_TEMP_T2_OFFSET) +#define NRF52_FICR_TEMP_T3 (NRF52_FICR_BASE + NRF52_FICR_TEMP_T3_OFFSET) +#define NRF52_FICR_TEMP_T4 (NRF52_FICR_BASE + NRF52_FICR_TEMP_T4_OFFSET) + +#define NRF52_FICR_NFC_TAGHEADER0 (NRF52_FICR_BASE + NRF52_FICR_NFC_TAGHEADER0_OFFSET) +#define NRF52_FICR_NFC_TAGHEADER1 (NRF52_FICR_BASE + NRF52_FICR_NFC_TAGHEADER1_OFFSET) +#define NRF52_FICR_NFC_TAGHEADER2 (NRF52_FICR_BASE + NRF52_FICR_NFC_TAGHEADER2_OFFSET) +#define NRF52_FICR_NFC_TAGHEADER3 (NRF52_FICR_BASE + NRF52_FICR_NFC_TAGHEADER3_OFFSET) + +/* FICR Register Bitfield Definitions **************************************************************/ + +#define NRF52_FICR_READY_READY (1 << 0) /* FICR is ready */ + +#define NRF52_FICR_CONFIG_WEN (1 << 0) /* Enable write program memory */ + +#define NRF52_FICR_ICACHECNF_CACHEEN (1 << 0) /* Cache enable */ +#define NRF52_FICR_ICACHECNF_CACHEPROFEN (1 << 8) /* Cache profiling enable */ + +/* ENABLE Register */ + +/* INTENSET Register */ + +#endif /* __ARCH_ARM_SRC_NRF52_CHIP_NRF52_FICR_H */ diff --git a/arch/arm/src/nrf52/chip/nrf52_nvmc.h b/arch/arm/src/nrf52/chip/nrf52_nvmc.h new file mode 100644 index 00000000000..502a2406479 --- /dev/null +++ b/arch/arm/src/nrf52/chip/nrf52_nvmc.h @@ -0,0 +1,99 @@ +/*************************************************************************************************** + * arch/arm/src/nrf52/chip/nrf52_nvmc.h + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Alan Carvalho de Assis + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ***************************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_NRF52_CHIP_NRF52_NVMC_H +#define __ARCH_ARM_SRC_NRF52_CHIP_NRF52_NVMC_H + +/*************************************************************************************************** + * Included Files + ***************************************************************************************************/ + +#include +#include "chip/nrf52_memorymap.h" + +/*************************************************************************************************** + * Pre-processor Definitions + ***************************************************************************************************/ + +/* NVMC Register Offsets ****************************************************************************/ + +/* Registers for the NVMC */ + +#define NRF52_NVMC_READY_OFFSET 0x400 /* Ready flag */ +#define NRF52_NVMC_CONFIG_OFFSET 0x504 /* Configuration register */ +#define NRF52_NVMC_ERASEPAGE_OFFSET 0x508 /* Register for erasing a page in Code area */ +#define NRF52_NVMC_ERASEPCR1_OFFSET 0x508 /* Equivalent to ERASEPAGE */ +#define NRF52_NVMC_ERASEALL_OFFSET 0x50c /* Register for erasing all non-volatile user memory */ +#define NRF52_NVMC_ERASEPCR0_OFFSET 0x510 /* Register for erasing a page in Code area. Equiv. ERASEPAGE */ +#define NRF52_NVMC_ERASEUICR_OFFSET 0x514 /* Register for erasing User Information Configuration Registers */ +#define NRF52_NVMC_ICACHECNF_OFFSET 0x540 /* I-Code cache configuration register */ +#define NRF52_NVMC_IHIT_OFFSET 0x548 /* I-Code cache hit counter. */ +#define NRF52_NVMC_IMISS_OFFSET 0x54c /* I-Code cache miss counter */ + +/* NVMC Register Addresses **************************************************************************/ + +#define NRF52_NVMC_READY (NRF52_NVMC_BASE + NRF52_NVMC_READY_OFFSET) +#define NRF52_NVMC_CONFIG (NRF52_NVMC_BASE + NRF52_NVMC_CONFIG_OFFSET) +#define NRF52_NVMC_ERASEPAGE (NRF52_NVMC_BASE + NRF52_NVMC_ERASEPAGE_OFFSET) +#define NRF52_NVMC_ERASEPCR1 (NRF52_NVMC_BASE + NRF52_NVMC_ERASEPCR1_OFFSET) +#define NRF52_NVMC_ERASEALL (NRF52_NVMC_BASE + NRF52_NVMC_ERASEALL_OFFSET) +#define NRF52_NVMC_ERASEPCR0 (NRF52_NVMC_BASE + NRF52_NVMC_ERASEPCR0_OFFSET) +#define NRF52_NVMC_ERASEUICR (NRF52_NVMC_BASE + NRF52_NVMC_ERASEUICR_OFFSET) +#define NRF52_NVMC_ICACHECNF (NRF52_NVMC_BASE + NRF52_NVMC_ICACHECNF_OFFSET) +#define NRF52_NVMC_IHIT (NRF52_NVMC_BASE + NRF52_NVMC_IHIT_OFFSET) +#define NRF52_NVMC_IMISS (NRF52_NVMC_BASE + NRF52_NVMC_IMISS_OFFSET) + +/* NVMC Register Bitfield Definitions **************************************************************/ + +/* READY Register */ + +#define NVMC_READY_READY (1 << 0) /* NVMC is ready */ + +/* CONFIG Register */ + +#define NVMC_CONFIG_SHIFT (0) +#define NVMC_CONFIG_MASK (3 << NVMC_CONFIG_SHIFT) +#define NVMC_CONFIG_REN (0 << NVMC_CONFIG_SHIFT) /* Read-only access */ +#define NVMC_CONFIG_WEN (1 << NVMC_CONFIG_SHIFT) /* Write Enabled */ +#define NVMC_CONFIG_EEN (2 << NVMC_CONFIG_SHIFT) /* Erase Enabled */ + +/* ICACHECNF Register */ + +#define NVMC_ICACHECNF_CACHEEN (1 << 0) /* Cache enable */ +#define NVMC_ICACHECNF_CACHEPROFEN (1 << 8) /* Cache profiling enable */ + +/* INTENSET Register */ + +#endif /* __ARCH_ARM_SRC_NRF52_CHIP_NRF52_NVMC_H */ diff --git a/arch/arm/src/nrf52/nrf52_flash.c b/arch/arm/src/nrf52/nrf52_flash.c new file mode 100644 index 00000000000..6d06216e0d4 --- /dev/null +++ b/arch/arm/src/nrf52/nrf52_flash.c @@ -0,0 +1,213 @@ +/**************************************************************************** + * arch/arm/src/nrf52/nrf52_flash.c + * Standard Flash access functions needed by the flash mtd driver. + * + * Copyright (C) 2018 Zglue Inc. All rights reserved. + * Author: Levin Li + * Author: Alan Carvalho de Assis + * + * Ported from the Nordic SDK, this is the original license: + * + * Copyright (c) 2012 - 2018, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include +#include +#include + +#include +#include + +#include "chip.h" + +#include "up_arch.h" + +#include "chip/nrf52_ficr.h" +#include "chip/nrf52_nvmc.h" +#include "nrf52_nvmc.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +#define NRF52_FLASH_PAGE_SIZE (4*1024) + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +size_t up_progmem_pagesize(size_t page) +{ + size_t npage = up_progmem_npages(); + + if (page >= npage) + { + _err("Error For Wrong Page Index[%d], Total Page %d.\n", page, npage); + return 0; + } + else + { + return NRF52_FLASH_PAGE_SIZE; + } +} + +ssize_t up_progmem_getpage(size_t addr) +{ + size_t page_end = 0; + + if (addr >= nrf_nvmc_get_flash_size()) + { + _err("Address is out of Total Size.\n"); + return -EFAULT; + } + + page_end = addr / NRF52_FLASH_PAGE_SIZE; + + return page_end; +} + +size_t up_progmem_getaddress(size_t page) +{ + + if (page >= up_progmem_npages()) + { + return SIZE_MAX; + } + + return page * NRF52_FLASH_PAGE_SIZE; +} + +size_t up_progmem_npages(void) +{ + return nrf_nvmc_get_flash_size() / NRF52_FLASH_PAGE_SIZE; +} + +bool up_progmem_isuniform(void) +{ + return true; +} + +ssize_t up_progmem_erasepage(size_t page) +{ + size_t page_address; + + if (page >= up_progmem_npages()) + { + _err("Wrong Page number %d.\n", page); + return -EFAULT; + } + + page_address = up_progmem_getaddress(page); + + /* Get flash ready and begin erasing single page */ + + nrf_nvmc_page_erase(page_address); + + /* Verify */ + + if (up_progmem_ispageerased(page) == 0) + { + return up_progmem_pagesize(page); + } + else + { + return -EIO; + } +} + +ssize_t up_progmem_ispageerased(size_t page) +{ + size_t addr; + size_t count; + size_t bwritten = 0; + + if (page >= up_progmem_npages()) + { + return -EFAULT; + } + + /* Verify */ + + for (addr = up_progmem_getaddress(page), count = up_progmem_pagesize(page); + count; count--, addr++) + { + if (getreg8(addr) != 0xff) + { + bwritten++; + } + } + + return bwritten; +} + +ssize_t up_progmem_write(size_t addr, const void *buf, size_t count) +{ + uint32_t *pword = (uint32_t *)buf; + size_t written = count; + + /* NRF52 requires word access */ + + if (count & 0x3) + { + return -EINVAL; + } + + /* Check for valid address range */ + + if ((addr + count) > nrf_nvmc_get_flash_size()) + { + return -EFAULT; + } + + + /* Get flash ready and begin flashing */ + + for (addr += NRF52_FLASH_BASE; count; count -= 4, pword++, addr += 4) + { + /* Write word and wait to complete */ + + nrf_nvmc_write_word(addr, *pword); + + /* Verify */ + + if (getreg32(addr) != *pword) + { + _err("Write Internal Flash Error.\n"); + return -EIO; + } + } + + return written; +} diff --git a/arch/arm/src/nrf52/nrf52_nvmc.c b/arch/arm/src/nrf52/nrf52_nvmc.c new file mode 100644 index 00000000000..e1fee5fd6bb --- /dev/null +++ b/arch/arm/src/nrf52/nrf52_nvmc.c @@ -0,0 +1,525 @@ +/**************************************************************************** + * arch/arm/src/nrf52/nrf52_nvmc.c + * + * Copyright (C) 2018 Zglue Inc. All rights reserved. + * Author: Levin Li + * Author: Alan Carvalho de Assis + * + * Ported from the Nordic SDK, this is the original license: + * + * Copyright (c) 2012 - 2018, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include "cache.h" + +#include "chip/nrf52_ficr.h" +#include "chip/nrf52_nvmc.h" +#include "nrf52_nvmc.h" + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: wait_for_flash_ready + * + * Description: + * Busy-wait until the flash operation is done. + * + * Input Parameter: + * None + * + * Returned Values: + * None + * + ****************************************************************************/ + +static inline void wait_for_flash_ready(void) +{ + while (!(getreg32(NRF52_NVMC_READY) & NVMC_READY_READY)) + { + } +} + +/**************************************************************************** + * Name: nrf_mem_barrier + * + * Description: + * Force memory sync before continuing. + * + * Input Parameter: + * None + * + * Returned Values: + * None + * + ****************************************************************************/ + +static inline void nrf_mem_barrier(void) +{ + ARM_ISB(); + ARM_DSB(); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: nrf_nvmc_enable_icache + * + * Description: + * Enable I-Cache for Flash + * + * Input Parameter: + * flag - Flag to enable or disable. + * + * Returned Values: + * None + * + ****************************************************************************/ + +void nrf_nvmc_enable_icache(bool flag) +{ + uint32_t value; + + /* Read the current icache configuration */ + + value = getreg32(NRF52_NVMC_ICACHECNF); + + if (flag) + { + value |= NVMC_ICACHECNF_CACHEEN; + } + else + { + value &= ~NVMC_ICACHECNF_CACHEEN; + } + + /* Setup the new icache configuration */ + + putreg32(value, NRF52_NVMC_ICACHECNF); +} + +/**************************************************************************** + * Name: nrf_nvmc_enable_profile + * + * Description: + * Enable profiling I-Cache for flash + * + * Input Parameter: + * flag - Flag to enable or disable. + * + * Returned Values: + * None + * + ****************************************************************************/ + +void nrf_nvmc_enable_profile(bool flag) +{ + uint32_t value; + + /* Read the current icache configuration */ + + value = getreg32(NRF52_NVMC_ICACHECNF); + + if (flag) + { + value |= NVMC_ICACHECNF_CACHEPROFEN; + } + else + { + value &= ~NVMC_ICACHECNF_CACHEPROFEN; + } + + /* Setup the new icache configuration */ + + putreg32(value, NRF52_NVMC_ICACHECNF); +} + +/**************************************************************************** + * Name: nrf_nvmc_get_profiling_ihit + * + * Description: + * Get I-Hit for profiling + * + * Input Parameter: + * None + * + * Returned Values: + * Number of cache hits. + * + ****************************************************************************/ + +uint32_t nrf_nvmc_get_profiling_ihit(void) +{ + return getreg32(NRF52_NVMC_IHIT); +} + +/**************************************************************************** + * Name: nrf_nvmc_get_profiling_imiss + * + * Description: + * Get I-Miss for profiling + * + * Input Parameter: + * None + * + * Returned Values: + * Number of cache misses. + * + ****************************************************************************/ + +uint32_t nrf_nvmc_get_profiling_imiss(void) +{ + return getreg32(NRF52_NVMC_IMISS); +} + +/**************************************************************************** + * Name: nrf_nvmc_get_flash_size + * + * Description: + * Get internal FLASH size + * + * Input Parameter: + * None + * + * Returned Values: + * Flash size. + * + ****************************************************************************/ + +uint32_t nrf_nvmc_get_flash_size(void) +{ + return getreg32(NRF52_FICR_INFO_FLASH) * 1024; +} + +/**************************************************************************** + * Name: nrf_nvmc_get_ram_size + * + * Description: + * Get internal RAM size. + * + * Input Parameter: + * None + * + * Returned Values: + * RAM size. + * + ****************************************************************************/ + +uint32_t nrf_nvmc_get_ram_size(void) +{ + return getreg32(NRF52_FICR_INFO_RAM) * 1024; +} + +/**************************************************************************** + * Name: nrf_nvmc_read_dev_id0 + * + * Description: + * Get device identifier 0 + * + * Input Parameter: + * None + * + * Returned Values: + * Value of ID0 + * + ****************************************************************************/ + +uint32_t nrf_nvmc_read_dev_id0(void) +{ + return getreg32(NRF52_FICR_DEVICEID0); +} + +/**************************************************************************** + * Name: nrf_nvmc_read_dev_id1 + * + * Description: + * Get device identifier 1 + * + * Input Parameter: + * None + * + * Returned Values: + * Value of ID1 + * + ****************************************************************************/ + +uint32_t nrf_nvmc_read_dev_id1(void) +{ + return getreg32(NRF52_FICR_DEVICEID1); +} + +/**************************************************************************** + * Name: system_image_start_address + * + * Description: + * Get system image code begin address. + * + * Input Parameter: + * None + * + * Returned Values: + * Address where code starts. + * + ****************************************************************************/ + +uint32_t system_image_start_address(void) +{ + extern uint32_t _stext; + return (uint32_t)&_stext; +} + +/**************************************************************************** + * Name: system_image_ro_section_end + * + * Description: + * Get system image end address of read only section. + * + * Input Parameter: + * None + * + * Returned Values: + * The end address of the RO section. + * + ****************************************************************************/ + +uint32_t system_image_ro_section_end(void) +{ + extern uint32_t _eronly; + return (uint32_t)&_eronly; +} + +/**************************************************************************** + * Name: system_image_data_section_size + * + * Description: + * Get system image data section size + * + * Input Parameter: + * None + * + * Returned Values: + * The size of the data section. + * + ****************************************************************************/ + +uint32_t system_image_data_section_size(void) +{ + extern uint32_t _edata; + extern uint32_t _sdata; + uint32_t data_size; + uint32_t start; + uint32_t end; + + start = (uint32_t)&_sdata; + end = (uint32_t)&_edata; + data_size = end - start; + return data_size; +} + +/**************************************************************************** + * Name: nrf_nvmc_page_erase + * + * Description: + * Erase a page in flash. This is required before writing to any + * address in the page. + * + * Input Parameter: + * address - Start address of the page. + * + * Returned Values: + * None + * + ****************************************************************************/ + +void nrf_nvmc_page_erase(uint32_t address) +{ + /* Enable erase */ + + putreg32(NVMC_CONFIG_EEN, NRF52_NVMC_CONFIG); + nrf_mem_barrier(); + + /* Erase the page */ + + putreg32(address, NRF52_NVMC_ERASEPAGE); + wait_for_flash_ready(); + + /* Return to read-only mode */ + + putreg32(NVMC_CONFIG_REN, NRF52_NVMC_CONFIG); + nrf_mem_barrier(); +} + +/**************************************************************************** + * Name: nrf_nvmc_write_byte + * + * Description: + * The function reads the word containing the byte, and then + * rewrites the entire word. + * + * Input Parameter: + * address - Address to write to. + * value - Value to write. + * + * Returned Values: + * None + * + ****************************************************************************/ + +void nrf_nvmc_write_byte(uint32_t address, uint8_t value) +{ + uint32_t byte_shift = address & (uint32_t)0x03; + uint32_t address32 = address & ~byte_shift; /* Address to the word this byte is in.*/ + uint32_t value32 = (*(uint32_t *)address32 & + ~((uint32_t)0xFF << (byte_shift << (uint32_t)3))); + value32 = value32 + ((uint32_t)value << (byte_shift << 3)); + + /* Enable write */ + + putreg32(NVMC_CONFIG_WEN, NRF52_NVMC_CONFIG); + nrf_mem_barrier(); + + /* Write the byte, needs to be a single 32-bit write operation */ + + *(uint32_t *)address32 = value32; + wait_for_flash_ready(); + + /* Return to read-only mode */ + + putreg32(NVMC_CONFIG_REN, NRF52_NVMC_CONFIG); + nrf_mem_barrier(); +} + +/**************************************************************************** + * Name: nrf_nvmc_write_word + * + * Description: + * Write a 32-bit word to flash. + * + * Input Parameter: + * address - Address to write to. + * value - Value to write. + * + * Returned Values: + * None + * + ****************************************************************************/ + +void nrf_nvmc_write_word(uint32_t address, uint32_t value) +{ + /* Enable write */ + + putreg32(NVMC_CONFIG_WEN, NRF52_NVMC_CONFIG); + nrf_mem_barrier(); + + /* Write the word */ + + *(uint32_t *)address = value; + wait_for_flash_ready(); + + /* Return to read-only mode */ + + putreg32(NVMC_CONFIG_REN, NRF52_NVMC_CONFIG); + nrf_mem_barrier(); +} + +/**************************************************************************** + * Name: nrf_nvmc_write_bytes + * + * Description: + * Write consecutive bytes to flash. + * + * Input Parameter: + * address - Address to write to. + * src - Pointer to data to copy from. + * num_bytes - Number of bytes in src to write. + * + * Returned Values: + * None + * + ****************************************************************************/ + +void nrf_nvmc_write_bytes(uint32_t address, const uint8_t *src, + uint32_t num_bytes) +{ + uint32_t i; + + for (i = 0; i < num_bytes; i++) + { + nrf_nvmc_write_byte(address + i, src[i]); + } +} + +/**************************************************************************** + * Name: nrf_nvmc_write_words + * + * Description: + * Write consecutive words to flash. + * + * Input Parameter: + * address - Address to write to. + * src - Pointer to data to copy from. + * num_words - Number of words in src to write. + * + * Returned Values: + * None + * + ****************************************************************************/ + +void nrf_nvmc_write_words(uint32_t address, const uint32_t *src, + uint32_t num_words) +{ + uint32_t i; + + /* Enable write */ + + putreg32(NVMC_CONFIG_WEN, NRF52_NVMC_CONFIG); + nrf_mem_barrier(); + + for (i = 0; i < num_words; i++) + { + ((uint32_t *)address)[i] = src[i]; + wait_for_flash_ready(); + } + + /* Return to read-only mode */ + + putreg32(NVMC_CONFIG_REN, NRF52_NVMC_CONFIG); + nrf_mem_barrier(); +} diff --git a/arch/arm/src/nrf52/nrf52_nvmc.h b/arch/arm/src/nrf52/nrf52_nvmc.h new file mode 100644 index 00000000000..637bc3e56da --- /dev/null +++ b/arch/arm/src/nrf52/nrf52_nvmc.h @@ -0,0 +1,329 @@ +/**************************************************************************** + * arch/arm/src/nrf52/nrf52_nvmc.h + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Ported from the Nordic SDK, this is the original license: + * + * Copyright (c) 2012 - 2018, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_NRF52_NRF52_NVMC_H +#define __ARCH_ARM_SRC_NRF52_NRF52_NVMC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifdef __cplusplus +extern "C" +{ +#endif + +/**************************************************************************** + * Name: nrf_nvmc_page_erase + * + * Description: + * Erase a page in flash. This is required before writing to any + * address in the page. + * + * Input Parameter: + * address - Start address of the page. + * + * Returned Values: + * None + * + ****************************************************************************/ + +void nrf_nvmc_page_erase(uint32_t address); + +/**************************************************************************** + * Name: nrf_nvmc_write_byte + * + * Description: + * The function reads the word containing the byte, and then + * rewrites the entire word. + * + * Input Parameter: + * address - Address to write to. + * value - Value to write. + * + * Returned Values: + * None + * + ****************************************************************************/ + +void nrf_nvmc_write_byte(uint32_t address, uint8_t value); + +/**************************************************************************** + * Name: nrf_nvmc_write_word + * + * Description: + * Write a 32-bit word to flash. + * + * Input Parameter: + * address - Address to write to. + * value - Value to write. + * + * Returned Values: + * None + * + ****************************************************************************/ + +void nrf_nvmc_write_word(uint32_t address, uint32_t value); + +/**************************************************************************** + * Name: nrf_nvmc_write_bytes + * + * Description: + * Write consecutive bytes to flash. + * + * Input Parameter: + * address - Address to write to. + * src - Pointer to data to copy from. + * num_bytes - Number of bytes in src to write. + * + * Returned Values: + * None + * + ****************************************************************************/ + +void nrf_nvmc_write_bytes(uint32_t address, const uint8_t *src, + uint32_t num_bytes); + +/**************************************************************************** + * Name: nrf_nvmc_write_words + * + * Description: + * Write consecutive words to flash. + * + * Input Parameter: + * address - Address to write to. + * src - Pointer to data to copy from. + * num_words - Number of words in src to write. + * + * Returned Values: + * None + * + ****************************************************************************/ + +void nrf_nvmc_write_words(uint32_t address, const uint32_t *src, + uint32_t num_words); + +/**************************************************************************** + * Name: nrf_nvmc_enable_icache + * + * Description: + * Enable I-Cache for Flash + * + * Input Parameter: + * flag - Flag to enable or disable. + * + * Returned Values: + * None + * + ****************************************************************************/ + +void nrf_nvmc_enable_icache(bool flag); + +/**************************************************************************** + * Name: nrf_nvmc_enable_profile + * + * Description: + * Enable profiling I-Cache for flash + * + * Input Parameter: + * flag - Flag to enable or disable. + * + * Returned Values: + * None + * + ****************************************************************************/ + +void nrf_nvmc_enable_profile(bool flag); + +/**************************************************************************** + * Name: nrf_nvmc_get_profiling_ihit + * + * Description: + * Get I-Hit for profiling + * + * Input Parameter: + * None + * + * Returned Values: + * Number of cache hits. + * + ****************************************************************************/ + +uint32_t nrf_nvmc_get_profiling_ihit(void); + +/**************************************************************************** + * Name: nrf_nvmc_get_profiling_imiss + * + * Description: + * Get I-Miss for profiling + * + * Input Parameter: + * None + * + * Returned Values: + * Number of cache misses. + * + ****************************************************************************/ + +uint32_t nrf_nvmc_get_profiling_imiss(void); + +/**************************************************************************** + * Name: nrf_nvmc_get_flash_size + * + * Description: + * Get internal FLASH size + * + * Input Parameter: + * None + * + * Returned Values: + * Flash size. + * + ****************************************************************************/ + +uint32_t nrf_nvmc_get_flash_size(void); + +/**************************************************************************** + * Name: nrf_nvmc_get_ram_size + * + * Description: + * Get internal RAM size. + * + * Input Parameter: + * None + * + * Returned Values: + * RAM size. + * + ****************************************************************************/ + +uint32_t nrf_nvmc_get_ram_size(void); + +/**************************************************************************** + * Name: system_image_start_address + * + * Description: + * Get system image code begin address. + * + * Input Parameter: + * None + * + * Returned Values: + * Address where code starts. + * + ****************************************************************************/ + +uint32_t system_image_start_address(void); + +/**************************************************************************** + * Name: system_image_ro_section_end + * + * Description: + * Get system image end address of read only section. + * + * Input Parameter: + * None + * + * Returned Values: + * The end address of the RO section. + * + ****************************************************************************/ + +uint32_t system_image_ro_section_end(void); + +/**************************************************************************** + * Name: system_image_data_section_size + * + * Description: + * Get system image data section size + * + * Input Parameter: + * None + * + * Returned Values: + * The size of the data section. + * + ****************************************************************************/ + +uint32_t system_image_data_section_size(void); + +/**************************************************************************** + * Name: nrf_nvmc_read_dev_id0 + * + * Description: + * Get device identifier 0 + * + * Input Parameter: + * None + * + * Returned Values: + * Value of ID0 + * + ****************************************************************************/ + +uint32_t nrf_nvmc_read_dev_id0(void); + +/**************************************************************************** + * Name: nrf_nvmc_read_dev_id1 + * + * Description: + * Get device identifier 1 + * + * Input Parameter: + * None + * + * Returned Values: + * Value of ID1 + * + ****************************************************************************/ + +uint32_t nrf_nvmc_read_dev_id1(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __ARCH_ARM_SRC_NRF52_NRF52_NVMC_H */ + diff --git a/arch/arm/src/nrf52/nrf52_start.c b/arch/arm/src/nrf52/nrf52_start.c index 7ca37b95467..a440e03d90d 100644 --- a/arch/arm/src/nrf52/nrf52_start.c +++ b/arch/arm/src/nrf52/nrf52_start.c @@ -54,6 +54,7 @@ #include "nrf52_start.h" #include "nrf52_gpio.h" #include "nrf52_serial.h" +#include "nrf52_nvmc.h" /**************************************************************************** * Pre-processor Definitions @@ -220,6 +221,12 @@ void __start(void) /* Initialize the FPU (if configured) */ nrf52_fpuconfig(); + +#ifdef CONFIG_NRF52_FLASH_PREFETCH + nrf_nvmc_enable_icache(true); + nrf_nvmc_enable_profile(true); +#endif + showprogress('D'); /* Perform early serial initialization */