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arch/arm/src/s32k1xx: Bring in Cortex-M0+ Systick and interrupt handling from samd2l2; bring in Cortex-M4F Systick and interrupt handling from LPC54xx.

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This commit is contained in:
Gregory Nutt 2019-08-13 19:10:38 -06:00
parent 7be79b661c
commit e3468c8aad
11 changed files with 1439 additions and 14 deletions
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3
arch/arm/src/s32k1xx/s32k11x/Make.defs
View file

@ -58,8 +58,7 @@ endif
# Source file specific to the S32k11x family
CHIP_ASRCS =
CHIP_CSRCS = s32k11x_irq.c s32k11x_lowputc.c s32k11x_port.c s32k11x_serial.c
CHIP_CSRCS += s32k11x_lpuart.c
CHIP_CSRCS = s32k11x_irq.c
# Configuration-dependent S32k11x files

336
arch/arm/src/s32k1xx/s32k11x/s32k11x_irq.c Normal file
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@ -0,0 +1,336 @@
/****************************************************************************
* arch/arm/src/s32k1xx/s32k11x/s32k11x_irq.c
*
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <debug.h>
#include <nuttx/irq.h>
#include <nuttx/arch.h>
#include <arch/irq.h>
#include "nvic.h"
#include "up_arch.h"
#include "up_internal.h"
#include "s32k14x/s32k14x_irq.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Get a 32-bit version of the default priority */
#define DEFPRIORITY32 \
(NVIC_SYSH_PRIORITY_DEFAULT << 24 | NVIC_SYSH_PRIORITY_DEFAULT << 16 | \
NVIC_SYSH_PRIORITY_DEFAULT << 8 | NVIC_SYSH_PRIORITY_DEFAULT)
/****************************************************************************
* Public Data
****************************************************************************/
/* g_current_regs[] holds a references to the current interrupt level
* register storage structure. If is non-NULL only during interrupt
* processing. Access to g_current_regs[] must be through the macro
* CURRENT_REGS for portability.
*/
volatile uint32_t *g_current_regs[1];
/****************************************************************************
* Private Data
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: s32k11x_nmi, s32k11x_busfault, s32k11x_usagefault, s32k11x_pendsv,
* s32k11x_dbgmonitor, s32k11x_pendsv, s32k11x_reserved
*
* Description:
* Handlers for various execptions. None are handled and all are fatal
* error conditions. The only advantage these provided over the default
* unexpected interrupt handler is that they provide a diagnostic output.
*
****************************************************************************/
#ifdef CONFIG_DEBUG_FEATURES
static int s32k11x_nmi(int irq, FAR void *context, FAR void *arg)
{
(void)up_irq_save();
_err("PANIC!!! NMI received\n");
PANIC();
return 0;
}
static int s32k11x_pendsv(int irq, FAR void *context, FAR void *arg)
{
(void)up_irq_save();
_err("PANIC!!! PendSV received\n");
PANIC();
return 0;
}
static int s32k11x_reserved(int irq, FAR void *context, FAR void *arg)
{
(void)up_irq_save();
_err("PANIC!!! Reserved interrupt\n");
PANIC();
return 0;
}
#endif
/****************************************************************************
* Name: s32k11x_clrpend
*
* Description:
* Clear a pending interrupt at the NVIC.
*
****************************************************************************/
static inline void s32k11x_clrpend(int irq)
{
/* This will be called on each interrupt exit whether the interrupt can be
* enambled or not. So this assertion is necessarily lame.
*/
DEBUGASSERT((unsigned)irq < NR_IRQS);
/* Check for an external interrupt */
if (irq >= S32K1XX_IRQ_INTERRUPT && irq < S32K1XX_IRQ_INTERRUPT + S32K1XX_IRQ_NINTS)
{
/* Set the appropriate bit in the ISER register to enable the
* interrupt
*/
putreg32((1 << (irq - S32K1XX_IRQ_INTERRUPT)), ARMV6M_NVIC_ICPR);
}
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: up_irqinitialize
****************************************************************************/
void up_irqinitialize(void)
{
uint32_t regaddr;
int i;
/* Disable all interrupts */
putreg32(0xffffffff, ARMV6M_NVIC_ICER);
/* Set all interrupts (and exceptions) to the default priority */
putreg32(DEFPRIORITY32, ARMV6M_SYSCON_SHPR2);
putreg32(DEFPRIORITY32, ARMV6M_SYSCON_SHPR3);
/* Now set all of the interrupt lines to the default priority */
for (i = 0; i < 8; i++)
{
regaddr = ARMV6M_NVIC_IPR(i);
putreg32(DEFPRIORITY32, regaddr);
}
/* currents_regs is non-NULL only while processing an interrupt */
CURRENT_REGS = NULL;
/* Attach the SVCall and Hard Fault exception handlers. The SVCall
* exception is used for performing context switches; The Hard Fault
* must also be caught because a SVCall may show up as a Hard Fault
* under certain conditions.
*/
irq_attach(S32K1XX_IRQ_SVCALL, up_svcall, NULL);
irq_attach(S32K1XX_IRQ_HARDFAULT, up_hardfault, NULL);
/* Attach all other processor exceptions (except reset and sys tick) */
#ifdef CONFIG_DEBUG_FEATURES
irq_attach(S32K1XX_IRQ_NMI, s32k11x_nmi, NULL);
irq_attach(S32K1XX_IRQ_PENDSV, s32k11x_pendsv, NULL);
irq_attach(S32K1XX_IRQ_RESERVED, s32k11x_reserved, NULL);
#endif
s32k11x_dumpnvic("initial", NR_IRQS);
#ifndef CONFIG_SUPPRESS_INTERRUPTS
/* And finally, enable interrupts */
up_irq_enable();
#endif
}
/****************************************************************************
* Name: up_disable_irq
*
* Description:
* Disable the IRQ specified by 'irq'
*
****************************************************************************/
void up_disable_irq(int irq)
{
DEBUGASSERT((unsigned)irq < NR_IRQS);
/* Check for an external interrupt */
if (irq >= S32K1XX_IRQ_INTERRUPT && irq < S32K1XX_IRQ_INTERRUPT + S32K1XX_IRQ_NINTS)
{
/* Set the appropriate bit in the ICER register to disable the
* interrupt
*/
putreg32((1 << (irq - S32K1XX_IRQ_INTERRUPT)), ARMV6M_NVIC_ICER);
}
/* Handle processor exceptions. Only SysTick can be disabled */
else if (irq == S32K1XX_IRQ_SYSTICK)
{
modifyreg32(ARMV6M_SYSTICK_CSR, SYSTICK_CSR_ENABLE, 0);
}
s32k11x_dumpnvic("disable", irq);
}
/****************************************************************************
* Name: up_enable_irq
*
* Description:
* Enable the IRQ specified by 'irq'
*
****************************************************************************/
void up_enable_irq(int irq)
{
/* This will be called on each interrupt exit whether the interrupt can be
* enambled or not. So this assertion is necessarily lame.
*/
DEBUGASSERT((unsigned)irq < NR_IRQS);
/* Check for external interrupt */
if (irq >= S32K1XX_IRQ_INTERRUPT && irq < S32K1XX_IRQ_INTERRUPT + S32K1XX_IRQ_NINTS)
{
/* Set the appropriate bit in the ISER register to enable the
* interrupt
*/
putreg32((1 << (irq - S32K1XX_IRQ_INTERRUPT)), ARMV6M_NVIC_ISER);
}
/* Handle processor exceptions. Only SysTick can be disabled */
else if (irq == S32K1XX_IRQ_SYSTICK)
{
modifyreg32(ARMV6M_SYSTICK_CSR, 0, SYSTICK_CSR_ENABLE);
}
s32k11x_dumpnvic("enable", irq);
}
/****************************************************************************
* Name: up_ack_irq
*
* Description:
* Acknowledge the IRQ
*
****************************************************************************/
void up_ack_irq(int irq)
{
s32k11x_clrpend(irq);
}
/****************************************************************************
* Name: s32k11x_dumpnvic
*
* Description:
* Dump some interesting NVIC registers
*
****************************************************************************/
#ifdef CONFIG_DEBUG_IRQ_INFO
void s32k11x_dumpnvic(const char *msg, int irq)
{
irqstate_t flags;
flags = enter_critical_section();
irqinfo("NVIC (%s, irq=%d):\n", msg, irq);
irqinfo(" ISER: %08x ICER: %08x\n",
getreg32(ARMV6M_NVIC_ISER), getreg32(ARMV6M_NVIC_ICER));
irqinfo(" ISPR: %08x ICPR: %08x\n",
getreg32(ARMV6M_NVIC_ISPR), getreg32(ARMV6M_NVIC_ICPR));
irqinfo(" IRQ PRIO: %08x %08x %08x %08x\n",
getreg32(ARMV6M_NVIC_IPR0), getreg32(ARMV6M_NVIC_IPR1),
getreg32(ARMV6M_NVIC_IPR2), getreg32(ARMV6M_NVIC_IPR3));
irqinfo(" %08x %08x %08x %08x\n",
getreg32(ARMV6M_NVIC_IPR4), getreg32(ARMV6M_NVIC_IPR5),
getreg32(ARMV6M_NVIC_IPR6), getreg32(ARMV6M_NVIC_IPR7));
irqinfo("SYSCON:\n");
irqinfo(" CPUID: %08x\n",
getreg32(ARMV6M_SYSCON_CPUID));
irqinfo(" ICSR: %08x AIRCR: %08x\n",
getreg32(ARMV6M_SYSCON_ICSR), getreg32(ARMV6M_SYSCON_AIRCR));
irqinfo(" SCR: %08x CCR: %08x\n",
getreg32(ARMV6M_SYSCON_SCR), getreg32(ARMV6M_SYSCON_CCR));
irqinfo(" SHPR2: %08x SHPR3: %08x\n",
getreg32(ARMV6M_SYSCON_SHPR2), getreg32(ARMV6M_SYSCON_SHPR3));
leave_critical_section(flags);
}
#else
# define s32k11x_dumpnvic(msg, irq)
#endif

63
arch/arm/src/s32k1xx/s32k11x/s32k11x_irq.h Normal file
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@ -0,0 +1,63 @@
/****************************************************************************
* arch/arm/src/s32k1xx/s32k11x_irq.h
*
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_S32K1XX_S32K11X_S32K11X_IRQ_H
#define __ARCH_ARM_SRC_S32K1XX_S32K11X_S32K11X_IRQ_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: s32k11x_dumpnvic
*
* Description:
* Dump some interesting NVIC registers
*
****************************************************************************/
#ifdef CONFIG_DEBUG_IRQ_INFO
void s32k11x_dumpnvic(const char *msg, int irq);
#else
# define s32k11x_dumpnvic(msg, irq)
#endif
#endif /* __ARCH_ARM_SRC_S32K1XX_S32K11X_S32K11X_IRQ_H */

143
arch/arm/src/s32k1xx/s32k11x/s32k11x_timerisr.c Normal file
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@ -0,0 +1,143 @@
/****************************************************************************
* arch/arm/src/s32k1xx/s32k11x/s32k11x_timerisr.c
*
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <time.h>
#include <debug.h>
#include <nuttx/arch.h>
#include <arch/board/board.h>
#include "nvic.h"
#include "clock/clock.h"
#include "up_internal.h"
#include "up_arch.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* The desired timer interrupt frequency is provided by the definition
* CLK_TCK (see include/time.h). CLK_TCK defines the desired number of
* system clock ticks per second. That value is a user configurable setting
* that defaults to 100 (100 ticks per second = 10 MS interval).
*
* Then, for example, if the CPU clock is the SysTick and
* BOARD_CPU_FREQUENCY is 48MHz and CLK_TCK is 100, then the reload value
* would be:
*
* SYSTICK_RELOAD = (48,000,000 / 100) - 1
* = 479,999
* = 0x752ff
*
* Which fits within the maximum 24-bit reload value.
*/
#define SYSTICK_RELOAD ((BOARD_CPU_FREQUENCY / CLK_TCK) - 1)
/* The size of the reload field is 24 bits. Verify that the reload value
* will fit in the reload register.
*/
#if SYSTICK_RELOAD > 0x00ffffff
# error SYSTICK_RELOAD exceeds the range of the RELOAD register
#endif
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Function: s32k11x_timerisr
*
* Description:
* The timer ISR will perform a variety of services for various portions
* of the systems.
*
****************************************************************************/
static int s32k11x_timerisr(int irq, uint32_t *regs, void *arg)
{
/* Process timer interrupt */
nxsched_process_timer();
return 0;
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Function: arm_timer_initialize
*
* Description:
* This function is called during start-up to initialize
* the timer interrupt.
*
****************************************************************************/
void arm_timer_initialize(void)
{
uint32_t regval;
/* Set the SysTick interrupt to the default priority */
regval = getreg32(ARMV6M_SYSCON_SHPR3);
regval &= ~SYSCON_SHPR3_PRI_15_MASK;
regval |= (NVIC_SYSH_PRIORITY_DEFAULT << SYSCON_SHPR3_PRI_15_SHIFT);
putreg32(regval, ARMV6M_SYSCON_SHPR3);
/* Configure SysTick to interrupt at the requested rate */
putreg32(SYSTICK_RELOAD, ARMV6M_SYSTICK_RVR);
/* Attach the timer interrupt vector */
(void)irq_attach(SAM_IRQ_SYSTICK, (xcpt_t)s32k11x_timerisr, NULL);
/* Enable SysTick interrupts */
putreg32((SYSTICK_CSR_TICKINT | SYSTICK_CSR_ENABLE), ARMV6M_SYSTICK_CSR);
/* And enable the timer interrupt */
up_enable_irq(SAM_IRQ_SYSTICK);
}

6
arch/arm/src/s32k1xx/s32k14x/Make.defs
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@ -77,6 +77,12 @@ endif
CHIP_ASRCS =
CHIP_CSRCS = s32k14x_irq.c s32k14x_clrpend.c
# Configuration-dependent S32k14x files
ifneq ($(CONFIG_SCHED_TICKLESS),y)
CHIP_CSRCS += s32k14x_timerisr.c
endif
ifeq ($(CONFIG_BUILD_PROTECTED),y)
CHIP_CSRCS += s32k14x_userspace.c s32k14x_mpuinit.c
endif

82
arch/arm/src/s32k1xx/s32k14x/s32k14x_clrpend.c Normal file
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@ -0,0 +1,82 @@
/****************************************************************************
* arch/arm/src/s32k1xx/s32k14x/s32k14x_clrpend.c
*
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <arch/irq.h>
#include "nvic.h"
#include "up_arch.h"
#include "s32k14x_irq.h"
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: s32k14x_clrpend
*
* Description:
* Clear a pending interrupt at the NVIC. This does not seem to be required
* for most interrupts. Don't know why... but the LPC54xx Ethernet EMAC
* interrupt definitely needs it!
*
* This function is logically a part of s32k14x_irq.c, but I will keep it in
* a separate file so that it will not increase the footprint on LPC54xx
* platforms that do not need this function.
*
****************************************************************************/
void s32k14x_clrpend(int irq)
{
/* Check for external interrupt */
if (irq >= LPC54_IRQ_EXTINT)
{
if (irq < (LPC54_IRQ_EXTINT + 32))
{
putreg32(1 << (irq - LPC54_IRQ_EXTINT), NVIC_IRQ0_31_CLRPEND);
}
else if (irq < LPC54_IRQ_NIRQS)
{
putreg32(1 << (irq - LPC54_IRQ_EXTINT - 32), NVIC_IRQ32_63_CLRPEND);
}
}
}

563
arch/arm/src/s32k1xx/s32k14x/s32k14x_irq.c Normal file
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@ -0,0 +1,563 @@
/****************************************************************************
* arch/arm/src/s32k1xx/s32k14x/s32k14x_irq.c
*
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <debug.h>
#include <nuttx/irq.h>
#include <nuttx/arch.h>
#include <arch/irq.h>
#include <arch/armv7-m/nvicpri.h>
#include "chip.h"
#include "nvic.h"
#include "ram_vectors.h"
#include "up_arch.h"
#include "up_internal.h"
#include "s32k14x_gpio.h"
#include "s32k14x/s32k14x_irq.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Get a 32-bit version of the default priority */
#define DEFPRIORITY32 \
(NVIC_SYSH_PRIORITY_DEFAULT << 24 | NVIC_SYSH_PRIORITY_DEFAULT << 16 | \
NVIC_SYSH_PRIORITY_DEFAULT << 8 | NVIC_SYSH_PRIORITY_DEFAULT)
/* Given the address of a NVIC ENABLE register, this is the offset to
* the corresponding CLEAR ENABLE register.
*/
#define NVIC_ENA_OFFSET (0)
#define NVIC_CLRENA_OFFSET (NVIC_IRQ0_31_CLEAR - NVIC_IRQ0_31_ENABLE)
/****************************************************************************
* Public Data
****************************************************************************/
/* g_current_regs[] holds a references to the current interrupt level
* register storage structure. If is non-NULL only during interrupt
* processing. Access to g_current_regs[] must be through the macro
* CURRENT_REGS for portability.
*/
volatile uint32_t *g_current_regs[1];
/* This is the address of the exception vector table (determined by the
* linker script).
*/
extern uint32_t _vectors[];
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: s32k14x_dumpnvic
*
* Description:
* Dump some interesting NVIC registers
*
****************************************************************************/
#if defined(CONFIG_DEBUG_IRQ_INFO)
static void s32k14x_dumpnvic(const char *msg, int irq)
{
irqstate_t flags;
flags = enter_critical_section();
irqinfo("NVIC (%s, irq=%d):\n", msg, irq);
irqinfo(" INTCTRL: %08x VECTAB: %08x\n",
getreg32(NVIC_INTCTRL), getreg32(NVIC_VECTAB));
#if 0
irqinfo(" SYSH ENABLE MEMFAULT: %08x BUSFAULT: %08x USGFAULT: %08x SYSTICK: %08x\n",
getreg32(NVIC_SYSHCON_MEMFAULTENA), getreg32(NVIC_SYSHCON_BUSFAULTENA),
getreg32(NVIC_SYSHCON_USGFAULTENA), getreg32(NVIC_SYSTICK_CTRL_ENABLE));
#endif
irqinfo(" IRQ ENABLE: %08x %08x\n",
getreg32(NVIC_IRQ0_31_ENABLE), getreg32(NVIC_IRQ32_63_ENABLE));
irqinfo(" SYSH_PRIO: %08x %08x %08x\n",
getreg32(NVIC_SYSH4_7_PRIORITY), getreg32(NVIC_SYSH8_11_PRIORITY),
getreg32(NVIC_SYSH12_15_PRIORITY));
irqinfo(" IRQ PRIO: %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ0_3_PRIORITY), getreg32(NVIC_IRQ4_7_PRIORITY),
getreg32(NVIC_IRQ8_11_PRIORITY), getreg32(NVIC_IRQ12_15_PRIORITY));
irqinfo(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ16_19_PRIORITY), getreg32(NVIC_IRQ20_23_PRIORITY),
getreg32(NVIC_IRQ24_27_PRIORITY), getreg32(NVIC_IRQ28_31_PRIORITY));
irqinfo(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ32_35_PRIORITY), getreg32(NVIC_IRQ36_39_PRIORITY),
getreg32(NVIC_IRQ40_43_PRIORITY), getreg32(NVIC_IRQ44_47_PRIORITY));
irqinfo(" %08x %08x %08x\n",
getreg32(NVIC_IRQ48_51_PRIORITY), getreg32(NVIC_IRQ52_55_PRIORITY),
getreg32(NVIC_IRQ56_59_PRIORITY));
leave_critical_section(flags);
}
#else
# define s32k14x_dumpnvic(msg, irq)
#endif
/****************************************************************************
* Name: s32k14x_nmi, s32k14x_busfault, s32k14x_usagefault, s32k14x_pendsv,
* s32k14x_dbgmonitor, s32k14x_pendsv, s32k14x_reserved
*
* Description:
* Handlers for various exceptions. None are handled and all are fatal
* error conditions. The only advantage these provided over the default
* unexpected interrupt handler is that they provide a diagnostic output.
*
****************************************************************************/
#ifdef CONFIG_DEBUG_FEATURES
static int s32k14x_nmi(int irq, FAR void *context, FAR void *arg)
{
(void)up_irq_save();
_err("PANIC!!! NMI received\n");
PANIC();
return 0;
}
static int s32k14x_busfault(int irq, FAR void *context, FAR void *arg)
{
(void)up_irq_save();
_err("PANIC!!! Bus fault recived\n");
PANIC();
return 0;
}
static int s32k14x_usagefault(int irq, FAR void *context, FAR void *arg)
{
(void)up_irq_save();
_err("PANIC!!! Usage fault received\n");
PANIC();
return 0;
}
static int s32k14x_pendsv(int irq, FAR void *context, FAR void *arg)
{
(void)up_irq_save();
_err("PANIC!!! PendSV received\n");
PANIC();
return 0;
}
static int s32k14x_dbgmonitor(int irq, FAR void *context, FAR void *arg)
{
(void)up_irq_save();
_err("PANIC!!! Debug Monitor received\n");
PANIC();
return 0;
}
static int s32k14x_reserved(int irq, FAR void *context, FAR void *arg)
{
(void)up_irq_save();
_err("PANIC!!! Reserved interrupt\n");
PANIC();
return 0;
}
#endif
/****************************************************************************
* Name: s32k14x_prioritize_syscall
*
* Description:
* Set the priority of an exception. This function may be needed
* internally even if support for prioritized interrupts is not enabled.
*
****************************************************************************/
#ifdef CONFIG_ARMV7M_USEBASEPRI
static inline void s32k14x_prioritize_syscall(int priority)
{
uint32_t regval;
/* SVCALL is system handler 11 */
regval = getreg32(NVIC_SYSH8_11_PRIORITY);
regval &= ~NVIC_SYSH_PRIORITY_PR11_MASK;
regval |= (priority << NVIC_SYSH_PRIORITY_PR11_SHIFT);
putreg32(regval, NVIC_SYSH8_11_PRIORITY);
}
#endif
/****************************************************************************
* Name: s32k14x_irqinfo
*
* Description:
* Given an IRQ number, provide the register and bit setting to enable or
* disable the irq.
*
****************************************************************************/
static int s32k14x_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit,
uintptr_t offset)
{
int n;
DEBUGASSERT(irq >= S32K1XX_IRQ_NMI && irq < NR_IRQS);
/* Check for external interrupt */
if (irq >= S32K1XX_IRQ_EXTINT)
{
n = irq - S32K1XX_IRQ_EXTINT;
*regaddr = NVIC_IRQ_ENABLE(n) + offset;
*bit = (uint32_t)1 << (n & 0x1f);
}
/* Handle processor exceptions. Only a few can be disabled */
else
{
*regaddr = NVIC_SYSHCON;
if (irq == S32K1XX_IRQ_MEMFAULT)
{
*bit = NVIC_SYSHCON_MEMFAULTENA;
}
else if (irq == S32K1XX_IRQ_BUSFAULT)
{
*bit = NVIC_SYSHCON_BUSFAULTENA;
}
else if (irq == S32K1XX_IRQ_USAGEFAULT)
{
*bit = NVIC_SYSHCON_USGFAULTENA;
}
else if (irq == S32K1XX_IRQ_SYSTICK)
{
*regaddr = NVIC_SYSTICK_CTRL;
*bit = NVIC_SYSTICK_CTRL_ENABLE;
}
else
{
return ERROR; /* Invalid or unsupported exception */
}
}
return OK;
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: up_irqinitialize
*
* Description:
* Complete initialization of the interrupt system and enable normal,
* interrupt processing.
*
****************************************************************************/
void up_irqinitialize(void)
{
uint32_t regaddr;
#if defined(CONFIG_DEBUG_FEATURES) && !defined(CONFIG_ARMV7M_USEBASEPRI)
uint32_t regval;
#endif
int num_priority_registers;
int i;
/* Disable all interrupts */
for (i = 0; i < S32K1XX_IRQ_NEXTINT; i += 32)
{
putreg32(0xffffffff, NVIC_IRQ_CLEAR(i));
}
/* Make sure that we are using the correct vector table. The default
* vector address is 0x0000:0000 but if we are executing code that is
* positioned in SRAM or in external FLASH, then we may need to reset
* the interrupt vector so that it refers to the table in SRAM or in
* external FLASH.
*/
putreg32((uint32_t)_vectors, NVIC_VECTAB);
#ifdef CONFIG_ARCH_RAMVECTORS
/* If CONFIG_ARCH_RAMVECTORS is defined, then we are using a RAM-based
* vector table that requires special initialization.
*/
up_ramvec_initialize();
#endif
/* Set all interrupts (and exceptions) to the default priority */
putreg32(DEFPRIORITY32, NVIC_SYSH4_7_PRIORITY);
putreg32(DEFPRIORITY32, NVIC_SYSH8_11_PRIORITY);
putreg32(DEFPRIORITY32, NVIC_SYSH12_15_PRIORITY);
/* The NVIC ICTR register (bits 0-4) holds the number of of interrupt
* lines that the NVIC supports:
*
* 0 -> 32 interrupt lines, 8 priority registers
* 1 -> 64 " " " ", 16 priority registers
* 2 -> 96 " " " ", 32 priority registers
* ...
*/
num_priority_registers = (getreg32(NVIC_ICTR) + 1) * 8;
/* Now set all of the interrupt lines to the default priority */
regaddr = NVIC_IRQ0_3_PRIORITY;
while (num_priority_registers--)
{
putreg32(DEFPRIORITY32, regaddr);
regaddr += 4;
}
/* currents_regs is non-NULL only while processing an interrupt */
CURRENT_REGS = NULL;
/* Attach the SVCall and Hard Fault exception handlers. The SVCall
* exception is used for performing context switches; The Hard Fault
* must also be caught because a SVCall may show up as a Hard Fault
* under certain conditions.
*/
irq_attach(S32K1XX_IRQ_SVCALL, up_svcall, NULL);
irq_attach(S32K1XX_IRQ_HARDFAULT, up_hardfault, NULL);
/* Set the priority of the SVCall interrupt */
#ifdef CONFIG_ARCH_IRQPRIO
/* up_prioritize_irq(S32K1XX_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */
#endif
#ifdef CONFIG_ARMV7M_USEBASEPRI
s32k14x_prioritize_syscall(NVIC_SYSH_SVCALL_PRIORITY);
#endif
#ifdef CONFIG_ARM_MPU
/* If the MPU is enabled, then attach and enable the Memory Management
* Fault handler.
*/
irq_attach(S32K1XX_IRQ_MEMFAULT, up_memfault, NULL);
up_enable_irq(S32K1XX_IRQ_MEMFAULT);
#endif
/* Attach all other processor exceptions (except reset and sys tick) */
#ifdef CONFIG_DEBUG_FEATURES
irq_attach(S32K1XX_IRQ_NMI, s32k14x_nmi, NULL);
#ifndef CONFIG_ARM_MPU
irq_attach(S32K1XX_IRQ_MEMFAULT, up_memfault, NULL);
#endif
irq_attach(S32K1XX_IRQ_BUSFAULT, s32k14x_busfault, NULL);
irq_attach(S32K1XX_IRQ_USAGEFAULT, s32k14x_usagefault, NULL);
irq_attach(S32K1XX_IRQ_PENDSV, s32k14x_pendsv, NULL);
irq_attach(S32K1XX_IRQ_DBGMONITOR, s32k14x_dbgmonitor, NULL);
irq_attach(S32K1XX_IRQ_RESERVED, s32k14x_reserved, NULL);
#endif
s32k14x_dumpnvic("initial", S32K1XX_IRQ_NIRQS);
#if defined(CONFIG_DEBUG_FEATURES) && !defined(CONFIG_ARMV7M_USEBASEPRI)
/* If a debugger is connected, try to prevent it from catching hardfaults.
* If CONFIG_ARMV7M_USEBASEPRI, no hardfaults are expected in normal
* operation.
*/
regval = getreg32(NVIC_DEMCR);
regval &= ~NVIC_DEMCR_VCHARDERR;
putreg32(regval, NVIC_DEMCR);
#endif
#ifdef CONFIG_S32K1XX_GPIOIRQ
/* Initialize GPIO interrupts */
s32k14x_gpio_irqinitialize();
#endif
#ifndef CONFIG_SUPPRESS_INTERRUPTS
/* And finally, enable interrupts */
up_irq_enable();
#endif
}
/****************************************************************************
* Name: up_disable_irq
*
* Description:
* Disable the IRQ specified by 'irq'
*
****************************************************************************/
void up_disable_irq(int irq)
{
uintptr_t regaddr;
uint32_t regval;
uint32_t bit;
if (s32k14x_irqinfo(irq, &regaddr, &bit, NVIC_CLRENA_OFFSET) == 0)
{
/* Modify the appropriate bit in the register to disable the interrupt.
* For normal interrupts, we need to set the bit in the associated
* Interrupt Clear Enable register. For other exceptions, we need to
* clear the bit in the System Handler Control and State Register.
*/
if (irq >= S32K1XX_IRQ_EXTINT)
{
putreg32(bit, regaddr);
}
else
{
regval = getreg32(regaddr);
regval &= ~bit;
putreg32(regval, regaddr);
}
}
s32k14x_dumpnvic("disable", irq);
}
/****************************************************************************
* Name: up_enable_irq
*
* Description:
* Enable the IRQ specified by 'irq'
*
****************************************************************************/
void up_enable_irq(int irq)
{
uintptr_t regaddr;
uint32_t regval;
uint32_t bit;
if (s32k14x_irqinfo(irq, &regaddr, &bit, NVIC_ENA_OFFSET) == 0)
{
/* Modify the appropriate bit in the register to enable the interrupt.
* For normal interrupts, we need to set the bit in the associated
* Interrupt Set Enable register. For other exceptions, we need to
* set the bit in the System Handler Control and State Register.
*/
if (irq >= S32K1XX_IRQ_EXTINT)
{
putreg32(bit, regaddr);
}
else
{
regval = getreg32(regaddr);
regval |= bit;
putreg32(regval, regaddr);
}
}
s32k14x_dumpnvic("enable", irq);
}
/****************************************************************************
* Name: up_ack_irq
*
* Description:
* Acknowledge the IRQ
*
****************************************************************************/
void up_ack_irq(int irq)
{
s32k14x_clrpend(irq);
}
/****************************************************************************
* Name: up_prioritize_irq
*
* Description:
* Set the priority of an IRQ.
*
* Since this API is not supported on all architectures, it should be
* avoided in common implementations where possible.
*
****************************************************************************/
#ifdef CONFIG_ARCH_IRQPRIO
int up_prioritize_irq(int irq, int priority)
{
uint32_t regaddr;
uint32_t regval;
int shift;
DEBUGASSERT(irq >= S32K1XX_IRQ_MEMFAULT && irq < NR_IRQS &&
(unsigned)priority <= NVIC_SYSH_PRIORITY_MIN);
if (irq < S32K1XX_IRQ_EXTINT)
{
/* NVIC_SYSH_PRIORITY() maps {0..15} to one of three priority
* registers (0-3 are invalid)
*/
regaddr = NVIC_SYSH_PRIORITY(irq);
irq -= 4;
}
else
{
/* NVIC_IRQ_PRIORITY() maps {0..} to one of many priority registers */
irq -= S32K1XX_IRQ_EXTINT;
regaddr = NVIC_IRQ_PRIORITY(irq);
}
regval = getreg32(regaddr);
shift = ((irq & 3) << 3);
regval &= ~(0xff << shift);
regval |= (priority << shift);
putreg32(regval, regaddr);
s32k14x_dumpnvic("prioritize", irq);
return OK;
}
#endif

60
arch/arm/src/s32k1xx/s32k14x/s32k14x_irq.h Normal file
View file

@ -0,0 +1,60 @@
/****************************************************************************
* arch/arm/src/s32k1xx/s32k14x/s32k14x_irq.h
*
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_S32K1XX_S32K14X_S32K14X_IRQ_H
#define __ARCH_ARM_SRC_S32K1XX_S32K14X_S32K14X_IRQ_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: s32k14x_clrpend
*
* Description:
* Clear a pending interrupt at the NVIC. This does not seem to be
* required for most interrupts.
*
****************************************************************************/
void s32k14x_clrpend(int irq);
#endif /* __ARCH_ARM_SRC_S32K1XX_S32K14X_S32K14X_IRQ_H */

173
arch/arm/src/s32k1xx/s32k14x/s32k14x_timerisr.c Normal file
View file

@ -0,0 +1,173 @@
/****************************************************************************
* arch/arm/src/lpc54xx/lpc54_timerisr.c
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <time.h>
#include <debug.h>
#include <nuttx/arch.h>
#include <arch/board/board.h>
#include "nvic.h"
#include "clock/clock.h"
#include "up_internal.h"
#include "up_arch.h"
#include "hardware/lpc54_syscon.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* The SysTick clock may be clocked internally either by the by the system
* clock (CLKSOURCE==1) or by the SysTick function clock (CLKSOURCE==0).
* The SysTick Function clock is equal to:
*
* Fsystick = Fmainclk / SYSTICKCLKDIV
*
* Both the divider value (BOARD_SYSTICKCLKDIV) and the resulting SysTick
* function clock frequency (Fsystick, BOARD_SYSTICK_CLOCK)
*
* The desired timer interrupt frequency is provided by the definition
* CLK_TCK (see include/time.h). CLK_TCK defines the desired number of
* system clock ticks per second. That value is a user configurable setting
* that defaults to 100 (100 ticks per second = 10 MS interval).
*
* reload = (Fsystick / CLK_TICK) - 1
*
* Tips for selecting BOARD_SYSTICKCLKDIV: The resulting reload value
* should be as large as possible, but must be less than 2^24:
*
* SYSTICKDIV > Fmainclk / CLK_TCK / 2^24
*/
#define SYSTICK_RELOAD ((BOARD_SYSTICK_CLOCK / CLK_TCK) - 1)
/* The size of the reload field is 24 bits. Verify that the reload value
* will fit in the reload register.
*/
#if SYSTICK_RELOAD > 0x00ffffff
# error SYSTICK_RELOAD exceeds the range of the RELOAD register
#endif
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Function: lpc54_timerisr
*
* Description:
* The timer ISR will perform a variety of services for various portions
* of the systems.
*
****************************************************************************/
static int lpc54_timerisr(int irq, uint32_t *regs, void *arg)
{
/* Process timer interrupt */
nxsched_process_timer();
return 0;
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Function: arm_timer_initialize
*
* Description:
* This function is called during start-up to initialize
* the timer interrupt.
*
****************************************************************************/
void arm_timer_initialize(void)
{
uint32_t regval;
/* May be clocked internally by the system clock or the SysTick function
* clock. Set the SysTick clock divider in the SYSCON_SYSTICK register.
* Since this function is called early after reset, it is safe to assume
* that the SysTick is disabled and so that no reset or halt actions are
* necessary.
*/
regval = (SYSCON_SYSTICKCLKDIV_DIV(BOARD_SYSTICKCLKDIV) |
SYSCON_SYSTICKCLKDIV_REQFLAG);
putreg32(regval, LPC54_SYSCON_SYSTICKCLKDIV);
/* The request flag will be cleared when the divider change is complete */
while ((getreg32(LPC54_SYSCON_SYSTICKCLKDIV) & SYSCON_SYSTICKCLKDIV_REQFLAG) != 0)
{
}
/* Make sure that the SYSTICK clock source is set to use the SysTick
* function clock (CLKSOURCE==0).
*
* REVISIT: This is over-writted with CLKSOURCE==1 below.
*/
regval = getreg32(NVIC_SYSTICK_CTRL);
regval &= ~NVIC_SYSTICK_CTRL_CLKSOURCE;
putreg32(regval, NVIC_SYSTICK_CTRL);
/* Configure SysTick to interrupt at the requested rate */
putreg32(SYSTICK_RELOAD, NVIC_SYSTICK_RELOAD);
/* Attach the timer interrupt vector */
(void)irq_attach(LPC54_IRQ_SYSTICK, (xcpt_t)lpc54_timerisr, NULL);
/* Enable SysTick interrupts */
putreg32((NVIC_SYSTICK_CTRL_CLKSOURCE | NVIC_SYSTICK_CTRL_TICKINT |
NVIC_SYSTICK_CTRL_ENABLE), NVIC_SYSTICK_CTRL);
/* And enable the timer interrupt */
up_enable_irq(LPC54_IRQ_SYSTICK);
}

12
arch/arm/src/s32k1xx/s32k1xx_lowputc.c
View file

@ -90,7 +90,7 @@
* of the TxFIFO, read clock of the RxFIFO and synchronization of the modem
* control input pins. It must always be running when UART is enabled.
*
* The default lpuart1 ipg_clk is 66MHz (max 66.5MHz). ipg_clk is shared
* The default lpuart0 ipg_clk is 66MHz (max 66.5MHz). ipg_clk is shared
* among many modules and should not be controlled by the UART logic.
*
* The module_clock is for all the state machines, writing RxFIFO, reading
@ -99,10 +99,10 @@
* peripheral_clock without changing configuration of baud rate.
*
* The default ipg_perclk is 80MHz (max 80MHz). ipg_perclk is gated by
* CCGR5[CG12], lpuart1_clk_enable. The clock generation sequence is:
* CCGR5[CG12], lpuart0_clk_enable. The clock generation sequence is:
*
* pll3_sw_clk (480M) -> CCGR5[CG12] -> 3 bit divider cg podf=6 ->
* PLL3_80M (80Mhz) -> CDCDR1: lpuart1_clk_podf ->
* PLL3_80M (80Mhz) -> CDCDR1: lpuart0_clk_podf ->
* 6 bit divider default=1 -> LPUART0_CLK_ROOT
*
* REVISIT: This logic assumes that all dividers are at the default value
@ -138,15 +138,15 @@ void s32k1xx_lpuart_clock_enable (uint32_t base)
{
if (base == S32K1XX_LPUART0_BASE)
{
s32k1xx_clockall_lpuart1();
s32k1xx_clockall_lpuart0();
}
else if (base == S32K1XX_LPUART1_BASE)
{
s32k1xx_clockall_lpuart2();
s32k1xx_clockall_lpuart1();
}
else if (base == S32K1XX_LPUART2_BASE)
{
s32k1xx_clockall_lpuart3();
s32k1xx_clockall_lpuart2();
}
}

12
arch/arm/src/samd2l2/sam_irq.h
View file

@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/samd2l2/sam_irq.h
*
* Copyright (C) 2014 Gregory Nutt. All rights reserved.
@ -31,20 +31,20 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAMD2L2_SAM_IRQ_H
#define __ARCH_ARM_SRC_SAMD2L2_SAM_IRQ_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
/************************************************************************************
/****************************************************************************
* Public Function Prototypes
************************************************************************************/
****************************************************************************/
/****************************************************************************
* Name: sam_dumpnvic