From dde121c49d53ee4eb434e18c4108eb528e9e302c Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 21 May 2015 16:23:15 -0600 Subject: [PATCH] SAML21: Clean up a few more compilation issues --- arch/arm/src/samdl/chip/saml_gclk.h | 19 ++++++------ arch/arm/src/samdl/sam_gclk.c | 29 +++++++++++------- arch/arm/src/samdl/sam_gclk.h | 4 +-- arch/arm/src/samdl/saml_clockconfig.c | 40 ++++--------------------- configs/saml21-xplained/include/board.h | 12 ++++---- 5 files changed, 42 insertions(+), 62 deletions(-) diff --git a/arch/arm/src/samdl/chip/saml_gclk.h b/arch/arm/src/samdl/chip/saml_gclk.h index fbd6aab7a96..7c65d65acb0 100644 --- a/arch/arm/src/samdl/chip/saml_gclk.h +++ b/arch/arm/src/samdl/chip/saml_gclk.h @@ -79,15 +79,16 @@ /* Status register */ #define GCLK_SYNCHBUSY_SWRST (1 << 0) /* Bit 0: SWRST synchronization busy */ -#define GCLK_SYNCHBUSY_GENCTRL0 (1 << 2) /* Bit 2: Generator control 0 busy */ -#define GCLK_SYNCHBUSY_GENCTRL1 (1 << 3) /* Bit 3: Generator control 1 busy */ -#define GCLK_SYNCHBUSY_GENCTRL2 (1 << 4) /* Bit 4: Generator control 2 busy */ -#define GCLK_SYNCHBUSY_GENCTRL3 (1 << 5) /* Bit 5: Generator control 3 busy */ -#define GCLK_SYNCHBUSY_GENCTRL4 (1 << 6) /* Bit 6: Generator control 4 busy */ -#define GCLK_SYNCHBUSY_GENCTRL5 (1 << 7) /* Bit 7: Generator control 5 busy */ -#define GCLK_SYNCHBUSY_GENCTRL6 (1 << 8) /* Bit 8: Generator control 6 busy */ -#define GCLK_SYNCHBUSY_GENCTRL7 (1 << 9) /* Bit 9: Generator control 7 busy */ -#define GCLK_SYNCHBUSY_GENCTRL8 (1 << 10) /* Bit 10: Generator control 8 busy */ +#define GCLK_SYNCHBUSY_GENCTRL(n) (1 << ((n) + 2)) /* Bit n+2: Generator control n busy */ +# define GCLK_SYNCHBUSY_GENCTRL0 (1 << 2) /* Bit 2: Generator control 0 busy */ +# define GCLK_SYNCHBUSY_GENCTRL1 (1 << 3) /* Bit 3: Generator control 1 busy */ +# define GCLK_SYNCHBUSY_GENCTRL2 (1 << 4) /* Bit 4: Generator control 2 busy */ +# define GCLK_SYNCHBUSY_GENCTRL3 (1 << 5) /* Bit 5: Generator control 3 busy */ +# define GCLK_SYNCHBUSY_GENCTRL4 (1 << 6) /* Bit 6: Generator control 4 busy */ +# define GCLK_SYNCHBUSY_GENCTRL5 (1 << 7) /* Bit 7: Generator control 5 busy */ +# define GCLK_SYNCHBUSY_GENCTRL6 (1 << 8) /* Bit 8: Generator control 6 busy */ +# define GCLK_SYNCHBUSY_GENCTRL7 (1 << 9) /* Bit 9: Generator control 7 busy */ +# define GCLK_SYNCHBUSY_GENCTRL8 (1 << 10) /* Bit 10: Generator control 8 busy */ /* General clock generator n */ diff --git a/arch/arm/src/samdl/sam_gclk.c b/arch/arm/src/samdl/sam_gclk.c index 2b875563cd8..56d978a68c1 100644 --- a/arch/arm/src/samdl/sam_gclk.c +++ b/arch/arm/src/samdl/sam_gclk.c @@ -63,22 +63,31 @@ * Name: sam_gclck_waitsyncbusy * * Description: - * What until the SYNCBUSY bit is cleared. This bit is cleared when the - * synchronization of registers between the clock domains is complete. - * This bit is set when the synchronization of registers between clock - * domains is started. + * What until the SYNCBUSY bit is cleared. The SYNCBUSY bit was set when + * the synchronization of registers between clock domains is started. The + * SYNCBUSY bit is cleared when the synchronization of registers between + * the clock domains is complete. * * Input Parameters: - * None + * glck - GCLK clock index * * Returned Value: * None * ****************************************************************************/ -static void sam_gclck_waitsyncbusy(void) +static void sam_gclck_waitsyncbusy(uint8_t gclk) { +#if defined(CONFIG_ARCH_FAMILY_SAMD20) while ((getreg8(SAM_GCLK_STATUS) & GCLK_STATUS_SYNCBUSY) != 0); + +#elif defined(CONFIG_ARCH_FAMILY_SAML21) + uintptr_t gclkbit = GCLK_SYNCHBUSY_GENCTRL(gclk); + while ((getreg8(SAM_GCLK_SYNCHBUSY) & gclkbit) != 0); + +#else +# error Unrecognized SAMD/L architecture +#endif } /**************************************************************************** @@ -174,7 +183,7 @@ void sam_gclk_config(FAR const struct sam_gclkconfig_s *config) /* Wait for synchronization */ - sam_gclck_waitsyncbusy(); + sam_gclck_waitsyncbusy(config->gclk); /* Select the generator */ @@ -183,7 +192,7 @@ void sam_gclk_config(FAR const struct sam_gclkconfig_s *config) /* Wait for synchronization */ - sam_gclck_waitsyncbusy(); + sam_gclck_waitsyncbusy(config->gclk); /* Write the new generator configuration */ @@ -191,7 +200,7 @@ void sam_gclk_config(FAR const struct sam_gclkconfig_s *config) /* Wait for synchronization */ - sam_gclck_waitsyncbusy(); + sam_gclck_waitsyncbusy(config->gclk); /* Enable the clock generator */ @@ -200,7 +209,7 @@ void sam_gclk_config(FAR const struct sam_gclkconfig_s *config) /* Wait for synchronization */ - sam_gclck_waitsyncbusy(); + sam_gclck_waitsyncbusy(config->gclk); } /**************************************************************************** diff --git a/arch/arm/src/samdl/sam_gclk.h b/arch/arm/src/samdl/sam_gclk.h index 7c91b7f111d..109336108a9 100644 --- a/arch/arm/src/samdl/sam_gclk.h +++ b/arch/arm/src/samdl/sam_gclk.h @@ -63,6 +63,8 @@ * Public Types ****************************************************************************/ +#ifndef __ASSEMBLY__ + /* This structure describes the configuration of one GCLK */ struct sam_gclkconfig_s @@ -78,8 +80,6 @@ struct sam_gclkconfig_s * Inline Functions ****************************************************************************/ -#ifndef __ASSEMBLY__ - /**************************************************************************** * Public Data ****************************************************************************/ diff --git a/arch/arm/src/samdl/saml_clockconfig.c b/arch/arm/src/samdl/saml_clockconfig.c index db805ffe79a..fcf6a014edc 100644 --- a/arch/arm/src/samdl/saml_clockconfig.c +++ b/arch/arm/src/samdl/saml_clockconfig.c @@ -787,7 +787,7 @@ static inline void sam_osc16m_config(void) * BOARD_DFLL48M_FINEVALUE - Value * * Closed loop mode only: - * BOARD_DFLL48M_SRCGCLKGEN - See GCLK_CLKCTRL_GEN* definitions + * BOARD_DFLL48M_REFCLK_CLKGEN - See GCLK_PCHCTRL_GEN* definitions * BOARD_DFLL48M_MULTIPLIER - Value * BOARD_DFLL48M_MAXCOARSESTEP - Value * BOARD_DFLL48M_MAXFINESTEP - Value @@ -936,7 +936,7 @@ static inline void sam_dfll48m_enable(void) * Enable DFLL reference clock if in closed loop mode. * Depends on: * - * BOARD_DFLL48M_SRCGCLKGEN - See GCLK_CLKCTRL_GEN* definitions + * BOARD_DFLL48M_REFCLK_CLKGEN - See GCLK_PCHCTRL_GEN* definitions * * Input Parameters: * None @@ -950,37 +950,7 @@ static inline void sam_dfll48m_enable(void) !defined(BOARD_DFLL48M_OPENLOOP) static inline void sam_dfll48m_refclk(void) { - uint16_t regval; - - /* Disabled the DFLL reference clock */ - - regval = GCLK_CLKCTRL_ID_DFLL48M; - putreg16(regval, SAM_GCLK_CLKCTRL); - - /* Wait for the clock to become disabled */ - - while ((getreg16(SAM_GCLK_CLKCTRL) & GCLK_CLKCTRL_CLKEN) != 0); - - /* Select the configured clock generator as the source for the DFLL - * reference clock. - * - * NOTE: We could enable write lock here to prevent further modification - */ - - regval = (BOARD_DFLL48M_SRCGCLKGEN | GCLK_CLKCTRL_ID_DFLL48M); - putreg16(regval, SAM_GCLK_CLKCTRL); - - /* Enable the DFLL reference clock */ - - regval |= GCLK_CLKCTRL_CLKEN; - putreg16(regval, SAM_GCLK_CLKCTRL); - - /* The CLKCTRL.CLKEN bit must be synchronized to the generic clock domain. - * CLKCTRL.CLKEN will continue to read as its previous state until the - * synchronization is complete. - */ - - while ((getreg16(SAM_GCLK_CLKCTRL) & GCLK_CLKCTRL_CLKEN) == 0); + sam_gclk_chan_enable(GCLK_CHAN_DFLL48M_REF, BOARD_DFLL48M_REFCLK_CLKGEN); } #else # define sam_dfll48m_refclk() @@ -1123,9 +1093,9 @@ static inline void sam_fdpll96m_config(void) * * BOARD_FDPLL96M_ENABLE - Boolean (defined / not defined) * BOARD_FDPLL96M_REFCLK - See OSCCTRL_DPLLCTRLB_REFLCK_* definitions - * BOARD_FDPLL96M_REFCLK_CLKGEN - See GCLK_CLKCTRL_GEN* definitions + * BOARD_FDPLL96M_REFCLK_CLKGEN - See GCLK_PCHCTRL_GEN* definitions * BOARD_FDPLL96M_LOCKTIME_ENABLE - Boolean (defined / not defined) - * BOARD_FDPLL96M_LOCKTIME_CLKGEN - See GCLK_CLKCTRL_GEN* definitions + * BOARD_FDPLL96M_LOCKTIME_CLKGEN - See GCLK_PCHCTRL_GEN* definitions * * Input Parameters: * None diff --git a/configs/saml21-xplained/include/board.h b/configs/saml21-xplained/include/board.h index 0c8cff538c1..5a453a19eda 100644 --- a/configs/saml21-xplained/include/board.h +++ b/configs/saml21-xplained/include/board.h @@ -192,7 +192,7 @@ * BOARD_DFLL48M_FINEVALUE - Value * * Closed loop mode only: - * BOARD_DFLL48M_GCLKGEN - See GCLK_CLKCTRL_GEN* definitions + * BOARD_DFLL48M_REFCLK_CLKGEN - See GCLK_PCHCTRL_GEN* definitions * BOARD_DFLL48M_MULTIPLIER - Value * BOARD_DFLL48M_MAXCOARSESTEP - Value * BOARD_DFLL48M_MAXFINESTEP - Value @@ -215,7 +215,7 @@ /* DFLL closed loop mode configuration */ -#define BOARD_DFLL48M_SRCGCLKGEN GCLK_CLKCTRL_GEN1 +#define BOARD_DFLL48M_REFCLK_CLKGEN GCLK_PCHCTRL_GEN1 #define BOARD_DFLL48M_MULTIPLIER 12 #define BOARD_DFLL48M_QUICKLOCK 1 #define BOARD_DFLL48M_TRACKAFTERFINELOCK 1 @@ -236,10 +236,10 @@ * BOARD_FDPLL96M_LPEN - Boolean (defined / not defined) * BOARD_FDPLL96M_FILTER - See OSCCTRL_DPLLCTRLB_FILTER_* definitions * BOARD_FDPLL96M_REFCLK - See OSCCTRL_DPLLCTRLB_REFLCK_* definitions - * BOARD_FDPLL96M_REFCLK_CLKGEN - See GCLK_CLKCTRL_GEN* definitions + * BOARD_FDPLL96M_REFCLK_CLKGEN - See GCLK_PCHCTRL_GEN* definitions * BOARD_FDPLL96M_LOCKTIME_ENABLE - Boolean (defined / not defined) * BOARD_FDPLL96M_LOCKTIME - See OSCCTRL_DPLLCTRLB_LTIME_* definitions - * BOARD_FDPLL96M_LOCKTIME_CLKGEN - See GCLK_CLKCTRL_GEN* definitions + * BOARD_FDPLL96M_LOCKTIME_CLKGEN - See GCLK_PCHCTRL_GEN* definitions * BOARD_FDPLL96M_REFDIV - Numeric value, 1 - 2047 * BOARD_FDPLL96M_PRESCALER - See OSCCTRL_DPLLPRESC_* definitions * BOARD_FDPLL96M_REFFREQ - Numeric value @@ -254,10 +254,10 @@ #undef BOARD_FDPLL96M_LPEN #define BOARD_FDPLL96M_FILTER OSCCTRL_DPLLCTRLB_FILTER_DEFAULT #define BOARD_FDPLL96M_REFCLK OSCCTRL_DPLLCTRLB_REFLCK_XOSCK32K -#define BOARD_FDPLL96M_REFCLK_CLKGEN GCLK_CLKCTRL_GEN1 +#define BOARD_FDPLL96M_REFCLK_CLKGEN GCLK_PCHCTRL_GEN1 #undef BOARD_FDPLL96M_LOCKTIME_ENABLE #define BOARD_FDPLL96M_LOCKTIME OSCCTRL_DPLLCTRLB_LTIME_NONE -#define BOARD_FDPLL96M_LOCKTIME_CLKGEN GCLK_CLKCTRL_GEN1 +#define BOARD_FDPLL96M_LOCKTIME_CLKGEN GCLK_PCHCTRL_GEN1 #define BOARD_FDPLL96M_REFDIV 1 #define BOARD_FDPLL96M_PRESCALER OSCCTRL_DPLLPRESC_DIV1