From dd0c546eac3fa55e7d475467e12d3abea0af7384 Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Mon, 18 May 2026 18:02:30 +0200 Subject: [PATCH] !arch/stm32u5: use common STM32 Kconfig symbols BREAKING CHANGE: STM32U5 Kconfig symbols were renamed from CONFIG_STM32U5_* to CONFIG_STM32_*. Out-of-tree code must update defconfigs and Kconfig references to the new CONFIG_STM32_* names. The custom clock option is a special breaking case that does not follow the family-to-common pattern: CONFIG_ARCH_BOARD_STM32U5_CUSTOM_CLOCKCONFIG was renamed to CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG. Signed-off-by: raiden00pl --- .../stm32u5/boards/b-u585i-iot02a/index.rst | 6 +- arch/arm/Kconfig | 1 + arch/arm/include/stm32u5/chip.h | 8 +- arch/arm/include/stm32u5/irq.h | 4 +- arch/arm/include/stm32u5/stm32u5xx_irq.h | 8 +- arch/arm/src/stm32u5/Kconfig | 3637 +---------------- arch/arm/src/stm32u5/hardware/stm32_flash.h | 32 +- .../src/stm32u5/hardware/stm32_memorymap.h | 4 +- arch/arm/src/stm32u5/hardware/stm32_pinmap.h | 2 +- arch/arm/src/stm32u5/hardware/stm32_spi.h | 4 +- arch/arm/src/stm32u5/hardware/stm32_syscfg.h | 2 +- arch/arm/src/stm32u5/hardware/stm32u5xx_rcc.h | 4 +- arch/arm/src/stm32u5/hardware/stm32u5xx_spi.h | 4 +- .../src/stm32u5/hardware/stm32u5xx_syscfg.h | 4 +- arch/arm/src/stm32u5/stm32_allocateheap.c | 22 +- arch/arm/src/stm32u5/stm32_dbgmcu.h | 2 +- arch/arm/src/stm32u5/stm32_exti.h | 2 +- arch/arm/src/stm32u5/stm32_flash.c | 6 +- arch/arm/src/stm32u5/stm32_gpio.h | 2 +- arch/arm/src/stm32u5/stm32_i2c.c | 96 +- arch/arm/src/stm32u5/stm32_i2c.h | 8 +- arch/arm/src/stm32u5/stm32_idle.c | 2 +- arch/arm/src/stm32u5/stm32_lse.c | 20 +- arch/arm/src/stm32u5/stm32_rcc.c | 10 +- arch/arm/src/stm32u5/stm32_rcc.h | 10 +- arch/arm/src/stm32u5/stm32_serial.c | 96 +- arch/arm/src/stm32u5/stm32_spi.c | 118 +- arch/arm/src/stm32u5/stm32_spi.h | 12 +- arch/arm/src/stm32u5/stm32_start.c | 2 +- arch/arm/src/stm32u5/stm32_tim.c | 246 +- arch/arm/src/stm32u5/stm32_tim_lowerhalf.c | 56 +- arch/arm/src/stm32u5/stm32_uart.h | 104 +- arch/arm/src/stm32u5/stm32u5xx_rcc.c | 160 +- .../b-u585i-iot02a/configs/nsh/defconfig | 9 +- .../stm32u5/b-u585i-iot02a/src/CMakeLists.txt | 2 +- .../arm/stm32u5/b-u585i-iot02a/src/Makefile | 2 +- .../b-u585i-iot02a/src/stm32_clockconfig.c | 4 +- .../stm32u5/b-u585i-iot02a/src/stm32_spi.c | 18 +- .../nucleo-u5a5zj-q/configs/nsh/defconfig | 17 +- .../nucleo-u5a5zj-q/src/CMakeLists.txt | 2 +- .../arm/stm32u5/nucleo-u5a5zj-q/src/Makefile | 2 +- .../nucleo-u5a5zj-q/src/stm32_clockconfig.c | 4 +- .../stm32u5/nucleo-u5a5zj-q/src/stm32_spi.c | 18 +- 43 files changed, 702 insertions(+), 4070 deletions(-) diff --git a/Documentation/platforms/arm/stm32u5/boards/b-u585i-iot02a/index.rst b/Documentation/platforms/arm/stm32u5/boards/b-u585i-iot02a/index.rst index 38846fffccc..60af81e77fa 100644 --- a/Documentation/platforms/arm/stm32u5/boards/b-u585i-iot02a/index.rst +++ b/Documentation/platforms/arm/stm32u5/boards/b-u585i-iot02a/index.rst @@ -102,9 +102,9 @@ NOTES: output on USART3, as described above under "Serial Console". The elevant configuration settings are listed below:: - CONFIG_STM32L5_USART3=y - CONFIG_STM32L5_USART3_SERIALDRIVER=y - CONFIG_STM32L5_USART=y + CONFIG_STM32_USART3=y + CONFIG_STM32_USART3_SERIALDRIVER=y + CONFIG_STM32_USART=y CONFIG_USART3_SERIALDRIVER=y CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 44d1ec4da3c..7fedd0258bc 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -630,6 +630,7 @@ config ARCH_CHIP_STM32L5 config ARCH_CHIP_STM32U5 bool "STMicro STM32 U5" + select ARCH_CHIP_STM32 select ARCH_CORTEXM33 select ARCH_HAVE_MPU select ARM_HAVE_DSP diff --git a/arch/arm/include/stm32u5/chip.h b/arch/arm/include/stm32u5/chip.h index 887ca72d38a..e0590348d6f 100644 --- a/arch/arm/include/stm32u5/chip.h +++ b/arch/arm/include/stm32u5/chip.h @@ -36,11 +36,11 @@ #if defined(CONFIG_STM32U5_STM32U535XX) || defined(CONFIG_STM32U5_STM32U545XX) # define STM32_SRAM1_SIZE (0x00030000) /* 192Kb SRAM1 */ # define STM32_SRAM2_SIZE (0x00010000) /* 64kB SRAM2 */ -#elif defined(CONFIG_STM32U5_STM32U575XX) || defined(CONFIG_STM32U5_STM32U585XX) +#elif defined(CONFIG_STM32U5_STM32U575XX) || defined(CONFIG_STM32_STM32U585XX) # define STM32_SRAM1_SIZE (0x00030000) /* 192Kb SRAM1 */ # define STM32_SRAM2_SIZE (0x00010000) /* 64kB SRAM2 */ # define STM32_SRAM3_SIZE (0x00080000) /* 512kB SRAM3 */ -#elif defined(CONFIG_STM32U5_STM32U59XX) || defined(CONFIG_STM32U5_STM32U59AXX) || defined(CONFIG_STM32U5_STM32U5A5XX) || defined(CONFIG_STM32U5_STM32U5A9XX) +#elif defined(CONFIG_STM32U5_STM32U59XX) || defined(CONFIG_STM32U5_STM32U59AXX) || defined(CONFIG_STM32_STM32U5A5XX) || defined(CONFIG_STM32U5_STM32U5A9XX) # define STM32_SRAM1_SIZE (0x000C0000) /* 768Kb SRAM1 */ # define STM32_SRAM2_SIZE (0x00010000) /* 64kB SRAM2 */ # define STM32_SRAM3_SIZE (0x000d0000) /* 832kB SRAM3 */ @@ -49,7 +49,7 @@ # error "Unsupported STM32U5 chip" #endif -#if defined(CONFIG_STM32U5_STM32U585XX) || defined(CONFIG_STM32U5_STM32U5A5XX) +#if defined(CONFIG_STM32_STM32U585XX) || defined(CONFIG_STM32_STM32U5A5XX) # define STM32_NFSMC 1 /* Have FSMC memory controller */ # define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ # define STM32_NGTIM32 2 /* 32-bit general timers TIM2 and 5 with DMA */ @@ -78,7 +78,7 @@ # define STM32_NCRC 1 /* CRC */ # define STM32_NCOMP 2 /* Comparators */ # define STM32_NOPAMP 2 /* Operational Amplifiers */ -#endif /* CONFIG_STM32U5_STM32U585XX */ +#endif /* CONFIG_STM32_STM32U585XX */ #if defined(CONFIG_STM32U5_STM32U5A5ZJT) # define STM32_NUSBOTGHS 1 /* USB OTG HS */ diff --git a/arch/arm/include/stm32u5/irq.h b/arch/arm/include/stm32u5/irq.h index 77c5c600bde..9810b119e02 100644 --- a/arch/arm/include/stm32u5/irq.h +++ b/arch/arm/include/stm32u5/irq.h @@ -34,9 +34,9 @@ #include #if defined(CONFIG_STM32U5_STM32U535XX) || defined(CONFIG_STM32U5_STM32U545XX) || \ - defined(CONFIG_STM32U5_STM32U575XX) || defined(CONFIG_STM32U5_STM32U585XX) || \ + defined(CONFIG_STM32U5_STM32U575XX) || defined(CONFIG_STM32_STM32U585XX) || \ defined(CONFIG_STM32U5_STM32U59XX) || defined(CONFIG_STM32U5_STM32U59AXX) || \ - defined(CONFIG_STM32U5_STM32U5A5XX) || defined(CONFIG_STM32U5_STM32U5A9XX) + defined(CONFIG_STM32_STM32U5A5XX) || defined(CONFIG_STM32U5_STM32U5A9XX) # include #else # error "Unsupported STM32U5 chip" diff --git a/arch/arm/include/stm32u5/stm32u5xx_irq.h b/arch/arm/include/stm32u5/stm32u5xx_irq.h index f1042c3d4a9..e29a074fde6 100644 --- a/arch/arm/include/stm32u5/stm32u5xx_irq.h +++ b/arch/arm/include/stm32u5/stm32u5xx_irq.h @@ -131,10 +131,10 @@ #define STM32_IRQ_TIM17 (STM32_IRQ_FIRST + 71) /* 71: TIM17 global interrupt */ #define STM32_IRQ_COMP (STM32_IRQ_FIRST + 72) /* 72: COMP1/COMP2 interrupts */ #if defined(CONFIG_STM32U5_STM32U535XX) || defined(CONFIG_STM32U5_STM32U545XX) || \ - defined(CONFIG_STM32U5_STM32U575XX) || defined(CONFIG_STM32U5_STM32U585XX) + defined(CONFIG_STM32U5_STM32U575XX) || defined(CONFIG_STM32_STM32U585XX) # define STM32_IRQ_OTG_FS (STM32_IRQ_FIRST + 73) /* 73: USB OTG FS global interrupt */ #elif defined(CONFIG_STM32U5_STM32U59XX) || defined(CONFIG_STM32U5_STM32U59AXX) || \ - defined(CONFIG_STM32U5_STM32U5A5XX) || defined(CONFIG_STM32U5_STM32U5A9XX) + defined(CONFIG_STM32_STM32U5A5XX) || defined(CONFIG_STM32U5_STM32U5A9XX) # define STM32_IRQ_OTG_HS (STM32_IRQ_FIRST + 73) /* 73: USB OTG HS global interrupt */ #else # error "Unsupported STM32U5 chip" @@ -192,9 +192,9 @@ #define STM32_IRQ_FMAC (STM32_IRQ_FIRST + 124) /* 124: FMAC interrupt */ #if defined(CONFIG_STM32U5_STM32U535XX) || defined(CONFIG_STM32U5_STM32U545XX) || \ - defined(CONFIG_STM32U5_STM32U575XX) || defined(CONFIG_STM32U5_STM32U585XX) || \ + defined(CONFIG_STM32U5_STM32U575XX) || defined(CONFIG_STM32_STM32U585XX) || \ defined(CONFIG_STM32U5_STM32U59XX) || defined(CONFIG_STM32U5_STM32U59AXX) || \ - defined(CONFIG_STM32U5_STM32U5A5XX) || defined(CONFIG_STM32U5_STM32U5A9XX) + defined(CONFIG_STM32_STM32U5A5XX) || defined(CONFIG_STM32U5_STM32U5A9XX) # define STM32_IRQ_NEXTINTS 125 #else # error "Unsupported STM32U5 chip" diff --git a/arch/arm/src/stm32u5/Kconfig b/arch/arm/src/stm32u5/Kconfig index 0a6b6cff64f..95e927f8b46 100644 --- a/arch/arm/src/stm32u5/Kconfig +++ b/arch/arm/src/stm32u5/Kconfig @@ -7,6 +7,71 @@ if ARCH_CHIP_STM32U5 comment "STM32U5 Configuration Options" +config STM32_U5_PERIPHERALS + bool + default y + select STM32_HAVE_COMP + select STM32_HAVE_CRS + select STM32_HAVE_DAC1 + select STM32_HAVE_DMA2D + select STM32_HAVE_FMAC + select STM32_HAVE_FSMC + select STM32_HAVE_HASH + select STM32_HAVE_I2C1 + select STM32_HAVE_I2C2 + select STM32_HAVE_I2C3 + select STM32_HAVE_I2C4 + select STM32_HAVE_LPTIM1 + select STM32_HAVE_LPTIM3 + select STM32_HAVE_LPTIM4 + select STM32_HAVE_LPUART1 + select STM32_HAVE_OTGFS if STM32_STM32U535XX || CONFIG_STM32_STM32U545XX || STM32_STM32U575XX || STM32_STM32U585XX + select STM32_HAVE_RNG + select STM32_HAVE_SAI1 + select STM32_HAVE_SAI2 + select STM32_HAVE_SDMMC1 + select STM32_HAVE_SDMMC2 + select STM32_HAVE_SPI1 + select STM32_HAVE_SPI2 + select STM32_HAVE_SPI3 + select STM32_HAVE_SYSCFG + select STM32_HAVE_TSC + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + select STM32_HAVE_USART1 + select STM32_HAVE_USART2 + select STM32_HAVE_USART3 + select STM32_HAVE_GPADMA1 + select STM32_HAVE_MDF1 + select STM32_HAVE_FLASH + select STM32_HAVE_RAMCFG + select STM32_HAVE_GTZC1 + select STM32_HAVE_GTZC2 + select STM32_HAVE_DCACHE1 + select STM32_HAVE_SRAM1 + select STM32_HAVE_SRAM2 + select STM32_HAVE_SRAM3 + select STM32_HAVE_SRAM5 + select STM32_HAVE_DCMI_PSSI + select STM32_HAVE_PKA + select STM32_HAVE_SAES + select STM32_HAVE_OCTOSPIM + select STM32_HAVE_OTFDEC1 + select STM32_HAVE_OTFDEC2 + select STM32_HAVE_OCTOSPI1 + select STM32_HAVE_OCTOSPI2 + select STM32_HAVE_LPGPIO1 + select STM32_HAVE_LPDMA1 + select STM32_HAVE_ADF1 + select STM32_HAVE_UCPD1 + select STM32_HAVE_VREF + select STM32_HAVE_RTCAPB + select STM32_HAVE_RTC_MAGIC + select STM32_HAVE_CRC + select STM32_HAVE_PWR + select STM32_HAVE_BKPSRAM + select STM32_HAVE_IP_WDG_M3M4_V1 + choice prompt "STM32 U5 Chip Selection" default ARCH_CHIP_STM32U585AI @@ -14,15 +79,15 @@ choice config ARCH_CHIP_STM32U585AI bool "STM32U585AI" - select STM32U5_STM32U585XX - select STM32U5_FLASH_CONFIG_I + select STM32_STM32U585XX + select STM32_FLASH_CONFIG_I select STM32U5_IO_CONFIG_A ---help--- STM32 U5 Cortex M33, 2048 Kb FLASH, 768 Kb SRAM config ARCH_CHIP_STM32U5A5ZJT bool "STM32U5A5ZJT" - select STM32U5_STM32U5A5XX + select STM32_STM32U5A5XX select STM32U5_IO_CONFIG_A ---help--- STM32 U5 Cortex M33, 4096 Kb FLASH, 2500 Kb SRAM, tqfp144 @@ -31,3551 +96,115 @@ endchoice # STM32 U5 Chip Selection # Chip families: -config STM32U5_STM32U5A5XX - # STM32U575 and STM32U585 devices documented in RM0456 +# STM32U575 and STM32U585 devices documented in RM0456 +config STM32_STM32U5A5XX + bool + default n + select STM32_HAVE_OTGHS + select ARCH_HAVE_FPU + select STM32_HAVE_AES + select STM32_HAVE_CORDIC + select STM32_HAVE_IP_AES_M3M4_V1 + select STM32_HAVE_IP_CORDIC_M3M4_V1 + select STM32_HAVE_LPUART1 + select STM32_HAVE_USART1 + select STM32_HAVE_USART2 + select STM32_HAVE_USART3 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + select STM32_HAVE_FDCAN1 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM8 + select STM32_HAVE_TIM15 + select STM32_HAVE_TIM16 + select STM32_HAVE_TIM17 + select STM32_HAVE_I2C5 + select STM32_HAVE_I2C6 + +# STM32U575 and STM32U585 devices documented in RM0456 +config STM32_STM32U585XX bool default n select ARCH_HAVE_FPU - select STM32U5_HAVE_LPUART1 - select STM32U5_HAVE_USART1 - select STM32U5_HAVE_USART2 - select STM32U5_HAVE_USART3 - select STM32U5_HAVE_UART4 - select STM32U5_HAVE_UART5 - -config STM32U5_STM32U585XX - # STM32U575 and STM32U585 devices documented in RM0456 - bool - default n - select ARCH_HAVE_FPU - select STM32U5_HAVE_LPUART1 - select STM32U5_HAVE_USART1 - select STM32U5_HAVE_USART2 - select STM32U5_HAVE_USART3 - select STM32U5_HAVE_UART4 - select STM32U5_HAVE_UART5 - -choice - prompt "Override Flash Size Designator" - depends on ARCH_CHIP_STM32U5 - default STM32U5_FLASH_OVERRIDE_DEFAULT - ---help--- - STM32U5 series parts numbering (sans the package type) ends with a letter - that designates the FLASH size. - - Designator Size in KiB - 8 64 - B 128 - C 256 - E 512 - G 1024 - I 2048 - - This configuration option defaults to using the configuration based on that designator - or the default smaller size if there is no last character designator is present in the - STM32 Chip Selection. - - Examples: - If the STM32U585AI is chosen, the Flash configuration would be 'I', if a variant of - the part with a 1024 KiB Flash is released in the future one could simply select - the 'G' designator here. - - If an STM32U5xxx Series parts is chosen the default Flash configuration will be set - herein and can be changed. - -config STM32U5_FLASH_OVERRIDE_DEFAULT - bool "Default" - -config STM32U5_FLASH_OVERRIDE_8 - bool "8 64 KB" - -config STM32U5_FLASH_OVERRIDE_B - bool "B 128 KB" - -config STM32U5_FLASH_OVERRIDE_C - bool "C 256 KB" - -config STM32U5_FLASH_OVERRIDE_E - bool "E 512 KB" - -config STM32U5_FLASH_OVERRIDE_G - bool "G 1024 KB" - -config STM32U5_FLASH_OVERRIDE_I - bool "I 2048 KB" - -endchoice # "Override Flash Size Designator" - -# Flash configurations - -config STM32U5_FLASH_CONFIG_8 - bool - default n - -config STM32U5_FLASH_CONFIG_B - bool - default n - -config STM32U5_FLASH_CONFIG_C - bool - default n - -config STM32U5_FLASH_CONFIG_E - bool - default n - -config STM32U5_FLASH_CONFIG_G - bool - default n - -config STM32U5_FLASH_CONFIG_I - bool - default n + select STM32_HAVE_AES + select STM32_HAVE_CORDIC + select STM32_HAVE_IP_AES_M3M4_V1 + select STM32_HAVE_IP_CORDIC_M3M4_V1 + select STM32_HAVE_LPUART1 + select STM32_HAVE_USART1 + select STM32_HAVE_USART2 + select STM32_HAVE_USART3 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + select STM32_HAVE_FDCAN1 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM8 + select STM32_HAVE_TIM15 + select STM32_HAVE_TIM16 + select STM32_HAVE_TIM17 # Pin/package configurations config STM32U5_IO_CONFIG_K + # Package designator K bool default n config STM32U5_IO_CONFIG_T + # Package designator T bool default n config STM32U5_IO_CONFIG_C + # Package designator C bool default n config STM32U5_IO_CONFIG_R + # Package designator R bool default n config STM32U5_IO_CONFIG_J + # Package designator J bool default n config STM32U5_IO_CONFIG_M + # Package designator M bool default n config STM32U5_IO_CONFIG_V + # Package designator V bool default n config STM32U5_IO_CONFIG_Q + # Package designator Q bool default n config STM32U5_IO_CONFIG_Z + # Package designator Z bool default n config STM32U5_IO_CONFIG_A + # Package designator A bool default n -comment "STM32U5 Peripherals" - -menu "STM32U5 Peripheral Support" - -# These "hidden" settings determine is a peripheral option is available for the -# selection MCU - -config STM32U5_HAVE_LPUART1 - bool - default n - -config STM32U5_HAVE_USART1 - bool - default n - -config STM32U5_HAVE_USART2 - bool - default n - -config STM32U5_HAVE_USART3 - bool - default n - -config STM32U5_HAVE_UART4 - bool - default n - -config STM32U5_HAVE_UART5 - bool - default n - -# These "hidden" settings are the OR of individual peripheral selections -# indicating that the general capability is required. - -config STM32U5_SPI - bool - default n - -config STM32U5_PWM - bool - default n - -config STM32U5_USART - bool - default n - -# These are the peripheral selections proper - -comment "AHB1 Peripherals" - -config STM32U5_GPADMA1 - bool "GPADMA1" - default n - -config STM32U5_CORDIC - bool "CORDIC" - default n - -config STM32U5_FMAC - bool "FMAC" - default n - -config STM32U5_MDF1 - bool "MDF1" - default n - -config STM32U5_FLASH - bool "FLASH" - default n - -config STM32U5_CRC - bool "CRC" - default n - -config STM32U5_TSC - bool "TSC" - default n - -config STM32U5_RAMCFG - bool "RAMCFG" - default n - -config STM32U5_DMA2D - bool "DMA2D" - default n - -config STM32U5_GTZC1 - bool "GTZC1" - default n - -config STM32U5_BKPSRAM - bool "BKPSRAM" - default n - -config STM32U5_DCACHE1 - bool "DCACHE1" - default n - -config STM32U5_SRAM1 - bool "SRAM1" - default y - -config STM32U5_SRAM2 - bool "SRAM2" - default n - -config STM32U5_SRAM3 - bool "SRAM3" - default n - depends on STM32U5_STM32U575XX || STM32U5_STM32U585XX || STM32U5_STM32U59XX || STM32U5_STM32U59AXX || \ - STM32U5_STM32U5A5XX || STM32U5_STM32U5A9XX - -config STM32U5_SRAM5 - bool "SRAM5" - default n - depends on STM32U5_STM32U575XX || STM32U5_STM32U585XX || STM32U5_STM32U59XX || STM32U5_STM32U59AXX || \ - STM32U5_STM32U5A5XX || STM32U5_STM32U5A9XX - -comment "SRAM Options" - -config STM32U5_SRAM2_HEAP - bool "SRAM2 is used for heap" - default n - depends on STM32U5_SRAM2 - select STM32U5_SRAM2_INIT - ---help--- - The STM32U5 SRAM2 region has special properties (power, protection, parity) - which may be used by the application for special purposes. But if these - special properties are not needed, it may be instead added to the heap for - use by malloc(). - NOTE: you must also select an appropriate number of memory regions in the - 'Memory Management' section. - -config STM32U5_SRAM2_INIT - bool "SRAM2 is initialized to zero" - default n - depends on STM32U5_SRAM2 - ---help--- - The STM32U5 SRAM2 region has parity checking. However, when the system - powers on, the memory is in an unknown state, and reads from uninitialized - memory can trigger parity faults from the random data. This can be - avoided by first writing to all locations to force the parity into a valid - state. - However, if the SRAM2 is being used for it's battery-backed capability, - this may be undesirable (because it will destroy the contents). In that - case, the board should handle the initialization itself at the appropriate - time. - -config STM32U5_SRAM3_HEAP - bool "SRAM3 is used for heap" - depends on STM32U5_SRAM3 - default n - -config STM32U5_SRAM5_HEAP - bool "SRAM5 is used for heap" - depends on STM32U5_SRAM5 - default n - -comment "AHB2 Peripherals" - -config STM32U5_ADC1 - bool "ADC1" - default n - -config STM32U5_DCMI_PSSI - bool "DCMI_PSSI" - default n - -config STM32U5_OTGFS - bool "OTG FS" - depends on STM32U5_STM32U535XX || CONFIG_STM32U5_STM32U545XX || STM32U5_STM32U575XX || STM32U5_STM32U585XX - default n - -config STM32U5_OTGHS - bool "OTG HS" - depends on STM32U5_STM32U59XX || STM32U5_STM32U59AXX || STM32U5_STM32U5A5XX || STM32U5_STM32U5A9XX - default n - -config STM32U5_AES - bool "AES" - default n - -config STM32U5_HASH - bool "HASH" - default n - -config STM32U5_RNG - bool "RNG" - default n - -config STM32U5_PKA - bool "PKA" - default n - -config STM32U5_SAES - bool "SAES" - default n - -config STM32U5_OCTOSPIM - bool "OCTOSPIM" - default n - -config STM32U5_OTFDEC1 - bool "OTFDEC1" - default n - -config STM32U5_OTFDEC2 - bool "OTFDEC2" - default n - -config STM32U5_SDMMC1 - bool "SDMMC1" - default n - -config STM32U5_SDMMC2 - bool "SDMMC2" - default n - -config STM32U5_FSMC - bool "FSMC" - default n - -config STM32U5_OCTOSPI1 - bool "OCTOSPI1" - default n - -config STM32U5_OCTOSPI2 - bool "OCTOSPI2" - default n - -comment "AHB3 Peripherals" - -config STM32U5_LPGPIO1 - bool "LPGPIO1" - default n - -config STM32U5_PWR - bool "PWR" - default n - -config STM32U5_ADC4 - bool "ADC4" - default n - -config STM32U5_DAC1 - bool "DAC1" - default n - -config STM32U5_LPDMA1 - bool "LPDMA1" - default n - -config STM32U5_ADF1 - bool "ADF1" - default n - -config STM32U5_GTZC2 - bool "GTZC2" - default n - -comment "APB1 Peripherals" - -config STM32U5_TIM2 - bool "TIM2" - default n - -config STM32U5_TIM3 - bool "TIM3" - default n - -config STM32U5_TIM4 - bool "TIM4" - default n - -config STM32U5_TIM5 - bool "TIM5" - default n - -config STM32U5_TIM6 - bool "TIM6" - default n - -config STM32U5_TIM7 - bool "TIM7" - default n - -config STM32U5_WWDG - bool "WWDG" - default n - -config STM32U5_SPI2 - bool "SPI2" - default n - select SPI - select STM32U5_SPI - -config STM32U5_USART2 - bool "USART2" - default n - select ARCH_HAVE_SERIAL_TERMIOS - select STM32U5_USART - -config STM32U5_USART3 - bool "USART3" - default n - select ARCH_HAVE_SERIAL_TERMIOS - select STM32U5_USART - -config STM32U5_UART4 - bool "UART4" - default n - select ARCH_HAVE_SERIAL_TERMIOS - select STM32U5_USART - -config STM32U5_UART5 - bool "UART5" - default n - select ARCH_HAVE_SERIAL_TERMIOS - select STM32U5_USART - -config STM32U5_I2C1 - bool "I2C1" - default n - select STM32U5_I2C - -config STM32U5_I2C2 - bool "I2C2" - default n - select STM32U5_I2C - -config STM32U5_I2C3 - bool "I2C3" - default n - select STM32U5_I2C - -config STM32U5_I2C4 - bool "I2C4" - default n - select STM32U5_I2C - -config STM32U5_I2C5 - bool "I2C5" - depends on STM32U5_STM32U59XX || STM32U5_STM32U59AXX || STM32U5_STM32U5A5XX || STM32U5_STM32U5A9XX - default n - select STM32U5_I2C - -config STM32U5_I2C6 - bool "I2C6" - depends on STM32U5_STM32U59XX || STM32U5_STM32U59AXX || STM32U5_STM32U5A5XX || STM32U5_STM32U5A9XX - default n - select STM32U5_I2C - -config STM32U5_CRS - bool "CRS" - default n - -config STM32U5_LPTIM2 - bool "LPTIM2" - default n - -config STM32U5_FDCAN1 - bool "FDCAN1" - default n - -config STM32U5_UCPD1 - bool "UCPD1" - default n - -comment "APB2 Peripherals" - -config STM32U5_TIM1 - bool "TIM1" - default n - -config STM32U5_SPI1 - bool "SPI1" - default n - select SPI - select STM32U5_SPI - -config STM32U5_TIM8 - bool "TIM8" - default n - -config STM32U5_USART1 - bool "USART1" - default n - select ARCH_HAVE_SERIAL_TERMIOS - select STM32U5_USART - -config STM32U5_TIM15 - bool "TIM15" - default n - -config STM32U5_TIM16 - bool "TIM16" - default n - -config STM32U5_TIM17 - bool "TIM17" - default n - -config STM32U5_SAI1 - bool "SAI1" - default n - -config STM32U5_SAI2 - bool "SAI2" - default n - -comment "APB3 Peripherals" - -config STM32U5_SYSCFG - bool "SYSCFG" - default y - -config STM32U5_SPI3 - bool "SPI3" - default n - select SPI - select STM32U5_SPI - -config STM32U5_LPUART1 - bool "LPUART1" - default n - select ARCH_HAVE_SERIAL_TERMIOS - select STM32U5_USART - -config STM32U5_LPTIM1 - bool "LPTIM1" - default n - -config STM32U5_LPTIM3 - bool "LPTIM3" - default n - -config STM32U5_LPTIM4 - bool "LPTIM4" - default n - -config STM32U5_OPAMP - bool "OPAMP" - default n - -config STM32U5_COMP - bool "COMP" - default n - -config STM32U5_VREF - bool "VREF" - default n - -config STM32U5_RTCAPB - bool "RTCAPB" - default n - -endmenu - -config STM32U5_SAI1PLL - bool "SAI1PLL" - default n - ---help--- - The STM32U5 has a separate PLL for the SAI1 block. - Set this true and provide configuration parameters in - board.h to use this PLL. - -config STM32U5_SAI2PLL - bool "SAI2PLL" - default n - depends on STM32U5_HAVE_SAI2 - ---help--- - The STM32U5 has a separate PLL for the SAI2 block. - Set this true and provide configuration parameters in - board.h to use this PLL. - -config STM32U5_FLASH_PREFETCH - bool "Enable FLASH Pre-fetch" - default y - ---help--- - Enable FLASH prefetch - -config STM32U5_DISABLE_IDLE_SLEEP_DURING_DEBUG - bool "Disable IDLE Sleep (WFI) in debug mode" - default n - ---help--- - In debug configuration, disables the WFI instruction in the IDLE loop - to prevent the JTAG from disconnecting. With some JTAG debuggers, such - as the ST-LINK2 with OpenOCD, if the ARM is put to sleep via the WFI - instruction, the debugger will disconnect, terminating the debug session. - -config ARCH_BOARD_STM32U5_CUSTOM_CLOCKCONFIG - bool "Custom clock configuration" - default n - ---help--- - Enables special, board-specific STM32 clock configuration. - -menu "RTC Configuration" - depends on STM32U5_RTC - -config STM32U5_RTC_MAGIC_REG - int "BKP register" - default 0 - range 0 31 - ---help--- - The BKP register used to store/check the Magic value to determine if - RTC is already setup - -config STM32U5_RTC_MAGIC - hex "RTC Magic 1" - default 0xfacefeed - ---help--- - Value used as Magic to determine if the RTC is already setup - -config STM32U5_RTC_MAGIC_TIME_SET - hex "RTC Magic 2" - default 0xf00dface - ---help--- - Value used as Magic to determine if the RTC has been setup and has - time set - -choice - prompt "RTC clock source" - default STM32U5_RTC_LSECLOCK - depends on STM32U5_RTC - -config STM32U5_RTC_LSECLOCK - bool "LSE clock" - ---help--- - Drive the RTC with the LSE clock - -config STM32U5_RTC_LSICLOCK - bool "LSI clock" - ---help--- - Drive the RTC with the LSI clock - -config STM32U5_RTC_HSECLOCK - bool "HSE clock" - ---help--- - Drive the RTC with the HSE clock, divided down to 1MHz. - -endchoice - -if STM32U5_RTC_LSECLOCK - -config STM32U5_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY - bool "Automatically boost the LSE oscillator drive capability level until it starts-up" - default n - ---help--- - This will cycle through the values from low to high. To avoid - damaging the crystal. We want to use the lowest setting that gets - the OSC running. See app note AN2867 - - 0 = Low drive capability (default) - 1 = Medium low drive capability - 2 = Medium high drive capability - 3 = High drive capability - -config STM32U5_RTC_LSECLOCK_START_DRV_CAPABILITY - int "LSE oscillator drive capability level at LSE start-up" - default 0 - range 0 3 - depends on !STM32U5_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY - ---help--- - 0 = Low drive capability (default) - 1 = Medium low drive capability - 2 = Medium high drive capability - 3 = High drive capability - -config STM32U5_RTC_LSECLOCK_LOWER_RUN_DRV_CAPABILITY - bool "Decrease LSE oscillator drive capability after LSE start-up" - default n - depends on !STM32U5_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY - ---help--- - The LSE oscillator drive capability can remain at the level used - during LSE start-up at run-time, or it can be reduced to the - 'Low drive capability' once the LSE started up successfully. - -endif # STM32U5_RTC_LSECLOCK - -endmenu # RTC Configuration - -menu "Timer Configuration" - -if SCHED_TICKLESS - -config STM32U5_ONESHOT - bool - default y - -config STM32U5_FREERUN - bool - default y - -config STM32U5_TICKLESS_ONESHOT - int "Tickless one-shot timer channel" - default 2 - range 1 8 - depends on STM32U5_ONESHOT - ---help--- - If the Tickless OS feature is enabled, then one clock must be - assigned to provide the one-shot timer needed by the OS. - -config STM32U5_TICKLESS_FREERUN - int "Tickless free-running timer channel" - default 5 - range 1 8 - depends on STM32U5_FREERUN - ---help--- - If the Tickless OS feature is enabled, then one clock must be - assigned to provide the free-running timer needed by the OS. - -endif # SCHED_TICKLESS - -if !SCHED_TICKLESS - -config STM32U5_ONESHOT - bool "TIM one-shot wrapper" - default n - ---help--- - Enable a wrapper around the low level timer/counter functions to - support one-shot timer. - -config STM32U5_FREERUN - bool "TIM free-running wrapper" - default n - ---help--- - Enable a wrapper around the low level timer/counter functions to - support a free-running timer. - -endif # !SCHED_TICKLESS - -config STM32U5_ONESHOT_MAXTIMERS - int "Maximum number of oneshot timers" - default 1 - range 1 8 - depends on STM32U5_ONESHOT - ---help--- - Determines the maximum number of oneshot timers that can be - supported. This setting pre-allocates some minimal support for each - of the timers and places an upper limit on the number of oneshot - timers that you can use. - -config STM32U5_LPTIM1_PWM - bool "LPTIM1 PWM" - default n - depends on STM32U5_LPTIM1 - select PWM - ---help--- - Reserve low-power timer 1 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32U5_LPTIM1 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32U5_LPTIM1_PWM - -choice - prompt "LPTIM1 clock source" - default STM32U5_LPTIM1_CLK_APB1 - -config STM32U5_LPTIM1_CLK_APB1 - bool "Clock LPTIM1 from APB1" - -config STM32U5_LPTIM1_CLK_LSE - bool "Clock LPTIM1 from LSE" - -config STM32U5_LPTIM1_CLK_LSI - bool "Clock LPTIM1 from LSI" - -config STM32U5_LPTIM1_CLK_HSI - bool "Clock LPTIM1 from HSI" -endchoice - -endif # STM32U5_LPTIM1_PWM - -config STM32U5_LPTIM2_PWM - bool "LPTIM2 PWM" - default n - depends on STM32U5_LPTIM2 - select PWM - ---help--- - Reserve low-power timer 2 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32U5_LPTIM2 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32U5_LPTIM2_PWM - -choice - prompt "LPTIM2 clock source" - default STM32U5_LPTIM2_CLK_APB1 - -config STM32U5_LPTIM2_CLK_APB1 - bool "Clock LPTIM2 from APB1" - -config STM32U5_LPTIM2_CLK_LSE - bool "Clock LPTIM2 from LSE" - -config STM32U5_LPTIM2_CLK_LSI - bool "Clock LPTIM2 from LSI" - -config STM32U5_LPTIM2_CLK_HSI - bool "Clock LPTIM2 from HSI" -endchoice - -endif # STM32U5_LPTIM2_PWM - -config STM32U5_TIM1_PWM - bool "TIM1 PWM" - default n - depends on STM32U5_TIM1 - select STM32U5_PWM - ---help--- - Reserve timer 1 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32U5_TIM1 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32U5_TIM1_PWM - -config STM32U5_TIM1_MODE - int "TIM1 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -if STM32U5_PWM_MULTICHAN - -config STM32U5_TIM1_CHANNEL1 - bool "TIM1 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32U5_TIM1_CHANNEL1 - -config STM32U5_TIM1_CH1MODE - int "TIM1 Channel 1 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32U5_TIM1_CH1OUT - bool "TIM1 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32U5_TIM1_CH1NOUT - bool "TIM1 Channel 1 Complementary Output" - default n - depends on STM32U5_TIM1_CH1OUT - ---help--- - Enables channel 1 complementary output. - -endif # STM32U5_TIM1_CHANNEL1 - -config STM32U5_TIM1_CHANNEL2 - bool "TIM1 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32U5_TIM1_CHANNEL2 - -config STM32U5_TIM1_CH2MODE - int "TIM1 Channel 2 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32U5_TIM1_CH2OUT - bool "TIM1 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -config STM32U5_TIM1_CH2NOUT - bool "TIM1 Channel 2 Complemenrary Output" - default n - depends on STM32U5_TIM1_CH2OUT - ---help--- - Enables channel 2 complementary output. - -endif # STM32U5_TIM1_CHANNEL2 - -config STM32U5_TIM1_CHANNEL3 - bool "TIM1 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32U5_TIM1_CHANNEL3 - -config STM32U5_TIM1_CH3MODE - int "TIM1 Channel 3 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32U5_TIM1_CH3OUT - bool "TIM1 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -config STM32U5_TIM1_CH3NOUT - bool "TIM1 Channel 3 Complementary Output" - default n - depends on STM32U5_TIM1_CH3OUT - ---help--- - Enables channel 3 complementary output. - -endif # STM32U5_TIM1_CHANNEL3 - -config STM32U5_TIM1_CHANNEL5 - bool "TIM1 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32U5_TIM1_CHANNEL5 - -config STM32U5_TIM1_CH4MODE - int "TIM1 Channel 4 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32U5_TIM1_CH4OUT - bool "TIM1 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32U5_TIM1_CHANNEL5 - -endif # STM32U5_PWM_MULTICHAN - -if !STM32U5_PWM_MULTICHAN - -config STM32U5_TIM1_CHANNEL - int "TIM1 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM1 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -config STM32U5_TIM1_CHMODE - int "TIM1 Channel Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -endif # !STM32U5_PWM_MULTICHAN - -endif # STM32U5_TIM1_PWM - -config STM32U5_TIM2_PWM - bool "TIM2 PWM" - default n - depends on STM32U5_TIM2 - select STM32U5_PWM - ---help--- - Reserve timer 2 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32U5_TIM2 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32U5_TIM2_PWM - -config STM32U5_TIM2_MODE - int "TIM2 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -if STM32U5_PWM_MULTICHAN - -config STM32U5_TIM2_CHANNEL1 - bool "TIM2 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32U5_TIM2_CHANNEL1 - -config STM32U5_TIM2_CH1MODE - int "TIM2 Channel 1 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32U5_TIM2_CH1OUT - bool "TIM2 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32U5_TIM2_CHANNEL1 - -config STM32U5_TIM2_CHANNEL2 - bool "TIM2 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32U5_TIM2_CHANNEL2 - -config STM32U5_TIM2_CH2MODE - int "TIM2 Channel 2 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32U5_TIM2_CH2OUT - bool "TIM2 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32U5_TIM2_CHANNEL2 - -config STM32U5_TIM2_CHANNEL3 - bool "TIM2 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32U5_TIM2_CHANNEL3 - -config STM32U5_TIM2_CH3MODE - int "TIM2 Channel 3 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32U5_TIM2_CH3OUT - bool "TIM2 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32U5_TIM2_CHANNEL3 - -config STM32U5_TIM2_CHANNEL5 - bool "TIM2 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32U5_TIM2_CHANNEL5 - -config STM32U5_TIM2_CH4MODE - int "TIM2 Channel 4 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32U5_TIM2_CH4OUT - bool "TIM2 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32U5_TIM2_CHANNEL5 - -endif # STM32U5_PWM_MULTICHAN - -if !STM32U5_PWM_MULTICHAN - -config STM32U5_TIM2_CHANNEL - int "TIM2 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM2 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -config STM32U5_TIM2_CHMODE - int "TIM2 Channel Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -endif # !STM32U5_PWM_MULTICHAN - -endif # STM32U5_TIM2_PWM - -config STM32U5_TIM3_PWM - bool "TIM3 PWM" - default n - depends on STM32U5_TIM3 - select STM32U5_PWM - ---help--- - Reserve timer 3 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32U5_TIM3 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32U5_TIM3_PWM - -config STM32U5_TIM3_MODE - int "TIM3 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -if STM32U5_PWM_MULTICHAN - -config STM32U5_TIM3_CHANNEL1 - bool "TIM3 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32U5_TIM3_CHANNEL1 - -config STM32U5_TIM3_CH1MODE - int "TIM3 Channel 1 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32U5_TIM3_CH1OUT - bool "TIM3 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32U5_TIM3_CHANNEL1 - -config STM32U5_TIM3_CHANNEL2 - bool "TIM3 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32U5_TIM3_CHANNEL2 - -config STM32U5_TIM3_CH2MODE - int "TIM3 Channel 2 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32U5_TIM3_CH2OUT - bool "TIM3 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32U5_TIM3_CHANNEL2 - -config STM32U5_TIM3_CHANNEL3 - bool "TIM3 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32U5_TIM3_CHANNEL3 - -config STM32U5_TIM3_CH3MODE - int "TIM3 Channel 3 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32U5_TIM3_CH3OUT - bool "TIM3 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32U5_TIM3_CHANNEL3 - -config STM32U5_TIM3_CHANNEL5 - bool "TIM3 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32U5_TIM3_CHANNEL5 - -config STM32U5_TIM3_CH4MODE - int "TIM3 Channel 4 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32U5_TIM3_CH4OUT - bool "TIM3 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32U5_TIM3_CHANNEL5 - -endif # STM32U5_PWM_MULTICHAN - -if !STM32U5_PWM_MULTICHAN - -config STM32U5_TIM3_CHANNEL - int "TIM3 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM3 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -config STM32U5_TIM3_CHMODE - int "TIM3 Channel Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -endif # !STM32U5_PWM_MULTICHAN - -endif # STM32U5_TIM3_PWM - -config STM32U5_TIM4_PWM - bool "TIM4 PWM" - default n - depends on STM32U5_TIM4 - select STM32U5_PWM - ---help--- - Reserve timer 4 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32U5_TIM4 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32U5_TIM4_PWM - -config STM32U5_TIM4_MODE - int "TIM4 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -if STM32U5_PWM_MULTICHAN - -config STM32U5_TIM4_CHANNEL1 - bool "TIM4 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32U5_TIM4_CHANNEL1 - -config STM32U5_TIM4_CH1MODE - int "TIM4 Channel 1 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32U5_TIM4_CH1OUT - bool "TIM4 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32U5_TIM4_CHANNEL1 - -config STM32U5_TIM4_CHANNEL2 - bool "TIM4 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32U5_TIM4_CHANNEL2 - -config STM32U5_TIM4_CH2MODE - int "TIM4 Channel 2 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32U5_TIM4_CH2OUT - bool "TIM4 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32U5_TIM4_CHANNEL2 - -config STM32U5_TIM4_CHANNEL3 - bool "TIM4 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32U5_TIM4_CHANNEL3 - -config STM32U5_TIM4_CH3MODE - int "TIM4 Channel 3 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32U5_TIM4_CH3OUT - bool "TIM4 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32U5_TIM4_CHANNEL3 - -config STM32U5_TIM4_CHANNEL5 - bool "TIM4 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32U5_TIM4_CHANNEL5 - -config STM32U5_TIM4_CH4MODE - int "TIM4 Channel 4 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32U5_TIM4_CH4OUT - bool "TIM4 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32U5_TIM4_CHANNEL5 - -endif # STM32U5_PWM_MULTICHAN - -if !STM32U5_PWM_MULTICHAN - -config STM32U5_TIM4_CHANNEL - int "TIM4 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM4 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -config STM32U5_TIM4_CHMODE - int "TIM4 Channel Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -endif # !STM32U5_PWM_MULTICHAN - -endif # STM32U5_TIM4_PWM - -config STM32U5_TIM5_PWM - bool "TIM5 PWM" - default n - depends on STM32U5_TIM5 - select STM32U5_PWM - ---help--- - Reserve timer 5 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32U5_TIM5 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32U5_TIM5_PWM - -config STM32U5_TIM5_MODE - int "TIM5 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -if STM32U5_PWM_MULTICHAN - -config STM32U5_TIM5_CHANNEL1 - bool "TIM5 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32U5_TIM5_CHANNEL1 - -config STM32U5_TIM5_CH1MODE - int "TIM5 Channel 1 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32U5_TIM5_CH1OUT - bool "TIM5 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32U5_TIM5_CHANNEL1 - -config STM32U5_TIM5_CHANNEL2 - bool "TIM5 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32U5_TIM5_CHANNEL2 - -config STM32U5_TIM5_CH2MODE - int "TIM5 Channel 2 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32U5_TIM5_CH2OUT - bool "TIM5 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32U5_TIM5_CHANNEL2 - -config STM32U5_TIM5_CHANNEL3 - bool "TIM5 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32U5_TIM5_CHANNEL3 - -config STM32U5_TIM5_CH3MODE - int "TIM5 Channel 3 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32U5_TIM5_CH3OUT - bool "TIM5 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32U5_TIM5_CHANNEL3 - -config STM32U5_TIM5_CHANNEL5 - bool "TIM5 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32U5_TIM5_CHANNEL5 - -config STM32U5_TIM5_CH4MODE - int "TIM5 Channel 4 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32U5_TIM5_CH4OUT - bool "TIM5 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32U5_TIM5_CHANNEL5 - -endif # STM32U5_PWM_MULTICHAN - -if !STM32U5_PWM_MULTICHAN - -config STM32U5_TIM5_CHANNEL - int "TIM5 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM5 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -config STM32U5_TIM5_CHMODE - int "TIM5 Channel Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -endif # !STM32U5_PWM_MULTICHAN - -endif # STM32U5_TIM5_PWM - -config STM32U5_TIM8_PWM - bool "TIM8 PWM" - default n - depends on STM32U5_TIM8 - select STM32U5_PWM - ---help--- - Reserve timer 8 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32U5_TIM8 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32U5_TIM8_PWM - -config STM32U5_TIM8_MODE - int "TIM8 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -if STM32U5_PWM_MULTICHAN - -config STM32U5_TIM8_CHANNEL1 - bool "TIM8 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32U5_TIM8_CHANNEL1 - -config STM32U5_TIM8_CH1MODE - int "TIM8 Channel 1 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32U5_TIM8_CH1OUT - bool "TIM8 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32U5_TIM8_CH1NOUT - bool "TIM8 Channel 1 Complementary Output" - default n - depends on STM32U5_TIM8_CH1OUT - ---help--- - Enables channel 1 complementary output. - -endif # STM32U5_TIM8_CHANNEL1 - -config STM32U5_TIM8_CHANNEL2 - bool "TIM8 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32U5_TIM8_CHANNEL2 - -config STM32U5_TIM8_CH2MODE - int "TIM8 Channel 2 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32U5_TIM8_CH2OUT - bool "TIM8 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -config STM32U5_TIM8_CH2NOUT - bool "TIM8 Channel 2 Complementary Output" - default n - depends on STM32U5_TIM8_CH2OUT - ---help--- - Enables channel 2 complementary output. - -endif # STM32U5_TIM8_CHANNEL2 - -config STM32U5_TIM8_CHANNEL3 - bool "TIM8 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32U5_TIM8_CHANNEL3 - -config STM32U5_TIM8_CH3MODE - int "TIM8 Channel 3 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32U5_TIM8_CH3OUT - bool "TIM8 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -config STM32U5_TIM8_CH3NOUT - bool "TIM8 Channel 3 Complementary Output" - default n - depends on STM32U5_TIM8_CH3OUT - ---help--- - Enables channel 3 complementary output. - -endif # STM32U5_TIM8_CHANNEL3 - -config STM32U5_TIM8_CHANNEL5 - bool "TIM8 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32U5_TIM8_CHANNEL5 - -config STM32U5_TIM8_CH4MODE - int "TIM8 Channel 4 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32U5_TIM8_CH4OUT - bool "TIM8 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32U5_TIM8_CHANNEL5 - -endif # STM32U5_PWM_MULTICHAN - -if !STM32U5_PWM_MULTICHAN - -config STM32U5_TIM8_CHANNEL - int "TIM8 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM8 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -config STM32U5_TIM8_CHMODE - int "TIM8 Channel Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -endif # !STM32U5_PWM_MULTICHAN - -endif # STM32U5_TIM8_PWM - -config STM32U5_TIM15_PWM - bool "TIM15 PWM" - default n - depends on STM32U5_TIM15 - select STM32U5_PWM - ---help--- - Reserve timer 15 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32U5_TIM15 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32U5_TIM15_PWM - -if STM32U5_PWM_MULTICHAN - -config STM32U5_TIM15_CHANNEL1 - bool "TIM15 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32U5_TIM15_CHANNEL1 - -config STM32U5_TIM15_CH1MODE - int "TIM15 Channel 1 Mode" - default 0 - range 0 3 - ---help--- - Specifies the channel mode. - -config STM32U5_TIM15_CH1OUT - bool "TIM15 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32U5_TIM15_CH1NOUT - bool "TIM15 Channel 1 Complementary Output" - default n - depends on STM32U5_TIM15_CH1OUT - ---help--- - Enables channel 1 complementary output. - -endif # STM32U5_TIM15_CHANNEL1 - -config STM32U5_TIM15_CHANNEL2 - bool "TIM15 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32U5_TIM15_CHANNEL2 - -config STM32U5_TIM15_CH2MODE - int "TIM15 Channel 2 Mode" - default 0 - range 0 3 - ---help--- - Specifies the channel mode. - -config STM32U5_TIM15_CH2OUT - bool "TIM15 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32U5_TIM15_CHANNEL2 - -endif # STM32U5_PWM_MULTICHAN - -if !STM32U5_PWM_MULTICHAN - -config STM32U5_TIM15_CHANNEL - int "TIM15 PWM Output Channel" - default 1 - range 1 2 - ---help--- - If TIM15 is enabled for PWM usage, you also need specifies the timer output - channel {1,2} - -config STM32U5_TIM15_CHMODE - int "TIM15 Channel Mode" - default 0 - range 0 3 - ---help--- - Specifies the channel mode. - -endif # !STM32U5_PWM_MULTICHAN - -endif # STM32U5_TIM15_PWM - -config STM32U5_TIM16_PWM - bool "TIM16 PWM" - default n - depends on STM32U5_TIM16 - select STM32U5_PWM - ---help--- - Reserve timer 16 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32U5_TIM16 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32U5_TIM16_PWM - -if STM32U5_PWM_MULTICHAN - -config STM32U5_TIM16_CHANNEL1 - bool "TIM16 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32U5_TIM16_CHANNEL1 - -config STM32U5_TIM16_CH1MODE - int "TIM16 Channel 1 Mode" - default 0 - range 0 1 - ---help--- - Specifies the channel mode. - -config STM32U5_TIM16_CH1OUT - bool "TIM16 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32U5_TIM16_CH1NOUT - bool "TIM16 Channel 1 Complementary Output" - default n - depends on STM32U5_TIM16_CH1OUT - ---help--- - Enables channel 1 complementary output. - -endif # STM32U5_TIM16_CHANNEL1 - -endif # STM32U5_PWM_MULTICHAN - -if !STM32U5_PWM_MULTICHAN - -config STM32U5_TIM16_CHANNEL - int "TIM16 PWM Output Channel" - default 1 - range 1 1 - ---help--- - If TIM16 is enabled for PWM usage, you also need specifies the timer output - channel {1} - -config STM32U5_TIM16_CHMODE - int "TIM16 Channel Mode" - default 0 - range 0 1 - ---help--- - Specifies the channel mode. - -endif # !STM32U5_PWM_MULTICHAN - -endif # STM32U5_TIM16_PWM - -config STM32U5_TIM17_PWM - bool "TIM17 PWM" - default n - depends on STM32U5_TIM17 - select STM32U5_PWM - ---help--- - Reserve timer 17 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32U5_TIM17 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32U5_TIM17_PWM - -if STM32U5_PWM_MULTICHAN - -config STM32U5_TIM17_CHANNEL1 - bool "TIM17 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32U5_TIM17_CHANNEL1 - -config STM32U5_TIM17_CH1MODE - int "TIM17 Channel 1 Mode" - default 0 - range 0 1 - ---help--- - Specifies the channel mode. - -config STM32U5_TIM17_CH1OUT - bool "TIM17 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32U5_TIM17_CH1NOUT - bool "TIM17 Channel 1 Complementary Output" - default n - depends on STM32U5_TIM17_CH1OUT - ---help--- - Enables channel 1 complementary output. - -endif # STM32U5_TIM17_CHANNEL1 - -endif # STM32U5_PWM_MULTICHAN - -if !STM32U5_PWM_MULTICHAN - -config STM32U5_TIM17_CHANNEL - int "TIM17 PWM Output Channel" - default 1 - range 1 1 - ---help--- - If TIM17 is enabled for PWM usage, you also need specifies the timer output - channel {1} - -config STM32U5_TIM17_CHMODE - int "TIM17 Channel Mode" - default 0 - range 0 1 - ---help--- - Specifies the channel mode. - -endif # !STM32U5_PWM_MULTICHAN - -endif # STM32U5_TIM17_PWM - -config STM32U5_PWM_MULTICHAN - bool "PWM Multiple Output Channels" - default n - depends on STM32U5_PWM - ---help--- - Specifies that the PWM driver supports multiple output - channels per timer. - -config STM32U5_TIM1_ADC - bool "TIM1 ADC" - default n - depends on STM32U5_TIM1 && STM32U5_ADC - ---help--- - Reserve timer 1 for use by ADC - - Timer devices may be used for different purposes. If STM32U5_TIM1 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select TIM1 ADC channel" - default STM32U5_TIM1_ADC1 - depends on STM32U5_TIM1_ADC - -config STM32U5_TIM1_ADC1 - bool "TIM1 ADC channel 1" - depends on STM32U5_ADC1 - select STM32U5_HAVE_ADC1_TIMER - ---help--- - Reserve TIM1 to trigger ADC1 - -config STM32U5_TIM1_ADC2 - bool "TIM1 ADC channel 2" - depends on STM32U5_ADC2 - select STM32U5_HAVE_ADC2_TIMER - ---help--- - Reserve TIM1 to trigger ADC2 - -config STM32U5_TIM1_ADC3 - bool "TIM1 ADC channel 3" - depends on STM32U5_ADC3 - select STM32U5_HAVE_ADC3_TIMER - ---help--- - Reserve TIM1 to trigger ADC3 - -endchoice - -config STM32U5_TIM2_ADC - bool "TIM2 ADC" - default n - depends on STM32U5_TIM2 && STM32U5_ADC - ---help--- - Reserve timer 2 for use by ADC - - Timer devices may be used for different purposes. If STM32U5_TIM2 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select TIM2 ADC channel" - default STM32U5_TIM2_ADC1 - depends on STM32U5_TIM2_ADC - -config STM32U5_TIM2_ADC1 - bool "TIM2 ADC channel 1" - depends on STM32U5_ADC1 - select STM32U5_HAVE_ADC1_TIMER - ---help--- - Reserve TIM2 to trigger ADC1 - -config STM32U5_TIM2_ADC2 - bool "TIM2 ADC channel 2" - depends on STM32U5_ADC2 - select STM32U5_HAVE_ADC2_TIMER - ---help--- - Reserve TIM2 to trigger ADC2 - -config STM32U5_TIM2_ADC3 - bool "TIM2 ADC channel 3" - depends on STM32U5_ADC3 - select STM32U5_HAVE_ADC3_TIMER - ---help--- - Reserve TIM2 to trigger ADC3 - -endchoice - -config STM32U5_TIM3_ADC - bool "TIM3 ADC" - default n - depends on STM32U5_TIM3 && STM32U5_ADC - ---help--- - Reserve timer 3 for use by ADC - - Timer devices may be used for different purposes. If STM32U5_TIM3 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select TIM3 ADC channel" - default STM32U5_TIM3_ADC1 - depends on STM32U5_TIM3_ADC - -config STM32U5_TIM3_ADC1 - bool "TIM3 ADC channel 1" - depends on STM32U5_ADC1 - select STM32U5_HAVE_ADC1_TIMER - ---help--- - Reserve TIM3 to trigger ADC1 - -config STM32U5_TIM3_ADC2 - bool "TIM3 ADC channel 2" - depends on STM32U5_ADC2 - select STM32U5_HAVE_ADC2_TIMER - ---help--- - Reserve TIM3 to trigger ADC2 - -config STM32U5_TIM3_ADC3 - bool "TIM3 ADC channel 3" - depends on STM32U5_ADC3 - select STM32U5_HAVE_ADC3_TIMER - ---help--- - Reserve TIM3 to trigger ADC3 - -endchoice - -config STM32U5_TIM4_ADC - bool "TIM4 ADC" - default n - depends on STM32U5_TIM4 && STM32U5_ADC - ---help--- - Reserve timer 4 for use by ADC - - Timer devices may be used for different purposes. If STM32U5_TIM4 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select TIM4 ADC channel" - default STM32U5_TIM4_ADC1 - depends on STM32U5_TIM4_ADC - -config STM32U5_TIM4_ADC1 - bool "TIM4 ADC channel 1" - depends on STM32U5_ADC1 - select STM32U5_HAVE_ADC1_TIMER - ---help--- - Reserve TIM4 to trigger ADC1 - -config STM32U5_TIM4_ADC2 - bool "TIM4 ADC channel 2" - depends on STM32U5_ADC2 - select STM32U5_HAVE_ADC2_TIMER - ---help--- - Reserve TIM4 to trigger ADC2 - -config STM32U5_TIM4_ADC3 - bool "TIM4 ADC channel 3" - depends on STM32U5_ADC3 - select STM32U5_HAVE_ADC3_TIMER - ---help--- - Reserve TIM4 to trigger ADC3 - -endchoice - -config STM32U5_TIM6_ADC - bool "TIM6 ADC" - default n - depends on STM32U5_TIM6 && STM32U5_ADC - ---help--- - Reserve timer 6 for use by ADC - - Timer devices may be used for different purposes. If STM32U5_TIM6 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select TIM6 ADC channel" - default STM32U5_TIM6_ADC1 - depends on STM32U5_TIM6_ADC - -config STM32U5_TIM6_ADC1 - bool "TIM6 ADC channel 1" - depends on STM32U5_ADC1 - select STM32U5_HAVE_ADC1_TIMER - ---help--- - Reserve TIM6 to trigger ADC1 - -config STM32U5_TIM6_ADC2 - bool "TIM6 ADC channel 2" - depends on STM32U5_ADC2 - select STM32U5_HAVE_ADC2_TIMER - ---help--- - Reserve TIM6 to trigger ADC2 - -config STM32U5_TIM6_ADC3 - bool "TIM6 ADC channel 3" - depends on STM32U5_ADC3 - select STM32U5_HAVE_ADC3_TIMER - ---help--- - Reserve TIM6 to trigger ADC3 - -endchoice - -config STM32U5_TIM8_ADC - bool "TIM8 ADC" - default n - depends on STM32U5_TIM8 && STM32U5_ADC - ---help--- - Reserve timer 8 for use by ADC - - Timer devices may be used for different purposes. If STM32U5_TIM8 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select TIM8 ADC channel" - default STM32U5_TIM8_ADC1 - depends on STM32U5_TIM8_ADC - -config STM32U5_TIM8_ADC1 - bool "TIM8 ADC channel 1" - depends on STM32U5_ADC1 - select STM32U5_HAVE_ADC1_TIMER - ---help--- - Reserve TIM8 to trigger ADC1 - -config STM32U5_TIM8_ADC2 - bool "TIM8 ADC channel 2" - depends on STM32U5_ADC2 - select STM32U5_HAVE_ADC2_TIMER - ---help--- - Reserve TIM8 to trigger ADC2 - -config STM32U5_TIM8_ADC3 - bool "TIM8 ADC channel 3" - depends on STM32U5_ADC3 - select STM32U5_HAVE_ADC3_TIMER - ---help--- - Reserve TIM8 to trigger ADC3 - -endchoice - -config STM32U5_TIM15_ADC - bool "TIM15 ADC" - default n - depends on STM32U5_TIM15 && STM32U5_ADC - ---help--- - Reserve timer 15 for use by ADC - - Timer devices may be used for different purposes. If STM32U5_TIM15 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select TIM15 ADC channel" - default STM32U5_TIM15_ADC1 - depends on STM32U5_TIM15_ADC - -config STM32U5_TIM15_ADC1 - bool "TIM15 ADC channel 1" - depends on STM32U5_ADC1 - select STM32U5_HAVE_ADC1_TIMER - ---help--- - Reserve TIM15 to trigger ADC1 - -config STM32U5_TIM15_ADC2 - bool "TIM15 ADC channel 2" - depends on STM32U5_ADC2 - select STM32U5_HAVE_ADC2_TIMER - ---help--- - Reserve TIM15 to trigger ADC2 - -config STM32U5_TIM15_ADC3 - bool "TIM15 ADC channel 3" - depends on STM32U5_ADC3 - select STM32U5_HAVE_ADC3_TIMER - ---help--- - Reserve TIM15 to trigger ADC3 - -endchoice - -config STM32U5_HAVE_ADC1_TIMER - bool - -config STM32U5_HAVE_ADC2_TIMER - bool - -config STM32U5_HAVE_ADC3_TIMER - bool - -config STM32U5_ADC1_SAMPLE_FREQUENCY - int "ADC1 Sampling Frequency" - default 100 - depends on STM32U5_HAVE_ADC1_TIMER - ---help--- - ADC1 sampling frequency. Default: 100Hz - -config STM32U5_ADC1_TIMTRIG - int "ADC1 Timer Trigger" - default 0 - range 0 4 - depends on STM32U5_HAVE_ADC1_TIMER - ---help--- - Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO - -config STM32U5_ADC2_SAMPLE_FREQUENCY - int "ADC2 Sampling Frequency" - default 100 - depends on STM32U5_HAVE_ADC2_TIMER - ---help--- - ADC2 sampling frequency. Default: 100Hz - -config STM32U5_ADC2_TIMTRIG - int "ADC2 Timer Trigger" - default 0 - range 0 4 - depends on STM32U5_HAVE_ADC2_TIMER - ---help--- - Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO - -config STM32U5_ADC3_SAMPLE_FREQUENCY - int "ADC3 Sampling Frequency" - default 100 - depends on STM32U5_HAVE_ADC3_TIMER - ---help--- - ADC3 sampling frequency. Default: 100Hz - -config STM32U5_ADC3_TIMTRIG - int "ADC3 Timer Trigger" - default 0 - range 0 4 - depends on STM32U5_HAVE_ADC3_TIMER - ---help--- - Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO - -config STM32U5_TIM1_DAC - bool "TIM1 DAC" - default n - depends on STM32U5_TIM1 && STM32U5_DAC - ---help--- - Reserve timer 1 for use by DAC - - Timer devices may be used for different purposes. If STM32U5_TIM1 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM1 DAC channel" - default STM32U5_TIM1_DAC1 - depends on STM32U5_TIM1_DAC - -config STM32U5_TIM1_DAC1 - bool "TIM1 DAC channel 1" - ---help--- - Reserve TIM1 to trigger DAC1 - -config STM32U5_TIM1_DAC2 - bool "TIM1 DAC channel 2" - ---help--- - Reserve TIM1 to trigger DAC2 - -endchoice - -config STM32U5_TIM2_DAC - bool "TIM2 DAC" - default n - depends on STM32U5_TIM2 && STM32U5_DAC - ---help--- - Reserve timer 2 for use by DAC - - Timer devices may be used for different purposes. If STM32U5_TIM2 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM2 DAC channel" - default STM32U5_TIM2_DAC1 - depends on STM32U5_TIM2_DAC - -config STM32U5_TIM2_DAC1 - bool "TIM2 DAC channel 1" - ---help--- - Reserve TIM2 to trigger DAC1 - -config STM32U5_TIM2_DAC2 - bool "TIM2 DAC channel 2" - ---help--- - Reserve TIM2 to trigger DAC2 - -endchoice - -config STM32U5_TIM3_DAC - bool "TIM3 DAC" - default n - depends on STM32U5_TIM3 && STM32U5_DAC - ---help--- - Reserve timer 3 for use by DAC - - Timer devices may be used for different purposes. If STM32U5_TIM3 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM3 DAC channel" - default STM32U5_TIM3_DAC1 - depends on STM32U5_TIM3_DAC - -config STM32U5_TIM3_DAC1 - bool "TIM3 DAC channel 1" - ---help--- - Reserve TIM3 to trigger DAC1 - -config STM32U5_TIM3_DAC2 - bool "TIM3 DAC channel 2" - ---help--- - Reserve TIM3 to trigger DAC2 - -endchoice - -config STM32U5_TIM4_DAC - bool "TIM4 DAC" - default n - depends on STM32U5_TIM4 && STM32U5_DAC - ---help--- - Reserve timer 4 for use by DAC - - Timer devices may be used for different purposes. If STM32U5_TIM4 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM4 DAC channel" - default STM32U5_TIM4_DAC1 - depends on STM32U5_TIM4_DAC - -config STM32U5_TIM4_DAC1 - bool "TIM4 DAC channel 1" - ---help--- - Reserve TIM4 to trigger DAC1 - -config STM32U5_TIM4_DAC2 - bool "TIM4 DAC channel 2" - ---help--- - Reserve TIM4 to trigger DAC2 - -endchoice - -config STM32U5_TIM5_DAC - bool "TIM5 DAC" - default n - depends on STM32U5_TIM5 && STM32U5_DAC - ---help--- - Reserve timer 5 for use by DAC - - Timer devices may be used for different purposes. If STM32U5_TIM5 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM5 DAC channel" - default STM32U5_TIM5_DAC1 - depends on STM32U5_TIM5_DAC - -config STM32U5_TIM5_DAC1 - bool "TIM5 DAC channel 1" - ---help--- - Reserve TIM5 to trigger DAC1 - -config STM32U5_TIM5_DAC2 - bool "TIM5 DAC channel 2" - ---help--- - Reserve TIM5 to trigger DAC2 - -endchoice - -config STM32U5_TIM6_DAC - bool "TIM6 DAC" - default n - depends on STM32U5_TIM6 && STM32U5_DAC - ---help--- - Reserve timer 6 for use by DAC - - Timer devices may be used for different purposes. If STM32U5_TIM6 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM6 DAC channel" - default STM32U5_TIM6_DAC1 - depends on STM32U5_TIM6_DAC - -config STM32U5_TIM6_DAC1 - bool "TIM6 DAC channel 1" - ---help--- - Reserve TIM6 to trigger DAC1 - -config STM32U5_TIM6_DAC2 - bool "TIM6 DAC channel 2" - ---help--- - Reserve TIM6 to trigger DAC2 - -endchoice - -config STM32U5_TIM7_DAC - bool "TIM7 DAC" - default n - depends on STM32U5_TIM7 && STM32U5_DAC - ---help--- - Reserve timer 7 for use by DAC - - Timer devices may be used for different purposes. If STM32U5_TIM7 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM7 DAC channel" - default STM32U5_TIM7_DAC1 - depends on STM32U5_TIM7_DAC - -config STM32U5_TIM7_DAC1 - bool "TIM7 DAC channel 1" - ---help--- - Reserve TIM7 to trigger DAC1 - -config STM32U5_TIM7_DAC2 - bool "TIM7 DAC channel 2" - ---help--- - Reserve TIM7 to trigger DAC2 - -endchoice - -config STM32U5_TIM8_DAC - bool "TIM8 DAC" - default n - depends on STM32U5_TIM8 && STM32U5_DAC - ---help--- - Reserve timer 8 for use by DAC - - Timer devices may be used for different purposes. If STM32U5_TIM8 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM8 DAC channel" - default STM32U5_TIM8_DAC1 - depends on STM32U5_TIM8_DAC - -config STM32U5_TIM8_DAC1 - bool "TIM8 DAC channel 1" - ---help--- - Reserve TIM8 to trigger DAC1 - -config STM32U5_TIM8_DAC2 - bool "TIM8 DAC channel 2" - ---help--- - Reserve TIM8 to trigger DAC2 - -endchoice - -config STM32U5_TIM1_CAP - bool "TIM1 Capture" - default n - depends on STM32U5_HAVE_TIM1 - ---help--- - Reserve timer 1 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32U5_TIM2_CAP - bool "TIM2 Capture" - default n - depends on STM32U5_HAVE_TIM2 - ---help--- - Reserve timer 2 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32U5_TIM3_CAP - bool "TIM3 Capture" - default n - depends on STM32U5_HAVE_TIM3 - ---help--- - Reserve timer 3 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32U5_TIM4_CAP - bool "TIM4 Capture" - default n - depends on STM32U5_HAVE_TIM4 - ---help--- - Reserve timer 4 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32U5_TIM5_CAP - bool "TIM5 Capture" - default n - depends on STM32U5_HAVE_TIM5 - ---help--- - Reserve timer 5 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32U5_TIM8_CAP - bool "TIM8 Capture" - default n - depends on STM32U5_HAVE_TIM8 - ---help--- - Reserve timer 8 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -endmenu # Timer Configuration - -menu "ADC Configuration" - depends on STM32U5_ADC - -config STM32U5_ADC1_DMA - bool "ADC1 DMA" - depends on STM32U5_ADC1 - default n - ---help--- - If DMA is selected, then the ADC may be configured to support - DMA transfer, which is necessary if multiple channels are read - or if very high trigger frequencies are used. - -config STM32U5_ADC2_DMA - bool "ADC2 DMA" - depends on STM32U5_ADC2 - default n - ---help--- - If DMA is selected, then the ADC may be configured to support - DMA transfer, which is necessary if multiple channels are read - or if very high trigger frequencies are used. - -config STM32U5_ADC3_DMA - bool "ADC3 DMA" - depends on STM32U5_ADC3 - default n - ---help--- - If DMA is selected, then the ADC may be configured to support - DMA transfer, which is necessary if multiple channels are read - or if very high trigger frequencies are used. - -config STM32U5_ADC1_OUTPUT_DFSDM - bool "ADC1 output to DFSDM" - depends on STM32U5_ADC1 && STM32U5_DFSDM1 && (STM32U5_STM32U596XX || STM32U5_STM32U5XR) - default n - ---help--- - Route ADC1 output directly to DFSDM parallel inputs. - -config STM32U5_ADC2_OUTPUT_DFSDM - bool "ADC2 output to DFSDM" - depends on STM32U5_ADC2 && STM32U5_DFSDM1 && STM32U5_STM32U596XX - default n - ---help--- - Route ADC2 output directly to DFSDM parallel inputs. - -config STM32U5_ADC3_OUTPUT_DFSDM - bool "ADC3 output to DFSDM" - depends on STM32U5_ADC3 && STM32U5_DFSDM1 && STM32U5_STM32U596XX - default n - ---help--- - Route ADC3 output directly to DFSDM parallel inputs. - -endmenu - -menu "DAC Configuration" - depends on STM32U5_DAC - -config STM32U5_DAC1_DMA - bool "DAC1 DMA" - depends on STM32U5_DAC1 - default n - ---help--- - If DMA is selected, then a timer and output frequency must also be - provided to support the DMA transfer. The DMA transfer could be - supported by an EXTI trigger, but this feature is not currently - supported by the driver. - -if STM32U5_DAC1_DMA - -config STM32U5_DAC1_TIMER - int "DAC1 timer" - range 2 8 - -config STM32U5_DAC1_TIMER_FREQUENCY - int "DAC1 timer frequency" - default 100 - ---help--- - DAC1 output frequency. Default: 100Hz - -config STM32U5_DAC1_DMA_BUFFER_SIZE - int "DAC1 DMA buffer size" - default 1 - -endif - -config STM32U5_DAC1_OUTPUT_ADC - bool "DAC1 output to ADC" - depends on STM32U5_DAC1 - default n - ---help--- - Route DAC1 output to ADC input instead of external pin. - -config STM32U5_DAC2_DMA - bool "DAC2 DMA" - depends on STM32U5_DAC2 - default n - ---help--- - If DMA is selected, then a timer and output frequency must also be - provided to support the DMA transfer. The DMA transfer could be - supported by an EXTI trigger, but this feature is not currently - supported by the driver. - -if STM32U5_DAC2_DMA - -config STM32U5_DAC2_TIMER - int "DAC2 timer" - default 0 - range 2 8 - -config STM32U5_DAC2_TIMER_FREQUENCY - int "DAC2 timer frequency" - default 100 - ---help--- - DAC2 output frequency. Default: 100Hz - -config STM32U5_DAC2_DMA_BUFFER_SIZE - int "DAC2 DMA buffer size" - default 1 - -endif - -config STM32U5_DAC2_OUTPUT_ADC - bool "DAC2 output to ADC" - depends on STM32U5_DAC2 - default n - ---help--- - Route DAC2 output to ADC input instead of external pin. - -endmenu - -menu "DFSDM Configuration" - depends on STM32U5_DFSDM1 - -config STM32U5_DFSDM1_FLT0 - bool "DFSDM1 Filter 0" - default n - select STM32U5_DFSDM - -config STM32U5_DFSDM1_FLT1 - bool "DFSDM1 Filter 1" - default n - select STM32U5_DFSDM - -config STM32U5_DFSDM1_FLT2 - bool "DFSDM1 Filter 2" - default n - depends on !STM32U5_STM32U5X3 - select STM32U5_DFSDM - -config STM32U5_DFSDM1_FLT3 - bool "DFSDM1 Filter 3" - default n - depends on !STM32U5_STM32U5X3 - select STM32U5_DFSDM - -config STM32U5_DFSDM1_DMA - bool "DFSDM1 DMA" - depends on STM32U5_DFSDM - default n - ---help--- - If DMA is selected, then the DFSDM may be configured to support - DMA transfer, which is necessary if multiple channels are read - or if very high trigger frequencies are used. - -endmenu - -config STM32U5_SERIALDRIVER - bool - -config STM32U5_1WIREDRIVER - bool - -menu "[LP]U[S]ART Configuration" - depends on STM32U5_USART - -choice - prompt "LPUART1 Driver Configuration" - default STM32U5_LPUART1_SERIALDRIVER - depends on STM32U5_LPUART1 - -config STM32U5_LPUART1_SERIALDRIVER - bool "Standard serial driver" - select LPUART1_SERIALDRIVER - select STM32U5_SERIALDRIVER - -config STM32U5_LPUART1_1WIREDRIVER - bool "1-Wire driver" - select STM32U5_1WIREDRIVER - -endchoice # LPUART1 Driver Configuration - -if LPUART1_SERIALDRIVER - -config LPUART1_RS485 - bool "RS-485 on LPUART1" - default n - depends on STM32U5_LPUART1 - ---help--- - Enable RS-485 interface on LPUART1. Your board config will have to - provide GPIO_LPUART1_RS485_DIR pin definition. Currently it cannot be - used with LPUART1_RXDMA. - -config LPUART1_RS485_DIR_POLARITY - int "LPUART1 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on LPUART1_RS485 - ---help--- - Polarity of DIR pin for RS-485 on LPUART1. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config LPUART1_RXDMA - bool "LPUART1 Rx DMA" - default n - depends on STM32U5_LPUART1 && (STM32U5_DMA1 || STM32U5_DMA2 || STM32U5_DMAMUX) - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -endif # LPUART1_SERIALDRIVER - -choice - prompt "USART1 Driver Configuration" - default STM32U5_USART1_SERIALDRIVER - depends on STM32U5_USART1 - -config STM32U5_USART1_SERIALDRIVER - bool "Standard serial driver" - select USART1_SERIALDRIVER - select STM32U5_SERIALDRIVER - -config STM32U5_USART1_1WIREDRIVER - bool "1-Wire driver" - select STM32U5_1WIREDRIVER - -endchoice # USART1 Driver Configuration - -if USART1_SERIALDRIVER - -config USART1_RS485 - bool "RS-485 on USART1" - default n - depends on STM32U5_USART1 - ---help--- - Enable RS-485 interface on USART1. Your board config will have to - provide GPIO_USART1_RS485_DIR pin definition. Currently it cannot be - used with USART1_RXDMA. - -config USART1_RS485_DIR_POLARITY - int "USART1 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART1_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART1. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config USART1_RXDMA - bool "USART1 Rx DMA" - default n - depends on STM32U5_USART1 && (STM32U5_DMA1 || STM32U5_DMA2 || STM32U5_DMAMUX) - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -endif # USART1_SERIALDRIVER - -choice - prompt "USART2 Driver Configuration" - default STM32U5_USART2_SERIALDRIVER - depends on STM32U5_USART2 - -config STM32U5_USART2_SERIALDRIVER - bool "Standard serial driver" - select USART2_SERIALDRIVER - select STM32U5_SERIALDRIVER - -config STM32U5_USART2_1WIREDRIVER - bool "1-Wire driver" - select STM32U5_1WIREDRIVER - -endchoice # USART2 Driver Configuration - -if USART2_SERIALDRIVER - -config USART2_RS485 - bool "RS-485 on USART2" - default n - depends on STM32U5_USART2 - ---help--- - Enable RS-485 interface on USART2. Your board config will have to - provide GPIO_USART2_RS485_DIR pin definition. Currently it cannot be - used with USART2_RXDMA. - -config USART2_RS485_DIR_POLARITY - int "USART2 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART2_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART2. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config USART2_RXDMA - bool "USART2 Rx DMA" - default n - depends on STM32U5_USART2 && (STM32U5_DMA1 || STM32U5_DMAMUX) - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -endif # USART2_SERIALDRIVER - -choice - prompt "USART3 Driver Configuration" - default STM32U5_USART3_SERIALDRIVER - depends on STM32U5_USART3 - -config STM32U5_USART3_SERIALDRIVER - bool "Standard serial driver" - select USART3_SERIALDRIVER - select STM32U5_SERIALDRIVER - -config STM32U5_USART3_1WIREDRIVER - bool "1-Wire driver" - select STM32U5_1WIREDRIVER - -endchoice # USART3 Driver Configuration - -if USART3_SERIALDRIVER - -config USART3_RS485 - bool "RS-485 on USART3" - default n - depends on STM32U5_USART3 - ---help--- - Enable RS-485 interface on USART3. Your board config will have to - provide GPIO_USART3_RS485_DIR pin definition. Currently it cannot be - used with USART3_RXDMA. - -config USART3_RS485_DIR_POLARITY - int "USART3 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART3_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART3. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config USART3_RXDMA - bool "USART3 Rx DMA" - default n - depends on STM32U5_USART3 && (STM32U5_DMA1 || STM32U5_DMAMUX) - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -endif # USART3_SERIALDRIVER - -choice - prompt "UART4 Driver Configuration" - default STM32U5_UART4_SERIALDRIVER - depends on STM32U5_UART4 - -config STM32U5_UART4_SERIALDRIVER - bool "Standard serial driver" - select UART4_SERIALDRIVER - select STM32U5_SERIALDRIVER - -config STM32U5_UART4_1WIREDRIVER - bool "1-Wire driver" - select STM32U5_1WIREDRIVER - -endchoice # UART4 Driver Configuration - -if UART4_SERIALDRIVER - -config UART4_RS485 - bool "RS-485 on UART4" - default n - depends on STM32U5_UART4 - ---help--- - Enable RS-485 interface on UART4. Your board config will have to - provide GPIO_UART4_RS485_DIR pin definition. Currently it cannot be - used with UART4_RXDMA. - -config UART4_RS485_DIR_POLARITY - int "UART4 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on UART4_RS485 - ---help--- - Polarity of DIR pin for RS-485 on UART4. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config UART4_RXDMA - bool "UART4 Rx DMA" - default n - depends on STM32U5_UART4 && (STM32U5_DMA2 || STM32U5_DMAMUX) - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -endif # UART4_SERIALDRIVER - -choice - prompt "UART5 Driver Configuration" - default STM32U5_UART5_SERIALDRIVER - depends on STM32U5_UART5 - -config STM32U5_UART5_SERIALDRIVER - bool "Standard serial driver" - select UART5_SERIALDRIVER - select STM32U5_SERIALDRIVER - -config STM32U5_UART5_1WIREDRIVER - bool "1-Wire driver" - select STM32U5_1WIREDRIVER - -endchoice # UART5 Driver Configuration - -if UART5_SERIALDRIVER - -config UART5_RS485 - bool "RS-485 on UART5" - default n - depends on STM32U5_UART5 - ---help--- - Enable RS-485 interface on UART5. Your board config will have to - provide GPIO_UART5_RS485_DIR pin definition. Currently it cannot be - used with UART5_RXDMA. - -config UART5_RS485_DIR_POLARITY - int "UART5 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on UART5_RS485 - ---help--- - Polarity of DIR pin for RS-485 on UART5. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config UART5_RXDMA - bool "UART5 Rx DMA" - default n - depends on STM32U5_UART5 && (STM32U5_DMA2 || STM32U5_DMAMUX) - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -endif # UART5_SERIALDRIVER - -if STM32U5_SERIALDRIVER - -comment "Serial Driver Configuration" - -config STM32U5_SERIAL_RXDMA_BUFFER_SIZE - int "Rx DMA buffer size" - default 32 - depends on USART1_RXDMA || USART2_RXDMA || USART3_RXDMA || UART4_RXDMA || UART5_RXDMA - ---help--- - The DMA buffer size when using RX DMA to emulate a FIFO. - - When streaming data, the generic serial layer will be called - every time the FIFO receives half this number of bytes. - - Value given here will be rounded up to next multiple of 32 bytes. - -config STM32U5_SERIAL_DISABLE_REORDERING - bool "Disable reordering of ttySx devices." - depends on STM32U5_USART1 || STM32U5_USART2 || STM32U5_USART3 || STM32U5_UART4 || STM32U5_UART5 - default n - ---help--- - NuttX per default reorders the serial ports (/dev/ttySx) so that the - console is always on /dev/ttyS0. If more than one UART is in use this - can, however, have the side-effect that all port mappings - (hardware USART1 -> /dev/ttyS0) change if the console is moved to another - UART. This is in particular relevant if a project uses the USB console - in some boards and a serial console in other boards, but does not - want the side effect of having all serial port names change when just - the console is moved from serial to USB. - -config STM32U5_FLOWCONTROL_BROKEN - bool "Use Software UART RTS flow control" - depends on STM32U5_USART - default n - ---help--- - Enable UART RTS flow control using Software. Because STM - Current STM32 have broken HW based RTS behavior (they assert - nRTS after every byte received) Enable this setting workaround - this issue by using software based management of RTS - -config STM32U5_USART_BREAKS - bool "Add TIOxSBRK to support sending Breaks" - depends on STM32U5_USART - default n - ---help--- - Add TIOCxBRK routines to send a line break per the STM32 manual, the - break will be a pulse based on the value M. This is not a BSD compatible - break. - -config STM32U5_SERIALBRK_BSDCOMPAT - bool "Use GPIO To send Break" - depends on STM32U5_USART && STM32U5_USART_BREAKS - default n - ---help--- - Enable using GPIO on the TX pin to send a BSD compatible break: - TIOCSBRK will start the break and TIOCCBRK will end the break. - The current STM32U5 U[S]ARTS have no way to leave the break on - (TX=LOW) because software starts the break and then the hardware - automatically clears the break. This makes it difficult to send - a long break. - -config STM32U5_USART_SINGLEWIRE - bool "Single Wire Support" - default n - depends on STM32U5_USART - ---help--- - Enable single wire UART support. The option enables support for the - TIOCSSINGLEWIRE ioctl in the STM32U5 serial driver. - -config STM32U5_USART_INVERT - bool "Signal Invert Support" - default n - depends on STM32U5_USART - ---help--- - Enable signal inversion UART support. The option enables support for the - TIOCSINVERT ioctl in the STM32U5 serial driver. - -config STM32U5_USART_SWAP - bool "Swap RX/TX pins support" - default n - depends on STM32U5_USART - ---help--- - Enable RX/TX pin swapping support. The option enables support for the - TIOCSSWAP ioctl in the STM32U5 serial driver. - -if PM - -config STM32U5_PM_SERIAL_ACTIVITY - int "PM serial activity" - default 10 - ---help--- - PM activity reported to power management logic on every serial - interrupt. - -endif -endif # STM32U5_SERIALDRIVER - -endmenu # U[S]ART Configuration - -menu "SPI Configuration" - depends on STM32U5_SPI - -config STM32U5_SPI_INTERRUPTS - bool "Interrupt driver SPI" - default n - ---help--- - Select to enable interrupt driven SPI support. Non-interrupt-driven, - poll-waiting is recommended if the interrupt rate would be to high in - the interrupt driven case. - -config STM32U5_SPI_DMA - bool "SPI DMA" - default n - ---help--- - Use DMA to improve SPI transfer performance. Cannot be used with STM32U5_SPI_INTERRUPT. - -endmenu - -config STM32U5_I2C - bool - default n - -menu "I2C Configuration" - depends on STM32U5_I2C - -config STM32U5_I2C_DYNTIMEO - bool "Use dynamic timeouts" - default n - depends on STM32U5_I2C - -config STM32U5_I2C_DYNTIMEO_USECPERBYTE - int "Timeout Microseconds per Byte" - default 500 - depends on STM32U5_I2C_DYNTIMEO - -config STM32U5_I2C_DYNTIMEO_STARTSTOP - int "Timeout for Start/Stop (Milliseconds)" - default 1000 - depends on STM32U5_I2C_DYNTIMEO - -config STM32U5_I2CTIMEOSEC - int "Timeout seconds" - default 0 - depends on STM32U5_I2C - -config STM32U5_I2CTIMEOMS - int "Timeout Milliseconds" - default 500 - depends on STM32U5_I2C && !STM32U5_I2C_DYNTIMEO - -config STM32U5_I2CTIMEOTICKS - int "Timeout for Done and Stop (ticks)" - default 500 - depends on STM32U5_I2C && !STM32U5_I2C_DYNTIMEO - -endmenu - -menu "SD/MMC Configuration" - depends on STM32U5_SDMMC - -config STM32U5_SDMMC_XFRDEBUG - bool "SDMMC transfer debug" - depends on DEBUG_FS_INFO - default n - ---help--- - Enable special debug instrumentation analyze SDMMC data transfers. - This logic is as non-invasive as possible: It samples SDMMC - registers at key points in the data transfer and then dumps all of - the registers at the end of the transfer. If DEBUG_DMA is also - enabled, then DMA register will be collected as well. Requires also - DEBUG_FS and CONFIG_DEBUG_INFO. - -config STM32U5_SDMMC_DMA - bool "Support DMA data transfers" - default n - select SDIO_DMA - depends on STM32U5_DMA - ---help--- - Support DMA data transfers. - -menu "SDMMC1 Configuration" - depends on STM32U5_SDMMC1 - -config STM32U5_SDMMC1_DMAPRIO - hex "SDMMC1 DMA priority" - default 0x00001000 - ---help--- - Select SDMMC1 DMA priority. - - Options are: 0x00000000 low, 0x00001000 medium, - 0x00002000 high, 0x00003000 very high. Default: medium. - -config SDMMC1_WIDTH_D1_ONLY - bool "Use D1 only on SDMMC1" - default n - ---help--- - Select 1-bit transfer mode. Default: 4-bit transfer mode. - -endmenu # SDMMC1 Configuration -endmenu # SD/MMC Configuration - -menu "CAN driver configuration" - depends on STM32U5_CAN1 || STM32U5_CAN2 - -config STM32U5_CAN1_BAUD - int "CAN1 BAUD" - default 250000 - depends on STM32U5_CAN1 - ---help--- - CAN1 BAUD rate. Required if CONFIG_STM32U5_CAN1 is defined. - -config STM32U5_CAN2_BAUD - int "CAN2 BAUD" - default 250000 - depends on STM32U5_CAN2 - ---help--- - CAN2 BAUD rate. Required if CONFIG_STM32U5_CAN2 is defined. - -config STM32U5_CAN_TSEG1 - int "TSEG1 quanta" - default 6 - ---help--- - The number of CAN time quanta in segment 1. Default: 6 - -config STM32U5_CAN_TSEG2 - int "TSEG2 quanta" - default 7 - ---help--- - The number of CAN time quanta in segment 2. Default: 7 - -config STM32U5_CAN_REGDEBUG - bool "CAN Register level debug" - depends on DEBUG_CAN_INFO - default n - ---help--- - Output detailed register-level CAN device debug information. - Requires also CONFIG_DEBUG_CAN_INFO. - -endmenu - -menu "QEncoder Driver" - depends on SENSORS_QENCODER - depends on STM32U5_TIM1 || STM32U5_TIM2 || STM32U5_TIM3 || STM32U5_TIM4 || STM32U5_TIM5 || STM32U5_TIM8 - -config STM32U5_TIM1_QE - bool "TIM1" - default n - depends on STM32U5_TIM1 - ---help--- - Reserve TIM1 for use by QEncoder. - -if STM32U5_TIM1_QE - -config STM32U5_TIM1_QEPSC - int "TIM1 pulse prescaler" - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, limiting the count rate at the expense of resolution. - -endif - -config STM32U5_TIM2_QE - bool "TIM2" - default n - depends on STM32U5_TIM2 - ---help--- - Reserve TIM2 for use by QEncoder. - -if STM32U5_TIM2_QE - -config STM32U5_TIM2_QEPSC - int "TIM2 pulse prescaler" - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, limiting the count rate at the expense of resolution. - -endif - -config STM32U5_TIM3_QE - bool "TIM3" - default n - depends on STM32U5_TIM3 - ---help--- - Reserve TIM3 for use by QEncoder. - -if STM32U5_TIM3_QE - -config STM32U5_TIM3_QEPSC - int "TIM3 pulse prescaler" - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, limiting the count rate at the expense of resolution. - -endif - -config STM32U5_TIM4_QE - bool "TIM4" - default n - depends on STM32U5_TIM4 - ---help--- - Reserve TIM4 for use by QEncoder. - -if STM32U5_TIM4_QE - -config STM32U5_TIM4_QEPSC - int "TIM4 pulse prescaler" - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, limiting the count rate at the expense of resolution. - -endif - -config STM32U5_TIM5_QE - bool "TIM5" - default n - depends on STM32U5_TIM5 - ---help--- - Reserve TIM5 for use by QEncoder. - -if STM32U5_TIM5_QE - -config STM32U5_TIM5_QEPSC - int "TIM5 pulse prescaler" - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, limiting the count rate at the expense of resolution. - -endif - -config STM32U5_TIM8_QE - bool "TIM8" - default n - depends on STM32U5_TIM8 - ---help--- - Reserve TIM8 for use by QEncoder. - -if STM32U5_TIM8_QE - -config STM32U5_TIM8_QEPSC - int "TIM8 pulse prescaler" - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, limiting the count rate at the expense of resolution. - -endif - -config STM32U5_QENCODER_FILTER - bool "Enable filtering on STM32 QEncoder input" - default y - -choice - depends on STM32U5_QENCODER_FILTER - prompt "Input channel sampling frequency" - default STM32U5_QENCODER_SAMPLE_FDTS_4 - -config STM32U5_QENCODER_SAMPLE_FDTS - bool "fDTS" - -config STM32U5_QENCODER_SAMPLE_CKINT - bool "fCK_INT" - -config STM32U5_QENCODER_SAMPLE_FDTS_2 - bool "fDTS/2" - -config STM32U5_QENCODER_SAMPLE_FDTS_4 - bool "fDTS/4" - -config STM32U5_QENCODER_SAMPLE_FDTS_8 - bool "fDTS/8" - -config STM32U5_QENCODER_SAMPLE_FDTS_16 - bool "fDTS/16" - -config STM32U5_QENCODER_SAMPLE_FDTS_32 - bool "fDTS/32" - -endchoice - -choice - depends on STM32U5_QENCODER_FILTER - prompt "Input channel event count" - default STM32U5_QENCODER_SAMPLE_EVENT_6 - -config STM32U5_QENCODER_SAMPLE_EVENT_1 - depends on STM32U5_QENCODER_SAMPLE_FDTS - bool "1" - -config STM32U5_QENCODER_SAMPLE_EVENT_2 - depends on STM32U5_QENCODER_SAMPLE_CKINT - bool "2" - -config STM32U5_QENCODER_SAMPLE_EVENT_4 - depends on STM32U5_QENCODER_SAMPLE_CKINT - bool "4" - -config STM32U5_QENCODER_SAMPLE_EVENT_5 - depends on STM32U5_QENCODER_SAMPLE_FDTS_16 || STM32U5_QENCODER_SAMPLE_FDTS_32 - bool "5" - -config STM32U5_QENCODER_SAMPLE_EVENT_6 - depends on !STM32U5_QENCODER_SAMPLE_FDTS && !STM32U5_QENCODER_SAMPLE_CKINT - bool "6" - -config STM32U5_QENCODER_SAMPLE_EVENT_8 - depends on !STM32U5_QENCODER_SAMPLE_FDTS - bool "8" - -endchoice - -endmenu - -menu "SAI Configuration" - depends on STM32U5_SAI - -choice - prompt "Operation mode" - default STM32U5_SAI_DMA - ---help--- - Select the operation mode the SAI driver should use. - -config STM32U5_SAI_POLLING - bool "Polling" - ---help--- - The SAI registers are polled for events. - -config STM32U5_SAI_INTERRUPTS - bool "Interrupt" - ---help--- - Select to enable interrupt driven SAI support. - -config STM32U5_SAI_DMA - bool "DMA" - ---help--- - Use DMA to improve SAI transfer performance. - -endchoice # Operation mode - -choice - prompt "SAI1 synchronization enable" - default STM32U5_SAI1_BOTH_ASYNC - depends on STM32U5_SAI1_A && STM32U5_SAI1_B - ---help--- - Select the synchronization mode of the SAI sub-blocks - -config STM32U5_SAI1_BOTH_ASYNC - bool "Both asynchronous" - -config STM32U5_SAI1_A_SYNC_WITH_B - bool "Block A is synchronous with Block B" - -config STM32U5_SAI1_B_SYNC_WITH_A - bool "Block B is synchronous with Block A" - -endchoice # SAI1 synchronization enable - -choice - prompt "SAI2 synchronization enable" - default STM32U5_SAI2_BOTH_ASYNC - depends on STM32U5_SAI2_A && STM32U5_SAI2_B - ---help--- - Select the synchronization mode of the SAI sub-blocks - -config STM32U5_SAI2_BOTH_ASYNC - bool "Both asynchronous" - -config STM32U5_SAI2_A_SYNC_WITH_B - bool "Block A is synchronous with Block B" - -config STM32U5_SAI2_B_SYNC_WITH_A - bool "Block B is synchronous with Block A" - -endchoice # SAI2 synchronization enable - -endmenu - endif # ARCH_CHIP_STM32U5 diff --git a/arch/arm/src/stm32u5/hardware/stm32_flash.h b/arch/arm/src/stm32u5/hardware/stm32_flash.h index 8d201546ad1..ea9a8b6990f 100644 --- a/arch/arm/src/stm32u5/hardware/stm32_flash.h +++ b/arch/arm/src/stm32u5/hardware/stm32_flash.h @@ -35,7 +35,7 @@ /* Flash size is known from the chip selection: * - * When CONFIG_STM32U5_FLASH_OVERRIDE_DEFAULT is set the + * When CONFIG_STM32_FLASH_OVERRIDE_DEFAULT is set the * CONFIG_STM32U5_FLASH_CONFIG_x selects the default FLASH size based on * the chip part number. This value can be overridden with * CONFIG_STM32U5_FLASH_OVERRIDE_x @@ -44,30 +44,30 @@ */ #if defined(CONFIG_ARCH_CHIP_STM32U585AI) -# if !defined(CONFIG_STM32U5_FLASH_OVERRIDE_DEFAULT) && \ - !defined(CONFIG_STM32U5_FLASH_OVERRIDE_C) && \ - !defined(CONFIG_STM32U5_FLASH_OVERRIDE_E) && \ - !defined(CONFIG_STM32U5_FLASH_CONFIG_C) && \ - !defined(CONFIG_STM32U5_FLASH_CONFIG_E) -# define CONFIG_STM32U5_FLASH_OVERRIDE_E +# if !defined(CONFIG_STM32_FLASH_OVERRIDE_DEFAULT) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_C) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_E) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_C) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_E) +# define CONFIG_STM32_FLASH_OVERRIDE_E # warning "Flash size not defined defaulting to 512KiB (E)" # endif /* Override of the Flash has been chosen */ -# if !defined(CONFIG_STM32U5_FLASH_OVERRIDE_DEFAULT) -# undef CONFIG_STM32U5_FLASH_CONFIG_C -# undef CONFIG_STM32U5_FLASH_CONFIG_E -# if defined(CONFIG_STM32U5_FLASH_OVERRIDE_C) -# define CONFIG_STM32U5_FLASH_CONFIG_C -# elif defined(CONFIG_STM32U5_FLASH_OVERRIDE_E) -# define CONFIG_STM32U5_FLASH_CONFIG_E +# if !defined(CONFIG_STM32_FLASH_OVERRIDE_DEFAULT) +# undef CONFIG_STM32_FLASH_CONFIG_C +# undef CONFIG_STM32_FLASH_CONFIG_E +# if defined(CONFIG_STM32_FLASH_OVERRIDE_C) +# define CONFIG_STM32_FLASH_CONFIG_C +# elif defined(CONFIG_STM32_FLASH_OVERRIDE_E) +# define CONFIG_STM32_FLASH_CONFIG_E # endif # endif /* Define the valid configuration */ -# if defined(CONFIG_STM32U5_FLASH_CONFIG_I) /* 2048 kB */ +# if defined(CONFIG_STM32_FLASH_CONFIG_I) /* 2048 kB */ # define STM32_FLASH_NPAGES 256 # define STM32_FLASH_PAGESIZE 8192 # else @@ -79,7 +79,7 @@ # define STM32_FLASH_SIZE (STM32_FLASH_NPAGES * STM32_FLASH_PAGESIZE) #endif -#if defined(CONFIG_STM32U5_STM32U5A5XX) +#if defined(CONFIG_STM32_STM32U5A5XX) # define STM32_FLASH_NPAGES 512 # define STM32_FLASH_PAGESIZE 8192 # define STM32_FLASH_SIZE (STM32_FLASH_NPAGES * STM32_FLASH_PAGESIZE) diff --git a/arch/arm/src/stm32u5/hardware/stm32_memorymap.h b/arch/arm/src/stm32u5/hardware/stm32_memorymap.h index 90fe085d6ee..8655250979f 100644 --- a/arch/arm/src/stm32u5/hardware/stm32_memorymap.h +++ b/arch/arm/src/stm32u5/hardware/stm32_memorymap.h @@ -51,7 +51,7 @@ # define STM32_SRAM1_BASE 0x20000000 /* 0x20000000-0x2002ffff: 192k SRAM1 */ # define STM32_SRAM2_BASE 0x20030000 /* 0x20030000-0x2003ffff: 64k SRAM2 */ -#elif defined(CONFIG_STM32U5_STM32U575XX) || defined(CONFIG_STM32U5_STM32U585XX) +#elif defined(CONFIG_STM32U5_STM32U575XX) || defined(CONFIG_STM32_STM32U585XX) # define STM32_BOOT_BASE 0x00000000 /* 0x00000000-0x000fffff: Aliased boot memory */ # define STM32_FLASH_BASE 0x08000000 /* 0x08000000-0x081fffff: FLASH memory */ @@ -60,7 +60,7 @@ # define STM32_SRAM3_BASE 0x20040000 /* 0x20040000-0x200bffff: 512k SRAM3 */ #elif defined(CONFIG_STM32U5_STM32U59XX) || defined(CONFIG_STM32U5_STM32U59AXX) || \ - defined(CONFIG_STM32U5_STM32U5A5XX) || defined(CONFIG_STM32U5_STM32U5A9XX) + defined(CONFIG_STM32_STM32U5A5XX) || defined(CONFIG_STM32U5_STM32U5A9XX) # define STM32_BOOT_BASE 0x00000000 /* 0x00000000-0x000fffff: Aliased boot memory */ # define STM32_FLASH_BASE 0x08000000 /* 0x08000000-0x081fffff: FLASH memory */ diff --git a/arch/arm/src/stm32u5/hardware/stm32_pinmap.h b/arch/arm/src/stm32u5/hardware/stm32_pinmap.h index b289ebb0c42..fd741826012 100644 --- a/arch/arm/src/stm32u5/hardware/stm32_pinmap.h +++ b/arch/arm/src/stm32u5/hardware/stm32_pinmap.h @@ -30,7 +30,7 @@ #include #include "chip.h" -#if defined(CONFIG_STM32U5_STM32U585XX) || defined(CONFIG_STM32U5_STM32U5A5XX) +#if defined(CONFIG_STM32_STM32U585XX) || defined(CONFIG_STM32_STM32U5A5XX) # include "hardware/stm32u5xx_pinmap.h" #else # error "Unsupported STM32U5 pin map" diff --git a/arch/arm/src/stm32u5/hardware/stm32_spi.h b/arch/arm/src/stm32u5/hardware/stm32_spi.h index b13c0664234..e230964aff0 100644 --- a/arch/arm/src/stm32u5/hardware/stm32_spi.h +++ b/arch/arm/src/stm32u5/hardware/stm32_spi.h @@ -31,9 +31,9 @@ #include "chip.h" #if defined(CONFIG_STM32U5_STM32U535XX) || defined(CONFIG_STM32U5_STM32U545XX) || \ - defined(CONFIG_STM32U5_STM32U575XX) || defined(CONFIG_STM32U5_STM32U585XX) || \ + defined(CONFIG_STM32U5_STM32U575XX) || defined(CONFIG_STM32_STM32U585XX) || \ defined(CONFIG_STM32U5_STM32U59XX) || defined(CONFIG_STM32U5_STM32U59AXX) || \ - defined(CONFIG_STM32U5_STM32U5A5XX) || defined(CONFIG_STM32U5_STM32U5A9XX) + defined(CONFIG_STM32_STM32U5A5XX) || defined(CONFIG_STM32U5_STM32U5A9XX) # include "hardware/stm32u5xx_spi.h" #else # error "Unsupported STM32U5 chip" diff --git a/arch/arm/src/stm32u5/hardware/stm32_syscfg.h b/arch/arm/src/stm32u5/hardware/stm32_syscfg.h index 120cbc4f58e..e79236a1fce 100644 --- a/arch/arm/src/stm32u5/hardware/stm32_syscfg.h +++ b/arch/arm/src/stm32u5/hardware/stm32_syscfg.h @@ -30,7 +30,7 @@ #include #include "chip.h" -#if defined(CONFIG_STM32U5_STM32U585XX) || defined(CONFIG_STM32U5_STM32U5A5XX) +#if defined(CONFIG_STM32_STM32U585XX) || defined(CONFIG_STM32_STM32U5A5XX) # include "hardware/stm32u5xx_syscfg.h" #else # error "Unsupported STM32U5 chip" diff --git a/arch/arm/src/stm32u5/hardware/stm32u5xx_rcc.h b/arch/arm/src/stm32u5/hardware/stm32u5xx_rcc.h index a106a9e574c..3e5ca6181a3 100644 --- a/arch/arm/src/stm32u5/hardware/stm32u5xx_rcc.h +++ b/arch/arm/src/stm32u5/hardware/stm32u5xx_rcc.h @@ -30,9 +30,9 @@ #include #if defined(CONFIG_STM32U5_STM32U535XX) || defined(CONFIG_STM32U5_STM32U545XX) || \ - defined(CONFIG_STM32U5_STM32U575XX) || defined(CONFIG_STM32U5_STM32U585XX) || \ + defined(CONFIG_STM32U5_STM32U575XX) || defined(CONFIG_STM32_STM32U585XX) || \ defined(CONFIG_STM32U5_STM32U59XX) || defined(CONFIG_STM32U5_STM32U59AXX) || \ - defined(CONFIG_STM32U5_STM32U5A5XX) || defined(CONFIG_STM32U5_STM32U5A9XX) + defined(CONFIG_STM32_STM32U5A5XX) || defined(CONFIG_STM32U5_STM32U5A9XX) /**************************************************************************** * Pre-processor Definitions diff --git a/arch/arm/src/stm32u5/hardware/stm32u5xx_spi.h b/arch/arm/src/stm32u5/hardware/stm32u5xx_spi.h index e7d98a97aec..241b83dadc9 100644 --- a/arch/arm/src/stm32u5/hardware/stm32u5xx_spi.h +++ b/arch/arm/src/stm32u5/hardware/stm32u5xx_spi.h @@ -30,9 +30,9 @@ #include #if defined(CONFIG_STM32U5_STM32U535XX) || defined(CONFIG_STM32U5_STM32U545XX) || \ - defined(CONFIG_STM32U5_STM32U575XX) || defined(CONFIG_STM32U5_STM32U585XX) || \ + defined(CONFIG_STM32U5_STM32U575XX) || defined(CONFIG_STM32_STM32U585XX) || \ defined(CONFIG_STM32U5_STM32U59XX) || defined(CONFIG_STM32U5_STM32U59AXX) || \ - defined(CONFIG_STM32U5_STM32U5A5XX) || defined(CONFIG_STM32U5_STM32U5A9XX) + defined(CONFIG_STM32_STM32U5A5XX) || defined(CONFIG_STM32U5_STM32U5A9XX) /**************************************************************************** * Pre-processor Definitions diff --git a/arch/arm/src/stm32u5/hardware/stm32u5xx_syscfg.h b/arch/arm/src/stm32u5/hardware/stm32u5xx_syscfg.h index 20bb8da6654..a531723ba39 100644 --- a/arch/arm/src/stm32u5/hardware/stm32u5xx_syscfg.h +++ b/arch/arm/src/stm32u5/hardware/stm32u5xx_syscfg.h @@ -31,9 +31,9 @@ #include "chip.h" #if defined(CONFIG_STM32U5_STM32U535XX) || defined(CONFIG_STM32U5_STM32U545XX) || \ - defined(CONFIG_STM32U5_STM32U575XX) || defined(CONFIG_STM32U5_STM32U585XX) || \ + defined(CONFIG_STM32U5_STM32U575XX) || defined(CONFIG_STM32_STM32U585XX) || \ defined(CONFIG_STM32U5_STM32U59XX) || defined(CONFIG_STM32U5_STM32U59AXX) || \ - defined(CONFIG_STM32U5_STM32U5A5XX) || defined(CONFIG_STM32U5_STM32U5A9XX) + defined(CONFIG_STM32_STM32U5A5XX) || defined(CONFIG_STM32U5_STM32U5A9XX) /**************************************************************************** * Pre-processor Definitions diff --git a/arch/arm/src/stm32u5/stm32_allocateheap.c b/arch/arm/src/stm32u5/stm32_allocateheap.c index ee0220c16d8..3e971fc2bc0 100644 --- a/arch/arm/src/stm32u5/stm32_allocateheap.c +++ b/arch/arm/src/stm32u5/stm32_allocateheap.c @@ -60,7 +60,7 @@ * FSMC. In order to use FSMC SRAM, the following additional things need to * be present in the NuttX configuration file: * - * CONFIG_STM32U5_FSMC=y : Enables the FSMC + * CONFIG_STM32_FSMC=y : Enables the FSMC * CONFIG_STM32U5_FSMC_SRAM=y : Indicates that SRAM is available via the * FSMC (as opposed to an LCD or FLASH). * CONFIG_HEAP2_BASE : The base address of the SRAM in the FSMC @@ -71,7 +71,7 @@ * include the additional regions. */ -#ifndef CONFIG_STM32U5_FSMC +#ifndef CONFIG_STM32_FSMC # undef CONFIG_STM32U5_FSMC_SRAM #endif @@ -121,16 +121,16 @@ * that we have been asked to add to the heap. */ -#if CONFIG_MM_REGIONS < defined(CONFIG_STM32U5_SRAM2_HEAP) + \ - defined(CONFIG_STM32U5_SRAM3_HEAP) + \ - defined(CONFIG_STM32U5_SRAM5_HEAP) + \ +#if CONFIG_MM_REGIONS < defined(CONFIG_STM32_SRAM2_HEAP) + \ + defined(CONFIG_STM32_SRAM3_HEAP) + \ + defined(CONFIG_STM32_SRAM5_HEAP) + \ defined(CONFIG_STM32U5_FSMC_SRAM_HEAP) + 1 # error "You need more memory manager regions to support selected heap components" #endif -#if CONFIG_MM_REGIONS > defined(CONFIG_STM32U5_SRAM2_HEAP) + \ - defined(CONFIG_STM32U5_SRAM3_HEAP) + \ - defined(CONFIG_STM32U5_SRAM5_HEAP) + \ +#if CONFIG_MM_REGIONS > defined(CONFIG_STM32_SRAM2_HEAP) + \ + defined(CONFIG_STM32_SRAM3_HEAP) + \ + defined(CONFIG_STM32_SRAM5_HEAP) + \ defined(CONFIG_STM32U5_FSMC_SRAM_HEAP) + 1 # warning "CONFIG_MM_REGIONS large enough but I do not know what some of the region(s) are" #endif @@ -319,7 +319,7 @@ void up_allocate_kheap(void **heap_start, size_t *heap_size) #if CONFIG_MM_REGIONS > 1 void arm_addregion(void) { -#ifdef CONFIG_STM32U5_SRAM2_HEAP +#ifdef CONFIG_STM32_SRAM2_HEAP # if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP) @@ -339,7 +339,7 @@ void arm_addregion(void) #endif /* SRAM2 */ -#ifdef CONFIG_STM32U5_SRAM3_HEAP +#ifdef CONFIG_STM32_SRAM3_HEAP # if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP) @@ -359,7 +359,7 @@ void arm_addregion(void) #endif /* SRAM3 */ -#ifdef CONFIG_STM32U5_SRAM5_HEAP +#ifdef CONFIG_STM32_SRAM5_HEAP # if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP) diff --git a/arch/arm/src/stm32u5/stm32_dbgmcu.h b/arch/arm/src/stm32u5/stm32_dbgmcu.h index 0db98b7196c..7997e386cbc 100644 --- a/arch/arm/src/stm32u5/stm32_dbgmcu.h +++ b/arch/arm/src/stm32u5/stm32_dbgmcu.h @@ -31,7 +31,7 @@ #include "chip.h" -#if defined(CONFIG_STM32U5_STM32U585XX) || defined(CONFIG_STM32U5_STM32U5A5XX) +#if defined(CONFIG_STM32_STM32U585XX) || defined(CONFIG_STM32_STM32U5A5XX) # include "hardware/stm32u5xx_dbgmcu.h" #else # error "Unsupported STM32U5 chip" diff --git a/arch/arm/src/stm32u5/stm32_exti.h b/arch/arm/src/stm32u5/stm32_exti.h index dd31b1946ef..6693179b0b5 100644 --- a/arch/arm/src/stm32u5/stm32_exti.h +++ b/arch/arm/src/stm32u5/stm32_exti.h @@ -141,7 +141,7 @@ int stm32_exti_wakeup(bool risingedge, bool fallingedge, bool event, * ****************************************************************************/ -#ifdef CONFIG_STM32U5_COMP +#ifdef CONFIG_STM32_COMP int stm32_exti_comp(int cmp, bool risingedge, bool fallingedge, bool event, xcpt_t func, void *arg); #endif diff --git a/arch/arm/src/stm32u5/stm32_flash.c b/arch/arm/src/stm32u5/stm32_flash.c index 586b3154561..526ba889c05 100644 --- a/arch/arm/src/stm32u5/stm32_flash.c +++ b/arch/arm/src/stm32u5/stm32_flash.c @@ -50,13 +50,13 @@ #include "stm32_flash.h" #include "arm_internal.h" -#if !defined(CONFIG_STM32U5_STM32U585XX) -#elif !defined(CONFIG_STM32U5_STM32U5A5XX) +#if !defined(CONFIG_STM32_STM32U585XX) +#elif !defined(CONFIG_STM32_STM32U5A5XX) #else # error "Unrecognized STM32 chip" #endif -#if !defined(CONFIG_STM32U5_FLASH_OVERRIDE_DEFAULT) +#if !defined(CONFIG_STM32_FLASH_OVERRIDE_DEFAULT) # warning "Flash Configuration has been overridden - make sure it is correct" #endif diff --git a/arch/arm/src/stm32u5/stm32_gpio.h b/arch/arm/src/stm32u5/stm32_gpio.h index ad41d5f41b5..5f37922b482 100644 --- a/arch/arm/src/stm32u5/stm32_gpio.h +++ b/arch/arm/src/stm32u5/stm32_gpio.h @@ -39,7 +39,7 @@ #include "chip.h" -#if defined(CONFIG_STM32U5_STM32U585XX) || defined(CONFIG_STM32U5_STM32U5A5XX) +#if defined(CONFIG_STM32_STM32U585XX) || defined(CONFIG_STM32_STM32U5A5XX) # include "hardware/stm32_gpio.h" #else # error "Unsupported STM32U5 chip" diff --git a/arch/arm/src/stm32u5/stm32_i2c.c b/arch/arm/src/stm32u5/stm32_i2c.c index 5ce09917885..2f99e55a86f 100644 --- a/arch/arm/src/stm32u5/stm32_i2c.c +++ b/arch/arm/src/stm32u5/stm32_i2c.c @@ -172,28 +172,28 @@ * * To use this driver, enable the following configuration variable: * - * CONFIG_STM32U5_I2C + * CONFIG_STM32_I2C * * and one or more interfaces: * - * CONFIG_STM32U5_I2C1 - * CONFIG_STM32U5_I2C2 - * CONFIG_STM32U5_I2C3 - * CONFIG_STM32U5_I2C4 + * CONFIG_STM32_I2C1 + * CONFIG_STM32_I2C2 + * CONFIG_STM32_I2C3 + * CONFIG_STM32_I2C4 * * To configure the ISR timeout using fixed values - * (CONFIG_STM32U5_I2C_DYNTIMEO=n): + * (CONFIG_STM32_I2C_DYNTIMEO=n): * - * CONFIG_STM32U5_I2CTIMEOSEC (Timeout in seconds) - * CONFIG_STM32U5_I2CTIMEOMS (Timeout in milliseconds) - * CONFIG_STM32U5_I2CTIMEOTICKS (Timeout in ticks) + * CONFIG_STM32_I2CTIMEOSEC (Timeout in seconds) + * CONFIG_STM32_I2CTIMEOMS (Timeout in milliseconds) + * CONFIG_STM32_I2CTIMEOTICKS (Timeout in ticks) * * To configure the ISR timeout using dynamic values - * (CONFIG_STM32U5_I2C_DYNTIMEO=y): + * (CONFIG_STM32_I2C_DYNTIMEO=y): * - * CONFIG_STM32U5_I2C_DYNTIMEO_USECPERBYTE + * CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE * (Timeout in microseconds per byte) - * CONFIG_STM32U5_I2C_DYNTIMEO_STARTSTOP + * CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP * (Timeout for start/stop inmilliseconds) * * Debugging output enabled with: @@ -273,8 +273,8 @@ /* At least one I2C peripheral must be enabled */ -#if defined(CONFIG_STM32U5_I2C1) || defined(CONFIG_STM32U5_I2C2) || \ - defined(CONFIG_STM32U5_I2C3) || defined(CONFIG_STM32U5_I2C4) +#if defined(CONFIG_STM32_I2C1) || defined(CONFIG_STM32_I2C2) || \ + defined(CONFIG_STM32_I2C3) || defined(CONFIG_STM32_I2C4) /**************************************************************************** * Pre-processor Definitions @@ -286,25 +286,25 @@ /* Interrupt wait timeout in seconds and milliseconds */ -#if !defined(CONFIG_STM32U5_I2CTIMEOSEC) && !defined(CONFIG_STM32U5_I2CTIMEOMS) -# define CONFIG_STM32U5_I2CTIMEOSEC 0 -# define CONFIG_STM32U5_I2CTIMEOMS 500 /* Default is 500 milliseconds */ +#if !defined(CONFIG_STM32_I2CTIMEOSEC) && !defined(CONFIG_STM32_I2CTIMEOMS) +# define CONFIG_STM32_I2CTIMEOSEC 0 +# define CONFIG_STM32_I2CTIMEOMS 500 /* Default is 500 milliseconds */ # warning "Using Default 500 Ms Timeout" -#elif !defined(CONFIG_STM32U5_I2CTIMEOSEC) -# define CONFIG_STM32U5_I2CTIMEOSEC 0 /* User provided milliseconds */ -#elif !defined(CONFIG_STM32U5_I2CTIMEOMS) -# define CONFIG_STM32U5_I2CTIMEOMS 0 /* User provided seconds */ +#elif !defined(CONFIG_STM32_I2CTIMEOSEC) +# define CONFIG_STM32_I2CTIMEOSEC 0 /* User provided milliseconds */ +#elif !defined(CONFIG_STM32_I2CTIMEOMS) +# define CONFIG_STM32_I2CTIMEOMS 0 /* User provided seconds */ #endif /* Interrupt wait time timeout in system timer ticks */ -#ifndef CONFIG_STM32U5_I2CTIMEOTICKS -# define CONFIG_STM32U5_I2CTIMEOTICKS \ - (SEC2TICK(CONFIG_STM32U5_I2CTIMEOSEC) + MSEC2TICK(CONFIG_STM32U5_I2CTIMEOMS)) +#ifndef CONFIG_STM32_I2CTIMEOTICKS +# define CONFIG_STM32_I2CTIMEOTICKS \ + (SEC2TICK(CONFIG_STM32_I2CTIMEOSEC) + MSEC2TICK(CONFIG_STM32_I2CTIMEOMS)) #endif -#ifndef CONFIG_STM32U5_I2C_DYNTIMEO_STARTSTOP -# define CONFIG_STM32U5_I2C_DYNTIMEO_STARTSTOP TICK2USEC(CONFIG_STM32U5_I2CTIMEOTICKS) +#ifndef CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP +# define CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP TICK2USEC(CONFIG_STM32_I2CTIMEOTICKS) #endif /* Macros to convert a I2C pin to a GPIO output */ @@ -472,9 +472,9 @@ static inline void stm32_i2c_modifyreg32(struct stm32_i2c_priv_s *priv, uint8_t offset, uint32_t clearbits, uint32_t setbits); -#ifdef CONFIG_STM32U5_I2C_DYNTIMEO +#ifdef CONFIG_STM32_I2C_DYNTIMEO static uint32_t stm32_i2c_toticks(int msgc, struct i2c_msg_s *msgs); -#endif /* CONFIG_STM32U5_I2C_DYNTIMEO */ +#endif /* CONFIG_STM32_I2C_DYNTIMEO */ static inline int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv); static inline @@ -518,7 +518,7 @@ static int stm32_i2c_pm_prepare(struct pm_callback_s *cb, int domain, * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32U5_I2C1 +#ifdef CONFIG_STM32_I2C1 static const struct stm32_i2c_config_s stm32_i2c1_config = { .base = STM32_I2C1_BASE, @@ -554,7 +554,7 @@ static struct stm32_i2c_priv_s stm32_i2c1_priv = }; #endif -#ifdef CONFIG_STM32U5_I2C2 +#ifdef CONFIG_STM32_I2C2 static const struct stm32_i2c_config_s stm32_i2c2_config = { .base = STM32_I2C2_BASE, @@ -590,7 +590,7 @@ static struct stm32_i2c_priv_s stm32_i2c2_priv = }; #endif -#ifdef CONFIG_STM32U5_I2C3 +#ifdef CONFIG_STM32_I2C3 static const struct stm32_i2c_config_s stm32_i2c3_config = { .base = STM32_I2C3_BASE, @@ -626,7 +626,7 @@ static struct stm32_i2c_priv_s stm32_i2c3_priv = }; #endif -#ifdef CONFIG_STM32U5_I2C4 +#ifdef CONFIG_STM32_I2C4 static const struct stm32_i2c_config_s stm32_i2c4_config = { .base = STM32_I2C4_BASE, @@ -759,7 +759,7 @@ void stm32_i2c_modifyreg32(struct stm32_i2c_priv_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32U5_I2C_DYNTIMEO +#ifdef CONFIG_STM32_I2C_DYNTIMEO static uint32_t stm32_i2c_toticks(int msgc, struct i2c_msg_s *msgs) { size_t bytecount = 0; @@ -776,7 +776,7 @@ static uint32_t stm32_i2c_toticks(int msgc, struct i2c_msg_s *msgs) * factor. */ - return USEC2TICK(CONFIG_STM32U5_I2C_DYNTIMEO_USECPERBYTE * bytecount); + return USEC2TICK(CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE * bytecount); } #endif @@ -834,12 +834,12 @@ int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv) { /* Wait until either the transfer is complete or the timeout expires */ -#ifdef CONFIG_STM32U5_I2C_DYNTIMEO +#ifdef CONFIG_STM32_I2C_DYNTIMEO ret = nxsem_tickwait_uninterruptible(&priv->sem_isr, stm32_i2c_toticks(priv->msgc, priv->msgv)); #else ret = nxsem_tickwait_uninterruptible(&priv->sem_isr, - CONFIG_STM32U5_I2CTIMEOTICKS); + CONFIG_STM32_I2CTIMEOTICKS); #endif if (ret < 0) { @@ -878,10 +878,10 @@ int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv) /* Get the timeout value */ -#ifdef CONFIG_STM32U5_I2C_DYNTIMEO +#ifdef CONFIG_STM32_I2C_DYNTIMEO timeout = stm32_i2c_toticks(priv->msgc, priv->msgv); #else - timeout = CONFIG_STM32U5_I2CTIMEOTICKS; + timeout = CONFIG_STM32_I2CTIMEOTICKS; #endif /* Signal the interrupt handler that we are waiting. NOTE: Interrupts @@ -1023,10 +1023,10 @@ void stm32_i2c_sem_waitstop(struct stm32_i2c_priv_s *priv) /* Select a timeout */ -#ifdef CONFIG_STM32U5_I2C_DYNTIMEO - timeout = USEC2TICK(CONFIG_STM32U5_I2C_DYNTIMEO_STARTSTOP); +#ifdef CONFIG_STM32_I2C_DYNTIMEO + timeout = USEC2TICK(CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP); #else - timeout = CONFIG_STM32U5_I2CTIMEOTICKS; + timeout = CONFIG_STM32_I2CTIMEOTICKS; #endif /* Wait as stop might still be in progress */ @@ -2367,7 +2367,7 @@ static int stm32_i2c_init(struct stm32_i2c_priv_s *priv) /* Enable power and reset the peripheral */ -#ifdef CONFIG_STM32U5_I2C4 +#ifdef CONFIG_STM32_I2C4 if (priv->config->base == STM32_I2C4_BASE) { modifyreg32(STM32_RCC_APB1ENR2, 0, priv->config->clk_bit); @@ -2452,7 +2452,7 @@ static int stm32_i2c_deinit(struct stm32_i2c_priv_s *priv) /* Disable clocking */ -#ifdef CONFIG_STM32U5_I2C4 +#ifdef CONFIG_STM32_I2C4 if (priv->config->base == STM32_I2C4_BASE) { modifyreg32(STM32_RCC_APB1ENR2, priv->config->clk_bit, 0); @@ -2957,22 +2957,22 @@ struct i2c_master_s *stm32_i2cbus_initialize(int port) switch (port) { -#ifdef CONFIG_STM32U5_I2C1 +#ifdef CONFIG_STM32_I2C1 case 1: priv = (struct stm32_i2c_priv_s *)&stm32_i2c1_priv; break; #endif -#ifdef CONFIG_STM32U5_I2C2 +#ifdef CONFIG_STM32_I2C2 case 2: priv = (struct stm32_i2c_priv_s *)&stm32_i2c2_priv; break; #endif -#ifdef CONFIG_STM32U5_I2C3 +#ifdef CONFIG_STM32_I2C3 case 3: priv = (struct stm32_i2c_priv_s *)&stm32_i2c3_priv; break; #endif -#ifdef CONFIG_STM32U5_I2C4 +#ifdef CONFIG_STM32_I2C4 case 4: priv = (struct stm32_i2c_priv_s *)&stm32_i2c4_priv; break; @@ -3058,4 +3058,4 @@ int stm32_i2cbus_uninitialize(struct i2c_master_s *dev) return OK; } -#endif /* CONFIG_STM32U5_I2C1 || CONFIG_STM32U5_I2C2 || CONFIG_STM32U5_I2C3 || CONFIG_STM32U5_I2C4 */ +#endif /* CONFIG_STM32_I2C1 || CONFIG_STM32_I2C2 || CONFIG_STM32_I2C3 || CONFIG_STM32_I2C4 */ diff --git a/arch/arm/src/stm32u5/stm32_i2c.h b/arch/arm/src/stm32u5/stm32_i2c.h index 5f31f8995ac..f34cf0166eb 100644 --- a/arch/arm/src/stm32u5/stm32_i2c.h +++ b/arch/arm/src/stm32u5/stm32_i2c.h @@ -41,10 +41,10 @@ * seconds per byte value must be provided as well. */ -#ifdef CONFIG_STM32U5_I2C_DYNTIMEO -# if CONFIG_STM32U5_I2C_DYNTIMEO_USECPERBYTE < 1 -# warning "Ignoring CONFIG_STM32U5_I2C_DYNTIMEO because of CONFIG_STM32U5_I2C_DYNTIMEO_USECPERBYTE" -# undef CONFIG_STM32U5_I2C_DYNTIMEO +#ifdef CONFIG_STM32_I2C_DYNTIMEO +# if CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE < 1 +# warning "Ignoring CONFIG_STM32_I2C_DYNTIMEO because of CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE" +# undef CONFIG_STM32_I2C_DYNTIMEO # endif #endif diff --git a/arch/arm/src/stm32u5/stm32_idle.c b/arch/arm/src/stm32u5/stm32_idle.c index 08a5d61d44c..f84145eca71 100644 --- a/arch/arm/src/stm32u5/stm32_idle.c +++ b/arch/arm/src/stm32u5/stm32_idle.c @@ -92,7 +92,7 @@ void up_idle(void) /* Sleep until an interrupt occurs to save power. */ -#if !(defined(CONFIG_DEBUG_SYMBOLS) && defined(CONFIG_STM32U5_DISABLE_IDLE_SLEEP_DURING_DEBUG)) +#if !(defined(CONFIG_DEBUG_SYMBOLS) && defined(CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG)) BEGIN_IDLE(); asm("WFI"); END_IDLE(); diff --git a/arch/arm/src/stm32u5/stm32_lse.c b/arch/arm/src/stm32u5/stm32_lse.c index 70438d4e8b0..ebac02e6c54 100644 --- a/arch/arm/src/stm32u5/stm32_lse.c +++ b/arch/arm/src/stm32u5/stm32_lse.c @@ -42,9 +42,9 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, #define LSERDY_TIMEOUT (500 * CONFIG_BOARD_LOOPSPERMSEC) -#ifdef CONFIG_STM32U5_RTC_LSECLOCK_START_DRV_CAPABILITY -# if CONFIG_STM32U5_RTC_LSECLOCK_START_DRV_CAPABILITY < 0 || \ - CONFIG_STM32U5_RTC_LSECLOCK_START_DRV_CAPABILITY > 3 +#ifdef CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY +# if CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY < 0 || \ + CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY > 3 # error "Invalid LSE drive capability setting" # endif #endif @@ -53,7 +53,7 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32U5_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY +#ifdef CONFIG_STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY static const uint32_t drives[4] = { RCC_BDCR_LSEDRV_LOW, @@ -80,7 +80,7 @@ void stm32_rcc_enablelse(void) bool writable; uint32_t regval; volatile int32_t timeout; -#ifdef CONFIG_STM32U5_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY +#ifdef CONFIG_STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY volatile int32_t drive = 0; #endif @@ -108,19 +108,19 @@ void stm32_rcc_enablelse(void) regval |= RCC_BDCR_LSEON; -#ifdef CONFIG_STM32U5_RTC_LSECLOCK_START_DRV_CAPABILITY +#ifdef CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY /* Set start-up drive capability for LSE oscillator. LSE must be OFF * to change drive strength. */ regval &= ~(RCC_BDCR_LSEDRV_MASK | RCC_BDCR_LSEON); - regval |= CONFIG_STM32U5_RTC_LSECLOCK_START_DRV_CAPABILITY << + regval |= CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY << RCC_BDCR_LSEDRV_SHIFT; putreg32(regval, STM32_RCC_BDCR); regval |= RCC_BDCR_LSEON; #endif -#ifdef CONFIG_STM32U5_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY +#ifdef CONFIG_STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY do { regval &= ~(RCC_BDCR_LSEDRV_MASK | RCC_BDCR_LSEON); @@ -148,7 +148,7 @@ void stm32_rcc_enablelse(void) } } -#ifdef CONFIG_STM32U5_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY +#ifdef CONFIG_STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY if (timeout != 0) { break; @@ -177,7 +177,7 @@ void stm32_rcc_enablelse(void) } } -#ifdef CONFIG_STM32U5_RTC_LSECLOCK_LOWER_RUN_DRV_CAPABILITY +#ifdef CONFIG_STM32_RTC_LSECLOCK_LOWER_RUN_DRV_CAPABILITY /* Set running drive capability for LSE oscillator. */ diff --git a/arch/arm/src/stm32u5/stm32_rcc.c b/arch/arm/src/stm32u5/stm32_rcc.c index 2b2972cde72..2e7ac13bb44 100644 --- a/arch/arm/src/stm32u5/stm32_rcc.c +++ b/arch/arm/src/stm32u5/stm32_rcc.c @@ -83,7 +83,7 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, * ****************************************************************************/ -#if defined(CONFIG_STM32U5_PWR) && defined(CONFIG_STM32U5_RTC) +#if defined(CONFIG_STM32_PWR) && defined(CONFIG_STM32_RTC) static inline void rcc_resetbkp(void) { bool init_stat; @@ -148,7 +148,7 @@ static inline void rcc_resetbkp(void) * and enable peripheral clocking for all peripherals enabled in the NuttX * configuration file. * - * If CONFIG_ARCH_BOARD_STM32U5_CUSTOM_CLOCKCONFIG is defined, then + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then * clocking will be enabled by an externally provided, board-specific * function called stm32_board_clockconfig(). * @@ -171,7 +171,7 @@ void stm32_clockconfig(void) rcc_resetbkp(); #endif -#if defined(CONFIG_ARCH_BOARD_STM32U5_CUSTOM_CLOCKCONFIG) +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) /* Invoke Board Custom Clock Configuration */ @@ -205,7 +205,7 @@ void stm32_clockconfig(void) * stm32_clockconfig() * reset the currently enabled peripheral clocks. * - * If CONFIG_ARCH_BOARD_STM32U5_CUSTOM_CLOCKCONFIG is defined, then + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then * clocking will be enabled by an externally provided, board-specific * function called stm32_board_clockconfig(). * @@ -220,7 +220,7 @@ void stm32_clockconfig(void) #ifdef CONFIG_PM void stm32_clockenable(void) { -#if defined(CONFIG_ARCH_BOARD_STM32U5_CUSTOM_CLOCKCONFIG) +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) /* Invoke Board Custom Clock Configuration */ diff --git a/arch/arm/src/stm32u5/stm32_rcc.h b/arch/arm/src/stm32u5/stm32_rcc.h index b788f167de9..ae75e4a2356 100644 --- a/arch/arm/src/stm32u5/stm32_rcc.h +++ b/arch/arm/src/stm32u5/stm32_rcc.h @@ -32,7 +32,7 @@ #include "arm_internal.h" #include "chip.h" -#if defined(CONFIG_STM32U5_STM32U585XX) || defined(CONFIG_STM32U5_STM32U5A5XX) +#if defined(CONFIG_STM32_STM32U585XX) || defined(CONFIG_STM32_STM32U5A5XX) # include "hardware/stm32u5xx_rcc.h" #else # error "Unsupported STM32U5 chip" @@ -97,7 +97,7 @@ static inline void stm32_mcoconfig(uint32_t source) * and enable peripheral clocking for all periperipherals enabled in the * NuttX configuration file. * - * If CONFIG_ARCH_BOARD_STM32U5_CUSTOM_CLOCKCONFIG is defined, then + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then * clocking will be enabled by an externally provided, board-specific * function called stm32_board_clockconfig(). * @@ -120,7 +120,7 @@ void stm32_clockconfig(void); * ****************************************************************************/ -#ifdef CONFIG_ARCH_BOARD_STM32U5_CUSTOM_CLOCKCONFIG +#ifdef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG void stm32_board_clockconfig(void); #endif @@ -135,7 +135,7 @@ void stm32_board_clockconfig(void); * ****************************************************************************/ -#ifndef CONFIG_ARCH_BOARD_STM32U5_CUSTOM_CLOCKCONFIG +#ifndef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG void stm32_stdclockconfig(void); #endif @@ -152,7 +152,7 @@ void stm32_stdclockconfig(void); * stm32_clockconfig(): It does not reset any devices, and it does not * reset the currently enabled peripheral clocks. * - * If CONFIG_ARCH_BOARD_STM32U5_CUSTOM_CLOCKCONFIG is defined, then + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then * clocking will be enabled by an externally provided, board-specific * function called stm32_board_clockconfig(). * diff --git a/arch/arm/src/stm32u5/stm32_serial.c b/arch/arm/src/stm32u5/stm32_serial.c index a5aea799e96..13d539fdb78 100644 --- a/arch/arm/src/stm32u5/stm32_serial.c +++ b/arch/arm/src/stm32u5/stm32_serial.c @@ -82,14 +82,14 @@ */ # if defined(CONFIG_USART2_RXDMA) || defined(CONFIG_USART3_RXDMA) -# if !defined(CONFIG_STM32U5_DMA1) && !defined(CONFIG_STM32U5_DMAMUX) -# error STM32U5 USART2/3 receive DMA requires CONFIG_STM32U5_DMA1 +# if !defined(CONFIG_STM32_DMA1) && !defined(CONFIG_STM32_DMAMUX) +# error STM32U5 USART2/3 receive DMA requires CONFIG_STM32_DMA1 # endif # endif # if defined(CONFIG_UART4_RXDMA) || defined(CONFIG_UART5_RXDMA) -# if !defined(CONFIG_STM32U5_DMA2) && !defined(CONFIG_STM32U5_DMAMUX) -# error STM32U5 UART4/5 receive DMA requires CONFIG_STM32U5_DMA2 +# if !defined(CONFIG_STM32_DMA2) && !defined(CONFIG_STM32_DMAMUX) +# error STM32U5 UART4/5 receive DMA requires CONFIG_STM32_DMA2 # endif # endif @@ -116,7 +116,7 @@ /* UART2-5 have no alternate channels without DMAMUX */ -# ifndef CONFIG_STM32U5_HAVE_DMAMUX +# ifndef CONFIG_STM32_HAVE_DMAMUX # define DMAMAP_USART2_RX DMACHAN_USART2_RX # define DMAMAP_USART3_RX DMACHAN_USART3_RX # define DMAMAP_UART4_RX DMACHAN_UART4_RX @@ -149,11 +149,11 @@ * can be individually invalidated. */ -# if !defined(CONFIG_STM32U5_SERIAL_RXDMA_BUFFER_SIZE) || \ - CONFIG_STM32U5_SERIAL_RXDMA_BUFFER_SIZE == 0 +# if !defined(CONFIG_STM32_SERIAL_RXDMA_BUFFER_SIZE) || \ + CONFIG_STM32_SERIAL_RXDMA_BUFFER_SIZE == 0 # define RXDMA_BUFFER_SIZE 32 # else -# define RXDMA_BUFFER_SIZE ((CONFIG_STM32U5_SERIAL_RXDMA_BUFFER_SIZE + 31) & ~31) +# define RXDMA_BUFFER_SIZE ((CONFIG_STM32_SERIAL_RXDMA_BUFFER_SIZE + 31) & ~31) # endif /* DMA priority */ @@ -185,8 +185,8 @@ /* Power management definitions */ -#if defined(CONFIG_PM) && !defined(CONFIG_STM32U5_PM_SERIAL_ACTIVITY) -# define CONFIG_STM32U5_PM_SERIAL_ACTIVITY 10 +#if defined(CONFIG_PM) && !defined(CONFIG_STM32_PM_SERIAL_ACTIVITY) +# define CONFIG_STM32_PM_SERIAL_ACTIVITY 10 #endif /* Keep track if a Break was set @@ -200,7 +200,7 @@ * See stm32serial_restoreusartint where the masking is done. */ -#ifdef CONFIG_STM32U5_SERIALBRK_BSDCOMPAT +#ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT # define USART_CR1_IE_BREAK_INPROGRESS_SHFTS 15 # define USART_CR1_IE_BREAK_INPROGRESS (1 << USART_CR1_IE_BREAK_INPROGRESS_SHFTS) #endif @@ -395,7 +395,7 @@ static const struct uart_ops_s g_uart_dma_ops = /* I/O buffers */ -#ifdef CONFIG_STM32U5_LPUART1_SERIALDRIVER +#ifdef CONFIG_STM32_LPUART1_SERIALDRIVER static char g_lpuart1rxbuffer[CONFIG_LPUART1_RXBUFSIZE]; static char g_lpuart1txbuffer[CONFIG_LPUART1_TXBUFSIZE]; # ifdef CONFIG_LPUART1_RXDMA @@ -403,7 +403,7 @@ static char g_lpuart1rxfifo[RXDMA_BUFFER_SIZE]; # endif #endif -#ifdef CONFIG_STM32U5_USART1_SERIALDRIVER +#ifdef CONFIG_STM32_USART1_SERIALDRIVER static char g_usart1rxbuffer[CONFIG_USART1_RXBUFSIZE]; static char g_usart1txbuffer[CONFIG_USART1_TXBUFSIZE]; # ifdef CONFIG_USART1_RXDMA @@ -411,7 +411,7 @@ static char g_usart1rxfifo[RXDMA_BUFFER_SIZE]; # endif #endif -#ifdef CONFIG_STM32U5_USART2_SERIALDRIVER +#ifdef CONFIG_STM32_USART2_SERIALDRIVER static char g_usart2rxbuffer[CONFIG_USART2_RXBUFSIZE]; static char g_usart2txbuffer[CONFIG_USART2_TXBUFSIZE]; # ifdef CONFIG_USART2_RXDMA @@ -419,7 +419,7 @@ static char g_usart2rxfifo[RXDMA_BUFFER_SIZE]; # endif #endif -#ifdef CONFIG_STM32U5_USART3_SERIALDRIVER +#ifdef CONFIG_STM32_USART3_SERIALDRIVER static char g_usart3rxbuffer[CONFIG_USART3_RXBUFSIZE]; static char g_usart3txbuffer[CONFIG_USART3_TXBUFSIZE]; # ifdef CONFIG_USART3_RXDMA @@ -427,7 +427,7 @@ static char g_usart3rxfifo[RXDMA_BUFFER_SIZE]; # endif #endif -#ifdef CONFIG_STM32U5_UART4_SERIALDRIVER +#ifdef CONFIG_STM32_UART4_SERIALDRIVER static char g_uart4rxbuffer[CONFIG_UART4_RXBUFSIZE]; static char g_uart4txbuffer[CONFIG_UART4_TXBUFSIZE]; # ifdef CONFIG_UART4_RXDMA @@ -435,7 +435,7 @@ static char g_uart4rxfifo[RXDMA_BUFFER_SIZE]; # endif #endif -#ifdef CONFIG_STM32U5_UART5_SERIALDRIVER +#ifdef CONFIG_STM32_UART5_SERIALDRIVER static char g_uart5rxbuffer[CONFIG_UART5_RXBUFSIZE]; static char g_uart5txbuffer[CONFIG_UART5_TXBUFSIZE]; # ifdef CONFIG_UART5_RXDMA @@ -445,7 +445,7 @@ static char g_uart5rxfifo[RXDMA_BUFFER_SIZE]; /* This describes the state of the STM32 USART1 ports. */ -#ifdef CONFIG_STM32U5_LPUART1_SERIALDRIVER +#ifdef CONFIG_STM32_LPUART1_SERIALDRIVER static struct stm32_serial_s g_lpuart1priv = { .dev = @@ -505,7 +505,7 @@ static struct stm32_serial_s g_lpuart1priv = }; #endif -#ifdef CONFIG_STM32U5_USART1_SERIALDRIVER +#ifdef CONFIG_STM32_USART1_SERIALDRIVER static struct stm32_serial_s g_usart1priv = { .dev = @@ -567,7 +567,7 @@ static struct stm32_serial_s g_usart1priv = /* This describes the state of the STM32 USART2 port. */ -#ifdef CONFIG_STM32U5_USART2_SERIALDRIVER +#ifdef CONFIG_STM32_USART2_SERIALDRIVER static struct stm32_serial_s g_usart2priv = { .dev = @@ -629,7 +629,7 @@ static struct stm32_serial_s g_usart2priv = /* This describes the state of the STM32 USART3 port. */ -#ifdef CONFIG_STM32U5_USART3_SERIALDRIVER +#ifdef CONFIG_STM32_USART3_SERIALDRIVER static struct stm32_serial_s g_usart3priv = { .dev = @@ -691,7 +691,7 @@ static struct stm32_serial_s g_usart3priv = /* This describes the state of the STM32 UART4 port. */ -#ifdef CONFIG_STM32U5_UART4_SERIALDRIVER +#ifdef CONFIG_STM32_UART4_SERIALDRIVER static struct stm32_serial_s g_uart4priv = { .dev = @@ -753,7 +753,7 @@ static struct stm32_serial_s g_uart4priv = /* This describes the state of the STM32 UART5 port. */ -#ifdef CONFIG_STM32U5_UART5_SERIALDRIVER +#ifdef CONFIG_STM32_UART5_SERIALDRIVER static struct stm32_serial_s g_uart5priv = { .dev = @@ -818,22 +818,22 @@ static struct stm32_serial_s g_uart5priv = static struct stm32_serial_s * const g_uart_devs[STM32_NLPUART + STM32_NUSART + STM32_NUART] = { -#ifdef CONFIG_STM32U5_LPUART1_SERIALDRIVER +#ifdef CONFIG_STM32_LPUART1_SERIALDRIVER [0] = &g_lpuart1priv, #endif -#ifdef CONFIG_STM32U5_USART1_SERIALDRIVER +#ifdef CONFIG_STM32_USART1_SERIALDRIVER [1] = &g_usart1priv, #endif -#ifdef CONFIG_STM32U5_USART2_SERIALDRIVER +#ifdef CONFIG_STM32_USART2_SERIALDRIVER [2] = &g_usart2priv, #endif -#ifdef CONFIG_STM32U5_USART3_SERIALDRIVER +#ifdef CONFIG_STM32_USART3_SERIALDRIVER [3] = &g_usart3priv, #endif -#ifdef CONFIG_STM32U5_UART4_SERIALDRIVER +#ifdef CONFIG_STM32_UART4_SERIALDRIVER [4] = &g_uart4priv, #endif -#ifdef CONFIG_STM32U5_UART5_SERIALDRIVER +#ifdef CONFIG_STM32_UART5_SERIALDRIVER [5] = &g_uart5priv, #endif }; @@ -1125,7 +1125,7 @@ static void stm32serial_setformat(struct uart_dev_s *dev) regval = stm32serial_getreg(priv, STM32_USART_CR3_OFFSET); regval &= ~(USART_CR3_CTSE | USART_CR3_RTSE); -#if defined(CONFIG_SERIAL_IFLOWCONTROL) && !defined(CONFIG_STM32U5_FLOWCONTROL_BROKEN) +#if defined(CONFIG_SERIAL_IFLOWCONTROL) && !defined(CONFIG_STM32_FLOWCONTROL_BROKEN) if (priv->iflow && (priv->rts_gpio != 0)) { regval |= USART_CR3_RTSE; @@ -1329,37 +1329,37 @@ static void stm32serial_setapbclock(struct uart_dev_s *dev, bool on) { default: return; -#ifdef CONFIG_STM32U5_LPUART1_SERIALDRIVER +#ifdef CONFIG_STM32_LPUART1_SERIALDRIVER case STM32_LPUART1_BASE: rcc_en = RCC_APB1ENR2_LPUART1EN; regaddr = STM32_RCC_APB1ENR2; break; #endif -#ifdef CONFIG_STM32U5_USART1_SERIALDRIVER +#ifdef CONFIG_STM32_USART1_SERIALDRIVER case STM32_USART1_BASE: rcc_en = RCC_APB2ENR_USART1EN; regaddr = STM32_RCC_APB2ENR; break; #endif -#ifdef CONFIG_STM32U5_USART2_SERIALDRIVER +#ifdef CONFIG_STM32_USART2_SERIALDRIVER case STM32_USART2_BASE: rcc_en = RCC_APB1ENR1_USART2EN; regaddr = STM32_RCC_APB1ENR1; break; #endif -#ifdef CONFIG_STM32U5_USART3_SERIALDRIVER +#ifdef CONFIG_STM32_USART3_SERIALDRIVER case STM32_USART3_BASE: rcc_en = RCC_APB1ENR1_USART3EN; regaddr = STM32_RCC_APB1ENR1; break; #endif -#ifdef CONFIG_STM32U5_UART4_SERIALDRIVER +#ifdef CONFIG_STM32_UART4_SERIALDRIVER case STM32_UART4_BASE: rcc_en = RCC_APB1ENR1_UART4EN; regaddr = STM32_RCC_APB1ENR1; break; #endif -#ifdef CONFIG_STM32U5_UART5_SERIALDRIVER +#ifdef CONFIG_STM32_UART5_SERIALDRIVER case STM32_UART5_BASE: rcc_en = RCC_APB1ENR1_UART5EN; regaddr = STM32_RCC_APB1ENR1; @@ -1428,7 +1428,7 @@ static int stm32serial_setup(struct uart_dev_s *dev) { uint32_t config = priv->rts_gpio; -#ifdef CONFIG_STM32U5_FLOWCONTROL_BROKEN +#ifdef CONFIG_STM32_FLOWCONTROL_BROKEN /* Instead of letting hw manage this pin, we will bitbang */ config = (config & ~GPIO_MODE_MASK) | GPIO_OUTPUT; @@ -1779,8 +1779,8 @@ static int stm32serial_interrupt(int irq, void *context, void *arg) /* Report serial activity to the power management logic */ -#if defined(CONFIG_PM) && CONFIG_STM32U5_PM_SERIAL_ACTIVITY > 0 - pm_activity(PM_IDLE_DOMAIN, CONFIG_STM32U5_PM_SERIAL_ACTIVITY); +#if defined(CONFIG_PM) && CONFIG_STM32_PM_SERIAL_ACTIVITY > 0 + pm_activity(PM_IDLE_DOMAIN, CONFIG_STM32_PM_SERIAL_ACTIVITY); #endif /* Loop until there are no characters to be transferred or, @@ -1923,7 +1923,7 @@ static int stm32serial_ioctl(struct file *filep, int cmd, break; #endif -#ifdef CONFIG_STM32U5_USART_SINGLEWIRE +#ifdef CONFIG_STM32_USART_SINGLEWIRE case TIOCSSINGLEWIRE: { uint32_t cr1; @@ -2001,7 +2001,7 @@ static int stm32serial_ioctl(struct file *filep, int cmd, break; #endif -#ifdef CONFIG_STM32U5_USART_INVERT +#ifdef CONFIG_STM32_USART_INVERT case TIOCSINVERT: { uint32_t cr1; @@ -2052,7 +2052,7 @@ static int stm32serial_ioctl(struct file *filep, int cmd, break; #endif -#ifdef CONFIG_STM32U5_USART_SWAP +#ifdef CONFIG_STM32_USART_SWAP case TIOCSSWAP: { uint32_t cr1; @@ -2189,8 +2189,8 @@ static int stm32serial_ioctl(struct file *filep, int cmd, break; #endif /* CONFIG_SERIAL_TERMIOS */ -#ifdef CONFIG_STM32U5_USART_BREAKS -# ifdef CONFIG_STM32U5_SERIALBRK_BSDCOMPAT +#ifdef CONFIG_STM32_USART_BREAKS +# ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT case TIOCSBRK: /* BSD compatibility: Turn break on, unconditionally */ { irqstate_t flags; @@ -2418,7 +2418,7 @@ static bool stm32serial_rxflowcontrol(struct uart_dev_s *dev, (struct stm32_serial_s *)dev->priv; #if defined(CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS) && \ - defined(CONFIG_STM32U5_FLOWCONTROL_BROKEN) + defined(CONFIG_STM32_FLOWCONTROL_BROKEN) if (priv->iflow && (priv->rts_gpio != 0)) { /* Assert/de-assert nRTS set it high resume/stop sending */ @@ -2770,7 +2770,7 @@ static void stm32serial_txint(struct uart_dev_s *dev, bool enable) } # endif -# ifdef CONFIG_STM32U5_SERIALBRK_BSDCOMPAT +# ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT if (priv->ie & USART_CR1_IE_BREAK_INPROGRESS) { leave_critical_section(flags); @@ -3111,7 +3111,7 @@ void arm_serialinit(void) #if CONSOLE_UART > 0 uart_register("/dev/console", &g_uart_devs[CONSOLE_UART - 1]->dev); -#ifndef CONFIG_STM32U5_SERIAL_DISABLE_REORDERING +#ifndef CONFIG_STM32_SERIAL_DISABLE_REORDERING /* If not disabled, register the console UART to ttyS0 and exclude * it from initializing it further down */ @@ -3140,7 +3140,7 @@ void arm_serialinit(void) continue; } -#ifndef CONFIG_STM32U5_SERIAL_DISABLE_REORDERING +#ifndef CONFIG_STM32_SERIAL_DISABLE_REORDERING /* Don't create a device for the console - we did that above */ if (g_uart_devs[i]->dev.isconsole) diff --git a/arch/arm/src/stm32u5/stm32_spi.c b/arch/arm/src/stm32u5/stm32_spi.c index bf4ded9c901..82ceb35c60d 100644 --- a/arch/arm/src/stm32u5/stm32_spi.c +++ b/arch/arm/src/stm32u5/stm32_spi.c @@ -74,8 +74,8 @@ #include "stm32_gpio.h" #include "stm32_spi.h" -#if defined(CONFIG_STM32U5_SPI1) || defined(CONFIG_STM32U5_SPI2) || \ - defined(CONFIG_STM32U5_SPI3) +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ + defined(CONFIG_STM32_SPI3) /**************************************************************************** * Pre-processor Definitions @@ -85,19 +85,19 @@ /* SPI interrupts */ -#ifdef CONFIG_STM32U5_SPI_INTERRUPTS +#ifdef CONFIG_STM32_SPI_INTERRUPTS # error "Interrupt driven SPI not yet supported" #endif /* Can't have both interrupt driven SPI and SPI DMA */ -#if defined(CONFIG_STM32U5_SPI_INTERRUPTS) && defined(CONFIG_STM32U5_SPI_DMA) +#if defined(CONFIG_STM32_SPI_INTERRUPTS) && defined(CONFIG_STM32_SPI_DMA) # error "Cannot enable both interrupt mode and DMA mode for SPI" #endif /* SPI DMA priority */ -#ifdef CONFIG_STM32U5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA # if defined(CONFIG_SPI_DMAPRIO) # define SPI_DMA_PRIO CONFIG_SPI_DMAPRIO @@ -135,21 +135,21 @@ # define SPIDMA_BUF_ALIGN # endif -# if defined(CONFIG_STM32U5_SPI1_DMA_BUFFER) && \ - CONFIG_STM32U5_SPI1_DMA_BUFFER > 0 -# define SPI1_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32U5_SPI1_DMA_BUFFER) +# if defined(CONFIG_STM32_SPI1_DMA_BUFFER) && \ + CONFIG_STM32_SPI1_DMA_BUFFER > 0 +# define SPI1_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32_SPI1_DMA_BUFFER) # define SPI1_DMABUFSIZE_ALGN SPIDMA_BUF_ALIGN # endif -# if defined(CONFIG_STM32U5_SPI2_DMA_BUFFER) && \ - CONFIG_STM32U5_SPI2_DMA_BUFFER > 0 -# define SPI2_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32U5_SPI2_DMA_BUFFER) +# if defined(CONFIG_STM32_SPI2_DMA_BUFFER) && \ + CONFIG_STM32_SPI2_DMA_BUFFER > 0 +# define SPI2_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32_SPI2_DMA_BUFFER) # define SPI2_DMABUFSIZE_ALGN SPIDMA_BUF_ALIGN # endif -# if defined(CONFIG_STM32U5_SPI3_DMA_BUFFER) && \ - CONFIG_STM32U5_SPI3_DMA_BUFFER > 0 -# define SPI3_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32U5_SPI3_DMA_BUFFER) +# if defined(CONFIG_STM32_SPI3_DMA_BUFFER) && \ + CONFIG_STM32_SPI3_DMA_BUFFER > 0 +# define SPI3_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32_SPI3_DMA_BUFFER) # define SPI3_DMABUFSIZE_ALGN SPIDMA_BUF_ALIGN # endif @@ -160,15 +160,15 @@ * - support for all kernel clock configuration */ -#if defined(CONFIG_STM32U5_SPI1) +#if defined(CONFIG_STM32_SPI1) # define SPI1_KERNEL_CLOCK_FREQ STM32_PCLK2_FREQUENCY #endif -#if defined(CONFIG_STM32U5_SPI2) +#if defined(CONFIG_STM32_SPI2) # define SPI2_KERNEL_CLOCK_FREQ STM32_PCLK1_FREQUENCY #endif -#if defined(CONFIG_STM32U5_SPI3) +#if defined(CONFIG_STM32_SPI3) # define SPI3_KERNEL_CLOCK_FREQ STM32_PCLK3_FREQUENCY #endif @@ -190,7 +190,7 @@ struct stm32_spidev_s uint32_t spibase; /* SPIn base address */ uint32_t spiclock; /* Clocking for the SPI module */ uint8_t spiirq; /* SPI IRQ number */ -#ifdef CONFIG_STM32U5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA volatile uint8_t rxresult; /* Result of the RX DMA */ volatile uint8_t txresult; /* Result of the RX DMA */ #ifdef CONFIG_SPI_TRIGGER @@ -240,7 +240,7 @@ static inline void spi_dumpregs(struct stm32_spidev_s *priv); /* DMA support */ -#ifdef CONFIG_STM32U5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static int spi_dmarxwait(struct stm32_spidev_s *priv); static int spi_dmatxwait(struct stm32_spidev_s *priv); static inline void spi_dmarxwakeup(struct stm32_spidev_s *priv); @@ -306,7 +306,7 @@ static int spi_pm_prepare(struct pm_callback_s *cb, int domain, * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32U5_SPI1 +#ifdef CONFIG_STM32_SPI1 static const struct spi_ops_s g_sp1iops = { .lock = spi_lock, @@ -355,7 +355,7 @@ static struct stm32_spidev_s g_spi1dev = .spibase = STM32_SPI1_BASE, .spiclock = SPI1_KERNEL_CLOCK_FREQ, .spiirq = STM32_IRQ_SPI1, -#ifdef CONFIG_STM32U5_SPI1_DMA +#ifdef CONFIG_STM32_SPI1_DMA .rxch = DMAMAP_SPI1_RX, .txch = DMAMAP_SPI1_TX, # if defined(SPI1_DMABUFSIZE_ADJUSTED) @@ -370,15 +370,15 @@ static struct stm32_spidev_s g_spi1dev = #ifdef CONFIG_PM .pm_cb.prepare = spi_pm_prepare, #endif -#ifdef CONFIG_STM32U5_SPI1_COMMTYPE - .config = CONFIG_STM32U5_SPI1_COMMTYPE, +#ifdef CONFIG_STM32_SPI1_COMMTYPE + .config = CONFIG_STM32_SPI1_COMMTYPE, #else .config = FULL_DUPLEX, #endif }; -#endif /* CONFIG_STM32U5_SPI1 */ +#endif /* CONFIG_STM32_SPI1 */ -#ifdef CONFIG_STM32U5_SPI2 +#ifdef CONFIG_STM32_SPI2 static const struct spi_ops_s g_sp2iops = { .lock = spi_lock, @@ -427,7 +427,7 @@ static struct stm32_spidev_s g_spi2dev = .spibase = STM32_SPI2_BASE, .spiclock = SPI2_KERNEL_CLOCK_FREQ, .spiirq = STM32_IRQ_SPI2, -#ifdef CONFIG_STM32U5_SPI2_DMA +#ifdef CONFIG_STM32_SPI2_DMA .rxch = DMAMAP_SPI2_RX, .txch = DMAMAP_SPI2_TX, # if defined(SPI2_DMABUFSIZE_ADJUSTED) @@ -442,15 +442,15 @@ static struct stm32_spidev_s g_spi2dev = #ifdef CONFIG_PM .pm_cb.prepare = spi_pm_prepare, #endif -#ifdef CONFIG_STM32U5_SPI2_COMMTYPE - .config = CONFIG_STM32U5_SPI2_COMMTYPE, +#ifdef CONFIG_STM32_SPI2_COMMTYPE + .config = CONFIG_STM32_SPI2_COMMTYPE, #else .config = FULL_DUPLEX, #endif }; -#endif /* CONFIG_STM32U5_SPI2 */ +#endif /* CONFIG_STM32_SPI2 */ -#ifdef CONFIG_STM32U5_SPI3 +#ifdef CONFIG_STM32_SPI3 static const struct spi_ops_s g_sp3iops = { .lock = spi_lock, @@ -499,7 +499,7 @@ static struct stm32_spidev_s g_spi3dev = .spibase = STM32_SPI3_BASE, .spiclock = SPI3_KERNEL_CLOCK_FREQ, .spiirq = STM32_IRQ_SPI3, -#ifdef CONFIG_STM32U5_SPI3_DMA +#ifdef CONFIG_STM32_SPI3_DMA .rxch = DMAMAP_SPI3_RX, .txch = DMAMAP_SPI3_TX, # if defined(SPI3_DMABUFSIZE_ADJUSTED) @@ -514,13 +514,13 @@ static struct stm32_spidev_s g_spi3dev = #ifdef CONFIG_PM .pm_cb.prepare = spi_pm_prepare, #endif -#ifdef CONFIG_STM32U5_SPI3_COMMTYPE - .config = CONFIG_STM32U5_SPI3_COMMTYPE, +#ifdef CONFIG_STM32_SPI3_COMMTYPE + .config = CONFIG_STM32_SPI3_COMMTYPE, #else .config = FULL_DUPLEX, #endif }; -#endif /* CONFIG_STM32U5_SPI3 */ +#endif /* CONFIG_STM32_SPI3 */ /**************************************************************************** * Private Functions @@ -840,7 +840,7 @@ static int spi_interrupt(int irq, void *context, void *arg) spi_modifyreg(priv, STM32_SPI_IER_OFFSET, SPI_IER_EOTIE, 0); /* Set result and release wait semaphore */ -#ifdef CONFIG_STM32U5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA priv->txresult = 0x80; nxsem_post(&priv->txsem); #endif @@ -857,7 +857,7 @@ static int spi_interrupt(int irq, void *context, void *arg) * ****************************************************************************/ -#ifdef CONFIG_STM32U5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static int spi_dmarxwait(struct stm32_spidev_s *priv) { int ret; @@ -897,7 +897,7 @@ static int spi_dmarxwait(struct stm32_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32U5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static int spi_dmatxwait(struct stm32_spidev_s *priv) { int ret; @@ -946,7 +946,7 @@ static int spi_dmatxwait(struct stm32_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32U5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static inline void spi_dmarxwakeup(struct stm32_spidev_s *priv) { nxsem_post(&priv->rxsem); @@ -961,7 +961,7 @@ static inline void spi_dmarxwakeup(struct stm32_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32U5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) { struct stm32_spidev_s *priv = (struct stm32_spidev_s *)arg; @@ -981,7 +981,7 @@ static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) * ****************************************************************************/ -#ifdef CONFIG_STM32U5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmarxsetup(struct stm32_spidev_s *priv, void *rxbuffer, void *rxdummy, size_t nwords, stm32_dmacfg_t *dmacfg) @@ -1043,7 +1043,7 @@ static void spi_dmarxsetup(struct stm32_spidev_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32U5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmatxsetup(struct stm32_spidev_s *priv, const void *txbuffer, const void *txdummy, size_t nwords, stm32_dmacfg_t *dmacfg) @@ -1103,7 +1103,7 @@ static void spi_dmatxsetup(struct stm32_spidev_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32U5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmarxstart(struct stm32_spidev_s *priv) { /* Can't receive in tx only mode */ @@ -1127,7 +1127,7 @@ static void spi_dmarxstart(struct stm32_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32U5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmatxstart(struct stm32_spidev_s *priv) { /* Can't transmit in rx only mode */ @@ -1662,9 +1662,9 @@ static uint32_t spi_send(struct spi_dev_s *dev, uint32_t wd) * ****************************************************************************/ -#if !defined(CONFIG_STM32U5_SPI_DMA) || defined(CONFIG_STM32U5_DMACAPABLE) || \ - defined(CONFIG_STM32U5_SPI_DMATHRESHOLD) -#if !defined(CONFIG_STM32U5_SPI_DMA) +#if !defined(CONFIG_STM32_SPI_DMA) || defined(CONFIG_STM32_DMACAPABLE) || \ + defined(CONFIG_STM32_SPI_DMATHRESHOLD) +#if !defined(CONFIG_STM32_SPI_DMA) static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, void *rxbuffer, size_t nwords) #else @@ -1753,8 +1753,8 @@ static void spi_exchange_nodma(struct spi_dev_s *dev, } } -#endif /* !CONFIG_STM32U5_SPI_DMA || CONFIG_STM32U5_DMACAPABLE || - * CONFIG_STM32U5_SPI_DMATHRESHOLD +#endif /* !CONFIG_STM32_SPI_DMA || CONFIG_STM32_DMACAPABLE || + * CONFIG_STM32_SPI_DMATHRESHOLD */ /**************************************************************************** @@ -1778,7 +1778,7 @@ static void spi_exchange_nodma(struct spi_dev_s *dev, * ****************************************************************************/ -#ifdef CONFIG_STM32U5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, void *rxbuffer, size_t nwords) { @@ -1796,12 +1796,12 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, size_t nbytes = (priv->nbits > 8) ? nwords << 1 : nwords; -#ifdef CONFIG_STM32U5_SPI_DMATHRESHOLD +#ifdef CONFIG_STM32_SPI_DMATHRESHOLD /* If this is a small SPI transfer, then let spi_exchange_nodma() do the * work. */ - if (nbytes <= CONFIG_STM32U5_SPI_DMATHRESHOLD) + if (nbytes <= CONFIG_STM32_SPI_DMATHRESHOLD) { spi_exchange_nodma(dev, txbuffer, rxbuffer, nwords); return; @@ -1865,7 +1865,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, spi_dmatxsetup(priv, txbuffer, &txdummy, nwords, &txdmacfg); spi_dmarxsetup(priv, rxbuffer, (uint16_t *)rxdummy, nwords, &rxdmacfg); -#ifdef CONFIG_STM32U5_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE /* Test for DMA capability of only callers buffers, internal buffers are * guaranteed capable. @@ -1995,7 +1995,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, priv->trigarmed = false; #endif } -#endif /* CONFIG_STM32U5_SPI_DMA */ +#endif /* CONFIG_STM32_SPI_DMA */ /**************************************************************************** * Name: spi_trigger @@ -2016,7 +2016,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, #ifdef CONFIG_SPI_TRIGGER static int spi_trigger(struct spi_dev_s *dev) { -#ifdef CONFIG_STM32U5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; if (!priv->trigarmed) @@ -2250,7 +2250,7 @@ static void spi_bus_initialize(struct stm32_spidev_s *priv) spi_putreg(priv, STM32_SPI_CRCPOLY_OFFSET, 7); -#ifdef CONFIG_STM32U5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA /* Get DMA channels. NOTE: stm32_dmachannel() will always assign the DMA * channel. If the channel is not available, then stm32_dmachannel() will * block and wait until the channel becomes available. WARNING: If you @@ -2332,7 +2332,7 @@ struct spi_dev_s *stm32_spibus_initialize(int bus) struct stm32_spidev_s *priv = NULL; irqstate_t flags = enter_critical_section(); -#ifdef CONFIG_STM32U5_SPI1 +#ifdef CONFIG_STM32_SPI1 if (bus == 1) { /* Select SPI1 */ @@ -2357,7 +2357,7 @@ struct spi_dev_s *stm32_spibus_initialize(int bus) } else #endif -#ifdef CONFIG_STM32U5_SPI2 +#ifdef CONFIG_STM32_SPI2 if (bus == 2) { /* Select SPI2 */ @@ -2382,7 +2382,7 @@ struct spi_dev_s *stm32_spibus_initialize(int bus) } else #endif -#ifdef CONFIG_STM32U5_SPI3 +#ifdef CONFIG_STM32_SPI3 if (bus == 3) { /* Select SPI3 */ @@ -2415,5 +2415,5 @@ struct spi_dev_s *stm32_spibus_initialize(int bus) return (struct spi_dev_s *)priv; } -#endif /* CONFIG_STM32U5_SPI1 || CONFIG_STM32U5_SPI2 || CONFIG_STM32U5_SPI3 +#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 || CONFIG_STM32_SPI3 */ diff --git a/arch/arm/src/stm32u5/stm32_spi.h b/arch/arm/src/stm32u5/stm32_spi.h index 9734b18924f..485b6a5a9a1 100644 --- a/arch/arm/src/stm32u5/stm32_spi.h +++ b/arch/arm/src/stm32u5/stm32_spi.h @@ -114,21 +114,21 @@ struct spi_slave_ctrlr_s *stm32_spi_slave_initialize(int bus); * ****************************************************************************/ -#ifdef CONFIG_STM32U5_SPI1 +#ifdef CONFIG_STM32_SPI1 void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected); uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid); int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); #endif -#ifdef CONFIG_STM32U5_SPI2 +#ifdef CONFIG_STM32_SPI2 void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected); uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid); int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); #endif -#ifdef CONFIG_STM32U5_SPI3 +#ifdef CONFIG_STM32_SPI3 void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, bool selected); uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid); @@ -156,17 +156,17 @@ int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); ****************************************************************************/ #ifdef CONFIG_SPI_CALLBACK -#ifdef CONFIG_STM32U5_SPI1 +#ifdef CONFIG_STM32_SPI1 int stm32_spi1register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif -#ifdef CONFIG_STM32U5_SPI2 +#ifdef CONFIG_STM32_SPI2 int stm32_spi2register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif -#ifdef CONFIG_STM32U5_SPI3 +#ifdef CONFIG_STM32_SPI3 int stm32_spi3register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif diff --git a/arch/arm/src/stm32u5/stm32_start.c b/arch/arm/src/stm32u5/stm32_start.c index ee12901462f..87609e5c881 100644 --- a/arch/arm/src/stm32u5/stm32_start.c +++ b/arch/arm/src/stm32u5/stm32_start.c @@ -131,7 +131,7 @@ void __start(void) ("sub r10, sp, %0" : : "r" (CONFIG_IDLETHREAD_STACKSIZE - 64) :); #endif -#ifdef CONFIG_STM32U5_SRAM2_INIT +#ifdef CONFIG_STM32_SRAM2_INIT /* The SRAM2 region is parity checked, but upon power up, it will be in * a random state and probably invalid with respect to parity, potentially * generating faults if accessed. If elected, we will write zeros to the diff --git a/arch/arm/src/stm32u5/stm32_tim.c b/arch/arm/src/stm32u5/stm32_tim.c index 7dbdba50ce4..bc4c4e1466b 100644 --- a/arch/arm/src/stm32u5/stm32_tim.c +++ b/arch/arm/src/stm32u5/stm32_tim.c @@ -73,118 +73,118 @@ * In any of these cases, the timer will not be used by this timer module. */ -#if defined(CONFIG_STM32U5_TIM1_PWM) || defined (CONFIG_STM32U5_TIM1_ADC) || \ - defined(CONFIG_STM32U5_TIM1_DAC) || defined(CONFIG_STM32U5_TIM1_QE) -# undef CONFIG_STM32U5_TIM1 +#if defined(CONFIG_STM32_TIM1_PWM) || defined (CONFIG_STM32_TIM1_ADC) || \ + defined(CONFIG_STM32_TIM1_DAC) || defined(CONFIG_STM32_TIM1_QE) +# undef CONFIG_STM32_TIM1 #endif -#if defined(CONFIG_STM32U5_TIM2_PWM) || defined (CONFIG_STM32U5_TIM2_ADC) || \ - defined(CONFIG_STM32U5_TIM2_DAC) || defined(CONFIG_STM32U5_TIM2_QE) -# undef CONFIG_STM32U5_TIM2 +#if defined(CONFIG_STM32_TIM2_PWM) || defined (CONFIG_STM32_TIM2_ADC) || \ + defined(CONFIG_STM32_TIM2_DAC) || defined(CONFIG_STM32_TIM2_QE) +# undef CONFIG_STM32_TIM2 #endif -#if defined(CONFIG_STM32U5_TIM3_PWM) || defined (CONFIG_STM32U5_TIM3_ADC) || \ - defined(CONFIG_STM32U5_TIM3_DAC) || defined(CONFIG_STM32U5_TIM3_QE) -# undef CONFIG_STM32U5_TIM3 +#if defined(CONFIG_STM32_TIM3_PWM) || defined (CONFIG_STM32_TIM3_ADC) || \ + defined(CONFIG_STM32_TIM3_DAC) || defined(CONFIG_STM32_TIM3_QE) +# undef CONFIG_STM32_TIM3 #endif -#if defined(CONFIG_STM32U5_TIM4_PWM) || defined (CONFIG_STM32U5_TIM4_ADC) || \ - defined(CONFIG_STM32U5_TIM4_DAC) || defined(CONFIG_STM32U5_TIM4_QE) -# undef CONFIG_STM32U5_TIM4 +#if defined(CONFIG_STM32_TIM4_PWM) || defined (CONFIG_STM32_TIM4_ADC) || \ + defined(CONFIG_STM32_TIM4_DAC) || defined(CONFIG_STM32_TIM4_QE) +# undef CONFIG_STM32_TIM4 #endif -#if defined(CONFIG_STM32U5_TIM5_PWM) || defined (CONFIG_STM32U5_TIM5_ADC) || \ - defined(CONFIG_STM32U5_TIM5_DAC) || defined(CONFIG_STM32U5_TIM5_QE) -# undef CONFIG_STM32U5_TIM5 +#if defined(CONFIG_STM32_TIM5_PWM) || defined (CONFIG_STM32_TIM5_ADC) || \ + defined(CONFIG_STM32_TIM5_DAC) || defined(CONFIG_STM32_TIM5_QE) +# undef CONFIG_STM32_TIM5 #endif -#if defined(CONFIG_STM32U5_TIM6_PWM) || defined (CONFIG_STM32U5_TIM6_ADC) || \ - defined(CONFIG_STM32U5_TIM6_DAC) || defined(CONFIG_STM32U5_TIM6_QE) -# undef CONFIG_STM32U5_TIM6 +#if defined(CONFIG_STM32U5_TIM6_PWM) || defined (CONFIG_STM32_TIM6_ADC) || \ + defined(CONFIG_STM32_TIM6_DAC) || defined(CONFIG_STM32U5_TIM6_QE) +# undef CONFIG_STM32_TIM6 #endif #if defined(CONFIG_STM32U5_TIM7_PWM) || defined (CONFIG_STM32U5_TIM7_ADC) || \ - defined(CONFIG_STM32U5_TIM7_DAC) || defined(CONFIG_STM32U5_TIM7_QE) -# undef CONFIG_STM32U5_TIM7 + defined(CONFIG_STM32_TIM7_DAC) || defined(CONFIG_STM32U5_TIM7_QE) +# undef CONFIG_STM32_TIM7 #endif -#if defined(CONFIG_STM32U5_TIM8_PWM) || defined (CONFIG_STM32U5_TIM8_ADC) || \ - defined(CONFIG_STM32U5_TIM8_DAC) || defined(CONFIG_STM32U5_TIM8_QE) -# undef CONFIG_STM32U5_TIM8 +#if defined(CONFIG_STM32_TIM8_PWM) || defined (CONFIG_STM32_TIM8_ADC) || \ + defined(CONFIG_STM32_TIM8_DAC) || defined(CONFIG_STM32_TIM8_QE) +# undef CONFIG_STM32_TIM8 #endif -#if defined(CONFIG_STM32U5_TIM15_PWM) || defined (CONFIG_STM32U5_TIM15_ADC) || \ +#if defined(CONFIG_STM32_TIM15_PWM) || defined (CONFIG_STM32_TIM15_ADC) || \ defined(CONFIG_STM32U5_TIM15_DAC) || defined(CONFIG_STM32U5_TIM15_QE) -# undef CONFIG_STM32U5_TIM15 +# undef CONFIG_STM32_TIM15 #endif -#if defined(CONFIG_STM32U5_TIM16_PWM) || defined (CONFIG_STM32U5_TIM16_ADC) || \ +#if defined(CONFIG_STM32_TIM16_PWM) || defined (CONFIG_STM32U5_TIM16_ADC) || \ defined(CONFIG_STM32U5_TIM16_DAC) || defined(CONFIG_STM32U5_TIM16_QE) -# undef CONFIG_STM32U5_TIM16 +# undef CONFIG_STM32_TIM16 #endif -#if defined(CONFIG_STM32U5_TIM17_PWM) || defined (CONFIG_STM32U5_TIM17_ADC) || \ +#if defined(CONFIG_STM32_TIM17_PWM) || defined (CONFIG_STM32U5_TIM17_ADC) || \ defined(CONFIG_STM32U5_TIM17_DAC) || defined(CONFIG_STM32U5_TIM17_QE) -# undef CONFIG_STM32U5_TIM17 +# undef CONFIG_STM32_TIM17 #endif -#if defined(CONFIG_STM32U5_TIM1) +#if defined(CONFIG_STM32_TIM1) # if defined(GPIO_TIM1_CH1OUT) ||defined(GPIO_TIM1_CH2OUT)||\ defined(GPIO_TIM1_CH3OUT) ||defined(GPIO_TIM1_CH4OUT) # define HAVE_TIM1_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32U5_TIM2) +#if defined(CONFIG_STM32_TIM2) # if defined(GPIO_TIM2_CH1OUT) ||defined(GPIO_TIM2_CH2OUT)||\ defined(GPIO_TIM2_CH3OUT) ||defined(GPIO_TIM2_CH4OUT) # define HAVE_TIM2_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32U5_TIM3) +#if defined(CONFIG_STM32_TIM3) # if defined(GPIO_TIM3_CH1OUT) ||defined(GPIO_TIM3_CH2OUT)||\ defined(GPIO_TIM3_CH3OUT) ||defined(GPIO_TIM3_CH4OUT) # define HAVE_TIM3_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32U5_TIM4) +#if defined(CONFIG_STM32_TIM4) # if defined(GPIO_TIM4_CH1OUT) ||defined(GPIO_TIM4_CH2OUT)||\ defined(GPIO_TIM4_CH3OUT) ||defined(GPIO_TIM4_CH4OUT) # define HAVE_TIM4_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32U5_TIM5) +#if defined(CONFIG_STM32_TIM5) # if defined(GPIO_TIM5_CH1OUT) ||defined(GPIO_TIM5_CH2OUT)||\ defined(GPIO_TIM5_CH3OUT) ||defined(GPIO_TIM5_CH4OUT) # define HAVE_TIM5_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32U5_TIM8) +#if defined(CONFIG_STM32_TIM8) # if defined(GPIO_TIM8_CH1OUT) ||defined(GPIO_TIM8_CH2OUT)||\ defined(GPIO_TIM8_CH3OUT) ||defined(GPIO_TIM8_CH4OUT) # define HAVE_TIM8_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32U5_TIM15) +#if defined(CONFIG_STM32_TIM15) # if defined(GPIO_TIM15_CH1OUT) ||defined(GPIO_TIM15_CH2OUT)||\ defined(GPIO_TIM15_CH3OUT) ||defined(GPIO_TIM15_CH4OUT) # define HAVE_TIM15_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32U5_TIM16) +#if defined(CONFIG_STM32_TIM16) # if defined(GPIO_TIM16_CH1OUT) ||defined(GPIO_TIM16_CH2OUT)||\ defined(GPIO_TIM16_CH3OUT) ||defined(GPIO_TIM16_CH4OUT) # define HAVE_TIM16_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32U5_TIM17) +#if defined(CONFIG_STM32_TIM17) # if defined(GPIO_TIM17_CH1OUT) ||defined(GPIO_TIM17_CH2OUT)||\ defined(GPIO_TIM17_CH3OUT) ||defined(GPIO_TIM17_CH4OUT) # define HAVE_TIM17_GPIOCONFIG 1 @@ -195,12 +195,12 @@ * intended for some other purpose. */ -#if defined(CONFIG_STM32U5_TIM1) || defined(CONFIG_STM32U5_TIM2) || \ - defined(CONFIG_STM32U5_TIM3) || defined(CONFIG_STM32U5_TIM4) || \ - defined(CONFIG_STM32U5_TIM5) || defined(CONFIG_STM32U5_TIM6) || \ - defined(CONFIG_STM32U5_TIM7) || defined(CONFIG_STM32U5_TIM8) || \ - defined(CONFIG_STM32U5_TIM15) || defined(CONFIG_STM32U5_TIM16) || \ - defined(CONFIG_STM32U5_TIM17) +#if defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM2) || \ + defined(CONFIG_STM32_TIM3) || defined(CONFIG_STM32_TIM4) || \ + defined(CONFIG_STM32_TIM5) || defined(CONFIG_STM32_TIM6) || \ + defined(CONFIG_STM32_TIM7) || defined(CONFIG_STM32_TIM8) || \ + defined(CONFIG_STM32_TIM15) || defined(CONFIG_STM32_TIM16) || \ + defined(CONFIG_STM32_TIM17) /**************************************************************************** * Private Types @@ -301,7 +301,7 @@ static const struct stm32_tim_ops_s stm32_tim_ops = .checkint = stm32_tim_checkint, }; -#ifdef CONFIG_STM32U5_TIM1 +#ifdef CONFIG_STM32_TIM1 struct stm32_tim_priv_s stm32_tim1_priv = { .ops = &stm32_tim_ops, @@ -309,7 +309,7 @@ struct stm32_tim_priv_s stm32_tim1_priv = .base = STM32_TIM1_BASE, }; #endif -#ifdef CONFIG_STM32U5_TIM2 +#ifdef CONFIG_STM32_TIM2 struct stm32_tim_priv_s stm32_tim2_priv = { .ops = &stm32_tim_ops, @@ -318,7 +318,7 @@ struct stm32_tim_priv_s stm32_tim2_priv = }; #endif -#ifdef CONFIG_STM32U5_TIM3 +#ifdef CONFIG_STM32_TIM3 struct stm32_tim_priv_s stm32_tim3_priv = { .ops = &stm32_tim_ops, @@ -327,7 +327,7 @@ struct stm32_tim_priv_s stm32_tim3_priv = }; #endif -#ifdef CONFIG_STM32U5_TIM4 +#ifdef CONFIG_STM32_TIM4 struct stm32_tim_priv_s stm32_tim4_priv = { .ops = &stm32_tim_ops, @@ -336,7 +336,7 @@ struct stm32_tim_priv_s stm32_tim4_priv = }; #endif -#ifdef CONFIG_STM32U5_TIM5 +#ifdef CONFIG_STM32_TIM5 struct stm32_tim_priv_s stm32_tim5_priv = { .ops = &stm32_tim_ops, @@ -345,7 +345,7 @@ struct stm32_tim_priv_s stm32_tim5_priv = }; #endif -#ifdef CONFIG_STM32U5_TIM6 +#ifdef CONFIG_STM32_TIM6 struct stm32_tim_priv_s stm32_tim6_priv = { .ops = &stm32_tim_ops, @@ -354,7 +354,7 @@ struct stm32_tim_priv_s stm32_tim6_priv = }; #endif -#ifdef CONFIG_STM32U5_TIM7 +#ifdef CONFIG_STM32_TIM7 struct stm32_tim_priv_s stm32_tim7_priv = { .ops = &stm32_tim_ops, @@ -363,7 +363,7 @@ struct stm32_tim_priv_s stm32_tim7_priv = }; #endif -#ifdef CONFIG_STM32U5_TIM8 +#ifdef CONFIG_STM32_TIM8 struct stm32_tim_priv_s stm32_tim8_priv = { .ops = &stm32_tim_ops, @@ -372,7 +372,7 @@ struct stm32_tim_priv_s stm32_tim8_priv = }; #endif -#ifdef CONFIG_STM32U5_TIM15 +#ifdef CONFIG_STM32_TIM15 struct stm32_tim_priv_s stm32_tim15_priv = { .ops = &stm32_tim_ops, @@ -381,7 +381,7 @@ struct stm32_tim_priv_s stm32_tim15_priv = }; #endif -#ifdef CONFIG_STM32U5_TIM16 +#ifdef CONFIG_STM32_TIM16 struct stm32_tim_priv_s stm32_tim16_priv = { .ops = &stm32_tim_ops, @@ -390,7 +390,7 @@ struct stm32_tim_priv_s stm32_tim16_priv = }; #endif -#ifdef CONFIG_STM32U5_TIM17 +#ifdef CONFIG_STM32_TIM17 struct stm32_tim_priv_s stm32_tim17_priv = { .ops = &stm32_tim_ops, @@ -654,66 +654,66 @@ static int stm32_tim_setclock(struct stm32_tim_dev_s *dev, switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32U5_TIM1 +#ifdef CONFIG_STM32_TIM1 case STM32_TIM1_BASE: freqin = BOARD_TIM1_FREQUENCY; break; #endif -#ifdef CONFIG_STM32U5_TIM2 +#ifdef CONFIG_STM32_TIM2 case STM32_TIM2_BASE: freqin = BOARD_TIM2_FREQUENCY; break; #endif -#ifdef CONFIG_STM32U5_TIM3 +#ifdef CONFIG_STM32_TIM3 case STM32_TIM3_BASE: freqin = BOARD_TIM3_FREQUENCY; break; #endif -#ifdef CONFIG_STM32U5_TIM4 +#ifdef CONFIG_STM32_TIM4 case STM32_TIM4_BASE: freqin = BOARD_TIM4_FREQUENCY; break; #endif -#ifdef CONFIG_STM32U5_TIM5 +#ifdef CONFIG_STM32_TIM5 case STM32_TIM5_BASE: freqin = BOARD_TIM5_FREQUENCY; break; #endif -#ifdef CONFIG_STM32U5_TIM6 +#ifdef CONFIG_STM32_TIM6 case STM32_TIM6_BASE: freqin = BOARD_TIM6_FREQUENCY; break; #endif -#ifdef CONFIG_STM32U5_TIM7 +#ifdef CONFIG_STM32_TIM7 case STM32_TIM7_BASE: freqin = BOARD_TIM7_FREQUENCY; break; #endif -#ifdef CONFIG_STM32U5_TIM8 +#ifdef CONFIG_STM32_TIM8 case STM32_TIM8_BASE: freqin = BOARD_TIM8_FREQUENCY; break; #endif -#ifdef CONFIG_STM32U5_TIM15 +#ifdef CONFIG_STM32_TIM15 case STM32_TIM15_BASE: freqin = BOARD_TIM15_FREQUENCY; break; #endif -#ifdef CONFIG_STM32U5_TIM16 +#ifdef CONFIG_STM32_TIM16 case STM32_TIM16_BASE: freqin = BOARD_TIM16_FREQUENCY; break; #endif -#ifdef CONFIG_STM32U5_TIM17 +#ifdef CONFIG_STM32_TIM17 case STM32_TIM17_BASE: freqin = BOARD_TIM17_FREQUENCY; break; @@ -769,64 +769,64 @@ static uint32_t stm32_tim_getclock(struct stm32_tim_dev_s *dev) switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32U5_TIM1 +#ifdef CONFIG_STM32_TIM1 case STM32_TIM1_BASE: freqin = BOARD_TIM1_FREQUENCY; break; #endif -#ifdef CONFIG_STM32U5_TIM2 +#ifdef CONFIG_STM32_TIM2 case STM32_TIM2_BASE: freqin = BOARD_TIM2_FREQUENCY; break; #endif -#ifdef CONFIG_STM32U5_TIM3 +#ifdef CONFIG_STM32_TIM3 case STM32_TIM3_BASE: freqin = BOARD_TIM3_FREQUENCY; break; #endif -#ifdef CONFIG_STM32U5_TIM4 +#ifdef CONFIG_STM32_TIM4 case STM32_TIM4_BASE: freqin = BOARD_TIM4_FREQUENCY; break; #endif -#ifdef CONFIG_STM32U5_TIM5 +#ifdef CONFIG_STM32_TIM5 case STM32_TIM5_BASE: freqin = BOARD_TIM5_FREQUENCY; break; #endif -#ifdef CONFIG_STM32U5_TIM6 +#ifdef CONFIG_STM32_TIM6 case STM32_TIM6_BASE: freqin = BOARD_TIM6_FREQUENCY; break; #endif -#ifdef CONFIG_STM32U5_TIM7 +#ifdef CONFIG_STM32_TIM7 case STM32_TIM7_BASE: freqin = BOARD_TIM7_FREQUENCY; break; #endif -#ifdef CONFIG_STM32U5_TIM8 +#ifdef CONFIG_STM32_TIM8 case STM32_TIM8_BASE: freqin = BOARD_TIM8_FREQUENCY; break; #endif -#ifdef CONFIG_STM32U5_TIM15 +#ifdef CONFIG_STM32_TIM15 case STM32_TIM15_BASE: freqin = BOARD_TIM15_FREQUENCY; break; #endif -#ifdef CONFIG_STM32U5_TIM16 +#ifdef CONFIG_STM32_TIM16 case STM32_TIM16_BASE: freqin = BOARD_TIM16_FREQUENCY; break; #endif -#ifdef CONFIG_STM32U5_TIM17 +#ifdef CONFIG_STM32_TIM17 case STM32_TIM17_BASE: freqin = BOARD_TIM17_FREQUENCY; break; @@ -875,13 +875,13 @@ static uint32_t stm32_tim_getcounter(struct stm32_tim_dev_s *dev) * reset it it result when not TIM2 or TIM5. */ -#if defined(CONFIG_STM32U5_TIM2) || defined(CONFIG_STM32U5_TIM5) +#if defined(CONFIG_STM32_TIM2) || defined(CONFIG_STM32_TIM5) switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32U5_TIM2 +#ifdef CONFIG_STM32_TIM2 case STM32_TIM2_BASE: #endif -#ifdef CONFIG_STM32U5_TIM5 +#ifdef CONFIG_STM32_TIM5 case STM32_TIM5_BASE: #endif return counter; @@ -987,7 +987,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32U5_TIM1 +#ifdef CONFIG_STM32_TIM1 case STM32_TIM1_BASE: switch (channel) { @@ -1020,7 +1020,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32U5_TIM2 +#ifdef CONFIG_STM32_TIM2 case STM32_TIM2_BASE: switch (channel) { @@ -1053,7 +1053,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32U5_TIM3 +#ifdef CONFIG_STM32_TIM3 case STM32_TIM3_BASE: switch (channel) { @@ -1086,7 +1086,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32U5_TIM4 +#ifdef CONFIG_STM32_TIM4 case STM32_TIM4_BASE: switch (channel) { @@ -1118,7 +1118,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32U5_TIM5 +#ifdef CONFIG_STM32_TIM5 case STM32_TIM5_BASE: switch (channel) { @@ -1151,7 +1151,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32U5_TIM8 +#ifdef CONFIG_STM32_TIM8 case STM32_TIM8_BASE: switch (channel) { @@ -1184,7 +1184,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32U5_TIM15 +#ifdef CONFIG_STM32_TIM15 case STM32_TIM15_BASE: switch (channel) { @@ -1217,7 +1217,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32U5_TIM16 +#ifdef CONFIG_STM32_TIM16 case STM32_TIM16_BASE: switch (channel) { @@ -1250,7 +1250,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32U5_TIM17 +#ifdef CONFIG_STM32_TIM17 case STM32_TIM17_BASE: switch (channel) { @@ -1366,65 +1366,65 @@ static int stm32_tim_setisr(struct stm32_tim_dev_s *dev, switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32U5_TIM1 +#ifdef CONFIG_STM32_TIM1 case STM32_TIM1_BASE: vectorno = STM32_IRQ_TIM1UP; break; #endif -#ifdef CONFIG_STM32U5_TIM2 +#ifdef CONFIG_STM32_TIM2 case STM32_TIM2_BASE: vectorno = STM32_IRQ_TIM2; break; #endif -#ifdef CONFIG_STM32U5_TIM3 +#ifdef CONFIG_STM32_TIM3 case STM32_TIM3_BASE: vectorno = STM32_IRQ_TIM3; break; #endif -#ifdef CONFIG_STM32U5_TIM4 +#ifdef CONFIG_STM32_TIM4 case STM32_TIM4_BASE: vectorno = STM32_IRQ_TIM4; break; #endif -#ifdef CONFIG_STM32U5_TIM5 +#ifdef CONFIG_STM32_TIM5 case STM32_TIM5_BASE: vectorno = STM32_IRQ_TIM5; break; #endif -#ifdef CONFIG_STM32U5_TIM6 +#ifdef CONFIG_STM32_TIM6 case STM32_TIM6_BASE: vectorno = STM32_IRQ_TIM6; break; #endif -#ifdef CONFIG_STM32U5_TIM7 +#ifdef CONFIG_STM32_TIM7 case STM32_TIM7_BASE: vectorno = STM32_IRQ_TIM7; break; #endif -#ifdef CONFIG_STM32U5_TIM8 +#ifdef CONFIG_STM32_TIM8 case STM32_TIM8_BASE: vectorno = STM32_IRQ_TIM8UP; break; #endif -#ifdef CONFIG_STM32U5_TIM15 +#ifdef CONFIG_STM32_TIM15 case STM32_TIM15_BASE: vectorno = STM32_IRQ_TIM15; break; #endif -#ifdef CONFIG_STM32U5_TIM16 +#ifdef CONFIG_STM32_TIM16 case STM32_TIM16_BASE: vectorno = STM32_IRQ_TIM16; break; #endif -#ifdef CONFIG_STM32U5_TIM17 +#ifdef CONFIG_STM32_TIM17 case STM32_TIM17_BASE: vectorno = STM32_IRQ_TIM17; break; @@ -1509,76 +1509,76 @@ struct stm32_tim_dev_s *stm32_tim_init(int timer) switch (timer) { -#ifdef CONFIG_STM32U5_TIM1 +#ifdef CONFIG_STM32_TIM1 case 1: dev = (struct stm32_tim_dev_s *)&stm32_tim1_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM1EN); break; #endif -#ifdef CONFIG_STM32U5_TIM2 +#ifdef CONFIG_STM32_TIM2 case 2: dev = (struct stm32_tim_dev_s *)&stm32_tim2_priv; modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM2EN); break; #endif -#ifdef CONFIG_STM32U5_TIM3 +#ifdef CONFIG_STM32_TIM3 case 3: dev = (struct stm32_tim_dev_s *)&stm32_tim3_priv; modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM3EN); break; #endif -#ifdef CONFIG_STM32U5_TIM4 +#ifdef CONFIG_STM32_TIM4 case 4: dev = (struct stm32_tim_dev_s *)&stm32_tim4_priv; modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM4EN); break; #endif -#ifdef CONFIG_STM32U5_TIM5 +#ifdef CONFIG_STM32_TIM5 case 5: dev = (struct stm32_tim_dev_s *)&stm32_tim5_priv; modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM5EN); break; #endif -#ifdef CONFIG_STM32U5_TIM6 +#ifdef CONFIG_STM32_TIM6 case 6: dev = (struct stm32_tim_dev_s *)&stm32_tim6_priv; modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM6EN); break; #endif -#ifdef CONFIG_STM32U5_TIM7 +#ifdef CONFIG_STM32_TIM7 case 7: dev = (struct stm32_tim_dev_s *)&stm32_tim7_priv; modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM7EN); break; #endif -#ifdef CONFIG_STM32U5_TIM8 +#ifdef CONFIG_STM32_TIM8 case 8: dev = (struct stm32_tim_dev_s *)&stm32_tim8_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM8EN); break; #endif -#ifdef CONFIG_STM32U5_TIM15 +#ifdef CONFIG_STM32_TIM15 case 15: dev = (struct stm32_tim_dev_s *)&stm32_tim15_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM15EN); break; #endif -#ifdef CONFIG_STM32U5_TIM16 +#ifdef CONFIG_STM32_TIM16 case 16: dev = (struct stm32_tim_dev_s *)&stm32_tim16_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM16EN); break; #endif -#ifdef CONFIG_STM32U5_TIM17 +#ifdef CONFIG_STM32_TIM17 case 17: dev = (struct stm32_tim_dev_s *)&stm32_tim17_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM17EN); @@ -1616,66 +1616,66 @@ int stm32_tim_deinit(struct stm32_tim_dev_s *dev) switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32U5_TIM1 +#ifdef CONFIG_STM32_TIM1 case STM32_TIM1_BASE: modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM1EN, 0); break; #endif -#ifdef CONFIG_STM32U5_TIM2 +#ifdef CONFIG_STM32_TIM2 case STM32_TIM2_BASE: modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM2EN, 0); break; #endif -#ifdef CONFIG_STM32U5_TIM3 +#ifdef CONFIG_STM32_TIM3 case STM32_TIM3_BASE: modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM3EN, 0); break; #endif -#ifdef CONFIG_STM32U5_TIM4 +#ifdef CONFIG_STM32_TIM4 case STM32_TIM4_BASE: modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM4EN, 0); break; #endif -#ifdef CONFIG_STM32U5_TIM5 +#ifdef CONFIG_STM32_TIM5 case STM32_TIM5_BASE: modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM5EN, 0); break; #endif -#ifdef CONFIG_STM32U5_TIM6 +#ifdef CONFIG_STM32_TIM6 case STM32_TIM6_BASE: modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM6EN, 0); break; #endif -#ifdef CONFIG_STM32U5_TIM7 +#ifdef CONFIG_STM32_TIM7 case STM32_TIM7_BASE: modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM7EN, 0); break; #endif -#ifdef CONFIG_STM32U5_TIM8 +#ifdef CONFIG_STM32_TIM8 case STM32_TIM8_BASE: modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM8EN, 0); break; #endif -#ifdef CONFIG_STM32U5_TIM15 +#ifdef CONFIG_STM32_TIM15 case STM32_TIM15_BASE: modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM15EN, 0); break; #endif -#ifdef CONFIG_STM32U5_TIM16 +#ifdef CONFIG_STM32_TIM16 case STM32_TIM16_BASE: modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM16EN, 0); break; #endif -#ifdef CONFIG_STM32U5_TIM17 +#ifdef CONFIG_STM32_TIM17 case STM32_TIM17_BASE: modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM17EN, 0); break; @@ -1692,4 +1692,4 @@ int stm32_tim_deinit(struct stm32_tim_dev_s *dev) return OK; } -#endif /* defined(CONFIG_STM32U5_TIM1 || ... || TIM17) */ +#endif /* defined(CONFIG_STM32_TIM1 || ... || TIM17) */ diff --git a/arch/arm/src/stm32u5/stm32_tim_lowerhalf.c b/arch/arm/src/stm32u5/stm32_tim_lowerhalf.c index 7752a4fda1b..a564a8af525 100644 --- a/arch/arm/src/stm32u5/stm32_tim_lowerhalf.c +++ b/arch/arm/src/stm32u5/stm32_tim_lowerhalf.c @@ -41,12 +41,12 @@ #include "stm32_tim.h" #if defined(CONFIG_TIMER) && \ - (defined(CONFIG_STM32U5_TIM1) || defined(CONFIG_STM32U5_TIM2) || \ - defined(CONFIG_STM32U5_TIM3) || defined(CONFIG_STM32U5_TIM4) || \ - defined(CONFIG_STM32U5_TIM5) || defined(CONFIG_STM32U5_TIM6) || \ - defined(CONFIG_STM32U5_TIM7) || defined(CONFIG_STM32U5_TIM8) || \ - defined(CONFIG_STM32U5_TIM15) || defined(CONFIG_STM32U5_TIM16) || \ - defined(CONFIG_STM32U5_TIM17)) + (defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM2) || \ + defined(CONFIG_STM32_TIM3) || defined(CONFIG_STM32_TIM4) || \ + defined(CONFIG_STM32_TIM5) || defined(CONFIG_STM32_TIM6) || \ + defined(CONFIG_STM32_TIM7) || defined(CONFIG_STM32_TIM8) || \ + defined(CONFIG_STM32_TIM15) || defined(CONFIG_STM32_TIM16) || \ + defined(CONFIG_STM32_TIM17)) /**************************************************************************** * Pre-processor Definitions @@ -118,7 +118,7 @@ static const struct timer_ops_s g_timer_ops = .ioctl = NULL, }; -#ifdef CONFIG_STM32U5_TIM1 +#ifdef CONFIG_STM32_TIM1 static struct stm32_lowerhalf_s g_tim1_lowerhalf = { .ops = &g_timer_ops, @@ -126,7 +126,7 @@ static struct stm32_lowerhalf_s g_tim1_lowerhalf = }; #endif -#ifdef CONFIG_STM32U5_TIM2 +#ifdef CONFIG_STM32_TIM2 static struct stm32_lowerhalf_s g_tim2_lowerhalf = { .ops = &g_timer_ops, @@ -134,7 +134,7 @@ static struct stm32_lowerhalf_s g_tim2_lowerhalf = }; #endif -#ifdef CONFIG_STM32U5_TIM3 +#ifdef CONFIG_STM32_TIM3 static struct stm32_lowerhalf_s g_tim3_lowerhalf = { .ops = &g_timer_ops, @@ -142,7 +142,7 @@ static struct stm32_lowerhalf_s g_tim3_lowerhalf = }; #endif -#ifdef CONFIG_STM32U5_TIM4 +#ifdef CONFIG_STM32_TIM4 static struct stm32_lowerhalf_s g_tim4_lowerhalf = { .ops = &g_timer_ops, @@ -150,7 +150,7 @@ static struct stm32_lowerhalf_s g_tim4_lowerhalf = }; #endif -#ifdef CONFIG_STM32U5_TIM5 +#ifdef CONFIG_STM32_TIM5 static struct stm32_lowerhalf_s g_tim5_lowerhalf = { .ops = &g_timer_ops, @@ -158,7 +158,7 @@ static struct stm32_lowerhalf_s g_tim5_lowerhalf = }; #endif -#ifdef CONFIG_STM32U5_TIM6 +#ifdef CONFIG_STM32_TIM6 static struct stm32_lowerhalf_s g_tim6_lowerhalf = { .ops = &g_timer_ops, @@ -166,7 +166,7 @@ static struct stm32_lowerhalf_s g_tim6_lowerhalf = }; #endif -#ifdef CONFIG_STM32U5_TIM7 +#ifdef CONFIG_STM32_TIM7 static struct stm32_lowerhalf_s g_tim7_lowerhalf = { .ops = &g_timer_ops, @@ -174,7 +174,7 @@ static struct stm32_lowerhalf_s g_tim7_lowerhalf = }; #endif -#ifdef CONFIG_STM32U5_TIM8 +#ifdef CONFIG_STM32_TIM8 static struct stm32_lowerhalf_s g_tim8_lowerhalf = { .ops = &g_timer_ops, @@ -182,7 +182,7 @@ static struct stm32_lowerhalf_s g_tim8_lowerhalf = }; #endif -#ifdef CONFIG_STM32U5_TIM15 +#ifdef CONFIG_STM32_TIM15 static struct stm32_lowerhalf_s g_tim15_lowerhalf = { .ops = &g_timer_ops, @@ -190,7 +190,7 @@ static struct stm32_lowerhalf_s g_tim15_lowerhalf = }; #endif -#ifdef CONFIG_STM32U5_TIM16 +#ifdef CONFIG_STM32_TIM16 static struct stm32_lowerhalf_s g_tim16_lowerhalf = { .ops = &g_timer_ops, @@ -198,7 +198,7 @@ static struct stm32_lowerhalf_s g_tim16_lowerhalf = }; #endif -#ifdef CONFIG_STM32U5_TIM17 +#ifdef CONFIG_STM32_TIM17 static struct stm32_lowerhalf_s g_tim17_lowerhalf = { .ops = &g_timer_ops, @@ -503,66 +503,66 @@ int stm32_timer_initialize(const char *devpath, int timer) switch (timer) { -#ifdef CONFIG_STM32U5_TIM1 +#ifdef CONFIG_STM32_TIM1 case 1: lower = &g_tim1_lowerhalf; break; #endif -#ifdef CONFIG_STM32U5_TIM2 +#ifdef CONFIG_STM32_TIM2 case 2: lower = &g_tim2_lowerhalf; break; #endif -#ifdef CONFIG_STM32U5_TIM3 +#ifdef CONFIG_STM32_TIM3 case 3: lower = &g_tim3_lowerhalf; break; #endif -#ifdef CONFIG_STM32U5_TIM4 +#ifdef CONFIG_STM32_TIM4 case 4: lower = &g_tim4_lowerhalf; break; #endif -#ifdef CONFIG_STM32U5_TIM5 +#ifdef CONFIG_STM32_TIM5 case 5: lower = &g_tim5_lowerhalf; break; #endif -#ifdef CONFIG_STM32U5_TIM6 +#ifdef CONFIG_STM32_TIM6 case 6: lower = &g_tim6_lowerhalf; break; #endif -#ifdef CONFIG_STM32U5_TIM7 +#ifdef CONFIG_STM32_TIM7 case 7: lower = &g_tim7_lowerhalf; break; #endif -#ifdef CONFIG_STM32U5_TIM8 +#ifdef CONFIG_STM32_TIM8 case 8: lower = &g_tim8_lowerhalf; break; #endif -#ifdef CONFIG_STM32U5_TIM15 +#ifdef CONFIG_STM32_TIM15 case 15: lower = &g_tim15_lowerhalf; break; #endif -#ifdef CONFIG_STM32U5_TIM16 +#ifdef CONFIG_STM32_TIM16 case 16: lower = &g_tim16_lowerhalf; break; #endif -#ifdef CONFIG_STM32U5_TIM17 +#ifdef CONFIG_STM32_TIM17 case 17: lower = &g_tim17_lowerhalf; break; diff --git a/arch/arm/src/stm32u5/stm32_uart.h b/arch/arm/src/stm32u5/stm32_uart.h index 198ef1e36a0..032d3609033 100644 --- a/arch/arm/src/stm32u5/stm32_uart.h +++ b/arch/arm/src/stm32u5/stm32_uart.h @@ -32,7 +32,7 @@ #include "chip.h" -#if defined(CONFIG_STM32U5_STM32U585XX) || defined(CONFIG_STM32U5_STM32U5A5XX) +#if defined(CONFIG_STM32_STM32U585XX) || defined(CONFIG_STM32_STM32U5A5XX) # include "hardware/stm32_uart.h" #else # error "Unsupported STM32U5 chip" @@ -46,63 +46,63 @@ * device. */ -#if !defined(CONFIG_STM32U5_HAVE_UART5) -# undef CONFIG_STM32U5_UART5 +#if !defined(CONFIG_STM32_HAVE_UART5) +# undef CONFIG_STM32_UART5 #endif -#if !defined(CONFIG_STM32U5_HAVE_UART4) -# undef CONFIG_STM32U5_UART4 +#if !defined(CONFIG_STM32_HAVE_UART4) +# undef CONFIG_STM32_UART4 #endif -#if !defined(CONFIG_STM32U5_HAVE_USART3) -# undef CONFIG_STM32U5_USART3 +#if !defined(CONFIG_STM32_HAVE_USART3) +# undef CONFIG_STM32_USART3 #endif -#if !defined(CONFIG_STM32U5_HAVE_USART2) -# undef CONFIG_STM32U5_USART2 +#if !defined(CONFIG_STM32_HAVE_USART2) +# undef CONFIG_STM32_USART2 #endif -#if !defined(CONFIG_STM32U5_HAVE_USART1) -# undef CONFIG_STM32U5_USART1 +#if !defined(CONFIG_STM32_HAVE_USART1) +# undef CONFIG_STM32_USART1 #endif -#if !defined(CONFIG_STM32U5_HAVE_LPUART1) -# undef CONFIG_STM32U5_LPUART1 +#if !defined(CONFIG_STM32_HAVE_LPUART1) +# undef CONFIG_STM32_LPUART1 #endif /* Sanity checks */ -#if !defined(CONFIG_STM32U5_LPUART1) -# undef CONFIG_STM32U5_LPUART1_SERIALDRIVER -# undef CONFIG_STM32U5_LPUART1_1WIREDRIVER +#if !defined(CONFIG_STM32_LPUART1) +# undef CONFIG_STM32_LPUART1_SERIALDRIVER +# undef CONFIG_STM32_LPUART1_1WIREDRIVER #endif -#if !defined(CONFIG_STM32U5_USART1) -# undef CONFIG_STM32U5_USART1_SERIALDRIVER -# undef CONFIG_STM32U5_USART1_1WIREDRIVER +#if !defined(CONFIG_STM32_USART1) +# undef CONFIG_STM32_USART1_SERIALDRIVER +# undef CONFIG_STM32_USART1_1WIREDRIVER #endif -#if !defined(CONFIG_STM32U5_USART2) -# undef CONFIG_STM32U5_USART2_SERIALDRIVER -# undef CONFIG_STM32U5_USART2_1WIREDRIVER +#if !defined(CONFIG_STM32_USART2) +# undef CONFIG_STM32_USART2_SERIALDRIVER +# undef CONFIG_STM32_USART2_1WIREDRIVER #endif -#if !defined(CONFIG_STM32U5_USART3) -# undef CONFIG_STM32U5_USART3_SERIALDRIVER -# undef CONFIG_STM32U5_USART3_1WIREDRIVER +#if !defined(CONFIG_STM32_USART3) +# undef CONFIG_STM32_USART3_SERIALDRIVER +# undef CONFIG_STM32_USART3_1WIREDRIVER #endif -#if !defined(CONFIG_STM32U5_UART4) -# undef CONFIG_STM32U5_UART4_SERIALDRIVER -# undef CONFIG_STM32U5_UART4_1WIREDRIVER +#if !defined(CONFIG_STM32_UART4) +# undef CONFIG_STM32_UART4_SERIALDRIVER +# undef CONFIG_STM32_UART4_1WIREDRIVER #endif -#if !defined(CONFIG_STM32U5_UART5) -# undef CONFIG_STM32U5_UART5_SERIALDRIVER -# undef CONFIG_STM32U5_UART5_1WIREDRIVER +#if !defined(CONFIG_STM32_UART5) +# undef CONFIG_STM32_UART5_SERIALDRIVER +# undef CONFIG_STM32_UART5_1WIREDRIVER #endif /* Is there a USART enabled? */ -#if defined(CONFIG_STM32U5_LPUART1) || defined(CONFIG_STM32U5_USART1) || \ - defined(CONFIG_STM32U5_USART2) || defined(CONFIG_STM32U5_USART3) || \ - defined(CONFIG_STM32U5_UART4) || defined(CONFIG_STM32U5_UART5) +#if defined(CONFIG_STM32_LPUART1) || defined(CONFIG_STM32_USART1) || \ + defined(CONFIG_STM32_USART2) || defined(CONFIG_STM32_USART3) || \ + defined(CONFIG_STM32_UART4) || defined(CONFIG_STM32_UART5) # define HAVE_UART 1 #endif /* Is there a serial console? */ -#if defined(CONFIG_LPUART1_SERIAL_CONSOLE) && defined(CONFIG_STM32U5_LPUART1_SERIALDRIVER) +#if defined(CONFIG_LPUART1_SERIAL_CONSOLE) && defined(CONFIG_STM32_LPUART1_SERIALDRIVER) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE @@ -110,7 +110,7 @@ # undef CONFIG_UART5_SERIAL_CONSOLE # define CONSOLE_UART 1 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_STM32U5_USART1_SERIALDRIVER) +#elif defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART1_SERIALDRIVER) # undef CONFIG_LPUART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE @@ -118,28 +118,28 @@ # undef CONFIG_UART5_SERIAL_CONSOLE # define CONSOLE_UART 2 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(CONFIG_STM32U5_USART2_SERIALDRIVER) +#elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART2_SERIALDRIVER) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE # undef CONFIG_UART4_SERIAL_CONSOLE # undef CONFIG_UART5_SERIAL_CONSOLE # define CONSOLE_UART 3 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_USART3_SERIAL_CONSOLE) && defined(CONFIG_STM32U5_USART3_SERIALDRIVER) +#elif defined(CONFIG_USART3_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART3_SERIALDRIVER) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_UART4_SERIAL_CONSOLE # undef CONFIG_UART5_SERIAL_CONSOLE # define CONSOLE_UART 4 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_UART4_SERIAL_CONSOLE) && defined(CONFIG_STM32U5_UART4_SERIALDRIVER) +#elif defined(CONFIG_UART4_SERIAL_CONSOLE) && defined(CONFIG_STM32_UART4_SERIALDRIVER) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE # undef CONFIG_UART5_SERIAL_CONSOLE # define CONSOLE_UART 5 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_UART5_SERIAL_CONSOLE) && defined(CONFIG_STM32U5_UART5_SERIALDRIVER) +#elif defined(CONFIG_UART5_SERIAL_CONSOLE) && defined(CONFIG_STM32_UART5_SERIALDRIVER) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE @@ -170,27 +170,27 @@ /* Disable the DMA configuration on all unused USARTs */ -#ifndef CONFIG_STM32U5_LPUART1_SERIALDRIVER +#ifndef CONFIG_STM32_LPUART1_SERIALDRIVER # undef CONFIG_LPUART1_RXDMA #endif -#ifndef CONFIG_STM32U5_USART1_SERIALDRIVER +#ifndef CONFIG_STM32_USART1_SERIALDRIVER # undef CONFIG_USART1_RXDMA #endif -#ifndef CONFIG_STM32U5_USART2_SERIALDRIVER +#ifndef CONFIG_STM32_USART2_SERIALDRIVER # undef CONFIG_USART2_RXDMA #endif -#ifndef CONFIG_STM32U5_USART3_SERIALDRIVER +#ifndef CONFIG_STM32_USART3_SERIALDRIVER # undef CONFIG_USART3_RXDMA #endif -#ifndef CONFIG_STM32U5_UART4_SERIALDRIVER +#ifndef CONFIG_STM32_UART4_SERIALDRIVER # undef CONFIG_UART4_RXDMA #endif -#ifndef CONFIG_STM32U5_UART5_SERIALDRIVER +#ifndef CONFIG_STM32_UART5_SERIALDRIVER # undef CONFIG_UART5_RXDMA #endif @@ -223,17 +223,17 @@ /* Is DMA used on all (enabled) USARTs */ #define SERIAL_HAVE_ONLY_DMA 1 -#if defined(CONFIG_STM32U5_LPUART1_SERIALDRIVER) && !defined(CONFIG_LPUART1_RXDMA) +#if defined(CONFIG_STM32_LPUART1_SERIALDRIVER) && !defined(CONFIG_LPUART1_RXDMA) # undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32U5_USART1_SERIALDRIVER) && !defined(CONFIG_USART1_RXDMA) +#elif defined(CONFIG_STM32_USART1_SERIALDRIVER) && !defined(CONFIG_USART1_RXDMA) # undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32U5_USART2_SERIALDRIVER) && !defined(CONFIG_USART2_RXDMA) +#elif defined(CONFIG_STM32_USART2_SERIALDRIVER) && !defined(CONFIG_USART2_RXDMA) # undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32U5_USART3_SERIALDRIVER) && !defined(CONFIG_USART3_RXDMA) +#elif defined(CONFIG_STM32_USART3_SERIALDRIVER) && !defined(CONFIG_USART3_RXDMA) # undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32U5_UART4_SERIALDRIVER) && !defined(CONFIG_UART4_RXDMA) +#elif defined(CONFIG_STM32_UART4_SERIALDRIVER) && !defined(CONFIG_UART4_RXDMA) # undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32U5_UART5_SERIALDRIVER) && !defined(CONFIG_UART5_RXDMA) +#elif defined(CONFIG_STM32_UART5_SERIALDRIVER) && !defined(CONFIG_UART5_RXDMA) # undef SERIAL_HAVE_ONLY_DMA #endif diff --git a/arch/arm/src/stm32u5/stm32u5xx_rcc.c b/arch/arm/src/stm32u5/stm32u5xx_rcc.c index 3fb5798bd7f..3a044f6a8ee 100644 --- a/arch/arm/src/stm32u5/stm32u5xx_rcc.c +++ b/arch/arm/src/stm32u5/stm32u5xx_rcc.c @@ -60,7 +60,7 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, /* Determine if board wants to use HSI48 as 48 MHz oscillator. */ -#if defined(CONFIG_STM32U5_HAVE_HSI48) && defined(STM32_USE_CLK48) +#if defined(CONFIG_STM32_HAVE_HSI48) && defined(STM32_USE_CLK48) # if STM32_CLK48_SEL == RCC_CCIPR_CLK48SEL_HSI48 # define STM32_USE_HSI48 # endif @@ -96,51 +96,51 @@ static inline void rcc_enableahb1(void) regval |= RCC_AHB1ENR_GPDMA1EN; #endif -#ifdef CONFIG_STM32U5_CORDIC +#ifdef CONFIG_STM32_CORDIC regval |= RCC_AHB1ENR_CORDIC; #endif -#ifdef CONFIG_STM32U5_FMAC +#ifdef CONFIG_STM32_FMAC regval |= RCC_AHB1ENR_FMACEN; #endif -#ifdef CONFIG_STM32U5_MDF1 +#ifdef CONFIG_STM32_MDF1 regval |= RCC_AHB1ENR_MDF1EN; #endif -#ifdef CONFIG_STM32U5_FLASH +#ifdef CONFIG_STM32_FLASH regval |= RCC_AHB1ENR_FLASHEN; #endif -#ifdef CONFIG_STM32U5_CRC +#ifdef CONFIG_STM32_CRC regval |= RCC_AHB1ENR_CRCEN; #endif -#ifdef CONFIG_STM32U5_TSC +#ifdef CONFIG_STM32_TSC regval |= RCC_AHB1ENR_TSCEN; #endif -#ifdef CONFIG_STM32U5_RAMCFG +#ifdef CONFIG_STM32_RAMCFG regval |= RCC_AHB1ENR_RAMCFGEN; #endif -#ifdef CONFIG_STM32U5_DMA2D +#ifdef CONFIG_STM32_DMA2D regval |= RCC_AHB1ENR_DMA2DEN; #endif -#ifdef CONFIG_STM32U5_GTZC1 +#ifdef CONFIG_STM32_GTZC1 regval |= RCC_AHB1ENR_GTZC1EN; #endif -#ifdef CONFIG_STM32U5_BKPSRAM +#ifdef CONFIG_STM32_BKPSRAM regval |= RCC_AHB1ENR_BKPSRAMEN; #endif -#ifdef CONFIG_STM32U5_DCACHE1 +#ifdef CONFIG_STM32_DCACHE1 regval |= RCC_AHB1ENR_DCACHE1EN; #endif -#ifdef CONFIG_STM32U5_SRAM1 +#ifdef CONFIG_STM32_SRAM1 regval |= RCC_AHB1ENR_SRAM1EN; #endif @@ -194,51 +194,51 @@ static inline void rcc_enableahb2(void) ); #endif -#if defined(CONFIG_STM32U5_ADC1) +#if defined(CONFIG_STM32_ADC1) regval |= RCC_AHB2ENR1_ADC1EN; #endif -#if defined(CONFIG_STM32U5_DCMI_PSSI) +#if defined(CONFIG_STM32_DCMI_PSSI) regval |= RCC_AHB2ENR1_DCMI_PSSIEN; #endif -#ifdef CONFIG_STM32U5_OTGHS +#ifdef CONFIG_STM32_OTGHS regval |= RCC_AHB2ENR1_OTGEN; #endif -#ifdef CONFIG_STM32U5_OTGHS +#ifdef CONFIG_STM32_OTGHS regval |= RCC_AHB2ENR1_OTGPHYEN; #endif -#ifdef CONFIG_STM32U5_AES +#ifdef CONFIG_STM32_AES regval |= RCC_AHB2ENR1_AESEN; #endif -#ifdef CONFIG_STM32U5_HASH +#ifdef CONFIG_STM32_HASH regval |= RCC_AHB2ENR1_HASHEN #endif -#ifdef CONFIG_STM32U5_RNG +#ifdef CONFIG_STM32_RNG regval |= RCC_AHB2ENR1_RNGEN; #endif -#ifdef CONFIG_STM32U5_PKA +#ifdef CONFIG_STM32_PKA regval |= RCC_AHB2ENR_PKAEN; #endif -#ifdef CONFIG_STM32U5_SAES +#ifdef CONFIG_STM32_SAES regval |= RCC_AHB2ENR1_SAES; #endif -#ifdef CONFIG_STM32U5_OCTOSPIM +#ifdef CONFIG_STM32_OCTOSPIM regval |= RCC_AHB2ENR1_OCTOSPIM; #endif -#ifdef CONFIG_STM32U5_OTFDEC1 +#ifdef CONFIG_STM32_OTFDEC1 regval |= RCC_AHB2ENR1_OTFDEC1; #endif -#ifdef CONFIG_STM32U5_OTFDEC2 +#ifdef CONFIG_STM32_OTFDEC2 regval |= RCC_AHB2ENR1_OTFDEC2; #endif @@ -250,11 +250,11 @@ static inline void rcc_enableahb2(void) regval |= RCC_AHB2ENR1_SDMMC2EN; #endif -#ifdef CONFIG_STM32U5_SRAM2 +#ifdef CONFIG_STM32_SRAM2 regval |= RCC_AHB2ENR1_SRAM2EN; #endif -#ifdef CONFIG_STM32U5_SRAM3 +#ifdef CONFIG_STM32_SRAM3 regval |= RCC_AHB2ENR1_SRAM3EN; #endif @@ -262,19 +262,19 @@ static inline void rcc_enableahb2(void) regval = getreg32(STM32_RCC_AHB2ENR2); -#ifdef CONFIG_STM32U5_FSMC +#ifdef CONFIG_STM32_FSMC regval |= RCC_AHB2ENR2_FSMCEN; #endif -#ifdef CONFIG_STM32U5_OCTOSPI1 +#ifdef CONFIG_STM32_OCTOSPI1 regval |= RCC_AHB2ENR2_OCTOSPI1EN; #endif -#ifdef CONFIG_STM32U5_OCTOSPI2 +#ifdef CONFIG_STM32_OCTOSPI2 regval |= RCC_AHB2ENR2_OCTOSPI2EN; #endif -#ifdef CONFIG_STM32U5_SRAM5 +#ifdef CONFIG_STM32_SRAM5 regval |= RCC_AHB2ENR2_SRAM5EN; #endif @@ -299,31 +299,31 @@ static inline void rcc_enableahb3(void) regval = getreg32(STM32_RCC_AHB3ENR); -#ifdef CONFIG_STM32U5_LPGPIO1 +#ifdef CONFIG_STM32_LPGPIO1 regval |= RCC_AHB3ENR_LPGPIO1EN; #endif -#ifdef CONFIG_STM32U5_PWR +#ifdef CONFIG_STM32_PWR regval |= RCC_AHB3ENR_PWREN; #endif -#ifdef CONFIG_STM32U5_ADC4 +#ifdef CONFIG_STM32_ADC4 regval |= RCC_AHB3ENR_ADC4EN; #endif -#ifdef CONFIG_STM32U5_DAC1 +#ifdef CONFIG_STM32_DAC1 regval |= RCC_AHB3ENR_DAC1EN; #endif -#ifdef CONFIG_STM32U5_LPDMA1 +#ifdef CONFIG_STM32_LPDMA1 regval |= RCC_AHB3ENR_LPDMA1EN; #endif -#ifdef CONFIG_STM32U5_ADF1 +#ifdef CONFIG_STM32_ADF1 regval |= RCC_AHB3ENR_ADF1EN; #endif -#ifdef CONFIG_STM32U5_GTZC2 +#ifdef CONFIG_STM32_GTZC2 regval |= RCC_AHB3ENR_GTZC2EN; #endif @@ -352,63 +352,63 @@ static inline void rcc_enableapb1(void) regval = getreg32(STM32_RCC_APB1ENR1); -#ifdef CONFIG_STM32U5_TIM2 +#ifdef CONFIG_STM32_TIM2 regval |= RCC_APB1ENR1_TIM2EN; #endif -#ifdef CONFIG_STM32U5_TIM3 +#ifdef CONFIG_STM32_TIM3 regval |= RCC_APB1ENR1_TIM3EN; #endif -#ifdef CONFIG_STM32U5_TIM4 +#ifdef CONFIG_STM32_TIM4 regval |= RCC_APB1ENR1_TIM4EN; #endif -#ifdef CONFIG_STM32U5_TIM5 +#ifdef CONFIG_STM32_TIM5 regval |= RCC_APB1ENR1_TIM5EN; #endif -#ifdef CONFIG_STM32U5_TIM6 +#ifdef CONFIG_STM32_TIM6 regval |= RCC_APB1ENR1_TIM6EN; #endif -#ifdef CONFIG_STM32U5_TIM7 +#ifdef CONFIG_STM32_TIM7 regval |= RCC_APB1ENR1_TIM7EN; #endif -#ifdef CONFIG_STM32U5_WWDG +#ifdef CONFIG_STM32_WWDG regval |= RCC_APB1ENR1_WWDGEN; #endif -#ifdef CONFIG_STM32U5_SPI2 +#ifdef CONFIG_STM32_SPI2 regval |= RCC_APB1ENR1_SPI2EN; #endif -#ifdef CONFIG_STM32U5_USART2 +#ifdef CONFIG_STM32_USART2 regval |= RCC_APB1ENR1_USART2EN; #endif -#ifdef CONFIG_STM32U5_USART3 +#ifdef CONFIG_STM32_USART3 regval |= RCC_APB1ENR1_USART3EN; #endif -#ifdef CONFIG_STM32U5_UART4 +#ifdef CONFIG_STM32_UART4 regval |= RCC_APB1ENR1_UART4EN; #endif -#ifdef CONFIG_STM32U5_UART5 +#ifdef CONFIG_STM32_UART5 regval |= RCC_APB1ENR1_UART5EN; #endif -#ifdef CONFIG_STM32U5_I2C1 +#ifdef CONFIG_STM32_I2C1 regval |= RCC_APB1ENR1_I2C1EN; #endif -#ifdef CONFIG_STM32U5_I2C2 +#ifdef CONFIG_STM32_I2C2 regval |= RCC_APB1ENR1_I2C2EN; #endif -#ifdef CONFIG_STM32U5_CRS +#ifdef CONFIG_STM32_CRS regval |= RCC_APB1ENR1_CRSEN; #endif @@ -418,19 +418,19 @@ static inline void rcc_enableapb1(void) regval = getreg32(STM32_RCC_APB1ENR2); -#ifdef CONFIG_STM32U5_I2C4 +#ifdef CONFIG_STM32_I2C4 regval |= RCC_APB1ENR2_I2C4EN; #endif -#ifdef CONFIG_STM32U5_LPTIM2 +#ifdef CONFIG_STM32_LPTIM2 regval |= RCC_APB1ENR2_LPTIM2EN; #endif -#ifdef CONFIG_STM32U5_FDCAN1 +#ifdef CONFIG_STM32_FDCAN1 regval |= RCC_APB1ENR2_FDCAN1EN; #endif -#ifdef CONFIG_STM32U5_UCPD1 +#ifdef CONFIG_STM32_UCPD1 regval |= RCC_APB1ENR2_UCPD1EN; #endif @@ -455,39 +455,39 @@ static inline void rcc_enableapb2(void) regval = getreg32(STM32_RCC_APB2ENR); -#ifdef CONFIG_STM32U5_TIM1 +#ifdef CONFIG_STM32_TIM1 regval |= RCC_APB2ENR_TIM1EN; #endif -#ifdef CONFIG_STM32U5_SPI1 +#ifdef CONFIG_STM32_SPI1 regval |= RCC_APB2ENR_SPI1EN; #endif -#ifdef CONFIG_STM32U5_TIM8 +#ifdef CONFIG_STM32_TIM8 regval |= RCC_APB2ENR_TIM8EN; #endif -#ifdef CONFIG_STM32U5_USART1 +#ifdef CONFIG_STM32_USART1 regval |= RCC_APB2ENR_USART1EN; #endif -#ifdef CONFIG_STM32U5_TIM15 +#ifdef CONFIG_STM32_TIM15 regval |= RCC_APB2ENR_TIM15EN; #endif -#ifdef CONFIG_STM32U5_TIM16 +#ifdef CONFIG_STM32_TIM16 regval |= RCC_APB2ENR_TIM16EN; #endif -#ifdef CONFIG_STM32U5_TIM17 +#ifdef CONFIG_STM32_TIM17 regval |= RCC_APB2ENR_TIM17EN; #endif -#ifdef CONFIG_STM32U5_SAI1 +#ifdef CONFIG_STM32_SAI1 regval |= RCC_APB2ENR_SAI1EN; #endif -#ifdef CONFIG_STM32U5_SAI2 +#ifdef CONFIG_STM32_SAI2 regval |= RCC_APB2ENR_SAI2EN; #endif @@ -512,15 +512,15 @@ static inline void rcc_enableapb3(void) regval = getreg32(STM32_RCC_APB3ENR); -#ifdef CONFIG_STM32U5_SYSCFG +#ifdef CONFIG_STM32_SYSCFG regval |= RCC_APB3ENR_SYSCFGEN; #endif -#ifdef CONFIG_STM32U5_SPI3 +#ifdef CONFIG_STM32_SPI3 regval |= RCC_APB3ENR_SPI3EN; #endif -#ifdef CONFIG_STM32U5_LPUART1 +#ifdef CONFIG_STM32_LPUART1 regval |= RCC_APB3ENR_LPUART1EN; #endif @@ -528,31 +528,31 @@ static inline void rcc_enableapb3(void) regval |= RCC_APB3ENR_I2C3EN; #endif -#ifdef CONFIG_STM32U5_LPTIM1 +#ifdef CONFIG_STM32_LPTIM1 regval |= RCC_APB3ENR_LPTIM1EN; #endif -#ifdef CONFIG_STM32U5_LPTIM3 +#ifdef CONFIG_STM32_LPTIM3 regval |= RCC_APB3ENR_LPTIM3EN; #endif -#ifdef CONFIG_STM32U5_LPTIM4 +#ifdef CONFIG_STM32_LPTIM4 regval |= RCC_APB3ENR_LPTIM4EN; #endif -#ifdef CONFIG_STM32U5_OPAMP +#ifdef CONFIG_STM32_OPAMP regval |= RCC_APB3ENR_OPAMPEN; #endif -#ifdef CONFIG_STM32U5_COMP +#ifdef CONFIG_STM32_COMP regval |= RCC_APB3ENR_COMPEN; #endif -#ifdef CONFIG_STM32U5_VREF +#ifdef CONFIG_STM32_VREF regval |= RCC_APB3ENR_VREFEN; #endif -#ifdef CONFIG_STM32U5_RTCAPB +#ifdef CONFIG_STM32_RTCAPB regval |= RCC_APB3ENR_RTCAPBEN; #endif @@ -604,7 +604,7 @@ void stm32_rcc_enableperipherals(void) * power clocking modes! ****************************************************************************/ -#ifndef CONFIG_ARCH_BOARD_STM32U5_CUSTOM_CLOCKCONFIG +#ifndef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG void stm32_stdclockconfig(void) { uint32_t regval; @@ -742,9 +742,9 @@ void stm32_stdclockconfig(void) regval |= STM32_RCC_CFGR3_PPRE3; putreg32(regval, STM32_RCC_CFGR3); -#ifdef CONFIG_STM32U5_RTC_HSECLOCK +#ifdef CONFIG_STM32_RTC_HSECLOCK -# error stm32_stdclockconfig() currently doesn not support CONFIG_STM32U5_RTC_HSECLOCK +# error stm32_stdclockconfig() currently doesn not support CONFIG_STM32_RTC_HSECLOCK #endif @@ -799,7 +799,7 @@ void stm32_stdclockconfig(void) { } -#if defined(CONFIG_STM32U5_IWDG) || defined(CONFIG_STM32U5_RTC_LSICLOCK) +#if defined(CONFIG_STM32_IWDG) || defined(CONFIG_STM32_RTC_LSICLOCK) /* Low speed internal clock source LSI */ stm32_rcc_enablelsi(); diff --git a/boards/arm/stm32u5/b-u585i-iot02a/configs/nsh/defconfig b/boards/arm/stm32u5/b-u585i-iot02a/configs/nsh/defconfig index 74b6940237b..eabf176d3fd 100644 --- a/boards/arm/stm32u5/b-u585i-iot02a/configs/nsh/defconfig +++ b/boards/arm/stm32u5/b-u585i-iot02a/configs/nsh/defconfig @@ -11,6 +11,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="b-u585i-iot02a" CONFIG_ARCH_BOARD_B_U585I_IOT02A=y CONFIG_ARCH_CHIP="stm32u5" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32U585AI=y CONFIG_ARCH_CHIP_STM32U5=y CONFIG_ARCH_INTERRUPTSTACK=2048 @@ -45,10 +46,10 @@ CONFIG_READLINE_TABCOMPLETION=y CONFIG_RR_INTERVAL=200 CONFIG_SCHED_WAITPID=y CONFIG_STACK_COLORATION=y -CONFIG_STM32U5_PWR=y -CONFIG_STM32U5_SPI1=y -CONFIG_STM32U5_SRAM3=y -CONFIG_STM32U5_USART1=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_SRAM3=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_SPITOOL=y CONFIG_SYSTEM_STACKMONITOR=y diff --git a/boards/arm/stm32u5/b-u585i-iot02a/src/CMakeLists.txt b/boards/arm/stm32u5/b-u585i-iot02a/src/CMakeLists.txt index a845f39aefe..150aef2e647 100644 --- a/boards/arm/stm32u5/b-u585i-iot02a/src/CMakeLists.txt +++ b/boards/arm/stm32u5/b-u585i-iot02a/src/CMakeLists.txt @@ -22,7 +22,7 @@ set(SRCS stm32_boot.c stm32_bringup.c stm32_spi.c) -if(CONFIG_ARCH_BOARD_STM32U5_CUSTOM_CLOCKCONFIG) +if(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) list(APPEND SRCS stm32_clockconfig.c) endif() diff --git a/boards/arm/stm32u5/b-u585i-iot02a/src/Makefile b/boards/arm/stm32u5/b-u585i-iot02a/src/Makefile index 0a32978916a..915275f7e6f 100644 --- a/boards/arm/stm32u5/b-u585i-iot02a/src/Makefile +++ b/boards/arm/stm32u5/b-u585i-iot02a/src/Makefile @@ -25,7 +25,7 @@ ASRCS = CSRCS = stm32_boot.c stm32_bringup.c stm32_spi.c -ifeq ($(CONFIG_ARCH_BOARD_STM32U5_CUSTOM_CLOCKCONFIG),y) +ifeq ($(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG),y) CSRCS += stm32_clockconfig.c endif diff --git a/boards/arm/stm32u5/b-u585i-iot02a/src/stm32_clockconfig.c b/boards/arm/stm32u5/b-u585i-iot02a/src/stm32_clockconfig.c index b6aa7c6a371..378c5ec51c7 100644 --- a/boards/arm/stm32u5/b-u585i-iot02a/src/stm32_clockconfig.c +++ b/boards/arm/stm32u5/b-u585i-iot02a/src/stm32_clockconfig.c @@ -38,12 +38,12 @@ * NuttX in the Non-Secure domain together with TrustedFirmware-M (TFM). * In this setup the clock configuration is done by TFM, not by NuttX. * Thus, the board's configuration sets - * CONFIG_ARCH_BOARD_STM32L5_CUSTOM_CLOCKCONFIG to avoid the standard clock + * CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG to avoid the standard clock * config logic to run and instead do just nothing in this function. * ****************************************************************************/ -#if defined(CONFIG_ARCH_BOARD_STM32U5_CUSTOM_CLOCKCONFIG) +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) void stm32_board_clockconfig(void) { } diff --git a/boards/arm/stm32u5/b-u585i-iot02a/src/stm32_spi.c b/boards/arm/stm32u5/b-u585i-iot02a/src/stm32_spi.c index 4bea93db071..13bd3f79895 100644 --- a/boards/arm/stm32u5/b-u585i-iot02a/src/stm32_spi.c +++ b/boards/arm/stm32u5/b-u585i-iot02a/src/stm32_spi.c @@ -41,7 +41,7 @@ #include "b-u585i-iot02a.h" #include -#ifdef CONFIG_STM32U5_SPI +#ifdef CONFIG_STM32_SPI /**************************************************************************** * Public Functions @@ -64,7 +64,7 @@ void stm32_spidev_initialize(void) * architecture. */ -#ifdef CONFIG_STM32U5_SPI1 +#ifdef CONFIG_STM32_SPI1 stm32_configgpio(GPIO_SPI1_NSS); #endif } @@ -95,7 +95,7 @@ void stm32_spidev_initialize(void) * ****************************************************************************/ -#ifdef CONFIG_STM32U5_SPI1 +#ifdef CONFIG_STM32_SPI1 void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -111,7 +111,7 @@ uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32U5_SPI2 +#ifdef CONFIG_STM32_SPI2 void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -125,7 +125,7 @@ uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32U5_SPI3 +#ifdef CONFIG_STM32_SPI3 void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -162,25 +162,25 @@ uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) ****************************************************************************/ #ifdef CONFIG_SPI_CMDDATA -#ifdef CONFIG_STM32U5_SPI1 +#ifdef CONFIG_STM32_SPI1 int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32U5_SPI2 +#ifdef CONFIG_STM32_SPI2 int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32U5_SPI3 +#ifdef CONFIG_STM32_SPI3 int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif #endif /* CONFIG_SPI_CMDDATA */ -#endif /* CONFIG_STM32U5_SPI */ +#endif /* CONFIG_STM32_SPI */ diff --git a/boards/arm/stm32u5/nucleo-u5a5zj-q/configs/nsh/defconfig b/boards/arm/stm32u5/nucleo-u5a5zj-q/configs/nsh/defconfig index a489a5a0284..62d5aa14537 100644 --- a/boards/arm/stm32u5/nucleo-u5a5zj-q/configs/nsh/defconfig +++ b/boards/arm/stm32u5/nucleo-u5a5zj-q/configs/nsh/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-u5a5zj-q" CONFIG_ARCH_BOARD_NUCLEO_U5A5ZJ_Q=y CONFIG_ARCH_CHIP="stm32u5" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32U5=y CONFIG_ARCH_CHIP_STM32U5A5ZJT=y CONFIG_ARCH_INTERRUPTSTACK=2048 @@ -47,14 +48,14 @@ CONFIG_READLINE_TABCOMPLETION=y CONFIG_RR_INTERVAL=200 CONFIG_SCHED_WAITPID=y CONFIG_STACK_COLORATION=y -CONFIG_STM32U5_PWR=y -CONFIG_STM32U5_SRAM2=y -CONFIG_STM32U5_SRAM2_HEAP=y -CONFIG_STM32U5_SRAM3=y -CONFIG_STM32U5_SRAM3_HEAP=y -CONFIG_STM32U5_SRAM5=y -CONFIG_STM32U5_SRAM5_HEAP=y -CONFIG_STM32U5_USART1=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SRAM2=y +CONFIG_STM32_SRAM2_HEAP=y +CONFIG_STM32_SRAM3=y +CONFIG_STM32_SRAM3_HEAP=y +CONFIG_STM32_SRAM5=y +CONFIG_STM32_SRAM5_HEAP=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_NSH_STACKSIZE=2048 CONFIG_SYSTEM_TEE=y diff --git a/boards/arm/stm32u5/nucleo-u5a5zj-q/src/CMakeLists.txt b/boards/arm/stm32u5/nucleo-u5a5zj-q/src/CMakeLists.txt index fa6b58b12dc..0ab477f5946 100644 --- a/boards/arm/stm32u5/nucleo-u5a5zj-q/src/CMakeLists.txt +++ b/boards/arm/stm32u5/nucleo-u5a5zj-q/src/CMakeLists.txt @@ -22,7 +22,7 @@ set(SRCS stm32_boot.c stm32_bringup.c stm32_spi.c) -if(CONFIG_ARCH_BOARD_STM32U5_CUSTOM_CLOCKCONFIG) +if(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) list(APPEND SRCS stm32_clockconfig.c) endif() diff --git a/boards/arm/stm32u5/nucleo-u5a5zj-q/src/Makefile b/boards/arm/stm32u5/nucleo-u5a5zj-q/src/Makefile index 1fa94c46e61..93d9723add3 100644 --- a/boards/arm/stm32u5/nucleo-u5a5zj-q/src/Makefile +++ b/boards/arm/stm32u5/nucleo-u5a5zj-q/src/Makefile @@ -25,7 +25,7 @@ ASRCS = CSRCS = stm32_boot.c stm32_bringup.c stm32_spi.c -ifeq ($(CONFIG_ARCH_BOARD_STM32U5_CUSTOM_CLOCKCONFIG),y) +ifeq ($(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG),y) CSRCS += stm32_clockconfig.c endif diff --git a/boards/arm/stm32u5/nucleo-u5a5zj-q/src/stm32_clockconfig.c b/boards/arm/stm32u5/nucleo-u5a5zj-q/src/stm32_clockconfig.c index 24afdb388ba..976a515f7b4 100644 --- a/boards/arm/stm32u5/nucleo-u5a5zj-q/src/stm32_clockconfig.c +++ b/boards/arm/stm32u5/nucleo-u5a5zj-q/src/stm32_clockconfig.c @@ -38,12 +38,12 @@ * NuttX in the Non-Secure domain together with TrustedFirmware-M (TFM). * In this setup the clock configuration is done by TFM, not by NuttX. * Thus, the board's configuration sets - * CONFIG_ARCH_BOARD_STM32L5_CUSTOM_CLOCKCONFIG to avoid the standard clock + * CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG to avoid the standard clock * config logic to run and instead do just nothing in this function. * ****************************************************************************/ -#if defined(CONFIG_ARCH_BOARD_STM32U5_CUSTOM_CLOCKCONFIG) +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) void stm32_board_clockconfig(void) { } diff --git a/boards/arm/stm32u5/nucleo-u5a5zj-q/src/stm32_spi.c b/boards/arm/stm32u5/nucleo-u5a5zj-q/src/stm32_spi.c index efae2e53942..34e5a5352dd 100644 --- a/boards/arm/stm32u5/nucleo-u5a5zj-q/src/stm32_spi.c +++ b/boards/arm/stm32u5/nucleo-u5a5zj-q/src/stm32_spi.c @@ -41,7 +41,7 @@ #include "nucleo-u5a5zj-q.h" #include -#ifdef CONFIG_STM32U5_SPI +#ifdef CONFIG_STM32_SPI /**************************************************************************** * Public Functions @@ -64,7 +64,7 @@ void stm32_spidev_initialize(void) * architecture. */ -#ifdef CONFIG_STM32U5_SPI1 +#ifdef CONFIG_STM32_SPI1 stm32_configgpio(GPIO_SPI1_NSS); #endif } @@ -95,7 +95,7 @@ void stm32_spidev_initialize(void) * ****************************************************************************/ -#ifdef CONFIG_STM32U5_SPI1 +#ifdef CONFIG_STM32_SPI1 void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -111,7 +111,7 @@ uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32U5_SPI2 +#ifdef CONFIG_STM32_SPI2 void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -125,7 +125,7 @@ uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32U5_SPI3 +#ifdef CONFIG_STM32_SPI3 void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -162,25 +162,25 @@ uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) ****************************************************************************/ #ifdef CONFIG_SPI_CMDDATA -#ifdef CONFIG_STM32U5_SPI1 +#ifdef CONFIG_STM32_SPI1 int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32U5_SPI2 +#ifdef CONFIG_STM32_SPI2 int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32U5_SPI3 +#ifdef CONFIG_STM32_SPI3 int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif #endif /* CONFIG_SPI_CMDDATA */ -#endif /* CONFIG_STM32U5_SPI */ +#endif /* CONFIG_STM32_SPI */