From da74440a2046dca43a4cbbd05f9b579816ff7ec4 Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Fri, 14 Aug 2026 08:58:13 +0200 Subject: [PATCH] arch/arm: add stm32u0 support add stm32u0 support Signed-off-by: raiden00pl Assisted-by: Claude Code --- Documentation/guides/stm32_ports.rst | 38 +- Documentation/platforms/arm/stm32u0/index.rst | 60 ++ arch/arm/Kconfig | 11 + arch/arm/include/stm32u0/chip.h | 106 +++ arch/arm/include/stm32u0/irq.h | 132 ++++ arch/arm/src/common/stm32/Kconfig | 1 + arch/arm/src/common/stm32/Kconfig.flash | 2 +- arch/arm/src/common/stm32/Kconfig.have | 5 +- .../common/stm32/hardware/stm32_adc_v2_m0.h | 13 +- .../common/stm32/hardware/stm32_dma_v1_7ch.h | 3 +- .../common/stm32/hardware/stm32_dmamux_7ch.h | 2 + .../stm32/hardware/stm32_exti_v1v2_m0.h | 2 + .../common/stm32/hardware/stm32_flash_m0.h | 2 + .../common/stm32/hardware/stm32_gpio_v2_m0.h | 2 + .../stm32/hardware/stm32_pwr_v1_m0_g0.h | 2 + .../arm/src/common/stm32/hardware/stm32_rcc.h | 2 + .../src/common/stm32/hardware/stm32_syscfg.h | 2 + arch/arm/src/common/stm32/stm32_adc_m0_v1.c | 17 +- arch/arm/src/common/stm32/stm32_adc_m0_v1.h | 9 + .../common/stm32/stm32_dma_m0_v1_7ch_dmamux.c | 6 +- arch/arm/src/common/stm32/stm32_gpio_m0_v1.h | 16 +- arch/arm/src/common/stm32/stm32_hsi48_m0_v1.c | 4 + arch/arm/src/common/stm32/stm32_lse_m0_v1.c | 2 +- arch/arm/src/common/stm32/stm32_pwr.h | 3 +- arch/arm/src/common/stm32/stm32_spi_m0_v1.c | 2 +- arch/arm/src/stm32u0/CMakeLists.txt | 28 + arch/arm/src/stm32u0/Kconfig | 199 +++++ arch/arm/src/stm32u0/Make.defs | 27 + arch/arm/src/stm32u0/chip.h | 44 ++ .../src/stm32u0/hardware/stm32_memorymap.h | 32 + arch/arm/src/stm32u0/hardware/stm32_pinmap.h | 32 + .../arm/src/stm32u0/hardware/stm32u0_dmamux.h | 326 ++++++++ arch/arm/src/stm32u0/hardware/stm32u0_exti.h | 85 +++ arch/arm/src/stm32u0/hardware/stm32u0_flash.h | 238 ++++++ .../src/stm32u0/hardware/stm32u0_memorymap.h | 144 ++++ .../arm/src/stm32u0/hardware/stm32u0_pinmap.h | 417 ++++++++++ arch/arm/src/stm32u0/hardware/stm32u0_pwr.h | 175 +++++ arch/arm/src/stm32u0/hardware/stm32u0_rcc.h | 611 +++++++++++++++ .../arm/src/stm32u0/hardware/stm32u0_syscfg.h | 356 +++++++++ arch/arm/src/stm32u0/stm32.h | 55 ++ arch/arm/src/stm32u0/stm32_rcc.c | 220 ++++++ arch/arm/src/stm32u0/stm32u0_rcc.c | 710 ++++++++++++++++++ 42 files changed, 4117 insertions(+), 26 deletions(-) create mode 100644 Documentation/platforms/arm/stm32u0/index.rst create mode 100644 arch/arm/include/stm32u0/chip.h create mode 100644 arch/arm/include/stm32u0/irq.h create mode 100644 arch/arm/src/stm32u0/CMakeLists.txt create mode 100644 arch/arm/src/stm32u0/Kconfig create mode 100644 arch/arm/src/stm32u0/Make.defs create mode 100644 arch/arm/src/stm32u0/chip.h create mode 100644 arch/arm/src/stm32u0/hardware/stm32_memorymap.h create mode 100644 arch/arm/src/stm32u0/hardware/stm32_pinmap.h create mode 100644 arch/arm/src/stm32u0/hardware/stm32u0_dmamux.h create mode 100644 arch/arm/src/stm32u0/hardware/stm32u0_exti.h create mode 100644 arch/arm/src/stm32u0/hardware/stm32u0_flash.h create mode 100644 arch/arm/src/stm32u0/hardware/stm32u0_memorymap.h create mode 100644 arch/arm/src/stm32u0/hardware/stm32u0_pinmap.h create mode 100644 arch/arm/src/stm32u0/hardware/stm32u0_pwr.h create mode 100644 arch/arm/src/stm32u0/hardware/stm32u0_rcc.h create mode 100644 arch/arm/src/stm32u0/hardware/stm32u0_syscfg.h create mode 100644 arch/arm/src/stm32u0/stm32.h create mode 100644 arch/arm/src/stm32u0/stm32_rcc.c create mode 100644 arch/arm/src/stm32u0/stm32u0_rcc.c diff --git a/Documentation/guides/stm32_ports.rst b/Documentation/guides/stm32_ports.rst index 50a955fafff..7e10a5f71e4 100644 --- a/Documentation/guides/stm32_ports.rst +++ b/Documentation/guides/stm32_ports.rst @@ -34,7 +34,7 @@ STM32MP1 Cortex-M4 unsupported none STM32MP2 Cortex-A35 unsupported none STM32MP2 Cortex-M33 unsupported none STM32N6 Cortex-M55 supported ``arch/arm/src/stm32n6`` -STM32U0 Cortex-M0+ unsupported none +STM32U0 Cortex-M0+ supported ``arch/arm/src/stm32u0`` STM32U3 Cortex-M33 unsupported none STM32U5 Cortex-M33 supported ``arch/arm/src/stm32u5`` STM32WB Cortex-M4 supported ``arch/arm/src/stm32wb`` @@ -694,10 +694,42 @@ RCC to be done arch/arm/src/stm32n6/stm32_rcc.c SPI/I2S to be done not supported TIM to be done not supported USART/LPUART v4 arch/arm/src/stm32n6/stm32_serial.c -USB device not supported -XSPI to be done not supported +USB device not supported +XSPI to be done not supported ============ ============ =================================== +STM32U0 +------- + +============ ============ ====================================================== +Peripheral Core version Driver +============ ============ ====================================================== +ADC v1 arch/arm/src/common/stm32/stm32_adc_m0_v1.c +AES v1 arch/arm/src/common/stm32/stm32_aes_m0_v1.c +COMP v1 not supported +DAC v1 not supported +DMA v1 arch/arm/src/common/stm32/stm32_dma_m0_v1_7ch_dmamux.c +DMAMUX v1 12ch arch/arm/src/common/stm32/stm32_dma_m0_v1_7ch_dmamux.c +EXTI v2 arch/arm/src/common/stm32/stm32_exti_gpio_m0_v1.c +FLASH U0 not supported +GPIO v1 arch/arm/src/common/stm32/stm32_gpio_m0_v1.c +I2C v1 arch/arm/src/common/stm32/stm32_i2c_m0_v1.c +IWDG v1 arch/arm/src/common/stm32/stm32_iwdg_m0_v1.c +LCD to be done not supported +LPTIM to be done not supported +PWR G0 arch/arm/src/common/stm32/stm32_pwr_m0_g0.c +RCC to be done arch/arm/src/stm32u0/stm32_rcc.c +RNG v1 arch/arm/src/common/stm32/stm32_rng_m0_v1.c +RTC RTCC M0 not supported +SPI/I2S v2 arch/arm/src/common/stm32/stm32_spi_m0_v1.c +SYSCFG to be done not supported +TIM v1 arch/arm/src/common/stm32/stm32_tim_m0_v1.c +TSC to be done not supported +USART/LPUART v4 arch/arm/src/common/stm32/stm32_serial_m0_v4.c +USB device not supported +WWDG v1 arch/arm/src/common/stm32/stm32_wwdg_m0_v1.c +============ ============ ====================================================== + STM32U5 ------- diff --git a/Documentation/platforms/arm/stm32u0/index.rst b/Documentation/platforms/arm/stm32u0/index.rst new file mode 100644 index 00000000000..1039c4164fe --- /dev/null +++ b/Documentation/platforms/arm/stm32u0/index.rst @@ -0,0 +1,60 @@ +========== +ST STM32U0 +========== + +Supported MCUs +============== + +========= ======= ======================= +MCU Support Note +========= ======= ======================= +STM32U031 No +STM32U073 Yes USB not supported yet +STM32U083 Yes USB not supported yet +========= ======= ======================= + +Peripheral Support +================== + +The following list indicates peripherals supported in NuttX: + +========== ======= ===== +Peripheral Support Notes +========== ======= ===== +FLASH No +PM No +RCC Yes +GPIO Yes +SYSCFG No +DMA Yes +DMAMUX Yes +EXTI Yes +CRC No +ADC Yes +DAC No +COMP No +OPAMP No +RNG Yes +AES Yes +TSC No +LCD No +TIM Yes +LPTIM No +IWDG Yes +WWDG Yes +RTC No +I2C Yes +USART Yes +LPUART No +SPI Yes +USB No +========== ======= ===== + +Supported Boards +================ + +.. toctree:: + :glob: + :maxdepth: 1 + + boards/*/* diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index febb01301d8..bf62351cbb4 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -623,6 +623,13 @@ config ARCH_CHIP_STM32C0 ---help--- STMicro STM32C0 architectures (ARM Cortex-M0+). +config ARCH_CHIP_STM32U0 + bool "STMicro STM32 U0" + select ARCH_CHIP_STM32 + select ARCH_CORTEXM0 + ---help--- + STMicro STM32U0 architectures (ARM Cortex-M0+). + config ARCH_CHIP_STM32F7 bool "STMicro STM32 F7" select ARCH_CHIP_STM32 @@ -1364,6 +1371,7 @@ config ARCH_CHIP default "stm32l0" if ARCH_CHIP_STM32L0 default "stm32g0" if ARCH_CHIP_STM32G0 default "stm32c0" if ARCH_CHIP_STM32C0 + default "stm32u0" if ARCH_CHIP_STM32U0 default "stm32f7" if ARCH_CHIP_STM32F7 default "stm32h7" if ARCH_CHIP_STM32H7 default "stm32l4" if ARCH_CHIP_STM32L4 @@ -1897,6 +1905,9 @@ endif if ARCH_CHIP_STM32C0 source "arch/arm/src/stm32c0/Kconfig" endif +if ARCH_CHIP_STM32U0 +source "arch/arm/src/stm32u0/Kconfig" +endif if ARCH_CHIP_STM32F7 source "arch/arm/src/stm32f7/Kconfig" endif diff --git a/arch/arm/include/stm32u0/chip.h b/arch/arm/include/stm32u0/chip.h new file mode 100644 index 00000000000..47ae057c900 --- /dev/null +++ b/arch/arm/include/stm32u0/chip.h @@ -0,0 +1,106 @@ +/**************************************************************************** + * arch/arm/include/stm32u0/chip.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_INCLUDE_STM32U0_CHIP_H +#define __ARCH_ARM_INCLUDE_STM32U0_CHIP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Prototypes + ****************************************************************************/ + +/* Number of peripheral interrupts */ + +#define ARMV6M_PERIPHERAL_INTERRUPTS 32 + +/* Get the flash size for each supported chip */ + +#if defined(CONFIG_ARCH_CHIP_STM32U073C8) || \ + defined(CONFIG_ARCH_CHIP_STM32U073M8) || \ + defined(CONFIG_ARCH_CHIP_STM32U073R8) +# define STM32_FLASH_SIZE (64 * 1024) /* 64Kb */ +#elif defined(CONFIG_ARCH_CHIP_STM32U073CB) || \ + defined(CONFIG_ARCH_CHIP_STM32U073MB) || \ + defined(CONFIG_ARCH_CHIP_STM32U073RB) +# define STM32_FLASH_SIZE (128 * 1024) /* 128Kb */ +#elif defined(CONFIG_ARCH_CHIP_STM32U073CC) || \ + defined(CONFIG_ARCH_CHIP_STM32U073MC) || \ + defined(CONFIG_ARCH_CHIP_STM32U073RC) || \ + defined(CONFIG_ARCH_CHIP_STM32U083CC) || \ + defined(CONFIG_ARCH_CHIP_STM32U083MC) || \ + defined(CONFIG_ARCH_CHIP_STM32U083RC) +# define STM32_FLASH_SIZE (256 * 1024) /* 256Kb */ +#endif + +/* Get customizations for each supported chip. + * The STM32U073xx and STM32U083xx families share the same peripheral set + * except for the AES accelerator which is available only on STM32U083xx. + */ + +# define STM32_SRAM_SIZE (40 * 1024) /* 40Kb = 32Kb SRAM1 + 8Kb + * backup SRAM2 (contiguous) */ + +# define STM32_NATIM 1 /* One advanced timer TIM1 */ +# define STM32_NGTIM16 3 /* 16-bit general up/down timers TIM3, + * TIM15-16 */ +# define STM32_NGTIM32 1 /* 32-bit general up/down timer TIM2 */ +# define STM32_NBTIM 2 /* Two basic timers: TIM6, TIM7 */ + /* Three LPTIMER: LPTIM1-3 */ +# define STM32_NSPI 3 /* Three SPI modules SPI1-3 */ +# define STM32_NI2S 1 /* One I2S module (SPI1 or I2S1) */ +# define STM32_NI2C 4 /* Four I2C modules I2C1-4 */ +# define STM32_NDMA 2 /* DMA1 7-channels, DMA2 5-channels */ +# define STM32_NUSART 4 /* Four USART modules, USART1-4 */ + /* Three LPUART: LPUART1-3 */ +# define STM32_NCAN 0 /* No CAN controllers */ +# define STM32_NLCD 1 /* One LCD controller */ +# define STM32_NUSBDEV 1 /* One USB full-speed device controller */ +# define STM32_NUSBOTG 0 /* No USB OTG */ +# define STM32_NCEC 0 /* No HDMI-CEC controller */ +# define STM32_NADC 1 /* (1) ADC1, 19-channels */ + +# define STM32_NDAC 1 /* One DAC channel */ +# define STM32_NCOMP 2 /* Two Analog Comparators */ +# define STM32_NCRC 1 /* One CRC module */ +# define STM32_NRNG 1 /* One Random number generator (RNG) */ +# define STM32_NCAP 1 /* One Touch sensing controller (TSC) */ +# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-F */ + +/* NVIC priority levels *****************************************************/ + +/* Each priority field holds a priority value, 0-31. The lower the value, + * the greater the priority of the corresponding interrupt. The processor + * implements only bits[7:6] of each field, bits[5:0] read as zero and + * ignore writes. + */ + +#define NVIC_SYSH_PRIORITY_MIN 0xc0 /* All bits[7:6] set is minimum priority */ +#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */ +#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */ +#define NVIC_SYSH_PRIORITY_STEP 0x40 /* Two bits of interrupt priority used */ + +#endif /* __ARCH_ARM_INCLUDE_STM32U0_CHIP_H */ diff --git a/arch/arm/include/stm32u0/irq.h b/arch/arm/include/stm32u0/irq.h new file mode 100644 index 00000000000..e13dcdf4fea --- /dev/null +++ b/arch/arm/include/stm32u0/irq.h @@ -0,0 +1,132 @@ +/**************************************************************************** + * arch/arm/include/stm32u0/irq.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* This file should never be included directly but, rather, only indirectly + * through nuttx/irq.h + */ + +#ifndef __ARCH_ARM_INCLUDE_STM32U0_IRQ_H +#define __ARCH_ARM_INCLUDE_STM32U0_IRQ_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#ifndef __ASSEMBLY__ +# include +#endif +#include + +/**************************************************************************** + * Pre-processor Prototypes + ****************************************************************************/ + +/* IRQ numbers. The IRQ number corresponds vector number and hence map + * directly to bits in the NVIC. This does, however, waste several words of + * memory in the IRQ to handle mapping tables. + */ + +/* Common Processor Exceptions (vectors 0-15) */ + +#define STM32_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */ + /* Vector 0: Reset stack pointer value */ + /* Vector 1: Reset (not handler as an IRQ) */ +#define STM32_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */ +#define STM32_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */ + /* Vectors 4-10: Reserved */ +#define STM32_IRQ_SVCALL (11) /* Vector 11: SVC call */ + /* Vector 12-13: Reserved */ +#define STM32_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */ +#define STM32_IRQ_SYSTICK (15) /* Vector 15: System tick */ + +/* External interrupts (vectors >= 16) */ + +#define STM32_IRQ_EXTINT (16) /* Vector number of the first external interrupt */ + +/* External interrupt vectors. + * Note that many vectors are shared by several peripherals (aliases below). + */ + +#define STM32_IRQ_WWDG (STM32_IRQ_EXTINT + 0) /* 0: Window Watchdog */ +#define STM32_IRQ_IWDG (STM32_IRQ_EXTINT + 0) /* 0: Independent Watchdog */ +#define STM32_IRQ_PVD (STM32_IRQ_EXTINT + 1) /* 1: PVD through EXTI Line detection */ +#define STM32_IRQ_PVM (STM32_IRQ_EXTINT + 1) /* 1: PVM through EXTI Line detection */ +#define STM32_IRQ_RTC (STM32_IRQ_EXTINT + 2) /* 2: RTC */ +#define STM32_IRQ_TAMP (STM32_IRQ_EXTINT + 2) /* 2: TAMP */ +#define STM32_IRQ_FLASH (STM32_IRQ_EXTINT + 3) /* 3: Flash, Flash ECC */ +#define STM32_IRQ_RCC (STM32_IRQ_EXTINT + 4) /* 4: RCC */ +#define STM32_IRQ_CRS (STM32_IRQ_EXTINT + 4) /* 4: CRS */ +#define STM32_IRQ_EXTI0_1 (STM32_IRQ_EXTINT + 5) /* 5: EXTI0_1 */ +#define STM32_IRQ_EXTI2_3 (STM32_IRQ_EXTINT + 6) /* 6: EXTI2_3 */ +#define STM32_IRQ_EXTI4_15 (STM32_IRQ_EXTINT + 7) /* 7: EXTI4_15 */ +#define STM32_IRQ_USB (STM32_IRQ_EXTINT + 8) /* 8: USB DRD FS */ +#define STM32_IRQ_DMA1CH1 (STM32_IRQ_EXTINT + 9) /* 9: DMA1_CH1 */ +#define STM32_IRQ_DMA1CH2 (STM32_IRQ_EXTINT + 10) /* 10: DMA1_CH2 */ +#define STM32_IRQ_DMA1CH3 (STM32_IRQ_EXTINT + 10) /* 10: DMA1_CH3 */ +#define STM32_IRQ_DMA1CH4 (STM32_IRQ_EXTINT + 11) /* 11: DMA1_CH4 */ +#define STM32_IRQ_DMA1CH5 (STM32_IRQ_EXTINT + 11) /* 11: DMA1_CH5 */ +#define STM32_IRQ_DMA1CH6 (STM32_IRQ_EXTINT + 11) /* 11: DMA1_CH6 */ +#define STM32_IRQ_DMA1CH7 (STM32_IRQ_EXTINT + 11) /* 11: DMA1_CH7 */ +#define STM32_IRQ_DMA2CH1 (STM32_IRQ_EXTINT + 11) /* 11: DMA2_CH1 */ +#define STM32_IRQ_DMA2CH2 (STM32_IRQ_EXTINT + 11) /* 11: DMA2_CH2 */ +#define STM32_IRQ_DMA2CH3 (STM32_IRQ_EXTINT + 11) /* 11: DMA2_CH3 */ +#define STM32_IRQ_DMA2CH4 (STM32_IRQ_EXTINT + 11) /* 11: DMA2_CH4 */ +#define STM32_IRQ_DMA2CH5 (STM32_IRQ_EXTINT + 11) /* 11: DMA2_CH5 */ +#define STM32_IRQ_DMAMUX (STM32_IRQ_EXTINT + 11) /* 11: DMAMUX overrun */ +#define STM32_IRQ_ADC (STM32_IRQ_EXTINT + 12) /* 12: ADC */ +#define STM32_IRQ_COMP (STM32_IRQ_EXTINT + 12) /* 12: COMP1, COMP2 */ +#define STM32_IRQ_TIM1_BRK (STM32_IRQ_EXTINT + 13) /* 13: TIM1_BRK_UP_TRG_COM */ +#define STM32_IRQ_TIM1_CC (STM32_IRQ_EXTINT + 14) /* 14: TIM1_CC */ +#define STM32_IRQ_TIM2 (STM32_IRQ_EXTINT + 15) /* 15: TIM2 */ +#define STM32_IRQ_TIM3 (STM32_IRQ_EXTINT + 16) /* 16: TIM3 */ +#define STM32_IRQ_TIM6 (STM32_IRQ_EXTINT + 17) /* 17: TIM6 */ +#define STM32_IRQ_DAC (STM32_IRQ_EXTINT + 17) /* 17: DAC */ +#define STM32_IRQ_LPTIM1 (STM32_IRQ_EXTINT + 17) /* 17: LPTIM1 */ +#define STM32_IRQ_TIM7 (STM32_IRQ_EXTINT + 18) /* 18: TIM7 */ +#define STM32_IRQ_LPTIM2 (STM32_IRQ_EXTINT + 18) /* 18: LPTIM2 */ +#define STM32_IRQ_TIM15 (STM32_IRQ_EXTINT + 19) /* 19: TIM15 */ +#define STM32_IRQ_LPTIM3 (STM32_IRQ_EXTINT + 19) /* 19: LPTIM3 */ +#define STM32_IRQ_TIM16 (STM32_IRQ_EXTINT + 20) /* 20: TIM16 */ +#define STM32_IRQ_TSC (STM32_IRQ_EXTINT + 21) /* 21: TSC */ +#define STM32_IRQ_LCD (STM32_IRQ_EXTINT + 22) /* 22: LCD */ +#define STM32_IRQ_I2C1 (STM32_IRQ_EXTINT + 23) /* 23: I2C1 */ +#define STM32_IRQ_I2C2 (STM32_IRQ_EXTINT + 24) /* 24: I2C2 */ +#define STM32_IRQ_I2C3 (STM32_IRQ_EXTINT + 24) /* 24: I2C3 */ +#define STM32_IRQ_I2C4 (STM32_IRQ_EXTINT + 24) /* 24: I2C4 */ +#define STM32_IRQ_SPI1 (STM32_IRQ_EXTINT + 25) /* 25: SPI1 */ +#define STM32_IRQ_SPI2 (STM32_IRQ_EXTINT + 26) /* 26: SPI2 */ +#define STM32_IRQ_SPI3 (STM32_IRQ_EXTINT + 26) /* 26: SPI3 */ +#define STM32_IRQ_USART1 (STM32_IRQ_EXTINT + 27) /* 27: USART1 */ +#define STM32_IRQ_USART2 (STM32_IRQ_EXTINT + 28) /* 28: USART2 */ +#define STM32_IRQ_LPUART2 (STM32_IRQ_EXTINT + 28) /* 28: LPUART2 */ +#define STM32_IRQ_USART3 (STM32_IRQ_EXTINT + 29) /* 29: USART3 */ +#define STM32_IRQ_LPUART1 (STM32_IRQ_EXTINT + 29) /* 29: LPUART1 */ +#define STM32_IRQ_USART4 (STM32_IRQ_EXTINT + 30) /* 30: USART4 */ +#define STM32_IRQ_LPUART3 (STM32_IRQ_EXTINT + 30) /* 30: LPUART3 */ +#define STM32_IRQ_RNG (STM32_IRQ_EXTINT + 31) /* 31: RNG */ +#define STM32_IRQ_AES (STM32_IRQ_EXTINT + 31) /* 31: AES */ + +#define STM32_IRQ_NEXTINTS (32) + +#define NR_IRQS (STM32_IRQ_EXTINT + STM32_IRQ_NEXTINTS) + +#endif /* __ARCH_ARM_INCLUDE_STM32U0_IRQ_H */ diff --git a/arch/arm/src/common/stm32/Kconfig b/arch/arm/src/common/stm32/Kconfig index a21fdfa9fa8..5c58b95d0ab 100644 --- a/arch/arm/src/common/stm32/Kconfig +++ b/arch/arm/src/common/stm32/Kconfig @@ -20,6 +20,7 @@ config STM32_COMMON_F0_L0_G0_C0 default y if ARCH_CHIP_STM32L0 default y if ARCH_CHIP_STM32G0 default y if ARCH_CHIP_STM32C0 + default y if ARCH_CHIP_STM32U0 config STM32_COMMON_F7_H7 bool diff --git a/arch/arm/src/common/stm32/Kconfig.flash b/arch/arm/src/common/stm32/Kconfig.flash index 1dc3d64bae9..0a04da242e1 100644 --- a/arch/arm/src/common/stm32/Kconfig.flash +++ b/arch/arm/src/common/stm32/Kconfig.flash @@ -61,7 +61,7 @@ config STM32_FLASH_CONFIG_Z default n config STM32_FLASH_OVERRIDE - bool "Override Flash Designator" if ARCH_CHIP_STM32G0 || ARCH_CHIP_STM32C0 + bool "Override Flash Designator" if ARCH_CHIP_STM32G0 || ARCH_CHIP_STM32C0 || ARCH_CHIP_STM32U0 default y if ARCH_CHIP_STM32F7 || STM32_COMMON_F7_H7_H5 default y if STM32_COMMON_L4_H5_L5_U5 || ARCH_CHIP_STM32WB default y if ARCH_CHIP_STM32WL5 diff --git a/arch/arm/src/common/stm32/Kconfig.have b/arch/arm/src/common/stm32/Kconfig.have index 73927364718..9ede5dc2247 100644 --- a/arch/arm/src/common/stm32/Kconfig.have +++ b/arch/arm/src/common/stm32/Kconfig.have @@ -64,7 +64,7 @@ config STM32_HAVE_ADC5 config STM32_HAVE_ADC_OVERSAMPLE bool - default STM32_STM32L0 || STM32_STM32G0 || STM32_STM32C0 + default STM32_STM32L0 || STM32_STM32G0 || STM32_STM32C0 || STM32_STM32U0 config STM32_HAVE_SDADC1 bool @@ -484,6 +484,9 @@ config STM32_HAVE_LPUART1 config STM32_HAVE_LPUART2 bool +config STM32_HAVE_LPUART3 + bool + config STM32_HAVE_LPUART bool diff --git a/arch/arm/src/common/stm32/hardware/stm32_adc_v2_m0.h b/arch/arm/src/common/stm32/hardware/stm32_adc_v2_m0.h index 645174f4637..0b1ac94b4db 100644 --- a/arch/arm/src/common/stm32/hardware/stm32_adc_v2_m0.h +++ b/arch/arm/src/common/stm32/hardware/stm32_adc_v2_m0.h @@ -49,7 +49,8 @@ /* Support for ADC clock prescaler */ -#if defined(CONFIG_STM32_STM32L0) || defined(CONFIG_STM32_STM32G0) +#if defined(CONFIG_STM32_STM32L0) || defined(CONFIG_STM32_STM32G0) || \ + defined(CONFIG_STM32_STM32U0) # define HAVE_ADC_PRE #else # undef HAVE_ADC_PRE @@ -120,7 +121,7 @@ #define STM32_ADC1_AWD2CR (STM32_ADC1_BASE + STM32_ADC_AWD2CR_OFFSET) #define STM32_ADC1_AWD3CR (STM32_ADC1_BASE + STM32_ADC_AWD3CR_OFFSET) #define STM32_ADC1_CALFACT (STM32_ADC1_BASE + STM32_ADC_CALFACT_OFFSET) -#if defined(CONFIG_ARCH_CHIP_STM32G0) +#if defined(CONFIG_ARCH_CHIP_STM32G0) || defined(CONFIG_ARCH_CHIP_STM32U0) # define STM32_ADC1_CCR (STM32_ADC1_BASE + STM32_ADC_CCR_OFFSET) #endif @@ -218,7 +219,8 @@ /* ADC sample time register */ -#if defined(CONFIG_ARCH_CHIP_STM32C0) || defined(CONFIG_ARCH_CHIP_STM32G0) +#if defined(CONFIG_ARCH_CHIP_STM32C0) || defined(CONFIG_ARCH_CHIP_STM32G0) || \ + defined(CONFIG_ARCH_CHIP_STM32U0) # define ADC_SMPR_1p5 (0) /* 000: 1.5 cycles */ # define ADC_SMPR_3p5 (1) /* 001: 3.5 cycles */ # define ADC_SMPR_7p5 (2) /* 010: 7.5 cycles */ @@ -243,7 +245,8 @@ #define ADC_SMPR_SMP2_SHIFT (4) /* Bits 4-6: Sampling time selection 2 */ #define ADC_SMPR_SMP2_MASK (7 << ADC_SMPR_SMP_SHIFT) #define ADC_SMPR_SMPSEL_SHIFT (8) /* Bits 8-26: channel-x sampling time selection */ -#if defined(CONFIG_ARCH_CHIP_STM32G0) || defined(CONFIG_ARCH_CHIP_STM32C0) +#if defined(CONFIG_ARCH_CHIP_STM32G0) || defined(CONFIG_ARCH_CHIP_STM32C0) || \ + defined(CONFIG_ARCH_CHIP_STM32U0) # define ADC_SMPR_SMPSEL(ch, smp) ((smp) << (ADC_SMPR_SMPSEL_SHIFT + ch)) /* ch = [0..22] and smp = 0 or 1 */ # define ADC_SMPSEL(ch, smp) ((smp) << (ch)) /* For use in adc_sampletime_set */ #else @@ -284,7 +287,7 @@ * Enabled when CHSELRMOD = 1 in ADC_CFGR1 */ -#if defined(CONFIG_ARCH_CHIP_STM32G0) +#if defined(CONFIG_ARCH_CHIP_STM32G0) || defined(CONFIG_ARCH_CHIP_STM32U0) # define ADC_CHSELR_ALT_SQN(sqn, ch) ((ch) << (((sqn) - 1) * 4)) /* sqn = [0..8], ch = [0..14] */ #endif diff --git a/arch/arm/src/common/stm32/hardware/stm32_dma_v1_7ch.h b/arch/arm/src/common/stm32/hardware/stm32_dma_v1_7ch.h index 6b3860db903..9cd4fc23e78 100644 --- a/arch/arm/src/common/stm32/hardware/stm32_dma_v1_7ch.h +++ b/arch/arm/src/common/stm32/hardware/stm32_dma_v1_7ch.h @@ -538,7 +538,8 @@ # define DMACHAN_USART5_TX_1 DMACHAN_SETTING(STM32_DMA1_CHAN7, 13) # define DMACHAN_USART5_TX_2 DMACHAN_SETTING(STM32_DMA1_CHAN3, 13) -#elif defined(CONFIG_ARCH_CHIP_STM32G0) || defined(CONFIG_ARCH_CHIP_STM32C0) +#elif defined(CONFIG_ARCH_CHIP_STM32G0) || defined(CONFIG_ARCH_CHIP_STM32C0) || \ + defined(CONFIG_ARCH_CHIP_STM32U0) /* This family uses a DMAMUX */ #else diff --git a/arch/arm/src/common/stm32/hardware/stm32_dmamux_7ch.h b/arch/arm/src/common/stm32/hardware/stm32_dmamux_7ch.h index b7c36335c0a..be49f6cca82 100644 --- a/arch/arm/src/common/stm32/hardware/stm32_dmamux_7ch.h +++ b/arch/arm/src/common/stm32/hardware/stm32_dmamux_7ch.h @@ -155,6 +155,8 @@ # include "hardware/stm32g0_dmamux.h" #elif defined(CONFIG_STM32_STM32C0) # include "hardware/stm32c0_dmamux.h" +#elif defined(CONFIG_STM32_STM32U0) +# include "hardware/stm32u0_dmamux.h" #else # error "Unsupported STM32 M0 sub family" #endif diff --git a/arch/arm/src/common/stm32/hardware/stm32_exti_v1v2_m0.h b/arch/arm/src/common/stm32/hardware/stm32_exti_v1v2_m0.h index 3f147d2a17f..9b454e56818 100644 --- a/arch/arm/src/common/stm32/hardware/stm32_exti_v1v2_m0.h +++ b/arch/arm/src/common/stm32/hardware/stm32_exti_v1v2_m0.h @@ -38,6 +38,8 @@ # include "hardware/stm32g0_exti.h" #elif defined(CONFIG_ARCH_CHIP_STM32C0) # include "hardware/stm32c0_exti.h" +#elif defined(CONFIG_ARCH_CHIP_STM32U0) +# include "hardware/stm32u0_exti.h" #else # error "Unrecognized STM32 M0 EXTI" #endif diff --git a/arch/arm/src/common/stm32/hardware/stm32_flash_m0.h b/arch/arm/src/common/stm32/hardware/stm32_flash_m0.h index 17f642f71e6..21c12858dd5 100644 --- a/arch/arm/src/common/stm32/hardware/stm32_flash_m0.h +++ b/arch/arm/src/common/stm32/hardware/stm32_flash_m0.h @@ -38,6 +38,8 @@ # include "hardware/stm32g0_flash.h" #elif defined(CONFIG_ARCH_CHIP_STM32C0) # include "hardware/stm32c0_flash.h" +#elif defined(CONFIG_ARCH_CHIP_STM32U0) +# include "hardware/stm32u0_flash.h" #else # error "Unsupported STM32 M0 FLASH" #endif diff --git a/arch/arm/src/common/stm32/hardware/stm32_gpio_v2_m0.h b/arch/arm/src/common/stm32/hardware/stm32_gpio_v2_m0.h index 94637dfc7a1..5af92aac291 100644 --- a/arch/arm/src/common/stm32/hardware/stm32_gpio_v2_m0.h +++ b/arch/arm/src/common/stm32/hardware/stm32_gpio_v2_m0.h @@ -35,6 +35,8 @@ # define STM32_GPIO_VERY_LOW_SPEED 1 /* Have very low speed operation */ #elif defined(CONFIG_ARCH_CHIP_STM32C0) # define STM32_GPIO_VERY_LOW_SPEED 1 /* Have very low speed operation */ +#elif defined(CONFIG_ARCH_CHIP_STM32U0) +# define STM32_GPIO_VERY_LOW_SPEED 1 /* Have very low speed operation */ #else # error "Unsupported STM32 M0 family" #endif diff --git a/arch/arm/src/common/stm32/hardware/stm32_pwr_v1_m0_g0.h b/arch/arm/src/common/stm32/hardware/stm32_pwr_v1_m0_g0.h index 66a345f6d82..5d95df75b42 100644 --- a/arch/arm/src/common/stm32/hardware/stm32_pwr_v1_m0_g0.h +++ b/arch/arm/src/common/stm32/hardware/stm32_pwr_v1_m0_g0.h @@ -38,6 +38,8 @@ # include "hardware/stm32g0_pwr.h" #elif defined(CONFIG_ARCH_CHIP_STM32C0) # include "hardware/stm32c0_pwr.h" +#elif defined(CONFIG_ARCH_CHIP_STM32U0) +# include "hardware/stm32u0_pwr.h" #else # error "Unsupported STM32 M0 PWR" #endif diff --git a/arch/arm/src/common/stm32/hardware/stm32_rcc.h b/arch/arm/src/common/stm32/hardware/stm32_rcc.h index 308cd4d9df9..c6b9ef5a770 100644 --- a/arch/arm/src/common/stm32/hardware/stm32_rcc.h +++ b/arch/arm/src/common/stm32/hardware/stm32_rcc.h @@ -38,6 +38,8 @@ # include "hardware/stm32g0_rcc.h" #elif defined(CONFIG_ARCH_CHIP_STM32C0) # include "hardware/stm32c0_rcc.h" +#elif defined(CONFIG_ARCH_CHIP_STM32U0) +# include "hardware/stm32u0_rcc.h" #elif defined(CONFIG_ARCH_CHIP_STM32F1) # include "hardware/stm32f10xxx_rcc.h" #elif defined(CONFIG_ARCH_CHIP_STM32F2) diff --git a/arch/arm/src/common/stm32/hardware/stm32_syscfg.h b/arch/arm/src/common/stm32/hardware/stm32_syscfg.h index 7ed634e52b2..5e308fe37f3 100644 --- a/arch/arm/src/common/stm32/hardware/stm32_syscfg.h +++ b/arch/arm/src/common/stm32/hardware/stm32_syscfg.h @@ -36,6 +36,8 @@ # include "hardware/stm32l0_syscfg.h" #elif defined(CONFIG_ARCH_CHIP_STM32G0) # include "hardware/stm32g0_syscfg.h" +#elif defined(CONFIG_ARCH_CHIP_STM32U0) +# include "hardware/stm32u0_syscfg.h" #else # error "Unsupported STM32 M0 SYSCFG" #endif diff --git a/arch/arm/src/common/stm32/stm32_adc_m0_v1.c b/arch/arm/src/common/stm32/stm32_adc_m0_v1.c index cfa4e5c8cf1..09e199b8dd3 100644 --- a/arch/arm/src/common/stm32/stm32_adc_m0_v1.c +++ b/arch/arm/src/common/stm32/stm32_adc_m0_v1.c @@ -88,21 +88,24 @@ /* Sample time default configuration */ -/* C0 and G0 support additional sample time selection 2 */ +/* C0, G0 and U0 support additional sample time selection 2 */ -#if defined(CONFIG_STM32_STM32G0) || defined(CONFIG_STM32_STM32C0) +#if defined(CONFIG_STM32_STM32G0) || defined(CONFIG_STM32_STM32C0) || \ + defined(CONFIG_STM32_STM32U0) # define ADC_HAVE_SMPR_SMP2 #endif #if defined(ADC_HAVE_DMA) || (CONFIG_STM32_ADC_MAX_SAMPLES == 1) -# if defined(CONFIG_ARCH_CHIP_STM32C0) || defined(CONFIG_ARCH_CHIP_STM32G0) +# if defined(CONFIG_ARCH_CHIP_STM32C0) || defined(CONFIG_ARCH_CHIP_STM32G0) || \ + defined(CONFIG_ARCH_CHIP_STM32U0) # define ADC_SMP1_DEFAULT ADC_SMPR_12p5 # define ADC_SMP2_DEFAULT ADC_SMPR_12p5 # else # define ADC_SMP1_DEFAULT ADC_SMPR_13p5 # endif #else /* Slow down sampling frequency */ -# if defined(CONFIG_ARCH_CHIP_STM32C0) || defined(CONFIG_ARCH_CHIP_STM32G0) +# if defined(CONFIG_ARCH_CHIP_STM32C0) || defined(CONFIG_ARCH_CHIP_STM32G0) || \ + defined(CONFIG_ARCH_CHIP_STM32U0) # define ADC_SMP1_DEFAULT ADC_SMPR_160p5 # define ADC_SMP2_DEFAULT ADC_SMPR_160p5 # else @@ -124,7 +127,8 @@ #if defined(CONFIG_STM32_STM32F0) || \ defined(CONFIG_STM32_STM32L0) || \ defined(CONFIG_STM32_STM32C0) || \ - defined(CONFIG_STM32_STM32G0) + defined(CONFIG_STM32_STM32G0) || \ + defined(CONFIG_STM32_STM32U0) # define ADC_CHANNELS_NUMBER 19 #else # error "Not supported" @@ -155,7 +159,8 @@ #define ADC_HAVE_DMACFG 1 -#if defined(CONFIG_STM32_STM32G0) || defined(CONFIG_STM32_STM32L0) +#if defined(CONFIG_STM32_STM32G0) || defined(CONFIG_STM32_STM32L0) || \ + defined(CONFIG_STM32_STM32U0) # ifndef ANIOC_SET_OVERSAMPLE # define ANIOC_SET_OVERSAMPLE _ANIOC(0x0f) # endif diff --git a/arch/arm/src/common/stm32/stm32_adc_m0_v1.h b/arch/arm/src/common/stm32/stm32_adc_m0_v1.h index 9413a2c5bc9..2ff945980b4 100644 --- a/arch/arm/src/common/stm32/stm32_adc_m0_v1.h +++ b/arch/arm/src/common/stm32/stm32_adc_m0_v1.h @@ -164,6 +164,15 @@ # define ADC1_EXTSEL_T15TRGO ADC12_CFGR1_EXTSEL_TRG4 /* TRG5 and TRG6 reserved */ # define ADC1_EXTSEL_EXTI11 ADC12_CFGR1_EXTSEL_TRG7 +#elif defined(CONFIG_STM32_STM32U0) +# define ADC1_EXTSEL_T1TRGO2 ADC12_CFGR1_EXTSEL_TRG0 +# define ADC1_EXTSEL_T1CC4 ADC12_CFGR1_EXTSEL_TRG1 +# define ADC1_EXTSEL_T2TRGO ADC12_CFGR1_EXTSEL_TRG2 +# define ADC1_EXTSEL_T3TRGO ADC12_CFGR1_EXTSEL_TRG3 +# define ADC1_EXTSEL_T15TRGO ADC12_CFGR1_EXTSEL_TRG4 +# define ADC1_EXTSEL_T6TRGO ADC12_CFGR1_EXTSEL_TRG5 + /* TRG6 reserved */ +# define ADC1_EXTSEL_EXTI11 ADC12_CFGR1_EXTSEL_TRG7 #else # error "Unrecognized STM32 M0 sub-family for ADC EXTSEL" #endif diff --git a/arch/arm/src/common/stm32/stm32_dma_m0_v1_7ch_dmamux.c b/arch/arm/src/common/stm32/stm32_dma_m0_v1_7ch_dmamux.c index 756c7031663..941b52d4e5e 100644 --- a/arch/arm/src/common/stm32/stm32_dma_m0_v1_7ch_dmamux.c +++ b/arch/arm/src/common/stm32/stm32_dma_m0_v1_7ch_dmamux.c @@ -63,7 +63,8 @@ # define DMA1_NCHAN 7 # define DMA2_NCHAN 0 # elif defined(CONFIG_STM32_STM32G0BX) || \ - defined(CONFIG_STM32_STM32G0C1) + defined(CONFIG_STM32_STM32G0C1) || \ + defined(CONFIG_STM32_STM32U0) # define DMA1_NCHAN 7 # define DMA2_NCHAN 5 # else @@ -95,7 +96,8 @@ defined(CONFIG_STM32_STM32G081) # define DMAMUX_NCHANNELS 7 #elif defined(CONFIG_STM32_STM32G0BX) || \ - defined(CONFIG_STM32_STM32G0C1) + defined(CONFIG_STM32_STM32G0C1) || \ + defined(CONFIG_STM32_STM32U0) # define DMAMUX_NCHANNELS 12 #else # error "Unknown chip for DMAMUX channel count" diff --git a/arch/arm/src/common/stm32/stm32_gpio_m0_v1.h b/arch/arm/src/common/stm32/stm32_gpio_m0_v1.h index 43990a8514a..381a26627db 100644 --- a/arch/arm/src/common/stm32/stm32_gpio_m0_v1.h +++ b/arch/arm/src/common/stm32/stm32_gpio_m0_v1.h @@ -64,7 +64,7 @@ * ---- ---- ---- ---- ---- * Inputs: MMUU .... ...X PPPP BBBB * Outputs: MMUU .... FFOV PPPP BBBB - * Alternate Functions: MMUU .AAA FFO. PPPP BBBB + * Alternate Functions: MMUU AAAA FFO. PPPP BBBB * Analog: MM.. .... .... PPPP BBBB */ @@ -102,11 +102,11 @@ * 1111 1111 1100 0000 0000 * 9876 5432 1098 7654 3210 * ---- ---- ---- ---- ---- - * .... .AAA .... .... .... + * .... AAAA .... .... .... */ -#define GPIO_AF_SHIFT (12) /* Bits 12-14: Alternate function */ -#define GPIO_AF_MASK (7 << GPIO_AF_SHIFT) +#define GPIO_AF_SHIFT (12) /* Bits 12-15: Alternate function */ +#define GPIO_AF_MASK (15 << GPIO_AF_SHIFT) # define GPIO_AF(n) ((n) << GPIO_AF_SHIFT) # define GPIO_AF0 (0 << GPIO_AF_SHIFT) # define GPIO_AF1 (1 << GPIO_AF_SHIFT) @@ -116,6 +116,14 @@ # define GPIO_AF5 (5 << GPIO_AF_SHIFT) # define GPIO_AF6 (6 << GPIO_AF_SHIFT) # define GPIO_AF7 (7 << GPIO_AF_SHIFT) +# define GPIO_AF8 (8 << GPIO_AF_SHIFT) +# define GPIO_AF9 (9 << GPIO_AF_SHIFT) +# define GPIO_AF10 (10 << GPIO_AF_SHIFT) +# define GPIO_AF11 (11 << GPIO_AF_SHIFT) +# define GPIO_AF12 (12 << GPIO_AF_SHIFT) +# define GPIO_AF13 (13 << GPIO_AF_SHIFT) +# define GPIO_AF14 (14 << GPIO_AF_SHIFT) +# define GPIO_AF15 (15 << GPIO_AF_SHIFT) /* Output/Alt function frequency selection: * diff --git a/arch/arm/src/common/stm32/stm32_hsi48_m0_v1.c b/arch/arm/src/common/stm32/stm32_hsi48_m0_v1.c index ac6162fc82b..747cc5f19dc 100644 --- a/arch/arm/src/common/stm32/stm32_hsi48_m0_v1.c +++ b/arch/arm/src/common/stm32/stm32_hsi48_m0_v1.c @@ -49,6 +49,10 @@ # define STM32_HSI48_REG STM32_RCC_CR # define STM32_HSI48ON RCC_CR_HSI48ON # define STM32_HSI48RDY RCC_CR_HSI48RDY +#elif defined(CONFIG_ARCH_CHIP_STM32U0) +# define STM32_HSI48_REG STM32_RCC_CRRCR +# define STM32_HSI48ON RCC_CRRCR_HSI48ON +# define STM32_HSI48RDY RCC_CRRCR_HSI48RDY #else # error "Unsupported STM32F0/L0 HSI48" #endif diff --git a/arch/arm/src/common/stm32/stm32_lse_m0_v1.c b/arch/arm/src/common/stm32/stm32_lse_m0_v1.c index 0e5bc4fbc3d..e2037c80405 100644 --- a/arch/arm/src/common/stm32/stm32_lse_m0_v1.c +++ b/arch/arm/src/common/stm32/stm32_lse_m0_v1.c @@ -69,7 +69,7 @@ void stm32_rcc_enablelse(void) { } -#elif defined(CONFIG_ARCH_CHIP_STM32F0) +#elif defined(CONFIG_ARCH_CHIP_STM32F0) || defined(CONFIG_ARCH_CHIP_STM32U0) /* Enable the External Low-Speed (LSE) oscillator by setting the LSEON bit * the RCC BDCR register. */ diff --git a/arch/arm/src/common/stm32/stm32_pwr.h b/arch/arm/src/common/stm32/stm32_pwr.h index f7d0ec2b909..9de201ed61e 100644 --- a/arch/arm/src/common/stm32/stm32_pwr.h +++ b/arch/arm/src/common/stm32/stm32_pwr.h @@ -211,7 +211,8 @@ void stm32_pwr_enablebreg(bool region); * ****************************************************************************/ -#if defined(CONFIG_STM32_ENERGYLITE) || defined(CONFIG_STM32_STM32G0) +#if defined(CONFIG_STM32_ENERGYLITE) || defined(CONFIG_STM32_STM32G0) || \ + defined(CONFIG_STM32_STM32U0) void stm32_pwr_setvos(uint16_t vos); #endif diff --git a/arch/arm/src/common/stm32/stm32_spi_m0_v1.c b/arch/arm/src/common/stm32/stm32_spi_m0_v1.c index 9b32cd490f5..ce9ed4b6508 100644 --- a/arch/arm/src/common/stm32/stm32_spi_m0_v1.c +++ b/arch/arm/src/common/stm32/stm32_spi_m0_v1.c @@ -132,7 +132,7 @@ #if defined(CONFIG_STM32_STM32F0) || defined(CONFIG_STM32_STM32L0) # define SPI1_PCLK_FREQUENCY STM32_PCLK2_FREQUENCY # define SPI2_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY -#elif defined(CONFIG_STM32_STM32G0) +#elif defined(CONFIG_STM32_STM32G0) || defined(CONFIG_STM32_STM32U0) # define SPI1_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY # define SPI2_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY # define SPI3_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY diff --git a/arch/arm/src/stm32u0/CMakeLists.txt b/arch/arm/src/stm32u0/CMakeLists.txt new file mode 100644 index 00000000000..53245c56d21 --- /dev/null +++ b/arch/arm/src/stm32u0/CMakeLists.txt @@ -0,0 +1,28 @@ +# ############################################################################## +# arch/arm/src/stm32u0/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS) + +list(APPEND SRCS stm32_rcc.c) + +target_sources(arch PRIVATE ${SRCS}) +add_subdirectory(${NUTTX_DIR}/arch/arm/src/common/stm32 stm32_common) diff --git a/arch/arm/src/stm32u0/Kconfig b/arch/arm/src/stm32u0/Kconfig new file mode 100644 index 00000000000..51bc15eb184 --- /dev/null +++ b/arch/arm/src/stm32u0/Kconfig @@ -0,0 +1,199 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# +comment "STM32 U0 configuration" + +if ARCH_CHIP_STM32U0 + +choice + prompt "ST STM32U0 Chip Selection" + default ARCH_CHIP_STM32U083RC + depends on ARCH_CHIP_STM32U0 + +config ARCH_CHIP_STM32U073C8 + bool "STM32U073C8" + select STM32_STM32U073 + select STM32_FLASH_CONFIG_8 + depends on ARCH_CHIP_STM32U0 + ---help--- + STM32 U0 Cortex M0+, 64 Kb FLASH, 40 Kb SRAM + +config ARCH_CHIP_STM32U073CB + bool "STM32U073CB" + select STM32_STM32U073 + select STM32_FLASH_CONFIG_B + depends on ARCH_CHIP_STM32U0 + ---help--- + STM32 U0 Cortex M0+, 128 Kb FLASH, 40 Kb SRAM + +config ARCH_CHIP_STM32U073CC + bool "STM32U073CC" + select STM32_STM32U073 + select STM32_FLASH_CONFIG_C + depends on ARCH_CHIP_STM32U0 + ---help--- + STM32 U0 Cortex M0+, 256 Kb FLASH, 40 Kb SRAM + +config ARCH_CHIP_STM32U073M8 + bool "STM32U073M8" + select STM32_STM32U073 + select STM32_FLASH_CONFIG_8 + depends on ARCH_CHIP_STM32U0 + ---help--- + STM32 U0 Cortex M0+, 64 Kb FLASH, 40 Kb SRAM + +config ARCH_CHIP_STM32U073MB + bool "STM32U073MB" + select STM32_STM32U073 + select STM32_FLASH_CONFIG_B + depends on ARCH_CHIP_STM32U0 + ---help--- + STM32 U0 Cortex M0+, 128 Kb FLASH, 40 Kb SRAM + +config ARCH_CHIP_STM32U073MC + bool "STM32U073MC" + select STM32_STM32U073 + select STM32_FLASH_CONFIG_C + depends on ARCH_CHIP_STM32U0 + ---help--- + STM32 U0 Cortex M0+, 256 Kb FLASH, 40 Kb SRAM + +config ARCH_CHIP_STM32U073R8 + bool "STM32U073R8" + select STM32_STM32U073 + select STM32_FLASH_CONFIG_8 + depends on ARCH_CHIP_STM32U0 + ---help--- + STM32 U0 Cortex M0+, 64 Kb FLASH, 40 Kb SRAM + +config ARCH_CHIP_STM32U073RB + bool "STM32U073RB" + select STM32_STM32U073 + select STM32_FLASH_CONFIG_B + depends on ARCH_CHIP_STM32U0 + ---help--- + STM32 U0 Cortex M0+, 128 Kb FLASH, 40 Kb SRAM + +config ARCH_CHIP_STM32U073RC + bool "STM32U073RC" + select STM32_STM32U073 + select STM32_FLASH_CONFIG_C + depends on ARCH_CHIP_STM32U0 + ---help--- + STM32 U0 Cortex M0+, 256 Kb FLASH, 40 Kb SRAM + +config ARCH_CHIP_STM32U083CC + bool "STM32U083CC" + select STM32_STM32U083 + select STM32_FLASH_CONFIG_C + depends on ARCH_CHIP_STM32U0 + ---help--- + STM32 U0 Cortex M0+, 256 Kb FLASH, 40 Kb SRAM + +config ARCH_CHIP_STM32U083MC + bool "STM32U083MC" + select STM32_STM32U083 + select STM32_FLASH_CONFIG_C + depends on ARCH_CHIP_STM32U0 + ---help--- + STM32 U0 Cortex M0+, 256 Kb FLASH, 40 Kb SRAM + +config ARCH_CHIP_STM32U083RC + bool "STM32U083RC" + select STM32_STM32U083 + select STM32_FLASH_CONFIG_C + depends on ARCH_CHIP_STM32U0 + ---help--- + STM32 U0 Cortex M0+, 256 Kb FLASH, 40 Kb SRAM + +endchoice + +endif + +config STM32_STM32U0 + bool + default n + select STM32_HAVE_DMA1 + select STM32_HAVE_USART1 + select STM32_HAVE_USART2 + select STM32_HAVE_I2C1 + select STM32_HAVE_I2C2 + select STM32_HAVE_I2C3 + select STM32_HAVE_SPI1 + select STM32_HAVE_SPI2 + select STM32_HAVE_DMAMUX + select STM32_HAVE_CRC + select STM32_HAVE_PWR + select STM32_HAVE_BKP + select STM32_HAVE_BKPSRAM + select STM32_HAVE_SYSCFG + select STM32_HAVE_CRS + select STM32_HAVE_HSI48 + select STM32_HAVE_LPUART1 + select STM32_HAVE_LPUART2 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM15 + select STM32_HAVE_TIM16 + select STM32_HAVE_LPTIM1 + select STM32_HAVE_LPTIM2 + select STM32_HAVE_IP_ADC_M0_V1 + select STM32_HAVE_IP_AES_M0_V1 if STM32_HAVE_AES + select STM32_HAVE_IP_COMP_M0_V1 if STM32_HAVE_COMP + select STM32_HAVE_IP_DAC_M0_V1 if STM32_HAVE_DAC1 + select STM32_HAVE_IP_DBGMCU_M0_V1 + select STM32_HAVE_IP_DMA_V1 + select STM32_HAVE_IP_DMA_V1_7CH_DMAMUX + select STM32_HAVE_IP_EXTI_V2 + select STM32_HAVE_IP_FLASH_M0_V1 + select STM32_HAVE_IP_GPIO_M0_V1 + select STM32_HAVE_IP_HSI48_M0_V1 + select STM32_HAVE_IP_I2C_M0_V1 + select STM32_HAVE_IP_PWR_G0 + select STM32_HAVE_IP_RNG_M0_V1 if STM32_HAVE_RNG + select STM32_HAVE_IP_RTCC_M0_V1 + select STM32_HAVE_IP_SPI_V2 + select STM32_HAVE_IP_TIMERS_M0_V1 + select STM32_HAVE_IP_USART_V4 + select STM32_HAVE_IP_WDG_M0_V1 + +config STM32_STM32U073 + bool + default n + select STM32_STM32U0 + select STM32_HAVE_DMA2 + select STM32_HAVE_USART3 + select STM32_HAVE_USART4 + select STM32_HAVE_LPUART3 + select STM32_HAVE_LPTIM3 + select STM32_HAVE_I2C4 + select STM32_HAVE_SPI3 + select STM32_HAVE_RNG + select STM32_HAVE_DAC1 + select STM32_HAVE_COMP1 + select STM32_HAVE_COMP2 + select STM32_HAVE_TSC + select STM32_HAVE_LCD + +config STM32_STM32U083 + bool + default n + select STM32_STM32U0 + select STM32_HAVE_DMA2 + select STM32_HAVE_USART3 + select STM32_HAVE_USART4 + select STM32_HAVE_LPUART3 + select STM32_HAVE_LPTIM3 + select STM32_HAVE_I2C4 + select STM32_HAVE_SPI3 + select STM32_HAVE_RNG + select STM32_HAVE_AES + select STM32_HAVE_DAC1 + select STM32_HAVE_COMP1 + select STM32_HAVE_COMP2 + select STM32_HAVE_TSC + select STM32_HAVE_LCD diff --git a/arch/arm/src/stm32u0/Make.defs b/arch/arm/src/stm32u0/Make.defs new file mode 100644 index 00000000000..cfb6f76bcec --- /dev/null +++ b/arch/arm/src/stm32u0/Make.defs @@ -0,0 +1,27 @@ +############################################################################ +# arch/arm/src/stm32u0/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include armv6-m/Make.defs + +CHIP_CSRCS = stm32_rcc.c + +include common/stm32/Make.defs diff --git a/arch/arm/src/stm32u0/chip.h b/arch/arm/src/stm32u0/chip.h new file mode 100644 index 00000000000..cc1af1cba2a --- /dev/null +++ b/arch/arm/src/stm32u0/chip.h @@ -0,0 +1,44 @@ +/**************************************************************************** + * arch/arm/src/stm32u0/chip.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32U0_CHIP_H +#define __ARCH_ARM_SRC_STM32U0_CHIP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include "nvic.h" + +/* Include the chip capabilities file */ + +#include + +/* Include the memory map file. + * Other chip hardware files should then include this file for the proper + * setup. + */ + +#include "hardware/stm32_memorymap.h" + +#endif /* __ARCH_ARM_SRC_STM32U0_CHIP_H */ diff --git a/arch/arm/src/stm32u0/hardware/stm32_memorymap.h b/arch/arm/src/stm32u0/hardware/stm32_memorymap.h new file mode 100644 index 00000000000..137bc0e45b0 --- /dev/null +++ b/arch/arm/src/stm32u0/hardware/stm32_memorymap.h @@ -0,0 +1,32 @@ +/**************************************************************************** + * arch/arm/src/stm32u0/hardware/stm32_memorymap.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32U0_HARDWARE_STM32_MEMORYMAP_H +#define __ARCH_ARM_SRC_STM32U0_HARDWARE_STM32_MEMORYMAP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "hardware/stm32u0_memorymap.h" + +#endif /* __ARCH_ARM_SRC_STM32U0_HARDWARE_STM32_MEMORYMAP_H */ diff --git a/arch/arm/src/stm32u0/hardware/stm32_pinmap.h b/arch/arm/src/stm32u0/hardware/stm32_pinmap.h new file mode 100644 index 00000000000..29bbf8c9f8d --- /dev/null +++ b/arch/arm/src/stm32u0/hardware/stm32_pinmap.h @@ -0,0 +1,32 @@ +/**************************************************************************** + * arch/arm/src/stm32u0/hardware/stm32_pinmap.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32U0_HARDWARE_STM32_PINMAP_H +#define __ARCH_ARM_SRC_STM32U0_HARDWARE_STM32_PINMAP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "hardware/stm32u0_pinmap.h" + +#endif /* __ARCH_ARM_SRC_STM32U0_HARDWARE_STM32_PINMAP_H */ diff --git a/arch/arm/src/stm32u0/hardware/stm32u0_dmamux.h b/arch/arm/src/stm32u0/hardware/stm32u0_dmamux.h new file mode 100644 index 00000000000..63b54e69f2f --- /dev/null +++ b/arch/arm/src/stm32u0/hardware/stm32u0_dmamux.h @@ -0,0 +1,326 @@ +/**************************************************************************** + * arch/arm/src/stm32u0/hardware/stm32u0_dmamux.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32U0_HARDWARE_STM32U0_DMAMUX_H +#define __ARCH_ARM_SRC_STM32U0_HARDWARE_STM32U0_DMAMUX_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include "chip.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* DMAMUX1 mapping **********************************************************/ + +/* Peripheral to DMAMUX request line mappings (RM0503, DMAMUX: assignment + * of multiplexer inputs to resources) + */ + +#define DMAMUX1_REQ_GEN0 1 +#define DMAMAP_DMA1_REQ_GEN0 DMAMAP_MAP(DMA1, DMAMUX1_REQ_GEN0) +#define DMAMAP_DMA2_REQ_GEN0 DMAMAP_MAP(DMA2, DMAMUX1_REQ_GEN0) +#define DMAMUX1_REQ_GEN1 2 +#define DMAMAP_DMA1_REQ_GEN1 DMAMAP_MAP(DMA1, DMAMUX1_REQ_GEN1) +#define DMAMAP_DMA2_REQ_GEN1 DMAMAP_MAP(DMA2, DMAMUX1_REQ_GEN1) +#define DMAMUX1_REQ_GEN2 3 +#define DMAMAP_DMA1_REQ_GEN2 DMAMAP_MAP(DMA1, DMAMUX1_REQ_GEN2) +#define DMAMAP_DMA2_REQ_GEN2 DMAMAP_MAP(DMA2, DMAMUX1_REQ_GEN2) +#define DMAMUX1_REQ_GEN3 4 +#define DMAMAP_DMA1_REQ_GEN3 DMAMAP_MAP(DMA1, DMAMUX1_REQ_GEN3) +#define DMAMAP_DMA2_REQ_GEN3 DMAMAP_MAP(DMA2, DMAMUX1_REQ_GEN3) +#define DMAMUX1_ADC1 5 +#define DMAMAP_DMA1_ADC1 DMAMAP_MAP(DMA1, DMAMUX1_ADC1) +#define DMAMAP_DMA2_ADC1 DMAMAP_MAP(DMA2, DMAMUX1_ADC1) +#define DMAMUX1_AES_IN 6 +#define DMAMAP_DMA1_AES_IN DMAMAP_MAP(DMA1, DMAMUX1_AES_IN) +#define DMAMAP_DMA2_AES_IN DMAMAP_MAP(DMA2, DMAMUX1_AES_IN) +#define DMAMUX1_AES_OUT 7 +#define DMAMAP_DMA1_AES_OUT DMAMAP_MAP(DMA1, DMAMUX1_AES_OUT) +#define DMAMAP_DMA2_AES_OUT DMAMAP_MAP(DMA2, DMAMUX1_AES_OUT) +#define DMAMUX1_DAC_CH1 8 +#define DMAMAP_DMA1_DAC_CH1 DMAMAP_MAP(DMA1, DMAMUX1_DAC_CH1) +#define DMAMAP_DMA2_DAC_CH1 DMAMAP_MAP(DMA2, DMAMUX1_DAC_CH1) +#define DMAMUX1_I2C1_RX 9 +#define DMAMAP_DMA1_I2C1_RX DMAMAP_MAP(DMA1, DMAMUX1_I2C1_RX) +#define DMAMAP_DMA2_I2C1_RX DMAMAP_MAP(DMA2, DMAMUX1_I2C1_RX) +#define DMAMUX1_I2C1_TX 10 +#define DMAMAP_DMA1_I2C1_TX DMAMAP_MAP(DMA1, DMAMUX1_I2C1_TX) +#define DMAMAP_DMA2_I2C1_TX DMAMAP_MAP(DMA2, DMAMUX1_I2C1_TX) +#define DMAMUX1_I2C2_RX 11 +#define DMAMAP_DMA1_I2C2_RX DMAMAP_MAP(DMA1, DMAMUX1_I2C2_RX) +#define DMAMAP_DMA2_I2C2_RX DMAMAP_MAP(DMA2, DMAMUX1_I2C2_RX) +#define DMAMUX1_I2C2_TX 12 +#define DMAMAP_DMA1_I2C2_TX DMAMAP_MAP(DMA1, DMAMUX1_I2C2_TX) +#define DMAMAP_DMA2_I2C2_TX DMAMAP_MAP(DMA2, DMAMUX1_I2C2_TX) +#define DMAMUX1_I2C3_RX 13 +#define DMAMAP_DMA1_I2C3_RX DMAMAP_MAP(DMA1, DMAMUX1_I2C3_RX) +#define DMAMAP_DMA2_I2C3_RX DMAMAP_MAP(DMA2, DMAMUX1_I2C3_RX) +#define DMAMUX1_I2C3_TX 14 +#define DMAMAP_DMA1_I2C3_TX DMAMAP_MAP(DMA1, DMAMUX1_I2C3_TX) +#define DMAMAP_DMA2_I2C3_TX DMAMAP_MAP(DMA2, DMAMUX1_I2C3_TX) +#define DMAMUX1_I2C4_RX 15 +#define DMAMAP_DMA1_I2C4_RX DMAMAP_MAP(DMA1, DMAMUX1_I2C4_RX) +#define DMAMAP_DMA2_I2C4_RX DMAMAP_MAP(DMA2, DMAMUX1_I2C4_RX) +#define DMAMUX1_I2C4_TX 16 +#define DMAMAP_DMA1_I2C4_TX DMAMAP_MAP(DMA1, DMAMUX1_I2C4_TX) +#define DMAMAP_DMA2_I2C4_TX DMAMAP_MAP(DMA2, DMAMUX1_I2C4_TX) +#define DMAMUX1_LPTIM1_IC1 17 +#define DMAMAP_DMA1_LPTIM1_IC1 DMAMAP_MAP(DMA1, DMAMUX1_LPTIM1_IC1) +#define DMAMAP_DMA2_LPTIM1_IC1 DMAMAP_MAP(DMA2, DMAMUX1_LPTIM1_IC1) +#define DMAMUX1_LPTIM1_IC2 18 +#define DMAMAP_DMA1_LPTIM1_IC2 DMAMAP_MAP(DMA1, DMAMUX1_LPTIM1_IC2) +#define DMAMAP_DMA2_LPTIM1_IC2 DMAMAP_MAP(DMA2, DMAMUX1_LPTIM1_IC2) +#define DMAMUX1_LPTIM1_IC3 19 +#define DMAMAP_DMA1_LPTIM1_IC3 DMAMAP_MAP(DMA1, DMAMUX1_LPTIM1_IC3) +#define DMAMAP_DMA2_LPTIM1_IC3 DMAMAP_MAP(DMA2, DMAMUX1_LPTIM1_IC3) +#define DMAMUX1_LPTIM1_IC4 20 +#define DMAMAP_DMA1_LPTIM1_IC4 DMAMAP_MAP(DMA1, DMAMUX1_LPTIM1_IC4) +#define DMAMAP_DMA2_LPTIM1_IC4 DMAMAP_MAP(DMA2, DMAMUX1_LPTIM1_IC4) +#define DMAMUX1_LPTIM1_UE 21 +#define DMAMAP_DMA1_LPTIM1_UE DMAMAP_MAP(DMA1, DMAMUX1_LPTIM1_UE) +#define DMAMAP_DMA2_LPTIM1_UE DMAMAP_MAP(DMA2, DMAMUX1_LPTIM1_UE) +#define DMAMUX1_LPTIM2_IC1 22 +#define DMAMAP_DMA1_LPTIM2_IC1 DMAMAP_MAP(DMA1, DMAMUX1_LPTIM2_IC1) +#define DMAMAP_DMA2_LPTIM2_IC1 DMAMAP_MAP(DMA2, DMAMUX1_LPTIM2_IC1) +#define DMAMUX1_LPTIM2_IC2 23 +#define DMAMAP_DMA1_LPTIM2_IC2 DMAMAP_MAP(DMA1, DMAMUX1_LPTIM2_IC2) +#define DMAMAP_DMA2_LPTIM2_IC2 DMAMAP_MAP(DMA2, DMAMUX1_LPTIM2_IC2) +#define DMAMUX1_LPTIM2_UE 24 +#define DMAMAP_DMA1_LPTIM2_UE DMAMAP_MAP(DMA1, DMAMUX1_LPTIM2_UE) +#define DMAMAP_DMA2_LPTIM2_UE DMAMAP_MAP(DMA2, DMAMUX1_LPTIM2_UE) +#define DMAMUX1_LPTIM3_IC1 25 +#define DMAMAP_DMA1_LPTIM3_IC1 DMAMAP_MAP(DMA1, DMAMUX1_LPTIM3_IC1) +#define DMAMAP_DMA2_LPTIM3_IC1 DMAMAP_MAP(DMA2, DMAMUX1_LPTIM3_IC1) +#define DMAMUX1_LPTIM3_IC2 26 +#define DMAMAP_DMA1_LPTIM3_IC2 DMAMAP_MAP(DMA1, DMAMUX1_LPTIM3_IC2) +#define DMAMAP_DMA2_LPTIM3_IC2 DMAMAP_MAP(DMA2, DMAMUX1_LPTIM3_IC2) +#define DMAMUX1_LPTIM3_IC3 27 +#define DMAMAP_DMA1_LPTIM3_IC3 DMAMAP_MAP(DMA1, DMAMUX1_LPTIM3_IC3) +#define DMAMAP_DMA2_LPTIM3_IC3 DMAMAP_MAP(DMA2, DMAMUX1_LPTIM3_IC3) +#define DMAMUX1_LPTIM3_IC4 28 +#define DMAMAP_DMA1_LPTIM3_IC4 DMAMAP_MAP(DMA1, DMAMUX1_LPTIM3_IC4) +#define DMAMAP_DMA2_LPTIM3_IC4 DMAMAP_MAP(DMA2, DMAMUX1_LPTIM3_IC4) +#define DMAMUX1_LPTIM3_UE 29 +#define DMAMAP_DMA1_LPTIM3_UE DMAMAP_MAP(DMA1, DMAMUX1_LPTIM3_UE) +#define DMAMAP_DMA2_LPTIM3_UE DMAMAP_MAP(DMA2, DMAMUX1_LPTIM3_UE) +#define DMAMUX1_LPUART1_RX 30 +#define DMAMAP_DMA1_LPUART1_RX DMAMAP_MAP(DMA1, DMAMUX1_LPUART1_RX) +#define DMAMAP_DMA2_LPUART1_RX DMAMAP_MAP(DMA2, DMAMUX1_LPUART1_RX) +#define DMAMUX1_LPUART1_TX 31 +#define DMAMAP_DMA1_LPUART1_TX DMAMAP_MAP(DMA1, DMAMUX1_LPUART1_TX) +#define DMAMAP_DMA2_LPUART1_TX DMAMAP_MAP(DMA2, DMAMUX1_LPUART1_TX) +#define DMAMUX1_LPUART2_RX 32 +#define DMAMAP_DMA1_LPUART2_RX DMAMAP_MAP(DMA1, DMAMUX1_LPUART2_RX) +#define DMAMAP_DMA2_LPUART2_RX DMAMAP_MAP(DMA2, DMAMUX1_LPUART2_RX) +#define DMAMUX1_LPUART2_TX 33 +#define DMAMAP_DMA1_LPUART2_TX DMAMAP_MAP(DMA1, DMAMUX1_LPUART2_TX) +#define DMAMAP_DMA2_LPUART2_TX DMAMAP_MAP(DMA2, DMAMUX1_LPUART2_TX) +#define DMAMUX1_LPUART3_RX 34 +#define DMAMAP_DMA1_LPUART3_RX DMAMAP_MAP(DMA1, DMAMUX1_LPUART3_RX) +#define DMAMAP_DMA2_LPUART3_RX DMAMAP_MAP(DMA2, DMAMUX1_LPUART3_RX) +#define DMAMUX1_LPUART3_TX 35 +#define DMAMAP_DMA1_LPUART3_TX DMAMAP_MAP(DMA1, DMAMUX1_LPUART3_TX) +#define DMAMAP_DMA2_LPUART3_TX DMAMAP_MAP(DMA2, DMAMUX1_LPUART3_TX) +#define DMAMUX1_SPI1_RX 36 +#define DMAMAP_DMA1_SPI1_RX DMAMAP_MAP(DMA1, DMAMUX1_SPI1_RX) +#define DMAMAP_DMA2_SPI1_RX DMAMAP_MAP(DMA2, DMAMUX1_SPI1_RX) +#define DMAMUX1_SPI1_TX 37 +#define DMAMAP_DMA1_SPI1_TX DMAMAP_MAP(DMA1, DMAMUX1_SPI1_TX) +#define DMAMAP_DMA2_SPI1_TX DMAMAP_MAP(DMA2, DMAMUX1_SPI1_TX) +#define DMAMUX1_SPI2_RX 38 +#define DMAMAP_DMA1_SPI2_RX DMAMAP_MAP(DMA1, DMAMUX1_SPI2_RX) +#define DMAMAP_DMA2_SPI2_RX DMAMAP_MAP(DMA2, DMAMUX1_SPI2_RX) +#define DMAMUX1_SPI2_TX 39 +#define DMAMAP_DMA1_SPI2_TX DMAMAP_MAP(DMA1, DMAMUX1_SPI2_TX) +#define DMAMAP_DMA2_SPI2_TX DMAMAP_MAP(DMA2, DMAMUX1_SPI2_TX) +#define DMAMUX1_SPI3_RX 40 +#define DMAMAP_DMA1_SPI3_RX DMAMAP_MAP(DMA1, DMAMUX1_SPI3_RX) +#define DMAMAP_DMA2_SPI3_RX DMAMAP_MAP(DMA2, DMAMUX1_SPI3_RX) +#define DMAMUX1_SPI3_TX 41 +#define DMAMAP_DMA1_SPI3_TX DMAMAP_MAP(DMA1, DMAMUX1_SPI3_TX) +#define DMAMAP_DMA2_SPI3_TX DMAMAP_MAP(DMA2, DMAMUX1_SPI3_TX) +#define DMAMUX1_TIM1_CH1 42 +#define DMAMAP_DMA1_TIM1_CH1 DMAMAP_MAP(DMA1, DMAMUX1_TIM1_CH1) +#define DMAMAP_DMA2_TIM1_CH1 DMAMAP_MAP(DMA2, DMAMUX1_TIM1_CH1) +#define DMAMUX1_TIM1_CH2 43 +#define DMAMAP_DMA1_TIM1_CH2 DMAMAP_MAP(DMA1, DMAMUX1_TIM1_CH2) +#define DMAMAP_DMA2_TIM1_CH2 DMAMAP_MAP(DMA2, DMAMUX1_TIM1_CH2) +#define DMAMUX1_TIM1_CH3 44 +#define DMAMAP_DMA1_TIM1_CH3 DMAMAP_MAP(DMA1, DMAMUX1_TIM1_CH3) +#define DMAMAP_DMA2_TIM1_CH3 DMAMAP_MAP(DMA2, DMAMUX1_TIM1_CH3) +#define DMAMUX1_TIM1_CH4 45 +#define DMAMAP_DMA1_TIM1_CH4 DMAMAP_MAP(DMA1, DMAMUX1_TIM1_CH4) +#define DMAMAP_DMA2_TIM1_CH4 DMAMAP_MAP(DMA2, DMAMUX1_TIM1_CH4) +#define DMAMUX1_TIM1_TRIG_COM 46 +#define DMAMAP_DMA1_TIM1_TRIG_COM DMAMAP_MAP(DMA1, DMAMUX1_TIM1_TRIG_COM) +#define DMAMAP_DMA2_TIM1_TRIG_COM DMAMAP_MAP(DMA2, DMAMUX1_TIM1_TRIG_COM) +#define DMAMUX1_TIM1_UP 47 +#define DMAMAP_DMA1_TIM1_UP DMAMAP_MAP(DMA1, DMAMUX1_TIM1_UP) +#define DMAMAP_DMA2_TIM1_UP DMAMAP_MAP(DMA2, DMAMUX1_TIM1_UP) +#define DMAMUX1_TIM2_CH1 48 +#define DMAMAP_DMA1_TIM2_CH1 DMAMAP_MAP(DMA1, DMAMUX1_TIM2_CH1) +#define DMAMAP_DMA2_TIM2_CH1 DMAMAP_MAP(DMA2, DMAMUX1_TIM2_CH1) +#define DMAMUX1_TIM2_CH2 49 +#define DMAMAP_DMA1_TIM2_CH2 DMAMAP_MAP(DMA1, DMAMUX1_TIM2_CH2) +#define DMAMAP_DMA2_TIM2_CH2 DMAMAP_MAP(DMA2, DMAMUX1_TIM2_CH2) +#define DMAMUX1_TIM2_CH3 50 +#define DMAMAP_DMA1_TIM2_CH3 DMAMAP_MAP(DMA1, DMAMUX1_TIM2_CH3) +#define DMAMAP_DMA2_TIM2_CH3 DMAMAP_MAP(DMA2, DMAMUX1_TIM2_CH3) +#define DMAMUX1_TIM2_CH4 51 +#define DMAMAP_DMA1_TIM2_CH4 DMAMAP_MAP(DMA1, DMAMUX1_TIM2_CH4) +#define DMAMAP_DMA2_TIM2_CH4 DMAMAP_MAP(DMA2, DMAMUX1_TIM2_CH4) +#define DMAMUX1_TIM2_TRIG 52 +#define DMAMAP_DMA1_TIM2_TRIG DMAMAP_MAP(DMA1, DMAMUX1_TIM2_TRIG) +#define DMAMAP_DMA2_TIM2_TRIG DMAMAP_MAP(DMA2, DMAMUX1_TIM2_TRIG) +#define DMAMUX1_TIM2_UP 53 +#define DMAMAP_DMA1_TIM2_UP DMAMAP_MAP(DMA1, DMAMUX1_TIM2_UP) +#define DMAMAP_DMA2_TIM2_UP DMAMAP_MAP(DMA2, DMAMUX1_TIM2_UP) +#define DMAMUX1_TIM3_CH1 54 +#define DMAMAP_DMA1_TIM3_CH1 DMAMAP_MAP(DMA1, DMAMUX1_TIM3_CH1) +#define DMAMAP_DMA2_TIM3_CH1 DMAMAP_MAP(DMA2, DMAMUX1_TIM3_CH1) +#define DMAMUX1_TIM3_CH2 55 +#define DMAMAP_DMA1_TIM3_CH2 DMAMAP_MAP(DMA1, DMAMUX1_TIM3_CH2) +#define DMAMAP_DMA2_TIM3_CH2 DMAMAP_MAP(DMA2, DMAMUX1_TIM3_CH2) +#define DMAMUX1_TIM3_CH3 56 +#define DMAMAP_DMA1_TIM3_CH3 DMAMAP_MAP(DMA1, DMAMUX1_TIM3_CH3) +#define DMAMAP_DMA2_TIM3_CH3 DMAMAP_MAP(DMA2, DMAMUX1_TIM3_CH3) +#define DMAMUX1_TIM3_CH4 57 +#define DMAMAP_DMA1_TIM3_CH4 DMAMAP_MAP(DMA1, DMAMUX1_TIM3_CH4) +#define DMAMAP_DMA2_TIM3_CH4 DMAMAP_MAP(DMA2, DMAMUX1_TIM3_CH4) +#define DMAMUX1_TIM3_TRIG 58 +#define DMAMAP_DMA1_TIM3_TRIG DMAMAP_MAP(DMA1, DMAMUX1_TIM3_TRIG) +#define DMAMAP_DMA2_TIM3_TRIG DMAMAP_MAP(DMA2, DMAMUX1_TIM3_TRIG) +#define DMAMUX1_TIM3_UP 59 +#define DMAMAP_DMA1_TIM3_UP DMAMAP_MAP(DMA1, DMAMUX1_TIM3_UP) +#define DMAMAP_DMA2_TIM3_UP DMAMAP_MAP(DMA2, DMAMUX1_TIM3_UP) +#define DMAMUX1_TIM6_UP 60 +#define DMAMAP_DMA1_TIM6_UP DMAMAP_MAP(DMA1, DMAMUX1_TIM6_UP) +#define DMAMAP_DMA2_TIM6_UP DMAMAP_MAP(DMA2, DMAMUX1_TIM6_UP) +#define DMAMUX1_TIM7_UP 61 +#define DMAMAP_DMA1_TIM7_UP DMAMAP_MAP(DMA1, DMAMUX1_TIM7_UP) +#define DMAMAP_DMA2_TIM7_UP DMAMAP_MAP(DMA2, DMAMUX1_TIM7_UP) +#define DMAMUX1_TIM15_CH1 62 +#define DMAMAP_DMA1_TIM15_CH1 DMAMAP_MAP(DMA1, DMAMUX1_TIM15_CH1) +#define DMAMAP_DMA2_TIM15_CH1 DMAMAP_MAP(DMA2, DMAMUX1_TIM15_CH1) +#define DMAMUX1_TIM15_CH2 63 +#define DMAMAP_DMA1_TIM15_CH2 DMAMAP_MAP(DMA1, DMAMUX1_TIM15_CH2) +#define DMAMAP_DMA2_TIM15_CH2 DMAMAP_MAP(DMA2, DMAMUX1_TIM15_CH2) +#define DMAMUX1_TIM15_TRIG_COM 64 +#define DMAMAP_DMA1_TIM15_TRIG_COM DMAMAP_MAP(DMA1, DMAMUX1_TIM15_TRIG_COM) +#define DMAMAP_DMA2_TIM15_TRIG_COM DMAMAP_MAP(DMA2, DMAMUX1_TIM15_TRIG_COM) +#define DMAMUX1_TIM15_UP 65 +#define DMAMAP_DMA1_TIM15_UP DMAMAP_MAP(DMA1, DMAMUX1_TIM15_UP) +#define DMAMAP_DMA2_TIM15_UP DMAMAP_MAP(DMA2, DMAMUX1_TIM15_UP) +#define DMAMUX1_TIM16_CH1 66 +#define DMAMAP_DMA1_TIM16_CH1 DMAMAP_MAP(DMA1, DMAMUX1_TIM16_CH1) +#define DMAMAP_DMA2_TIM16_CH1 DMAMAP_MAP(DMA2, DMAMUX1_TIM16_CH1) +#define DMAMUX1_TIM16_COM 67 +#define DMAMAP_DMA1_TIM16_COM DMAMAP_MAP(DMA1, DMAMUX1_TIM16_COM) +#define DMAMAP_DMA2_TIM16_COM DMAMAP_MAP(DMA2, DMAMUX1_TIM16_COM) +#define DMAMUX1_TIM16_UP 68 +#define DMAMAP_DMA1_TIM16_UP DMAMAP_MAP(DMA1, DMAMUX1_TIM16_UP) +#define DMAMAP_DMA2_TIM16_UP DMAMAP_MAP(DMA2, DMAMUX1_TIM16_UP) +#define DMAMUX1_USART1_RX 69 +#define DMAMAP_DMA1_USART1_RX DMAMAP_MAP(DMA1, DMAMUX1_USART1_RX) +#define DMAMAP_DMA2_USART1_RX DMAMAP_MAP(DMA2, DMAMUX1_USART1_RX) +#define DMAMUX1_USART1_TX 70 +#define DMAMAP_DMA1_USART1_TX DMAMAP_MAP(DMA1, DMAMUX1_USART1_TX) +#define DMAMAP_DMA2_USART1_TX DMAMAP_MAP(DMA2, DMAMUX1_USART1_TX) +#define DMAMUX1_USART2_RX 71 +#define DMAMAP_DMA1_USART2_RX DMAMAP_MAP(DMA1, DMAMUX1_USART2_RX) +#define DMAMAP_DMA2_USART2_RX DMAMAP_MAP(DMA2, DMAMUX1_USART2_RX) +#define DMAMUX1_USART2_TX 72 +#define DMAMAP_DMA1_USART2_TX DMAMAP_MAP(DMA1, DMAMUX1_USART2_TX) +#define DMAMAP_DMA2_USART2_TX DMAMAP_MAP(DMA2, DMAMUX1_USART2_TX) +#define DMAMUX1_USART3_RX 73 +#define DMAMAP_DMA1_USART3_RX DMAMAP_MAP(DMA1, DMAMUX1_USART3_RX) +#define DMAMAP_DMA2_USART3_RX DMAMAP_MAP(DMA2, DMAMUX1_USART3_RX) +#define DMAMUX1_USART3_TX 74 +#define DMAMAP_DMA1_USART3_TX DMAMAP_MAP(DMA1, DMAMUX1_USART3_TX) +#define DMAMAP_DMA2_USART3_TX DMAMAP_MAP(DMA2, DMAMUX1_USART3_TX) +#define DMAMUX1_USART4_RX 75 +#define DMAMAP_DMA1_USART4_RX DMAMAP_MAP(DMA1, DMAMUX1_USART4_RX) +#define DMAMAP_DMA2_USART4_RX DMAMAP_MAP(DMA2, DMAMUX1_USART4_RX) +#define DMAMUX1_USART4_TX 76 +#define DMAMAP_DMA1_USART4_TX DMAMAP_MAP(DMA1, DMAMUX1_USART4_TX) +#define DMAMAP_DMA2_USART4_TX DMAMAP_MAP(DMA2, DMAMUX1_USART4_TX) + +/* DMAMUX trigger input sources (RM0503, DMAMUX: trigger inputs) */ + +#define DMAMUX_TRIG_EXTI0 0 +#define DMAMUX_TRIG_EXTI1 1 +#define DMAMUX_TRIG_EXTI2 2 +#define DMAMUX_TRIG_EXTI3 3 +#define DMAMUX_TRIG_EXTI4 4 +#define DMAMUX_TRIG_EXTI5 5 +#define DMAMUX_TRIG_EXTI6 6 +#define DMAMUX_TRIG_EXTI7 7 +#define DMAMUX_TRIG_EXTI8 8 +#define DMAMUX_TRIG_EXTI9 9 +#define DMAMUX_TRIG_EXTI10 10 +#define DMAMUX_TRIG_EXTI11 11 +#define DMAMUX_TRIG_EXTI12 12 +#define DMAMUX_TRIG_EXTI13 13 +#define DMAMUX_TRIG_EXTI14 14 +#define DMAMUX_TRIG_EXTI15 15 +#define DMAMUX_TRIG_EVT0 16 +#define DMAMUX_TRIG_EVT1 17 +#define DMAMUX_TRIG_EVT2 18 +#define DMAMUX_TRIG_EVT3 19 +#define DMAMUX_TRIG_LPTIM1_OUT 20 +#define DMAMUX_TRIG_LPTIM2_OUT 21 +#define DMAMUX_TRIG_LPTIM3_OUT 22 + +/* Sync inputs use the same values as trigger inputs (RM0503, DMAMUX: + * synchronization inputs) + */ + +#define DMAMUX_SYNC_EXTI0 0 +#define DMAMUX_SYNC_EXTI1 1 +#define DMAMUX_SYNC_EXTI2 2 +#define DMAMUX_SYNC_EXTI3 3 +#define DMAMUX_SYNC_EXTI4 4 +#define DMAMUX_SYNC_EXTI5 5 +#define DMAMUX_SYNC_EXTI6 6 +#define DMAMUX_SYNC_EXTI7 7 +#define DMAMUX_SYNC_EXTI8 8 +#define DMAMUX_SYNC_EXTI9 9 +#define DMAMUX_SYNC_EXTI10 10 +#define DMAMUX_SYNC_EXTI11 11 +#define DMAMUX_SYNC_EXTI12 12 +#define DMAMUX_SYNC_EXTI13 13 +#define DMAMUX_SYNC_EXTI14 14 +#define DMAMUX_SYNC_EXTI15 15 +#define DMAMUX_SYNC_EVT0 16 +#define DMAMUX_SYNC_EVT1 17 +#define DMAMUX_SYNC_EVT2 18 +#define DMAMUX_SYNC_EVT3 19 +#define DMAMUX_SYNC_LPTIM1_OUT 20 +#define DMAMUX_SYNC_LPTIM2_OUT 21 +#define DMAMUX_SYNC_LPTIM3_OUT 22 + +#endif /* __ARCH_ARM_SRC_STM32U0_HARDWARE_STM32U0_DMAMUX_H */ diff --git a/arch/arm/src/stm32u0/hardware/stm32u0_exti.h b/arch/arm/src/stm32u0/hardware/stm32u0_exti.h new file mode 100644 index 00000000000..40cab0c1a61 --- /dev/null +++ b/arch/arm/src/stm32u0/hardware/stm32u0_exti.h @@ -0,0 +1,85 @@ +/**************************************************************************** + * arch/arm/src/stm32u0/hardware/stm32u0_exti.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32U0_HARDWARE_STM32U0_EXTI_H +#define __ARCH_ARM_SRC_STM32U0_HARDWARE_STM32U0_EXTI_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include "chip.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define STM32_NEXTI 22 +#define STM32_EXTI_MASK 0x003fffff +#define STM32_EXTI_BIT(n) (1 << (n)) + +/* Register Offsets *********************************************************/ + +#define STM32_EXTI_RTSR1_OFFSET 0x0000 /* Rising trigger selection 1 */ +#define STM32_EXTI_FTSR1_OFFSET 0x0004 /* Falling trigger selection 1 */ +#define STM32_EXTI_SWIER1_OFFSET 0x0008 /* Software interrupt event 1 */ +#define STM32_EXTI_RPR1_OFFSET 0x000c /* Rising edge pending 1 */ +#define STM32_EXTI_FPR1_OFFSET 0x0010 /* Falling edge pending 1 */ +#define STM32_EXTI_EXTICR_OFFSET(p) (0x0060 + ((p) & 0x000c)) /* Registers are displaced by 4! */ +#define STM32_EXTI_EXTICR1_OFFSET 0x0060 /* Interrupt selection 1 */ +#define STM32_EXTI_EXTICR2_OFFSET 0x0064 /* Interrupt selection 2 */ +#define STM32_EXTI_EXTICR3_OFFSET 0x0068 /* Interrupt selection 3 */ +#define STM32_EXTI_EXTICR4_OFFSET 0x006c /* Interrupt selection 4 */ +#define STM32_EXTI_IMR1_OFFSET 0x0080 /* Interrupt mask 1 */ +#define STM32_EXTI_EMR1_OFFSET 0x0084 /* Event mask 1 */ +#define STM32_EXTI_IMR2_OFFSET 0x0090 /* Interrupt mask 2 */ +#define STM32_EXTI_EMR2_OFFSET 0x0094 /* Event mask 2 */ + +/* Register Addresses *******************************************************/ + +#define STM32_EXTI_RTSR1 (STM32_EXTI_BASE+STM32_EXTI_RTSR1_OFFSET) +#define STM32_EXTI_FTSR1 (STM32_EXTI_BASE+STM32_EXTI_FTSR1_OFFSET) +#define STM32_EXTI_SWIER1 (STM32_EXTI_BASE+STM32_EXTI_SWIER1_OFFSET) +#define STM32_EXTI_RPR1 (STM32_EXTI_BASE+STM32_EXTI_RPR1_OFFSET) +#define STM32_EXTI_FPR1 (STM32_EXTI_BASE+STM32_EXTI_FPR1_OFFSET) +#define STM32_EXTI_EXTICR(p) (STM32_EXTI_BASE+STM32_EXTI_EXTICR_OFFSET(p)) +#define STM32_EXTI_IMR1 (STM32_EXTI_BASE+STM32_EXTI_IMR1_OFFSET) +#define STM32_EXTI_EMR1 (STM32_EXTI_BASE+STM32_EXTI_EMR1_OFFSET) +#define STM32_EXTI_IMR2 (STM32_EXTI_BASE+STM32_EXTI_IMR2_OFFSET) +#define STM32_EXTI_EMR2 (STM32_EXTI_BASE+STM32_EXTI_EMR2_OFFSET) + +/* Register Bitfield Definitions ********************************************/ + +/* EXTI external interrupt configuration register 1-4 */ + +#define EXTI_EXTICR_PORTA (0) /* 0000: PA[x] pin */ +#define EXTI_EXTICR_PORTB (1) /* 0001: PB[x] pin */ +#define EXTI_EXTICR_PORTC (2) /* 0010: PC[x] pin */ +#define EXTI_EXTICR_PORTD (3) /* 0011: PD[x] pin */ +#define EXTI_EXTICR_PORTE (4) /* 0100: PE[x] pin */ +#define EXTI_EXTICR_PORTF (5) /* 0101: PF[x] pin */ +#define EXTI_EXTICR_PORT_MASK (0xff) +#define EXTI_EXTICR_EXTI_SHIFT(g) (((g) & 3) << 3) +#define EXTI_EXTICR_EXTI_MASK(g) (EXTI_EXTICR_PORT_MASK <<(EXTI_EXTICR_EXTI_SHIFT(g))) + +#endif /* __ARCH_ARM_SRC_STM32U0_HARDWARE_STM32U0_EXTI_H */ diff --git a/arch/arm/src/stm32u0/hardware/stm32u0_flash.h b/arch/arm/src/stm32u0/hardware/stm32u0_flash.h new file mode 100644 index 00000000000..5d26e068822 --- /dev/null +++ b/arch/arm/src/stm32u0/hardware/stm32u0_flash.h @@ -0,0 +1,238 @@ +/**************************************************************************** + * arch/arm/src/stm32u0/hardware/stm32u0_flash.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32U0_HARDWARE_STM32U0_FLASH_H +#define __ARCH_ARM_SRC_STM32U0_HARDWARE_STM32U0_FLASH_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include "chip.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register Offsets *********************************************************/ + +#define STM32_FLASH_ACR_OFFSET 0x0000 /* Access control register */ +#define STM32_FLASH_KEYR_OFFSET 0x0008 /* Key register */ +#define STM32_FLASH_OPTKEYR_OFFSET 0x000c /* Option key register */ +#define STM32_FLASH_SR_OFFSET 0x0010 /* Status register */ +#define STM32_FLASH_CR_OFFSET 0x0014 /* Control register */ +#define STM32_FLASH_ECCR_OFFSET 0x0018 /* ECC register */ +#define STM32_FLASH_OPTR_OFFSET 0x0020 /* Option register */ +#define STM32_FLASH_WRP1AR_OFFSET 0x002c /* WRP area A address reg */ +#define STM32_FLASH_WRP1BR_OFFSET 0x0030 /* WRP area B address reg */ +#define STM32_FLASH_SECR_OFFSET 0x0080 /* Security register */ +#define STM32_FLASH_OEM1KEYW0R_OFFSET 0x0088 /* OEM1 key register 1 */ +#define STM32_FLASH_OEM1KEYW1R_OFFSET 0x008c /* OEM1 key register 2 */ +#define STM32_FLASH_OEM1KEYW2R_OFFSET 0x0090 /* OEM1 key register 3 */ +#define STM32_FLASH_OEM1KEYW3R_OFFSET 0x0094 /* OEM1 key register 4 */ +#define STM32_FLASH_OEM2KEYW0R_OFFSET 0x0098 /* OEM2 key register 1 */ +#define STM32_FLASH_OEM2KEYW1R_OFFSET 0x009c /* OEM2 key register 2 */ +#define STM32_FLASH_OEM2KEYW2R_OFFSET 0x00a0 /* OEM2 key register 3 */ +#define STM32_FLASH_OEM2KEYW3R_OFFSET 0x00a4 /* OEM2 key register 4 */ +#define STM32_FLASH_OEMKEYSR_OFFSET 0x00a8 /* OEM key status register */ +#define STM32_FLASH_HDPCR_OFFSET 0x00ac /* HDP control register */ +#define STM32_FLASH_HDPEXTR_OFFSET 0x00b0 /* HDP extension register */ + +/* Register Addresses *******************************************************/ + +#define STM32_FLASH_ACR (STM32_FLASHIF_BASE+STM32_FLASH_ACR_OFFSET) +#define STM32_FLASH_KEYR (STM32_FLASHIF_BASE+STM32_FLASH_KEYR_OFFSET) +#define STM32_FLASH_OPTKEYR (STM32_FLASHIF_BASE+STM32_FLASH_OPTKEYR_OFFSET) +#define STM32_FLASH_SR (STM32_FLASHIF_BASE+STM32_FLASH_SR_OFFSET) +#define STM32_FLASH_CR (STM32_FLASHIF_BASE+STM32_FLASH_CR_OFFSET) +#define STM32_FLASH_ECCR (STM32_FLASHIF_BASE+STM32_FLASH_ECCR_OFFSET) +#define STM32_FLASH_OPTR (STM32_FLASHIF_BASE+STM32_FLASH_OPTR_OFFSET) +#define STM32_FLASH_WRP1AR (STM32_FLASHIF_BASE+STM32_FLASH_WRP1AR_OFFSET) +#define STM32_FLASH_WRP1BR (STM32_FLASHIF_BASE+STM32_FLASH_WRP1BR_OFFSET) +#define STM32_FLASH_SECR (STM32_FLASHIF_BASE+STM32_FLASH_SECR_OFFSET) +#define STM32_FLASH_OEM1KEYW0R (STM32_FLASHIF_BASE+STM32_FLASH_OEM1KEYW0R_OFFSET) +#define STM32_FLASH_OEM1KEYW1R (STM32_FLASHIF_BASE+STM32_FLASH_OEM1KEYW1R_OFFSET) +#define STM32_FLASH_OEM1KEYW2R (STM32_FLASHIF_BASE+STM32_FLASH_OEM1KEYW2R_OFFSET) +#define STM32_FLASH_OEM1KEYW3R (STM32_FLASHIF_BASE+STM32_FLASH_OEM1KEYW3R_OFFSET) +#define STM32_FLASH_OEM2KEYW0R (STM32_FLASHIF_BASE+STM32_FLASH_OEM2KEYW0R_OFFSET) +#define STM32_FLASH_OEM2KEYW1R (STM32_FLASHIF_BASE+STM32_FLASH_OEM2KEYW1R_OFFSET) +#define STM32_FLASH_OEM2KEYW2R (STM32_FLASHIF_BASE+STM32_FLASH_OEM2KEYW2R_OFFSET) +#define STM32_FLASH_OEM2KEYW3R (STM32_FLASHIF_BASE+STM32_FLASH_OEM2KEYW3R_OFFSET) +#define STM32_FLASH_OEMKEYSR (STM32_FLASHIF_BASE+STM32_FLASH_OEMKEYSR_OFFSET) +#define STM32_FLASH_HDPCR (STM32_FLASHIF_BASE+STM32_FLASH_HDPCR_OFFSET) +#define STM32_FLASH_HDPEXTR (STM32_FLASHIF_BASE+STM32_FLASH_HDPEXTR_OFFSET) + +/* Register Bitfield Definitions ********************************************/ + +/* Flash Access Control Register (ACR) */ + +#define FLASH_ACR_LATENCY_SHIFT (0) /* Bits 0-2: Flash memory access latency */ +#define FLASH_ACR_LATENCY_MASK (7 << FLASH_ACR_LATENCY_SHIFT) +# define FLASH_ACR_LATENCY(n) ((n) << FLASH_ACR_LATENCY_SHIFT) +# define FLASH_ACR_LATENCY_0 (0 << FLASH_ACR_LATENCY_SHIFT) /* 000: Zero wait states */ +# define FLASH_ACR_LATENCY_1 (1 << FLASH_ACR_LATENCY_SHIFT) /* 001: One wait state */ +# define FLASH_ACR_LATENCY_2 (2 << FLASH_ACR_LATENCY_SHIFT) /* 010: Two wait states */ + /* Bits 3-7: Reserved */ +#define FLASH_ACR_PRFTEN (1 << 8) /* Bit 8: Prefetch enable */ +#define FLASH_ACR_ICEN (1 << 9) /* Bit 9: Instruction cache enable */ + /* Bit 10: Reserved */ +#define FLASH_ACR_ICRST (1 << 11) /* Bit 11: Instruction cache reset */ + /* Bits 12-15: Reserved */ +#define FLASH_ACR_EMPTY (1 << 16) /* Bit 16: Main Flash memory area empty */ + /* Bit 17: Reserved */ +#define FLASH_ACR_DBGSWEN (1 << 18) /* Bit 18: Debug access software enable */ + /* Bits 19-31: Reserved */ + +/* Flash Status Register (SR) */ + +#define FLASH_SR_EOP (1 << 0) /* Bit 0: End of operation */ +#define FLASH_SR_OPERR (1 << 1) /* Bit 1: Operation error */ + /* Bit 2: Reserved */ +#define FLASH_SR_PROGERR (1 << 3) /* Bit 3: Programming error */ +#define FLASH_SR_WRPERR (1 << 4) /* Bit 4: Write protection error */ +#define FLASH_SR_PGAERR (1 << 5) /* Bit 5: Programming alignment error */ +#define FLASH_SR_SIZERR (1 << 6) /* Bit 6: Size error */ +#define FLASH_SR_PGSERR (1 << 7) /* Bit 7: Programming sequence error */ +#define FLASH_SR_MISSERR (1 << 8) /* Bit 8: Fast programming data miss error */ +#define FLASH_SR_FASTERR (1 << 9) /* Bit 9: Fast programming error */ + /* Bit 10: Reserved */ +#define FLASH_SR_HDPOPTWERR (1 << 11) /* Bit 11: HDP option bytes write error */ +#define FLASH_SR_OEMOPTWERR (1 << 12) /* Bit 12: OEM option bytes write error */ + /* Bits 13-14: Reserved */ +#define FLASH_SR_OPTVERR (1 << 15) /* Bit 15: Option validity error */ +#define FLASH_SR_BSY1 (1 << 16) /* Bit 16: Busy */ + /* Bit 17: Reserved */ +#define FLASH_SR_CFGBSY (1 << 18) /* Bit 18: Programming or erase configuration busy */ + /* Bit 19: Reserved */ +#define FLASH_SR_OEM1LOCK (1 << 20) /* Bit 20: OEM1 lock */ +#define FLASH_SR_OEM2LOCK (1 << 21) /* Bit 21: OEM2 lock */ + /* Bits 22-31: Reserved */ + +/* Flash Control Register (CR) */ + +#define FLASH_CR_PG (1 << 0) /* Bit 0: Programming enable */ +#define FLASH_CR_PER (1 << 1) /* Bit 1: Page erase enable */ +#define FLASH_CR_MER1 (1 << 2) /* Bit 2: Mass erase */ +#define FLASH_CR_PNB_SHIFT (3) /* Bits 3-9: Page number */ +#define FLASH_CR_PNB_MASK (0x7f << FLASH_CR_PNB_SHIFT) +# define FLASH_CR_PNB(n) ((n) << FLASH_CR_PNB_SHIFT) + /* Bits 10-15: Reserved */ +#define FLASH_CR_STRT (1 << 16) /* Bit 16: Start erase operation */ +#define FLASH_CR_OPTSTRT (1 << 17) /* Bit 17: Start of modification of option bytes */ +#define FLASH_CR_FSTPG (1 << 18) /* Bit 18: Fast programming enable */ + /* Bits 19-23: Reserved */ +#define FLASH_CR_EOPIE (1 << 24) /* Bit 24: End-of-operation interrupt enable */ +#define FLASH_CR_ERRIE (1 << 25) /* Bit 25: Error interrupt enable */ + /* Bit 26: Reserved */ +#define FLASH_CR_OBL_LAUNCH (1 << 27) /* Bit 27: Option byte load launch */ + /* Bits 28-29: Reserved */ +#define FLASH_CR_OPTLOCK (1 << 30) /* Bit 30: Options lock */ +#define FLASH_CR_LOCK (1 << 31) /* Bit 31: FLASH_CR lock */ + +/* Flash ECC register (ECCR) */ + +#define FLASH_ECCR_ADDR_ECC_SHIFT (0) /* Bits 0-13: ECC fail double-word address offset */ +#define FLASH_ECCR_ADDR_ECC_MASK (0x3fff << FLASH_ECCR_ADDR_ECC_SHIFT) + /* Bits 14-19: Reserved */ +#define FLASH_ECCR_SYSF_ECC (1 << 20) /* Bit 20: System flash memory ECC fail */ + /* Bits 21-23: Reserved */ +#define FLASH_ECCR_ECCCIE (1 << 24) /* Bit 24: ECC correction interrupt enable */ + /* Bits 25-29: Reserved */ +#define FLASH_ECCR_ECCC (1 << 30) /* Bit 30: ECC correction */ +#define FLASH_ECCR_ECCD (1 << 31) /* Bit 31: ECC detection */ + +/* Flash Option Register (OPTR) */ + +#define FLASH_OPTR_RDP_SHIFT (0) /* Bits 0-7: Read protection level */ +#define FLASH_OPTR_RDP_MASK (0xff << FLASH_OPTR_RDP_SHIFT) +#define FLASH_OPTR_BOR_EN (1 << 8) /* Bit 8: BOR enable */ +#define FLASH_OPTR_BOR_LEV_SHIFT (9) /* Bits 9-10: BOR threshold */ +#define FLASH_OPTR_BOR_LEV_MASK (3 << FLASH_OPTR_BOR_LEV_SHIFT) + /* Bits 11-12: Reserved */ +#define FLASH_OPTR_NRST_STOP (1 << 13) /* Bit 13: Reset in Stop */ +#define FLASH_OPTR_NRST_STDBY (1 << 14) /* Bit 14: Reset in Standby */ +#define FLASH_OPTR_NRST_SHDW (1 << 15) /* Bit 15: Reset in Shutdown */ +#define FLASH_OPTR_IWDG_SW (1 << 16) /* Bit 16: Independent watchdog selection */ +#define FLASH_OPTR_IWDG_STOP (1 << 17) /* Bit 17: IWDG counter freeze in Stop mode */ +#define FLASH_OPTR_IWDG_STDBY (1 << 18) /* Bit 18: IWDG counter freeze in Standby mode */ +#define FLASH_OPTR_WWDG_SW (1 << 19) /* Bit 19: Window watchdog selection */ + /* Bit 20: Reserved */ +#define FLASH_OPTR_BDRST (1 << 21) /* Bit 21: Backup domain reset */ +#define FLASH_OPTR_RAM_PARITY_CHECK (1 << 22) /* Bit 22: SRAM parity check control */ +#define FLASH_OPTR_BKPSRAM_HW_ERASE (1 << 23) /* Bit 23: Backup SRAM erase on tamper detection */ +#define FLASH_OPTR_NBOOT_SEL (1 << 24) /* Bit 24: Boot0 selection */ +#define FLASH_OPTR_NBOOT1 (1 << 25) /* Bit 25: Boot1 config */ +#define FLASH_OPTR_NBOOT0 (1 << 26) /* Bit 26: Boot0 option bit */ +#define FLASH_OPTR_NRST_MODE_SHIFT (27) /* Bits 27-28: NRST mode */ +#define FLASH_OPTR_NRST_MODE_MASK (3 << FLASH_OPTR_NRST_MODE_SHIFT) +#define FLASH_OPTR_IRHEN (1 << 29) /* Bit 29: Internal reset holder enable */ + +/* Flash WRP area A address register (WRP1AR) */ + +#define FLASH_WRP1AR_WRP1A_STRT_SHIFT (0) /* Bits 0-15: Area A start */ +#define FLASH_WRP1AR_WRP1A_STRT_MASK (0xffff << FLASH_WRP1AR_WRP1A_STRT_SHIFT) +#define FLASH_WRP1AR_WRP1A_END_SHIFT (16) /* Bits 16-31: Area A end */ +#define FLASH_WRP1AR_WRP1A_END_MASK (0xffff << FLASH_WRP1AR_WRP1A_END_SHIFT) + +/* Flash WRP area B address register (WRP1BR) */ + +#define FLASH_WRP1BR_WRP1B_STRT_SHIFT (0) /* Bits 0-15: Area B start */ +#define FLASH_WRP1BR_WRP1B_STRT_MASK (0xffff << FLASH_WRP1BR_WRP1B_STRT_SHIFT) +#define FLASH_WRP1BR_WRP1B_END_SHIFT (16) /* Bits 16-31: Area B end */ +#define FLASH_WRP1BR_WRP1B_END_MASK (0xffff << FLASH_WRP1BR_WRP1B_END_SHIFT) + +/* Flash Security register (SECR) */ + +#define FLASH_SECR_HDP1_PEND_SHIFT (0) /* Bits 0-5: HDP1 area end page */ +#define FLASH_SECR_HDP1_PEND_MASK (0x3f << FLASH_SECR_HDP1_PEND_SHIFT) + /* Bits 6-15: Reserved */ +#define FLASH_SECR_BOOT_LOCK (1 << 16) /* Bit 16: Force boot from user area */ + /* Bits 17-23: Reserved */ +#define FLASH_SECR_HDP1EN_SHIFT (24) /* Bits 24-31: HDP1 area enable */ +#define FLASH_SECR_HDP1EN_MASK (0xff << FLASH_SECR_HDP1EN_SHIFT) + +/* Flash OEM key status register (OEMKEYSR) */ + +#define FLASH_OEMKEYSR_OEM1KEYCRC_SHIFT (0) /* Bits 0-7: OEM1 key CRC */ +#define FLASH_OEMKEYSR_OEM1KEYCRC_MASK (0xff << FLASH_OEMKEYSR_OEM1KEYCRC_SHIFT) + /* Bits 8-15: Reserved */ +#define FLASH_OEMKEYSR_OEM2KEYCRC_SHIFT (16) /* Bits 16-23: OEM2 key CRC */ +#define FLASH_OEMKEYSR_OEM2KEYCRC_MASK (0xff << FLASH_OEMKEYSR_OEM2KEYCRC_SHIFT) + /* Bits 24-31: Reserved */ + +/* Flash HDP control register (HDPCR) */ + +#define FLASH_HDPCR_HDP1_ACCDIS_SHIFT (0) /* Bits 0-7: HDP1 access disable */ +#define FLASH_HDPCR_HDP1_ACCDIS_MASK (0xff << FLASH_HDPCR_HDP1_ACCDIS_SHIFT) + /* Bits 8-15: Reserved */ +#define FLASH_HDPCR_HDP1EXT_ACCDIS_SHIFT (16) /* Bits 16-23: HDP1 extension access disable */ +#define FLASH_HDPCR_HDP1EXT_ACCDIS_MASK (0xff << FLASH_HDPCR_HDP1EXT_ACCDIS_SHIFT) + /* Bits 24-31: Reserved */ + +/* Flash HDP extension register (HDPEXTR) */ + +#define FLASH_HDPEXTR_HDP1_EXT_SHIFT (0) /* Bits 0-5: HDP1 extension area size */ +#define FLASH_HDPEXTR_HDP1_EXT_MASK (0x3f << FLASH_HDPEXTR_HDP1_EXT_SHIFT) + /* Bits 6-31: Reserved */ + +#endif /* __ARCH_ARM_SRC_STM32U0_HARDWARE_STM32U0_FLASH_H */ diff --git a/arch/arm/src/stm32u0/hardware/stm32u0_memorymap.h b/arch/arm/src/stm32u0/hardware/stm32u0_memorymap.h new file mode 100644 index 00000000000..fc9fc254ad0 --- /dev/null +++ b/arch/arm/src/stm32u0/hardware/stm32u0_memorymap.h @@ -0,0 +1,144 @@ +/**************************************************************************** + * arch/arm/src/stm32u0/hardware/stm32u0_memorymap.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32U0_HARDWARE_STM32U0_MEMORYMAP_H +#define __ARCH_ARM_SRC_STM32U0_HARDWARE_STM32U0_MEMORYMAP_H + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* STM32U0 Address Blocks ***************************************************/ + +#define STM32_CODE_BASE 0x00000000 /* 0x00000000-0x1fffffff: 512Mb code block */ +#define STM32_SRAM_BASE 0x20000000 /* 0x20000000-0x3fffffff: 512Mb sram block */ +#define STM32_PERIPH_BASE 0x40000000 /* 0x40000000-0x5fffffff: 512Mb peripheral block */ + /* 0x60000000-0xdfffffff: Reserved */ +#define STM32_CORTEX_BASE 0xe0000000 /* 0xe0000000-0xffffffff: 512Mb Cortex-M0+ block */ + +#define STM32_REGION_MASK 0xf0000000 +#define STM32_IS_SRAM(a) ((((uint32_t)(a)) & STM32_REGION_MASK) == STM32_SRAM_BASE) + +/* Code Base Addresses ******************************************************/ + +#define STM32_BOOT_BASE 0x00000000 /* 0x00000000-0x0003ffff: Aliased boot memory */ + /* 0x00040000-0x07ffffff: Reserved */ +#define STM32_FLASH_BASE 0x08000000 /* 0x08000000-0x0803ffff: FLASH memory */ + /* 0x08040000-0x1ffeffff: Reserved */ +#define STM32_SYSMEM_BASE 0x1fff0000 /* 0x1fff0000-0x1fff67ff: System memory */ +#define STM32_OTP_BASE 0x1fff6800 /* 0x1fff6800-0x1fff6bff: OTP memory */ +#define STM32_PACKAGE_BASE 0x1fff6d00 /* 0x1fff6d00: Package data register */ + +/* SRAM Base Addresses ******************************************************/ + +#define STM32_SRAM1_BASE 0x20000000 /* 0x20000000-0x20007fff: 32Kb SRAM1 */ +#define STM32_BKPSRAM2_BASE 0x20008000 /* 0x20008000-0x20009fff: 8Kb backup SRAM2 */ + +/* Peripheral Base Addresses ************************************************/ + +#define STM32_APB1_BASE 0x40000000 /* 0x40000000-0x4000bfff: APB */ +#define STM32_APB2_BASE 0x40010000 /* 0x40010000-0x40015bff: APB */ +#define STM32_AHB_BASE 0x40020000 /* 0x40020000-0x400263ff: AHB */ + /* 0x40026400-0x4fffffff: Reserved */ +#define STM32_IOPORT_BASE 0x50000000 /* 0x50000000-0x500017ff: IOPORT */ + +/* APB Base Addresses *******************************************************/ + +#define STM32_TIM2_BASE 0x40000000 /* 0x40000000-0x400003ff TIM2 */ +#define STM32_TIM3_BASE 0x40000400 /* 0x40000400-0x400007ff TIM3 */ +#define STM32_TIM6_BASE 0x40001000 /* 0x40001000-0x400013ff TIM6 */ +#define STM32_TIM7_BASE 0x40001400 /* 0x40001400-0x400017ff TIM7 */ +#define STM32_LCD_BASE 0x40002400 /* 0x40002400-0x400027ff LCD */ +#define STM32_RTC_BASE 0x40002800 /* 0x40002800-0x40002bff RTC */ +#define STM32_WWDG_BASE 0x40002c00 /* 0x40002c00-0x40002fff WWDG */ +#define STM32_IWDG_BASE 0x40003000 /* 0x40003000-0x400033ff IWDG */ +#define STM32_SPI2_BASE 0x40003800 /* 0x40003800-0x40003bff SPI2 */ +#define STM32_SPI3_BASE 0x40003c00 /* 0x40003c00-0x40003fff SPI3 */ +#define STM32_USART2_BASE 0x40004400 /* 0x40004400-0x400047ff USART2 */ +#define STM32_USART3_BASE 0x40004800 /* 0x40004800-0x40004bff USART3 */ +#define STM32_USART4_BASE 0x40004c00 /* 0x40004c00-0x40004fff USART4 */ +#define STM32_I2C1_BASE 0x40005400 /* 0x40005400-0x400057ff I2C1 */ +#define STM32_I2C2_BASE 0x40005800 /* 0x40005800-0x40005bff I2C2 */ +#define STM32_USB_BASE 0x40005c00 /* 0x40005c00-0x40005fff USB DRD FS */ +#define STM32_CRS_BASE 0x40006c00 /* 0x40006c00-0x40006fff CRS */ +#define STM32_PWR_BASE 0x40007000 /* 0x40007000-0x400073ff PWR */ +#define STM32_DAC1_BASE 0x40007400 /* 0x40007400-0x400077ff DAC1 */ +#define STM32_OPAMP1_BASE 0x40007800 /* 0x40007800-0x40007bff OPAMP1 */ +#define STM32_LPTIM1_BASE 0x40007c00 /* 0x40007c00-0x40007fff LPTIM1 */ +#define STM32_LPUART1_BASE 0x40008000 /* 0x40008000-0x400083ff LPUART1 */ +#define STM32_LPUART2_BASE 0x40008400 /* 0x40008400-0x400087ff LPUART2 */ +#define STM32_I2C3_BASE 0x40008800 /* 0x40008800-0x40008bff I2C3 */ +#define STM32_LPUART3_BASE 0x40008c00 /* 0x40008c00-0x40008fff LPUART3 */ +#define STM32_LPTIM3_BASE 0x40009000 /* 0x40009000-0x400093ff LPTIM3 */ +#define STM32_LPTIM2_BASE 0x40009400 /* 0x40009400-0x400097ff LPTIM2 */ +#define STM32_USBRAM_BASE 0x40009800 /* 0x40009800-0x40009fff USB SRAM (PMA) */ +#define STM32_I2C4_BASE 0x4000a000 /* 0x4000a000-0x4000a3ff I2C4 */ +#define STM32_TAMP_BASE 0x4000b000 /* 0x4000b000-0x4000b3ff TAMP */ + +#define STM32_SYSCFG_BASE 0x40010000 /* 0x40010000-0x400103ff SYSCFG */ +#define STM32_VREFBUF_BASE 0x40010030 /* 0x40010030: VREFBUF */ +#define STM32_COMP1_BASE 0x40010200 /* 0x40010200: COMP1 */ +#define STM32_COMP2_BASE 0x40010204 /* 0x40010204: COMP2 */ +#define STM32_ADC1_BASE 0x40012400 /* 0x40012400-0x400127ff ADC1 */ +#define STM32_TIM1_BASE 0x40012c00 /* 0x40012c00-0x40012fff TIM1 */ +#define STM32_SPI1_BASE 0x40013000 /* 0x40013000-0x400133ff SPI1 */ +#define STM32_I2S1_BASE 0x40013000 /* 0x40013000-0x400133ff I2S1 */ +#define STM32_USART1_BASE 0x40013800 /* 0x40013800-0x40013bff USART1 */ +#define STM32_TIM15_BASE 0x40014000 /* 0x40014000-0x400143ff TIM15 */ +#define STM32_TIM16_BASE 0x40014400 /* 0x40014400-0x400147ff TIM16 */ +#define STM32_DBGMCU_BASE 0x40015800 /* 0x40015800-0x40015bff DBGMCU */ + +/* AHB Base Addresses *******************************************************/ + +#define STM32_DMA1_BASE 0x40020000 /* 0x40020000-0x400203ff: DMA1 */ +#define STM32_DMA2_BASE 0x40020400 /* 0x40020400-0x400207ff: DMA2 */ +#define STM32_DMAMUX1_BASE 0x40020800 /* 0x40020800-0x40020bff: DMAMUX */ +#define STM32_RCC_BASE 0x40021000 /* 0x40021000-0x400213ff: Reset and Clock control RCC */ +#define STM32_EXTI_BASE 0x40021800 /* 0x40021800-0x40021bff: EXTI */ +#define STM32_FLASHIF_BASE 0x40022000 /* 0x40022000-0x400223ff: Flash memory interface */ +#define STM32_CRC_BASE 0x40023000 /* 0x40023000-0x400233ff: CRC */ +#define STM32_TSC_BASE 0x40024000 /* 0x40024000-0x400243ff: TSC */ +#define STM32_RNG_BASE 0x40025000 /* 0x40025000-0x400253ff: RNG */ +#define STM32_AES_BASE 0x40026000 /* 0x40026000-0x400263ff: AES */ + +/* IOPORT Base Addresses ****************************************************/ + +#define STM32_GPIOA_BASE 0x50000000 /* 0x50000000-0x500003ff: GPIO Port A */ +#define STM32_GPIOB_BASE 0x50000400 /* 0x50000400-0x500007ff: GPIO Port B */ +#define STM32_GPIOC_BASE 0x50000800 /* 0x50000800-0x50000bff: GPIO Port C */ +#define STM32_GPIOD_BASE 0x50000c00 /* 0x50000c00-0x50000fff: GPIO Port D */ +#define STM32_GPIOE_BASE 0x50001000 /* 0x50001000-0x500013ff: GPIO Port E */ +#define STM32_GPIOF_BASE 0x50001400 /* 0x50001400-0x500017ff: GPIO Port F */ + +/* Cortex-M0+ Base Addresses ************************************************/ + +/* Other registers -- see armv6-m/nvic.h for standard Cortex-M0+ registers + * in this address range + */ + +#define STM32_SCS_BASE 0xe000e000 + +/* System Memory Addresses **************************************************/ + +#define STM32_SYSMEM_UID 0x1fff6e50 /* The 96-bit unique device identifier */ + +#endif /* __ARCH_ARM_SRC_STM32U0_HARDWARE_STM32U0_MEMORYMAP_H */ diff --git a/arch/arm/src/stm32u0/hardware/stm32u0_pinmap.h b/arch/arm/src/stm32u0/hardware/stm32u0_pinmap.h new file mode 100644 index 00000000000..0532e4a2188 --- /dev/null +++ b/arch/arm/src/stm32u0/hardware/stm32u0_pinmap.h @@ -0,0 +1,417 @@ +/**************************************************************************** + * arch/arm/src/stm32u0/hardware/stm32u0_pinmap.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32U0_HARDWARE_STM32U0_PINMAP_H +#define __ARCH_ARM_SRC_STM32U0_HARDWARE_STM32U0_PINMAP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "stm32_gpio.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Alternate Pin Functions. + * + * Alternative pin selections are provided with a numeric suffix like _1, _2, + * etc. Drivers, however, will use the pin selection without the numeric + * suffix. Additional definitions are required in the board.h file. For + * example, if I2C1_SCL connects via PB6 on some board, then the following + * definitions should appear in the board.h header file for that board: + * + * #define GPIO_I2C1_SCL GPIO_I2C1_SCL_1 + * + * The driver will then automatically configure PB6 as the I2C1 SCL pin. + */ + +/* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! + * Additional effort is required to select specific GPIO options such as + * frequency, open-drain/push-pull, and pull-up/down! Just the basics are + * defined for most pins in this file. + */ + +/* ADC */ + +#define GPIO_ADC1_IN0_1 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN0) +#define GPIO_ADC1_IN1_1 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN1) +#define GPIO_ADC1_IN2_1 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN2) +#define GPIO_ADC1_IN3_1 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN3) +#define GPIO_ADC1_IN4_1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN0) +#define GPIO_ADC1_IN5_1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN1) +#define GPIO_ADC1_IN6_1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN2) +#define GPIO_ADC1_IN7_1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN3) +#define GPIO_ADC1_IN8_1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN4) +#define GPIO_ADC1_IN9_1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN5) +#define GPIO_ADC1_IN10_1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN6) +#define GPIO_ADC1_IN14_1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN7) +#define GPIO_ADC1_IN15_1 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN4) +#define GPIO_ADC1_IN16_1 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN5) +#define GPIO_ADC1_IN17_1 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN0) +#define GPIO_ADC1_IN18_1 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN1) + +/* COMP */ + +#define GPIO_COMP1_INM_1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN0) +#define GPIO_COMP1_INM_2 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN4) +#define GPIO_COMP1_INM_3 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN5) +#define GPIO_COMP1_INM_4 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN1) +#define GPIO_COMP1_INM_5 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN4) +#define GPIO_COMP1_INP_1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN1) +#define GPIO_COMP1_INP_2 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN9) +#define GPIO_COMP1_INP_3 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN2) +#define GPIO_COMP1_INP_4 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN5) +#define GPIO_COMP1_INP_5 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN6) +#define GPIO_COMP1_OUT_1 (GPIO_ALT | GPIO_AF12 | GPIO_PORTA | GPIO_PIN0) +#define GPIO_COMP1_OUT_2 (GPIO_ALT | GPIO_AF6 | GPIO_PORTA | GPIO_PIN6) +#define GPIO_COMP1_OUT_3 (GPIO_ALT | GPIO_AF12 | GPIO_PORTA | GPIO_PIN11) +#define GPIO_COMP1_OUT_4 (GPIO_ALT | GPIO_AF12 | GPIO_PORTB | GPIO_PIN0) +#define GPIO_COMP1_OUT_5 (GPIO_ALT | GPIO_AF12 | GPIO_PORTB | GPIO_PIN10) + +#define GPIO_COMP2_INM_1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN2) +#define GPIO_COMP2_INM_2 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN4) +#define GPIO_COMP2_INM_3 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN5) +#define GPIO_COMP2_INM_4 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN3) +#define GPIO_COMP2_INM_5 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN7) +#define GPIO_COMP2_INP_1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN3) +#define GPIO_COMP2_INP_2 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN4) +#define GPIO_COMP2_INP_3 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN6) +#define GPIO_COMP2_INP_4 (GPIO_ANALOG | GPIO_PORTD | GPIO_PIN10) +#define GPIO_COMP2_OUT_1 (GPIO_ALT | GPIO_AF12 | GPIO_PORTA | GPIO_PIN2) +#define GPIO_COMP2_OUT_2 (GPIO_ALT | GPIO_AF12 | GPIO_PORTA | GPIO_PIN7) +#define GPIO_COMP2_OUT_3 (GPIO_ALT | GPIO_AF12 | GPIO_PORTB | GPIO_PIN5) +#define GPIO_COMP2_OUT_4 (GPIO_ALT | GPIO_AF12 | GPIO_PORTB | GPIO_PIN11) + +/* DAC */ + +#define GPIO_DAC1_OUT1_1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN4) + +/* I2C */ + +#define GPIO_I2C1_SCL_1 (GPIO_ALT | GPIO_AF4 | GPIO_PORTA | GPIO_PIN9) +#define GPIO_I2C1_SCL_2 (GPIO_ALT | GPIO_AF4 | GPIO_PORTB | GPIO_PIN6) +#define GPIO_I2C1_SCL_3 (GPIO_ALT | GPIO_AF4 | GPIO_PORTB | GPIO_PIN8) +#define GPIO_I2C1_SDA_1 (GPIO_ALT | GPIO_AF4 | GPIO_PORTA | GPIO_PIN10) +#define GPIO_I2C1_SDA_2 (GPIO_ALT | GPIO_AF4 | GPIO_PORTB | GPIO_PIN7) +#define GPIO_I2C1_SDA_3 (GPIO_ALT | GPIO_AF4 | GPIO_PORTB | GPIO_PIN9) + +#define GPIO_I2C2_SCL_1 (GPIO_ALT | GPIO_AF3 | GPIO_PORTA | GPIO_PIN7) +#define GPIO_I2C2_SCL_2 (GPIO_ALT | GPIO_AF5 | GPIO_PORTA | GPIO_PIN9) +#define GPIO_I2C2_SCL_3 (GPIO_ALT | GPIO_AF3 | GPIO_PORTB | GPIO_PIN3) +#define GPIO_I2C2_SCL_4 (GPIO_ALT | GPIO_AF5 | GPIO_PORTB | GPIO_PIN6) +#define GPIO_I2C2_SCL_5 (GPIO_ALT | GPIO_AF3 | GPIO_PORTB | GPIO_PIN8) +#define GPIO_I2C2_SCL_6 (GPIO_ALT | GPIO_AF4 | GPIO_PORTB | GPIO_PIN10) +#define GPIO_I2C2_SCL_7 (GPIO_ALT | GPIO_AF4 | GPIO_PORTB | GPIO_PIN13) +#define GPIO_I2C2_SDA_1 (GPIO_ALT | GPIO_AF3 | GPIO_PORTA | GPIO_PIN6) +#define GPIO_I2C2_SDA_2 (GPIO_ALT | GPIO_AF5 | GPIO_PORTA | GPIO_PIN10) +#define GPIO_I2C2_SDA_3 (GPIO_ALT | GPIO_AF3 | GPIO_PORTB | GPIO_PIN4) +#define GPIO_I2C2_SDA_4 (GPIO_ALT | GPIO_AF5 | GPIO_PORTB | GPIO_PIN7) +#define GPIO_I2C2_SDA_5 (GPIO_ALT | GPIO_AF3 | GPIO_PORTB | GPIO_PIN9) +#define GPIO_I2C2_SDA_6 (GPIO_ALT | GPIO_AF4 | GPIO_PORTB | GPIO_PIN11) +#define GPIO_I2C2_SDA_7 (GPIO_ALT | GPIO_AF4 | GPIO_PORTB | GPIO_PIN14) + +#define GPIO_I2C3_SCL_1 (GPIO_ALT | GPIO_AF4 | GPIO_PORTA | GPIO_PIN7) +#define GPIO_I2C3_SCL_2 (GPIO_ALT | GPIO_AF4 | GPIO_PORTB | GPIO_PIN3) +#define GPIO_I2C3_SCL_3 (GPIO_ALT | GPIO_AF4 | GPIO_PORTC | GPIO_PIN0) +#define GPIO_I2C3_SDA_1 (GPIO_ALT | GPIO_AF4 | GPIO_PORTA | GPIO_PIN6) +#define GPIO_I2C3_SDA_2 (GPIO_ALT | GPIO_AF4 | GPIO_PORTB | GPIO_PIN4) +#define GPIO_I2C3_SDA_3 (GPIO_ALT | GPIO_AF4 | GPIO_PORTC | GPIO_PIN1) + +#define GPIO_I2C4_SCL_1 (GPIO_ALT | GPIO_AF3 | GPIO_PORTB | GPIO_PIN6) +#define GPIO_I2C4_SCL_2 (GPIO_ALT | GPIO_AF3 | GPIO_PORTB | GPIO_PIN10) +#define GPIO_I2C4_SCL_3 (GPIO_ALT | GPIO_AF2 | GPIO_PORTC | GPIO_PIN0) +#define GPIO_I2C4_SCL_4 (GPIO_ALT | GPIO_AF4 | GPIO_PORTD | GPIO_PIN12) +#define GPIO_I2C4_SDA_1 (GPIO_ALT | GPIO_AF3 | GPIO_PORTB | GPIO_PIN7) +#define GPIO_I2C4_SDA_2 (GPIO_ALT | GPIO_AF3 | GPIO_PORTB | GPIO_PIN11) +#define GPIO_I2C4_SDA_3 (GPIO_ALT | GPIO_AF2 | GPIO_PORTC | GPIO_PIN1) +#define GPIO_I2C4_SDA_4 (GPIO_ALT | GPIO_AF4 | GPIO_PORTD | GPIO_PIN13) + +/* MCO */ + +#define GPIO_MCO_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTA | GPIO_PIN8) +#define GPIO_MCO_2 (GPIO_ALT | GPIO_AF0 | GPIO_PORTA | GPIO_PIN9) +#define GPIO_MCO_3 (GPIO_ALT | GPIO_AF0 | GPIO_PORTF | GPIO_PIN2) +#define GPIO_MCO2_1 (GPIO_ALT | GPIO_AF3 | GPIO_PORTA | GPIO_PIN8) +#define GPIO_MCO2_2 (GPIO_ALT | GPIO_AF3 | GPIO_PORTA | GPIO_PIN10) +#define GPIO_MCO2_3 (GPIO_ALT | GPIO_AF0 | GPIO_PORTC | GPIO_PIN2) + +/* SPI */ + +#define GPIO_SPI1_SCK_1 (GPIO_ALT | GPIO_AF5 | GPIO_PORTA | GPIO_PIN1) +#define GPIO_SPI1_SCK_2 (GPIO_ALT | GPIO_AF5 | GPIO_PORTA | GPIO_PIN5) +#define GPIO_SPI1_SCK_3 (GPIO_ALT | GPIO_AF5 | GPIO_PORTB | GPIO_PIN3) +#define GPIO_SPI1_MISO_1 (GPIO_ALT | GPIO_AF5 | GPIO_PORTA | GPIO_PIN6) +#define GPIO_SPI1_MISO_2 (GPIO_ALT | GPIO_AF5 | GPIO_PORTA | GPIO_PIN11) +#define GPIO_SPI1_MISO_3 (GPIO_ALT | GPIO_AF5 | GPIO_PORTB | GPIO_PIN4) +#define GPIO_SPI1_MOSI_1 (GPIO_ALT | GPIO_AF5 | GPIO_PORTA | GPIO_PIN7) +#define GPIO_SPI1_MOSI_2 (GPIO_ALT | GPIO_AF5 | GPIO_PORTA | GPIO_PIN12) +#define GPIO_SPI1_MOSI_3 (GPIO_ALT | GPIO_AF5 | GPIO_PORTB | GPIO_PIN5) +#define GPIO_SPI1_NSS_1 (GPIO_ALT | GPIO_AF5 | GPIO_PORTA | GPIO_PIN4) +#define GPIO_SPI1_NSS_2 (GPIO_ALT | GPIO_AF5 | GPIO_PORTA | GPIO_PIN15) +#define GPIO_SPI1_NSS_3 (GPIO_ALT | GPIO_AF5 | GPIO_PORTB | GPIO_PIN0) + +#define GPIO_SPI2_SCK_1 (GPIO_ALT | GPIO_AF6 | GPIO_PORTA | GPIO_PIN1) +#define GPIO_SPI2_SCK_2 (GPIO_ALT | GPIO_AF5 | GPIO_PORTB | GPIO_PIN10) +#define GPIO_SPI2_SCK_3 (GPIO_ALT | GPIO_AF5 | GPIO_PORTB | GPIO_PIN13) +#define GPIO_SPI2_SCK_4 (GPIO_ALT | GPIO_AF5 | GPIO_PORTD | GPIO_PIN1) +#define GPIO_SPI2_MISO_1 (GPIO_ALT | GPIO_AF6 | GPIO_PORTA | GPIO_PIN11) +#define GPIO_SPI2_MISO_2 (GPIO_ALT | GPIO_AF5 | GPIO_PORTB | GPIO_PIN14) +#define GPIO_SPI2_MISO_3 (GPIO_ALT | GPIO_AF5 | GPIO_PORTC | GPIO_PIN2) +#define GPIO_SPI2_MISO_4 (GPIO_ALT | GPIO_AF5 | GPIO_PORTD | GPIO_PIN3) +#define GPIO_SPI2_MOSI_1 (GPIO_ALT | GPIO_AF6 | GPIO_PORTA | GPIO_PIN12) +#define GPIO_SPI2_MOSI_2 (GPIO_ALT | GPIO_AF5 | GPIO_PORTB | GPIO_PIN15) +#define GPIO_SPI2_MOSI_3 (GPIO_ALT | GPIO_AF5 | GPIO_PORTC | GPIO_PIN3) +#define GPIO_SPI2_MOSI_4 (GPIO_ALT | GPIO_AF5 | GPIO_PORTD | GPIO_PIN4) +#define GPIO_SPI2_NSS_1 (GPIO_ALT | GPIO_AF6 | GPIO_PORTA | GPIO_PIN10) +#define GPIO_SPI2_NSS_2 (GPIO_ALT | GPIO_AF5 | GPIO_PORTB | GPIO_PIN9) +#define GPIO_SPI2_NSS_3 (GPIO_ALT | GPIO_AF5 | GPIO_PORTB | GPIO_PIN12) +#define GPIO_SPI2_NSS_4 (GPIO_ALT | GPIO_AF5 | GPIO_PORTD | GPIO_PIN0) + +#define GPIO_SPI3_SCK_1 (GPIO_ALT | GPIO_AF6 | GPIO_PORTB | GPIO_PIN3) +#define GPIO_SPI3_SCK_2 (GPIO_ALT | GPIO_AF6 | GPIO_PORTC | GPIO_PIN10) +#define GPIO_SPI3_MISO_1 (GPIO_ALT | GPIO_AF6 | GPIO_PORTB | GPIO_PIN4) +#define GPIO_SPI3_MISO_2 (GPIO_ALT | GPIO_AF6 | GPIO_PORTC | GPIO_PIN11) +#define GPIO_SPI3_MOSI_1 (GPIO_ALT | GPIO_AF6 | GPIO_PORTB | GPIO_PIN5) +#define GPIO_SPI3_MOSI_2 (GPIO_ALT | GPIO_AF6 | GPIO_PORTC | GPIO_PIN12) +#define GPIO_SPI3_NSS_1 (GPIO_ALT | GPIO_AF6 | GPIO_PORTA | GPIO_PIN4) +#define GPIO_SPI3_NSS_2 (GPIO_ALT | GPIO_AF6 | GPIO_PORTA | GPIO_PIN15) + +/* Timers */ + +#define GPIO_TIM1_BKIN_1 (GPIO_ALT | GPIO_AF1 | GPIO_PORTA | GPIO_PIN6) +#define GPIO_TIM1_BKIN_2 (GPIO_ALT | GPIO_AF1 | GPIO_PORTB | GPIO_PIN12) +#define GPIO_TIM1_BKIN2_1 (GPIO_ALT | GPIO_AF2 | GPIO_PORTA | GPIO_PIN11) + +#define GPIO_TIM1_CH1IN_1 (GPIO_ALT | GPIO_FLOAT | GPIO_AF1 | GPIO_PORTA | GPIO_PIN8) +#define GPIO_TIM1_CH2IN_1 (GPIO_ALT | GPIO_FLOAT | GPIO_AF1 | GPIO_PORTA | GPIO_PIN9) +#define GPIO_TIM1_CH1IN_2 (GPIO_ALT | GPIO_FLOAT | GPIO_AF1 | GPIO_PORTE | GPIO_PIN9) + +#define GPIO_TIM1_CH1OUT_1 (GPIO_ALT | GPIO_AF1 | GPIO_PORTA | GPIO_PIN8) +#define GPIO_TIM1_CH1OUT_2 (GPIO_ALT | GPIO_AF1 | GPIO_PORTE | GPIO_PIN9) +#define GPIO_TIM1_CH1NOUT_1 (GPIO_ALT | GPIO_AF1 | GPIO_PORTA | GPIO_PIN7) +#define GPIO_TIM1_CH1NOUT_2 (GPIO_ALT | GPIO_AF1 | GPIO_PORTB | GPIO_PIN13) +#define GPIO_TIM1_CH1NOUT_3 (GPIO_ALT | GPIO_AF1 | GPIO_PORTE | GPIO_PIN8) +#define GPIO_TIM1_CH2OUT_1 (GPIO_ALT | GPIO_AF1 | GPIO_PORTA | GPIO_PIN9) +#define GPIO_TIM1_CH2NOUT_1 (GPIO_ALT | GPIO_AF1 | GPIO_PORTB | GPIO_PIN0) +#define GPIO_TIM1_CH2NOUT_2 (GPIO_ALT | GPIO_AF1 | GPIO_PORTB | GPIO_PIN14) +#define GPIO_TIM1_CH3OUT_1 (GPIO_ALT | GPIO_AF1 | GPIO_PORTA | GPIO_PIN10) +#define GPIO_TIM1_CH3NOUT_1 (GPIO_ALT | GPIO_AF1 | GPIO_PORTB | GPIO_PIN1) +#define GPIO_TIM1_CH3NOUT_2 (GPIO_ALT | GPIO_AF1 | GPIO_PORTB | GPIO_PIN15) +#define GPIO_TIM1_CH4OUT_1 (GPIO_ALT | GPIO_AF1 | GPIO_PORTA | GPIO_PIN11) + +#define GPIO_TIM2_CH1IN_1 (GPIO_ALT | GPIO_FLOAT | GPIO_AF1 | GPIO_PORTA | GPIO_PIN5) +#define GPIO_TIM2_CH1IN_2 (GPIO_ALT | GPIO_FLOAT | GPIO_AF1 | GPIO_PORTA | GPIO_PIN15) +#define GPIO_TIM2_CH2IN_1 (GPIO_ALT | GPIO_FLOAT | GPIO_AF1 | GPIO_PORTA | GPIO_PIN1) +#define GPIO_TIM2_CH2IN_2 (GPIO_ALT | GPIO_FLOAT | GPIO_AF1 | GPIO_PORTB | GPIO_PIN3) + +#define GPIO_TIM2_CH1OUT_1 (GPIO_ALT | GPIO_AF1 | GPIO_PORTA | GPIO_PIN5) +#define GPIO_TIM2_CH1OUT_2 (GPIO_ALT | GPIO_AF1 | GPIO_PORTA | GPIO_PIN15) +#define GPIO_TIM2_CH2OUT_1 (GPIO_ALT | GPIO_AF1 | GPIO_PORTA | GPIO_PIN1) +#define GPIO_TIM2_CH2OUT_2 (GPIO_ALT | GPIO_AF1 | GPIO_PORTB | GPIO_PIN3) +#define GPIO_TIM2_CH3OUT_1 (GPIO_ALT | GPIO_AF1 | GPIO_PORTA | GPIO_PIN2) +#define GPIO_TIM2_CH3OUT_2 (GPIO_ALT | GPIO_AF1 | GPIO_PORTB | GPIO_PIN10) +#define GPIO_TIM2_CH4OUT_1 (GPIO_ALT | GPIO_AF1 | GPIO_PORTA | GPIO_PIN3) +#define GPIO_TIM2_CH4OUT_2 (GPIO_ALT | GPIO_AF1 | GPIO_PORTB | GPIO_PIN11) + +#define GPIO_TIM3_CH1IN_1 (GPIO_ALT | GPIO_FLOAT | GPIO_AF2 | GPIO_PORTA | GPIO_PIN6) +#define GPIO_TIM3_CH1IN_2 (GPIO_ALT | GPIO_FLOAT | GPIO_AF2 | GPIO_PORTB | GPIO_PIN4) +#define GPIO_TIM3_CH1IN_3 (GPIO_ALT | GPIO_FLOAT | GPIO_AF2 | GPIO_PORTC | GPIO_PIN6) +#define GPIO_TIM3_CH2IN_1 (GPIO_ALT | GPIO_FLOAT | GPIO_AF2 | GPIO_PORTA | GPIO_PIN7) +#define GPIO_TIM3_CH2IN_2 (GPIO_ALT | GPIO_FLOAT | GPIO_AF2 | GPIO_PORTB | GPIO_PIN5) +#define GPIO_TIM3_CH2IN_3 (GPIO_ALT | GPIO_FLOAT | GPIO_AF2 | GPIO_PORTC | GPIO_PIN7) + +#define GPIO_TIM3_CH1OUT_1 (GPIO_ALT | GPIO_AF2 | GPIO_PORTA | GPIO_PIN6) +#define GPIO_TIM3_CH1OUT_2 (GPIO_ALT | GPIO_AF2 | GPIO_PORTB | GPIO_PIN4) +#define GPIO_TIM3_CH1OUT_3 (GPIO_ALT | GPIO_AF2 | GPIO_PORTC | GPIO_PIN6) +#define GPIO_TIM3_CH2OUT_1 (GPIO_ALT | GPIO_AF2 | GPIO_PORTA | GPIO_PIN7) +#define GPIO_TIM3_CH2OUT_2 (GPIO_ALT | GPIO_AF2 | GPIO_PORTB | GPIO_PIN5) +#define GPIO_TIM3_CH2OUT_3 (GPIO_ALT | GPIO_AF2 | GPIO_PORTC | GPIO_PIN7) +#define GPIO_TIM3_CH3OUT_1 (GPIO_ALT | GPIO_AF2 | GPIO_PORTB | GPIO_PIN0) +#define GPIO_TIM3_CH3OUT_2 (GPIO_ALT | GPIO_AF2 | GPIO_PORTC | GPIO_PIN8) +#define GPIO_TIM3_CH4OUT_1 (GPIO_ALT | GPIO_AF2 | GPIO_PORTB | GPIO_PIN1) +#define GPIO_TIM3_CH4OUT_2 (GPIO_ALT | GPIO_AF2 | GPIO_PORTC | GPIO_PIN9) + +#define GPIO_TIM15_BKIN_1 (GPIO_ALT | GPIO_AF14 | GPIO_PORTA | GPIO_PIN9) +#define GPIO_TIM15_BKIN_2 (GPIO_ALT | GPIO_AF14 | GPIO_PORTB | GPIO_PIN12) +#define GPIO_TIM15_CH1OUT_1 (GPIO_ALT | GPIO_AF14 | GPIO_PORTA | GPIO_PIN2) +#define GPIO_TIM15_CH1OUT_2 (GPIO_ALT | GPIO_AF14 | GPIO_PORTB | GPIO_PIN14) +#define GPIO_TIM15_CH1NOUT_1 (GPIO_ALT | GPIO_AF14 | GPIO_PORTA | GPIO_PIN1) +#define GPIO_TIM15_CH1NOUT_2 (GPIO_ALT | GPIO_AF14 | GPIO_PORTB | GPIO_PIN13) +#define GPIO_TIM15_CH2OUT_1 (GPIO_ALT | GPIO_AF14 | GPIO_PORTA | GPIO_PIN3) +#define GPIO_TIM15_CH2OUT_2 (GPIO_ALT | GPIO_AF14 | GPIO_PORTB | GPIO_PIN15) + +#define GPIO_TIM16_BKIN_1 (GPIO_ALT | GPIO_AF14 | GPIO_PORTB | GPIO_PIN5) +#define GPIO_TIM16_CH1OUT_1 (GPIO_ALT | GPIO_AF14 | GPIO_PORTA | GPIO_PIN6) +#define GPIO_TIM16_CH1OUT_2 (GPIO_ALT | GPIO_AF14 | GPIO_PORTB | GPIO_PIN8) +#define GPIO_TIM16_CH1NOUT_1 (GPIO_ALT | GPIO_AF14 | GPIO_PORTB | GPIO_PIN6) + +/* LPTIM */ + +#define GPIO_LPTIM1_CH1_1 (GPIO_ALT | GPIO_AF1 | GPIO_PORTA | GPIO_PIN14) +#define GPIO_LPTIM1_CH1_2 (GPIO_ALT | GPIO_AF1 | GPIO_PORTB | GPIO_PIN2) +#define GPIO_LPTIM1_CH1_3 (GPIO_ALT | GPIO_AF1 | GPIO_PORTC | GPIO_PIN1) +#define GPIO_LPTIM1_CH2_1 (GPIO_ALT | GPIO_AF2 | GPIO_PORTA | GPIO_PIN1) +#define GPIO_LPTIM1_CH3_1 (GPIO_ALT | GPIO_AF2 | GPIO_PORTB | GPIO_PIN3) +#define GPIO_LPTIM1_CH3_2 (GPIO_ALT | GPIO_AF2 | GPIO_PORTC | GPIO_PIN13) +#define GPIO_LPTIM1_CH3_3 (GPIO_ALT | GPIO_AF1 | GPIO_PORTD | GPIO_PIN4) +#define GPIO_LPTIM1_CH3_4 (GPIO_ALT | GPIO_AF2 | GPIO_PORTE | GPIO_PIN9) +#define GPIO_LPTIM1_CH4_1 (GPIO_ALT | GPIO_AF1 | GPIO_PORTB | GPIO_PIN4) +#define GPIO_LPTIM1_CH4_2 (GPIO_ALT | GPIO_AF14 | GPIO_PORTB | GPIO_PIN9) +#define GPIO_LPTIM1_CH4_3 (GPIO_ALT | GPIO_AF1 | GPIO_PORTD | GPIO_PIN1) +#define GPIO_LPTIM1_IN1_1 (GPIO_ALT | GPIO_AF1 | GPIO_PORTB | GPIO_PIN5) +#define GPIO_LPTIM1_IN1_2 (GPIO_ALT | GPIO_AF1 | GPIO_PORTC | GPIO_PIN0) +#define GPIO_LPTIM1_IN2_1 (GPIO_ALT | GPIO_AF1 | GPIO_PORTB | GPIO_PIN7) +#define GPIO_LPTIM1_IN2_2 (GPIO_ALT | GPIO_AF1 | GPIO_PORTB | GPIO_PIN8) +#define GPIO_LPTIM1_IN2_3 (GPIO_ALT | GPIO_AF1 | GPIO_PORTC | GPIO_PIN2) +#define GPIO_LPTIM1_ETR_1 (GPIO_ALT | GPIO_AF1 | GPIO_PORTB | GPIO_PIN6) +#define GPIO_LPTIM1_ETR_2 (GPIO_ALT | GPIO_AF1 | GPIO_PORTC | GPIO_PIN3) + +#define GPIO_LPTIM2_CH1_1 (GPIO_ALT | GPIO_AF14 | GPIO_PORTA | GPIO_PIN4) +#define GPIO_LPTIM2_CH1_2 (GPIO_ALT | GPIO_AF14 | GPIO_PORTA | GPIO_PIN8) +#define GPIO_LPTIM2_CH1_3 (GPIO_ALT | GPIO_AF14 | GPIO_PORTD | GPIO_PIN13) +#define GPIO_LPTIM2_CH2_1 (GPIO_ALT | GPIO_AF14 | GPIO_PORTA | GPIO_PIN7) +#define GPIO_LPTIM2_CH2_2 (GPIO_ALT | GPIO_AF14 | GPIO_PORTC | GPIO_PIN7) +#define GPIO_LPTIM2_CH2_3 (GPIO_ALT | GPIO_AF14 | GPIO_PORTD | GPIO_PIN10) +#define GPIO_LPTIM2_IN1_1 (GPIO_ALT | GPIO_AF14 | GPIO_PORTB | GPIO_PIN1) +#define GPIO_LPTIM2_IN1_2 (GPIO_ALT | GPIO_AF14 | GPIO_PORTC | GPIO_PIN0) +#define GPIO_LPTIM2_IN1_3 (GPIO_ALT | GPIO_AF14 | GPIO_PORTD | GPIO_PIN12) +#define GPIO_LPTIM2_ETR_1 (GPIO_ALT | GPIO_AF14 | GPIO_PORTA | GPIO_PIN5) +#define GPIO_LPTIM2_ETR_2 (GPIO_ALT | GPIO_AF14 | GPIO_PORTC | GPIO_PIN3) +#define GPIO_LPTIM2_ETR_3 (GPIO_ALT | GPIO_AF14 | GPIO_PORTD | GPIO_PIN11) + +#define GPIO_LPTIM3_CH1_1 (GPIO_ALT | GPIO_AF4 | GPIO_PORTB | GPIO_PIN0) +#define GPIO_LPTIM3_CH1_2 (GPIO_ALT | GPIO_AF2 | GPIO_PORTB | GPIO_PIN10) +#define GPIO_LPTIM3_CH1_3 (GPIO_ALT | GPIO_AF2 | GPIO_PORTC | GPIO_PIN3) +#define GPIO_LPTIM3_CH1_4 (GPIO_ALT | GPIO_AF4 | GPIO_PORTC | GPIO_PIN8) +#define GPIO_LPTIM3_CH2_1 (GPIO_ALT | GPIO_AF4 | GPIO_PORTB | GPIO_PIN1) +#define GPIO_LPTIM3_CH2_2 (GPIO_ALT | GPIO_AF4 | GPIO_PORTC | GPIO_PIN9) +#define GPIO_LPTIM3_CH3_1 (GPIO_ALT | GPIO_AF14 | GPIO_PORTA | GPIO_PIN15) +#define GPIO_LPTIM3_CH3_2 (GPIO_ALT | GPIO_AF4 | GPIO_PORTC | GPIO_PIN5) +#define GPIO_LPTIM3_CH3_3 (GPIO_ALT | GPIO_AF4 | GPIO_PORTC | GPIO_PIN12) +#define GPIO_LPTIM3_CH3_4 (GPIO_ALT | GPIO_AF4 | GPIO_PORTC | GPIO_PIN13) +#define GPIO_LPTIM3_CH4_1 (GPIO_ALT | GPIO_AF2 | GPIO_PORTB | GPIO_PIN9) +#define GPIO_LPTIM3_CH4_2 (GPIO_ALT | GPIO_AF4 | GPIO_PORTC | GPIO_PIN7) +#define GPIO_LPTIM3_IN1_1 (GPIO_ALT | GPIO_AF2 | GPIO_PORTB | GPIO_PIN13) +#define GPIO_LPTIM3_IN1_2 (GPIO_ALT | GPIO_AF2 | GPIO_PORTC | GPIO_PIN11) +#define GPIO_LPTIM3_IN1_3 (GPIO_ALT | GPIO_AF4 | GPIO_PORTD | GPIO_PIN9) +#define GPIO_LPTIM3_IN2_1 (GPIO_ALT | GPIO_AF4 | GPIO_PORTA | GPIO_PIN15) +#define GPIO_LPTIM3_IN2_2 (GPIO_ALT | GPIO_AF2 | GPIO_PORTB | GPIO_PIN8) +#define GPIO_LPTIM3_ETR_1 (GPIO_ALT | GPIO_AF2 | GPIO_PORTB | GPIO_PIN14) +#define GPIO_LPTIM3_ETR_2 (GPIO_ALT | GPIO_AF2 | GPIO_PORTC | GPIO_PIN10) +#define GPIO_LPTIM3_ETR_3 (GPIO_ALT | GPIO_AF4 | GPIO_PORTD | GPIO_PIN10) + +/* USART */ + +#define GPIO_USART1_CTS_1 (GPIO_ALT | GPIO_AF7 | GPIO_PORTA | GPIO_PIN11) +#define GPIO_USART1_CTS_2 (GPIO_ALT | GPIO_AF7 | GPIO_PORTB | GPIO_PIN4) +#define GPIO_USART1_RTS_1 (GPIO_ALT | GPIO_AF7 | GPIO_PORTA | GPIO_PIN12) +#define GPIO_USART1_RTS_2 (GPIO_ALT | GPIO_AF7 | GPIO_PORTB | GPIO_PIN3) +#define GPIO_USART1_RX_1 (GPIO_ALT | GPIO_PULLUP | GPIO_AF7 | GPIO_PUSHPULL | GPIO_PORTA | GPIO_PIN10) +#define GPIO_USART1_RX_2 (GPIO_ALT | GPIO_PULLUP | GPIO_AF7 | GPIO_PUSHPULL | GPIO_PORTB | GPIO_PIN7) +#define GPIO_USART1_TX_1 (GPIO_ALT | GPIO_PULLUP | GPIO_AF7 | GPIO_PUSHPULL | GPIO_PORTA | GPIO_PIN9) +#define GPIO_USART1_TX_2 (GPIO_ALT | GPIO_PULLUP | GPIO_AF7 | GPIO_PUSHPULL | GPIO_PORTB | GPIO_PIN6) + +#define GPIO_USART2_CTS_1 (GPIO_ALT | GPIO_AF7 | GPIO_PORTA | GPIO_PIN0) +#define GPIO_USART2_CTS_2 (GPIO_ALT | GPIO_AF7 | GPIO_PORTD | GPIO_PIN3) +#define GPIO_USART2_RTS_1 (GPIO_ALT | GPIO_AF7 | GPIO_PORTA | GPIO_PIN1) +#define GPIO_USART2_RTS_2 (GPIO_ALT | GPIO_AF7 | GPIO_PORTD | GPIO_PIN4) +#define GPIO_USART2_RX_1 (GPIO_ALT | GPIO_PULLUP | GPIO_AF7 | GPIO_PUSHPULL | GPIO_PORTA | GPIO_PIN3) +#define GPIO_USART2_RX_2 (GPIO_ALT | GPIO_PULLUP | GPIO_AF3 | GPIO_PUSHPULL | GPIO_PORTA | GPIO_PIN15) +#define GPIO_USART2_RX_3 (GPIO_ALT | GPIO_PULLUP | GPIO_AF7 | GPIO_PUSHPULL | GPIO_PORTD | GPIO_PIN6) +#define GPIO_USART2_TX_1 (GPIO_ALT | GPIO_PULLUP | GPIO_AF7 | GPIO_PUSHPULL | GPIO_PORTA | GPIO_PIN2) +#define GPIO_USART2_TX_2 (GPIO_ALT | GPIO_PULLUP | GPIO_AF7 | GPIO_PUSHPULL | GPIO_PORTD | GPIO_PIN5) + +#define GPIO_USART3_CTS_1 (GPIO_ALT | GPIO_AF7 | GPIO_PORTA | GPIO_PIN6) +#define GPIO_USART3_CTS_2 (GPIO_ALT | GPIO_AF7 | GPIO_PORTB | GPIO_PIN13) +#define GPIO_USART3_CTS_3 (GPIO_ALT | GPIO_AF7 | GPIO_PORTD | GPIO_PIN11) +#define GPIO_USART3_RTS_1 (GPIO_ALT | GPIO_AF7 | GPIO_PORTA | GPIO_PIN15) +#define GPIO_USART3_RTS_2 (GPIO_ALT | GPIO_AF7 | GPIO_PORTB | GPIO_PIN1) +#define GPIO_USART3_RTS_3 (GPIO_ALT | GPIO_AF7 | GPIO_PORTB | GPIO_PIN14) +#define GPIO_USART3_RTS_4 (GPIO_ALT | GPIO_AF7 | GPIO_PORTD | GPIO_PIN2) +#define GPIO_USART3_RTS_5 (GPIO_ALT | GPIO_AF7 | GPIO_PORTD | GPIO_PIN12) +#define GPIO_USART3_RX_1 (GPIO_ALT | GPIO_PULLUP | GPIO_AF7 | GPIO_PUSHPULL | GPIO_PORTA | GPIO_PIN7) +#define GPIO_USART3_RX_2 (GPIO_ALT | GPIO_PULLUP | GPIO_AF7 | GPIO_PUSHPULL | GPIO_PORTB | GPIO_PIN9) +#define GPIO_USART3_RX_3 (GPIO_ALT | GPIO_PULLUP | GPIO_AF7 | GPIO_PUSHPULL | GPIO_PORTB | GPIO_PIN11) +#define GPIO_USART3_RX_4 (GPIO_ALT | GPIO_PULLUP | GPIO_AF7 | GPIO_PUSHPULL | GPIO_PORTC | GPIO_PIN5) +#define GPIO_USART3_RX_5 (GPIO_ALT | GPIO_PULLUP | GPIO_AF7 | GPIO_PUSHPULL | GPIO_PORTC | GPIO_PIN11) +#define GPIO_USART3_RX_6 (GPIO_ALT | GPIO_PULLUP | GPIO_AF7 | GPIO_PUSHPULL | GPIO_PORTD | GPIO_PIN9) +#define GPIO_USART3_TX_1 (GPIO_ALT | GPIO_PULLUP | GPIO_AF7 | GPIO_PUSHPULL | GPIO_PORTA | GPIO_PIN5) +#define GPIO_USART3_TX_2 (GPIO_ALT | GPIO_PULLUP | GPIO_AF7 | GPIO_PUSHPULL | GPIO_PORTB | GPIO_PIN8) +#define GPIO_USART3_TX_3 (GPIO_ALT | GPIO_PULLUP | GPIO_AF7 | GPIO_PUSHPULL | GPIO_PORTB | GPIO_PIN10) +#define GPIO_USART3_TX_4 (GPIO_ALT | GPIO_PULLUP | GPIO_AF7 | GPIO_PUSHPULL | GPIO_PORTC | GPIO_PIN4) +#define GPIO_USART3_TX_5 (GPIO_ALT | GPIO_PULLUP | GPIO_AF7 | GPIO_PUSHPULL | GPIO_PORTC | GPIO_PIN10) +#define GPIO_USART3_TX_6 (GPIO_ALT | GPIO_PULLUP | GPIO_AF7 | GPIO_PUSHPULL | GPIO_PORTD | GPIO_PIN8) + +#define GPIO_USART4_CTS_1 (GPIO_ALT | GPIO_AF8 | GPIO_PORTB | GPIO_PIN7) +#define GPIO_USART4_RTS_1 (GPIO_ALT | GPIO_AF8 | GPIO_PORTA | GPIO_PIN15) +#define GPIO_USART4_RX_1 (GPIO_ALT | GPIO_PULLUP | GPIO_AF8 | GPIO_PUSHPULL | GPIO_PORTA | GPIO_PIN1) +#define GPIO_USART4_RX_2 (GPIO_ALT | GPIO_PULLUP | GPIO_AF8 | GPIO_PUSHPULL | GPIO_PORTC | GPIO_PIN11) +#define GPIO_USART4_TX_1 (GPIO_ALT | GPIO_PULLUP | GPIO_AF8 | GPIO_PUSHPULL | GPIO_PORTA | GPIO_PIN0) +#define GPIO_USART4_TX_2 (GPIO_ALT | GPIO_PULLUP | GPIO_AF8 | GPIO_PUSHPULL | GPIO_PORTC | GPIO_PIN10) + +/* LPUART */ + +#define GPIO_LPUART1_CTS_1 (GPIO_ALT | GPIO_AF8 | GPIO_PORTA | GPIO_PIN6) +#define GPIO_LPUART1_CTS_2 (GPIO_ALT | GPIO_AF8 | GPIO_PORTB | GPIO_PIN13) +#define GPIO_LPUART1_RTS_1 (GPIO_ALT | GPIO_AF8 | GPIO_PORTB | GPIO_PIN1) +#define GPIO_LPUART1_RTS_2 (GPIO_ALT | GPIO_AF8 | GPIO_PORTB | GPIO_PIN12) +#define GPIO_LPUART1_RX_1 (GPIO_ALT | GPIO_PULLUP | GPIO_AF8 | GPIO_PUSHPULL | GPIO_PORTA | GPIO_PIN3) +#define GPIO_LPUART1_RX_2 (GPIO_ALT | GPIO_PULLUP | GPIO_AF8 | GPIO_PUSHPULL | GPIO_PORTB | GPIO_PIN10) +#define GPIO_LPUART1_RX_3 (GPIO_ALT | GPIO_PULLUP | GPIO_AF8 | GPIO_PUSHPULL | GPIO_PORTC | GPIO_PIN0) +#define GPIO_LPUART1_TX_1 (GPIO_ALT | GPIO_PULLUP | GPIO_AF8 | GPIO_PUSHPULL | GPIO_PORTA | GPIO_PIN2) +#define GPIO_LPUART1_TX_2 (GPIO_ALT | GPIO_PULLUP | GPIO_AF8 | GPIO_PUSHPULL | GPIO_PORTB | GPIO_PIN11) +#define GPIO_LPUART1_TX_3 (GPIO_ALT | GPIO_PULLUP | GPIO_AF8 | GPIO_PUSHPULL | GPIO_PORTC | GPIO_PIN1) + +#define GPIO_LPUART2_CTS_1 (GPIO_ALT | GPIO_AF8 | GPIO_PORTB | GPIO_PIN0) +#define GPIO_LPUART2_RTS_1 (GPIO_ALT | GPIO_AF10 | GPIO_PORTB | GPIO_PIN1) +#define GPIO_LPUART2_RX_1 (GPIO_ALT | GPIO_PULLUP | GPIO_AF10 | GPIO_PUSHPULL | GPIO_PORTB | GPIO_PIN7) +#define GPIO_LPUART2_RX_2 (GPIO_ALT | GPIO_PULLUP | GPIO_AF10 | GPIO_PUSHPULL | GPIO_PORTB | GPIO_PIN10) +#define GPIO_LPUART2_RX_3 (GPIO_ALT | GPIO_PULLUP | GPIO_AF10 | GPIO_PUSHPULL | GPIO_PORTC | GPIO_PIN1) +#define GPIO_LPUART2_RX_4 (GPIO_ALT | GPIO_PULLUP | GPIO_AF8 | GPIO_PUSHPULL | GPIO_PORTC | GPIO_PIN7) +#define GPIO_LPUART2_TX_1 (GPIO_ALT | GPIO_PULLUP | GPIO_AF10 | GPIO_PUSHPULL | GPIO_PORTB | GPIO_PIN6) +#define GPIO_LPUART2_TX_2 (GPIO_ALT | GPIO_PULLUP | GPIO_AF10 | GPIO_PUSHPULL | GPIO_PORTB | GPIO_PIN11) +#define GPIO_LPUART2_TX_3 (GPIO_ALT | GPIO_PULLUP | GPIO_AF10 | GPIO_PUSHPULL | GPIO_PORTC | GPIO_PIN0) +#define GPIO_LPUART2_TX_4 (GPIO_ALT | GPIO_PULLUP | GPIO_AF8 | GPIO_PUSHPULL | GPIO_PORTC | GPIO_PIN6) + +#define GPIO_LPUART3_CTS_1 (GPIO_ALT | GPIO_AF8 | GPIO_PORTB | GPIO_PIN5) +#define GPIO_LPUART3_CTS_2 (GPIO_ALT | GPIO_AF8 | GPIO_PORTD | GPIO_PIN11) +#define GPIO_LPUART3_RTS_1 (GPIO_ALT | GPIO_AF8 | GPIO_PORTB | GPIO_PIN4) +#define GPIO_LPUART3_RTS_2 (GPIO_ALT | GPIO_AF8 | GPIO_PORTD | GPIO_PIN12) +#define GPIO_LPUART3_RX_1 (GPIO_ALT | GPIO_PULLUP | GPIO_AF8 | GPIO_PUSHPULL | GPIO_PORTA | GPIO_PIN5) +#define GPIO_LPUART3_RX_2 (GPIO_ALT | GPIO_PULLUP | GPIO_AF6 | GPIO_PUSHPULL | GPIO_PORTB | GPIO_PIN7) +#define GPIO_LPUART3_RX_3 (GPIO_ALT | GPIO_PULLUP | GPIO_AF8 | GPIO_PUSHPULL | GPIO_PORTC | GPIO_PIN5) +#define GPIO_LPUART3_RX_4 (GPIO_ALT | GPIO_PULLUP | GPIO_AF8 | GPIO_PUSHPULL | GPIO_PORTD | GPIO_PIN9) +#define GPIO_LPUART3_TX_1 (GPIO_ALT | GPIO_PULLUP | GPIO_AF8 | GPIO_PUSHPULL | GPIO_PORTA | GPIO_PIN4) +#define GPIO_LPUART3_TX_2 (GPIO_ALT | GPIO_PULLUP | GPIO_AF6 | GPIO_PUSHPULL | GPIO_PORTB | GPIO_PIN6) +#define GPIO_LPUART3_TX_3 (GPIO_ALT | GPIO_PULLUP | GPIO_AF8 | GPIO_PUSHPULL | GPIO_PORTC | GPIO_PIN4) +#define GPIO_LPUART3_TX_4 (GPIO_ALT | GPIO_PULLUP | GPIO_AF8 | GPIO_PUSHPULL | GPIO_PORTD | GPIO_PIN8) + +/* USB */ + +#define GPIO_USB_NOE_1 (GPIO_ALT | GPIO_AF10 | GPIO_PORTA | GPIO_PIN13) +#define GPIO_USB_NOE_2 (GPIO_ALT | GPIO_AF10 | GPIO_PORTC | GPIO_PIN9) + +#endif /* __ARCH_ARM_SRC_STM32U0_HARDWARE_STM32U0_PINMAP_H */ diff --git a/arch/arm/src/stm32u0/hardware/stm32u0_pwr.h b/arch/arm/src/stm32u0/hardware/stm32u0_pwr.h new file mode 100644 index 00000000000..454c9ebe6c0 --- /dev/null +++ b/arch/arm/src/stm32u0/hardware/stm32u0_pwr.h @@ -0,0 +1,175 @@ +/**************************************************************************** + * arch/arm/src/stm32u0/hardware/stm32u0_pwr.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32U0_HARDWARE_STM32U0_PWR_H +#define __ARCH_ARM_SRC_STM32U0_HARDWARE_STM32U0_PWR_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include "chip.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define HAVE_PWR_DBP 1 + +/* Register Offsets *********************************************************/ + +#define STM32_PWR_CR1_OFFSET 0x0000 /* Power control register 1 */ +#define STM32_PWR_CR2_OFFSET 0x0004 /* Power control register 2 */ +#define STM32_PWR_CR3_OFFSET 0x0008 /* Power control register 3 */ +#define STM32_PWR_CR4_OFFSET 0x000C /* Power control register 4 */ +#define STM32_PWR_SR1_OFFSET 0x0010 /* Power status register 1 */ +#define STM32_PWR_SR2_OFFSET 0x0014 /* Power status register 2 */ +#define STM32_PWR_SCR_OFFSET 0x0018 /* Power status clear register */ +#define STM32_PWR_PUCRA_OFFSET 0x0020 /* Port A pull-up control register */ +#define STM32_PWR_PDCRA_OFFSET 0x0024 /* Port A pull-down control register */ +#define STM32_PWR_PUCRB_OFFSET 0x0028 /* Port B pull-up control register */ +#define STM32_PWR_PDCRB_OFFSET 0x002C /* Port B pull-down control register */ +#define STM32_PWR_PUCRC_OFFSET 0x0030 /* Port C pull-up control register */ +#define STM32_PWR_PDCRC_OFFSET 0x0034 /* Port C pull-down control register */ +#define STM32_PWR_PUCRD_OFFSET 0x0038 /* Port D pull-up control register */ +#define STM32_PWR_PDCRD_OFFSET 0x003C /* Port D pull-down control register */ +#define STM32_PWR_PUCRE_OFFSET 0x0040 /* Port E pull-up control register */ +#define STM32_PWR_PDCRE_OFFSET 0x0044 /* Port E pull-down control register */ +#define STM32_PWR_PUCRF_OFFSET 0x0048 /* Port F pull-up control register */ +#define STM32_PWR_PDCRF_OFFSET 0x004C /* Port F pull-down control register */ + +/* Register Addresses *******************************************************/ + +#define STM32_PWR_CR1 (STM32_PWR_BASE+STM32_PWR_CR1_OFFSET) +#define STM32_PWR_CR2 (STM32_PWR_BASE+STM32_PWR_CR2_OFFSET) +#define STM32_PWR_CR3 (STM32_PWR_BASE+STM32_PWR_CR3_OFFSET) +#define STM32_PWR_CR4 (STM32_PWR_BASE+STM32_PWR_CR4_OFFSET) +#define STM32_PWR_SR1 (STM32_PWR_BASE+STM32_PWR_SR1_OFFSET) +#define STM32_PWR_SR2 (STM32_PWR_BASE+STM32_PWR_SR2_OFFSET) +#define STM32_PWR_SCR (STM32_PWR_BASE+STM32_PWR_SCR_OFFSET) +#define STM32_PWR_PUCRA (STM32_PWR_BASE+STM32_PWR_PUCRA_OFFSET) +#define STM32_PWR_PDCRA (STM32_PWR_BASE+STM32_PWR_PDCRA_OFFSET) +#define STM32_PWR_PUCRB (STM32_PWR_BASE+STM32_PWR_PUCRB_OFFSET) +#define STM32_PWR_PDCRB (STM32_PWR_BASE+STM32_PWR_PDCRB_OFFSET) +#define STM32_PWR_PUCRC (STM32_PWR_BASE+STM32_PWR_PUCRC_OFFSET) +#define STM32_PWR_PDCRC (STM32_PWR_BASE+STM32_PWR_PDCRC_OFFSET) +#define STM32_PWR_PUCRD (STM32_PWR_BASE+STM32_PWR_PUCRD_OFFSET) +#define STM32_PWR_PDCRD (STM32_PWR_BASE+STM32_PWR_PDCRD_OFFSET) +#define STM32_PWR_PUCRE (STM32_PWR_BASE+STM32_PWR_PUCRE_OFFSET) +#define STM32_PWR_PDCRE (STM32_PWR_BASE+STM32_PWR_PDCRE_OFFSET) +#define STM32_PWR_PUCRF (STM32_PWR_BASE+STM32_PWR_PUCRF_OFFSET) +#define STM32_PWR_PDCRF (STM32_PWR_BASE+STM32_PWR_PDCRF_OFFSET) + +/* Register Bitfield Definitions ********************************************/ + +/* Power control register 1 */ + +#define PWR_CR1_LPMS_SHIFT (0) /* Bits 0-2: Low-power mode */ +#define PWR_CR1_LPMS_MASK (7 << PWR_CR1_LPMS_SHIFT) +# define PWR_CR1_LPMS_STOP0 (0 << PWR_CR1_LPMS_SHIFT) /* 000: Stop 0 */ +# define PWR_CR1_LPMS_STOP1 (1 << PWR_CR1_LPMS_SHIFT) /* 001: Stop 1 */ +# define PWR_CR1_LPMS_STOP2 (2 << PWR_CR1_LPMS_SHIFT) /* 010: Stop 2 */ +# define PWR_CR1_LPMS_STANDBY (3 << PWR_CR1_LPMS_SHIFT) /* 011: Standby */ +# define PWR_CR1_LPMS_SHUTDOWN (4 << PWR_CR1_LPMS_SHIFT) /* 1xx: Shutdown */ +#define PWR_CR1_FPDSTOP (1 << 3) /* Bit 3: Flash PD in Stop mode */ +#define PWR_CR1_FPDLPRUN (1 << 4) /* Bit 4: Flash PD in LP run */ +#define PWR_CR1_FPDLPSLP (1 << 5) /* Bit 5: Flash PD in LP sleep */ +#define PWR_CR1_DBP (1 << 8) /* Bit 8: Disable backup domain write protection */ +#define PWR_CR1_VOS_SHIFT (9) /* Bits 9-10: Voltage scaling range selection */ +#define PWR_CR1_VOS_MASK (3 << PWR_CR1_VOS_SHIFT) +# define PWR_CR1_VOS_RANGE1 (1 << PWR_CR1_VOS_SHIFT) /* 01: Range 1 */ +# define PWR_CR1_VOS_RANGE2 (2 << PWR_CR1_VOS_SHIFT) /* 10: Range 2 */ +#define PWR_CR1_LPR (1 << 14) /* Bit 14: Low-power run */ + +/* Power control register 2 */ + +#define PWR_CR2_PVDE (1 << 0) /* Bit 0: PVD enable */ +#define PWR_CR2_PLS_SHIFT (1) /* Bits 1-3: PVD level */ +#define PWR_CR2_PLS_MASK (7 << PWR_CR2_PLS_SHIFT) +# define PWR_CR2_PLS(n) ((n) << PWR_CR2_PLS_SHIFT) +#define PWR_CR2_PVME1 (1 << 4) /* Bit 4: PVM VDDUSB enable */ +#define PWR_CR2_PVME3 (1 << 5) /* Bit 5: PVM VDDADC enable */ +#define PWR_CR2_PVME4 (1 << 6) /* Bit 6: PVM VDDDAC enable */ +#define PWR_CR2_USV (1 << 10) /* Bit 10: VDDUSB supply valid */ + +/* Power control register 3 */ + +#define PWR_CR3_EWUP1 (1 << 0) /* Bit 0: Enable WKUP1 pin */ +#define PWR_CR3_EWUP2 (1 << 1) /* Bit 1: Enable WKUP2 pin */ +#define PWR_CR3_EWUP3 (1 << 2) /* Bit 2: Enable WKUP3 pin */ +#define PWR_CR3_EWUP4 (1 << 3) /* Bit 3: Enable WKUP4 pin */ +#define PWR_CR3_EWUP5 (1 << 4) /* Bit 4: Enable WKUP5 pin */ +#define PWR_CR3_EWUP7 (1 << 6) /* Bit 6: Enable WKUP7 pin */ +#define PWR_CR3_RRS (1 << 8) /* Bit 8: SRAM2 retention in Standby mode */ +#define PWR_CR3_ENULP (1 << 9) /* Bit 9: Enable ULP sampling */ +#define PWR_CR3_APC (1 << 10) /* Bit 10: Apply pull-up and pull-down configuration */ +#define PWR_CR3_EIWUL (1 << 15) /* Bit 15: Enable internal wakeup line */ + +/* Power control register 4 */ + +#define PWR_CR4_WP1 (1 << 0) /* Bit 0: WKUP1 pin polarity */ +#define PWR_CR4_WP2 (1 << 1) /* Bit 1: WKUP2 pin polarity */ +#define PWR_CR4_WP3 (1 << 2) /* Bit 2: WKUP3 pin polarity */ +#define PWR_CR4_WP4 (1 << 3) /* Bit 3: WKUP4 pin polarity */ +#define PWR_CR4_WP5 (1 << 4) /* Bit 4: WKUP5 pin polarity */ +#define PWR_CR4_WP7 (1 << 6) /* Bit 6: WKUP7 pin polarity */ +#define PWR_CR4_VBE (1 << 8) /* Bit 8: VBAT charging enable */ +#define PWR_CR4_VBRS (1 << 9) /* Bit 9: VBAT charging resistor selection */ +# define PWR_CR4_VBRS_5k 0 /* 0: 5k resistor */ +# define PWR_CR4_VBRS_1k5 PWR_CR4_VBRS /* 1: 1k5 resistor */ + +/* Power status register 1 */ + +#define PWR_SR1_WUF1 (1 << 0) /* Bit 0: Wakeup flag 1 */ +#define PWR_SR1_WUF2 (1 << 1) /* Bit 1: Wakeup flag 2 */ +#define PWR_SR1_WUF3 (1 << 2) /* Bit 2: Wakeup flag 3 */ +#define PWR_SR1_WUF4 (1 << 3) /* Bit 3: Wakeup flag 4 */ +#define PWR_SR1_WUF5 (1 << 4) /* Bit 4: Wakeup flag 5 */ +#define PWR_SR1_WUF7 (1 << 6) /* Bit 6: Wakeup flag 7 */ +#define PWR_SR1_SBF (1 << 8) /* Bit 8: Standby flag */ +#define PWR_SR1_STOPF_SHIFT (9) /* Bits 9-11: Stop flags */ +#define PWR_SR1_STOPF_MASK (7 << PWR_SR1_STOPF_SHIFT) +#define PWR_SR1_WUFI (1 << 15) /* Bit 15: Wakeup internal flag */ + +/* Power status register 2 */ + +#define PWR_SR2_FLASHRDY (1 << 7) /* Bit 7: Flash ready flag */ +#define PWR_SR2_REGLPS (1 << 8) /* Bit 8: Low-power regulator started */ +#define PWR_SR2_REGLPF (1 << 9) /* Bit 9: Low-power regulator flag */ +#define PWR_SR2_VOSF (1 << 10) /* Bit 10: Voltage scaling flag */ +#define PWR_SR2_PVDO (1 << 11) /* Bit 11: PVD output */ +#define PWR_SR2_PVMO1 (1 << 12) /* Bit 12: PVM VDDUSB output */ +#define PWR_SR2_PVMO3 (1 << 14) /* Bit 14: PVM VDDADC output */ +#define PWR_SR2_PVMO4 (1 << 15) /* Bit 15: PVM VDDDAC output */ + +/* Power status clear register */ + +#define PWR_SCR_CWUF1 (1 << 0) /* Bit 0: Clear wakeup flag 1 */ +#define PWR_SCR_CWUF2 (1 << 1) /* Bit 1: Clear wakeup flag 2 */ +#define PWR_SCR_CWUF3 (1 << 2) /* Bit 2: Clear wakeup flag 3 */ +#define PWR_SCR_CWUF4 (1 << 3) /* Bit 3: Clear wakeup flag 4 */ +#define PWR_SCR_CWUF5 (1 << 4) /* Bit 4: Clear wakeup flag 5 */ +#define PWR_SCR_CWUF7 (1 << 6) /* Bit 6: Clear wakeup flag 7 */ +#define PWR_SCR_CSBF (1 << 8) /* Bit 8: Clear standby flag */ + +#endif /* __ARCH_ARM_SRC_STM32U0_HARDWARE_STM32U0_PWR_H */ diff --git a/arch/arm/src/stm32u0/hardware/stm32u0_rcc.h b/arch/arm/src/stm32u0/hardware/stm32u0_rcc.h new file mode 100644 index 00000000000..14873641064 --- /dev/null +++ b/arch/arm/src/stm32u0/hardware/stm32u0_rcc.h @@ -0,0 +1,611 @@ +/**************************************************************************** + * arch/arm/src/stm32u0/hardware/stm32u0_rcc.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32U0_HARDWARE_STM32U0_RCC_H +#define __ARCH_ARM_SRC_STM32U0_HARDWARE_STM32U0_RCC_H + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register Offsets *********************************************************/ + +#define STM32_RCC_CR_OFFSET 0x0000 /* Clock control register */ +#define STM32_RCC_ICSCR_OFFSET 0x0004 /* Internal clock sources calibration register */ +#define STM32_RCC_CFGR_OFFSET 0x0008 /* Clock configuration register */ +#define STM32_RCC_PLLCFG_OFFSET 0x000c /* PLL clock configuration register */ +#define STM32_RCC_CIER_OFFSET 0x0018 /* Clock interrupt enable register */ +#define STM32_RCC_CIFR_OFFSET 0x001c /* Clock interrupt flag register */ +#define STM32_RCC_CICR_OFFSET 0x0020 /* Clock interrupt clear register */ +#define STM32_RCC_AHBRSTR_OFFSET 0x0028 /* AHB peripheral reset register */ +#define STM32_RCC_IOPRSTR_OFFSET 0x002c /* GPIO reset register */ +#define STM32_RCC_APB1RSTR_OFFSET 0x0038 /* APB1 peripheral reset register (APBRSTR1) */ +#define STM32_RCC_APB2RSTR_OFFSET 0x0040 /* APB2 peripheral reset register (APBRSTR2) */ +#define STM32_RCC_AHBENR_OFFSET 0x0048 /* AHB peripheral clock enable register */ +#define STM32_RCC_IOPENR_OFFSET 0x004c /* GPIO clock enable register */ +#define STM32_RCC_DBGCFGR_OFFSET 0x0050 /* Debug configuration register */ +#define STM32_RCC_APB1ENR_OFFSET 0x0058 /* APB1 peripheral clock enable register (APBENR1) */ +#define STM32_RCC_APB2ENR_OFFSET 0x0060 /* APB2 peripheral clock enable register (APBENR2) */ +#define STM32_RCC_AHBSMENR_OFFSET 0x0068 /* AHB peripheral clock enable in Sleep mode register */ +#define STM32_RCC_IOPSMENR_OFFSET 0x006c /* GPIO clock enable in Sleep mode register */ +#define STM32_RCC_APB1SMENR_OFFSET 0x0078 /* APB1 peripheral clock enable in Sleep mode register */ +#define STM32_RCC_APB2SMENR_OFFSET 0x0080 /* APB2 peripheral clock enable in Sleep mode register */ +#define STM32_RCC_CCIPR_OFFSET 0x0088 /* Peripherals independent clock configuration register */ +#define STM32_RCC_BDCR_OFFSET 0x0090 /* RTC domain control register */ +#define STM32_RCC_CSR_OFFSET 0x0094 /* Control/status register */ +#define STM32_RCC_CRRCR_OFFSET 0x0098 /* Clock recovery RC register */ + +/* Register Addresses *******************************************************/ + +#define STM32_RCC_CR (STM32_RCC_BASE+STM32_RCC_CR_OFFSET) +#define STM32_RCC_ICSCR (STM32_RCC_BASE+STM32_RCC_ICSCR_OFFSET) +#define STM32_RCC_CFGR (STM32_RCC_BASE+STM32_RCC_CFGR_OFFSET) +#define STM32_RCC_PLLCFG (STM32_RCC_BASE+STM32_RCC_PLLCFG_OFFSET) +#define STM32_RCC_CIER (STM32_RCC_BASE+STM32_RCC_CIER_OFFSET) +#define STM32_RCC_CIFR (STM32_RCC_BASE+STM32_RCC_CIFR_OFFSET) +#define STM32_RCC_CICR (STM32_RCC_BASE+STM32_RCC_CICR_OFFSET) +#define STM32_RCC_AHBRSTR (STM32_RCC_BASE+STM32_RCC_AHBRSTR_OFFSET) +#define STM32_RCC_IOPRSTR (STM32_RCC_BASE+STM32_RCC_IOPRSTR_OFFSET) +#define STM32_RCC_APB1RSTR (STM32_RCC_BASE+STM32_RCC_APB1RSTR_OFFSET) +#define STM32_RCC_APB2RSTR (STM32_RCC_BASE+STM32_RCC_APB2RSTR_OFFSET) +#define STM32_RCC_AHBENR (STM32_RCC_BASE+STM32_RCC_AHBENR_OFFSET) +#define STM32_RCC_IOPENR (STM32_RCC_BASE+STM32_RCC_IOPENR_OFFSET) +#define STM32_RCC_DBGCFGR (STM32_RCC_BASE+STM32_RCC_DBGCFGR_OFFSET) +#define STM32_RCC_APB1ENR (STM32_RCC_BASE+STM32_RCC_APB1ENR_OFFSET) +#define STM32_RCC_APB2ENR (STM32_RCC_BASE+STM32_RCC_APB2ENR_OFFSET) +#define STM32_RCC_AHBSMENR (STM32_RCC_BASE+STM32_RCC_AHBSMENR_OFFSET) +#define STM32_RCC_IOPSMENR (STM32_RCC_BASE+STM32_RCC_IOPSMENR_OFFSET) +#define STM32_RCC_APB1SMENR (STM32_RCC_BASE+STM32_RCC_APB1SMENR_OFFSET) +#define STM32_RCC_APB2SMENR (STM32_RCC_BASE+STM32_RCC_APB2SMENR_OFFSET) +#define STM32_RCC_CCIPR (STM32_RCC_BASE+STM32_RCC_CCIPR_OFFSET) +#define STM32_RCC_BDCR (STM32_RCC_BASE+STM32_RCC_BDCR_OFFSET) +#define STM32_RCC_CSR (STM32_RCC_BASE+STM32_RCC_CSR_OFFSET) +#define STM32_RCC_CRRCR (STM32_RCC_BASE+STM32_RCC_CRRCR_OFFSET) + +/* Register Bitfield Definitions ********************************************/ + +/* Clock control register */ + +#define RCC_CR_MSION (1 << 0) /* Bit 0: MSI clock enable */ +#define RCC_CR_MSIRDY (1 << 1) /* Bit 1: MSI clock ready flag */ +#define RCC_CR_MSIPLLEN (1 << 2) /* Bit 2: MSI clock PLL enable */ +#define RCC_CR_MSIRGSEL (1 << 3) /* Bit 3: MSI clock range selection */ +#define RCC_CR_MSIRANGE_SHIFT (4) /* Bits 4-7: MSI clock ranges */ +#define RCC_CR_MSIRANGE_MASK (0x0f << RCC_CR_MSIRANGE_SHIFT) +# define RCC_CR_MSIRANGE_0 (0 << RCC_CR_MSIRANGE_SHIFT) /* 100 kHz */ +# define RCC_CR_MSIRANGE_1 (1 << RCC_CR_MSIRANGE_SHIFT) /* 200 kHz */ +# define RCC_CR_MSIRANGE_2 (2 << RCC_CR_MSIRANGE_SHIFT) /* 400 kHz */ +# define RCC_CR_MSIRANGE_3 (3 << RCC_CR_MSIRANGE_SHIFT) /* 800 kHz */ +# define RCC_CR_MSIRANGE_4 (4 << RCC_CR_MSIRANGE_SHIFT) /* 1 MHz */ +# define RCC_CR_MSIRANGE_5 (5 << RCC_CR_MSIRANGE_SHIFT) /* 2 MHz */ +# define RCC_CR_MSIRANGE_6 (6 << RCC_CR_MSIRANGE_SHIFT) /* 4 MHz */ +# define RCC_CR_MSIRANGE_7 (7 << RCC_CR_MSIRANGE_SHIFT) /* 8 MHz */ +# define RCC_CR_MSIRANGE_8 (8 << RCC_CR_MSIRANGE_SHIFT) /* 16 MHz */ +# define RCC_CR_MSIRANGE_9 (9 << RCC_CR_MSIRANGE_SHIFT) /* 24 MHz */ +# define RCC_CR_MSIRANGE_10 (10 << RCC_CR_MSIRANGE_SHIFT) /* 32 MHz */ +# define RCC_CR_MSIRANGE_11 (11 << RCC_CR_MSIRANGE_SHIFT) /* 48 MHz */ +#define RCC_CR_HSION (1 << 8) /* Bit 8: HSI16 clock enable */ +#define RCC_CR_HSIKERON (1 << 9) /* Bit 9: HSI16 clock enable for some IP kernels */ +#define RCC_CR_HSIRDY (1 << 10) /* Bit 10: HSI16 clock ready flag */ +#define RCC_CR_HSIASFS (1 << 11) /* Bit 11: HSI16 automatic start from Stop */ + /* Bits 12-15: Reserved */ +#define RCC_CR_HSEON (1 << 16) /* Bit 16: HSE clock enable */ +#define RCC_CR_HSERDY (1 << 17) /* Bit 17: HSE clock ready flag */ +#define RCC_CR_HSEBYP (1 << 18) /* Bit 18: HSE clock bypass */ +#define RCC_CR_CSSON (1 << 19) /* Bit 19: HSE clock security system enable */ + /* Bits 20-23: Reserved */ +#define RCC_CR_PLLON (1 << 24) /* Bit 24: PLL enable */ +#define RCC_CR_PLLRDY (1 << 25) /* Bit 25: PLL clock ready flag */ + /* Bits 26-31: Reserved */ + +/* Internal clock sources calibration register */ + +#define RCC_ICSCR_MSICAL_SHIFT (0) /* Bits 0-7: MSI clock calibration */ +#define RCC_ICSCR_MSICAL_MASK (0xff << RCC_ICSCR_MSICAL_SHIFT) +#define RCC_ICSCR_MSITRIM_SHIFT (8) /* Bits 8-15: MSI clock trimming */ +#define RCC_ICSCR_MSITRIM_MASK (0xff << RCC_ICSCR_MSITRIM_SHIFT) +#define RCC_ICSCR_HSICAL_SHIFT (16) /* Bits 16-23: HSI16 clock calibration */ +#define RCC_ICSCR_HSICAL_MASK (0xff << RCC_ICSCR_HSICAL_SHIFT) +#define RCC_ICSCR_HSITRIM_SHIFT (24) /* Bits 24-30: HSI16 clock trimming */ +#define RCC_ICSCR_HSITRIM_MASK (0x7f << RCC_ICSCR_HSITRIM_SHIFT) + +/* Clock configuration register */ + +#define RCC_CFGR_SW_SHIFT (0) /* Bits 0-2: System clock switch */ +#define RCC_CFGR_SW_MASK (7 << RCC_CFGR_SW_SHIFT) +# define RCC_CFGR_SW_MSI (0 << RCC_CFGR_SW_SHIFT) /* 000: MSI */ +# define RCC_CFGR_SW_HSI (1 << RCC_CFGR_SW_SHIFT) /* 001: HSI16 */ +# define RCC_CFGR_SW_HSE (2 << RCC_CFGR_SW_SHIFT) /* 010: HSE */ +# define RCC_CFGR_SW_PLL (3 << RCC_CFGR_SW_SHIFT) /* 011: PLLRCLK */ +# define RCC_CFGR_SW_LSI (4 << RCC_CFGR_SW_SHIFT) /* 100: LSI */ +# define RCC_CFGR_SW_LSE (5 << RCC_CFGR_SW_SHIFT) /* 101: LSE */ +#define RCC_CFGR_SWS_SHIFT (3) /* Bits 3-5: System clock switch status */ +#define RCC_CFGR_SWS_MASK (7 << RCC_CFGR_SWS_SHIFT) +# define RCC_CFGR_SWS_MSI (0 << RCC_CFGR_SWS_SHIFT) /* 000: MSI */ +# define RCC_CFGR_SWS_HSI (1 << RCC_CFGR_SWS_SHIFT) /* 001: HSI16 */ +# define RCC_CFGR_SWS_HSE (2 << RCC_CFGR_SWS_SHIFT) /* 010: HSE */ +# define RCC_CFGR_SWS_PLL (3 << RCC_CFGR_SWS_SHIFT) /* 011: PLLRCLK */ +# define RCC_CFGR_SWS_LSI (4 << RCC_CFGR_SWS_SHIFT) /* 100: LSI */ +# define RCC_CFGR_SWS_LSE (5 << RCC_CFGR_SWS_SHIFT) /* 101: LSE */ + /* Bits 6-7: Reserved */ +#define RCC_CFGR_HPRE_SHIFT (8) /* Bits 8-11: AHB prescaler */ +#define RCC_CFGR_HPRE_MASK (0x0f << RCC_CFGR_HPRE_SHIFT) +# define RCC_CFGR_HPRE_SYSCLK (0 << RCC_CFGR_HPRE_SHIFT) /* 0xxx: SYSCLK not divided */ +# define RCC_CFGR_HPRE_SYSCLKd2 (8 << RCC_CFGR_HPRE_SHIFT) /* 1000: SYSCLK divided by 2 */ +# define RCC_CFGR_HPRE_SYSCLKd4 (9 << RCC_CFGR_HPRE_SHIFT) /* 1001: SYSCLK divided by 4 */ +# define RCC_CFGR_HPRE_SYSCLKd8 (10 << RCC_CFGR_HPRE_SHIFT) /* 1010: SYSCLK divided by 8 */ +# define RCC_CFGR_HPRE_SYSCLKd16 (11 << RCC_CFGR_HPRE_SHIFT) /* 1011: SYSCLK divided by 16 */ +# define RCC_CFGR_HPRE_SYSCLKd64 (12 << RCC_CFGR_HPRE_SHIFT) /* 1100: SYSCLK divided by 64 */ +# define RCC_CFGR_HPRE_SYSCLKd128 (13 << RCC_CFGR_HPRE_SHIFT) /* 1101: SYSCLK divided by 128 */ +# define RCC_CFGR_HPRE_SYSCLKd256 (14 << RCC_CFGR_HPRE_SHIFT) /* 1110: SYSCLK divided by 256 */ +# define RCC_CFGR_HPRE_SYSCLKd512 (15 << RCC_CFGR_HPRE_SHIFT) /* 1111: SYSCLK divided by 512 */ +#define RCC_CFGR_PPRE1_SHIFT (12) /* Bits 12-14: APB prescaler (PPRE) */ +#define RCC_CFGR_PPRE1_MASK (7 << RCC_CFGR_PPRE1_SHIFT) +# define RCC_CFGR_PPRE1_HCLK (0 << RCC_CFGR_PPRE1_SHIFT) /* 0xx: HCLK not divided */ +# define RCC_CFGR_PPRE1_HCLKd2 (4 << RCC_CFGR_PPRE1_SHIFT) /* 100: HCLK divided by 2 */ +# define RCC_CFGR_PPRE1_HCLKd4 (5 << RCC_CFGR_PPRE1_SHIFT) /* 101: HCLK divided by 4 */ +# define RCC_CFGR_PPRE1_HCLKd8 (6 << RCC_CFGR_PPRE1_SHIFT) /* 110: HCLK divided by 8 */ +# define RCC_CFGR_PPRE1_HCLKd16 (7 << RCC_CFGR_PPRE1_SHIFT) /* 111: HCLK divided by 16 */ +#define RCC_CFGR_STOPWUCK (1 << 15) /* Bit 15: Wakeup from Stop and CSS backup clock selection */ +#define RCC_CFGR_MCO2SEL_SHIFT (16) /* Bits 16-19: MCO2 clock output selection */ +#define RCC_CFGR_MCO2SEL_MASK (0x0f << RCC_CFGR_MCO2SEL_SHIFT) +#define RCC_CFGR_MCO2PRE_SHIFT (20) /* Bits 20-23: MCO2 prescaler */ +#define RCC_CFGR_MCO2PRE_MASK (0x0f << RCC_CFGR_MCO2PRE_SHIFT) +#define RCC_CFGR_MCO1SEL_SHIFT (24) /* Bits 24-27: MCO1 clock output selection */ +#define RCC_CFGR_MCO1SEL_MASK (0x0f << RCC_CFGR_MCO1SEL_SHIFT) +#define RCC_CFGR_MCO1PRE_SHIFT (28) /* Bits 28-31: MCO1 prescaler */ +#define RCC_CFGR_MCO1PRE_MASK (0x0f << RCC_CFGR_MCO1PRE_SHIFT) + +/* Compatibility aliases for MCO (MCO1) */ + +#define RCC_CFGR_MCOSEL_SHIFT RCC_CFGR_MCO1SEL_SHIFT +#define RCC_CFGR_MCOSEL_MASK RCC_CFGR_MCO1SEL_MASK +#define RCC_CFGR_MCOPRE_SHIFT RCC_CFGR_MCO1PRE_SHIFT +#define RCC_CFGR_MCOPRE_MASK RCC_CFGR_MCO1PRE_MASK + +/* PLL clock configuration register */ + +#define RCC_PLLCFG_PLLSRC_SHIFT (0) /* Bits 0-1: PLL entry clock source */ +#define RCC_PLLCFG_PLLSRC_MASK (3 << RCC_PLLCFG_PLLSRC_SHIFT) +# define RCC_PLLCFG_PLLSRC_NOCLK (0 << RCC_PLLCFG_PLLSRC_SHIFT) /* 00: No clock */ +# define RCC_PLLCFG_PLLSRC_MSI (1 << RCC_PLLCFG_PLLSRC_SHIFT) /* 01: MSI */ +# define RCC_PLLCFG_PLLSRC_HSI (2 << RCC_PLLCFG_PLLSRC_SHIFT) /* 10: HSI16 */ +# define RCC_PLLCFG_PLLSRC_HSE (3 << RCC_PLLCFG_PLLSRC_SHIFT) /* 11: HSE */ +#define RCC_PLLCFG_PLLM_SHIFT (4) /* Bits 4-6: Division factor M of the PLL input clock divider */ +#define RCC_PLLCFG_PLLM_MASK (7 << RCC_PLLCFG_PLLM_SHIFT) +#define RCC_PLLCFG_PLLM(n) ((n-1) << RCC_PLLCFG_PLLM_SHIFT) /* n=1,...,8 */ + /* Bit 7: Reserved */ +#define RCC_PLLCFG_PLLN_SHIFT (8) /* Bits 8-14: PLL frequency multiplication factor N */ +#define RCC_PLLCFG_PLLN_MASK (0x7f << RCC_PLLCFG_PLLN_SHIFT) +#define RCC_PLLCFG_PLLN(n) ((n) << RCC_PLLCFG_PLLN_SHIFT) /* n=4,...,127 */ + /* Bit 15: Reserved */ +#define RCC_PLLCFG_PLLPEN (1 << 16) /* Bit 16: PLLPCLK clock output enable */ +#define RCC_PLLCFG_PLLP_SHIFT (17) /* Bits 17-21: PLL VCO division factor P for PLLPCLK clock output */ +#define RCC_PLLCFG_PLLP_MASK (0x1f << RCC_PLLCFG_PLLP_SHIFT) +#define RCC_PLLCFG_PLLP(n) ((n-1) << RCC_PLLCFG_PLLP_SHIFT) /* n=2,...,32 */ + /* Bits 22-23: Reserved */ +#define RCC_PLLCFG_PLLQEN (1 << 24) /* Bit 24: PLLQCLK clock output enable */ +#define RCC_PLLCFG_PLLQ_SHIFT (25) /* Bits 25-27: PLL VCO division factor Q for PLLQCLK clock output */ +#define RCC_PLLCFG_PLLQ_MASK (7 << RCC_PLLCFG_PLLQ_SHIFT) +#define RCC_PLLCFG_PLLQ(n) ((n-1) << RCC_PLLCFG_PLLQ_SHIFT) /* n=2,...,8 */ +#define RCC_PLLCFG_PLLREN (1 << 28) /* Bit 28: PLLRCLK clock output enable */ +#define RCC_PLLCFG_PLLR_SHIFT (29) /* Bits 29-31: PLL VCO division factor R for PLLRCLK clock output */ +#define RCC_PLLCFG_PLLR_MASK (7 << RCC_PLLCFG_PLLR_SHIFT) +#define RCC_PLLCFG_PLLR(n) ((n-1) << RCC_PLLCFG_PLLR_SHIFT) /* n=2,...,8 */ + +/* Clock interrupt enable register */ + +#define RCC_CIER_LSIRDYIE (1 << 0) /* Bit 0: LSI ready interrupt enable */ +#define RCC_CIER_LSERDYIE (1 << 1) /* Bit 1: LSE ready interrupt enable */ +#define RCC_CIER_MSIRDYIE (1 << 2) /* Bit 2: MSI ready interrupt enable */ +#define RCC_CIER_HSIRDYIE (1 << 3) /* Bit 3: HSI16 ready interrupt enable */ +#define RCC_CIER_HSERDYIE (1 << 4) /* Bit 4: HSE ready interrupt enable */ +#define RCC_CIER_PLLRDYIE (1 << 5) /* Bit 5: PLL ready interrupt enable */ + /* Bits 6-8: Reserved */ +#define RCC_CIER_LSECSSIE (1 << 9) /* Bit 9: LSE clock security system interrupt enable */ +#define RCC_CIER_HSI48RDYIE (1 << 10) /* Bit 10: HSI48 ready interrupt enable */ + +/* Clock interrupt flag register */ + +#define RCC_CIFR_LSIRDYF (1 << 0) /* Bit 0: LSI ready interrupt flag */ +#define RCC_CIFR_LSERDYF (1 << 1) /* Bit 1: LSE ready interrupt flag */ +#define RCC_CIFR_MSIRDYF (1 << 2) /* Bit 2: MSI ready interrupt flag */ +#define RCC_CIFR_HSIRDYF (1 << 3) /* Bit 3: HSI16 ready interrupt flag */ +#define RCC_CIFR_HSERDYF (1 << 4) /* Bit 4: HSE ready interrupt flag */ +#define RCC_CIFR_PLLRDYF (1 << 5) /* Bit 5: PLL ready interrupt flag */ + /* Bits 6-7: Reserved */ +#define RCC_CIFR_CSSF (1 << 8) /* Bit 8: HSE clock security system interrupt flag */ +#define RCC_CIFR_LSECSSF (1 << 9) /* Bit 9: LSE clock security system interrupt flag */ +#define RCC_CIFR_HSI48RDYF (1 << 10) /* Bit 10: HSI48 ready interrupt flag */ + +/* Clock interrupt clear register */ + +#define RCC_CICR_LSIRDYC (1 << 0) /* Bit 0: LSI ready interrupt clear */ +#define RCC_CICR_LSERDYC (1 << 1) /* Bit 1: LSE ready interrupt clear */ +#define RCC_CICR_MSIRDYC (1 << 2) /* Bit 2: MSI ready interrupt clear */ +#define RCC_CICR_HSIRDYC (1 << 3) /* Bit 3: HSI16 ready interrupt clear */ +#define RCC_CICR_HSERDYC (1 << 4) /* Bit 4: HSE ready interrupt clear */ +#define RCC_CICR_PLLRDYC (1 << 5) /* Bit 5: PLL ready interrupt clear */ + /* Bits 6-7: Reserved */ +#define RCC_CICR_CSSC (1 << 8) /* Bit 8: HSE clock security system interrupt clear */ +#define RCC_CICR_LSECSSC (1 << 9) /* Bit 9: LSE clock security system interrupt clear */ +#define RCC_CICR_HSI48RDYC (1 << 10) /* Bit 10: HSI48 ready interrupt clear */ + +/* AHB peripheral reset register */ + +#define RCC_AHBRSTR_DMA1RST (1 << 0) /* Bit 0: DMA1 reset */ +#define RCC_AHBRSTR_DMA2RST (1 << 1) /* Bit 1: DMA2 reset */ + /* Bits 2-7: Reserved */ +#define RCC_AHBRSTR_FLASHRST (1 << 8) /* Bit 8: Flash memory interface reset */ + /* Bits 9-11: Reserved */ +#define RCC_AHBRSTR_CRCRST (1 << 12) /* Bit 12: CRC reset */ + /* Bits 13-15: Reserved */ +#define RCC_AHBRSTR_AESRST (1 << 16) /* Bit 16: AES hardware accelerator reset */ + /* Bit 17: Reserved */ +#define RCC_AHBRSTR_RNGRST (1 << 18) /* Bit 18: Random number generator reset */ + /* Bits 19-23: Reserved */ +#define RCC_AHBRSTR_TSCRST (1 << 24) /* Bit 24: Touch sensing controller reset */ + /* Bits 25-31: Reserved */ + +/* GPIO reset register */ + +#define RCC_IOPRSTR_IOPARST (1 << 0) /* Bit 0: IO port A reset */ +#define RCC_IOPRSTR_IOPBRST (1 << 1) /* Bit 1: IO port B reset */ +#define RCC_IOPRSTR_IOPCRST (1 << 2) /* Bit 2: IO port C reset */ +#define RCC_IOPRSTR_IOPDRST (1 << 3) /* Bit 3: IO port D reset */ +#define RCC_IOPRSTR_IOPERST (1 << 4) /* Bit 4: IO port E reset */ +#define RCC_IOPRSTR_IOPFRST (1 << 5) /* Bit 5: IO port F reset */ + +/* APB1 peripheral reset register (APBRSTR1) */ + +#define RCC_APB1RSTR_TIM2RST (1 << 0) /* Bit 0: Timer 2 reset */ +#define RCC_APB1RSTR_TIM3RST (1 << 1) /* Bit 1: Timer 3 reset */ + /* Bits 2-3: Reserved */ +#define RCC_APB1RSTR_TIM6RST (1 << 4) /* Bit 4: Timer 6 reset */ +#define RCC_APB1RSTR_TIM7RST (1 << 5) /* Bit 5: Timer 7 reset */ + /* Bit 6: Reserved */ +#define RCC_APB1RSTR_LPUART2RST (1 << 7) /* Bit 7: Low-power UART 2 reset */ + /* Bit 8: Reserved */ +#define RCC_APB1RSTR_LCDRST (1 << 9) /* Bit 9: LCD controller reset */ + /* Bits 10-11: Reserved */ +#define RCC_APB1RSTR_LPUART3RST (1 << 12) /* Bit 12: Low-power UART 3 reset */ +#define RCC_APB1RSTR_USBRST (1 << 13) /* Bit 13: USB reset */ +#define RCC_APB1RSTR_SPI2RST (1 << 14) /* Bit 14: SPI2 reset */ +#define RCC_APB1RSTR_SPI3RST (1 << 15) /* Bit 15: SPI3 reset */ +#define RCC_APB1RSTR_CRSRST (1 << 16) /* Bit 16: CRS reset */ +#define RCC_APB1RSTR_USART2RST (1 << 17) /* Bit 17: USART2 reset */ +#define RCC_APB1RSTR_USART3RST (1 << 18) /* Bit 18: USART3 reset */ +#define RCC_APB1RSTR_USART4RST (1 << 19) /* Bit 19: USART4 reset */ +#define RCC_APB1RSTR_LPUART1RST (1 << 20) /* Bit 20: Low-power UART 1 reset */ +#define RCC_APB1RSTR_I2C1RST (1 << 21) /* Bit 21: I2C1 reset */ +#define RCC_APB1RSTR_I2C2RST (1 << 22) /* Bit 22: I2C2 reset */ +#define RCC_APB1RSTR_I2C3RST (1 << 23) /* Bit 23: I2C3 reset */ +#define RCC_APB1RSTR_OPAMPRST (1 << 24) /* Bit 24: OPAMP reset */ +#define RCC_APB1RSTR_I2C4RST (1 << 25) /* Bit 25: I2C4 reset */ +#define RCC_APB1RSTR_LPTIM3RST (1 << 26) /* Bit 26: Low-power timer 3 reset */ + /* Bit 27: Reserved */ +#define RCC_APB1RSTR_PWRRST (1 << 28) /* Bit 28: PWR reset */ +#define RCC_APB1RSTR_DAC1RST (1 << 29) /* Bit 29: DAC1 reset */ +#define RCC_APB1RSTR_LPTIM2RST (1 << 30) /* Bit 30: Low-power timer 2 reset */ +#define RCC_APB1RSTR_LPTIM1RST (1 << 31) /* Bit 31: Low-power timer 1 reset */ + +/* APB2 peripheral reset register (APBRSTR2) */ + +#define RCC_APB2RSTR_SYSCFGRST (1 << 0) /* Bit 0: SYSCFG reset */ + /* Bits 1-10: Reserved */ +#define RCC_APB2RSTR_TIM1RST (1 << 11) /* Bit 11: TIM1 timer reset */ +#define RCC_APB2RSTR_SPI1RST (1 << 12) /* Bit 12: SPI1 reset */ + /* Bit 13: Reserved */ +#define RCC_APB2RSTR_USART1RST (1 << 14) /* Bit 14: USART1 reset */ + /* Bit 15: Reserved */ +#define RCC_APB2RSTR_TIM15RST (1 << 16) /* Bit 16: TIM15 timer reset */ +#define RCC_APB2RSTR_TIM16RST (1 << 17) /* Bit 17: TIM16 timer reset */ + /* Bits 18-19: Reserved */ +#define RCC_APB2RSTR_ADC1RST (1 << 20) /* Bit 20: ADC reset */ + +/* AHB peripheral clock enable register */ + +#define RCC_AHBENR_DMA1EN (1 << 0) /* Bit 0: DMA1 clock enable */ +#define RCC_AHBENR_DMA2EN (1 << 1) /* Bit 1: DMA2 clock enable */ + /* Bits 2-7: Reserved */ +#define RCC_AHBENR_FLASHEN (1 << 8) /* Bit 8: Flash memory interface clock enable */ + /* Bits 9-11: Reserved */ +#define RCC_AHBENR_CRCEN (1 << 12) /* Bit 12: CRC clock enable */ + /* Bits 13-15: Reserved */ +#define RCC_AHBENR_AESEN (1 << 16) /* Bit 16: AES hardware accelerator clock enable */ + /* Bit 17: Reserved */ +#define RCC_AHBENR_RNGEN (1 << 18) /* Bit 18: Random number generator clock enable */ + /* Bits 19-23: Reserved */ +#define RCC_AHBENR_TSCEN (1 << 24) /* Bit 24: Touch sensing controller clock enable */ + /* Bits 25-31: Reserved */ + +/* GPIO clock enable register */ + +#define RCC_IOPENR_IOPAEN (1 << 0) /* Bit 0: IO port A clock enable */ +#define RCC_IOPENR_IOPBEN (1 << 1) /* Bit 1: IO port B clock enable */ +#define RCC_IOPENR_IOPCEN (1 << 2) /* Bit 2: IO port C clock enable */ +#define RCC_IOPENR_IOPDEN (1 << 3) /* Bit 3: IO port D clock enable */ +#define RCC_IOPENR_IOPEEN (1 << 4) /* Bit 4: IO port E clock enable */ +#define RCC_IOPENR_IOPFEN (1 << 5) /* Bit 5: IO port F clock enable */ + +/* Debug configuration register */ + +#define RCC_DBGCFGR_DBGEN (1 << 0) /* Bit 0: Debug support clock enable */ +#define RCC_DBGCFGR_DBGRST (1 << 1) /* Bit 1: Debug support reset */ + +/* APB1 peripheral clock enable register (APBENR1) */ + +#define RCC_APB1ENR_TIM2EN (1 << 0) /* Bit 0: Timer 2 clock enable */ +#define RCC_APB1ENR_TIM3EN (1 << 1) /* Bit 1: Timer 3 clock enable */ + /* Bits 2-3: Reserved */ +#define RCC_APB1ENR_TIM6EN (1 << 4) /* Bit 4: Timer 6 clock enable */ +#define RCC_APB1ENR_TIM7EN (1 << 5) /* Bit 5: Timer 7 clock enable */ + /* Bit 6: Reserved */ +#define RCC_APB1ENR_LPUART2EN (1 << 7) /* Bit 7: Low-power UART 2 clock enable */ + /* Bit 8: Reserved */ +#define RCC_APB1ENR_LCDEN (1 << 9) /* Bit 9: LCD controller clock enable */ +#define RCC_APB1ENR_RTCAPBEN (1 << 10) /* Bit 10: RTC APB clock enable */ +#define RCC_APB1ENR_WWDGEN (1 << 11) /* Bit 11: Window watchdog clock enable */ +#define RCC_APB1ENR_LPUART3EN (1 << 12) /* Bit 12: Low-power UART 3 clock enable */ +#define RCC_APB1ENR_USBEN (1 << 13) /* Bit 13: USB clock enable */ +#define RCC_APB1ENR_SPI2EN (1 << 14) /* Bit 14: SPI2 clock enable */ +#define RCC_APB1ENR_SPI3EN (1 << 15) /* Bit 15: SPI3 clock enable */ +#define RCC_APB1ENR_CRSEN (1 << 16) /* Bit 16: CRS clock enable */ +#define RCC_APB1ENR_USART2EN (1 << 17) /* Bit 17: USART2 clock enable */ +#define RCC_APB1ENR_USART3EN (1 << 18) /* Bit 18: USART3 clock enable */ +#define RCC_APB1ENR_USART4EN (1 << 19) /* Bit 19: USART4 clock enable */ +#define RCC_APB1ENR_LPUART1EN (1 << 20) /* Bit 20: Low-power UART 1 clock enable */ +#define RCC_APB1ENR_I2C1EN (1 << 21) /* Bit 21: I2C1 clock enable */ +#define RCC_APB1ENR_I2C2EN (1 << 22) /* Bit 22: I2C2 clock enable */ +#define RCC_APB1ENR_I2C3EN (1 << 23) /* Bit 23: I2C3 clock enable */ +#define RCC_APB1ENR_OPAMPEN (1 << 24) /* Bit 24: OPAMP clock enable */ +#define RCC_APB1ENR_I2C4EN (1 << 25) /* Bit 25: I2C4 clock enable */ +#define RCC_APB1ENR_LPTIM3EN (1 << 26) /* Bit 26: Low-power timer 3 clock enable */ + /* Bit 27: Reserved */ +#define RCC_APB1ENR_PWREN (1 << 28) /* Bit 28: PWR clock enable */ +#define RCC_APB1ENR_DAC1EN (1 << 29) /* Bit 29: DAC1 clock enable */ +#define RCC_APB1ENR_LPTIM2EN (1 << 30) /* Bit 30: Low-power timer 2 clock enable */ +#define RCC_APB1ENR_LPTIM1EN (1 << 31) /* Bit 31: Low-power timer 1 clock enable */ + +/* APB2 peripheral clock enable register (APBENR2) */ + +#define RCC_APB2ENR_SYSCFGEN (1 << 0) /* Bit 0: SYSCFG clock enable */ + /* Bits 1-10: Reserved */ +#define RCC_APB2ENR_TIM1EN (1 << 11) /* Bit 11: TIM1 timer clock enable */ +#define RCC_APB2ENR_SPI1EN (1 << 12) /* Bit 12: SPI1 clock enable */ + /* Bit 13: Reserved */ +#define RCC_APB2ENR_USART1EN (1 << 14) /* Bit 14: USART1 clock enable */ + /* Bit 15: Reserved */ +#define RCC_APB2ENR_TIM15EN (1 << 16) /* Bit 16: TIM15 timer clock enable */ +#define RCC_APB2ENR_TIM16EN (1 << 17) /* Bit 17: TIM16 timer clock enable */ + /* Bits 18-19: Reserved */ +#define RCC_APB2ENR_ADC1EN (1 << 20) /* Bit 20: ADC clock enable */ + +/* AHB peripheral clock enable in Sleep mode register */ + +#define RCC_AHBSMENR_DMA1SMEN (1 << 0) /* Bit 0: DMA1 clock enable in Sleep mode */ +#define RCC_AHBSMENR_DMA2SMEN (1 << 1) /* Bit 1: DMA2 clock enable in Sleep mode */ + /* Bits 2-7: Reserved */ +#define RCC_AHBSMENR_FLASHSMEN (1 << 8) /* Bit 8: Flash memory interface clock enable in Sleep mode */ +#define RCC_AHBSMENR_SRAM1SMEN (1 << 9) /* Bit 9: SRAM1 clock enable in Sleep mode */ + /* Bits 10-11: Reserved */ +#define RCC_AHBSMENR_CRCSMEN (1 << 12) /* Bit 12: CRC clock enable in Sleep mode */ + /* Bits 13-15: Reserved */ +#define RCC_AHBSMENR_AESSMEN (1 << 16) /* Bit 16: AES clock enable in Sleep mode */ + /* Bit 17: Reserved */ +#define RCC_AHBSMENR_RNGSMEN (1 << 18) /* Bit 18: RNG clock enable in Sleep mode */ + /* Bits 19-23: Reserved */ +#define RCC_AHBSMENR_TSCSMEN (1 << 24) /* Bit 24: TSC clock enable in Sleep mode */ + +/* GPIO clock enable in Sleep mode register */ + +#define RCC_IOPSMENR_IOPASMEN (1 << 0) /* Bit 0: IO port A clock enable in Sleep mode */ +#define RCC_IOPSMENR_IOPBSMEN (1 << 1) /* Bit 1: IO port B clock enable in Sleep mode */ +#define RCC_IOPSMENR_IOPCSMEN (1 << 2) /* Bit 2: IO port C clock enable in Sleep mode */ +#define RCC_IOPSMENR_IOPDSMEN (1 << 3) /* Bit 3: IO port D clock enable in Sleep mode */ +#define RCC_IOPSMENR_IOPESMEN (1 << 4) /* Bit 4: IO port E clock enable in Sleep mode */ +#define RCC_IOPSMENR_IOPFSMEN (1 << 5) /* Bit 5: IO port F clock enable in Sleep mode */ + +/* APB1 peripheral clock enable in Sleep mode register (APBSMENR1) */ + +#define RCC_APB1SMENR_TIM2SMEN (1 << 0) /* Bit 0: Timer 2 clock enable in Sleep mode */ +#define RCC_APB1SMENR_TIM3SMEN (1 << 1) /* Bit 1: Timer 3 clock enable in Sleep mode */ + /* Bits 2-3: Reserved */ +#define RCC_APB1SMENR_TIM6SMEN (1 << 4) /* Bit 4: Timer 6 clock enable in Sleep mode */ +#define RCC_APB1SMENR_TIM7SMEN (1 << 5) /* Bit 5: Timer 7 clock enable in Sleep mode */ + /* Bit 6: Reserved */ +#define RCC_APB1SMENR_LPUART2SMEN (1 << 7) /* Bit 7: LPUART2 clock enable in Sleep mode */ + /* Bit 8: Reserved */ +#define RCC_APB1SMENR_LCDSMEN (1 << 9) /* Bit 9: LCD clock enable in Sleep mode */ +#define RCC_APB1SMENR_RTCAPBSMEN (1 << 10) /* Bit 10: RTC APB clock enable in Sleep mode */ +#define RCC_APB1SMENR_WWDGSMEN (1 << 11) /* Bit 11: WWDG clock enable in Sleep mode */ +#define RCC_APB1SMENR_LPUART3SMEN (1 << 12) /* Bit 12: LPUART3 clock enable in Sleep mode */ +#define RCC_APB1SMENR_USBSMEN (1 << 13) /* Bit 13: USB clock enable in Sleep mode */ +#define RCC_APB1SMENR_SPI2SMEN (1 << 14) /* Bit 14: SPI2 clock enable in Sleep mode */ +#define RCC_APB1SMENR_SPI3SMEN (1 << 15) /* Bit 15: SPI3 clock enable in Sleep mode */ +#define RCC_APB1SMENR_CRSSMEN (1 << 16) /* Bit 16: CRS clock enable in Sleep mode */ +#define RCC_APB1SMENR_USART2SMEN (1 << 17) /* Bit 17: USART2 clock enable in Sleep mode */ +#define RCC_APB1SMENR_USART3SMEN (1 << 18) /* Bit 18: USART3 clock enable in Sleep mode */ +#define RCC_APB1SMENR_USART4SMEN (1 << 19) /* Bit 19: USART4 clock enable in Sleep mode */ +#define RCC_APB1SMENR_LPUART1SMEN (1 << 20) /* Bit 20: LPUART1 clock enable in Sleep mode */ +#define RCC_APB1SMENR_I2C1SMEN (1 << 21) /* Bit 21: I2C1 clock enable in Sleep mode */ +#define RCC_APB1SMENR_I2C2SMEN (1 << 22) /* Bit 22: I2C2 clock enable in Sleep mode */ +#define RCC_APB1SMENR_I2C3SMEN (1 << 23) /* Bit 23: I2C3 clock enable in Sleep mode */ +#define RCC_APB1SMENR_OPAMPSMEN (1 << 24) /* Bit 24: OPAMP clock enable in Sleep mode */ +#define RCC_APB1SMENR_I2C4SMEN (1 << 25) /* Bit 25: I2C4 clock enable in Sleep mode */ +#define RCC_APB1SMENR_LPTIM3SMEN (1 << 26) /* Bit 26: LPTIM3 clock enable in Sleep mode */ + /* Bit 27: Reserved */ +#define RCC_APB1SMENR_PWRSMEN (1 << 28) /* Bit 28: PWR clock enable in Sleep mode */ +#define RCC_APB1SMENR_DAC1SMEN (1 << 29) /* Bit 29: DAC1 clock enable in Sleep mode */ +#define RCC_APB1SMENR_LPTIM2SMEN (1 << 30) /* Bit 30: LPTIM2 clock enable in Sleep mode */ +#define RCC_APB1SMENR_LPTIM1SMEN (1 << 31) /* Bit 31: LPTIM1 clock enable in Sleep mode */ + +/* APB2 peripheral clock enable in Sleep mode register (APBSMENR2) */ + +#define RCC_APB2SMENR_SYSCFGSMEN (1 << 0) /* Bit 0: SYSCFG clock enable in Sleep mode */ + /* Bits 1-10: Reserved */ +#define RCC_APB2SMENR_TIM1SMEN (1 << 11) /* Bit 11: TIM1 clock enable in Sleep mode */ +#define RCC_APB2SMENR_SPI1SMEN (1 << 12) /* Bit 12: SPI1 clock enable in Sleep mode */ + /* Bit 13: Reserved */ +#define RCC_APB2SMENR_USART1SMEN (1 << 14) /* Bit 14: USART1 clock enable in Sleep mode */ + /* Bit 15: Reserved */ +#define RCC_APB2SMENR_TIM15SMEN (1 << 16) /* Bit 16: TIM15 clock enable in Sleep mode */ +#define RCC_APB2SMENR_TIM16SMEN (1 << 17) /* Bit 17: TIM16 clock enable in Sleep mode */ + /* Bits 18-19: Reserved */ +#define RCC_APB2SMENR_ADC1SMEN (1 << 20) /* Bit 20: ADC clock enable in Sleep mode */ + +/* Peripherals independent clock configuration register */ + +#define RCC_CCIPR_USART1SEL_SHIFT (0) /* Bits 0-1: USART1 clock source selection */ +#define RCC_CCIPR_USART1SEL_MASK (3 << RCC_CCIPR_USART1SEL_SHIFT) +# define RCC_CCIPR_USART1SEL_PCLK (0 << RCC_CCIPR_USART1SEL_SHIFT) +# define RCC_CCIPR_USART1SEL_SYSCLK (1 << RCC_CCIPR_USART1SEL_SHIFT) +# define RCC_CCIPR_USART1SEL_HSI16 (2 << RCC_CCIPR_USART1SEL_SHIFT) +# define RCC_CCIPR_USART1SEL_LSE (3 << RCC_CCIPR_USART1SEL_SHIFT) +#define RCC_CCIPR_USART2SEL_SHIFT (2) /* Bits 2-3: USART2 clock source selection */ +#define RCC_CCIPR_USART2SEL_MASK (3 << RCC_CCIPR_USART2SEL_SHIFT) +# define RCC_CCIPR_USART2SEL_PCLK (0 << RCC_CCIPR_USART2SEL_SHIFT) +# define RCC_CCIPR_USART2SEL_SYSCLK (1 << RCC_CCIPR_USART2SEL_SHIFT) +# define RCC_CCIPR_USART2SEL_HSI16 (2 << RCC_CCIPR_USART2SEL_SHIFT) +# define RCC_CCIPR_USART2SEL_LSE (3 << RCC_CCIPR_USART2SEL_SHIFT) + /* Bits 4-5: Reserved */ +#define RCC_CCIPR_LPUART3SEL_SHIFT (6) /* Bits 6-7: LPUART3 clock source selection */ +#define RCC_CCIPR_LPUART3SEL_MASK (3 << RCC_CCIPR_LPUART3SEL_SHIFT) +# define RCC_CCIPR_LPUART3SEL_PCLK (0 << RCC_CCIPR_LPUART3SEL_SHIFT) +# define RCC_CCIPR_LPUART3SEL_SYSCLK (1 << RCC_CCIPR_LPUART3SEL_SHIFT) +# define RCC_CCIPR_LPUART3SEL_HSI16 (2 << RCC_CCIPR_LPUART3SEL_SHIFT) +# define RCC_CCIPR_LPUART3SEL_LSE (3 << RCC_CCIPR_LPUART3SEL_SHIFT) +#define RCC_CCIPR_LPUART2SEL_SHIFT (8) /* Bits 8-9: LPUART2 clock source selection */ +#define RCC_CCIPR_LPUART2SEL_MASK (3 << RCC_CCIPR_LPUART2SEL_SHIFT) +# define RCC_CCIPR_LPUART2SEL_PCLK (0 << RCC_CCIPR_LPUART2SEL_SHIFT) +# define RCC_CCIPR_LPUART2SEL_SYSCLK (1 << RCC_CCIPR_LPUART2SEL_SHIFT) +# define RCC_CCIPR_LPUART2SEL_HSI16 (2 << RCC_CCIPR_LPUART2SEL_SHIFT) +# define RCC_CCIPR_LPUART2SEL_LSE (3 << RCC_CCIPR_LPUART2SEL_SHIFT) +#define RCC_CCIPR_LPUART1SEL_SHIFT (10) /* Bits 10-11: LPUART1 clock source selection */ +#define RCC_CCIPR_LPUART1SEL_MASK (3 << RCC_CCIPR_LPUART1SEL_SHIFT) +# define RCC_CCIPR_LPUART1SEL_PCLK (0 << RCC_CCIPR_LPUART1SEL_SHIFT) +# define RCC_CCIPR_LPUART1SEL_SYSCLK (1 << RCC_CCIPR_LPUART1SEL_SHIFT) +# define RCC_CCIPR_LPUART1SEL_HSI16 (2 << RCC_CCIPR_LPUART1SEL_SHIFT) +# define RCC_CCIPR_LPUART1SEL_LSE (3 << RCC_CCIPR_LPUART1SEL_SHIFT) +#define RCC_CCIPR_I2C1SEL_SHIFT (12) /* Bits 12-13: I2C1 clock source selection */ +#define RCC_CCIPR_I2C1SEL_MASK (3 << RCC_CCIPR_I2C1SEL_SHIFT) +# define RCC_CCIPR_I2C1SEL_PCLK (0 << RCC_CCIPR_I2C1SEL_SHIFT) +# define RCC_CCIPR_I2C1SEL_SYSCLK (1 << RCC_CCIPR_I2C1SEL_SHIFT) +# define RCC_CCIPR_I2C1SEL_HSI16 (2 << RCC_CCIPR_I2C1SEL_SHIFT) + /* Bits 14-15: Reserved */ +#define RCC_CCIPR_I2C3SEL_SHIFT (16) /* Bits 16-17: I2C3 clock source selection */ +#define RCC_CCIPR_I2C3SEL_MASK (3 << RCC_CCIPR_I2C3SEL_SHIFT) +# define RCC_CCIPR_I2C3SEL_PCLK (0 << RCC_CCIPR_I2C3SEL_SHIFT) +# define RCC_CCIPR_I2C3SEL_SYSCLK (1 << RCC_CCIPR_I2C3SEL_SHIFT) +# define RCC_CCIPR_I2C3SEL_HSI16 (2 << RCC_CCIPR_I2C3SEL_SHIFT) +#define RCC_CCIPR_LPTIM1SEL_SHIFT (18) /* Bits 18-19: LPTIM1 clock source selection */ +#define RCC_CCIPR_LPTIM1SEL_MASK (3 << RCC_CCIPR_LPTIM1SEL_SHIFT) +# define RCC_CCIPR_LPTIM1SEL_PCLK (0 << RCC_CCIPR_LPTIM1SEL_SHIFT) +# define RCC_CCIPR_LPTIM1SEL_LSI (1 << RCC_CCIPR_LPTIM1SEL_SHIFT) +# define RCC_CCIPR_LPTIM1SEL_HSI16 (2 << RCC_CCIPR_LPTIM1SEL_SHIFT) +# define RCC_CCIPR_LPTIM1SEL_LSE (3 << RCC_CCIPR_LPTIM1SEL_SHIFT) +#define RCC_CCIPR_LPTIM2SEL_SHIFT (20) /* Bits 20-21: LPTIM2 clock source selection */ +#define RCC_CCIPR_LPTIM2SEL_MASK (3 << RCC_CCIPR_LPTIM2SEL_SHIFT) +# define RCC_CCIPR_LPTIM2SEL_PCLK (0 << RCC_CCIPR_LPTIM2SEL_SHIFT) +# define RCC_CCIPR_LPTIM2SEL_LSI (1 << RCC_CCIPR_LPTIM2SEL_SHIFT) +# define RCC_CCIPR_LPTIM2SEL_HSI16 (2 << RCC_CCIPR_LPTIM2SEL_SHIFT) +# define RCC_CCIPR_LPTIM2SEL_LSE (3 << RCC_CCIPR_LPTIM2SEL_SHIFT) +#define RCC_CCIPR_LPTIM3SEL_SHIFT (22) /* Bits 22-23: LPTIM3 clock source selection */ +#define RCC_CCIPR_LPTIM3SEL_MASK (3 << RCC_CCIPR_LPTIM3SEL_SHIFT) +# define RCC_CCIPR_LPTIM3SEL_PCLK (0 << RCC_CCIPR_LPTIM3SEL_SHIFT) +# define RCC_CCIPR_LPTIM3SEL_LSI (1 << RCC_CCIPR_LPTIM3SEL_SHIFT) +# define RCC_CCIPR_LPTIM3SEL_HSI16 (2 << RCC_CCIPR_LPTIM3SEL_SHIFT) +# define RCC_CCIPR_LPTIM3SEL_LSE (3 << RCC_CCIPR_LPTIM3SEL_SHIFT) +#define RCC_CCIPR_TIM1SEL (1 << 24) /* Bit 24: TIM1 clock source (0=TIMPCLK, 1=PLLQCLK) */ +#define RCC_CCIPR_TIM15SEL (1 << 25) /* Bit 25: TIM15 clock source (0=TIMPCLK, 1=PLLQCLK) */ +#define RCC_CCIPR_CLK48SEL_SHIFT (26) /* Bits 26-27: 48 MHz clock source selection */ +#define RCC_CCIPR_CLK48SEL_MASK (3 << RCC_CCIPR_CLK48SEL_SHIFT) +# define RCC_CCIPR_CLK48SEL_HSI48 (0 << RCC_CCIPR_CLK48SEL_SHIFT) +# define RCC_CCIPR_CLK48SEL_MSI (1 << RCC_CCIPR_CLK48SEL_SHIFT) +# define RCC_CCIPR_CLK48SEL_PLLQCLK (2 << RCC_CCIPR_CLK48SEL_SHIFT) +#define RCC_CCIPR_ADCSEL_SHIFT (28) /* Bits 28-29: ADC clock source selection */ +#define RCC_CCIPR_ADCSEL_MASK (3 << RCC_CCIPR_ADCSEL_SHIFT) +# define RCC_CCIPR_ADCSEL_SYSCLK (0 << RCC_CCIPR_ADCSEL_SHIFT) +# define RCC_CCIPR_ADCSEL_PLLPCLK (1 << RCC_CCIPR_ADCSEL_SHIFT) +# define RCC_CCIPR_ADCSEL_HSI16 (2 << RCC_CCIPR_ADCSEL_SHIFT) + +/* RTC domain control register */ + +#define RCC_BDCR_LSEON (1 << 0) /* Bit 0: LSE enable */ +#define RCC_BDCR_LSERDY (1 << 1) /* Bit 1: LSE ready */ +#define RCC_BDCR_LSEBYP (1 << 2) /* Bit 2: LSE bypass */ +#define RCC_BDCR_LSEDRV_SHIFT (3) /* Bits 3-4: LSE driving capability */ +#define RCC_BDCR_LSEDRV_MASK (3 << RCC_BDCR_LSEDRV_SHIFT) +# define RCC_BDCR_LSEDRV_LOW (0 << RCC_BDCR_LSEDRV_SHIFT) /* 00: Low */ +# define RCC_BDCR_LSEDRV_MEDLO (1 << RCC_BDCR_LSEDRV_SHIFT) /* 01: Medium low */ +# define RCC_BDCR_LSEDRV_MEDHI (2 << RCC_BDCR_LSEDRV_SHIFT) /* 10: Medium high */ +# define RCC_BDCR_LSEDRV_HIGH (3 << RCC_BDCR_LSEDRV_SHIFT) /* 11: High */ +#define RCC_BDCR_LSECSSON (1 << 5) /* Bit 5: CSS on LSE enable */ +#define RCC_BDCR_LSECSSD (1 << 6) /* Bit 6: CSS on LSE failure detection */ +#define RCC_BDCR_LSESYSEN (1 << 7) /* Bit 7: LSE clock enable for system usage */ +#define RCC_BDCR_RTCSEL_SHIFT (8) /* Bits 8-9: RTC clock source selection */ +#define RCC_BDCR_RTCSEL_MASK (3 << RCC_BDCR_RTCSEL_SHIFT) +# define RCC_BDCR_RTCSEL_NOCLK (0 << RCC_BDCR_RTCSEL_SHIFT) /* 00: No clock */ +# define RCC_BDCR_RTCSEL_LSE (1 << RCC_BDCR_RTCSEL_SHIFT) /* 01: LSE */ +# define RCC_BDCR_RTCSEL_LSI (2 << RCC_BDCR_RTCSEL_SHIFT) /* 10: LSI */ +# define RCC_BDCR_RTCSEL_HSE (3 << RCC_BDCR_RTCSEL_SHIFT) /* 11: HSE/32 */ + /* Bit 10: Reserved */ +#define RCC_BDCR_LSESYSRDY (1 << 11) /* Bit 11: LSE clock ready for system usage */ + /* Bits 12-14: Reserved */ +#define RCC_BDCR_RTCEN (1 << 15) /* Bit 15: RTC clock enable */ +#define RCC_BDCR_BDRST (1 << 16) /* Bit 16: RTC domain software reset */ + /* Bits 17-23: Reserved */ +#define RCC_BDCR_LSCOEN (1 << 24) /* Bit 24: Low-speed clock output enable */ +#define RCC_BDCR_LSCOSEL (1 << 25) /* Bit 25: Low-speed clock output selection (0=LSI, 1=LSE) */ + +/* Control/status register */ + +#define RCC_CSR_LSION (1 << 0) /* Bit 0: LSI enable */ +#define RCC_CSR_LSIRDY (1 << 1) /* Bit 1: LSI ready */ +#define RCC_CSR_LSIPREDIV (1 << 2) /* Bit 2: LSI prescaler (0=div 1, 1=div 128) */ + /* Bits 3-7: Reserved */ +#define RCC_CSR_MSISTBYRG_SHIFT (8) /* Bits 8-11: MSI range after Standby mode */ +#define RCC_CSR_MSISTBYRG_MASK (0x0f << RCC_CSR_MSISTBYRG_SHIFT) +# define RCC_CSR_MSISTBYRG_1M (4 << RCC_CSR_MSISTBYRG_SHIFT) /* 1 MHz */ +# define RCC_CSR_MSISTBYRG_2M (5 << RCC_CSR_MSISTBYRG_SHIFT) /* 2 MHz */ +# define RCC_CSR_MSISTBYRG_4M (6 << RCC_CSR_MSISTBYRG_SHIFT) /* 4 MHz */ +# define RCC_CSR_MSISTBYRG_8M (7 << RCC_CSR_MSISTBYRG_SHIFT) /* 8 MHz */ + /* Bits 12-22: Reserved */ +#define RCC_CSR_RMVF (1 << 23) /* Bit 23: Remove reset flags */ + /* Bit 24: Reserved */ +#define RCC_CSR_OBLRSTF (1 << 25) /* Bit 25: Option bytes loading reset flag */ +#define RCC_CSR_PINRSTF (1 << 26) /* Bit 26: PIN reset flag */ +#define RCC_CSR_PWRRSTF (1 << 27) /* Bit 27: BOR or POR/PDR reset flag */ +#define RCC_CSR_SFTRSTF (1 << 28) /* Bit 28: Software reset flag */ +#define RCC_CSR_IWDGRSTF (1 << 29) /* Bit 29: IWDG reset flag */ +#define RCC_CSR_WWDGRSTF (1 << 30) /* Bit 30: WWDG reset flag */ +#define RCC_CSR_LPWRRSTF (1 << 31) /* Bit 31: Low-power reset flag */ + +/* Clock recovery RC register */ + +#define RCC_CRRCR_HSI48ON (1 << 0) /* Bit 0: HSI48 clock enable */ +#define RCC_CRRCR_HSI48RDY (1 << 1) /* Bit 1: HSI48 clock ready flag */ + /* Bits 2-6: Reserved */ +#define RCC_CRRCR_HSI48CAL_SHIFT (7) /* Bits 7-15: HSI48 clock calibration */ +#define RCC_CRRCR_HSI48CAL_MASK (0x1ff << RCC_CRRCR_HSI48CAL_SHIFT) + +#endif /* __ARCH_ARM_SRC_STM32U0_HARDWARE_STM32U0_RCC_H */ diff --git a/arch/arm/src/stm32u0/hardware/stm32u0_syscfg.h b/arch/arm/src/stm32u0/hardware/stm32u0_syscfg.h new file mode 100644 index 00000000000..48ff04f9970 --- /dev/null +++ b/arch/arm/src/stm32u0/hardware/stm32u0_syscfg.h @@ -0,0 +1,356 @@ +/**************************************************************************** + * arch/arm/src/stm32u0/hardware/stm32u0_syscfg.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32U0_HARDWARE_STM32U0_SYSCFG_H +#define __ARCH_ARM_SRC_STM32U0_HARDWARE_STM32U0_SYSCFG_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include "chip.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register Offsets *********************************************************/ + +#define STM32_SYSCFG_CFGR1_OFFSET 0x0000 /* Configuration register 1 */ +#define STM32_SYSCFG_CFGR2_OFFSET 0x0018 /* Configuration register 2 */ +#define STM32_SYSCFG_SCSR_OFFSET 0x001c /* Backup SRAM control and status register */ +#define STM32_SYSCFG_SKR_OFFSET 0x0020 /* Backup SRAM key register */ +#define STM32_SYSCFG_TSCCR_OFFSET 0x0024 /* TSC comparator register */ +#define STM32_SYSCFG_ITLINE0_OFFSET 0x0080 /* Interrupt line 0 status */ +#define STM32_SYSCFG_ITLINE1_OFFSET 0x0084 /* Interrupt line 1 status */ +#define STM32_SYSCFG_ITLINE2_OFFSET 0x0088 /* Interrupt line 2 status */ +#define STM32_SYSCFG_ITLINE3_OFFSET 0x008c /* Interrupt line 3 status */ +#define STM32_SYSCFG_ITLINE4_OFFSET 0x0090 /* Interrupt line 4 status */ +#define STM32_SYSCFG_ITLINE5_OFFSET 0x0094 /* Interrupt line 5 status */ +#define STM32_SYSCFG_ITLINE6_OFFSET 0x0098 /* Interrupt line 6 status */ +#define STM32_SYSCFG_ITLINE7_OFFSET 0x009c /* Interrupt line 7 status */ +#define STM32_SYSCFG_ITLINE8_OFFSET 0x00a0 /* Interrupt line 8 status */ +#define STM32_SYSCFG_ITLINE9_OFFSET 0x00a4 /* Interrupt line 9 status */ +#define STM32_SYSCFG_ITLINE10_OFFSET 0x00a8 /* Interrupt line 10 status */ +#define STM32_SYSCFG_ITLINE11_OFFSET 0x00ac /* Interrupt line 11 status */ +#define STM32_SYSCFG_ITLINE12_OFFSET 0x00b0 /* Interrupt line 12 status */ +#define STM32_SYSCFG_ITLINE13_OFFSET 0x00b4 /* Interrupt line 13 status */ +#define STM32_SYSCFG_ITLINE14_OFFSET 0x00b8 /* Interrupt line 14 status */ +#define STM32_SYSCFG_ITLINE15_OFFSET 0x00bc /* Interrupt line 15 status */ +#define STM32_SYSCFG_ITLINE16_OFFSET 0x00c0 /* Interrupt line 16 status */ +#define STM32_SYSCFG_ITLINE17_OFFSET 0x00c4 /* Interrupt line 17 status */ +#define STM32_SYSCFG_ITLINE18_OFFSET 0x00c8 /* Interrupt line 18 status */ +#define STM32_SYSCFG_ITLINE19_OFFSET 0x00cc /* Interrupt line 19 status */ +#define STM32_SYSCFG_ITLINE20_OFFSET 0x00d0 /* Interrupt line 20 status */ +#define STM32_SYSCFG_ITLINE21_OFFSET 0x00d4 /* Interrupt line 21 status */ +#define STM32_SYSCFG_ITLINE22_OFFSET 0x00d8 /* Interrupt line 22 status */ +#define STM32_SYSCFG_ITLINE23_OFFSET 0x00dc /* Interrupt line 23 status */ +#define STM32_SYSCFG_ITLINE24_OFFSET 0x00e0 /* Interrupt line 24 status */ +#define STM32_SYSCFG_ITLINE25_OFFSET 0x00e4 /* Interrupt line 25 status */ +#define STM32_SYSCFG_ITLINE26_OFFSET 0x00e8 /* Interrupt line 26 status */ +#define STM32_SYSCFG_ITLINE27_OFFSET 0x00ec /* Interrupt line 27 status */ +#define STM32_SYSCFG_ITLINE28_OFFSET 0x00f0 /* Interrupt line 28 status */ +#define STM32_SYSCFG_ITLINE29_OFFSET 0x00f4 /* Interrupt line 29 status */ +#define STM32_SYSCFG_ITLINE30_OFFSET 0x00f8 /* Interrupt line 30 status */ +#define STM32_SYSCFG_ITLINE31_OFFSET 0x00fc /* Interrupt line 31 status */ + +/* Register Addresses *******************************************************/ + +#define STM32_SYSCFG_CFGR1 (STM32_SYSCFG_BASE + STM32_SYSCFG_CFGR1_OFFSET) +#define STM32_SYSCFG_CFGR2 (STM32_SYSCFG_BASE + STM32_SYSCFG_CFGR2_OFFSET) +#define STM32_SYSCFG_SCSR (STM32_SYSCFG_BASE + STM32_SYSCFG_SCSR_OFFSET) +#define STM32_SYSCFG_SKR (STM32_SYSCFG_BASE + STM32_SYSCFG_SKR_OFFSET) +#define STM32_SYSCFG_TSCCR (STM32_SYSCFG_BASE + STM32_SYSCFG_TSCCR_OFFSET) +#define STM32_SYSCFG_ITLINE(n) (STM32_SYSCFG_BASE +STM32_SYSCFG_ITLINE0_OFFSET + ((n) << 2)) +#define STM32_SYSCFG_ITLINE0 (STM32_SYSCFG_BASE +STM32_SYSCFG_ITLINE0_OFFSET) +#define STM32_SYSCFG_ITLINE1 (STM32_SYSCFG_BASE +STM32_SYSCFG_ITLINE1_OFFSET) +#define STM32_SYSCFG_ITLINE2 (STM32_SYSCFG_BASE +STM32_SYSCFG_ITLINE2_OFFSET) +#define STM32_SYSCFG_ITLINE3 (STM32_SYSCFG_BASE +STM32_SYSCFG_ITLINE3_OFFSET) +#define STM32_SYSCFG_ITLINE4 (STM32_SYSCFG_BASE +STM32_SYSCFG_ITLINE4_OFFSET) +#define STM32_SYSCFG_ITLINE5 (STM32_SYSCFG_BASE +STM32_SYSCFG_ITLINE5_OFFSET) +#define STM32_SYSCFG_ITLINE6 (STM32_SYSCFG_BASE +STM32_SYSCFG_ITLINE6_OFFSET) +#define STM32_SYSCFG_ITLINE7 (STM32_SYSCFG_BASE +STM32_SYSCFG_ITLINE7_OFFSET) +#define STM32_SYSCFG_ITLINE8 (STM32_SYSCFG_BASE +STM32_SYSCFG_ITLINE8_OFFSET) +#define STM32_SYSCFG_ITLINE9 (STM32_SYSCFG_BASE +STM32_SYSCFG_ITLINE9_OFFSET) +#define STM32_SYSCFG_ITLINE10 (STM32_SYSCFG_BASE +STM32_SYSCFG_ITLINE10_OFFSET) +#define STM32_SYSCFG_ITLINE11 (STM32_SYSCFG_BASE +STM32_SYSCFG_ITLINE11_OFFSET) +#define STM32_SYSCFG_ITLINE12 (STM32_SYSCFG_BASE +STM32_SYSCFG_ITLINE12_OFFSET) +#define STM32_SYSCFG_ITLINE13 (STM32_SYSCFG_BASE +STM32_SYSCFG_ITLINE13_OFFSET) +#define STM32_SYSCFG_ITLINE14 (STM32_SYSCFG_BASE +STM32_SYSCFG_ITLINE14_OFFSET) +#define STM32_SYSCFG_ITLINE15 (STM32_SYSCFG_BASE +STM32_SYSCFG_ITLINE15_OFFSET) +#define STM32_SYSCFG_ITLINE16 (STM32_SYSCFG_BASE +STM32_SYSCFG_ITLINE16_OFFSET) +#define STM32_SYSCFG_ITLINE17 (STM32_SYSCFG_BASE +STM32_SYSCFG_ITLINE17_OFFSET) +#define STM32_SYSCFG_ITLINE18 (STM32_SYSCFG_BASE +STM32_SYSCFG_ITLINE18_OFFSET) +#define STM32_SYSCFG_ITLINE19 (STM32_SYSCFG_BASE +STM32_SYSCFG_ITLINE19_OFFSET) +#define STM32_SYSCFG_ITLINE20 (STM32_SYSCFG_BASE +STM32_SYSCFG_ITLINE20_OFFSET) +#define STM32_SYSCFG_ITLINE21 (STM32_SYSCFG_BASE +STM32_SYSCFG_ITLINE21_OFFSET) +#define STM32_SYSCFG_ITLINE22 (STM32_SYSCFG_BASE +STM32_SYSCFG_ITLINE22_OFFSET) +#define STM32_SYSCFG_ITLINE23 (STM32_SYSCFG_BASE +STM32_SYSCFG_ITLINE23_OFFSET) +#define STM32_SYSCFG_ITLINE24 (STM32_SYSCFG_BASE +STM32_SYSCFG_ITLINE24_OFFSET) +#define STM32_SYSCFG_ITLINE25 (STM32_SYSCFG_BASE +STM32_SYSCFG_ITLINE25_OFFSET) +#define STM32_SYSCFG_ITLINE26 (STM32_SYSCFG_BASE +STM32_SYSCFG_ITLINE26_OFFSET) +#define STM32_SYSCFG_ITLINE27 (STM32_SYSCFG_BASE +STM32_SYSCFG_ITLINE27_OFFSET) +#define STM32_SYSCFG_ITLINE28 (STM32_SYSCFG_BASE +STM32_SYSCFG_ITLINE28_OFFSET) +#define STM32_SYSCFG_ITLINE29 (STM32_SYSCFG_BASE +STM32_SYSCFG_ITLINE29_OFFSET) +#define STM32_SYSCFG_ITLINE30 (STM32_SYSCFG_BASE +STM32_SYSCFG_ITLINE30_OFFSET) +#define STM32_SYSCFG_ITLINE31 (STM32_SYSCFG_BASE +STM32_SYSCFG_ITLINE31_OFFSET) + +/* Register Bitfield Definitions ********************************************/ + +/* SYSCFG configuration register 1 */ + +#define SYSCFG_CFGR1_MEMMODE_SHIFT (0) /* Bits 0-1: Memory mapping selection */ +#define SYSCFG_CFGR1_MEMMODE_MASK (3 << SYSCFG_CFGR1_MEMMODE_SHIFT) +# define SYSCFG_CFGR1_MEMMODE_FLASH (0 << SYSCFG_CFGR1_MEMMODE_SHIFT) /* 00: Main Flash at 0x00000000 */ +# define SYSCFG_CFGR1_MEMMODE_SYSTEM (1 << SYSCFG_CFGR1_MEMMODE_SHIFT) /* 01: System Flash at 0x00000000 */ +# define SYSCFG_CFGR1_MEMMODE_SRAM (3 << SYSCFG_CFGR1_MEMMODE_SHIFT) /* 11: Embedded SRAM at 0x00000000 */ + /* Bit 2: Reserved */ +#define SYSCFG_CFGR1_PA11_RMP (1 << 3) /* Bit 3: PA11 remapping */ +#define SYSCFG_CFGR1_PA12_RMP (1 << 4) /* Bit 4: PA12 remapping */ +#define SYSCFG_CFGR1_IRPOL (1 << 5) /* Bit 5: IR output polarity selection */ +#define SYSCFG_CFGR1_IRMOD_SHIFT (6) /* Bits 6-7: IR mode */ +#define SYSCFG_CFGR1_IRMOD_MASK (3 << SYSCFG_CFGR1_IRMOD_SHIFT) +# define SYSCFG_CFGR1_IRMOD_TIM16 (0 << SYSCFG_CFGR1_IRMOD_SHIFT) /* 00: TIM16 selected */ +# define SYSCFG_CFGR1_IRMOD_USART1 (1 << SYSCFG_CFGR1_IRMOD_SHIFT) /* 01: USART1 selected */ +# define SYSCFG_CFGR1_IRMOD_USART4 (2 << SYSCFG_CFGR1_IRMOD_SHIFT) /* 10: USART4 selected */ +#define SYSCFG_CFGR1_BOOSTEN (1 << 8) /* Bit 8: IO analog switch voltage booster enable */ + /* Bits 9-15: Reserved */ +#define SYSCFG_CFGR1_I2CPB6FMP (1 << 16) /* Bit 16: PB6 FM+ */ +#define SYSCFG_CFGR1_I2CPB7FMP (1 << 17) /* Bit 17: PB7 FM+ */ +#define SYSCFG_CFGR1_I2CPB8FMP (1 << 18) /* Bit 18: PB8 FM+ */ +#define SYSCFG_CFGR1_I2CPB9FMP (1 << 19) /* Bit 19: PB9 FM+ */ + /* Bits 20-21: Reserved */ +#define SYSCFG_CFGR1_I2CPA9FMP (1 << 22) /* Bit 22: PA9 FM+ */ +#define SYSCFG_CFGR1_I2CPA10FMP (1 << 23) /* Bit 23: PA10 FM+ */ +#define SYSCFG_CFGR1_I2C3FMP (1 << 24) /* Bit 24: I2C3 FM+ */ + /* Bits 25-31: Reserved */ + +/* SYSCFG configuration register 2 */ + +#define SYSCFG_CFGR2_CCL (1 << 0) /* Bit 0: Cortex-M0+ LOCKUP enable */ +#define SYSCFG_CFGR2_SPL (1 << 1) /* Bit 1: SRAM parity lock */ +#define SYSCFG_CFGR2_PVDL (1 << 2) /* Bit 2: PVD lock */ +#define SYSCFG_CFGR2_ECCL (1 << 3) /* Bit 3: ECC lock */ +#define SYSCFG_CFGR2_BKPL (1 << 4) /* Bit 4: Backup SRAM parity lock */ + /* Bits 5-6: Reserved */ +#define SYSCFG_CFGR2_BKPF (1 << 7) /* Bit 7: Backup SRAM parity error flag */ +#define SYSCFG_CFGR2_SPF (1 << 8) /* Bit 8: SRAM parity error flag */ + /* Bits 9-31: Reserved */ + +/* SYSCFG backup SRAM control and status register */ + +#define SYSCFG_SCSR_SRAM2ER (1 << 0) /* Bit 0: Backup SRAM erase */ +#define SYSCFG_SCSR_SRAM2BSY (1 << 1) /* Bit 1: Backup SRAM erase busy */ + +/* SYSCFG backup SRAM key register */ + +#define SYSCFG_SKR_KEY_SHIFT (0) /* Bits 0-7: Backup SRAM erase key */ +#define SYSCFG_SKR_KEY_MASK (0xff << SYSCFG_SKR_KEY_SHIFT) + +/* SYSCFG TSC comparator register */ + +#define SYSCFG_TSCCR_G2IO1 (1 << 0) /* Bit 0: G2_IO1 (PB4) */ +#define SYSCFG_TSCCR_G2IO3 (1 << 1) /* Bit 1: G2_IO3 (PB6) */ +#define SYSCFG_TSCCR_G4IO1 (1 << 2) /* Bit 2: G4_IO1 (PC6) */ +#define SYSCFG_TSCCR_G6IO1 (1 << 3) /* Bit 3: G6_IO1 (PD10) */ +#define SYSCFG_TSCCR_G7IO2 (1 << 4) /* Bit 4: G7_IO2 (PA9) */ +#define SYSCFG_TSCCR_TSCIOCTRL (1 << 5) /* Bit 5: Comparator mode control */ + +/* SYSCFG interrupt line 0 status register */ + +#define SYSCFG_ITLINE0_WWDG (1 << 0) /* Bit 0: WWDG pending */ + +/* SYSCFG interrupt line 1 status register */ + +#define SYSCFG_ITLINE1_PVDOUT (1 << 0) /* Bit 0: PVD pending */ +#define SYSCFG_ITLINE1_PVMOUT1 (1 << 1) /* Bit 1: PVM1 pending */ +#define SYSCFG_ITLINE1_PVMOUT3 (1 << 2) /* Bit 2: PVM3 pending */ +#define SYSCFG_ITLINE1_PVMOUT4 (1 << 3) /* Bit 3: PVM4 pending */ + +/* SYSCFG interrupt line 2 status register */ + +#define SYSCFG_ITLINE2_TAMPER (1 << 0) /* Bit 0: TAMP pending */ +#define SYSCFG_ITLINE2_RTC (1 << 1) /* Bit 1: RTC pending */ + +/* SYSCFG interrupt line 3 status register */ + +#define SYSCFG_ITLINE3_FLASH_ECC (1 << 0) /* Bit 0: Flash ECC pending */ +#define SYSCFG_ITLINE3_FLASH_ITF (1 << 1) /* Bit 1: Flash interface pending */ + +/* SYSCFG interrupt line 4 status register */ + +#define SYSCFG_ITLINE4_RCC (1 << 0) /* Bit 0: RCC pending */ +#define SYSCFG_ITLINE4_CRS (1 << 1) /* Bit 1: CRS pending */ + +/* SYSCFG interrupt line 5 status register */ + +#define SYSCFG_ITLINE5_EXTI0 (1 << 0) /* Bit 0: EXTI 0 pending */ +#define SYSCFG_ITLINE5_EXTI1 (1 << 1) /* Bit 1: EXTI 1 pending */ + +/* SYSCFG interrupt line 6 status register */ + +#define SYSCFG_ITLINE6_EXTI2 (1 << 0) /* Bit 0: EXTI 2 pending */ +#define SYSCFG_ITLINE6_EXTI3 (1 << 1) /* Bit 1: EXTI 3 pending */ + +/* SYSCFG interrupt line 7 status register */ + +#define SYSCFG_ITLINE7_EXTI4 (1 << 0) /* Bit 0: EXTI 4 pending */ +#define SYSCFG_ITLINE7_EXTI5 (1 << 1) /* Bit 1: EXTI 5 pending */ +#define SYSCFG_ITLINE7_EXTI6 (1 << 2) /* Bit 2: EXTI 6 pending */ +#define SYSCFG_ITLINE7_EXTI7 (1 << 3) /* Bit 3: EXTI 7 pending */ +#define SYSCFG_ITLINE7_EXTI8 (1 << 4) /* Bit 4: EXTI 8 pending */ +#define SYSCFG_ITLINE7_EXTI9 (1 << 5) /* Bit 5: EXTI 9 pending */ +#define SYSCFG_ITLINE7_EXTI10 (1 << 6) /* Bit 6: EXTI 10 pending */ +#define SYSCFG_ITLINE7_EXTI11 (1 << 7) /* Bit 7: EXTI 11 pending */ +#define SYSCFG_ITLINE7_EXTI12 (1 << 8) /* Bit 8: EXTI 12 pending */ +#define SYSCFG_ITLINE7_EXTI13 (1 << 9) /* Bit 9: EXTI 13 pending */ +#define SYSCFG_ITLINE7_EXTI14 (1 << 10) /* Bit 10: EXTI 14 pending */ +#define SYSCFG_ITLINE7_EXTI15 (1 << 11) /* Bit 11: EXTI 15 pending */ + +/* SYSCFG interrupt line 8 status register */ + +#define SYSCFG_ITLINE8_USBFS (1 << 0) /* Bit 0: USB FS pending */ + +/* SYSCFG interrupt line 9 status register */ + +#define SYSCFG_ITLINE9_DMA1_CH1 (1 << 0) /* Bit 0: DMA1 CH1 pending */ + +/* SYSCFG interrupt line 10 status register */ + +#define SYSCFG_ITLINE10_DMA1_CH2 (1 << 0) /* Bit 0: DMA1 CH2 pending */ +#define SYSCFG_ITLINE10_DMA1_CH3 (1 << 1) /* Bit 1: DMA1 CH3 pending */ + +/* SYSCFG interrupt line 11 status register */ + +#define SYSCFG_ITLINE11_DMAMUX (1 << 0) /* Bit 0: DMAMUX pending */ +#define SYSCFG_ITLINE11_DMA1_CH4 (1 << 1) /* Bit 1: DMA1 CH4 pending */ +#define SYSCFG_ITLINE11_DMA1_CH5 (1 << 2) /* Bit 2: DMA1 CH5 pending */ +#define SYSCFG_ITLINE11_DMA1_CH6 (1 << 3) /* Bit 3: DMA1 CH6 pending */ +#define SYSCFG_ITLINE11_DMA1_CH7 (1 << 4) /* Bit 4: DMA1 CH7 pending */ +#define SYSCFG_ITLINE11_DMA2_CH1 (1 << 5) /* Bit 5: DMA2 CH1 pending */ +#define SYSCFG_ITLINE11_DMA2_CH2 (1 << 6) /* Bit 6: DMA2 CH2 pending */ +#define SYSCFG_ITLINE11_DMA2_CH3 (1 << 7) /* Bit 7: DMA2 CH3 pending */ +#define SYSCFG_ITLINE11_DMA2_CH4 (1 << 8) /* Bit 8: DMA2 CH4 pending */ +#define SYSCFG_ITLINE11_DMA2_CH5 (1 << 9) /* Bit 9: DMA2 CH5 pending */ + +/* SYSCFG interrupt line 12 status register */ + +#define SYSCFG_ITLINE12_ADC (1 << 0) /* Bit 0: ADC pending */ +#define SYSCFG_ITLINE12_COMP1 (1 << 1) /* Bit 1: COMP1 pending */ +#define SYSCFG_ITLINE12_COMP2 (1 << 2) /* Bit 2: COMP2 pending */ + +/* SYSCFG interrupt line 13 status register */ + +#define SYSCFG_ITLINE13_TIM1_CCU (1 << 0) /* Bit 0: TIM1 commutation pending */ +#define SYSCFG_ITLINE13_TIM1_TRG (1 << 1) /* Bit 1: TIM1 trigger pending */ +#define SYSCFG_ITLINE13_TIM1_UPD (1 << 2) /* Bit 2: TIM1 update pending */ +#define SYSCFG_ITLINE13_TIM1_BRK (1 << 3) /* Bit 3: TIM1 break pending */ + +/* SYSCFG interrupt line 14 status register */ + +#define SYSCFG_ITLINE14_TIM1_CC1 (1 << 0) /* Bit 0: TIM1 CC1 pending */ +#define SYSCFG_ITLINE14_TIM1_CC2 (1 << 1) /* Bit 1: TIM1 CC2 pending */ +#define SYSCFG_ITLINE14_TIM1_CC3 (1 << 2) /* Bit 2: TIM1 CC3 pending */ +#define SYSCFG_ITLINE14_TIM1_CC4 (1 << 3) /* Bit 3: TIM1 CC4 pending */ + +/* SYSCFG interrupt line 15 status register */ + +#define SYSCFG_ITLINE15_TIM2 (1 << 0) /* Bit 0: TIM2 pending */ + +/* SYSCFG interrupt line 16 status register */ + +#define SYSCFG_ITLINE16_TIM3 (1 << 0) /* Bit 0: TIM3 pending */ + +/* SYSCFG interrupt line 17 status register */ + +#define SYSCFG_ITLINE17_TIM6 (1 << 0) /* Bit 0: TIM6 pending */ +#define SYSCFG_ITLINE17_DAC (1 << 1) /* Bit 1: DAC underrun pending */ +#define SYSCFG_ITLINE17_LPTIM1 (1 << 2) /* Bit 2: LPTIM1 pending */ + +/* SYSCFG interrupt line 18 status register */ + +#define SYSCFG_ITLINE18_TIM7 (1 << 0) /* Bit 0: TIM7 pending */ +#define SYSCFG_ITLINE18_LPTIM2 (1 << 1) /* Bit 1: LPTIM2 pending */ + +/* SYSCFG interrupt line 19 status register */ + +#define SYSCFG_ITLINE19_TIM15 (1 << 0) /* Bit 0: TIM15 pending */ +#define SYSCFG_ITLINE19_LPTIM3 (1 << 1) /* Bit 1: LPTIM3 pending */ + +/* SYSCFG interrupt line 20 status register */ + +#define SYSCFG_ITLINE20_TIM16 (1 << 0) /* Bit 0: TIM16 pending */ + +/* SYSCFG interrupt line 21 status register */ + +#define SYSCFG_ITLINE21_TSC_MCE (1 << 0) /* Bit 0: TSC MCE pending */ +#define SYSCFG_ITLINE21_TSC_EOA (1 << 1) /* Bit 1: TSC EOA pending */ + +/* SYSCFG interrupt line 22 status register */ + +#define SYSCFG_ITLINE22_LCD (1 << 0) /* Bit 0: LCD pending */ + +/* SYSCFG interrupt line 23 status register */ + +#define SYSCFG_ITLINE23_I2C1 (1 << 0) /* Bit 0: I2C1 pending */ + +/* SYSCFG interrupt line 24 status register */ + +#define SYSCFG_ITLINE24_I2C2 (1 << 0) /* Bit 0: I2C2 pending */ +#define SYSCFG_ITLINE24_I2C4 (1 << 1) /* Bit 1: I2C4 pending */ +#define SYSCFG_ITLINE24_I2C3 (1 << 2) /* Bit 2: I2C3 pending */ + +/* SYSCFG interrupt line 25 status register */ + +#define SYSCFG_ITLINE25_SPI1 (1 << 0) /* Bit 0: SPI1 pending */ + +/* SYSCFG interrupt line 26 status register */ + +#define SYSCFG_ITLINE26_SPI2 (1 << 0) /* Bit 0: SPI2 pending */ +#define SYSCFG_ITLINE26_SPI3 (1 << 1) /* Bit 1: SPI3 pending */ + +/* SYSCFG interrupt line 27 status register */ + +#define SYSCFG_ITLINE27_USART1 (1 << 0) /* Bit 0: USART1 pending */ + +/* SYSCFG interrupt line 28 status register */ + +#define SYSCFG_ITLINE28_USART2 (1 << 0) /* Bit 0: USART2 pending */ +#define SYSCFG_ITLINE28_LPUART2 (1 << 1) /* Bit 1: LPUART2 pending */ + +/* SYSCFG interrupt line 29 status register */ + +#define SYSCFG_ITLINE29_USART3 (1 << 0) /* Bit 0: USART3 pending */ +#define SYSCFG_ITLINE29_LPUART1 (1 << 1) /* Bit 1: LPUART1 pending */ + +/* SYSCFG interrupt line 30 status register */ + +#define SYSCFG_ITLINE30_USART4 (1 << 0) /* Bit 0: USART4 pending */ +#define SYSCFG_ITLINE30_LPUART3 (1 << 1) /* Bit 1: LPUART3 pending */ + +/* SYSCFG interrupt line 31 status register */ + +#define SYSCFG_ITLINE31_RNG (1 << 0) /* Bit 0: RNG pending */ +#define SYSCFG_ITLINE31_AES (1 << 1) /* Bit 1: AES pending */ + +#endif /* __ARCH_ARM_SRC_STM32U0_HARDWARE_STM32U0_SYSCFG_H */ diff --git a/arch/arm/src/stm32u0/stm32.h b/arch/arm/src/stm32u0/stm32.h new file mode 100644 index 00000000000..122bc4e0e7d --- /dev/null +++ b/arch/arm/src/stm32u0/stm32.h @@ -0,0 +1,55 @@ +/**************************************************************************** + * arch/arm/src/stm32u0/stm32.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32U0_STM32_H +#define __ARCH_ARM_SRC_STM32U0_STM32_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include + +#include "arm_internal.h" + +/* Peripherals **************************************************************/ + +#include "chip.h" +#include "stm32_dma.h" +#include "stm32_gpio.h" +#include "stm32_i2c.h" +#include "stm32_pwr.h" +#include "stm32_rcc.h" +#include "stm32_spi.h" +#include "stm32_tim.h" +#include "stm32_uart.h" +#include "stm32_lowputc.h" +#include "stm32_adc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#endif /* __ARCH_ARM_SRC_STM32U0_STM32_H */ diff --git a/arch/arm/src/stm32u0/stm32_rcc.c b/arch/arm/src/stm32u0/stm32_rcc.c new file mode 100644 index 00000000000..212b21ee11f --- /dev/null +++ b/arch/arm/src/stm32u0/stm32_rcc.c @@ -0,0 +1,220 @@ +/**************************************************************************** + * arch/arm/src/stm32u0/stm32_rcc.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include + +#include "arm_internal.h" +#include "hardware/stm32_flash.h" +#include "stm32_rcc.h" +#include "stm32_hsi48_m0_v1.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifdef CONFIG_STM32_RNG +# ifndef STM32_USE_CLK48 +# error RNG requires CLK48 enabled +# endif +#endif + +#ifdef CONFIG_STM32_USB +# ifndef STM32_USE_CLK48 +# error USB requires CLK48 enabled +# endif +#endif + +static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, + "Configure BOARD_LOOPSPERMSEC to non-default value."); + +/* Allow up to 100 milliseconds for the high speed clock to become ready. + * that is a very long delay, but if the clock does not become ready we are + * hosed anyway. + */ + +#define HSERDY_TIMEOUT (100 * CONFIG_BOARD_LOOPSPERMSEC) + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/* Include chip-specific clocking initialization logic */ + +#include "stm32u0_rcc.c" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: rcc_resetbkp + * + * Description: + * The RTC needs to reset the Backup Domain to change RTCSEL and resetting + * the Backup Domain renders to disabling the LSE as consequence. + * In order to avoid resetting the Backup Domain when we already configured + * LSE we will reset the Backup Domain early (here). + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +#if defined(CONFIG_STM32_RTC) && defined(CONFIG_STM32_PWR) +static inline void rcc_resetbkp(void) +{ + uint32_t regval; + + /* Check if the RTC is already configured */ + + stm32_pwr_initbkp(false); + + regval = getreg32(RTC_MAGIC_REG); + if (regval != RTC_MAGIC && regval != RTC_MAGIC_TIME_SET) + { + stm32_pwr_enablebkp(true); + + /* We might be changing RTCSEL - to ensure such changes work, we must + * reset the backup domain (having backed up the RTC_MAGIC token) + */ + + modifyreg32(STM32_RCC_BDCR, 0, RCC_BDCR_BDRST); + modifyreg32(STM32_RCC_BDCR, RCC_BDCR_BDRST, 0); + + stm32_pwr_enablebkp(false); + } +} +#else +# define rcc_resetbkp() +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_clockconfig + * + * Description: + * Called to establish the clock settings based on the values in board.h. + * This function (by default) will reset most everything, enable the PLL, + * and enable peripheral clocking for all peripherals enabled in the NuttX + * configuration file. + * + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then + * clocking will be enabled by an externally provided, board-specific + * function called stm32_board_clockconfig(). + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void stm32_clockconfig(void) +{ + /* Make sure that we are starting in the reset state */ + + rcc_reset(); + + /* Reset backup domain if appropriate */ + + rcc_resetbkp(); + +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) + /* Invoke Board Custom Clock Configuration */ + + stm32_board_clockconfig(); + +#else + /* Invoke standard, fixed clock configuration based on definitions + * in board.h + */ + + stm32_stdclockconfig(); + +#endif + + /* Enable peripheral clocking */ + + rcc_enableperipherals(); +} + +/**************************************************************************** + * Name: stm32_clockenable + * + * Description: + * Re-enable the clock and restore the clock settings based on settings in + * board.h. This function is only available to support low-power modes of + * operation: When re-awakening from deep-sleep modes, it is necessary to + * re-enable/re-start the PLL + * + * This functional performs a subset of the operations performed by + * stm32_clockconfig(): It does not reset any devices, and it does not + * reset the currently enabled peripheral clocks. + * + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then + * clocking will be enabled by an externally provided, board-specific + * function called stm32_board_clockconfig(). + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_PM +void stm32_clockenable(void) +{ +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) + /* Invoke Board Custom Clock Configuration */ + + stm32_board_clockconfig(); + +#else + /* Invoke standard, fixed clock configuration based on definitions + * in board.h + */ + + stm32_stdclockconfig(); + +#endif +} +#endif diff --git a/arch/arm/src/stm32u0/stm32u0_rcc.c b/arch/arm/src/stm32u0/stm32u0_rcc.c new file mode 100644 index 00000000000..303209302a8 --- /dev/null +++ b/arch/arm/src/stm32u0/stm32u0_rcc.c @@ -0,0 +1,710 @@ +/**************************************************************************** + * arch/arm/src/stm32u0/stm32u0_rcc.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "stm32_pwr.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, + "Configure BOARD_LOOPSPERMSEC to non-default value."); + +/* Allow up to 100 milliseconds for the high speed clock to become + * ready. that is a very long delay, but if the clock does not become + * ready we are hosed anyway. Normally this is very fast, but I have + * seen at least one board that required this long, long timeout for + * the HSE to be ready. + */ + +#define HSERDY_TIMEOUT (100 * CONFIG_BOARD_LOOPSPERMSEC) + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: rcc_reset + * + * Description: + * Put all RCC registers in reset state + * + ****************************************************************************/ + +static inline void rcc_reset(void) +{ + uint32_t regval; + + /* Make sure that MSI is on and ready. MSI is the default system clock + * source after reset. + */ + + regval = getreg32(STM32_RCC_CR); + regval |= RCC_CR_MSION; + putreg32(regval, STM32_RCC_CR); + + while ((getreg32(STM32_RCC_CR) & RCC_CR_MSIRDY) == 0); + + /* Reset CFGR register (MSI as the system clock) */ + + putreg32(0, STM32_RCC_CFGR); + + /* Wait until MSI is used as the system clock */ + + while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != + RCC_CFGR_SWS_MSI); + + /* Turn off HSI, HSE and PLL, keep MSI on */ + + putreg32(RCC_CR_MSION, STM32_RCC_CR); + + /* Reset PLLCFGR register */ + + putreg32(0, STM32_RCC_PLLCFG); + + /* DBG clock enable */ + + putreg32(RCC_DBGCFGR_DBGEN, STM32_RCC_DBGCFGR); +} + +/**************************************************************************** + * Name: rcc_enableio + * + * Description: + * Enable selected GPIO + * + ****************************************************************************/ + +static inline void rcc_enableio(void) +{ + uint32_t regval = 0; + + regval |= (RCC_IOPENR_IOPAEN | RCC_IOPENR_IOPBEN | RCC_IOPENR_IOPCEN | + RCC_IOPENR_IOPDEN | RCC_IOPENR_IOPEEN | RCC_IOPENR_IOPFEN); + + putreg32(regval, STM32_RCC_IOPENR); /* Enable GPIO */ +} + +/**************************************************************************** + * Name: rcc_enableahb + * + * Description: + * Enable selected AHB peripherals + * + ****************************************************************************/ + +static inline void rcc_enableahb(void) +{ + uint32_t regval = 0; + + /* Set the appropriate bits in the AHBENR register to enabled the + * selected AHBENR peripherals. + */ + + regval = getreg32(STM32_RCC_AHBENR); + +#ifdef CONFIG_STM32_DMA1 + /* DMA 1 clock enable */ + + regval |= RCC_AHBENR_DMA1EN; +#endif + +#ifdef CONFIG_STM32_DMA2 + /* DMA 2 clock enable */ + + regval |= RCC_AHBENR_DMA2EN; +#endif + +#ifdef CONFIG_STM32_CRC + /* CRC clock enable */ + + regval |= RCC_AHBENR_CRCEN; +#endif + +#ifdef CONFIG_STM32_TSC + /* Touch sensing controller clock enable */ + + regval |= RCC_AHBENR_TSCEN; +#endif + +#ifdef CONFIG_STM32_RNG + /* Random number generator clock enable */ + + regval |= RCC_AHBENR_RNGEN; +#endif + +#ifdef CONFIG_STM32_AES + /* AES modules clock enable */ + + regval |= RCC_AHBENR_AESEN; +#endif + + putreg32(regval, STM32_RCC_AHBENR); /* Enable peripherals */ +} + +/**************************************************************************** + * Name: rcc_enableapb1 + * + * Description: + * Enable selected APB1 peripherals + * + ****************************************************************************/ + +static inline void rcc_enableapb1(void) +{ + uint32_t regval; + + /* Set the appropriate bits in the APB1ENR register to enabled the + * selected APB1 peripherals. + */ + + regval = getreg32(STM32_RCC_APB1ENR); + +#ifdef CONFIG_STM32_TIM2 + /* Timer 2 clock enable */ + + regval |= RCC_APB1ENR_TIM2EN; +#endif + +#ifdef CONFIG_STM32_TIM3 + /* Timer 3 clock enable */ + + regval |= RCC_APB1ENR_TIM3EN; +#endif + +#ifdef CONFIG_STM32_TIM6 + /* Timer 6 clock enable */ + + regval |= RCC_APB1ENR_TIM6EN; +#endif + +#ifdef CONFIG_STM32_TIM7 + /* Timer 7 clock enable */ + + regval |= RCC_APB1ENR_TIM7EN; +#endif + +#ifdef CONFIG_STM32_LCD + /* LCD clock enable */ + + regval |= RCC_APB1ENR_LCDEN; +#endif + +#ifdef CONFIG_STM32_RTC + /* RTC APB clock enable */ + + regval |= RCC_APB1ENR_RTCAPBEN; +#endif + +#ifdef CONFIG_STM32_WWDG + /* Window watchdog clock enable */ + + regval |= RCC_APB1ENR_WWDGEN; +#endif + +#ifdef CONFIG_STM32_SPI2 + /* SPI 2 clock enable */ + + regval |= RCC_APB1ENR_SPI2EN; +#endif + +#ifdef CONFIG_STM32_SPI3 + /* SPI 3 clock enable */ + + regval |= RCC_APB1ENR_SPI3EN; +#endif + +#ifdef CONFIG_STM32_USB + /* USB clock enable */ + + regval |= RCC_APB1ENR_USBEN; +#endif + +#ifdef CONFIG_STM32_CRS + /* CRS clock enable */ + + regval |= RCC_APB1ENR_CRSEN; +#endif + +#ifdef CONFIG_STM32_USART2 + /* USART 2 clock enable */ + + regval |= RCC_APB1ENR_USART2EN; +#endif + +#ifdef CONFIG_STM32_USART3 + /* USART 3 clock enable */ + + regval |= RCC_APB1ENR_USART3EN; +#endif + +#ifdef CONFIG_STM32_USART4 + /* USART 4 clock enable */ + + regval |= RCC_APB1ENR_USART4EN; +#endif + +#ifdef CONFIG_STM32_LPUART1 + /* LPUART 1 clock enable */ + + regval |= RCC_APB1ENR_LPUART1EN; +#endif + +#ifdef CONFIG_STM32_I2C1 + /* I2C 1 clock enable */ + + regval |= RCC_APB1ENR_I2C1EN; +#endif + +#ifdef CONFIG_STM32_I2C2 + /* I2C 2 clock enable */ + + regval |= RCC_APB1ENR_I2C2EN; +#endif + +#ifdef CONFIG_STM32_I2C3 + /* I2C 3 clock enable */ + + regval |= RCC_APB1ENR_I2C3EN; +#endif + +#ifdef CONFIG_STM32_I2C4 + /* I2C 4 clock enable */ + + regval |= RCC_APB1ENR_I2C4EN; +#endif + +#ifdef CONFIG_STM32_PWR + /* Power interface clock enable */ + + regval |= RCC_APB1ENR_PWREN; +#endif + +#ifdef CONFIG_STM32_DAC1 + /* DAC 1 interface clock enable */ + + regval |= RCC_APB1ENR_DAC1EN; +#endif + +#ifdef CONFIG_STM32_LPTIM1 + /* LPTIM1 clock enable */ + + regval |= RCC_APB1ENR_LPTIM1EN; +#endif + +#ifdef CONFIG_STM32_LPTIM2 + /* LPTIM2 clock enable */ + + regval |= RCC_APB1ENR_LPTIM2EN; +#endif + +#ifdef CONFIG_STM32_LPTIM3 + /* LPTIM3 clock enable */ + + regval |= RCC_APB1ENR_LPTIM3EN; +#endif + + putreg32(regval, STM32_RCC_APB1ENR); +} + +/**************************************************************************** + * Name: rcc_enableapb2 + * + * Description: + * Enable selected APB2 peripherals + * + ****************************************************************************/ + +static inline void rcc_enableapb2(void) +{ + uint32_t regval; + + /* Set the appropriate bits in the APB2ENR register to enabled the + * selected APB2 peripherals. + */ + + regval = getreg32(STM32_RCC_APB2ENR); + +#ifdef CONFIG_STM32_SYSCFG + /* SYSCFG clock */ + + regval |= RCC_APB2ENR_SYSCFGEN; +#endif + +#ifdef CONFIG_STM32_TIM1 + /* TIM1 Timer clock enable */ + + regval |= RCC_APB2ENR_TIM1EN; +#endif + +#ifdef CONFIG_STM32_SPI1 + /* SPI 1 clock enable */ + + regval |= RCC_APB2ENR_SPI1EN; +#endif + +#ifdef CONFIG_STM32_USART1 + /* USART1 clock enable */ + + regval |= RCC_APB2ENR_USART1EN; +#endif + +#ifdef CONFIG_STM32_TIM15 + /* TIM15 Timer clock enable */ + + regval |= RCC_APB2ENR_TIM15EN; +#endif + +#ifdef CONFIG_STM32_TIM16 + /* TIM16 Timer clock enable */ + + regval |= RCC_APB2ENR_TIM16EN; +#endif + +#ifdef CONFIG_STM32_ADC1 + /* ADC 1 clock enable */ + + regval |= RCC_APB2ENR_ADC1EN; +#endif + + putreg32(regval, STM32_RCC_APB2ENR); +} + +/**************************************************************************** + * Name: stm32_rcc_enablehse + * + * Description: + * Enable the External High-Speed (HSE) Oscillator. + * + ****************************************************************************/ + +#if (STM32_PLLCFG_PLLSRC == RCC_PLLCFG_PLLSRC_HSE) || (STM32_SYSCLK_SW == RCC_CFGR_SW_HSE) +static inline bool stm32_rcc_enablehse(void) +{ + uint32_t regval; + volatile int32_t timeout; + + /* Enable External High-Speed Clock (HSE) */ + + regval = getreg32(STM32_RCC_CR); +#ifdef STM32_HSEBYP_ENABLE /* May be defined in board.h header file */ + regval |= RCC_CR_HSEBYP; /* Enable HSE clock bypass */ +#else + regval &= ~RCC_CR_HSEBYP; /* Disable HSE clock bypass */ +#endif + regval |= RCC_CR_HSEON; /* Enable HSE */ + putreg32(regval, STM32_RCC_CR); + + /* Wait until the HSE is ready (or until a timeout elapsed) */ + + for (timeout = HSERDY_TIMEOUT; timeout > 0; timeout--) + { + /* Check if the HSERDY flag is set in the CR */ + + if ((getreg32(STM32_RCC_CR) & RCC_CR_HSERDY) != 0) + { + /* If so, then return TRUE */ + + return true; + } + } + + /* In the case of a timeout starting the HSE, we really don't have a + * strategy. This is almost always a hardware failure or misconfiguration. + */ + + return false; +} +#endif + +/**************************************************************************** + * Name: stm32_stdclockconfig + * + * Description: + * Called to change to new clock based on settings in board.h. + * + * NOTE: This logic would need to be extended if you need to select low- + * power clocking modes or any clocking other than PLL driven by the HSE. + * + ****************************************************************************/ + +#ifndef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG +static void stm32_stdclockconfig(void) +{ + uint32_t regval; +#ifdef CONFIG_STM32_PWR + uint32_t pwr_vos; +#endif + uint32_t flash_ws; + + /* Enable PWR clock from APB1 to give access to PWR_CR register */ + + regval = getreg32(STM32_RCC_APB1ENR); + regval |= RCC_APB1ENR_PWREN; + putreg32(regval, STM32_RCC_APB1ENR); + + /* Two voltage ranges are available: + * + * Range 1: High-performance range (default) + * Typical output voltage 1.2 V + * SYSCLK up to 56 MHz + * + * Range 2: Low-power range + * Typical output voltage 1.0V + * SYSCLK up to 16 MHz + * + * Flash wait states (latency) according to range and HCLK: + * + * Range 1: + * - Flash 0WS if HCLK <= 24 + * - Flash 1WS if HCLK <= 48 + * - Flash 2WS if HCLK <= 56 + * + * Range 2: + * - Flash 0WS if HCLK <= 8 + * - Flash 1WS if HCLK <= 16 + * + * Where HCLK = (SYSCLK / HPRE div) + */ + + if (STM32_SYSCLK_FREQUENCY > 16000000) + { +#ifdef CONFIG_STM32_PWR + pwr_vos = PWR_CR1_VOS_RANGE1; +#endif + + if (STM32_HCLK_FREQUENCY <= 24000000) + { + flash_ws = FLASH_ACR_LATENCY_0; + } + else if (STM32_HCLK_FREQUENCY <= 48000000) + { + flash_ws = FLASH_ACR_LATENCY_1; + } + else + { + flash_ws = FLASH_ACR_LATENCY_2; + } + } + else + { +#ifdef CONFIG_STM32_PWR + pwr_vos = PWR_CR1_VOS_RANGE2; +#endif + + if (STM32_HCLK_FREQUENCY <= 8000000) + { + flash_ws = FLASH_ACR_LATENCY_0; + } + else + { + flash_ws = FLASH_ACR_LATENCY_1; + } + } + +#ifdef CONFIG_STM32_PWR + stm32_pwr_setvos(pwr_vos); +#endif + + /* Enable the source clock for the PLL (via HSE, HSI or MSI), HSE, HSI + * or MSI. + */ + +#if (STM32_SYSCLK_SW == RCC_CFGR_SW_HSE) || \ + ((STM32_SYSCLK_SW == RCC_CFGR_SW_PLL) && (STM32_PLLCFG_PLLSRC == RCC_PLLCFG_PLLSRC_HSE)) + + /* The PLL is using the HSE, or the HSE is the system clock. In either + * case, we need to enable HSE clocking. + */ + + if (!stm32_rcc_enablehse()) + { + /* In the case of a timeout starting the HSE, we really don't have a + * strategy. This is almost always a hardware failure or + * misconfiguration (for example, if no crystal is fitted on the board. + */ + + return; + } + +#elif (STM32_SYSCLK_SW == RCC_CFGR_SW_HSI) || \ + ((STM32_SYSCLK_SW == RCC_CFGR_SW_PLL) && STM32_PLLCFG_PLLSRC == RCC_PLLCFG_PLLSRC_HSI) + + /* The PLL is using the HSI, or the HSI is the system clock. In either + * case, we need to enable HSI clocking. + */ + + regval = getreg32(STM32_RCC_CR); /* Enable the HSI */ + regval |= RCC_CR_HSION; + putreg32(regval, STM32_RCC_CR); + + /* Wait until the HSI clock is ready. Since this is an internal clock, no + * timeout is expected + */ + + while ((getreg32(STM32_RCC_CR) & RCC_CR_HSIRDY) == 0); + +#elif (STM32_SYSCLK_SW == RCC_CFGR_SW_MSI) || \ + ((STM32_SYSCLK_SW == RCC_CFGR_SW_PLL) && STM32_PLLCFG_PLLSRC == RCC_PLLCFG_PLLSRC_MSI) + + /* The PLL is using the MSI, or the MSI is the system clock. In either + * case, we need to enable MSI clocking with the board provided range. + * The MSI range can be modified only when MSI is off or when MSI is + * ready - both conditions are satisfied here since rcc_reset() left us + * running on a ready MSI. + */ + + regval = getreg32(STM32_RCC_CR); +#ifdef STM32_MSI_RANGE + regval &= ~RCC_CR_MSIRANGE_MASK; + regval |= STM32_MSI_RANGE | RCC_CR_MSIRGSEL; +#endif + regval |= RCC_CR_MSION; + putreg32(regval, STM32_RCC_CR); + + /* Wait until the MSI clock is ready. Since this is an internal clock, + * no timeout is expected + */ + + while ((getreg32(STM32_RCC_CR) & RCC_CR_MSIRDY) == 0); + +#endif + + /* Configure FLASH wait states and enable prefetch */ + + regval = getreg32(STM32_FLASH_ACR); + regval &= ~FLASH_ACR_LATENCY_MASK; + regval |= (flash_ws & FLASH_ACR_LATENCY_MASK) | FLASH_ACR_PRFTEN; + putreg32(regval, STM32_FLASH_ACR); + + /* Set the HCLK source/divider */ + + regval = getreg32(STM32_RCC_CFGR); + regval &= ~RCC_CFGR_HPRE_MASK; + regval |= STM32_RCC_CFGR_HPRE; + putreg32(regval, STM32_RCC_CFGR); + + /* Set the PCLK1 divider */ + + regval = getreg32(STM32_RCC_CFGR); + regval &= ~RCC_CFGR_PPRE1_MASK; + regval |= STM32_RCC_CFGR_PPRE1; + putreg32(regval, STM32_RCC_CFGR); + + /* If we are using the PLL, configure and start it */ + +#if STM32_SYSCLK_SW == RCC_CFGR_SW_PLL + + /* Configure PLLs */ + + regval = STM32_PLLCFG_PLLSRC | STM32_PLLCFG_PLLCFG; + + /* Configure PLL clock input */ + + regval |= STM32_PLLCFG_PLLM | STM32_PLLCFG_PLLN; + + /* Configure PLL clock outputs division */ + + regval |= STM32_PLLCFG_PLLP | STM32_PLLCFG_PLLQ | STM32_PLLCFG_PLLR; + + /* Write PLLCFG register */ + + putreg32(regval, STM32_RCC_PLLCFG); + + /* Enable PLL */ + + regval = getreg32(STM32_RCC_CR); + regval |= RCC_CR_PLLON; + putreg32(regval, STM32_RCC_CR); + + /* Wait until the PLL is ready */ + + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLRDY) == 0); +#endif + + /* Select the system clock source (probably the PLL) */ + + regval = getreg32(STM32_RCC_CFGR); + regval &= ~RCC_CFGR_SW_MASK; + regval |= STM32_SYSCLK_SW; + putreg32(regval, STM32_RCC_CFGR); + + /* Wait until the selected source is used as the system clock source */ + + while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != STM32_SYSCLK_SWS); + +#if defined(CONFIG_STM32_IWDG) || \ + defined(CONFIG_STM32_RTC_LSICLOCK) || defined(CONFIG_LCD_LSICLOCK) + /* Low speed internal clock source LSI + * + * TODO: There is another case where the LSI needs to + * be enabled: if the MCO pin selects LSI as source. + */ + + stm32_rcc_enablelsi(); + +#endif + +#if defined(CONFIG_STM32_RTC_LSECLOCK) || defined(CONFIG_LCD_LSECLOCK) + /* Low speed external clock source LSE + * + * TODO: There is another case where the LSE needs to + * be enabled: if the MCO pin selects LSE as source. + */ + + stm32_rcc_enablelse(); +#endif + +#if defined(STM32_RCC_CCIPR_ADCSEL) + regval = getreg32(STM32_RCC_CCIPR); + regval &= ~RCC_CCIPR_ADCSEL_MASK; + regval |= STM32_RCC_CCIPR_ADCSEL; + putreg32(regval, STM32_RCC_CCIPR); +#endif +} +#endif + +/**************************************************************************** + * Name: rcc_enableperiphals + ****************************************************************************/ + +static inline void rcc_enableperipherals(void) +{ + rcc_enableio(); + rcc_enableahb(); + rcc_enableapb2(); + rcc_enableapb1(); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/