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Run all .c and .h files modified by this PR through nxstyle.

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This commit is contained in:
Gregory Nutt 2020-05-03 08:47:28 -06:00 • committed by Abdelatif Guettouche
parent 01d32a2b22
commit da4c597b5f
7 changed files with 30 additions and 24 deletions
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14
arch/arm/src/stm32/stm32_rtcounter.c
View file

@ -80,7 +80,9 @@
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Configuration ********************************************************************/
/* In hi-res mode, the RTC operates at 16384Hz. Overflow interrupts are handled
* when the 32-bit RTC counter overflows every 3 days and 43 minutes. A BKP register
* is incremented on each overflow interrupt creating, effectively, a 48-bit RTC
@ -125,7 +127,8 @@
# endif
#endif
/* RTC/BKP Definitions *************************************************************/
/* RTC/BKP Definitions **************************************************************/
/* STM32_RTC_PRESCALAR_VALUE
* RTC pre-scalar value. The RTC is driven by a 32,768Hz input clock. This input
* value is divided by this value (plus one) to generate the RTC frequency.
@ -286,7 +289,8 @@ static void stm32_rtc_breakout(FAR const struct timespec *tp,
/* Break up the time in seconds + milleconds into the correct values for our use */
frac = ((uint64_t)tp->tv_nsec * CONFIG_RTC_FREQUENCY) / 1000000000;
cnt = (tp->tv_sec << RTC_CLOCKS_SHIFT) | ((uint32_t)frac & (CONFIG_RTC_FREQUENCY-1));
cnt = (tp->tv_sec << RTC_CLOCKS_SHIFT) |
((uint32_t)frac & (CONFIG_RTC_FREQUENCY - 1));
ovf = (tp->tv_sec >> (32 - RTC_CLOCKS_SHIFT));
/* Then return the broken out time */
@ -609,8 +613,10 @@ int up_rtc_gettime(FAR struct timespec *tp)
/* Then we can save the time in seconds and fractional seconds. */
tp->tv_sec = (ms << (32-RTC_CLOCKS_SHIFT-16)) | (ls >> (RTC_CLOCKS_SHIFT+16));
tp->tv_nsec = (ls & (CONFIG_RTC_FREQUENCY-1)) * (1000000000/CONFIG_RTC_FREQUENCY);
tp->tv_sec = (ms << (32 - RTC_CLOCKS_SHIFT - 16)) |
(ls >> (RTC_CLOCKS_SHIFT + 16));
tp->tv_nsec = (ls & (CONFIG_RTC_FREQUENCY - 1)) *
(1000000000 / CONFIG_RTC_FREQUENCY);
return OK;
}
#endif

6
arch/arm/src/stm32/stm32_waste.c
View file

@ -42,10 +42,10 @@
#include "stm32_waste.h"
/****************************************************************************
* Private Data
* Public Data
****************************************************************************/
uint32_t idle_wastecounter = 0;
uint32_t g_waste_counter = 0;
/****************************************************************************
* Public Functions
@ -53,5 +53,5 @@ uint32_t idle_wastecounter = 0;
void stm32_waste(void)
{
idle_wastecounter++;
g_waste_counter++;
}

2
arch/arm/src/stm32/stm32_waste.h
View file

@ -54,7 +54,7 @@ extern "C"
#endif
/****************************************************************************
* Public Functions
* Public Function Prototypes
****************************************************************************/
/** Waste CPU Time

2
arch/arm/src/stm32f7/stm32_flash.c
View file

@ -356,7 +356,7 @@ ssize_t up_progmem_eraseblock(size_t block)
while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY)
{
stm32_waste();
{
}
modifyreg32(STM32_FLASH_CR, FLASH_CR_SER, 0);
sem_unlock();

12
arch/arm/src/stm32l4/stm32l4_lse.c
View file

@ -87,9 +87,9 @@ void stm32l4_rcc_enablelse(void)
if ((regval & (RCC_BDCR_LSEON | RCC_BDCR_LSERDY)) !=
(RCC_BDCR_LSEON | RCC_BDCR_LSERDY))
{
/* The LSE is in the RTC domain and write access is denied to this domain
* after reset, you have to enable write access using DBP bit in the PWR CR
* register before to configuring the LSE.
/* The LSE is in the RTC domain and write access is denied to this
* domain after reset, you have to enable write access using DBP bit
* in the PWR CR register before to configuring the LSE.
*/
writable = stm32l4_pwr_enablebkp(true);
@ -133,8 +133,8 @@ void stm32l4_rcc_enablelse(void)
putreg32(regval, STM32L4_RCC_BDCR);
#endif
/* Disable backup domain access if it was disabled on entry */
/* Disable backup domain access if it was disabled on entry */
stm32l4_pwr_enablebkp(writable);
}
stm32l4_pwr_enablebkp(writable);
}
}

6
arch/arm/src/stm32l4/stm32l4_waste.c
View file

@ -42,10 +42,10 @@
#include "stm32l4_waste.h"
/****************************************************************************
* Private Data
* Public Data
****************************************************************************/
uint32_t idle_wastecounter = 0;
uint32_t g_waste_counter = 0;
/****************************************************************************
* Public Functions
@ -53,5 +53,5 @@ uint32_t idle_wastecounter = 0;
void stm32l4_waste(void)
{
idle_wastecounter++;
g_waste_counter++;
}

12
arch/arm/src/stm32l4/stm32l4_waste.h
View file

@ -57,16 +57,16 @@ extern "C"
* Public Function Prototypes
****************************************************************************/
/** Waste CPU Time
/* Waste CPU Time
*
* stm32l4_waste() is the logic that will be executed when portions of kernel
* or user-app is polling some register or similar, waiting for desired
* status. This time is wasted away. This function offers a measure of
* badly written piece of software or some undesired behavior.
* stm32l4_waste() is the logic that will be executed when portions of
* kernel or user-app is polling some register or similar, waiting for
* desired status. This time is wasted away. This function offers a
* measure of badly written piece of software or some undesired behavior.
*
* At the same time this function adds to some IDLE time which portion
* cannot be used for other purposes (yet).
**/
*/
void stm32l4_waste(void);