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SAMA5 EHCI: Add IOC error handling
This commit is contained in:
Gregory Nutt
parent
73efdf8d05
commit
da3ff83fc3
1 changed files with 104 additions and 33 deletions
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@ -180,6 +180,7 @@ struct sam_epinfo_s
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uint8_t toggle:1; /* Next data toggle */
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uint8_t xfrtype:2; /* See USB_EP_ATTR_XFER_* definitions in usb.h */
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uint8_t speed:2; /* See USB_*_SPEED definitions in ehci.h */
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uint8_t status; /* Retained token status bits (for debug purposes) */
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volatile bool iocwait; /* TRUE: Thread is waiting for transfer completion */
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uint16_t maxpacket; /* Maximum packet size */
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int result; /* The result of the transfer */
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@ -711,6 +712,8 @@ static void sam_takesem(sem_t *sem)
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* Description:
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* Allocate a Queue Head (QH) structure by removing it from the free list
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*
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* Assumption: Caller holds the exclsem
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*
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*******************************************************************************/
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static struct sam_qh_s *sam_qh_alloc(void)
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@ -735,6 +738,8 @@ static struct sam_qh_s *sam_qh_alloc(void)
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* Description:
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* Free a Queue Head (QH) structure by returning it to the free list
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*
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* Assumption: Caller holds the exclsem
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*
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*******************************************************************************/
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static void sam_qh_free(struct sam_qh_s *qh)
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@ -754,6 +759,8 @@ static void sam_qh_free(struct sam_qh_s *qh)
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* Allocate a Queue Element Transfer Descriptor (qTD) by removing it from the
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* free list
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*
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* Assumption: Caller holds the exclsem
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*
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*******************************************************************************/
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static struct sam_qtd_s *sam_qtd_alloc(void)
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@ -773,12 +780,14 @@ static struct sam_qtd_s *sam_qtd_alloc(void)
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}
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/*******************************************************************************
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* Name: sam_edfree
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* Name: sam_qtd_free
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*
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* Description:
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* Free a Queue Element Transfer Descriptor (qTD) by returning it to the free
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* list
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*
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* Assumption: Caller holds the exclsem
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*
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*******************************************************************************/
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static void sam_qtd_free(struct sam_qtd_s *qtd)
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@ -819,7 +828,7 @@ static int sam_qh_foreach(struct sam_qh_s *qh, uint32_t **bp, foreach_qh_t handl
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* terminate (T) bit. If T==1, then the HLP address is not valid.
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*/
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if ((qh->hw.hlp & QH_HLP_T) != 0)
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if ((sam_swap32(qh->hw.hlp) & QH_HLP_T) != 0)
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{
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/* Set the next pointer to NULL. This will terminate the loop. */
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@ -928,7 +937,7 @@ static int sam_qtd_foreach(struct sam_qh_s *qh, foreach_qtd_t handler, void *arg
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* terminate (T) bit. If T==1, then the NQP address is not valid.
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*/
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if ((qtd->hw.nqp & QTD_NQP_T) != 0)
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if ((sam_swap32(qtd->hw.nqp) & QTD_NQP_T) != 0)
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{
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/* Set the next pointer to NULL. This will terminate the loop. */
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@ -1141,8 +1150,10 @@ static int sam_ioc_setup(struct sam_rhport_s *rhport, struct sam_epinfo_s *epinf
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* completed.
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*/
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epinfo->iocwait = true;
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ret = OK;
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epinfo->iocwait = true; /* We want to be awakened by IOC interrupt */
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epinfo->status = 0; /* No status yet */
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epinfo->result = -EBUSY; /* Transfer in progress */
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ret = OK; /* We are good to go */
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}
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irqrestore(flags);
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@ -1280,37 +1291,26 @@ errout_with_iocwait:
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static int sam_qtd_ioccheck(struct sam_qtd_s *qtd, uint32_t **bp, void *arg)
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{
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DEBUGASSERT(qtd);
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/* Make sure we reload the QH from memory */
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cp15_invalidate_dcache((uintptr_t)&qtd->hw,
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(uintptr_t)&qtd->hw + sizeof(struct ehci_qtd_s));
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/* Is the qTD still active? */
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/* Remove the qTD from the list */
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if ((sam_swap32(qtd->hw.token) & QH_TOKEN_ACTIVE) == 0)
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{
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/* No.. remove the qTD from the list */
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**bp = qtd->hw.nqp;
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**bp = qtd->hw.nqp;
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/* NOTE that we don't check if the qTD is active nor do we check if there
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* are any errors reported in the qTD. If the transfer halted due to
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* an error, then I am not sure if we can believe this information anyway.
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* The only sure place to check for errors in in the QH overlay.
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*/
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/* Check the endpoint was halted (or other errors were reported). If
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* so, then set the result of the transfer as failed.
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*/
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#warning "Missing logic"
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/* Then release this QH by returning it to the free list */
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sam_qtd_free(qtd);
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}
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else
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{
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/* Otherwise, the next qTD pointer of this qTD will become the next
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* back pointer.
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*/
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*bp = &qtd->hw.nqp;
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}
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/* Release this QH by returning it to the free list */
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sam_qtd_free(qtd);
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return OK;
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}
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@ -1328,6 +1328,7 @@ static int sam_qtd_ioccheck(struct sam_qtd_s *qtd, uint32_t **bp, void *arg)
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static int sam_qh_ioccheck(struct sam_qh_s *qh, uint32_t **bp, void *arg)
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{
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struct sam_epinfo_s *epinfo;
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uint32_t token;
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int ret;
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DEBUGASSERT(qh && bp);
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@ -1337,7 +1338,36 @@ static int sam_qh_ioccheck(struct sam_qh_s *qh, uint32_t **bp, void *arg)
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cp15_invalidate_dcache((uintptr_t)&qh->hw,
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(uintptr_t)&qh->hw + sizeof(struct ehci_qh_s));
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/* Remove all active, attached qTD structures */
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/* Get the endpoint info pointer from the extended QH data */
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epinfo = qh->epinfo;
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DEBUGASSERT(epinfo);
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/* Paragraph 3.6.3: "The nine DWords in [the Transfer Overlay] area represent
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* a transaction working space for the host controller. The general
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* operational model is that the host controller can detect whether the
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* overlay area contains a description of an active transfer. If it does
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* not contain an active transfer, then it follows the Queue Head Horizontal
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* Link Pointer to the next queue head. The host controller will never follow
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* the Next Transfer Queue Element or Alternate Queue Element pointers unless
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* it is actively attempting to advance the queue ..."
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*/
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/* Is the qTD still active? */
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token = sam_swap32(qh->hw.overlay.token);
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uvdbg("EP%d TOKEN=%08x\n", epinfo->epno, token);
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if ((token & QH_TOKEN_ACTIVE) != 0)
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{
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/* Yes... we cannot process the QH while it is still active. Return
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* zero to visit the next QH in the list.
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*/
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return OK;
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}
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/* Remove all active, attached qTD structures from the inactive QH */
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ret = sam_qtd_foreach(qh, sam_qtd_ioccheck, NULL);
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if (ret < 0)
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@ -1357,14 +1387,34 @@ static int sam_qh_ioccheck(struct sam_qh_s *qh, uint32_t **bp, void *arg)
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**bp = qh->hw.overlay.nqp;
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/* Get the info pointer from the QH */
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/* Check for errors, update the data toggle */
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epinfo = qh->epinfo;
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if ((token & QH_TOKEN_ERRORS) == 0)
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{
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/* No errors.. Save the last data toggle value */
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/* Is there a thread waiting form this tranfer to complete? */
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epinfo->toggle = ((token & QTD_TOKEN_TOGGLE) != 0);
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/* Report success */
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epinfo->status = 0;
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epinfo->result = OK;
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}
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else
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{
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/* An error occurred */
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udbg("ERROR: EP%d TOKEN=%08x", epinfo->epno, token);
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epinfo->status = (token & QH_TOKEN_STATUS_MASK) >> QH_TOKEN_STATUS_SHIFT;
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epinfo->result = -EIO;
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}
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/* Is there a thread waiting for this transfer to complete? */
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if (epinfo->iocwait)
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{
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/* Yes... wake it up */
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sam_givesem(&epinfo->iocsem);
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epinfo->iocwait = 0;
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}
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@ -1396,6 +1446,8 @@ static int sam_qh_ioccheck(struct sam_qh_s *qh, uint32_t **bp, void *arg)
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* (actual number of bytes received was less than the expected number of
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* bytes)."
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*
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* Assumptions: The caller holds the EHCI exclsem
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*
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*******************************************************************************/
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static inline void sam_ioc_bottomhalf(void)
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@ -1610,6 +1662,13 @@ static void sam_ehci_bottomhalf(FAR void *arg)
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{
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uint32_t pending = (uint32_t)arg;
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/* We need to have exclusive access to the EHCI data structures. Waiting here
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* is not a good thing to do on the worker thread, but there is no real option
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* (other than to reschedule and delay).
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*/
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sam_takesem(&g_ehci.exclsem);
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/* Handle all unmasked interrupt sources */
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/* USB Interrupt (USBINT)
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*
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@ -1708,6 +1767,10 @@ static void sam_ehci_bottomhalf(FAR void *arg)
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sam_async_advance_bottomhalf();
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}
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/* We are done with the EHCI structures */
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sam_givesem(&g_ehci.exclsem);
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/* Re-enable relevant EHCI interrupts. Interrupts should still be enabled
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* at the level of the AIC.
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*/
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@ -2750,15 +2813,18 @@ FAR struct usbhost_connection_s *sam_ehci_initialize(int controller)
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*/
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memset(&g_asynchead, 0, sizeof(struct sam_qh_s));
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g_asynchead.hw.hlp = sam_swap32((uint32_t)&g_asynchead | QH_HLP_TYP_QH);
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physaddr = sam_physramaddr((uintptr_t)&g_asynchead);
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g_asynchead.hw.hlp = sam_swap32(physaddr | QH_HLP_TYP_QH);
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g_asynchead.hw.epchar = sam_swap32(QH_EPCHAR_H | QH_EPCHAR_EPS_FULL);
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g_asynchead.hw.overlay.nqp = sam_swap32(QH_NQP_T);
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g_asynchead.hw.overlay.alt = sam_swap32(QH_NQP_T);
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g_asynchead.hw.overlay.token = sam_swap32(QH_TOKEN_HALTED);
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cp15_coherent_dcache((uintptr_t)&g_asynchead.hw,
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(uintptr_t)&g_asynchead.hw + sizeof(struct ehci_qh_s));
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/* Set the Current Asynchronous List Address. */
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physaddr = sam_physramaddr((uintptr_t)&g_asynchead);
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sam_putreg(sam_swap32(physaddr), &HCOR->asynclistaddr);
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#ifndef CONFIG_USBHOST_INT_DISABLE
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@ -2781,6 +2847,11 @@ FAR struct usbhost_connection_s *sam_ehci_initialize(int controller)
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/* Set the Periodic Frame List Base Address. */
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cp15_coherent_dcache((uintptr_t)&g_perhead.hw,
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(uintptr_t)&g_perhead.hw + sizeof(struct ehci_qh_s));
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cp15_coherent_dcache((uintptr_t)g_framelist,
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(uintptr_t)g_framelist + FRAME_LIST_SIZE * sizeof(uint32_t));
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sam_putreg(sam_swap32(physaddr), &HCOR->periodiclistbase);
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#endif
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