From da13734f8267fa06745fb6a9cbfd88ad62dcae96 Mon Sep 17 00:00:00 2001 From: patacongo Date: Tue, 6 Dec 2011 19:31:28 +0000 Subject: [PATCH] Basic bring-up of the STM3240G-EVAL board is complete git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4138 42af7a65-404d-4744-a932-0658087f49c3 --- configs/stm3240g-eval/include/board.h | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/configs/stm3240g-eval/include/board.h b/configs/stm3240g-eval/include/board.h index b66997235ef..8ed7663430f 100755 --- a/configs/stm3240g-eval/include/board.h +++ b/configs/stm3240g-eval/include/board.h @@ -124,16 +124,16 @@ #define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY #define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* same as above, to satisfy compiler */ -/* APB2 clock (PCLK2) is HCLK/2 (84MHz) */ - -#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE1_HCLKd2 /* PCLK2 = HCLK / 2 */ -#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2) - /* APB1 clock (PCLK1) is HCLK/4 (42MHz) */ -#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE2_HCLKd4 /* PCLK1 = HCLK / 4 */ +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */ #define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4) +/* APB2 clock (PCLK2) is HCLK/2 (84MHz) */ + +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2) + /* Timer Frequencies, if APBx is set to 1, frequency is same to APBx * otherwise frequency is 2xAPBx. * Note: TIM1,8 are on APB2, others on APB1