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Fix nuttx coding style

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Remove TABs
Fix indentation
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simbit18 2023-07-14 10:44:16 +02:00 • committed by Xiang Xiao
parent a8939f6d4b
commit d991ef77e8
17 changed files with 731 additions and 731 deletions
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320
arch/arm/src/cxd56xx/hardware/cxd56_scu.h
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@ -21,165 +21,165 @@
#ifndef __ARCH_ARM_SRC_CXD56XX_HARDWARE_CXD56_SCU_H
#define __ARCH_ARM_SRC_CXD56XX_HARDWARE_CXD56_SCU_H
#define SCU_DEBUG_I2C0 (CXD56_SCU_BASE + 0x0018)
#define SCU_DEBUG_I2C1 (CXD56_SCU_BASE + 0x001c)
#define SCU_SEQ_ENABLE_ALL (CXD56_SCU_BASE + 0x0020)
#define SCU_SEQ_ACCESS_INHIBIT (CXD56_SCU_BASE + 0x0024)
#define SCU_START_CTRL_COMMON (CXD56_SCU_BASE + 0x0028)
#define SCU_START_MODE0 (CXD56_SCU_BASE + 0x002c)
#define SCU_START_MODE1 (CXD56_SCU_BASE + 0x0030)
#define SCU_START_INTERVAL3_0 (CXD56_SCU_BASE + 0x0034)
#define SCU_START_INTERVAL7_4 (CXD56_SCU_BASE + 0x0038)
#define SCU_START_INTERVAL9_8 (CXD56_SCU_BASE + 0x003c)
#define SCU_START_PHASE1_0 (CXD56_SCU_BASE + 0x0040)
#define SCU_START_PHASE3_2 (CXD56_SCU_BASE + 0x0044)
#define SCU_START_PHASE5_4 (CXD56_SCU_BASE + 0x0048)
#define SCU_START_PHASE7_6 (CXD56_SCU_BASE + 0x004c)
#define SCU_START_PHASE9_8 (CXD56_SCU_BASE + 0x0050)
#define SCU_SINGLE_EXE (CXD56_SCU_BASE + 0x0054)
#define SCU_START_CTRL_STT0 (CXD56_SCU_BASE + 0x0058)
#define SCU_START_CTRL_STT1 (CXD56_SCU_BASE + 0x005c)
#define SCU_DEBUG_CTRL (CXD56_SCU_BASE + 0x0060)
#define SCU_OFST_GAIN_EN (CXD56_SCU_BASE + 0x0070)
#define SCU_UNSIGNED_TO_SIGNED (CXD56_SCU_BASE + 0x0074)
#define SCU_DEC_CLR (CXD56_SCU_BASE + 0x0078)
#define SCU_MATHFUNC_CLR (CXD56_SCU_BASE + 0x007c)
#define SCU_EVENT_STT (CXD56_SCU_BASE + 0x0080)
#define SCU_DECIMATION_PARAM0 (CXD56_SCU_BASE + 0x0084)
#define SCU_DECIMATION_PARAM1 (CXD56_SCU_BASE + 0x0088)
#define SCU_MATHFUNC_SEL (CXD56_SCU_BASE + 0x008c)
#define SCU_MATHFUNC_POS0 (CXD56_SCU_BASE + 0x0090)
#define SCU_MATHFUNC_POS1 (CXD56_SCU_BASE + 0x0094)
#define SCU_MATHFUNC_POS2 (CXD56_SCU_BASE + 0x0098)
#define SCU_MATHFUNC_POS(n) (SCU_MATHFUNC_POS0 + (n * 4))
#define SCU_MATHFUNC_PARAM_0_0 (CXD56_SCU_BASE + 0x00a0)
#define SCU_MATHFUNC_PARAM_C0_0_0_MSB (CXD56_SCU_BASE + 0x00a4)
#define SCU_MATHFUNC_PARAM_C0_0_0_LSB (CXD56_SCU_BASE + 0x00a8)
#define SCU_MATHFUNC_PARAM_C1_0_0_MSB (CXD56_SCU_BASE + 0x00b0)
#define SCU_MATHFUNC_PARAM_C1_0_0_LSB (CXD56_SCU_BASE + 0x00b4)
#define SCU_MATHFUNC_PARAM_C2_0_0_MSB (CXD56_SCU_BASE + 0x00b8)
#define SCU_MATHFUNC_PARAM_C2_0_0_LSB (CXD56_SCU_BASE + 0x00bc)
#define SCU_MATHFUNC_PARAM_C3_0_0_MSB (CXD56_SCU_BASE + 0x00d0)
#define SCU_MATHFUNC_PARAM_C3_0_0_LSB (CXD56_SCU_BASE + 0x00d4)
#define SCU_MATHFUNC_PARAM_C4_0_0_MSB (CXD56_SCU_BASE + 0x00d8)
#define SCU_MATHFUNC_PARAM_C4_0_0_LSB (CXD56_SCU_BASE + 0x00dc)
#define SCU_MATHFUNC_PARAM_0_1 (CXD56_SCU_BASE + 0x00e0)
#define SCU_MATHFUNC_PARAM_C0_0_1_MSB (CXD56_SCU_BASE + 0x00e4)
#define SCU_MATHFUNC_PARAM_C0_0_1_LSB (CXD56_SCU_BASE + 0x00e8)
#define SCU_MATHFUNC_PARAM_C1_0_1_MSB (CXD56_SCU_BASE + 0x00ec)
#define SCU_MATHFUNC_PARAM_C1_0_1_LSB (CXD56_SCU_BASE + 0x00f0)
#define SCU_MATHFUNC_PARAM_C2_0_1_MSB (CXD56_SCU_BASE + 0x00f4)
#define SCU_MATHFUNC_PARAM_C2_0_1_LSB (CXD56_SCU_BASE + 0x00f8)
#define SCU_MATHFUNC_PARAM_C3_0_1_MSB (CXD56_SCU_BASE + 0x00fc)
#define SCU_MATHFUNC_PARAM_C3_0_1_LSB (CXD56_SCU_BASE + 0x0100)
#define SCU_MATHFUNC_PARAM_C4_0_1_MSB (CXD56_SCU_BASE + 0x0104)
#define SCU_MATHFUNC_PARAM_C4_0_1_LSB (CXD56_SCU_BASE + 0x0108)
#define SCU_MATHFUNC_PARAM_1_0 (CXD56_SCU_BASE + 0x010c)
#define SCU_MATHFUNC_PARAM_C0_1_0_MSB (CXD56_SCU_BASE + 0x0110)
#define SCU_MATHFUNC_PARAM_C0_1_0_LSB (CXD56_SCU_BASE + 0x0114)
#define SCU_MATHFUNC_PARAM_C1_1_0_MSB (CXD56_SCU_BASE + 0x0118)
#define SCU_MATHFUNC_PARAM_C1_1_0_LSB (CXD56_SCU_BASE + 0x011c)
#define SCU_MATHFUNC_PARAM_C2_1_0_MSB (CXD56_SCU_BASE + 0x0120)
#define SCU_MATHFUNC_PARAM_C2_1_0_LSB (CXD56_SCU_BASE + 0x0124)
#define SCU_MATHFUNC_PARAM_C3_1_0_MSB (CXD56_SCU_BASE + 0x0128)
#define SCU_MATHFUNC_PARAM_C3_1_0_LSB (CXD56_SCU_BASE + 0x012c)
#define SCU_MATHFUNC_PARAM_C4_1_0_MSB (CXD56_SCU_BASE + 0x0130)
#define SCU_MATHFUNC_PARAM_C4_1_0_LSB (CXD56_SCU_BASE + 0x0134)
#define SCU_MATHFUNC_PARAM_1_1 (CXD56_SCU_BASE + 0x0138)
#define SCU_MATHFUNC_PARAM_C0_1_1_MSB (CXD56_SCU_BASE + 0x013c)
#define SCU_MATHFUNC_PARAM_C0_1_1_LSB (CXD56_SCU_BASE + 0x0140)
#define SCU_MATHFUNC_PARAM_C1_1_1_MSB (CXD56_SCU_BASE + 0x0144)
#define SCU_MATHFUNC_PARAM_C1_1_1_LSB (CXD56_SCU_BASE + 0x0148)
#define SCU_MATHFUNC_PARAM_C2_1_1_MSB (CXD56_SCU_BASE + 0x014c)
#define SCU_MATHFUNC_PARAM_C2_1_1_LSB (CXD56_SCU_BASE + 0x0150)
#define SCU_MATHFUNC_PARAM_C3_1_1_MSB (CXD56_SCU_BASE + 0x0154)
#define SCU_MATHFUNC_PARAM_C3_1_1_LSB (CXD56_SCU_BASE + 0x0158)
#define SCU_MATHFUNC_PARAM_C4_1_1_MSB (CXD56_SCU_BASE + 0x015c)
#define SCU_MATHFUNC_PARAM_C4_1_1_LSB (CXD56_SCU_BASE + 0x0160)
#define SCU_MATHFUNC_PARAM_2_0 (CXD56_SCU_BASE + 0x0164)
#define SCU_MATHFUNC_PARAM_C0_2_0_MSB (CXD56_SCU_BASE + 0x0168)
#define SCU_MATHFUNC_PARAM_C0_2_0_LSB (CXD56_SCU_BASE + 0x016c)
#define SCU_MATHFUNC_PARAM_C1_2_0_MSB (CXD56_SCU_BASE + 0x0170)
#define SCU_MATHFUNC_PARAM_C1_2_0_LSB (CXD56_SCU_BASE + 0x0174)
#define SCU_MATHFUNC_PARAM_C2_2_0_MSB (CXD56_SCU_BASE + 0x0178)
#define SCU_MATHFUNC_PARAM_C2_2_0_LSB (CXD56_SCU_BASE + 0x017c)
#define SCU_MATHFUNC_PARAM_C3_2_0_MSB (CXD56_SCU_BASE + 0x0180)
#define SCU_MATHFUNC_PARAM_C3_2_0_LSB (CXD56_SCU_BASE + 0x0184)
#define SCU_MATHFUNC_PARAM_C4_2_0_MSB (CXD56_SCU_BASE + 0x0188)
#define SCU_MATHFUNC_PARAM_C4_2_0_LSB (CXD56_SCU_BASE + 0x018c)
#define SCU_MATHFUNC_PARAM_2_1 (CXD56_SCU_BASE + 0x0190)
#define SCU_MATHFUNC_PARAM_C0_2_1_MSB (CXD56_SCU_BASE + 0x0194)
#define SCU_MATHFUNC_PARAM_C0_2_1_LSB (CXD56_SCU_BASE + 0x0198)
#define SCU_MATHFUNC_PARAM_C1_2_1_MSB (CXD56_SCU_BASE + 0x019c)
#define SCU_MATHFUNC_PARAM_C1_2_1_LSB (CXD56_SCU_BASE + 0x01a0)
#define SCU_MATHFUNC_PARAM_C2_2_1_MSB (CXD56_SCU_BASE + 0x01a4)
#define SCU_MATHFUNC_PARAM_C2_2_1_LSB (CXD56_SCU_BASE + 0x01a8)
#define SCU_MATHFUNC_PARAM_C3_2_1_MSB (CXD56_SCU_BASE + 0x01ac)
#define SCU_MATHFUNC_PARAM_C3_2_1_LSB (CXD56_SCU_BASE + 0x01b0)
#define SCU_MATHFUNC_PARAM_C4_2_1_MSB (CXD56_SCU_BASE + 0x01b4)
#define SCU_MATHFUNC_PARAM_C4_2_1_LSB (CXD56_SCU_BASE + 0x01b8)
#define SCU_EVENT_PARAM_THRESH(n) (SCU_EVENT_PARAM0_THRESH + ((n) * 0x10))
#define SCU_EVENT_PARAM_COUNT0(n) (SCU_EVENT_PARAM0_COUNT0 + ((n) * 0x10))
#define SCU_EVENT_PARAM_COUNT1(n) (SCU_EVENT_PARAM0_COUNT1 + ((n) * 0x10))
#define SCU_EVENT_INTR_ENABLE(n) (SCU_EVENT_PARAM0_COUNT2 + ((n) * 0x10))
#define SCU_EVENT_PARAM_DELAY_SAMPLE(n) (SCU_EVENT_PARAM0_DELAY_SAMPLE + ((n) * 0x4))
#define SCU_EVENT_PARAM0_THRESH (CXD56_SCU_BASE + 0x01bc)
#define SCU_EVENT_PARAM0_COUNT0 (CXD56_SCU_BASE + 0x01c0)
#define SCU_EVENT_PARAM0_COUNT1 (CXD56_SCU_BASE + 0x01c4)
#define SCU_EVENT_PARAM0_COUNT2 (CXD56_SCU_BASE + 0x01c8)
#define SCU_EVENT_PARAM1_THRESH (CXD56_SCU_BASE + 0x01cc)
#define SCU_EVENT_PARAM1_COUNT0 (CXD56_SCU_BASE + 0x01d0)
#define SCU_EVENT_PARAM1_COUNT1 (CXD56_SCU_BASE + 0x01d4)
#define SCU_EVENT_PARAM1_COUNT2 (CXD56_SCU_BASE + 0x01d8)
#define SCU_EVENT_PARAM2_THRESH (CXD56_SCU_BASE + 0x01dc)
#define SCU_EVENT_PARAM2_COUNT0 (CXD56_SCU_BASE + 0x01e0)
#define SCU_EVENT_PARAM2_COUNT1 (CXD56_SCU_BASE + 0x01e4)
#define SCU_EVENT_PARAM2_COUNT2 (CXD56_SCU_BASE + 0x01e8)
#define SCU_EVENT_PARAM0_DELAY_SAMPLE (CXD56_SCU_BASE + 0x01ec)
#define SCU_EVENT_PARAM1_DELAY_SAMPLE (CXD56_SCU_BASE + 0x01f0)
#define SCU_EVENT_PARAM2_DELAY_SAMPLE (CXD56_SCU_BASE + 0x01f4)
#define SCU_EVENT_TIMESTAMP0_R_MSB (CXD56_SCU_BASE + 0x0200)
#define SCU_EVENT_TIMESTAMP0_R_LSB (CXD56_SCU_BASE + 0x0204)
#define SCU_EVENT_TIMESTAMP1_R_MSB (CXD56_SCU_BASE + 0x0208)
#define SCU_EVENT_TIMESTAMP1_R_LSB (CXD56_SCU_BASE + 0x020c)
#define SCU_EVENT_TIMESTAMP2_R_MSB (CXD56_SCU_BASE + 0x0210)
#define SCU_EVENT_TIMESTAMP2_R_LSB (CXD56_SCU_BASE + 0x0214)
#define SCU_EVENT_TIMESTAMP0_F_MSB (CXD56_SCU_BASE + 0x0218)
#define SCU_EVENT_TIMESTAMP0_F_LSB (CXD56_SCU_BASE + 0x021c)
#define SCU_EVENT_TIMESTAMP1_F_MSB (CXD56_SCU_BASE + 0x0220)
#define SCU_EVENT_TIMESTAMP1_F_LSB (CXD56_SCU_BASE + 0x0224)
#define SCU_EVENT_TIMESTAMP2_F_MSB (CXD56_SCU_BASE + 0x0228)
#define SCU_EVENT_TIMESTAMP2_F_LSB (CXD56_SCU_BASE + 0x022c)
#define SCU_FIFO_WRITE_CTRL (CXD56_SCU_BASE + 0x0230)
#define SCU_DMA0_SEL (CXD56_SCU_BASE + 0x0300)
#define SCU_INT_ENABLE_MAIN (CXD56_SCU_BASE + 0x0400)
#define SCU_INT_DISABLE_MAIN (CXD56_SCU_BASE + 0x0404)
#define SCU_INT_CLEAR_MAIN (CXD56_SCU_BASE + 0x0408)
#define SCU_LEVEL_SEL_MAIN (CXD56_SCU_BASE + 0x040c)
#define SCU_INT_RAW_STT_MAIN (CXD56_SCU_BASE + 0x0410)
#define SCU_INT_MASKED_STT_MAIN (CXD56_SCU_BASE + 0x0414)
#define SCU_INT_ENABLE_ERR_0 (CXD56_SCU_BASE + 0x0420)
#define SCU_INT_DISABLE_ERR_0 (CXD56_SCU_BASE + 0x0424)
#define SCU_INT_CLEAR_ERR_0 (CXD56_SCU_BASE + 0x0428)
#define SCU_INT_RAW_STT_ERR_0 (CXD56_SCU_BASE + 0x042c)
#define SCU_INT_MASKED_STT_ERR_0 (CXD56_SCU_BASE + 0x0430)
#define SCU_INT_ENABLE_ERR_1 (CXD56_SCU_BASE + 0x0440)
#define SCU_INT_DISABLE_ERR_1 (CXD56_SCU_BASE + 0x0444)
#define SCU_INT_CLEAR_ERR_1 (CXD56_SCU_BASE + 0x0448)
#define SCU_INT_RAW_STT_ERR_1 (CXD56_SCU_BASE + 0x044c)
#define SCU_INT_MASKED_STT_ERR_1 (CXD56_SCU_BASE + 0x0450)
#define SCU_INT_ENABLE_ERR_2 (CXD56_SCU_BASE + 0x0460)
#define SCU_INT_DISABLE_ERR_2 (CXD56_SCU_BASE + 0x0464)
#define SCU_INT_CLEAR_ERR_2 (CXD56_SCU_BASE + 0x0468)
#define SCU_INT_RAW_STT_ERR_2 (CXD56_SCU_BASE + 0x046c)
#define SCU_INT_MASKED_STT_ERR_2 (CXD56_SCU_BASE + 0x0470)
#define SCU_RAM_TEST (CXD56_SCU_BASE + 0x0500)
#define SCU_POWER (CXD56_SCU_BASE + 0x0510)
#define SCU_INT_ENABLE_MAIN_AD (CXD56_SCU_BASE + 0x0520)
#define SCU_INT_DISABLE_MAIN_AD (CXD56_SCU_BASE + 0x0524)
#define SCU_INT_CLEAR_MAIN_AD (CXD56_SCU_BASE + 0x0528)
#define SCU_INT_LEVEL_SEL_MAIN_AD (CXD56_SCU_BASE + 0x052c)
#define SCU_INT_RAW_STT_MAIN_AD (CXD56_SCU_BASE + 0x0530)
#define SCU_INT_MASKED_STT_MAIN_AD (CXD56_SCU_BASE + 0x0534)
#define SCU_DEBUG_I2C0 (CXD56_SCU_BASE + 0x0018)
#define SCU_DEBUG_I2C1 (CXD56_SCU_BASE + 0x001c)
#define SCU_SEQ_ENABLE_ALL (CXD56_SCU_BASE + 0x0020)
#define SCU_SEQ_ACCESS_INHIBIT (CXD56_SCU_BASE + 0x0024)
#define SCU_START_CTRL_COMMON (CXD56_SCU_BASE + 0x0028)
#define SCU_START_MODE0 (CXD56_SCU_BASE + 0x002c)
#define SCU_START_MODE1 (CXD56_SCU_BASE + 0x0030)
#define SCU_START_INTERVAL3_0 (CXD56_SCU_BASE + 0x0034)
#define SCU_START_INTERVAL7_4 (CXD56_SCU_BASE + 0x0038)
#define SCU_START_INTERVAL9_8 (CXD56_SCU_BASE + 0x003c)
#define SCU_START_PHASE1_0 (CXD56_SCU_BASE + 0x0040)
#define SCU_START_PHASE3_2 (CXD56_SCU_BASE + 0x0044)
#define SCU_START_PHASE5_4 (CXD56_SCU_BASE + 0x0048)
#define SCU_START_PHASE7_6 (CXD56_SCU_BASE + 0x004c)
#define SCU_START_PHASE9_8 (CXD56_SCU_BASE + 0x0050)
#define SCU_SINGLE_EXE (CXD56_SCU_BASE + 0x0054)
#define SCU_START_CTRL_STT0 (CXD56_SCU_BASE + 0x0058)
#define SCU_START_CTRL_STT1 (CXD56_SCU_BASE + 0x005c)
#define SCU_DEBUG_CTRL (CXD56_SCU_BASE + 0x0060)
#define SCU_OFST_GAIN_EN (CXD56_SCU_BASE + 0x0070)
#define SCU_UNSIGNED_TO_SIGNED (CXD56_SCU_BASE + 0x0074)
#define SCU_DEC_CLR (CXD56_SCU_BASE + 0x0078)
#define SCU_MATHFUNC_CLR (CXD56_SCU_BASE + 0x007c)
#define SCU_EVENT_STT (CXD56_SCU_BASE + 0x0080)
#define SCU_DECIMATION_PARAM0 (CXD56_SCU_BASE + 0x0084)
#define SCU_DECIMATION_PARAM1 (CXD56_SCU_BASE + 0x0088)
#define SCU_MATHFUNC_SEL (CXD56_SCU_BASE + 0x008c)
#define SCU_MATHFUNC_POS0 (CXD56_SCU_BASE + 0x0090)
#define SCU_MATHFUNC_POS1 (CXD56_SCU_BASE + 0x0094)
#define SCU_MATHFUNC_POS2 (CXD56_SCU_BASE + 0x0098)
#define SCU_MATHFUNC_POS(n) (SCU_MATHFUNC_POS0 + (n * 4))
#define SCU_MATHFUNC_PARAM_0_0 (CXD56_SCU_BASE + 0x00a0)
#define SCU_MATHFUNC_PARAM_C0_0_0_MSB (CXD56_SCU_BASE + 0x00a4)
#define SCU_MATHFUNC_PARAM_C0_0_0_LSB (CXD56_SCU_BASE + 0x00a8)
#define SCU_MATHFUNC_PARAM_C1_0_0_MSB (CXD56_SCU_BASE + 0x00b0)
#define SCU_MATHFUNC_PARAM_C1_0_0_LSB (CXD56_SCU_BASE + 0x00b4)
#define SCU_MATHFUNC_PARAM_C2_0_0_MSB (CXD56_SCU_BASE + 0x00b8)
#define SCU_MATHFUNC_PARAM_C2_0_0_LSB (CXD56_SCU_BASE + 0x00bc)
#define SCU_MATHFUNC_PARAM_C3_0_0_MSB (CXD56_SCU_BASE + 0x00d0)
#define SCU_MATHFUNC_PARAM_C3_0_0_LSB (CXD56_SCU_BASE + 0x00d4)
#define SCU_MATHFUNC_PARAM_C4_0_0_MSB (CXD56_SCU_BASE + 0x00d8)
#define SCU_MATHFUNC_PARAM_C4_0_0_LSB (CXD56_SCU_BASE + 0x00dc)
#define SCU_MATHFUNC_PARAM_0_1 (CXD56_SCU_BASE + 0x00e0)
#define SCU_MATHFUNC_PARAM_C0_0_1_MSB (CXD56_SCU_BASE + 0x00e4)
#define SCU_MATHFUNC_PARAM_C0_0_1_LSB (CXD56_SCU_BASE + 0x00e8)
#define SCU_MATHFUNC_PARAM_C1_0_1_MSB (CXD56_SCU_BASE + 0x00ec)
#define SCU_MATHFUNC_PARAM_C1_0_1_LSB (CXD56_SCU_BASE + 0x00f0)
#define SCU_MATHFUNC_PARAM_C2_0_1_MSB (CXD56_SCU_BASE + 0x00f4)
#define SCU_MATHFUNC_PARAM_C2_0_1_LSB (CXD56_SCU_BASE + 0x00f8)
#define SCU_MATHFUNC_PARAM_C3_0_1_MSB (CXD56_SCU_BASE + 0x00fc)
#define SCU_MATHFUNC_PARAM_C3_0_1_LSB (CXD56_SCU_BASE + 0x0100)
#define SCU_MATHFUNC_PARAM_C4_0_1_MSB (CXD56_SCU_BASE + 0x0104)
#define SCU_MATHFUNC_PARAM_C4_0_1_LSB (CXD56_SCU_BASE + 0x0108)
#define SCU_MATHFUNC_PARAM_1_0 (CXD56_SCU_BASE + 0x010c)
#define SCU_MATHFUNC_PARAM_C0_1_0_MSB (CXD56_SCU_BASE + 0x0110)
#define SCU_MATHFUNC_PARAM_C0_1_0_LSB (CXD56_SCU_BASE + 0x0114)
#define SCU_MATHFUNC_PARAM_C1_1_0_MSB (CXD56_SCU_BASE + 0x0118)
#define SCU_MATHFUNC_PARAM_C1_1_0_LSB (CXD56_SCU_BASE + 0x011c)
#define SCU_MATHFUNC_PARAM_C2_1_0_MSB (CXD56_SCU_BASE + 0x0120)
#define SCU_MATHFUNC_PARAM_C2_1_0_LSB (CXD56_SCU_BASE + 0x0124)
#define SCU_MATHFUNC_PARAM_C3_1_0_MSB (CXD56_SCU_BASE + 0x0128)
#define SCU_MATHFUNC_PARAM_C3_1_0_LSB (CXD56_SCU_BASE + 0x012c)
#define SCU_MATHFUNC_PARAM_C4_1_0_MSB (CXD56_SCU_BASE + 0x0130)
#define SCU_MATHFUNC_PARAM_C4_1_0_LSB (CXD56_SCU_BASE + 0x0134)
#define SCU_MATHFUNC_PARAM_1_1 (CXD56_SCU_BASE + 0x0138)
#define SCU_MATHFUNC_PARAM_C0_1_1_MSB (CXD56_SCU_BASE + 0x013c)
#define SCU_MATHFUNC_PARAM_C0_1_1_LSB (CXD56_SCU_BASE + 0x0140)
#define SCU_MATHFUNC_PARAM_C1_1_1_MSB (CXD56_SCU_BASE + 0x0144)
#define SCU_MATHFUNC_PARAM_C1_1_1_LSB (CXD56_SCU_BASE + 0x0148)
#define SCU_MATHFUNC_PARAM_C2_1_1_MSB (CXD56_SCU_BASE + 0x014c)
#define SCU_MATHFUNC_PARAM_C2_1_1_LSB (CXD56_SCU_BASE + 0x0150)
#define SCU_MATHFUNC_PARAM_C3_1_1_MSB (CXD56_SCU_BASE + 0x0154)
#define SCU_MATHFUNC_PARAM_C3_1_1_LSB (CXD56_SCU_BASE + 0x0158)
#define SCU_MATHFUNC_PARAM_C4_1_1_MSB (CXD56_SCU_BASE + 0x015c)
#define SCU_MATHFUNC_PARAM_C4_1_1_LSB (CXD56_SCU_BASE + 0x0160)
#define SCU_MATHFUNC_PARAM_2_0 (CXD56_SCU_BASE + 0x0164)
#define SCU_MATHFUNC_PARAM_C0_2_0_MSB (CXD56_SCU_BASE + 0x0168)
#define SCU_MATHFUNC_PARAM_C0_2_0_LSB (CXD56_SCU_BASE + 0x016c)
#define SCU_MATHFUNC_PARAM_C1_2_0_MSB (CXD56_SCU_BASE + 0x0170)
#define SCU_MATHFUNC_PARAM_C1_2_0_LSB (CXD56_SCU_BASE + 0x0174)
#define SCU_MATHFUNC_PARAM_C2_2_0_MSB (CXD56_SCU_BASE + 0x0178)
#define SCU_MATHFUNC_PARAM_C2_2_0_LSB (CXD56_SCU_BASE + 0x017c)
#define SCU_MATHFUNC_PARAM_C3_2_0_MSB (CXD56_SCU_BASE + 0x0180)
#define SCU_MATHFUNC_PARAM_C3_2_0_LSB (CXD56_SCU_BASE + 0x0184)
#define SCU_MATHFUNC_PARAM_C4_2_0_MSB (CXD56_SCU_BASE + 0x0188)
#define SCU_MATHFUNC_PARAM_C4_2_0_LSB (CXD56_SCU_BASE + 0x018c)
#define SCU_MATHFUNC_PARAM_2_1 (CXD56_SCU_BASE + 0x0190)
#define SCU_MATHFUNC_PARAM_C0_2_1_MSB (CXD56_SCU_BASE + 0x0194)
#define SCU_MATHFUNC_PARAM_C0_2_1_LSB (CXD56_SCU_BASE + 0x0198)
#define SCU_MATHFUNC_PARAM_C1_2_1_MSB (CXD56_SCU_BASE + 0x019c)
#define SCU_MATHFUNC_PARAM_C1_2_1_LSB (CXD56_SCU_BASE + 0x01a0)
#define SCU_MATHFUNC_PARAM_C2_2_1_MSB (CXD56_SCU_BASE + 0x01a4)
#define SCU_MATHFUNC_PARAM_C2_2_1_LSB (CXD56_SCU_BASE + 0x01a8)
#define SCU_MATHFUNC_PARAM_C3_2_1_MSB (CXD56_SCU_BASE + 0x01ac)
#define SCU_MATHFUNC_PARAM_C3_2_1_LSB (CXD56_SCU_BASE + 0x01b0)
#define SCU_MATHFUNC_PARAM_C4_2_1_MSB (CXD56_SCU_BASE + 0x01b4)
#define SCU_MATHFUNC_PARAM_C4_2_1_LSB (CXD56_SCU_BASE + 0x01b8)
#define SCU_EVENT_PARAM_THRESH(n) (SCU_EVENT_PARAM0_THRESH + ((n) * 0x10))
#define SCU_EVENT_PARAM_COUNT0(n) (SCU_EVENT_PARAM0_COUNT0 + ((n) * 0x10))
#define SCU_EVENT_PARAM_COUNT1(n) (SCU_EVENT_PARAM0_COUNT1 + ((n) * 0x10))
#define SCU_EVENT_INTR_ENABLE(n) (SCU_EVENT_PARAM0_COUNT2 + ((n) * 0x10))
#define SCU_EVENT_PARAM_DELAY_SAMPLE(n) (SCU_EVENT_PARAM0_DELAY_SAMPLE + ((n) * 0x4))
#define SCU_EVENT_PARAM0_THRESH (CXD56_SCU_BASE + 0x01bc)
#define SCU_EVENT_PARAM0_COUNT0 (CXD56_SCU_BASE + 0x01c0)
#define SCU_EVENT_PARAM0_COUNT1 (CXD56_SCU_BASE + 0x01c4)
#define SCU_EVENT_PARAM0_COUNT2 (CXD56_SCU_BASE + 0x01c8)
#define SCU_EVENT_PARAM1_THRESH (CXD56_SCU_BASE + 0x01cc)
#define SCU_EVENT_PARAM1_COUNT0 (CXD56_SCU_BASE + 0x01d0)
#define SCU_EVENT_PARAM1_COUNT1 (CXD56_SCU_BASE + 0x01d4)
#define SCU_EVENT_PARAM1_COUNT2 (CXD56_SCU_BASE + 0x01d8)
#define SCU_EVENT_PARAM2_THRESH (CXD56_SCU_BASE + 0x01dc)
#define SCU_EVENT_PARAM2_COUNT0 (CXD56_SCU_BASE + 0x01e0)
#define SCU_EVENT_PARAM2_COUNT1 (CXD56_SCU_BASE + 0x01e4)
#define SCU_EVENT_PARAM2_COUNT2 (CXD56_SCU_BASE + 0x01e8)
#define SCU_EVENT_PARAM0_DELAY_SAMPLE (CXD56_SCU_BASE + 0x01ec)
#define SCU_EVENT_PARAM1_DELAY_SAMPLE (CXD56_SCU_BASE + 0x01f0)
#define SCU_EVENT_PARAM2_DELAY_SAMPLE (CXD56_SCU_BASE + 0x01f4)
#define SCU_EVENT_TIMESTAMP0_R_MSB (CXD56_SCU_BASE + 0x0200)
#define SCU_EVENT_TIMESTAMP0_R_LSB (CXD56_SCU_BASE + 0x0204)
#define SCU_EVENT_TIMESTAMP1_R_MSB (CXD56_SCU_BASE + 0x0208)
#define SCU_EVENT_TIMESTAMP1_R_LSB (CXD56_SCU_BASE + 0x020c)
#define SCU_EVENT_TIMESTAMP2_R_MSB (CXD56_SCU_BASE + 0x0210)
#define SCU_EVENT_TIMESTAMP2_R_LSB (CXD56_SCU_BASE + 0x0214)
#define SCU_EVENT_TIMESTAMP0_F_MSB (CXD56_SCU_BASE + 0x0218)
#define SCU_EVENT_TIMESTAMP0_F_LSB (CXD56_SCU_BASE + 0x021c)
#define SCU_EVENT_TIMESTAMP1_F_MSB (CXD56_SCU_BASE + 0x0220)
#define SCU_EVENT_TIMESTAMP1_F_LSB (CXD56_SCU_BASE + 0x0224)
#define SCU_EVENT_TIMESTAMP2_F_MSB (CXD56_SCU_BASE + 0x0228)
#define SCU_EVENT_TIMESTAMP2_F_LSB (CXD56_SCU_BASE + 0x022c)
#define SCU_FIFO_WRITE_CTRL (CXD56_SCU_BASE + 0x0230)
#define SCU_DMA0_SEL (CXD56_SCU_BASE + 0x0300)
#define SCU_INT_ENABLE_MAIN (CXD56_SCU_BASE + 0x0400)
#define SCU_INT_DISABLE_MAIN (CXD56_SCU_BASE + 0x0404)
#define SCU_INT_CLEAR_MAIN (CXD56_SCU_BASE + 0x0408)
#define SCU_LEVEL_SEL_MAIN (CXD56_SCU_BASE + 0x040c)
#define SCU_INT_RAW_STT_MAIN (CXD56_SCU_BASE + 0x0410)
#define SCU_INT_MASKED_STT_MAIN (CXD56_SCU_BASE + 0x0414)
#define SCU_INT_ENABLE_ERR_0 (CXD56_SCU_BASE + 0x0420)
#define SCU_INT_DISABLE_ERR_0 (CXD56_SCU_BASE + 0x0424)
#define SCU_INT_CLEAR_ERR_0 (CXD56_SCU_BASE + 0x0428)
#define SCU_INT_RAW_STT_ERR_0 (CXD56_SCU_BASE + 0x042c)
#define SCU_INT_MASKED_STT_ERR_0 (CXD56_SCU_BASE + 0x0430)
#define SCU_INT_ENABLE_ERR_1 (CXD56_SCU_BASE + 0x0440)
#define SCU_INT_DISABLE_ERR_1 (CXD56_SCU_BASE + 0x0444)
#define SCU_INT_CLEAR_ERR_1 (CXD56_SCU_BASE + 0x0448)
#define SCU_INT_RAW_STT_ERR_1 (CXD56_SCU_BASE + 0x044c)
#define SCU_INT_MASKED_STT_ERR_1 (CXD56_SCU_BASE + 0x0450)
#define SCU_INT_ENABLE_ERR_2 (CXD56_SCU_BASE + 0x0460)
#define SCU_INT_DISABLE_ERR_2 (CXD56_SCU_BASE + 0x0464)
#define SCU_INT_CLEAR_ERR_2 (CXD56_SCU_BASE + 0x0468)
#define SCU_INT_RAW_STT_ERR_2 (CXD56_SCU_BASE + 0x046c)
#define SCU_INT_MASKED_STT_ERR_2 (CXD56_SCU_BASE + 0x0470)
#define SCU_RAM_TEST (CXD56_SCU_BASE + 0x0500)
#define SCU_POWER (CXD56_SCU_BASE + 0x0510)
#define SCU_INT_ENABLE_MAIN_AD (CXD56_SCU_BASE + 0x0520)
#define SCU_INT_DISABLE_MAIN_AD (CXD56_SCU_BASE + 0x0524)
#define SCU_INT_CLEAR_MAIN_AD (CXD56_SCU_BASE + 0x0528)
#define SCU_INT_LEVEL_SEL_MAIN_AD (CXD56_SCU_BASE + 0x052c)
#define SCU_INT_RAW_STT_MAIN_AD (CXD56_SCU_BASE + 0x0530)
#define SCU_INT_MASKED_STT_MAIN_AD (CXD56_SCU_BASE + 0x0534)
#endif /* __ARCH_ARM_SRC_CXD56XX_HARDWARE_CXD56_SCU_H */

710
arch/arm/src/cxd56xx/hardware/cxd56_scufifo.h
View file

@ -51,361 +51,361 @@
#define SCUFIFO_ADCINTERVAL(x) (((x) & 0xf) << 8) /* [W] ADC interval */
#define SCUFIFO_BPS(x) ((x) & 0xf) /* [W] Bytes per sample */
#define SCUFIFO_D0_W0_S_CTRL0 (CXD56_SCU_FIFO_REG_BASE + 0x0)
#define SCUFIFO_D0_W0_S_CTRL1 (CXD56_SCU_FIFO_REG_BASE + 0x4)
#define SCUFIFO_D0_W0_S_STATUS (CXD56_SCU_FIFO_REG_BASE + 0x8)
#define SCUFIFO_D0_W0_S_TIMSTAMP0 (CXD56_SCU_FIFO_REG_BASE + 0xc)
#define SCUFIFO_D0_W0_S_TIMSTAMP1 (CXD56_SCU_FIFO_REG_BASE + 0x10)
#define SCUFIFO_D0_W1_S_CTRL0 (CXD56_SCU_FIFO_REG_BASE + 0x20)
#define SCUFIFO_D0_W1_S_CTRL1 (CXD56_SCU_FIFO_REG_BASE + 0x24)
#define SCUFIFO_D0_W1_S_STATUS (CXD56_SCU_FIFO_REG_BASE + 0x28)
#define SCUFIFO_D0_W1_S_TIMSTAMP0 (CXD56_SCU_FIFO_REG_BASE + 0x2c)
#define SCUFIFO_D0_W1_S_TIMSTAMP1 (CXD56_SCU_FIFO_REG_BASE + 0x30)
#define SCUFIFO_D0_W2_S_CTRL0 (CXD56_SCU_FIFO_REG_BASE + 0x40)
#define SCUFIFO_D0_W2_S_CTRL1 (CXD56_SCU_FIFO_REG_BASE + 0x44)
#define SCUFIFO_D0_W2_S_STATUS (CXD56_SCU_FIFO_REG_BASE + 0x48)
#define SCUFIFO_D0_W2_S_TIMSTAMP0 (CXD56_SCU_FIFO_REG_BASE + 0x4c)
#define SCUFIFO_D0_W2_S_TIMSTAMP1 (CXD56_SCU_FIFO_REG_BASE + 0x50)
#define SCUFIFO_D0_W3_S_CTRL0 (CXD56_SCU_FIFO_REG_BASE + 0x60)
#define SCUFIFO_D0_W3_S_CTRL1 (CXD56_SCU_FIFO_REG_BASE + 0x64)
#define SCUFIFO_D0_W3_S_STATUS (CXD56_SCU_FIFO_REG_BASE + 0x68)
#define SCUFIFO_D0_W3_S_TIMSTAMP0 (CXD56_SCU_FIFO_REG_BASE + 0x6c)
#define SCUFIFO_D0_W3_S_TIMSTAMP1 (CXD56_SCU_FIFO_REG_BASE + 0x70)
#define SCUFIFO_D1_W0_S_CTRL0 (CXD56_SCU_FIFO_REG_BASE + 0x80)
#define SCUFIFO_D1_W0_S_CTRL1 (CXD56_SCU_FIFO_REG_BASE + 0x84)
#define SCUFIFO_D1_W0_S_STATUS (CXD56_SCU_FIFO_REG_BASE + 0x88)
#define SCUFIFO_D1_W0_S_TIMSTAMP0 (CXD56_SCU_FIFO_REG_BASE + 0x8c)
#define SCUFIFO_D1_W0_S_TIMSTAMP1 (CXD56_SCU_FIFO_REG_BASE + 0x90)
#define SCUFIFO_D1_W1_S_CTRL0 (CXD56_SCU_FIFO_REG_BASE + 0xa0)
#define SCUFIFO_D1_W1_S_CTRL1 (CXD56_SCU_FIFO_REG_BASE + 0xa4)
#define SCUFIFO_D1_W1_S_STATUS (CXD56_SCU_FIFO_REG_BASE + 0xa8)
#define SCUFIFO_D1_W1_S_TIMSTAMP0 (CXD56_SCU_FIFO_REG_BASE + 0xac)
#define SCUFIFO_D1_W1_S_TIMSTAMP1 (CXD56_SCU_FIFO_REG_BASE + 0xb0)
#define SCUFIFO_D1_W2_S_CTRL0 (CXD56_SCU_FIFO_REG_BASE + 0xc0)
#define SCUFIFO_D1_W2_S_CTRL1 (CXD56_SCU_FIFO_REG_BASE + 0xc4)
#define SCUFIFO_D1_W2_S_STATUS (CXD56_SCU_FIFO_REG_BASE + 0xc8)
#define SCUFIFO_D1_W2_S_TIMSTAMP0 (CXD56_SCU_FIFO_REG_BASE + 0xcc)
#define SCUFIFO_D1_W2_S_TIMSTAMP1 (CXD56_SCU_FIFO_REG_BASE + 0xd0)
#define SCUFIFO_D1_W3_S_CTRL0 (CXD56_SCU_FIFO_REG_BASE + 0xe0)
#define SCUFIFO_D1_W3_S_CTRL1 (CXD56_SCU_FIFO_REG_BASE + 0xe4)
#define SCUFIFO_D1_W3_S_STATUS (CXD56_SCU_FIFO_REG_BASE + 0xe8)
#define SCUFIFO_D1_W3_S_TIMSTAMP0 (CXD56_SCU_FIFO_REG_BASE + 0xec)
#define SCUFIFO_D1_W3_S_TIMSTAMP1 (CXD56_SCU_FIFO_REG_BASE + 0xf0)
#define SCUFIFO_N0_W_S_CTRL0 (CXD56_SCU_FIFO_REG_BASE + 0x100)
#define SCUFIFO_N0_W_S_CTRL1 (CXD56_SCU_FIFO_REG_BASE + 0x104)
#define SCUFIFO_N0_W_S_STATUS (CXD56_SCU_FIFO_REG_BASE + 0x108)
#define SCUFIFO_N0_W_S_TIMSTAMP0 (CXD56_SCU_FIFO_REG_BASE + 0x10c)
#define SCUFIFO_N0_W_S_TIMSTAMP1 (CXD56_SCU_FIFO_REG_BASE + 0x110)
#define SCUFIFO_N1_W_S_CTRL0 (CXD56_SCU_FIFO_REG_BASE + 0x120)
#define SCUFIFO_N1_W_S_CTRL1 (CXD56_SCU_FIFO_REG_BASE + 0x124)
#define SCUFIFO_N1_W_S_STATUS (CXD56_SCU_FIFO_REG_BASE + 0x128)
#define SCUFIFO_N1_W_S_TIMSTAMP0 (CXD56_SCU_FIFO_REG_BASE + 0x12c)
#define SCUFIFO_N1_W_S_TIMSTAMP1 (CXD56_SCU_FIFO_REG_BASE + 0x130)
#define SCUFIFO_N2_W_S_CTRL0 (CXD56_SCU_FIFO_REG_BASE + 0x140)
#define SCUFIFO_N2_W_S_CTRL1 (CXD56_SCU_FIFO_REG_BASE + 0x144)
#define SCUFIFO_N2_W_S_STATUS (CXD56_SCU_FIFO_REG_BASE + 0x148)
#define SCUFIFO_N2_W_S_TIMSTAMP0 (CXD56_SCU_FIFO_REG_BASE + 0x14c)
#define SCUFIFO_N2_W_S_TIMSTAMP1 (CXD56_SCU_FIFO_REG_BASE + 0x150)
#define SCUFIFO_N3_W_S_CTRL0 (CXD56_SCU_FIFO_REG_BASE + 0x160)
#define SCUFIFO_N3_W_S_CTRL1 (CXD56_SCU_FIFO_REG_BASE + 0x164)
#define SCUFIFO_N3_W_S_STATUS (CXD56_SCU_FIFO_REG_BASE + 0x168)
#define SCUFIFO_N3_W_S_TIMSTAMP0 (CXD56_SCU_FIFO_REG_BASE + 0x16c)
#define SCUFIFO_N3_W_S_TIMSTAMP1 (CXD56_SCU_FIFO_REG_BASE + 0x170)
#define SCUFIFO_N4_W_S_CTRL0 (CXD56_SCU_FIFO_REG_BASE + 0x180)
#define SCUFIFO_N4_W_S_CTRL1 (CXD56_SCU_FIFO_REG_BASE + 0x184)
#define SCUFIFO_N4_W_S_STATUS (CXD56_SCU_FIFO_REG_BASE + 0x188)
#define SCUFIFO_N4_W_S_TIMSTAMP0 (CXD56_SCU_FIFO_REG_BASE + 0x18c)
#define SCUFIFO_N4_W_S_TIMSTAMP1 (CXD56_SCU_FIFO_REG_BASE + 0x190)
#define SCUFIFO_N5_W_S_CTRL0 (CXD56_SCU_FIFO_REG_BASE + 0x1a0)
#define SCUFIFO_N5_W_S_CTRL1 (CXD56_SCU_FIFO_REG_BASE + 0x1a4)
#define SCUFIFO_N5_W_S_STATUS (CXD56_SCU_FIFO_REG_BASE + 0x1a8)
#define SCUFIFO_N5_W_S_TIMSTAMP0 (CXD56_SCU_FIFO_REG_BASE + 0x1ac)
#define SCUFIFO_N5_W_S_TIMSTAMP1 (CXD56_SCU_FIFO_REG_BASE + 0x1b0)
#define SCUFIFO_N6_W_S_CTRL0 (CXD56_SCU_FIFO_REG_BASE + 0x1c0)
#define SCUFIFO_N6_W_S_CTRL1 (CXD56_SCU_FIFO_REG_BASE + 0x1c4)
#define SCUFIFO_N6_W_S_STATUS (CXD56_SCU_FIFO_REG_BASE + 0x1c8)
#define SCUFIFO_N6_W_S_TIMSTAMP0 (CXD56_SCU_FIFO_REG_BASE + 0x1cc)
#define SCUFIFO_N6_W_S_TIMSTAMP1 (CXD56_SCU_FIFO_REG_BASE + 0x1d0)
#define SCUFIFO_N7_W_S_CTRL0 (CXD56_SCU_FIFO_REG_BASE + 0x1e0)
#define SCUFIFO_N7_W_S_CTRL1 (CXD56_SCU_FIFO_REG_BASE + 0x1e4)
#define SCUFIFO_N7_W_S_STATUS (CXD56_SCU_FIFO_REG_BASE + 0x1e8)
#define SCUFIFO_N7_W_S_TIMSTAMP0 (CXD56_SCU_FIFO_REG_BASE + 0x1ec)
#define SCUFIFO_N7_W_S_TIMSTAMP1 (CXD56_SCU_FIFO_REG_BASE + 0x1f0)
#define SCUFIFO_V0_W_C_CTRL0 (CXD56_SCU_FIFO_REG_BASE + 0x200)
#define SCUFIFO_V0_W_C_CTRL1 (CXD56_SCU_FIFO_REG_BASE + 0x204)
#define SCUFIFO_V0_W_C_STATUS (CXD56_SCU_FIFO_REG_BASE + 0x208)
#define SCUFIFO_V0_W_C_TIMSTAMP0 (CXD56_SCU_FIFO_REG_BASE + 0x20c)
#define SCUFIFO_V0_W_C_TIMSTAMP1 (CXD56_SCU_FIFO_REG_BASE + 0x210)
#define SCUFIFO_V0_W_C_TIMSTAMP_SET0 (CXD56_SCU_FIFO_REG_BASE + 0x214)
#define SCUFIFO_V0_W_C_TIMSTAMP_SET1 (CXD56_SCU_FIFO_REG_BASE + 0x218)
#define SCUFIFO_V1_W_C_CTRL0 (CXD56_SCU_FIFO_REG_BASE + 0x220)
#define SCUFIFO_V1_W_C_CTRL1 (CXD56_SCU_FIFO_REG_BASE + 0x224)
#define SCUFIFO_V1_W_C_STATUS (CXD56_SCU_FIFO_REG_BASE + 0x228)
#define SCUFIFO_V1_W_C_TIMSTAMP0 (CXD56_SCU_FIFO_REG_BASE + 0x22c)
#define SCUFIFO_V1_W_C_TIMSTAMP1 (CXD56_SCU_FIFO_REG_BASE + 0x230)
#define SCUFIFO_V1_W_C_TIMSTAMP_SET0 (CXD56_SCU_FIFO_REG_BASE + 0x234)
#define SCUFIFO_V1_W_C_TIMSTAMP_SET1 (CXD56_SCU_FIFO_REG_BASE + 0x238)
#define SCUFIFO_V2_W_C_CTRL0 (CXD56_SCU_FIFO_REG_BASE + 0x240)
#define SCUFIFO_V2_W_C_CTRL1 (CXD56_SCU_FIFO_REG_BASE + 0x244)
#define SCUFIFO_V2_W_C_STATUS (CXD56_SCU_FIFO_REG_BASE + 0x248)
#define SCUFIFO_V2_W_C_TIMSTAMP0 (CXD56_SCU_FIFO_REG_BASE + 0x24c)
#define SCUFIFO_V2_W_C_TIMSTAMP1 (CXD56_SCU_FIFO_REG_BASE + 0x250)
#define SCUFIFO_V2_W_C_TIMSTAMP_SET0 (CXD56_SCU_FIFO_REG_BASE + 0x254)
#define SCUFIFO_V2_W_C_TIMSTAMP_SET1 (CXD56_SCU_FIFO_REG_BASE + 0x258)
#define SCUFIFO_V3_W_C_CTRL0 (CXD56_SCU_FIFO_REG_BASE + 0x260)
#define SCUFIFO_V3_W_C_CTRL1 (CXD56_SCU_FIFO_REG_BASE + 0x264)
#define SCUFIFO_V3_W_C_STATUS (CXD56_SCU_FIFO_REG_BASE + 0x268)
#define SCUFIFO_V3_W_C_TIMSTAMP0 (CXD56_SCU_FIFO_REG_BASE + 0x26c)
#define SCUFIFO_V3_W_C_TIMSTAMP1 (CXD56_SCU_FIFO_REG_BASE + 0x270)
#define SCUFIFO_V3_W_C_TIMSTAMP_SET0 (CXD56_SCU_FIFO_REG_BASE + 0x274)
#define SCUFIFO_V3_W_C_TIMSTAMP_SET1 (CXD56_SCU_FIFO_REG_BASE + 0x278)
#define SCUFIFO_V4_W_C_CTRL0 (CXD56_SCU_FIFO_REG_BASE + 0x280)
#define SCUFIFO_V4_W_C_CTRL1 (CXD56_SCU_FIFO_REG_BASE + 0x284)
#define SCUFIFO_V4_W_C_STATUS (CXD56_SCU_FIFO_REG_BASE + 0x288)
#define SCUFIFO_V4_W_C_TIMSTAMP0 (CXD56_SCU_FIFO_REG_BASE + 0x28c)
#define SCUFIFO_V4_W_C_TIMSTAMP1 (CXD56_SCU_FIFO_REG_BASE + 0x290)
#define SCUFIFO_V4_W_C_TIMSTAMP_SET0 (CXD56_SCU_FIFO_REG_BASE + 0x294)
#define SCUFIFO_V4_W_C_TIMSTAMP_SET1 (CXD56_SCU_FIFO_REG_BASE + 0x298)
#define SCUFIFO_V5_W_C_CTRL0 (CXD56_SCU_FIFO_REG_BASE + 0x2a0)
#define SCUFIFO_V5_W_C_CTRL1 (CXD56_SCU_FIFO_REG_BASE + 0x2a4)
#define SCUFIFO_V5_W_C_STATUS (CXD56_SCU_FIFO_REG_BASE + 0x2a8)
#define SCUFIFO_V5_W_C_TIMSTAMP0 (CXD56_SCU_FIFO_REG_BASE + 0x2ac)
#define SCUFIFO_V5_W_C_TIMSTAMP1 (CXD56_SCU_FIFO_REG_BASE + 0x2b0)
#define SCUFIFO_V5_W_C_TIMSTAMP_SET0 (CXD56_SCU_FIFO_REG_BASE + 0x2b4)
#define SCUFIFO_V5_W_C_TIMSTAMP_SET1 (CXD56_SCU_FIFO_REG_BASE + 0x2b8)
#define SCUFIFO_V6_W_C_CTRL0 (CXD56_SCU_FIFO_REG_BASE + 0x2c0)
#define SCUFIFO_V6_W_C_CTRL1 (CXD56_SCU_FIFO_REG_BASE + 0x2c4)
#define SCUFIFO_V6_W_C_STATUS (CXD56_SCU_FIFO_REG_BASE + 0x2c8)
#define SCUFIFO_V6_W_C_TIMSTAMP0 (CXD56_SCU_FIFO_REG_BASE + 0x2cc)
#define SCUFIFO_V6_W_C_TIMSTAMP1 (CXD56_SCU_FIFO_REG_BASE + 0x2d0)
#define SCUFIFO_V6_W_C_TIMSTAMP_SET0 (CXD56_SCU_FIFO_REG_BASE + 0x2d4)
#define SCUFIFO_V6_W_C_TIMSTAMP_SET1 (CXD56_SCU_FIFO_REG_BASE + 0x2d8)
#define SCUFIFO_V7_W_C_CTRL0 (CXD56_SCU_FIFO_REG_BASE + 0x2e0)
#define SCUFIFO_V7_W_C_CTRL1 (CXD56_SCU_FIFO_REG_BASE + 0x2e4)
#define SCUFIFO_V7_W_C_STATUS (CXD56_SCU_FIFO_REG_BASE + 0x2e8)
#define SCUFIFO_V7_W_C_TIMSTAMP0 (CXD56_SCU_FIFO_REG_BASE + 0x2ec)
#define SCUFIFO_V7_W_C_TIMSTAMP1 (CXD56_SCU_FIFO_REG_BASE + 0x2f0)
#define SCUFIFO_V7_W_C_TIMSTAMP_SET0 (CXD56_SCU_FIFO_REG_BASE + 0x2f4)
#define SCUFIFO_V7_W_C_TIMSTAMP_SET1 (CXD56_SCU_FIFO_REG_BASE + 0x2f8)
#define SCUFIFO_V8_W_C_CTRL0 (CXD56_SCU_FIFO_REG_BASE + 0x300)
#define SCUFIFO_V8_W_C_CTRL1 (CXD56_SCU_FIFO_REG_BASE + 0x304)
#define SCUFIFO_V8_W_C_STATUS (CXD56_SCU_FIFO_REG_BASE + 0x308)
#define SCUFIFO_V8_W_C_TIMSTAMP0 (CXD56_SCU_FIFO_REG_BASE + 0x30c)
#define SCUFIFO_V8_W_C_TIMSTAMP1 (CXD56_SCU_FIFO_REG_BASE + 0x310)
#define SCUFIFO_V8_W_C_TIMSTAMP_SET0 (CXD56_SCU_FIFO_REG_BASE + 0x314)
#define SCUFIFO_V8_W_C_TIMSTAMP_SET1 (CXD56_SCU_FIFO_REG_BASE + 0x318)
#define SCUFIFO_V9_W_C_CTRL0 (CXD56_SCU_FIFO_REG_BASE + 0x320)
#define SCUFIFO_V9_W_C_CTRL1 (CXD56_SCU_FIFO_REG_BASE + 0x324)
#define SCUFIFO_V9_W_C_STATUS (CXD56_SCU_FIFO_REG_BASE + 0x328)
#define SCUFIFO_V9_W_C_TIMSTAMP0 (CXD56_SCU_FIFO_REG_BASE + 0x32c)
#define SCUFIFO_V9_W_C_TIMSTAMP1 (CXD56_SCU_FIFO_REG_BASE + 0x330)
#define SCUFIFO_V9_W_C_TIMSTAMP_SET0 (CXD56_SCU_FIFO_REG_BASE + 0x334)
#define SCUFIFO_V9_W_C_TIMSTAMP_SET1 (CXD56_SCU_FIFO_REG_BASE + 0x338)
#define SCUFIFO_D0_R1_C_CTRL0 (CXD56_SCU_FIFO_REG_BASE + 0x1000)
#define SCUFIFO_D0_R1_C_CTRL1 (CXD56_SCU_FIFO_REG_BASE + 0x1004)
#define SCUFIFO_D0_R1_C_STATUS0 (CXD56_SCU_FIFO_REG_BASE + 0x1008)
#define SCUFIFO_D0_R1_C_STATUS1 (CXD56_SCU_FIFO_REG_BASE + 0x100c)
#define SCUFIFO_D0_R1_C_TIMSTAMP0 (CXD56_SCU_FIFO_REG_BASE + 0x1010)
#define SCUFIFO_D0_R1_C_TIMSTAMP1 (CXD56_SCU_FIFO_REG_BASE + 0x1014)
#define SCUFIFO_D0_R2_C_CTRL0 (CXD56_SCU_FIFO_REG_BASE + 0x1020)
#define SCUFIFO_D0_R2_C_CTRL1 (CXD56_SCU_FIFO_REG_BASE + 0x1024)
#define SCUFIFO_D0_R2_C_STATUS0 (CXD56_SCU_FIFO_REG_BASE + 0x1028)
#define SCUFIFO_D0_R2_C_STATUS1 (CXD56_SCU_FIFO_REG_BASE + 0x102c)
#define SCUFIFO_D0_R2_C_TIMSTAMP0 (CXD56_SCU_FIFO_REG_BASE + 0x1030)
#define SCUFIFO_D0_R2_C_TIMSTAMP1 (CXD56_SCU_FIFO_REG_BASE + 0x1034)
#define SCUFIFO_D1_R1_C_CTRL0 (CXD56_SCU_FIFO_REG_BASE + 0x1040)
#define SCUFIFO_D1_R1_C_CTRL1 (CXD56_SCU_FIFO_REG_BASE + 0x1044)
#define SCUFIFO_D1_R1_C_STATUS0 (CXD56_SCU_FIFO_REG_BASE + 0x1048)
#define SCUFIFO_D1_R1_C_STATUS1 (CXD56_SCU_FIFO_REG_BASE + 0x104c)
#define SCUFIFO_D1_R1_C_TIMSTAMP0 (CXD56_SCU_FIFO_REG_BASE + 0x1050)
#define SCUFIFO_D1_R1_C_TIMSTAMP1 (CXD56_SCU_FIFO_REG_BASE + 0x1054)
#define SCUFIFO_D1_R2_C_CTRL0 (CXD56_SCU_FIFO_REG_BASE + 0x1060)
#define SCUFIFO_D1_R2_C_CTRL1 (CXD56_SCU_FIFO_REG_BASE + 0x1064)
#define SCUFIFO_D1_R2_C_STATUS0 (CXD56_SCU_FIFO_REG_BASE + 0x1068)
#define SCUFIFO_D1_R2_C_STATUS1 (CXD56_SCU_FIFO_REG_BASE + 0x106c)
#define SCUFIFO_D1_R2_C_TIMSTAMP0 (CXD56_SCU_FIFO_REG_BASE + 0x1070)
#define SCUFIFO_D1_R2_C_TIMSTAMP1 (CXD56_SCU_FIFO_REG_BASE + 0x1074)
#define SCUFIFO_N0_R1_C_CTRL0 (CXD56_SCU_FIFO_REG_BASE + 0x1080)
#define SCUFIFO_N0_R1_C_CTRL1 (CXD56_SCU_FIFO_REG_BASE + 0x1084)
#define SCUFIFO_N0_R1_C_STATUS0 (CXD56_SCU_FIFO_REG_BASE + 0x1088)
#define SCUFIFO_N0_R1_C_STATUS1 (CXD56_SCU_FIFO_REG_BASE + 0x108c)
#define SCUFIFO_N0_R1_C_TIMSTAMP0 (CXD56_SCU_FIFO_REG_BASE + 0x1090)
#define SCUFIFO_N0_R1_C_TIMSTAMP1 (CXD56_SCU_FIFO_REG_BASE + 0x1094)
#define SCUFIFO_N1_R1_C_CTRL0 (CXD56_SCU_FIFO_REG_BASE + 0x10a0)
#define SCUFIFO_N1_R1_C_CTRL1 (CXD56_SCU_FIFO_REG_BASE + 0x10a4)
#define SCUFIFO_N1_R1_C_STATUS0 (CXD56_SCU_FIFO_REG_BASE + 0x10a8)
#define SCUFIFO_N1_R1_C_STATUS1 (CXD56_SCU_FIFO_REG_BASE + 0x10ac)
#define SCUFIFO_N1_R1_C_TIMSTAMP0 (CXD56_SCU_FIFO_REG_BASE + 0x10b0)
#define SCUFIFO_N1_R1_C_TIMSTAMP1 (CXD56_SCU_FIFO_REG_BASE + 0x10b4)
#define SCUFIFO_N2_R1_C_CTRL0 (CXD56_SCU_FIFO_REG_BASE + 0x10c0)
#define SCUFIFO_N2_R1_C_CTRL1 (CXD56_SCU_FIFO_REG_BASE + 0x10c4)
#define SCUFIFO_N2_R1_C_STATUS0 (CXD56_SCU_FIFO_REG_BASE + 0x10c8)
#define SCUFIFO_N2_R1_C_STATUS1 (CXD56_SCU_FIFO_REG_BASE + 0x10cc)
#define SCUFIFO_N2_R1_C_TIMSTAMP0 (CXD56_SCU_FIFO_REG_BASE + 0x10d0)
#define SCUFIFO_N2_R1_C_TIMSTAMP1 (CXD56_SCU_FIFO_REG_BASE + 0x10d4)
#define SCUFIFO_N3_R1_C_CTRL0 (CXD56_SCU_FIFO_REG_BASE + 0x10e0)
#define SCUFIFO_N3_R1_C_CTRL1 (CXD56_SCU_FIFO_REG_BASE + 0x10e4)
#define SCUFIFO_N3_R1_C_STATUS0 (CXD56_SCU_FIFO_REG_BASE + 0x10e8)
#define SCUFIFO_N3_R1_C_STATUS1 (CXD56_SCU_FIFO_REG_BASE + 0x10ec)
#define SCUFIFO_N3_R1_C_TIMSTAMP0 (CXD56_SCU_FIFO_REG_BASE + 0x10f0)
#define SCUFIFO_N3_R1_C_TIMSTAMP1 (CXD56_SCU_FIFO_REG_BASE + 0x10f4)
#define SCUFIFO_N4_R1_C_CTRL0 (CXD56_SCU_FIFO_REG_BASE + 0x1100)
#define SCUFIFO_N4_R1_C_CTRL1 (CXD56_SCU_FIFO_REG_BASE + 0x1104)
#define SCUFIFO_N4_R1_C_STATUS0 (CXD56_SCU_FIFO_REG_BASE + 0x1108)
#define SCUFIFO_N4_R1_C_STATUS1 (CXD56_SCU_FIFO_REG_BASE + 0x110c)
#define SCUFIFO_N4_R1_C_TIMSTAMP0 (CXD56_SCU_FIFO_REG_BASE + 0x1110)
#define SCUFIFO_N4_R1_C_TIMSTAMP1 (CXD56_SCU_FIFO_REG_BASE + 0x1114)
#define SCUFIFO_N5_R1_C_CTRL0 (CXD56_SCU_FIFO_REG_BASE + 0x1120)
#define SCUFIFO_N5_R1_C_CTRL1 (CXD56_SCU_FIFO_REG_BASE + 0x1124)
#define SCUFIFO_N5_R1_C_STATUS0 (CXD56_SCU_FIFO_REG_BASE + 0x1128)
#define SCUFIFO_N5_R1_C_STATUS1 (CXD56_SCU_FIFO_REG_BASE + 0x112c)
#define SCUFIFO_N5_R1_C_TIMSTAMP0 (CXD56_SCU_FIFO_REG_BASE + 0x1130)
#define SCUFIFO_N5_R1_C_TIMSTAMP1 (CXD56_SCU_FIFO_REG_BASE + 0x1134)
#define SCUFIFO_N6_R1_C_CTRL0 (CXD56_SCU_FIFO_REG_BASE + 0x1140)
#define SCUFIFO_N6_R1_C_CTRL1 (CXD56_SCU_FIFO_REG_BASE + 0x1144)
#define SCUFIFO_N6_R1_C_STATUS0 (CXD56_SCU_FIFO_REG_BASE + 0x1148)
#define SCUFIFO_N6_R1_C_STATUS1 (CXD56_SCU_FIFO_REG_BASE + 0x114c)
#define SCUFIFO_N6_R1_C_TIMSTAMP0 (CXD56_SCU_FIFO_REG_BASE + 0x1150)
#define SCUFIFO_N6_R1_C_TIMSTAMP1 (CXD56_SCU_FIFO_REG_BASE + 0x1154)
#define SCUFIFO_N7_R1_C_CTRL0 (CXD56_SCU_FIFO_REG_BASE + 0x1160)
#define SCUFIFO_N7_R1_C_CTRL1 (CXD56_SCU_FIFO_REG_BASE + 0x1164)
#define SCUFIFO_N7_R1_C_STATUS0 (CXD56_SCU_FIFO_REG_BASE + 0x1168)
#define SCUFIFO_N7_R1_C_STATUS1 (CXD56_SCU_FIFO_REG_BASE + 0x116c)
#define SCUFIFO_N7_R1_C_TIMSTAMP0 (CXD56_SCU_FIFO_REG_BASE + 0x1170)
#define SCUFIFO_N7_R1_C_TIMSTAMP1 (CXD56_SCU_FIFO_REG_BASE + 0x1174)
#define SCUFIFO_D0_R3_CH_CTRL0 (CXD56_SCU_FIFO_REG_BASE + 0x1180)
#define SCUFIFO_D0_R3_CH_CTRL1 (CXD56_SCU_FIFO_REG_BASE + 0x1184)
#define SCUFIFO_D0_R3_CH_STATUS0 (CXD56_SCU_FIFO_REG_BASE + 0x1188)
#define SCUFIFO_D0_R3_CH_STATUS1 (CXD56_SCU_FIFO_REG_BASE + 0x118c)
#define SCUFIFO_D0_R3_CH_TIMSTAMP0 (CXD56_SCU_FIFO_REG_BASE + 0x1190)
#define SCUFIFO_D0_R3_CH_TIMSTAMP1 (CXD56_SCU_FIFO_REG_BASE + 0x1194)
#define SCUFIFO_D1_R3_CH_CTRL0 (CXD56_SCU_FIFO_REG_BASE + 0x11a0)
#define SCUFIFO_D1_R3_CH_CTRL1 (CXD56_SCU_FIFO_REG_BASE + 0x11a4)
#define SCUFIFO_D1_R3_CH_STATUS0 (CXD56_SCU_FIFO_REG_BASE + 0x11a8)
#define SCUFIFO_D1_R3_CH_STATUS1 (CXD56_SCU_FIFO_REG_BASE + 0x11ac)
#define SCUFIFO_D1_R3_CH_TIMSTAMP0 (CXD56_SCU_FIFO_REG_BASE + 0x11b0)
#define SCUFIFO_D1_R3_CH_TIMSTAMP1 (CXD56_SCU_FIFO_REG_BASE + 0x11b4)
#define SCUFIFO_D0_R0_H_CTRL0 (CXD56_SCU_FIFO_REG_BASE + 0x11c0)
#define SCUFIFO_D0_R0_H_CTRL1 (CXD56_SCU_FIFO_REG_BASE + 0x11c4)
#define SCUFIFO_D0_R0_H_STATUS0 (CXD56_SCU_FIFO_REG_BASE + 0x11c8)
#define SCUFIFO_D0_R0_H_STATUS1 (CXD56_SCU_FIFO_REG_BASE + 0x11cc)
#define SCUFIFO_D0_R0_H_TIMSTAMP0 (CXD56_SCU_FIFO_REG_BASE + 0x11d0)
#define SCUFIFO_D0_R0_H_TIMSTAMP1 (CXD56_SCU_FIFO_REG_BASE + 0x11d4)
#define SCUFIFO_D1_R0_H_CTRL0 (CXD56_SCU_FIFO_REG_BASE + 0x11e0)
#define SCUFIFO_D1_R0_H_CTRL1 (CXD56_SCU_FIFO_REG_BASE + 0x11e4)
#define SCUFIFO_D1_R0_H_STATUS0 (CXD56_SCU_FIFO_REG_BASE + 0x11e8)
#define SCUFIFO_D1_R0_H_STATUS1 (CXD56_SCU_FIFO_REG_BASE + 0x11ec)
#define SCUFIFO_D1_R0_H_TIMSTAMP0 (CXD56_SCU_FIFO_REG_BASE + 0x11f0)
#define SCUFIFO_D1_R0_H_TIMSTAMP1 (CXD56_SCU_FIFO_REG_BASE + 0x11f4)
#define SCUFIFO_N0_R0_H_CTRL0 (CXD56_SCU_FIFO_REG_BASE + 0x1200)
#define SCUFIFO_N0_R0_H_CTRL1 (CXD56_SCU_FIFO_REG_BASE + 0x1204)
#define SCUFIFO_N0_R0_H_STATUS0 (CXD56_SCU_FIFO_REG_BASE + 0x1208)
#define SCUFIFO_N0_R0_H_STATUS1 (CXD56_SCU_FIFO_REG_BASE + 0x120c)
#define SCUFIFO_N0_R0_H_TIMSTAMP0 (CXD56_SCU_FIFO_REG_BASE + 0x1210)
#define SCUFIFO_N0_R0_H_TIMSTAMP1 (CXD56_SCU_FIFO_REG_BASE + 0x1214)
#define SCUFIFO_N1_R0_H_CTRL0 (CXD56_SCU_FIFO_REG_BASE + 0x1220)
#define SCUFIFO_N1_R0_H_CTRL1 (CXD56_SCU_FIFO_REG_BASE + 0x1224)
#define SCUFIFO_N1_R0_H_STATUS0 (CXD56_SCU_FIFO_REG_BASE + 0x1228)
#define SCUFIFO_N1_R0_H_STATUS1 (CXD56_SCU_FIFO_REG_BASE + 0x122c)
#define SCUFIFO_N1_R0_H_TIMSTAMP0 (CXD56_SCU_FIFO_REG_BASE + 0x1230)
#define SCUFIFO_N1_R0_H_TIMSTAMP1 (CXD56_SCU_FIFO_REG_BASE + 0x1234)
#define SCUFIFO_N2_R0_H_CTRL0 (CXD56_SCU_FIFO_REG_BASE + 0x1240)
#define SCUFIFO_N2_R0_H_CTRL1 (CXD56_SCU_FIFO_REG_BASE + 0x1244)
#define SCUFIFO_N2_R0_H_STATUS0 (CXD56_SCU_FIFO_REG_BASE + 0x1248)
#define SCUFIFO_N2_R0_H_STATUS1 (CXD56_SCU_FIFO_REG_BASE + 0x124c)
#define SCUFIFO_N2_R0_H_TIMSTAMP0 (CXD56_SCU_FIFO_REG_BASE + 0x1250)
#define SCUFIFO_N2_R0_H_TIMSTAMP1 (CXD56_SCU_FIFO_REG_BASE + 0x1254)
#define SCUFIFO_N3_R0_H_CTRL0 (CXD56_SCU_FIFO_REG_BASE + 0x1260)
#define SCUFIFO_N3_R0_H_CTRL1 (CXD56_SCU_FIFO_REG_BASE + 0x1264)
#define SCUFIFO_N3_R0_H_STATUS0 (CXD56_SCU_FIFO_REG_BASE + 0x1268)
#define SCUFIFO_N3_R0_H_STATUS1 (CXD56_SCU_FIFO_REG_BASE + 0x126c)
#define SCUFIFO_N3_R0_H_TIMSTAMP0 (CXD56_SCU_FIFO_REG_BASE + 0x1270)
#define SCUFIFO_N3_R0_H_TIMSTAMP1 (CXD56_SCU_FIFO_REG_BASE + 0x1274)
#define SCUFIFO_N4_R0_H_CTRL0 (CXD56_SCU_FIFO_REG_BASE + 0x1280)
#define SCUFIFO_N4_R0_H_CTRL1 (CXD56_SCU_FIFO_REG_BASE + 0x1284)
#define SCUFIFO_N4_R0_H_STATUS0 (CXD56_SCU_FIFO_REG_BASE + 0x1288)
#define SCUFIFO_N4_R0_H_STATUS1 (CXD56_SCU_FIFO_REG_BASE + 0x128c)
#define SCUFIFO_N4_R0_H_TIMSTAMP0 (CXD56_SCU_FIFO_REG_BASE + 0x1290)
#define SCUFIFO_N4_R0_H_TIMSTAMP1 (CXD56_SCU_FIFO_REG_BASE + 0x1294)
#define SCUFIFO_N5_R0_H_CTRL0 (CXD56_SCU_FIFO_REG_BASE + 0x12a0)
#define SCUFIFO_N5_R0_H_CTRL1 (CXD56_SCU_FIFO_REG_BASE + 0x12a4)
#define SCUFIFO_N5_R0_H_STATUS0 (CXD56_SCU_FIFO_REG_BASE + 0x12a8)
#define SCUFIFO_N5_R0_H_STATUS1 (CXD56_SCU_FIFO_REG_BASE + 0x12ac)
#define SCUFIFO_N5_R0_H_TIMSTAMP0 (CXD56_SCU_FIFO_REG_BASE + 0x12b0)
#define SCUFIFO_N5_R0_H_TIMSTAMP1 (CXD56_SCU_FIFO_REG_BASE + 0x12b4)
#define SCUFIFO_N6_R0_H_CTRL0 (CXD56_SCU_FIFO_REG_BASE + 0x12c0)
#define SCUFIFO_N6_R0_H_CTRL1 (CXD56_SCU_FIFO_REG_BASE + 0x12c4)
#define SCUFIFO_N6_R0_H_STATUS0 (CXD56_SCU_FIFO_REG_BASE + 0x12c8)
#define SCUFIFO_N6_R0_H_STATUS1 (CXD56_SCU_FIFO_REG_BASE + 0x12cc)
#define SCUFIFO_N6_R0_H_TIMSTAMP0 (CXD56_SCU_FIFO_REG_BASE + 0x12d0)
#define SCUFIFO_N6_R0_H_TIMSTAMP1 (CXD56_SCU_FIFO_REG_BASE + 0x12d4)
#define SCUFIFO_N7_R0_H_CTRL0 (CXD56_SCU_FIFO_REG_BASE + 0x12e0)
#define SCUFIFO_N7_R0_H_CTRL1 (CXD56_SCU_FIFO_REG_BASE + 0x12e4)
#define SCUFIFO_N7_R0_H_STATUS0 (CXD56_SCU_FIFO_REG_BASE + 0x12e8)
#define SCUFIFO_N7_R0_H_STATUS1 (CXD56_SCU_FIFO_REG_BASE + 0x12ec)
#define SCUFIFO_N7_R0_H_TIMSTAMP0 (CXD56_SCU_FIFO_REG_BASE + 0x12f0)
#define SCUFIFO_N7_R0_H_TIMSTAMP1 (CXD56_SCU_FIFO_REG_BASE + 0x12f4)
#define SCUFIFO_V0_R_H_CTRL0 (CXD56_SCU_FIFO_REG_BASE + 0x1300)
#define SCUFIFO_V0_R_H_CTRL1 (CXD56_SCU_FIFO_REG_BASE + 0x1304)
#define SCUFIFO_V0_R_H_STATUS0 (CXD56_SCU_FIFO_REG_BASE + 0x1308)
#define SCUFIFO_V0_R_H_STATUS1 (CXD56_SCU_FIFO_REG_BASE + 0x130c)
#define SCUFIFO_V0_R_H_TIMSTAMP0 (CXD56_SCU_FIFO_REG_BASE + 0x1310)
#define SCUFIFO_V0_R_H_TIMSTAMP1 (CXD56_SCU_FIFO_REG_BASE + 0x1314)
#define SCUFIFO_V1_R_H_CTRL0 (CXD56_SCU_FIFO_REG_BASE + 0x1320)
#define SCUFIFO_V1_R_H_CTRL1 (CXD56_SCU_FIFO_REG_BASE + 0x1324)
#define SCUFIFO_V1_R_H_STATUS0 (CXD56_SCU_FIFO_REG_BASE + 0x1328)
#define SCUFIFO_V1_R_H_STATUS1 (CXD56_SCU_FIFO_REG_BASE + 0x132c)
#define SCUFIFO_V1_R_H_TIMSTAMP0 (CXD56_SCU_FIFO_REG_BASE + 0x1330)
#define SCUFIFO_V1_R_H_TIMSTAMP1 (CXD56_SCU_FIFO_REG_BASE + 0x1334)
#define SCUFIFO_V2_R_H_CTRL0 (CXD56_SCU_FIFO_REG_BASE + 0x1340)
#define SCUFIFO_V2_R_H_CTRL1 (CXD56_SCU_FIFO_REG_BASE + 0x1344)
#define SCUFIFO_V2_R_H_STATUS0 (CXD56_SCU_FIFO_REG_BASE + 0x1348)
#define SCUFIFO_V2_R_H_STATUS1 (CXD56_SCU_FIFO_REG_BASE + 0x134c)
#define SCUFIFO_V2_R_H_TIMSTAMP0 (CXD56_SCU_FIFO_REG_BASE + 0x1350)
#define SCUFIFO_V2_R_H_TIMSTAMP1 (CXD56_SCU_FIFO_REG_BASE + 0x1354)
#define SCUFIFO_V3_R_H_CTRL0 (CXD56_SCU_FIFO_REG_BASE + 0x1360)
#define SCUFIFO_V3_R_H_CTRL1 (CXD56_SCU_FIFO_REG_BASE + 0x1364)
#define SCUFIFO_V3_R_H_STATUS0 (CXD56_SCU_FIFO_REG_BASE + 0x1368)
#define SCUFIFO_V3_R_H_STATUS1 (CXD56_SCU_FIFO_REG_BASE + 0x136c)
#define SCUFIFO_V3_R_H_TIMSTAMP0 (CXD56_SCU_FIFO_REG_BASE + 0x1370)
#define SCUFIFO_V3_R_H_TIMSTAMP1 (CXD56_SCU_FIFO_REG_BASE + 0x1374)
#define SCUFIFO_V4_R_H_CTRL0 (CXD56_SCU_FIFO_REG_BASE + 0x1380)
#define SCUFIFO_V4_R_H_CTRL1 (CXD56_SCU_FIFO_REG_BASE + 0x1384)
#define SCUFIFO_V4_R_H_STATUS0 (CXD56_SCU_FIFO_REG_BASE + 0x1388)
#define SCUFIFO_V4_R_H_STATUS1 (CXD56_SCU_FIFO_REG_BASE + 0x138c)
#define SCUFIFO_V4_R_H_TIMSTAMP0 (CXD56_SCU_FIFO_REG_BASE + 0x1390)
#define SCUFIFO_V4_R_H_TIMSTAMP1 (CXD56_SCU_FIFO_REG_BASE + 0x1394)
#define SCUFIFO_V5_R_H_CTRL0 (CXD56_SCU_FIFO_REG_BASE + 0x13a0)
#define SCUFIFO_V5_R_H_CTRL1 (CXD56_SCU_FIFO_REG_BASE + 0x13a4)
#define SCUFIFO_V5_R_H_STATUS0 (CXD56_SCU_FIFO_REG_BASE + 0x13a8)
#define SCUFIFO_V5_R_H_STATUS1 (CXD56_SCU_FIFO_REG_BASE + 0x13ac)
#define SCUFIFO_V5_R_H_TIMSTAMP0 (CXD56_SCU_FIFO_REG_BASE + 0x13b0)
#define SCUFIFO_V5_R_H_TIMSTAMP1 (CXD56_SCU_FIFO_REG_BASE + 0x13b4)
#define SCUFIFO_V6_R_H_CTRL0 (CXD56_SCU_FIFO_REG_BASE + 0x13c0)
#define SCUFIFO_V6_R_H_CTRL1 (CXD56_SCU_FIFO_REG_BASE + 0x13c4)
#define SCUFIFO_V6_R_H_STATUS0 (CXD56_SCU_FIFO_REG_BASE + 0x13c8)
#define SCUFIFO_V6_R_H_STATUS1 (CXD56_SCU_FIFO_REG_BASE + 0x13cc)
#define SCUFIFO_V6_R_H_TIMSTAMP0 (CXD56_SCU_FIFO_REG_BASE + 0x13d0)
#define SCUFIFO_V6_R_H_TIMSTAMP1 (CXD56_SCU_FIFO_REG_BASE + 0x13d4)
#define SCUFIFO_V7_R_H_CTRL0 (CXD56_SCU_FIFO_REG_BASE + 0x13e0)
#define SCUFIFO_V7_R_H_CTRL1 (CXD56_SCU_FIFO_REG_BASE + 0x13e4)
#define SCUFIFO_V7_R_H_STATUS0 (CXD56_SCU_FIFO_REG_BASE + 0x13e8)
#define SCUFIFO_V7_R_H_STATUS1 (CXD56_SCU_FIFO_REG_BASE + 0x13ec)
#define SCUFIFO_V7_R_H_TIMSTAMP0 (CXD56_SCU_FIFO_REG_BASE + 0x13f0)
#define SCUFIFO_V7_R_H_TIMSTAMP1 (CXD56_SCU_FIFO_REG_BASE + 0x13f4)
#define SCUFIFO_V8_R_H_CTRL0 (CXD56_SCU_FIFO_REG_BASE + 0x1400)
#define SCUFIFO_V8_R_H_CTRL1 (CXD56_SCU_FIFO_REG_BASE + 0x1404)
#define SCUFIFO_V8_R_H_STATUS0 (CXD56_SCU_FIFO_REG_BASE + 0x1408)
#define SCUFIFO_V8_R_H_STATUS1 (CXD56_SCU_FIFO_REG_BASE + 0x140c)
#define SCUFIFO_V8_R_H_TIMSTAMP0 (CXD56_SCU_FIFO_REG_BASE + 0x1410)
#define SCUFIFO_V8_R_H_TIMSTAMP1 (CXD56_SCU_FIFO_REG_BASE + 0x1414)
#define SCUFIFO_V9_R_H_CTRL0 (CXD56_SCU_FIFO_REG_BASE + 0x1420)
#define SCUFIFO_V9_R_H_CTRL1 (CXD56_SCU_FIFO_REG_BASE + 0x1424)
#define SCUFIFO_V9_R_H_STATUS0 (CXD56_SCU_FIFO_REG_BASE + 0x1428)
#define SCUFIFO_V9_R_H_STATUS1 (CXD56_SCU_FIFO_REG_BASE + 0x142c)
#define SCUFIFO_V9_R_H_TIMSTAMP0 (CXD56_SCU_FIFO_REG_BASE + 0x1430)
#define SCUFIFO_V9_R_H_TIMSTAMP1 (CXD56_SCU_FIFO_REG_BASE + 0x1434)
#define SCUFIFO_DECI_PARTITION_SEL (CXD56_SCU_FIFO_REG_BASE + 0x1c00)
#define SCUFIFO_D0_W0_S_CTRL0 (CXD56_SCU_FIFO_REG_BASE + 0x0)
#define SCUFIFO_D0_W0_S_CTRL1 (CXD56_SCU_FIFO_REG_BASE + 0x4)
#define SCUFIFO_D0_W0_S_STATUS (CXD56_SCU_FIFO_REG_BASE + 0x8)
#define SCUFIFO_D0_W0_S_TIMSTAMP0 (CXD56_SCU_FIFO_REG_BASE + 0xc)
#define SCUFIFO_D0_W0_S_TIMSTAMP1 (CXD56_SCU_FIFO_REG_BASE + 0x10)
#define SCUFIFO_D0_W1_S_CTRL0 (CXD56_SCU_FIFO_REG_BASE + 0x20)
#define SCUFIFO_D0_W1_S_CTRL1 (CXD56_SCU_FIFO_REG_BASE + 0x24)
#define SCUFIFO_D0_W1_S_STATUS (CXD56_SCU_FIFO_REG_BASE + 0x28)
#define SCUFIFO_D0_W1_S_TIMSTAMP0 (CXD56_SCU_FIFO_REG_BASE + 0x2c)
#define SCUFIFO_D0_W1_S_TIMSTAMP1 (CXD56_SCU_FIFO_REG_BASE + 0x30)
#define SCUFIFO_D0_W2_S_CTRL0 (CXD56_SCU_FIFO_REG_BASE + 0x40)
#define SCUFIFO_D0_W2_S_CTRL1 (CXD56_SCU_FIFO_REG_BASE + 0x44)
#define SCUFIFO_D0_W2_S_STATUS (CXD56_SCU_FIFO_REG_BASE + 0x48)
#define SCUFIFO_D0_W2_S_TIMSTAMP0 (CXD56_SCU_FIFO_REG_BASE + 0x4c)
#define SCUFIFO_D0_W2_S_TIMSTAMP1 (CXD56_SCU_FIFO_REG_BASE + 0x50)
#define SCUFIFO_D0_W3_S_CTRL0 (CXD56_SCU_FIFO_REG_BASE + 0x60)
#define SCUFIFO_D0_W3_S_CTRL1 (CXD56_SCU_FIFO_REG_BASE + 0x64)
#define SCUFIFO_D0_W3_S_STATUS (CXD56_SCU_FIFO_REG_BASE + 0x68)
#define SCUFIFO_D0_W3_S_TIMSTAMP0 (CXD56_SCU_FIFO_REG_BASE + 0x6c)
#define SCUFIFO_D0_W3_S_TIMSTAMP1 (CXD56_SCU_FIFO_REG_BASE + 0x70)
#define SCUFIFO_D1_W0_S_CTRL0 (CXD56_SCU_FIFO_REG_BASE + 0x80)
#define SCUFIFO_D1_W0_S_CTRL1 (CXD56_SCU_FIFO_REG_BASE + 0x84)
#define SCUFIFO_D1_W0_S_STATUS (CXD56_SCU_FIFO_REG_BASE + 0x88)
#define SCUFIFO_D1_W0_S_TIMSTAMP0 (CXD56_SCU_FIFO_REG_BASE + 0x8c)
#define SCUFIFO_D1_W0_S_TIMSTAMP1 (CXD56_SCU_FIFO_REG_BASE + 0x90)
#define SCUFIFO_D1_W1_S_CTRL0 (CXD56_SCU_FIFO_REG_BASE + 0xa0)
#define SCUFIFO_D1_W1_S_CTRL1 (CXD56_SCU_FIFO_REG_BASE + 0xa4)
#define SCUFIFO_D1_W1_S_STATUS (CXD56_SCU_FIFO_REG_BASE + 0xa8)
#define SCUFIFO_D1_W1_S_TIMSTAMP0 (CXD56_SCU_FIFO_REG_BASE + 0xac)
#define SCUFIFO_D1_W1_S_TIMSTAMP1 (CXD56_SCU_FIFO_REG_BASE + 0xb0)
#define SCUFIFO_D1_W2_S_CTRL0 (CXD56_SCU_FIFO_REG_BASE + 0xc0)
#define SCUFIFO_D1_W2_S_CTRL1 (CXD56_SCU_FIFO_REG_BASE + 0xc4)
#define SCUFIFO_D1_W2_S_STATUS (CXD56_SCU_FIFO_REG_BASE + 0xc8)
#define SCUFIFO_D1_W2_S_TIMSTAMP0 (CXD56_SCU_FIFO_REG_BASE + 0xcc)
#define SCUFIFO_D1_W2_S_TIMSTAMP1 (CXD56_SCU_FIFO_REG_BASE + 0xd0)
#define SCUFIFO_D1_W3_S_CTRL0 (CXD56_SCU_FIFO_REG_BASE + 0xe0)
#define SCUFIFO_D1_W3_S_CTRL1 (CXD56_SCU_FIFO_REG_BASE + 0xe4)
#define SCUFIFO_D1_W3_S_STATUS (CXD56_SCU_FIFO_REG_BASE + 0xe8)
#define SCUFIFO_D1_W3_S_TIMSTAMP0 (CXD56_SCU_FIFO_REG_BASE + 0xec)
#define SCUFIFO_D1_W3_S_TIMSTAMP1 (CXD56_SCU_FIFO_REG_BASE + 0xf0)
#define SCUFIFO_N0_W_S_CTRL0 (CXD56_SCU_FIFO_REG_BASE + 0x100)
#define SCUFIFO_N0_W_S_CTRL1 (CXD56_SCU_FIFO_REG_BASE + 0x104)
#define SCUFIFO_N0_W_S_STATUS (CXD56_SCU_FIFO_REG_BASE + 0x108)
#define SCUFIFO_N0_W_S_TIMSTAMP0 (CXD56_SCU_FIFO_REG_BASE + 0x10c)
#define SCUFIFO_N0_W_S_TIMSTAMP1 (CXD56_SCU_FIFO_REG_BASE + 0x110)
#define SCUFIFO_N1_W_S_CTRL0 (CXD56_SCU_FIFO_REG_BASE + 0x120)
#define SCUFIFO_N1_W_S_CTRL1 (CXD56_SCU_FIFO_REG_BASE + 0x124)
#define SCUFIFO_N1_W_S_STATUS (CXD56_SCU_FIFO_REG_BASE + 0x128)
#define SCUFIFO_N1_W_S_TIMSTAMP0 (CXD56_SCU_FIFO_REG_BASE + 0x12c)
#define SCUFIFO_N1_W_S_TIMSTAMP1 (CXD56_SCU_FIFO_REG_BASE + 0x130)
#define SCUFIFO_N2_W_S_CTRL0 (CXD56_SCU_FIFO_REG_BASE + 0x140)
#define SCUFIFO_N2_W_S_CTRL1 (CXD56_SCU_FIFO_REG_BASE + 0x144)
#define SCUFIFO_N2_W_S_STATUS (CXD56_SCU_FIFO_REG_BASE + 0x148)
#define SCUFIFO_N2_W_S_TIMSTAMP0 (CXD56_SCU_FIFO_REG_BASE + 0x14c)
#define SCUFIFO_N2_W_S_TIMSTAMP1 (CXD56_SCU_FIFO_REG_BASE + 0x150)
#define SCUFIFO_N3_W_S_CTRL0 (CXD56_SCU_FIFO_REG_BASE + 0x160)
#define SCUFIFO_N3_W_S_CTRL1 (CXD56_SCU_FIFO_REG_BASE + 0x164)
#define SCUFIFO_N3_W_S_STATUS (CXD56_SCU_FIFO_REG_BASE + 0x168)
#define SCUFIFO_N3_W_S_TIMSTAMP0 (CXD56_SCU_FIFO_REG_BASE + 0x16c)
#define SCUFIFO_N3_W_S_TIMSTAMP1 (CXD56_SCU_FIFO_REG_BASE + 0x170)
#define SCUFIFO_N4_W_S_CTRL0 (CXD56_SCU_FIFO_REG_BASE + 0x180)
#define SCUFIFO_N4_W_S_CTRL1 (CXD56_SCU_FIFO_REG_BASE + 0x184)
#define SCUFIFO_N4_W_S_STATUS (CXD56_SCU_FIFO_REG_BASE + 0x188)
#define SCUFIFO_N4_W_S_TIMSTAMP0 (CXD56_SCU_FIFO_REG_BASE + 0x18c)
#define SCUFIFO_N4_W_S_TIMSTAMP1 (CXD56_SCU_FIFO_REG_BASE + 0x190)
#define SCUFIFO_N5_W_S_CTRL0 (CXD56_SCU_FIFO_REG_BASE + 0x1a0)
#define SCUFIFO_N5_W_S_CTRL1 (CXD56_SCU_FIFO_REG_BASE + 0x1a4)
#define SCUFIFO_N5_W_S_STATUS (CXD56_SCU_FIFO_REG_BASE + 0x1a8)
#define SCUFIFO_N5_W_S_TIMSTAMP0 (CXD56_SCU_FIFO_REG_BASE + 0x1ac)
#define SCUFIFO_N5_W_S_TIMSTAMP1 (CXD56_SCU_FIFO_REG_BASE + 0x1b0)
#define SCUFIFO_N6_W_S_CTRL0 (CXD56_SCU_FIFO_REG_BASE + 0x1c0)
#define SCUFIFO_N6_W_S_CTRL1 (CXD56_SCU_FIFO_REG_BASE + 0x1c4)
#define SCUFIFO_N6_W_S_STATUS (CXD56_SCU_FIFO_REG_BASE + 0x1c8)
#define SCUFIFO_N6_W_S_TIMSTAMP0 (CXD56_SCU_FIFO_REG_BASE + 0x1cc)
#define SCUFIFO_N6_W_S_TIMSTAMP1 (CXD56_SCU_FIFO_REG_BASE + 0x1d0)
#define SCUFIFO_N7_W_S_CTRL0 (CXD56_SCU_FIFO_REG_BASE + 0x1e0)
#define SCUFIFO_N7_W_S_CTRL1 (CXD56_SCU_FIFO_REG_BASE + 0x1e4)
#define SCUFIFO_N7_W_S_STATUS (CXD56_SCU_FIFO_REG_BASE + 0x1e8)
#define SCUFIFO_N7_W_S_TIMSTAMP0 (CXD56_SCU_FIFO_REG_BASE + 0x1ec)
#define SCUFIFO_N7_W_S_TIMSTAMP1 (CXD56_SCU_FIFO_REG_BASE + 0x1f0)
#define SCUFIFO_V0_W_C_CTRL0 (CXD56_SCU_FIFO_REG_BASE + 0x200)
#define SCUFIFO_V0_W_C_CTRL1 (CXD56_SCU_FIFO_REG_BASE + 0x204)
#define SCUFIFO_V0_W_C_STATUS (CXD56_SCU_FIFO_REG_BASE + 0x208)
#define SCUFIFO_V0_W_C_TIMSTAMP0 (CXD56_SCU_FIFO_REG_BASE + 0x20c)
#define SCUFIFO_V0_W_C_TIMSTAMP1 (CXD56_SCU_FIFO_REG_BASE + 0x210)
#define SCUFIFO_V0_W_C_TIMSTAMP_SET0 (CXD56_SCU_FIFO_REG_BASE + 0x214)
#define SCUFIFO_V0_W_C_TIMSTAMP_SET1 (CXD56_SCU_FIFO_REG_BASE + 0x218)
#define SCUFIFO_V1_W_C_CTRL0 (CXD56_SCU_FIFO_REG_BASE + 0x220)
#define SCUFIFO_V1_W_C_CTRL1 (CXD56_SCU_FIFO_REG_BASE + 0x224)
#define SCUFIFO_V1_W_C_STATUS (CXD56_SCU_FIFO_REG_BASE + 0x228)
#define SCUFIFO_V1_W_C_TIMSTAMP0 (CXD56_SCU_FIFO_REG_BASE + 0x22c)
#define SCUFIFO_V1_W_C_TIMSTAMP1 (CXD56_SCU_FIFO_REG_BASE + 0x230)
#define SCUFIFO_V1_W_C_TIMSTAMP_SET0 (CXD56_SCU_FIFO_REG_BASE + 0x234)
#define SCUFIFO_V1_W_C_TIMSTAMP_SET1 (CXD56_SCU_FIFO_REG_BASE + 0x238)
#define SCUFIFO_V2_W_C_CTRL0 (CXD56_SCU_FIFO_REG_BASE + 0x240)
#define SCUFIFO_V2_W_C_CTRL1 (CXD56_SCU_FIFO_REG_BASE + 0x244)
#define SCUFIFO_V2_W_C_STATUS (CXD56_SCU_FIFO_REG_BASE + 0x248)
#define SCUFIFO_V2_W_C_TIMSTAMP0 (CXD56_SCU_FIFO_REG_BASE + 0x24c)
#define SCUFIFO_V2_W_C_TIMSTAMP1 (CXD56_SCU_FIFO_REG_BASE + 0x250)
#define SCUFIFO_V2_W_C_TIMSTAMP_SET0 (CXD56_SCU_FIFO_REG_BASE + 0x254)
#define SCUFIFO_V2_W_C_TIMSTAMP_SET1 (CXD56_SCU_FIFO_REG_BASE + 0x258)
#define SCUFIFO_V3_W_C_CTRL0 (CXD56_SCU_FIFO_REG_BASE + 0x260)
#define SCUFIFO_V3_W_C_CTRL1 (CXD56_SCU_FIFO_REG_BASE + 0x264)
#define SCUFIFO_V3_W_C_STATUS (CXD56_SCU_FIFO_REG_BASE + 0x268)
#define SCUFIFO_V3_W_C_TIMSTAMP0 (CXD56_SCU_FIFO_REG_BASE + 0x26c)
#define SCUFIFO_V3_W_C_TIMSTAMP1 (CXD56_SCU_FIFO_REG_BASE + 0x270)
#define SCUFIFO_V3_W_C_TIMSTAMP_SET0 (CXD56_SCU_FIFO_REG_BASE + 0x274)
#define SCUFIFO_V3_W_C_TIMSTAMP_SET1 (CXD56_SCU_FIFO_REG_BASE + 0x278)
#define SCUFIFO_V4_W_C_CTRL0 (CXD56_SCU_FIFO_REG_BASE + 0x280)
#define SCUFIFO_V4_W_C_CTRL1 (CXD56_SCU_FIFO_REG_BASE + 0x284)
#define SCUFIFO_V4_W_C_STATUS (CXD56_SCU_FIFO_REG_BASE + 0x288)
#define SCUFIFO_V4_W_C_TIMSTAMP0 (CXD56_SCU_FIFO_REG_BASE + 0x28c)
#define SCUFIFO_V4_W_C_TIMSTAMP1 (CXD56_SCU_FIFO_REG_BASE + 0x290)
#define SCUFIFO_V4_W_C_TIMSTAMP_SET0 (CXD56_SCU_FIFO_REG_BASE + 0x294)
#define SCUFIFO_V4_W_C_TIMSTAMP_SET1 (CXD56_SCU_FIFO_REG_BASE + 0x298)
#define SCUFIFO_V5_W_C_CTRL0 (CXD56_SCU_FIFO_REG_BASE + 0x2a0)
#define SCUFIFO_V5_W_C_CTRL1 (CXD56_SCU_FIFO_REG_BASE + 0x2a4)
#define SCUFIFO_V5_W_C_STATUS (CXD56_SCU_FIFO_REG_BASE + 0x2a8)
#define SCUFIFO_V5_W_C_TIMSTAMP0 (CXD56_SCU_FIFO_REG_BASE + 0x2ac)
#define SCUFIFO_V5_W_C_TIMSTAMP1 (CXD56_SCU_FIFO_REG_BASE + 0x2b0)
#define SCUFIFO_V5_W_C_TIMSTAMP_SET0 (CXD56_SCU_FIFO_REG_BASE + 0x2b4)
#define SCUFIFO_V5_W_C_TIMSTAMP_SET1 (CXD56_SCU_FIFO_REG_BASE + 0x2b8)
#define SCUFIFO_V6_W_C_CTRL0 (CXD56_SCU_FIFO_REG_BASE + 0x2c0)
#define SCUFIFO_V6_W_C_CTRL1 (CXD56_SCU_FIFO_REG_BASE + 0x2c4)
#define SCUFIFO_V6_W_C_STATUS (CXD56_SCU_FIFO_REG_BASE + 0x2c8)
#define SCUFIFO_V6_W_C_TIMSTAMP0 (CXD56_SCU_FIFO_REG_BASE + 0x2cc)
#define SCUFIFO_V6_W_C_TIMSTAMP1 (CXD56_SCU_FIFO_REG_BASE + 0x2d0)
#define SCUFIFO_V6_W_C_TIMSTAMP_SET0 (CXD56_SCU_FIFO_REG_BASE + 0x2d4)
#define SCUFIFO_V6_W_C_TIMSTAMP_SET1 (CXD56_SCU_FIFO_REG_BASE + 0x2d8)
#define SCUFIFO_V7_W_C_CTRL0 (CXD56_SCU_FIFO_REG_BASE + 0x2e0)
#define SCUFIFO_V7_W_C_CTRL1 (CXD56_SCU_FIFO_REG_BASE + 0x2e4)
#define SCUFIFO_V7_W_C_STATUS (CXD56_SCU_FIFO_REG_BASE + 0x2e8)
#define SCUFIFO_V7_W_C_TIMSTAMP0 (CXD56_SCU_FIFO_REG_BASE + 0x2ec)
#define SCUFIFO_V7_W_C_TIMSTAMP1 (CXD56_SCU_FIFO_REG_BASE + 0x2f0)
#define SCUFIFO_V7_W_C_TIMSTAMP_SET0 (CXD56_SCU_FIFO_REG_BASE + 0x2f4)
#define SCUFIFO_V7_W_C_TIMSTAMP_SET1 (CXD56_SCU_FIFO_REG_BASE + 0x2f8)
#define SCUFIFO_V8_W_C_CTRL0 (CXD56_SCU_FIFO_REG_BASE + 0x300)
#define SCUFIFO_V8_W_C_CTRL1 (CXD56_SCU_FIFO_REG_BASE + 0x304)
#define SCUFIFO_V8_W_C_STATUS (CXD56_SCU_FIFO_REG_BASE + 0x308)
#define SCUFIFO_V8_W_C_TIMSTAMP0 (CXD56_SCU_FIFO_REG_BASE + 0x30c)
#define SCUFIFO_V8_W_C_TIMSTAMP1 (CXD56_SCU_FIFO_REG_BASE + 0x310)
#define SCUFIFO_V8_W_C_TIMSTAMP_SET0 (CXD56_SCU_FIFO_REG_BASE + 0x314)
#define SCUFIFO_V8_W_C_TIMSTAMP_SET1 (CXD56_SCU_FIFO_REG_BASE + 0x318)
#define SCUFIFO_V9_W_C_CTRL0 (CXD56_SCU_FIFO_REG_BASE + 0x320)
#define SCUFIFO_V9_W_C_CTRL1 (CXD56_SCU_FIFO_REG_BASE + 0x324)
#define SCUFIFO_V9_W_C_STATUS (CXD56_SCU_FIFO_REG_BASE + 0x328)
#define SCUFIFO_V9_W_C_TIMSTAMP0 (CXD56_SCU_FIFO_REG_BASE + 0x32c)
#define SCUFIFO_V9_W_C_TIMSTAMP1 (CXD56_SCU_FIFO_REG_BASE + 0x330)
#define SCUFIFO_V9_W_C_TIMSTAMP_SET0 (CXD56_SCU_FIFO_REG_BASE + 0x334)
#define SCUFIFO_V9_W_C_TIMSTAMP_SET1 (CXD56_SCU_FIFO_REG_BASE + 0x338)
#define SCUFIFO_D0_R1_C_CTRL0 (CXD56_SCU_FIFO_REG_BASE + 0x1000)
#define SCUFIFO_D0_R1_C_CTRL1 (CXD56_SCU_FIFO_REG_BASE + 0x1004)
#define SCUFIFO_D0_R1_C_STATUS0 (CXD56_SCU_FIFO_REG_BASE + 0x1008)
#define SCUFIFO_D0_R1_C_STATUS1 (CXD56_SCU_FIFO_REG_BASE + 0x100c)
#define SCUFIFO_D0_R1_C_TIMSTAMP0 (CXD56_SCU_FIFO_REG_BASE + 0x1010)
#define SCUFIFO_D0_R1_C_TIMSTAMP1 (CXD56_SCU_FIFO_REG_BASE + 0x1014)
#define SCUFIFO_D0_R2_C_CTRL0 (CXD56_SCU_FIFO_REG_BASE + 0x1020)
#define SCUFIFO_D0_R2_C_CTRL1 (CXD56_SCU_FIFO_REG_BASE + 0x1024)
#define SCUFIFO_D0_R2_C_STATUS0 (CXD56_SCU_FIFO_REG_BASE + 0x1028)
#define SCUFIFO_D0_R2_C_STATUS1 (CXD56_SCU_FIFO_REG_BASE + 0x102c)
#define SCUFIFO_D0_R2_C_TIMSTAMP0 (CXD56_SCU_FIFO_REG_BASE + 0x1030)
#define SCUFIFO_D0_R2_C_TIMSTAMP1 (CXD56_SCU_FIFO_REG_BASE + 0x1034)
#define SCUFIFO_D1_R1_C_CTRL0 (CXD56_SCU_FIFO_REG_BASE + 0x1040)
#define SCUFIFO_D1_R1_C_CTRL1 (CXD56_SCU_FIFO_REG_BASE + 0x1044)
#define SCUFIFO_D1_R1_C_STATUS0 (CXD56_SCU_FIFO_REG_BASE + 0x1048)
#define SCUFIFO_D1_R1_C_STATUS1 (CXD56_SCU_FIFO_REG_BASE + 0x104c)
#define SCUFIFO_D1_R1_C_TIMSTAMP0 (CXD56_SCU_FIFO_REG_BASE + 0x1050)
#define SCUFIFO_D1_R1_C_TIMSTAMP1 (CXD56_SCU_FIFO_REG_BASE + 0x1054)
#define SCUFIFO_D1_R2_C_CTRL0 (CXD56_SCU_FIFO_REG_BASE + 0x1060)
#define SCUFIFO_D1_R2_C_CTRL1 (CXD56_SCU_FIFO_REG_BASE + 0x1064)
#define SCUFIFO_D1_R2_C_STATUS0 (CXD56_SCU_FIFO_REG_BASE + 0x1068)
#define SCUFIFO_D1_R2_C_STATUS1 (CXD56_SCU_FIFO_REG_BASE + 0x106c)
#define SCUFIFO_D1_R2_C_TIMSTAMP0 (CXD56_SCU_FIFO_REG_BASE + 0x1070)
#define SCUFIFO_D1_R2_C_TIMSTAMP1 (CXD56_SCU_FIFO_REG_BASE + 0x1074)
#define SCUFIFO_N0_R1_C_CTRL0 (CXD56_SCU_FIFO_REG_BASE + 0x1080)
#define SCUFIFO_N0_R1_C_CTRL1 (CXD56_SCU_FIFO_REG_BASE + 0x1084)
#define SCUFIFO_N0_R1_C_STATUS0 (CXD56_SCU_FIFO_REG_BASE + 0x1088)
#define SCUFIFO_N0_R1_C_STATUS1 (CXD56_SCU_FIFO_REG_BASE + 0x108c)
#define SCUFIFO_N0_R1_C_TIMSTAMP0 (CXD56_SCU_FIFO_REG_BASE + 0x1090)
#define SCUFIFO_N0_R1_C_TIMSTAMP1 (CXD56_SCU_FIFO_REG_BASE + 0x1094)
#define SCUFIFO_N1_R1_C_CTRL0 (CXD56_SCU_FIFO_REG_BASE + 0x10a0)
#define SCUFIFO_N1_R1_C_CTRL1 (CXD56_SCU_FIFO_REG_BASE + 0x10a4)
#define SCUFIFO_N1_R1_C_STATUS0 (CXD56_SCU_FIFO_REG_BASE + 0x10a8)
#define SCUFIFO_N1_R1_C_STATUS1 (CXD56_SCU_FIFO_REG_BASE + 0x10ac)
#define SCUFIFO_N1_R1_C_TIMSTAMP0 (CXD56_SCU_FIFO_REG_BASE + 0x10b0)
#define SCUFIFO_N1_R1_C_TIMSTAMP1 (CXD56_SCU_FIFO_REG_BASE + 0x10b4)
#define SCUFIFO_N2_R1_C_CTRL0 (CXD56_SCU_FIFO_REG_BASE + 0x10c0)
#define SCUFIFO_N2_R1_C_CTRL1 (CXD56_SCU_FIFO_REG_BASE + 0x10c4)
#define SCUFIFO_N2_R1_C_STATUS0 (CXD56_SCU_FIFO_REG_BASE + 0x10c8)
#define SCUFIFO_N2_R1_C_STATUS1 (CXD56_SCU_FIFO_REG_BASE + 0x10cc)
#define SCUFIFO_N2_R1_C_TIMSTAMP0 (CXD56_SCU_FIFO_REG_BASE + 0x10d0)
#define SCUFIFO_N2_R1_C_TIMSTAMP1 (CXD56_SCU_FIFO_REG_BASE + 0x10d4)
#define SCUFIFO_N3_R1_C_CTRL0 (CXD56_SCU_FIFO_REG_BASE + 0x10e0)
#define SCUFIFO_N3_R1_C_CTRL1 (CXD56_SCU_FIFO_REG_BASE + 0x10e4)
#define SCUFIFO_N3_R1_C_STATUS0 (CXD56_SCU_FIFO_REG_BASE + 0x10e8)
#define SCUFIFO_N3_R1_C_STATUS1 (CXD56_SCU_FIFO_REG_BASE + 0x10ec)
#define SCUFIFO_N3_R1_C_TIMSTAMP0 (CXD56_SCU_FIFO_REG_BASE + 0x10f0)
#define SCUFIFO_N3_R1_C_TIMSTAMP1 (CXD56_SCU_FIFO_REG_BASE + 0x10f4)
#define SCUFIFO_N4_R1_C_CTRL0 (CXD56_SCU_FIFO_REG_BASE + 0x1100)
#define SCUFIFO_N4_R1_C_CTRL1 (CXD56_SCU_FIFO_REG_BASE + 0x1104)
#define SCUFIFO_N4_R1_C_STATUS0 (CXD56_SCU_FIFO_REG_BASE + 0x1108)
#define SCUFIFO_N4_R1_C_STATUS1 (CXD56_SCU_FIFO_REG_BASE + 0x110c)
#define SCUFIFO_N4_R1_C_TIMSTAMP0 (CXD56_SCU_FIFO_REG_BASE + 0x1110)
#define SCUFIFO_N4_R1_C_TIMSTAMP1 (CXD56_SCU_FIFO_REG_BASE + 0x1114)
#define SCUFIFO_N5_R1_C_CTRL0 (CXD56_SCU_FIFO_REG_BASE + 0x1120)
#define SCUFIFO_N5_R1_C_CTRL1 (CXD56_SCU_FIFO_REG_BASE + 0x1124)
#define SCUFIFO_N5_R1_C_STATUS0 (CXD56_SCU_FIFO_REG_BASE + 0x1128)
#define SCUFIFO_N5_R1_C_STATUS1 (CXD56_SCU_FIFO_REG_BASE + 0x112c)
#define SCUFIFO_N5_R1_C_TIMSTAMP0 (CXD56_SCU_FIFO_REG_BASE + 0x1130)
#define SCUFIFO_N5_R1_C_TIMSTAMP1 (CXD56_SCU_FIFO_REG_BASE + 0x1134)
#define SCUFIFO_N6_R1_C_CTRL0 (CXD56_SCU_FIFO_REG_BASE + 0x1140)
#define SCUFIFO_N6_R1_C_CTRL1 (CXD56_SCU_FIFO_REG_BASE + 0x1144)
#define SCUFIFO_N6_R1_C_STATUS0 (CXD56_SCU_FIFO_REG_BASE + 0x1148)
#define SCUFIFO_N6_R1_C_STATUS1 (CXD56_SCU_FIFO_REG_BASE + 0x114c)
#define SCUFIFO_N6_R1_C_TIMSTAMP0 (CXD56_SCU_FIFO_REG_BASE + 0x1150)
#define SCUFIFO_N6_R1_C_TIMSTAMP1 (CXD56_SCU_FIFO_REG_BASE + 0x1154)
#define SCUFIFO_N7_R1_C_CTRL0 (CXD56_SCU_FIFO_REG_BASE + 0x1160)
#define SCUFIFO_N7_R1_C_CTRL1 (CXD56_SCU_FIFO_REG_BASE + 0x1164)
#define SCUFIFO_N7_R1_C_STATUS0 (CXD56_SCU_FIFO_REG_BASE + 0x1168)
#define SCUFIFO_N7_R1_C_STATUS1 (CXD56_SCU_FIFO_REG_BASE + 0x116c)
#define SCUFIFO_N7_R1_C_TIMSTAMP0 (CXD56_SCU_FIFO_REG_BASE + 0x1170)
#define SCUFIFO_N7_R1_C_TIMSTAMP1 (CXD56_SCU_FIFO_REG_BASE + 0x1174)
#define SCUFIFO_D0_R3_CH_CTRL0 (CXD56_SCU_FIFO_REG_BASE + 0x1180)
#define SCUFIFO_D0_R3_CH_CTRL1 (CXD56_SCU_FIFO_REG_BASE + 0x1184)
#define SCUFIFO_D0_R3_CH_STATUS0 (CXD56_SCU_FIFO_REG_BASE + 0x1188)
#define SCUFIFO_D0_R3_CH_STATUS1 (CXD56_SCU_FIFO_REG_BASE + 0x118c)
#define SCUFIFO_D0_R3_CH_TIMSTAMP0 (CXD56_SCU_FIFO_REG_BASE + 0x1190)
#define SCUFIFO_D0_R3_CH_TIMSTAMP1 (CXD56_SCU_FIFO_REG_BASE + 0x1194)
#define SCUFIFO_D1_R3_CH_CTRL0 (CXD56_SCU_FIFO_REG_BASE + 0x11a0)
#define SCUFIFO_D1_R3_CH_CTRL1 (CXD56_SCU_FIFO_REG_BASE + 0x11a4)
#define SCUFIFO_D1_R3_CH_STATUS0 (CXD56_SCU_FIFO_REG_BASE + 0x11a8)
#define SCUFIFO_D1_R3_CH_STATUS1 (CXD56_SCU_FIFO_REG_BASE + 0x11ac)
#define SCUFIFO_D1_R3_CH_TIMSTAMP0 (CXD56_SCU_FIFO_REG_BASE + 0x11b0)
#define SCUFIFO_D1_R3_CH_TIMSTAMP1 (CXD56_SCU_FIFO_REG_BASE + 0x11b4)
#define SCUFIFO_D0_R0_H_CTRL0 (CXD56_SCU_FIFO_REG_BASE + 0x11c0)
#define SCUFIFO_D0_R0_H_CTRL1 (CXD56_SCU_FIFO_REG_BASE + 0x11c4)
#define SCUFIFO_D0_R0_H_STATUS0 (CXD56_SCU_FIFO_REG_BASE + 0x11c8)
#define SCUFIFO_D0_R0_H_STATUS1 (CXD56_SCU_FIFO_REG_BASE + 0x11cc)
#define SCUFIFO_D0_R0_H_TIMSTAMP0 (CXD56_SCU_FIFO_REG_BASE + 0x11d0)
#define SCUFIFO_D0_R0_H_TIMSTAMP1 (CXD56_SCU_FIFO_REG_BASE + 0x11d4)
#define SCUFIFO_D1_R0_H_CTRL0 (CXD56_SCU_FIFO_REG_BASE + 0x11e0)
#define SCUFIFO_D1_R0_H_CTRL1 (CXD56_SCU_FIFO_REG_BASE + 0x11e4)
#define SCUFIFO_D1_R0_H_STATUS0 (CXD56_SCU_FIFO_REG_BASE + 0x11e8)
#define SCUFIFO_D1_R0_H_STATUS1 (CXD56_SCU_FIFO_REG_BASE + 0x11ec)
#define SCUFIFO_D1_R0_H_TIMSTAMP0 (CXD56_SCU_FIFO_REG_BASE + 0x11f0)
#define SCUFIFO_D1_R0_H_TIMSTAMP1 (CXD56_SCU_FIFO_REG_BASE + 0x11f4)
#define SCUFIFO_N0_R0_H_CTRL0 (CXD56_SCU_FIFO_REG_BASE + 0x1200)
#define SCUFIFO_N0_R0_H_CTRL1 (CXD56_SCU_FIFO_REG_BASE + 0x1204)
#define SCUFIFO_N0_R0_H_STATUS0 (CXD56_SCU_FIFO_REG_BASE + 0x1208)
#define SCUFIFO_N0_R0_H_STATUS1 (CXD56_SCU_FIFO_REG_BASE + 0x120c)
#define SCUFIFO_N0_R0_H_TIMSTAMP0 (CXD56_SCU_FIFO_REG_BASE + 0x1210)
#define SCUFIFO_N0_R0_H_TIMSTAMP1 (CXD56_SCU_FIFO_REG_BASE + 0x1214)
#define SCUFIFO_N1_R0_H_CTRL0 (CXD56_SCU_FIFO_REG_BASE + 0x1220)
#define SCUFIFO_N1_R0_H_CTRL1 (CXD56_SCU_FIFO_REG_BASE + 0x1224)
#define SCUFIFO_N1_R0_H_STATUS0 (CXD56_SCU_FIFO_REG_BASE + 0x1228)
#define SCUFIFO_N1_R0_H_STATUS1 (CXD56_SCU_FIFO_REG_BASE + 0x122c)
#define SCUFIFO_N1_R0_H_TIMSTAMP0 (CXD56_SCU_FIFO_REG_BASE + 0x1230)
#define SCUFIFO_N1_R0_H_TIMSTAMP1 (CXD56_SCU_FIFO_REG_BASE + 0x1234)
#define SCUFIFO_N2_R0_H_CTRL0 (CXD56_SCU_FIFO_REG_BASE + 0x1240)
#define SCUFIFO_N2_R0_H_CTRL1 (CXD56_SCU_FIFO_REG_BASE + 0x1244)
#define SCUFIFO_N2_R0_H_STATUS0 (CXD56_SCU_FIFO_REG_BASE + 0x1248)
#define SCUFIFO_N2_R0_H_STATUS1 (CXD56_SCU_FIFO_REG_BASE + 0x124c)
#define SCUFIFO_N2_R0_H_TIMSTAMP0 (CXD56_SCU_FIFO_REG_BASE + 0x1250)
#define SCUFIFO_N2_R0_H_TIMSTAMP1 (CXD56_SCU_FIFO_REG_BASE + 0x1254)
#define SCUFIFO_N3_R0_H_CTRL0 (CXD56_SCU_FIFO_REG_BASE + 0x1260)
#define SCUFIFO_N3_R0_H_CTRL1 (CXD56_SCU_FIFO_REG_BASE + 0x1264)
#define SCUFIFO_N3_R0_H_STATUS0 (CXD56_SCU_FIFO_REG_BASE + 0x1268)
#define SCUFIFO_N3_R0_H_STATUS1 (CXD56_SCU_FIFO_REG_BASE + 0x126c)
#define SCUFIFO_N3_R0_H_TIMSTAMP0 (CXD56_SCU_FIFO_REG_BASE + 0x1270)
#define SCUFIFO_N3_R0_H_TIMSTAMP1 (CXD56_SCU_FIFO_REG_BASE + 0x1274)
#define SCUFIFO_N4_R0_H_CTRL0 (CXD56_SCU_FIFO_REG_BASE + 0x1280)
#define SCUFIFO_N4_R0_H_CTRL1 (CXD56_SCU_FIFO_REG_BASE + 0x1284)
#define SCUFIFO_N4_R0_H_STATUS0 (CXD56_SCU_FIFO_REG_BASE + 0x1288)
#define SCUFIFO_N4_R0_H_STATUS1 (CXD56_SCU_FIFO_REG_BASE + 0x128c)
#define SCUFIFO_N4_R0_H_TIMSTAMP0 (CXD56_SCU_FIFO_REG_BASE + 0x1290)
#define SCUFIFO_N4_R0_H_TIMSTAMP1 (CXD56_SCU_FIFO_REG_BASE + 0x1294)
#define SCUFIFO_N5_R0_H_CTRL0 (CXD56_SCU_FIFO_REG_BASE + 0x12a0)
#define SCUFIFO_N5_R0_H_CTRL1 (CXD56_SCU_FIFO_REG_BASE + 0x12a4)
#define SCUFIFO_N5_R0_H_STATUS0 (CXD56_SCU_FIFO_REG_BASE + 0x12a8)
#define SCUFIFO_N5_R0_H_STATUS1 (CXD56_SCU_FIFO_REG_BASE + 0x12ac)
#define SCUFIFO_N5_R0_H_TIMSTAMP0 (CXD56_SCU_FIFO_REG_BASE + 0x12b0)
#define SCUFIFO_N5_R0_H_TIMSTAMP1 (CXD56_SCU_FIFO_REG_BASE + 0x12b4)
#define SCUFIFO_N6_R0_H_CTRL0 (CXD56_SCU_FIFO_REG_BASE + 0x12c0)
#define SCUFIFO_N6_R0_H_CTRL1 (CXD56_SCU_FIFO_REG_BASE + 0x12c4)
#define SCUFIFO_N6_R0_H_STATUS0 (CXD56_SCU_FIFO_REG_BASE + 0x12c8)
#define SCUFIFO_N6_R0_H_STATUS1 (CXD56_SCU_FIFO_REG_BASE + 0x12cc)
#define SCUFIFO_N6_R0_H_TIMSTAMP0 (CXD56_SCU_FIFO_REG_BASE + 0x12d0)
#define SCUFIFO_N6_R0_H_TIMSTAMP1 (CXD56_SCU_FIFO_REG_BASE + 0x12d4)
#define SCUFIFO_N7_R0_H_CTRL0 (CXD56_SCU_FIFO_REG_BASE + 0x12e0)
#define SCUFIFO_N7_R0_H_CTRL1 (CXD56_SCU_FIFO_REG_BASE + 0x12e4)
#define SCUFIFO_N7_R0_H_STATUS0 (CXD56_SCU_FIFO_REG_BASE + 0x12e8)
#define SCUFIFO_N7_R0_H_STATUS1 (CXD56_SCU_FIFO_REG_BASE + 0x12ec)
#define SCUFIFO_N7_R0_H_TIMSTAMP0 (CXD56_SCU_FIFO_REG_BASE + 0x12f0)
#define SCUFIFO_N7_R0_H_TIMSTAMP1 (CXD56_SCU_FIFO_REG_BASE + 0x12f4)
#define SCUFIFO_V0_R_H_CTRL0 (CXD56_SCU_FIFO_REG_BASE + 0x1300)
#define SCUFIFO_V0_R_H_CTRL1 (CXD56_SCU_FIFO_REG_BASE + 0x1304)
#define SCUFIFO_V0_R_H_STATUS0 (CXD56_SCU_FIFO_REG_BASE + 0x1308)
#define SCUFIFO_V0_R_H_STATUS1 (CXD56_SCU_FIFO_REG_BASE + 0x130c)
#define SCUFIFO_V0_R_H_TIMSTAMP0 (CXD56_SCU_FIFO_REG_BASE + 0x1310)
#define SCUFIFO_V0_R_H_TIMSTAMP1 (CXD56_SCU_FIFO_REG_BASE + 0x1314)
#define SCUFIFO_V1_R_H_CTRL0 (CXD56_SCU_FIFO_REG_BASE + 0x1320)
#define SCUFIFO_V1_R_H_CTRL1 (CXD56_SCU_FIFO_REG_BASE + 0x1324)
#define SCUFIFO_V1_R_H_STATUS0 (CXD56_SCU_FIFO_REG_BASE + 0x1328)
#define SCUFIFO_V1_R_H_STATUS1 (CXD56_SCU_FIFO_REG_BASE + 0x132c)
#define SCUFIFO_V1_R_H_TIMSTAMP0 (CXD56_SCU_FIFO_REG_BASE + 0x1330)
#define SCUFIFO_V1_R_H_TIMSTAMP1 (CXD56_SCU_FIFO_REG_BASE + 0x1334)
#define SCUFIFO_V2_R_H_CTRL0 (CXD56_SCU_FIFO_REG_BASE + 0x1340)
#define SCUFIFO_V2_R_H_CTRL1 (CXD56_SCU_FIFO_REG_BASE + 0x1344)
#define SCUFIFO_V2_R_H_STATUS0 (CXD56_SCU_FIFO_REG_BASE + 0x1348)
#define SCUFIFO_V2_R_H_STATUS1 (CXD56_SCU_FIFO_REG_BASE + 0x134c)
#define SCUFIFO_V2_R_H_TIMSTAMP0 (CXD56_SCU_FIFO_REG_BASE + 0x1350)
#define SCUFIFO_V2_R_H_TIMSTAMP1 (CXD56_SCU_FIFO_REG_BASE + 0x1354)
#define SCUFIFO_V3_R_H_CTRL0 (CXD56_SCU_FIFO_REG_BASE + 0x1360)
#define SCUFIFO_V3_R_H_CTRL1 (CXD56_SCU_FIFO_REG_BASE + 0x1364)
#define SCUFIFO_V3_R_H_STATUS0 (CXD56_SCU_FIFO_REG_BASE + 0x1368)
#define SCUFIFO_V3_R_H_STATUS1 (CXD56_SCU_FIFO_REG_BASE + 0x136c)
#define SCUFIFO_V3_R_H_TIMSTAMP0 (CXD56_SCU_FIFO_REG_BASE + 0x1370)
#define SCUFIFO_V3_R_H_TIMSTAMP1 (CXD56_SCU_FIFO_REG_BASE + 0x1374)
#define SCUFIFO_V4_R_H_CTRL0 (CXD56_SCU_FIFO_REG_BASE + 0x1380)
#define SCUFIFO_V4_R_H_CTRL1 (CXD56_SCU_FIFO_REG_BASE + 0x1384)
#define SCUFIFO_V4_R_H_STATUS0 (CXD56_SCU_FIFO_REG_BASE + 0x1388)
#define SCUFIFO_V4_R_H_STATUS1 (CXD56_SCU_FIFO_REG_BASE + 0x138c)
#define SCUFIFO_V4_R_H_TIMSTAMP0 (CXD56_SCU_FIFO_REG_BASE + 0x1390)
#define SCUFIFO_V4_R_H_TIMSTAMP1 (CXD56_SCU_FIFO_REG_BASE + 0x1394)
#define SCUFIFO_V5_R_H_CTRL0 (CXD56_SCU_FIFO_REG_BASE + 0x13a0)
#define SCUFIFO_V5_R_H_CTRL1 (CXD56_SCU_FIFO_REG_BASE + 0x13a4)
#define SCUFIFO_V5_R_H_STATUS0 (CXD56_SCU_FIFO_REG_BASE + 0x13a8)
#define SCUFIFO_V5_R_H_STATUS1 (CXD56_SCU_FIFO_REG_BASE + 0x13ac)
#define SCUFIFO_V5_R_H_TIMSTAMP0 (CXD56_SCU_FIFO_REG_BASE + 0x13b0)
#define SCUFIFO_V5_R_H_TIMSTAMP1 (CXD56_SCU_FIFO_REG_BASE + 0x13b4)
#define SCUFIFO_V6_R_H_CTRL0 (CXD56_SCU_FIFO_REG_BASE + 0x13c0)
#define SCUFIFO_V6_R_H_CTRL1 (CXD56_SCU_FIFO_REG_BASE + 0x13c4)
#define SCUFIFO_V6_R_H_STATUS0 (CXD56_SCU_FIFO_REG_BASE + 0x13c8)
#define SCUFIFO_V6_R_H_STATUS1 (CXD56_SCU_FIFO_REG_BASE + 0x13cc)
#define SCUFIFO_V6_R_H_TIMSTAMP0 (CXD56_SCU_FIFO_REG_BASE + 0x13d0)
#define SCUFIFO_V6_R_H_TIMSTAMP1 (CXD56_SCU_FIFO_REG_BASE + 0x13d4)
#define SCUFIFO_V7_R_H_CTRL0 (CXD56_SCU_FIFO_REG_BASE + 0x13e0)
#define SCUFIFO_V7_R_H_CTRL1 (CXD56_SCU_FIFO_REG_BASE + 0x13e4)
#define SCUFIFO_V7_R_H_STATUS0 (CXD56_SCU_FIFO_REG_BASE + 0x13e8)
#define SCUFIFO_V7_R_H_STATUS1 (CXD56_SCU_FIFO_REG_BASE + 0x13ec)
#define SCUFIFO_V7_R_H_TIMSTAMP0 (CXD56_SCU_FIFO_REG_BASE + 0x13f0)
#define SCUFIFO_V7_R_H_TIMSTAMP1 (CXD56_SCU_FIFO_REG_BASE + 0x13f4)
#define SCUFIFO_V8_R_H_CTRL0 (CXD56_SCU_FIFO_REG_BASE + 0x1400)
#define SCUFIFO_V8_R_H_CTRL1 (CXD56_SCU_FIFO_REG_BASE + 0x1404)
#define SCUFIFO_V8_R_H_STATUS0 (CXD56_SCU_FIFO_REG_BASE + 0x1408)
#define SCUFIFO_V8_R_H_STATUS1 (CXD56_SCU_FIFO_REG_BASE + 0x140c)
#define SCUFIFO_V8_R_H_TIMSTAMP0 (CXD56_SCU_FIFO_REG_BASE + 0x1410)
#define SCUFIFO_V8_R_H_TIMSTAMP1 (CXD56_SCU_FIFO_REG_BASE + 0x1414)
#define SCUFIFO_V9_R_H_CTRL0 (CXD56_SCU_FIFO_REG_BASE + 0x1420)
#define SCUFIFO_V9_R_H_CTRL1 (CXD56_SCU_FIFO_REG_BASE + 0x1424)
#define SCUFIFO_V9_R_H_STATUS0 (CXD56_SCU_FIFO_REG_BASE + 0x1428)
#define SCUFIFO_V9_R_H_STATUS1 (CXD56_SCU_FIFO_REG_BASE + 0x142c)
#define SCUFIFO_V9_R_H_TIMSTAMP0 (CXD56_SCU_FIFO_REG_BASE + 0x1430)
#define SCUFIFO_V9_R_H_TIMSTAMP1 (CXD56_SCU_FIFO_REG_BASE + 0x1434)
#define SCUFIFO_DECI_PARTITION_SEL (CXD56_SCU_FIFO_REG_BASE + 0x1c00)
#define SCUFIFO_FIFO_DATA(x) (CXD56_SCU_FIFO_REG_BASE + 0x2100 + (0x4 * (x)))

24
arch/avr/src/avr/excptmacros.h
View file

@ -177,22 +177,22 @@
* HANDLER, r15 was saved above, and r26-r27 saved later, out of sequence)
*/
push r18
push r19
push r20
push r21
push r22
push r23
push r18
push r19
push r20
push r21
push r22
push r23
/* Save r28-r29 - Call-saved, "static" registers */
push r28
push r29
push r28
push r29
/* Save r30-r31 - Call-used, "volatile" registers */
push r30
push r31
push r30
push r31
/* Now save r26-r27 */
@ -201,7 +201,7 @@
/* Finally, save the stack pointer. BUT we want the value of the stack
* pointer as it was just BEFORE the exception. We'll have to add to get
* that value. The value to add is the size of the register save area
* that value. The value to add is the size of the register save area
* including the bytes pushed by the interrupt handler (2), by the HANDLER
* macro (1), and the 32 registers pushed above. That is, the entire size
* of the register save structure MINUS two bytes for the stack pointer
@ -388,7 +388,7 @@
/* Skip over r0 -- the scratch register */
adiw r26, 1
adiw r26, 1
/* Save the status register
* (probably not necessary since interrupts are disabled)

4
arch/mips/src/pic32mx/excptmacros.h
View file

@ -118,7 +118,7 @@
* register save array.
*/
addiu sp, sp, -XCPTCONTEXT_SIZE
addiu sp, sp, -XCPTCONTEXT_SIZE
/* Save the EPC and STATUS in the register context array */
@ -267,7 +267,7 @@
* Use k1 as the pointer to the register save array.
*/
move k1, \regs
move k1, \regs
/* Restore the floating point register state */

2
arch/mips/src/pic32mz/pic32mz_excptmacros.h
View file

@ -118,7 +118,7 @@
* register save array.
*/
addiu sp, sp, -XCPTCONTEXT_SIZE
addiu sp, sp, -XCPTCONTEXT_SIZE
/* Save the EPC and STATUS in the register context array */

8
arch/misoc/src/common/hw/ethmac_mem.h
View file

@ -31,9 +31,9 @@
* Pre-processor Definitions
****************************************************************************/
#define ETHMAC_RX0_BASE ETHMAC_BASE
#define ETHMAC_RX1_BASE (ETHMAC_BASE+0x0800)
#define ETHMAC_TX0_BASE (ETHMAC_BASE+0x1000)
#define ETHMAC_TX1_BASE (ETHMAC_BASE+0x1800)
#define ETHMAC_RX0_BASE ETHMAC_BASE
#define ETHMAC_RX1_BASE (ETHMAC_BASE+0x0800)
#define ETHMAC_TX0_BASE (ETHMAC_BASE+0x1000)
#define ETHMAC_TX1_BASE (ETHMAC_BASE+0x1800)
#endif /* __ARCH_MISOC_SRC_COMMON_HW_ETHMAC_MEM_H */

12
arch/renesas/src/rx65n/rx65n_rspi_sw.c
View file

@ -158,13 +158,13 @@ struct rx65n_rspidev_s
uint32_t frequency; /* Requested clock frequency */
uint32_t actual; /* Actual clock frequency */
int ntxwords; /* Number of words left to transfer on the Tx Buffer */
int nrxwords; /* Number of words received on the Rx Buffer */
int nwords; /* Number of words to be exchanged */
int ntxwords; /* Number of words left to transfer on the Tx Buffer */
int nrxwords; /* Number of words received on the Rx Buffer */
int nwords; /* Number of words to be exchanged */
uint8_t nbits; /* Width of word in bits (4 through 16) */
uint8_t mode; /* Mode 0,1,2,3 */
uint8_t bufsize; /* Buf size: 1,2,3 or 4 word */
uint8_t nbits; /* Width of word in bits (4 through 16) */
uint8_t mode; /* Mode 0,1,2,3 */
uint8_t bufsize; /* Buf size: 1,2,3 or 4 word */
};
/****************************************************************************

12
arch/risc-v/src/mpfs/hardware/mpfs_ihc.h
View file

@ -190,18 +190,18 @@ struct ihc_sbi_rx_msg_s
* communicating with
*/
#define HSS_REMOTE_HARTS_MASK (HART1_MASK | HART2_MASK | HART3_MASK | HART4_MASK)
#define HSS_REMOTE_HARTS_MASK (HART1_MASK | HART2_MASK | HART3_MASK | HART4_MASK)
/* Define which harts are connected via comms channels to a particular hart
* user defined.
*/
#define IHCIA_H0_REMOTE_HARTS ((~HSS_HART_MASK) & HSS_REMOTE_HARTS_MASK)
#define IHCIA_H0_REMOTE_HARTS ((~HSS_HART_MASK) & HSS_REMOTE_HARTS_MASK)
#define IHCIA_H1_REMOTE_HARTS (HSS_HART_MASK | (1 << CONTEXTA_HARTID))
#define IHCIA_H2_REMOTE_HARTS (HSS_HART_MASK | (1 << CONTEXTA_HARTID))
#define IHCIA_H3_REMOTE_HARTS (HSS_HART_MASK | (1 << CONTEXTA_HARTID))
#define IHCIA_H4_REMOTE_HARTS (HSS_HART_MASK | (1 << CONTEXTA_HARTID))
#define IHCIA_H1_REMOTE_HARTS (HSS_HART_MASK | (1 << CONTEXTA_HARTID))
#define IHCIA_H2_REMOTE_HARTS (HSS_HART_MASK | (1 << CONTEXTA_HARTID))
#define IHCIA_H3_REMOTE_HARTS (HSS_HART_MASK | (1 << CONTEXTA_HARTID))
#define IHCIA_H4_REMOTE_HARTS (HSS_HART_MASK | (1 << CONTEXTA_HARTID))
#define HSS_HART_DEFAULT_INT_EN (0 << 0)

78
arch/sparc/include/bm3803/irq.h
View file

@ -44,23 +44,23 @@
#define BM3803_IRQ_FIRST 0x00
#define BM3803_IRQ_RESET 0x00
#define BM3803_IRQ_INST_ACC_EXCEPTION 0x01
#define BM3803_IRQ_ILL_INST 0x02
#define BM3803_IRQ_PRIVELEGE_INST 0x03
#define BM3803_IRQ_FP_DISABLED 0x04
#define BM3803_IRQ_WINDOW_OVERFLOW 0x05
#define BM3803_IRQ_WINDOW_UNDERFLOW 0x06
#define BM3803_IRQ_ADD_NOT_ALIGNED 0x07
#define BM3803_IRQ_ADD_FP_EXCEPTION 0x08
#define BM3803_IRQ_DATA_ACC_EXCEPTION 0x09
#define BM3803_IRQ_TAG_OVERFLOW 0x0A
#define BM3803_IRQ_HW_UNDEFINED_0B 0x0B
#define BM3803_IRQ_HW_UNDEFINED_0C 0x0C
#define BM3803_IRQ_HW_UNDEFINED_0D 0x0D
#define BM3803_IRQ_HW_UNDEFINED_0E 0x0E
#define BM3803_IRQ_HW_UNDEFINED_0F 0x0F
#define BM3803_IRQ_HW_UNDEFINED_10 0x10
#define BM3803_IRQ_RESET 0x00
#define BM3803_IRQ_INST_ACC_EXCEPTION 0x01
#define BM3803_IRQ_ILL_INST 0x02
#define BM3803_IRQ_PRIVELEGE_INST 0x03
#define BM3803_IRQ_FP_DISABLED 0x04
#define BM3803_IRQ_WINDOW_OVERFLOW 0x05
#define BM3803_IRQ_WINDOW_UNDERFLOW 0x06
#define BM3803_IRQ_ADD_NOT_ALIGNED 0x07
#define BM3803_IRQ_ADD_FP_EXCEPTION 0x08
#define BM3803_IRQ_DATA_ACC_EXCEPTION 0x09
#define BM3803_IRQ_TAG_OVERFLOW 0x0A
#define BM3803_IRQ_HW_UNDEFINED_0B 0x0B
#define BM3803_IRQ_HW_UNDEFINED_0C 0x0C
#define BM3803_IRQ_HW_UNDEFINED_0D 0x0D
#define BM3803_IRQ_HW_UNDEFINED_0E 0x0E
#define BM3803_IRQ_HW_UNDEFINED_0F 0x0F
#define BM3803_IRQ_HW_UNDEFINED_10 0x10
#define BM3803_IRQ_FIRST_INTERRUPT 0x11
#define BM3803_IRQ_CORRECTABLE_MEMORY_ERROR 0x11
@ -80,42 +80,42 @@
#define BM3803_IRQ_EMPTY6 0x1F
#define BM3803_IRQ_LAST_INTERRUPT 0x1F
#define BM3803_IRQ_HW_UNDEFINED_20 0x20
#define BM3803_IRQ_HW_UNDEFINED_21 0x21
#define BM3803_IRQ_HW_UNDEFINED_22 0x22
#define BM3803_IRQ_HW_UNDEFINED_23 0x23
#define BM3803_IRQ_HW_UNDEFINED_20 0x20
#define BM3803_IRQ_HW_UNDEFINED_21 0x21
#define BM3803_IRQ_HW_UNDEFINED_22 0x22
#define BM3803_IRQ_HW_UNDEFINED_23 0x23
#define BM3803_IRQ_CP_DISABLED 0x24
#define BM3803_IRQ_CP_DISABLED 0x24
#define BM3803_IRQ_HW_UNDEFINED_25 0x25
#define BM3803_IRQ_HW_UNDEFINED_26 0x26
#define BM3803_IRQ_HW_UNDEFINED_27 0x27
#define BM3803_IRQ_HW_UNDEFINED_25 0x25
#define BM3803_IRQ_HW_UNDEFINED_26 0x26
#define BM3803_IRQ_HW_UNDEFINED_27 0x27
#define BM3803_IRQ_CP_EXCEPTION 0x28
#define BM3803_IRQ_CP_EXCEPTION 0x28
#define BM3803_IRQ_HW_UNDEFINED_29 0x29
#define BM3803_IRQ_HW_UNDEFINED_7F 0x7F
#define BM3803_IRQ_HW_UNDEFINED_29 0x29
#define BM3803_IRQ_HW_UNDEFINED_7F 0x7F
#define BM3803_IRQ_SW_SYSCALL_TA0 0x80
#define BM3803_IRQ_SW_UNDEFINED_81 0x81
#define BM3803_IRQ_SW_UNDEFINED_82 0x82
#define BM3803_IRQ_SW_SYSCALL_TA0 0x80
#define BM3803_IRQ_SW_UNDEFINED_81 0x81
#define BM3803_IRQ_SW_UNDEFINED_82 0x82
#define BM3803_IRQ_SW_FLUSH_WINDOWS 0x83
#define BM3803_IRQ_SW_UNDEFINED_84 0x84
#define BM3803_IRQ_SW_UNDEFINED_85 0x85
#define BM3803_IRQ_SW_UNDEFINED_86 0x86
#define BM3803_IRQ_SW_UNDEFINED_87 0x87
#define BM3803_IRQ_SW_SYSCALL_TA8 0x88
#define BM3803_IRQ_SW_UNDEFINED_84 0x84
#define BM3803_IRQ_SW_UNDEFINED_85 0x85
#define BM3803_IRQ_SW_UNDEFINED_86 0x86
#define BM3803_IRQ_SW_UNDEFINED_87 0x87
#define BM3803_IRQ_SW_SYSCALL_TA8 0x88
#define BM3803_IRQ_SW_SYSCALL_IRQDIS 0x89
#define BM3803_IRQ_SW_SYSCALL_IRQEN 0x8A
#define BM3803_IRQ_SW_UNDEFINED_8B 0x8B
#define BM3803_IRQ_SW_UNDEFINED_FF 0xFF
#define BM3803_IRQ_SW_UNDEFINED_8B 0x8B
#define BM3803_IRQ_SW_UNDEFINED_FF 0xFF
#define BM3803_IRQ_LAST 0xFF
# define NR_IRQS 256
#define NR_IRQS 256
#else
#error "Unrecognized chip"

82
arch/sparc/include/bm3823/irq.h
View file

@ -46,26 +46,26 @@
#define BM3823_IRQ_FIRST 0x00
#define BM3823_IRQ_RESET 0x00
#define BM3823_IRQ_INST_ACC_EXCEPTION 0x01
#define BM3823_IRQ_ILL_INST 0x02
#define BM3823_IRQ_PRIVELEGE_INST 0x03
#define BM3823_IRQ_FP_DISABLED 0x04
#define BM3823_IRQ_WINDOW_OVERFLOW 0x05
#define BM3823_IRQ_WINDOW_UNDERFLOW 0x06
#define BM3823_IRQ_ADD_NOT_ALIGNED 0x07
#define BM3823_IRQ_ADD_FP_EXCEPTION 0x08
#define BM3823_IRQ_DATA_ACC_EXCEPTION 0x09
#define BM3823_IRQ_TAG_OVERFLOW 0x0A
#define BM3823_IRQ_HW_UNDEFINED_0B 0x0B
#define BM3823_IRQ_HW_UNDEFINED_0C 0x0C
#define BM3823_IRQ_HW_UNDEFINED_0D 0x0D
#define BM3823_IRQ_HW_UNDEFINED_0E 0x0E
#define BM3823_IRQ_HW_UNDEFINED_0F 0x0F
#define BM3823_IRQ_HW_UNDEFINED_10 0x10
#define BM3823_IRQ_RESET 0x00
#define BM3823_IRQ_INST_ACC_EXCEPTION 0x01
#define BM3823_IRQ_ILL_INST 0x02
#define BM3823_IRQ_PRIVELEGE_INST 0x03
#define BM3823_IRQ_FP_DISABLED 0x04
#define BM3823_IRQ_WINDOW_OVERFLOW 0x05
#define BM3823_IRQ_WINDOW_UNDERFLOW 0x06
#define BM3823_IRQ_ADD_NOT_ALIGNED 0x07
#define BM3823_IRQ_ADD_FP_EXCEPTION 0x08
#define BM3823_IRQ_DATA_ACC_EXCEPTION 0x09
#define BM3823_IRQ_TAG_OVERFLOW 0x0A
#define BM3823_IRQ_HW_UNDEFINED_0B 0x0B
#define BM3823_IRQ_HW_UNDEFINED_0C 0x0C
#define BM3823_IRQ_HW_UNDEFINED_0D 0x0D
#define BM3823_IRQ_HW_UNDEFINED_0E 0x0E
#define BM3823_IRQ_HW_UNDEFINED_0F 0x0F
#define BM3823_IRQ_HW_UNDEFINED_10 0x10
#define BM3823_IRQ_FIRST_INTERRUPT 0x11
#define BM3823_IRQ_AHB_ERROR 0x11
#define BM3823_IRQ_AHB_ERROR 0x11
#define BM3823_IRQ_UART_2_RX_TX 0x12
#define BM3823_IRQ_UART_1_RX_TX 0x13
#define BM3823_IRQ_EXTERNAL_0 0x14
@ -76,48 +76,48 @@
#define BM3823_IRQ_EXTERNAL_5 0x19
#define BM3823_IRQ_SECOND 0x1A
#define BM3823_IRQ_DSUTRACWBUFF 0x1B
#define BM3823_IRQ_PCI 0x1C
#define BM3823_IRQ_PCI 0x1C
#define BM3823_IRQ_TIMER2 0x1D
#define BM3823_IRQ_TIMER1 0x1E
#define BM3823_IRQ_NONMASK 0x1F
#define BM3823_IRQ_LAST_INTERRUPT 0x1F
#define BM3823_IRQ_HW_UNDEFINED_20 0x20
#define BM3823_IRQ_HW_UNDEFINED_21 0x21
#define BM3823_IRQ_HW_UNDEFINED_22 0x22
#define BM3823_IRQ_HW_UNDEFINED_23 0x23
#define BM3823_IRQ_HW_UNDEFINED_20 0x20
#define BM3823_IRQ_HW_UNDEFINED_21 0x21
#define BM3823_IRQ_HW_UNDEFINED_22 0x22
#define BM3823_IRQ_HW_UNDEFINED_23 0x23
#define BM3823_IRQ_CP_DISABLED 0x24
#define BM3823_IRQ_CP_DISABLED 0x24
#define BM3823_IRQ_HW_UNDEFINED_25 0x25
#define BM3823_IRQ_HW_UNDEFINED_26 0x26
#define BM3823_IRQ_HW_UNDEFINED_27 0x27
#define BM3823_IRQ_HW_UNDEFINED_25 0x25
#define BM3823_IRQ_HW_UNDEFINED_26 0x26
#define BM3823_IRQ_HW_UNDEFINED_27 0x27
#define BM3823_IRQ_CP_EXCEPTION 0x28
#define BM3823_IRQ_CP_EXCEPTION 0x28
#define BM3823_IRQ_HW_UNDEFINED_29 0x29
#define BM3823_IRQ_HW_UNDEFINED_7F 0x7F
#define BM3823_IRQ_HW_UNDEFINED_29 0x29
#define BM3823_IRQ_HW_UNDEFINED_7F 0x7F
#define BM3823_IRQ_SW_SYSCALL_TA0 0x80
#define BM3823_IRQ_SW_UNDEFINED_81 0x81
#define BM3823_IRQ_SW_UNDEFINED_82 0x82
#define BM3823_IRQ_SW_SYSCALL_TA0 0x80
#define BM3823_IRQ_SW_UNDEFINED_81 0x81
#define BM3823_IRQ_SW_UNDEFINED_82 0x82
#define BM3823_IRQ_SW_FLUSH_WINDOWS 0x83
#define BM3823_IRQ_SW_UNDEFINED_84 0x84
#define BM3823_IRQ_SW_UNDEFINED_85 0x85
#define BM3823_IRQ_SW_UNDEFINED_86 0x86
#define BM3823_IRQ_SW_UNDEFINED_87 0x87
#define BM3823_IRQ_SW_SYSCALL_TA8 0x88
#define BM3823_IRQ_SW_UNDEFINED_84 0x84
#define BM3823_IRQ_SW_UNDEFINED_85 0x85
#define BM3823_IRQ_SW_UNDEFINED_86 0x86
#define BM3823_IRQ_SW_UNDEFINED_87 0x87
#define BM3823_IRQ_SW_SYSCALL_TA8 0x88
#define BM3823_IRQ_SW_SYSCALL_IRQDIS 0x89
#define BM3823_IRQ_SW_SYSCALL_IRQEN 0x8A
#define BM3823_IRQ_SW_UNDEFINED_8B 0x8B
#define BM3823_IRQ_SW_UNDEFINED_FF 0xFF
#define BM3823_IRQ_SW_UNDEFINED_8B 0x8B
#define BM3823_IRQ_SW_UNDEFINED_FF 0xFF
#define BM3823_IRQ_LAST 0xFF
# define NR_IRQS 256
#define NR_IRQS 256
#else
#error "Unrecognized chip"

104
arch/sparc/include/elf.h
View file

@ -27,58 +27,58 @@
/* Relocation codes */
#define R_SPARC_NONE 0
#define R_SPARC_8 1
#define R_SPARC_16 2
#define R_SPARC_32 3
#define R_SPARC_DISP8 4
#define R_SPARC_DISP16 5
#define R_SPARC_DISP32 6
#define R_SPARC_WDISP30 7
#define R_SPARC_WDISP22 8
#define R_SPARC_HI22 9
#define R_SPARC_22 10
#define R_SPARC_13 11
#define R_SPARC_LO10 12
#define R_SPARC_GOT10 13
#define R_SPARC_GOT13 14
#define R_SPARC_GOT22 15
#define R_SPARC_PC10 16
#define R_SPARC_PC22 17
#define R_SPARC_WPLT30 18
#define R_SPARC_COPY 19
#define R_SPARC_GLOB_DAT 20
#define R_SPARC_JMP_SLOT 21
#define R_SPARC_RELATIVE 22
#define R_SPARC_UA32 23
#define R_SPARC_PLT32 24
#define R_SPARC_HIPLT22 25
#define R_SPARC_LOPLT10 26
#define R_SPARC_PCPLT32 27
#define R_SPARC_PCPLT22 28
#define R_SPARC_PCPLT10 29
#define R_SPARC_10 30
#define R_SPARC_11 31
#define R_SPARC_64 32
#define R_SPARC_OLO10 33
#define R_SPARC_HH22 34
#define R_SPARC_HM10 35
#define R_SPARC_LM22 36
#define R_SPARC_PC_HH22 37
#define R_SPARC_PC_HM10 38
#define R_SPARC_PC_LM22 39
#define R_SPARC_WDISP16 40
#define R_SPARC_WDISP19 41
#define R_SPARC_GLOB_JMP 42
#define R_SPARC_7 43
#define R_SPARC_5 44
#define R_SPARC_6 45
#define R_SPARC_NONE 0
#define R_SPARC_8 1
#define R_SPARC_16 2
#define R_SPARC_32 3
#define R_SPARC_DISP8 4
#define R_SPARC_DISP16 5
#define R_SPARC_DISP32 6
#define R_SPARC_WDISP30 7
#define R_SPARC_WDISP22 8
#define R_SPARC_HI22 9
#define R_SPARC_22 10
#define R_SPARC_13 11
#define R_SPARC_LO10 12
#define R_SPARC_GOT10 13
#define R_SPARC_GOT13 14
#define R_SPARC_GOT22 15
#define R_SPARC_PC10 16
#define R_SPARC_PC22 17
#define R_SPARC_WPLT30 18
#define R_SPARC_COPY 19
#define R_SPARC_GLOB_DAT 20
#define R_SPARC_JMP_SLOT 21
#define R_SPARC_RELATIVE 22
#define R_SPARC_UA32 23
#define R_SPARC_PLT32 24
#define R_SPARC_HIPLT22 25
#define R_SPARC_LOPLT10 26
#define R_SPARC_PCPLT32 27
#define R_SPARC_PCPLT22 28
#define R_SPARC_PCPLT10 29
#define R_SPARC_10 30
#define R_SPARC_11 31
#define R_SPARC_64 32
#define R_SPARC_OLO10 33
#define R_SPARC_HH22 34
#define R_SPARC_HM10 35
#define R_SPARC_LM22 36
#define R_SPARC_PC_HH22 37
#define R_SPARC_PC_HM10 38
#define R_SPARC_PC_LM22 39
#define R_SPARC_WDISP16 40
#define R_SPARC_WDISP19 41
#define R_SPARC_GLOB_JMP 42
#define R_SPARC_7 43
#define R_SPARC_5 44
#define R_SPARC_6 45
#define OPCODE_NOP 0x01000000 /* nop */
#define OPCODE_CALL 0x40000000 /* call ?; add PC-rel word address */
#define OPCODE_SETHI_G1 0x03000000 /* sethi ?, %g1; add value>>10 */
#define OPCODE_JMP_G1 0x81c06000 /* jmp %g1+?; add lo 10 bits of value */
#define OPCODE_SAVE_SP 0x9de3bfa8 /* save %sp, -(16+6)*4, %sp */
#define OPCODE_BA 0x30800000 /* b,a ?; add PC-rel word address */
#define OPCODE_NOP 0x01000000 /* nop */
#define OPCODE_CALL 0x40000000 /* call ?; add PC-rel word address */
#define OPCODE_SETHI_G1 0x03000000 /* sethi ?, %g1; add value>>10 */
#define OPCODE_JMP_G1 0x81c06000 /* jmp %g1+?; add lo 10 bits of value */
#define OPCODE_SAVE_SP 0x9de3bfa8 /* save %sp, -(16+6)*4, %sp */
#define OPCODE_BA 0x30800000 /* b,a ?; add PC-rel word address */
#endif /* __ARCH_SPARC_INCLUDE_ELF_H */

78
arch/sparc/include/s698pm/irq.h
View file

@ -68,23 +68,23 @@
#define S698PM_IRQ_FIRST 0x00
#define S698PM_IRQ_RESET 0x00
#define S698PM_IRQ_INST_ACC_EXCEPTION 0x01
#define S698PM_IRQ_ILL_INST 0x02
#define S698PM_IRQ_PRIVELEGE_INST 0x03
#define S698PM_IRQ_FP_DISABLED 0x04
#define S698PM_IRQ_WINDOW_OVERFLOW 0x05
#define S698PM_IRQ_WINDOW_UNDERFLOW 0x06
#define S698PM_IRQ_ADD_NOT_ALIGNED 0x07
#define S698PM_IRQ_ADD_FP_EXCEPTION 0x08
#define S698PM_IRQ_DATA_ACC_EXCEPTION 0x09
#define S698PM_IRQ_TAG_OVERFLOW 0x0A
#define S698PM_IRQ_HW_UNDEFINED_0B 0x0B
#define S698PM_IRQ_HW_UNDEFINED_0C 0x0C
#define S698PM_IRQ_HW_UNDEFINED_0D 0x0D
#define S698PM_IRQ_HW_UNDEFINED_0E 0x0E
#define S698PM_IRQ_HW_UNDEFINED_0F 0x0F
#define S698PM_IRQ_HW_UNDEFINED_10 0x10
#define S698PM_IRQ_RESET 0x00
#define S698PM_IRQ_INST_ACC_EXCEPTION 0x01
#define S698PM_IRQ_ILL_INST 0x02
#define S698PM_IRQ_PRIVELEGE_INST 0x03
#define S698PM_IRQ_FP_DISABLED 0x04
#define S698PM_IRQ_WINDOW_OVERFLOW 0x05
#define S698PM_IRQ_WINDOW_UNDERFLOW 0x06
#define S698PM_IRQ_ADD_NOT_ALIGNED 0x07
#define S698PM_IRQ_ADD_FP_EXCEPTION 0x08
#define S698PM_IRQ_DATA_ACC_EXCEPTION 0x09
#define S698PM_IRQ_TAG_OVERFLOW 0x0A
#define S698PM_IRQ_HW_UNDEFINED_0B 0x0B
#define S698PM_IRQ_HW_UNDEFINED_0C 0x0C
#define S698PM_IRQ_HW_UNDEFINED_0D 0x0D
#define S698PM_IRQ_HW_UNDEFINED_0E 0x0E
#define S698PM_IRQ_HW_UNDEFINED_0F 0x0F
#define S698PM_IRQ_HW_UNDEFINED_10 0x10
#define S698PM_IRQ_FIRST_INT 0x11
@ -106,38 +106,38 @@
#define S698PM_IRQ_LAST_INT 0x1F
#define S698PM_IRQ_HW_UNDEFINED_20 0x20
#define S698PM_IRQ_HW_UNDEFINED_21 0x21
#define S698PM_IRQ_HW_UNDEFINED_22 0x22
#define S698PM_IRQ_HW_UNDEFINED_23 0x23
#define S698PM_IRQ_HW_UNDEFINED_20 0x20
#define S698PM_IRQ_HW_UNDEFINED_21 0x21
#define S698PM_IRQ_HW_UNDEFINED_22 0x22
#define S698PM_IRQ_HW_UNDEFINED_23 0x23
#define S698PM_IRQ_CP_DISABLED 0x24
#define S698PM_IRQ_CP_DISABLED 0x24
#define S698PM_IRQ_HW_UNDEFINED_25 0x25
#define S698PM_IRQ_HW_UNDEFINED_26 0x26
#define S698PM_IRQ_HW_UNDEFINED_27 0x27
#define S698PM_IRQ_HW_UNDEFINED_25 0x25
#define S698PM_IRQ_HW_UNDEFINED_26 0x26
#define S698PM_IRQ_HW_UNDEFINED_27 0x27
#define S698PM_IRQ_CP_EXCEPTION 0x28
#define S698PM_IRQ_CP_EXCEPTION 0x28
#define S698PM_IRQ_HW_UNDEFINED_29 0x29
#define S698PM_IRQ_HW_UNDEFINED_7F 0x7F
#define S698PM_IRQ_HW_UNDEFINED_29 0x29
#define S698PM_IRQ_HW_UNDEFINED_7F 0x7F
#define S698PM_IRQ_SW_SYSCALL_TA0 0x80
#define S698PM_IRQ_SW_UNDEFINED_81 0x81
#define S698PM_IRQ_SW_UNDEFINED_82 0x82
#define S698PM_IRQ_SW_SYSCALL_TA0 0x80
#define S698PM_IRQ_SW_UNDEFINED_81 0x81
#define S698PM_IRQ_SW_UNDEFINED_82 0x82
#define S698PM_IRQ_SW_FLUSH_WINDOWS 0x83
#define S698PM_IRQ_SW_UNDEFINED_84 0x84
#define S698PM_IRQ_SW_UNDEFINED_85 0x85
#define S698PM_IRQ_SW_UNDEFINED_86 0x86
#define S698PM_IRQ_SW_UNDEFINED_87 0x87
#define S698PM_IRQ_SW_SYSCALL_TA8 0x88
#define S698PM_IRQ_SW_UNDEFINED_84 0x84
#define S698PM_IRQ_SW_UNDEFINED_85 0x85
#define S698PM_IRQ_SW_UNDEFINED_86 0x86
#define S698PM_IRQ_SW_UNDEFINED_87 0x87
#define S698PM_IRQ_SW_SYSCALL_TA8 0x88
#define S698PM_IRQ_SW_SYSCALL_IRQDIS 0x89
#define S698PM_IRQ_SW_SYSCALL_IRQEN 0x8A
#define S698PM_IRQ_SW_UNDEFINED_8B 0x8B
#define S698PM_IRQ_SW_UNDEFINED_FF 0xFF
#define S698PM_IRQ_SW_UNDEFINED_8B 0x8B
#define S698PM_IRQ_SW_UNDEFINED_FF 0xFF
#define S698PM_IRQ_LAST 0xFF
@ -158,7 +158,7 @@
#define S698PM_IRQ_UART_4_RX_TX 0x10E
#define S698PM_IRQ_L2CACHE 0x10F
#define NR_IRQS 272
#define NR_IRQS 272
#define S698PM_EXTENDED_IRQ 11
#define S698PM_IPI_VECTOR 14
#define S698PM_IPI_IRQ S698PM_IRQ_EXTERNAL_14

2
arch/sparc/src/bm3803/bm3803-timerisr.c
View file

@ -56,7 +56,7 @@
#define TIMCTR_ENABLE_COUNTER (1 << 0)
/* Bit 1: automatically reloaded with the reload value after each underflow */
#define TIMCTR_AUTO_RELOAD (1 << 1)
#define TIMCTR_AUTO_RELOAD (1 << 1)
/* Bit 2: Set 1, will load the timer reload register into the timer counter
* register

16
arch/sparc/src/bm3823/bm3823-uart.h
View file

@ -69,9 +69,9 @@
/* Register Bit-Field Definitions *******************************************/
#define ODD 1
#define ODD 1
#define EVEN 0
#define ON 1
#define ON 1
#define OFF 0
#define NONE 2
#define RX 0
@ -111,7 +111,7 @@
#define UART_BRG_MASK 0xfff
#define uart1_set_baudrate(baudrate) (EXTER_REG.uart_scaler1 = (uint32_t)((((BOARD_PERIPH_CLOCK*10)/(baudrate * 8))-5)/10))
#define uart1_set_baudrate(baudrate) (EXTER_REG.uart_scaler1 = (uint32_t)((((BOARD_PERIPH_CLOCK*10)/(baudrate * 8))-5)/10))
#define uart1_parity_config(uart_parity) ( uart_parity == ODD \
? (EXTER_REG.uart_ctrl1 = ((EXTER_REG.uart_ctrl1 | MSK_UART_PAR) | MSK_UART_ENABLE_PAR)) \
@ -137,11 +137,11 @@
#define uart1_tx_ready() ((EXTER_REG.uart_status1 & MSK_UART_TXH_READY) == MSK_UART_TXH_READY )
#define uart1_rx_ready() ((EXTER_REG.uart_status1 & MSK_UART_DATA_READY) == MSK_UART_DATA_READY)
#define uart1_send_byte(ch) (EXTER_REG.uart_data1 = ch)
#define uart1_send_byte(ch) (EXTER_REG.uart_data1 = ch)
/****************************************************************************/
#define uart2_set_baudrate(baudrate) (EXTER_REG.uart_scaler2 = (((BOARD_PERIPH_CLOCK*10)/(baudrate*8))-5)/10)
#define uart2_set_baudrate(baudrate) (EXTER_REG.uart_scaler2 = (((BOARD_PERIPH_CLOCK*10)/(baudrate*8))-5)/10)
#define uart2_parity_config(uart_parity) ( uart_parity == ODD \
? (EXTER_REG.uart_ctrl2 = ((EXTER_REG.uart_ctrl2 | MSK_UART_PAR) | MSK_UART_ENABLE_PAR)) \
@ -167,11 +167,11 @@
#define uart2_tx_ready() ((EXTER_REG.uart_status2 & MSK_UART_TXH_READY) == MSK_UART_TXH_READY )
#define uart2_rx_ready() ((EXTER_REG.uart_status2 & MSK_UART_DATA_READY) == MSK_UART_DATA_READY)
#define uart2_send_byte(ch) (EXTER_REG.uart_data2 = ch)
#define uart2_send_byte(ch) (EXTER_REG.uart_data2 = ch)
/****************************************************************************/
#define uart3_set_baudrate(baudrate) (BM3823_REG.uart_scaler3 = (((BOARD_PERIPH_CLOCK*10)/(baudrate*8))-5)/10)
#define uart3_set_baudrate(baudrate) (BM3823_REG.uart_scaler3 = (((BOARD_PERIPH_CLOCK*10)/(baudrate*8))-5)/10)
#define uart3_parity_config(uart_parity) ( uart_parity == ODD \
? (BM3823_REG.uart_ctrl3 = ((BM3823_REG.uart_ctrl3 | MSK_UART_PAR) | MSK_UART_ENABLE_PAR)) \
@ -197,7 +197,7 @@
#define uart3_tx_ready() ((BM3823_REG.uart_status3 & MSK_UART_TXH_READY) == MSK_UART_TXH_READY )
#define uart3_rx_ready() ((BM3823_REG.uart_status3 & MSK_UART_DATA_READY) == MSK_UART_DATA_READY)
#define uart3_send_byte(ch) (BM3823_REG.uart_data3 = ch)
#define uart3_send_byte(ch) (BM3823_REG.uart_data3 = ch)
/****************************************************************************
* Public Types

2
arch/sparc/src/s698pm/s698pm-timerisr.c
View file

@ -61,7 +61,7 @@
/* Bit 1: automatically reloaded with the reload value after each underflow */
#define TIMCTR_AUTO_RELOAD (1 << 1)
#define TIMCTR_AUTO_RELOAD (1 << 1)
/* Bit 2: Set 1, will load the timer reload register into the timer counter
* register

6
arch/sparc/src/s698pm/s698pm-uart.h
View file

@ -75,9 +75,9 @@
/* Register Bit-Field Definitions *******************************************/
#define ODD 1
#define ODD 1
#define EVEN 0
#define ON 1
#define ON 1
#define OFF 0
#define NONE 2
#define RX 0
@ -125,7 +125,7 @@
#define UART_BRG_MASK 0xfff
#define uart_set_baudrate(baudrate) ((uint32_t)((((BOARD_CPU_CLOCK*10)/(baudrate * 8))-5)/10))
#define uart_set_baudrate(baudrate) ((uint32_t)((((BOARD_CPU_CLOCK*10)/(baudrate * 8))-5)/10))
#define uart_parity_config(reg, uart_parity) ((uart_parity == ODD) ? \
(reg = ((reg | MSK_UART_PAR) | MSK_UART_ENABLE_PAR)) : \

2
boards/arm/samd5e5/metro-m4/src/metro-m4.h
View file

@ -55,7 +55,7 @@
#define PORT_RED_LED (PORT_OUTPUT | PORT_PULL_NONE | PORT_OUTPUT_SET | PORTA | PORT_PIN16)
#define PORT_D8 (PORT_OUTPUT | PORT_PULL_NONE | PORT_OUTPUT_SET | PORTA | PORT_PIN21)
#define PORT_D8 (PORT_OUTPUT | PORT_PULL_NONE | PORT_OUTPUT_SET | PORTA | PORT_PIN21)
#define PORT_D9 (PORT_INTERRUPT | PORT_PULL_NONE | PORT_INT_RISING | PORTA | PORT_PIN20)
#define PORT_D10 (PORT_INPUT | PORT_PULL_NONE | PORT_INT_CHANGE | PORTA | PORT_PIN18)