diff --git a/arch/arm/src/sam34/chip/sam4l_usart.h b/arch/arm/src/sam34/chip/sam4l_usart.h
index feaf4b48c54..08d2a8e746d 100644
--- a/arch/arm/src/sam34/chip/sam4l_usart.h
+++ b/arch/arm/src/sam34/chip/sam4l_usart.h
@@ -284,7 +284,6 @@
  * - Bits that provide interrupts with UART_INT_
  * - Bits unique to the USART status register begin with UART_SR_
  */
-
 #define UART_INT_RXRDY               (1 << 0)  /* Bit 0:  RXRDY Interrupt */
 #define UART_INT_TXRDY               (1 << 1)  /* Bit 1:  TXRDY Interrupt */
 #define UART_INT_RXBRK               (1 << 2)  /* Bit 2:  Break Received/End of Break */
@@ -318,6 +317,8 @@
 #define UART_INT_LINSTE              (1 << 30) /* Bit 30: LIN Sync Tolerance Error */
 #define UART_INT_LINHTE              (1 << 31) /* Bit 31: LIN Header Time-out Error */
 
+#define UART_INT_ALLINTS             0xff0ff7e7
+
 /* USART Receiver Holding Register */
 
 #define UART_RHR_RXCHR_SHIFT         (0)       /* Bits 0-8: Received Character */
diff --git a/arch/arm/src/sam34/sam4s_gpio.h b/arch/arm/src/sam34/sam4s_gpio.h
index 2d9fd8bb567..2217a164832 100644
--- a/arch/arm/src/sam34/sam4s_gpio.h
+++ b/arch/arm/src/sam34/sam4s_gpio.h
@@ -56,7 +56,7 @@
 
 /* 32-bit Encoding:
  *
- *   MMMC CCCC II.. VPPB BBBB
+ *   MMMC CCCC III. VPPB BBBB
  */
 
 /* Input/Output mode:
@@ -90,17 +90,22 @@
 
 /* Additional interrupt modes:
  *
- *   .... .... II.. .... ....
+ *   .... .... III. .... ....
  */
 
-#define GPIO_INT_SHIFT             (10)        /* Bits 10-11: GPIO interrupt bits */
-#define GPIO_INT_MASK              (3 << GPIO_INT_SHIFT)
-#  define GPIO_INT_LEVEL           (1 << 10)   /* Bit 10: Level detection interrupt */
-#  define GPIO_INT_EDGE            (0)         /*        (vs. Edge detection interrupt) */
-#  define GPIO_INT_HIGHLEVEL       (1 << 9)    /* Bit 9: High level detection interrupt */
-#  define GPIO_INT_LOWLEVEL        (0)         /*        (vs. Low level detection interrupt) */
-#  define GPIO_INT_RISING          (1 << 9)    /* Bit 9: Rising edge detection interrupt */
-#  define GPIO_INT_FALLING         (0)         /*        (vs. Falling edge detection interrupt) */
+#define GPIO_INT_SHIFT             (9)         /* Bits 9-11: GPIO interrupt bits */
+#define GPIO_INT_MASK              (7 << GPIO_INT_SHIFT)
+#  define _GIO_INT_AIM             (1 << 10)   /* Bit 10: Additional Interrupt modes */
+#  define _GPIO_INT_LEVEL          (1 << 9)    /* Bit 9: Level detection interrupt */
+#  define _GPIO_INT_EDGE           (0)         /*        (vs. Edge detection interrupt) */
+#  define _GPIO_INT_RH             (1 << 8)    /* Bit 9: Rising edge/High level detection interrupt */
+#  define _GPIO_INT_FL             (0)         /*        (vs. Falling edge/Low level detection interrupt) */
+
+#  define GPIO_INT_HIGHLEVEL       (_GIO_INT_AIM | _GPIO_INT_LEVEL | _GPIO_INT_RH)
+#  define GPIO_INT_LOWLEVEL        (_GIO_INT_AIM | _GPIO_INT_LEVEL | _GPIO_INT_FL)
+#  define GPIO_INT_RISING          (_GIO_INT_AIM | _GPIO_INT_EDGE  | _GPIO_INT_RH)
+#  define GPIO_INT_FALLING         (_GIO_INT_AIM | _GPIO_INT_EDGE  | _GPIO_INT_FL)
+#  define GPIO_INT_BOTHEDGES       (0)
 
 /* If the pin is an GPIO output, then this identifies the initial output value:
  *