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arch/arm/src/stm32: unify pulse count driver into common/stm32

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Merge the six near-identical pulse count drivers (two common, plus
the F7/H7/H5/L4 copies) into a single common/stm32/stm32_pulsecount.c.

Signed-off-by: raiden00pl <raiden00@railab.me>
This commit is contained in:
raiden00pl 2026-06-03 12:29:40 +02:00 • committed by Xiang Xiao
parent 30c5040547
commit d5b78ed9aa
25 changed files with 83 additions and 2012 deletions
Download patch file Download diff file Expand all files Collapse all files

3
.github/CODEOWNERS vendored
View file

@ -1820,9 +1820,8 @@ arch/arm/src/common/stm32/stm32_pminitialize_m3m4_v1.c alin.jerpelea@sony.com ju
arch/arm/src/common/stm32/stm32_pmsleep_m3m4_v1.c alin.jerpelea@sony.com juha.niskanen@haltian.com 59230071+hartmannathan@users.noreply.github.com raiden00@railab.me xiaoxiang@xiaomi.com
arch/arm/src/common/stm32/stm32_pmstandby_m3m4_v1.c alin.jerpelea@sony.com 59230071+hartmannathan@users.noreply.github.com raiden00@railab.me xiaoxiang@xiaomi.com
arch/arm/src/common/stm32/stm32_pmstop_m3m4_v1.c alin.jerpelea@sony.com xiaoxiang@xiaomi.com raiden00@railab.me
arch/arm/src/common/stm32/stm32_pulsecount.c raiden00@railab.me
arch/arm/src/common/stm32/stm32_pulsecount.h alin.jerpelea@sony.com raiden00@railab.me moura.fmo@gmail.com xiaoxiang@xiaomi.com
arch/arm/src/common/stm32/stm32_pulsecount_m0_v1.c raiden00@railab.me
arch/arm/src/common/stm32/stm32_pulsecount_m3m4_v1v2v3.c raiden00@railab.me
arch/arm/src/common/stm32/stm32_pwm.h alin.jerpelea@sony.com raiden00@railab.me
arch/arm/src/common/stm32/stm32_pwm_m0_v1.c paul-a.patience@polymtl.ca dev@ziggurat29.com dpo@certi.org.br raiden00@railab.me gvr@certi.org.br
arch/arm/src/common/stm32/stm32_pwm_m0_v1.h raiden00@railab.me dpo@certi.org.br alin.jerpelea@sony.com gvr@certi.org.br anchao@xiaomi.com

32
Documentation/guides/stm32_ports.rst
View file

@ -418,9 +418,9 @@ WWDG v1 arch/arm/src/common/stm32/stm32_wwdg_m3m4_v1.c
STM32L4
-------
============ ============ =========================================
============ ============ ============================================
Peripheral Core version Driver
============ ============ =========================================
============ ============ ============================================
ADC to be done arch/arm/src/stm32l4/stm32l4_adc.c
CAN/FDCAN bxCAN arch/arm/src/stm32l4/stm32l4_can.c
COMP to be done arch/arm/src/stm32l4/stm32l4_comp.c
@ -444,18 +444,18 @@ SPI/I2S to be done arch/arm/src/stm32l4/stm32l4_spi.c
TIM to be done arch/arm/src/stm32l4/stm32l4_tim.c
USART/LPUART v3 arch/arm/src/stm32l4/stm32l4_serial.c
USB OTG FS arch/arm/src/stm32l4/stm32l4_otgfsdev.c
PULSECOUNT n/a arch/arm/src/stm32l4/stm32l4_pulsecount.c
PULSECOUNT n/a arch/arm/src/common/stm32/stm32_pulsecount.c
PWM n/a arch/arm/src/stm32l4/stm32l4_pwm.c
QENCODER n/a arch/arm/src/stm32l4/stm32l4_qencoder.c
USB host n/a arch/arm/src/stm32l4/stm32l4_otgfshost.c
============ ============ =========================================
============ ============ ============================================
STM32F7
-------
============ ============ =======================================
============ ============ ============================================
Peripheral Core version Driver
============ ============ =======================================
============ ============ ============================================
ADC to be done arch/arm/src/stm32f7/stm32_adc.c
CAN/FDCAN bxCAN arch/arm/src/stm32f7/stm32_can.c
DAC to be done not supported
@ -483,12 +483,12 @@ WWDG v1 not supported
BBSRAM n/a arch/arm/src/stm32f7/stm32_bbsram.c
CAPTURE n/a arch/arm/src/stm32f7/stm32_capture.c
FOC n/a arch/arm/src/stm32f7/stm32_foc.c
PULSECOUNT n/a arch/arm/src/stm32f7/stm32_pulsecount.c
PULSECOUNT n/a arch/arm/src/common/stm32/stm32_pulsecount.c
PWM n/a arch/arm/src/stm32f7/stm32_pwm.c
QENCODER n/a arch/arm/src/stm32f7/stm32_qencoder.c
SAI n/a arch/arm/src/stm32f7/stm32_sai.c
USB host n/a arch/arm/src/stm32f7/stm32_otghost.c
============ ============ =======================================
============ ============ ============================================
STM32G0
-------
@ -522,9 +522,9 @@ WWDG v1 arch/arm/src/common/stm32/stm32_wwdg_m0_v1.c
STM32H5
-------
============ ============ =======================================
============ ============ ============================================
Peripheral Core version Driver
============ ============ =======================================
============ ============ ============================================
ADC to be done arch/arm/src/stm32h5/stm32_adc.c
AES/CRYP to be done not supported
CAN/FDCAN FDCAN arch/arm/src/stm32h5/stm32_fdcan.c
@ -544,18 +544,18 @@ SPI/I2S to be done arch/arm/src/stm32h5/stm32_spi.c
TIM to be done arch/arm/src/stm32h5/stm32_tim.c
USART/LPUART v3 arch/arm/src/stm32h5/stm32_serial.c
USB FS arch/arm/src/stm32h5/stm32_usbfs.c
PULSECOUNT n/a arch/arm/src/stm32h5/stm32_pulsecount.c
PULSECOUNT n/a arch/arm/src/common/stm32/stm32_pulsecount.c
PWM n/a arch/arm/src/stm32h5/stm32_pwm.c
RNG n/a arch/arm/src/stm32h5/stm32_rng.c
USB host n/a arch/arm/src/stm32h5/stm32_usbdrdhost.c
============ ============ =======================================
============ ============ ============================================
STM32H7
-------
============ ============ =======================================
============ ============ ============================================
Peripheral Core version Driver
============ ============ =======================================
============ ============ ============================================
ADC to be done arch/arm/src/stm32h7/stm32_adc.c
BDMA to be done arch/arm/src/stm32h7/stm32_dma.c
CAN/FDCAN FDCAN arch/arm/src/stm32h7/stm32_fdcan_sock.c
@ -587,11 +587,11 @@ AES/CRYP n/a arch/arm/src/stm32h7/stm32_aes.c
BBSRAM n/a arch/arm/src/stm32h7/stm32_bbsram.c
CAPTURE n/a arch/arm/src/stm32h7/stm32_capture.c
LPTIM n/a arch/arm/src/stm32h7/stm32_lptim.c
PULSECOUNT n/a arch/arm/src/stm32h7/stm32_pulsecount.c
PULSECOUNT n/a arch/arm/src/common/stm32/stm32_pulsecount.c
PWM n/a arch/arm/src/stm32h7/stm32_pwm.c
QENCODER n/a arch/arm/src/stm32h7/stm32_qencoder.c
USB host n/a arch/arm/src/stm32h7/stm32_otghost.c
============ ============ =======================================
============ ============ ============================================
STM32L0
-------

12
arch/arm/src/common/stm32/CMakeLists.txt
View file

@ -34,6 +34,10 @@ set(SRCS)
list(APPEND SRCS stm32_waste.c)
list(APPEND SRCS stm32_uid.c)
if(CONFIG_STM32_PULSECOUNT)
list(APPEND SRCS stm32_pulsecount.c)
endif()
if(CONFIG_STM32_COMMON_LEGACY)
list(
APPEND
@ -281,10 +285,6 @@ if(CONFIG_STM32_COMMON_LEGACY)
list(APPEND SRCS stm32_pwm_m3m4_v1v2v3.c)
endif()
if(CONFIG_STM32_PULSECOUNT)
list(APPEND SRCS stm32_pulsecount_m3m4_v1v2v3.c)
endif()
if(CONFIG_STM32_CAP)
list(APPEND SRCS stm32_capture_m3m4_v1_lowerhalf.c)
endif()
@ -444,10 +444,6 @@ if(CONFIG_ARCH_CORTEXM0)
list(APPEND SRCS stm32_pwm_m0_v1.c)
endif()
if(CONFIG_PULSECOUNT AND CONFIG_STM32_TIM1_PULSECOUNT)
list(APPEND SRCS stm32_pulsecount_m0_v1.c)
endif()
if(CONFIG_STM32_ADC AND CONFIG_STM32_HAVE_IP_ADC_M0_V1)
list(APPEND SRCS stm32_adc_m0_v1.c)
endif()

3
arch/arm/src/common/stm32/Kconfig.tim
View file

@ -2762,7 +2762,6 @@ config STM32_TIM1_PULSECOUNT_TDTS
int "TIM1 pulse count clock division"
default 0
range 0 2
depends on !STM32_HAVE_IP_TIMERS
config STM32_TIM1_PULSECOUNT_CHANNEL
int "TIM1 pulse count channel"
@ -2775,13 +2774,11 @@ config STM32_TIM1_PULSECOUNT_POL
int "TIM1 pulse count output polarity"
default 0
range 0 1
depends on !STM32_HAVE_IP_TIMERS
config STM32_TIM1_PULSECOUNT_IDLE
int "TIM1 pulse count idle state"
default 0
range 0 1
depends on !STM32_HAVE_IP_TIMERS
endif # STM32_TIM1_PULSECOUNT

14
arch/arm/src/common/stm32/Make.defs
View file

@ -42,6 +42,10 @@ ARCHXXINCLUDES += ${INCDIR_PREFIX}$(STM32_COMMON_SRCDIR)
CHIP_CSRCS += stm32_waste.c
CHIP_CSRCS += stm32_uid.c
ifeq ($(CONFIG_STM32_PULSECOUNT),y)
CHIP_CSRCS += stm32_pulsecount.c
endif
ifeq ($(CONFIG_STM32_COMMON_LEGACY),y)
CHIP_CSRCS += stm32_allocateheap_m3m4_v1.c
@ -314,10 +318,6 @@ ifeq ($(CONFIG_STM32_PWM),y)
CHIP_CSRCS += stm32_pwm_m3m4_v1v2v3.c
endif
ifeq ($(CONFIG_STM32_PULSECOUNT),y)
CHIP_CSRCS += stm32_pulsecount_m3m4_v1v2v3.c
endif
ifeq ($(CONFIG_STM32_CAP),y)
CHIP_CSRCS += stm32_capture_m3m4_v1_lowerhalf.c
endif
@ -495,12 +495,6 @@ ifeq ($(CONFIG_STM32_PWM),y)
CHIP_CSRCS += stm32_pwm_m0_v1.c
endif
ifeq ($(CONFIG_PULSECOUNT),y)
ifeq ($(CONFIG_STM32_TIM1_PULSECOUNT),y)
CHIP_CSRCS += stm32_pulsecount_m0_v1.c
endif
endif
ifeq ($(CONFIG_STM32_ADC)$(CONFIG_STM32_HAVE_IP_ADC_M0_V1),yy)
CHIP_CSRCS += stm32_adc_m0_v1.c
endif

62
arch/arm/src/stm32f7/stm32_pulsecount.c → arch/arm/src/common/stm32/stm32_pulsecount.c
View file

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/stm32f7/stm32_pulsecount.c
* arch/arm/src/common/stm32/stm32_pulsecount.c
*
* SPDX-License-Identifier: Apache-2.0
*
@ -39,9 +39,9 @@
#include "arm_internal.h"
#include "chip.h"
#include "stm32_pulsecount.h"
#include "stm32_rcc.h"
#include "stm32_gpio.h"
#include "stm32_tim.h"
#include "stm32.h"
/* Generalized pulse count support for all STM32 families */
/****************************************************************************
* Pre-processor Definitions
@ -70,9 +70,31 @@
#define TIMRCCRST_TIM8 STM32_RCC_APB2RSTR
#define TIMRST_TIM8 RCC_APB2RSTR_TIM8RST
/* The TIM1/TIM8 update-event interrupt vector is named differently across
* families. This will be unified later.
*/
#if defined(STM32_IRQ_TIM1UP)
# define PULSECOUNT_TIM1_IRQ STM32_IRQ_TIM1UP
#elif defined(STM32_IRQ_TIM1_UP)
# define PULSECOUNT_TIM1_IRQ STM32_IRQ_TIM1_UP
#elif defined(STM32_IRQ_TIM1_BRK)
# define PULSECOUNT_TIM1_IRQ STM32_IRQ_TIM1_BRK
#endif
#if defined(STM32_IRQ_TIM8UP)
# define PULSECOUNT_TIM8_IRQ STM32_IRQ_TIM8UP
#elif defined(STM32_IRQ_TIM8_UP)
# define PULSECOUNT_TIM8_IRQ STM32_IRQ_TIM8_UP
#endif
/* Default GPIO pins state */
#define PINCFG_DEFAULT (GPIO_INPUT | GPIO_FLOAT)
#if defined(CONFIG_STM32_STM32F10XX)
# define PINCFG_DEFAULT (GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT)
#else
# define PINCFG_DEFAULT (GPIO_INPUT | GPIO_FLOAT)
#endif
#define PULSECOUNT_POL_NEG 1
#define PULSECOUNT_IDLE_ACTIVE 1
@ -247,7 +269,7 @@ static struct stm32_tim_s g_pulsecount1dev =
.timid = 1,
.timtype = TIMTYPE_TIM1,
.t_dts = CONFIG_STM32_TIM1_PULSECOUNT_TDTS,
.irq = STM32_IRQ_TIM1UP,
.irq = PULSECOUNT_TIM1_IRQ,
.base = STM32_TIM1_BASE,
.pclk = TIMCLK_TIM1,
};
@ -298,7 +320,7 @@ static struct stm32_tim_s g_pulsecount8dev =
.timid = 8,
.timtype = TIMTYPE_TIM8,
.t_dts = CONFIG_STM32_TIM8_PULSECOUNT_TDTS,
.irq = STM32_IRQ_TIM8UP,
.irq = PULSECOUNT_TIM8_IRQ,
.base = STM32_TIM8_BASE,
.pclk = TIMCLK_TIM8,
};
@ -342,6 +364,11 @@ static bool pulsecount_reg_is_32bit(uint8_t timtype, uint32_t offset)
{
bool ret = false;
/* TODO: If all the advanced-timer registers are safely word-accessible
* then this helper could be dropped and every access made 32-bit.
* This is NOT verified yet.
*/
if (timtype == TIMTYPE_ADVANCED)
{
if (offset == STM32_ATIM_CR2_OFFSET ||
@ -807,10 +834,17 @@ static int pulsecount_channel_configure(struct pulsecount_lowerhalf_s *dev,
case 3:
{
ccmr &= ~(ATIM_CCMR1_CC1S_MASK | ATIM_CCMR1_OC1M_MASK |
ATIM_CCMR1_OC1PE | ATIM_CCMR1_OC1M);
ATIM_CCMR1_OC1PE);
ocmode |= (ATIM_CCMR_CCS_CCOUT << ATIM_CCMR1_CC1S_SHIFT);
ocmode |= (chanmode << ATIM_CCMR1_OC1M_SHIFT);
ocmode |= ATIM_CCMR1_OC1PE;
#ifdef ATIM_CCMR1_OC1M
/* Clear the extended (bit 3) output-compare-mode bit on the timer
* IP versions that have it.
*/
ccmr &= ~(ATIM_CCMR1_OC1M);
#endif
break;
}
@ -820,10 +854,17 @@ static int pulsecount_channel_configure(struct pulsecount_lowerhalf_s *dev,
case 4:
{
ccmr &= ~(ATIM_CCMR1_CC2S_MASK | ATIM_CCMR1_OC2M_MASK |
ATIM_CCMR1_OC2PE | ATIM_CCMR1_OC2M);
ATIM_CCMR1_OC2PE);
ocmode |= (ATIM_CCMR_CCS_CCOUT << ATIM_CCMR1_CC2S_SHIFT);
ocmode |= (chanmode << ATIM_CCMR1_OC2M_SHIFT);
ocmode |= ATIM_CCMR1_OC2PE;
#ifdef ATIM_CCMR1_OC2M
/* Clear the extended (bit 3) output-compare-mode bit on the timer
* IP versions that have it.
*/
ccmr &= ~(ATIM_CCMR1_OC2M);
#endif
break;
}
}
@ -1672,7 +1713,8 @@ static int pulsecount_start(struct pulsecount_lowerhalf_s *dev,
if (info->count > 0)
{
/* Only the advanced timers (TIM1,8 can support the pulse counting) */
/* Only the advanced timers (TIM1,8 can support the pulse counting)
*/
if (priv->timtype != TIMTYPE_ADVANCED)
{

1775
arch/arm/src/common/stm32/stm32_pulsecount_m3m4_v1v2v3.c
View file

File diff suppressed because it is too large Load diff

1
arch/arm/src/stm32c0/stm32.h
View file

@ -43,6 +43,7 @@
#include "stm32_pwr.h"
#include "stm32_rcc.h"
#include "stm32_spi.h"
#include "stm32_tim.h"
#include "stm32_uart.h"
#include "stm32_lowputc.h"
#include "stm32_adc.h"

1
arch/arm/src/stm32f0/stm32.h
View file

@ -43,6 +43,7 @@
#include "stm32_pwr.h"
#include "stm32_rcc.h"
#include "stm32_spi.h"
#include "stm32_tim.h"
#include "stm32_uart.h"
#include "stm32_lowputc.h"
#include "stm32_adc.h"

4
arch/arm/src/stm32f7/CMakeLists.txt
View file

@ -178,10 +178,6 @@ if(CONFIG_STM32_PWM)
list(APPEND SRCS stm32_pwm.c)
endif()
if(CONFIG_PULSECOUNT)
list(APPEND SRCS stm32_pulsecount.c)
endif()
if(CONFIG_STM32_FOC)
list(APPEND SRCS stm32_foc.c)
endif()

4
arch/arm/src/stm32f7/Make.defs
View file

@ -179,10 +179,6 @@ ifeq ($(CONFIG_STM32_PWM),y)
CHIP_CSRCS += stm32_pwm.c
endif
ifeq ($(CONFIG_STM32_PULSECOUNT),y)
CHIP_CSRCS += stm32_pulsecount.c
endif
ifeq ($(CONFIG_STM32_FOC),y)
CHIP_CSRCS += stm32_foc.c
endif

39
arch/arm/src/stm32f7/stm32_pulsecount.h
View file

@ -1,39 +0,0 @@
/****************************************************************************
* arch/arm/src/stm32f7/stm32_pulsecount.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F7_STM32_PULSECOUNT_H
#define __ARCH_ARM_SRC_STM32F7_STM32_PULSECOUNT_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/timers/pulsecount.h>
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
struct pulsecount_lowerhalf_s *stm32_pulsecountinitialize(int timer);
#endif /* __ARCH_ARM_SRC_STM32F7_STM32_PULSECOUNT_H */

1
arch/arm/src/stm32g0/stm32.h
View file

@ -43,6 +43,7 @@
#include "stm32_pwr.h"
#include "stm32_rcc.h"
#include "stm32_spi.h"
#include "stm32_tim.h"
#include "stm32_uart.h"
#include "stm32_lowputc.h"
#include "stm32_adc.h"

4
arch/arm/src/stm32h5/CMakeLists.txt
View file

@ -115,10 +115,6 @@ if(CONFIG_STM32_PWM)
list(APPEND SRCS stm32_pwm.c)
endif()
if(CONFIG_PULSECOUNT)
list(APPEND SRCS stm32_pulsecount.c)
endif()
# Required chip type specific files
if(CONFIG_STM32_STM32H5XXXX)

4
arch/arm/src/stm32h5/Make.defs
View file

@ -112,10 +112,6 @@ ifeq ($(CONFIG_STM32_PWM),y)
CHIP_CSRCS += stm32_pwm.c
endif
ifeq ($(CONFIG_STM32_PULSECOUNT),y)
CHIP_CSRCS += stm32_pulsecount.c
endif
# Required chip type specific files
ifeq ($(CONFIG_STM32_STM32H5XXXX),y)

1
arch/arm/src/stm32h5/stm32.h
View file

@ -47,6 +47,7 @@
#include "stm32_lowputc.h"
#include "stm32_pwr.h"
#include "stm32_rcc.h"
#include "stm32_tim.h"
#include "stm32_uart.h"
#include "stm32_usbfs.h"

39
arch/arm/src/stm32h5/stm32_pulsecount.h
View file

@ -1,39 +0,0 @@
/****************************************************************************
* arch/arm/src/stm32h5/stm32_pulsecount.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32H5_STM32_PULSECOUNT_H
#define __ARCH_ARM_SRC_STM32H5_STM32_PULSECOUNT_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/timers/pulsecount.h>
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
struct pulsecount_lowerhalf_s *stm32_pulsecountinitialize(int timer);
#endif /* __ARCH_ARM_SRC_STM32H5_STM32_PULSECOUNT_H */

4
arch/arm/src/stm32h7/CMakeLists.txt
View file

@ -184,10 +184,6 @@ if(CONFIG_STM32_PWM)
list(APPEND SRCS stm32_pwm.c)
endif()
if(CONFIG_PULSECOUNT)
list(APPEND SRCS stm32_pulsecount.c)
endif()
if(CONFIG_STM32_ETHMAC)
list(APPEND SRCS stm32_ethernet.c)
endif()

4
arch/arm/src/stm32h7/Make.defs
View file

@ -183,10 +183,6 @@ ifeq ($(CONFIG_STM32_PWM),y)
CHIP_CSRCS += stm32_pwm.c
endif
ifeq ($(CONFIG_STM32_PULSECOUNT),y)
CHIP_CSRCS += stm32_pulsecount.c
endif
ifeq ($(CONFIG_STM32_ETHMAC),y)
CHIP_CSRCS += stm32_ethernet.c
endif

1
arch/arm/src/stm32h7/stm32.h
View file

@ -43,6 +43,7 @@
#include "stm32_i2c.h"
#include "stm32_spi.h"
#include "stm32_rcc.h"
#include "stm32_tim.h"
#include "stm32_lowputc.h"
#endif /* __ARCH_ARM_SRC_STM32H7_STM32_H */

39
arch/arm/src/stm32h7/stm32_pulsecount.h
View file

@ -1,39 +0,0 @@
/****************************************************************************
* arch/arm/src/stm32h7/stm32_pulsecount.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32H7_STM32_PULSECOUNT_H
#define __ARCH_ARM_SRC_STM32H7_STM32_PULSECOUNT_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/timers/pulsecount.h>
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
struct pulsecount_lowerhalf_s *stm32_pulsecountinitialize(int timer);
#endif /* __ARCH_ARM_SRC_STM32H7_STM32_PULSECOUNT_H */

1
arch/arm/src/stm32l0/stm32.h
View file

@ -43,6 +43,7 @@
#include "stm32_pwr.h"
#include "stm32_rcc.h"
#include "stm32_spi.h"
#include "stm32_tim.h"
#include "stm32_uart.h"
#include "stm32_lowputc.h"
#include "stm32_adc.h"

4
arch/arm/src/stm32l4/CMakeLists.txt
View file

@ -162,10 +162,6 @@ if(CONFIG_STM32_PWM)
list(APPEND SRCS stm32l4_pwm.c)
endif()
if(CONFIG_PULSECOUNT)
list(APPEND SRCS stm32l4_pulsecount.c)
endif()
if(CONFIG_SENSORS_QENCODER)
list(APPEND SRCS stm32l4_qencoder.c)
endif()

4
arch/arm/src/stm32l4/Make.defs
View file

@ -158,10 +158,6 @@ ifeq ($(CONFIG_STM32_PWM),y)
CHIP_CSRCS += stm32l4_pwm.c
endif
ifeq ($(CONFIG_STM32_PULSECOUNT),y)
CHIP_CSRCS += stm32l4_pulsecount.c
endif
ifeq ($(CONFIG_SENSORS_QENCODER),y)
CHIP_CSRCS += stm32l4_qencoder.c
endif

39
arch/arm/src/stm32l4/stm32l4_pulsecount.h
View file

@ -1,39 +0,0 @@
/****************************************************************************
* arch/arm/src/stm32l4/stm32l4_pulsecount.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32L4_STM32L4_PULSECOUNT_H
#define __ARCH_ARM_SRC_STM32L4_STM32L4_PULSECOUNT_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/timers/pulsecount.h>
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
struct pulsecount_lowerhalf_s *stm32_pulsecountinitialize(int timer);
#endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_PULSECOUNT_H */