From d3beea967d92bc4bf61678377412ebd3cc5d6712 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sun, 29 Mar 2015 14:42:03 -0600 Subject: [PATCH] Cortex-M7: Add support for enabled the D-Cache in write only mode. SAMV7 Ethernet: I- and D-Cache are now enabled in the netnsh/ configuration. D-Cache is enabled in write-though mode. This mode is necessary because the DMA descriptors are each 8-bytes in size but the D-Cache cache line is 32-bits in size. So it is impossible make coherency for every 8-byte DMA descriptor without write-through. --- arch/arm/src/samv7/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/src/samv7/Kconfig b/arch/arm/src/samv7/Kconfig index 41e40b5df17..08d8f7570cb 100644 --- a/arch/arm/src/samv7/Kconfig +++ b/arch/arm/src/samv7/Kconfig @@ -120,10 +120,10 @@ config SAMV7_EMAC select ARMV7M_DCACHE_WRITETHROUGH if ARMV7M_DCACHE ---help--- NOTE that write-through caching is automatically selected. This is - to work around issues with the RX and TX descriptors with are 8-bits + to work around issues with the RX and TX descriptors with are 8-bytes in size. But the D-Cache cache line size is 32-bytes. That means that you cannot reload, clean or invalidate a descriptor without also - effecting three neighboring desciptors. Setting write through mode + effecting three neighboring descriptors. Setting write through mode eliminates the need for cleaning. If only reloading and invalidating are done, then there is no problem.