diff --git a/arch/arm/src/stm32f7/Kconfig b/arch/arm/src/stm32f7/Kconfig index f8a5832319a..f08c2165093 100644 --- a/arch/arm/src/stm32f7/Kconfig +++ b/arch/arm/src/stm32f7/Kconfig @@ -4692,7 +4692,8 @@ config STM32F7_LTDC_BACKCOLOR default 0x0 ---help--- This is the background color that will be used as the LTDC - background layer color. It is an RGB888 format value. + background layer color. It is an RGB888 format value, + which gets written unmodified to register LTDC_BCCR. config STM32F7_LTDC_DITHER bool "Dither support" @@ -4817,6 +4818,15 @@ config FB_TRANSPARENCY ltdc L8 format. endif + +config STM32F7_LTDC_REGDEBUG + bool "Enable LTDC register value debug messages" + default n + ---help--- + This gives additional messages for LTDC related register values. + Additionally, you have to select "Low-level LCD Debug Features" + to enable the debug messages. + endmenu endif # STM32F7_LTDC diff --git a/arch/arm/src/stm32f7/chip/stm32_ltdc.h b/arch/arm/src/stm32f7/chip/stm32_ltdc.h index 38068183c5d..ca7e1cd715a 100755 --- a/arch/arm/src/stm32f7/chip/stm32_ltdc.h +++ b/arch/arm/src/stm32f7/chip/stm32_ltdc.h @@ -194,7 +194,7 @@ # define LTDC_GCR_DRW(n) ((uint32_t)(n) << LTDC_GCR_DRW_SHIFT) #define LTDC_GCR_DEN (1 << 16) /* Bit 16: Dither Enable */ #define LTDC_GCR_PCPOL (1 << 28) /* Bit 28: Pixel Clock Polarity */ -#define LTDC_GCR_DEPOL (1 << 29) /* Bit 29: Data Enable Polarity */ +#define LTDC_GCR_DEPOL (1 << 29) /* Bit 29: Not(Data Enable) Polarity */ #define LTDC_GCR_VSPOL (1 << 30) /* Bit 30: Vertical Sync Polarity */ #define LTDC_GCR_HSPOL (1 << 31) /* Bit 31: Horizontal Sync Polarity */ diff --git a/arch/arm/src/stm32f7/chip/stm32f74xx75xx_memorymap.h b/arch/arm/src/stm32f7/chip/stm32f74xx75xx_memorymap.h index fcf522327ad..89d5223845b 100644 --- a/arch/arm/src/stm32f7/chip/stm32f74xx75xx_memorymap.h +++ b/arch/arm/src/stm32f7/chip/stm32f74xx75xx_memorymap.h @@ -60,8 +60,8 @@ #define STM32_FMC_BASE34 0x80000000 /* 0x80000000-0x8fffffff: 512Mb FMC bank3&4 block */ # define STM32_FMC_BANK3 0x80000000 /* 0x80000000-0x8fffffff: 256Mb NAND FLASH */ # define STM32_FMC_BANK4 0x90000000 /* 0x90000000-0x9fffffff: 256Mb PC CARD */ -#define STM32_FMC_BASE5 0xc0000000 /* 0xc0000000-0xcfffffff: 256Mb FMC */ -#define STM32_FMC_BASE6 0xd0000000 /* 0xd0000000-0xdfffffff: 256Mb FMC */ +#define STM32_FMC_BASE5 0xc0000000 /* 0xc0000000-0xcfffffff: 256Mb FMC SDRAM Bank 1 */ +#define STM32_FMC_BASE6 0xd0000000 /* 0xd0000000-0xdfffffff: 256Mb FMC SDRAM Bank 2 */ #define STM32_CORTEX_BASE 0xe0000000 /* 0xe0000000-0xffffffff: 512Mb Cortex-M7 block */ #define STM32_REGION_MASK 0xf0000000 diff --git a/arch/arm/src/stm32f7/stm32_allocateheap.c b/arch/arm/src/stm32f7/stm32_allocateheap.c index eafadfe6697..bb80ffd7877 100644 --- a/arch/arm/src/stm32f7/stm32_allocateheap.c +++ b/arch/arm/src/stm32f7/stm32_allocateheap.c @@ -70,20 +70,21 @@ * CONFIG_RAM_END : End address (+1) of SRAM (F1 family only, the * : F4 family uses the a priori end of SRAM) * - * In addition to internal SRAM, SRAM may also be available through the FMC. - * In order to use FMC SRAM, the following additional things need to be + * In addition to internal SRAM, external RAM may also be available through the FMC. + * In order to use FMC RAM, the following additional things need to be * present in the NuttX configuration file: * - * CONFIG_STM32F7_FMC=y : Enables the FMC - * CONFIG_STM32F7_FMC_SRAM=y : Indicates that SRAM is available via the - * FMC (as opposed to an LCD or FLASH). - * CONFIG_HEAP2_BASE : The base address of the SRAM in the FMC - * address space - * CONFIG_HEAP2_SIZE : The size of the SRAM in the FMC - * address space - * CONFIG_MM_REGIONS : Must be set to a large enough value to - * include the FMC SRAM (as determined by - * the rules provided below) + * CONFIG_STM32F7_FMC=y : Enables the FMC + * CONFIG_STM32F7_FMC_S[D]RAM=y : SRAM and/or SDRAM is available via the FMC. + * Either of these autoselects CONFIG_ARCH_HAVE_HEAP2 + * which is what we are interested in here. + * CONFIG_HEAP2_BASE : The base address of the external RAM in the FMC + * address space + * CONFIG_HEAP2_SIZE : The size of the external RAM in the FMC + * address space + * CONFIG_MM_REGIONS : Must be set to a large enough value to + * include the FMC external RAM (as determined by + * the rules provided below) */ /* Set the start and end of SRAM1 and SRAM2 */ @@ -108,21 +109,31 @@ # undef HAVE_DTCM #endif -/* We can't possibly have FMC SRAM if the FMC is not enabled */ +/* We can't possibly have FMC external RAM if the FMC is not enabled */ #ifndef CONFIG_STM32F7_FMC -# undef CONFIG_STM32F7_FMC_SRAM +# ifdef CONFIG_ARCH_HAVE_HEAP2 +# error CONFIG_ARCH_HAVE_HEAP2 but not CONFIG_STM32F7_FMC! Kconfig flawed? +# endif +# undef CONFIG_ARCH_HAVE_HEAP2 #endif -/* If FMC SRAM is going to be used as heap, then verify that the starting +/* If FMC external RAM is going to be used as heap, then verify that the starting * address and size of the external SRAM region has been provided in the * configuration (as CONFIG_HEAP2_BASE and CONFIG_HEAP2_SIZE). */ -#ifdef CONFIG_STM32F7_FMC_SRAM +#ifdef CONFIG_ARCH_HAVE_HEAP2 # if !defined(CONFIG_HEAP2_BASE) || !defined(CONFIG_HEAP2_SIZE) # error CONFIG_HEAP2_BASE and CONFIG_HEAP2_SIZE must be provided -# undef CONFIG_STM32F7_FMC_SRAM +# undef CONFIG_ARCH_HAVE_HEAP2 +# endif +#endif + +#ifdef CONFIG_ARCH_HAVE_HEAP2 +# if CONFIG_HEAP2_BASE == 0 || CONFIG_HEAP2_SIZE == 0 +# warning "CONFIG_HEAP2_BASE or CONFIG_HEAP2_SIZE are zero. No HEAP2 enabled!" +# undef CONFIG_ARCH_HAVE_HEAP2 # endif #endif @@ -130,21 +141,21 @@ * * Configuration 1. System SRAM1 (only) * CONFIG_MM_REGIONS == 1 - * CONFIG_STM32F7_FMC_SRAM NOT defined + * CONFIG_ARCH_HAVE_HEAP2 NOT defined * Configuration 2. System SRAM1 and SRAM2 * CONFIG_MM_REGIONS == 2 - * CONFIG_STM32F7_FMC_SRAM NOT defined + * CONFIG_ARCH_HAVE_HEAP2 NOT defined * Configuration 3. System SRAM1 and SRAM2 and DTCM * CONFIG_MM_REGIONS == 3 - * CONFIG_STM32F7_FMC_SRAM undefined + * CONFIG_ARCH_HAVE_HEAP2 undefined * HAVE_DTCM defined - * Configuration 4. System SRAM1 and SRAM2 and FMC SRAM + * Configuration 4. System SRAM1 and SRAM2 and FMC RAM * CONFIG_MM_REGIONS == 3 - * CONFIG_STM32F7_FMC_SRAM defined + * CONFIG_ARCH_HAVE_HEAP2 defined * HAVE_DTCM undefined - * Configuration 5. System SRAM1 and SRAM2 and DTCM and FMC SRAM + * Configuration 5. System SRAM1 and SRAM2 and DTCM and FMC RAM * CONFIG_MM_REGIONS == 4 - * CONFIG_STM32F7_FMC_SRAM defined + * CONFIG_ARCH_HAVE_HEAP2 defined * HAVE_DTCM defined * * Let's make sure that all definitions are consistent before doing @@ -152,9 +163,9 @@ */ #if CONFIG_MM_REGIONS < 2 -# ifdef CONFIG_STM32F7_FMC_SRAM -# warning "FMC SRAM excluded from the heap" -# undef CONFIG_STM32F7_FMC_SRAM +# ifdef CONFIG_ARCH_HAVE_HEAP2 +# warning "FMC external RAM excluded from the heap" +# undef CONFIG_ARCH_HAVE_HEAP2 # endif # ifdef HAVE_DTCM # warning "DTCM excluded from the heap" @@ -162,29 +173,29 @@ # endif # warning "SRAM2 excluded from the heap" #elif CONFIG_MM_REGIONS < 3 -# ifdef CONFIG_STM32F7_FMC_SRAM -# warning "FMC SRAM excluded from the heap" -# undef CONFIG_STM32F7_FMC_SRAM +# ifdef CONFIG_ARCH_HAVE_HEAP2 +# warning "FMC external RAM excluded from the heap" +# undef CONFIG_ARCH_HAVE_HEAP2 # endif # ifdef HAVE_DTCM # warning "DTCM excluded from the heap" # undef HAVE_DTCM # endif #elif CONFIG_MM_REGIONS < 4 -# if defined(CONFIG_STM32F7_FMC_SRAM) && defined(HAVE_DTCM) -# warning "CONFIG_MM_REGIONS == 3 but have both FMC SRAM and DTCM. DTCM excluded from the heap." +# if defined(CONFIG_ARCH_HAVE_HEAP2) && defined(HAVE_DTCM) +# warning "CONFIG_MM_REGIONS == 3 but have both FMC external RAM and DTCM. DTCM excluded from the heap." # undef HAVE_DTCM -# elif !defined(CONFIG_STM32F7_FMC_SRAM) && !defined(HAVE_DTCM) +# elif !defined(CONFIG_ARCH_HAVE_HEAP2) && !defined(HAVE_DTCM) # error "CONFIG_MM_REGIONS == 3 but I do not know what some of the region(s) are" # undef CONFIG_MM_REGIONS # define CONFIG_MM_REGIONS 2 # endif #elif CONFIG_MM_REGIONS < 5 -# if !defined(CONFIG_STM32F7_FMC_SRAM) && !defined(HAVE_DTCM) +# if !defined(CONFIG_ARCH_HAVE_HEAP2) && !defined(HAVE_DTCM) # error "CONFIG_MM_REGIONS == 4 but I do not know what some of the region(s) are" # undef CONFIG_MM_REGIONS # define CONFIG_MM_REGIONS 2 -# elif !defined(CONFIG_STM32F7_FMC_SRAM) || !defined(HAVE_DTCM) +# elif !defined(CONFIG_ARCH_HAVE_HEAP2) || !defined(HAVE_DTCM) # error "CONFIG_MM_REGIONS == 4 but I do not know what some of the region(s) are" # undef CONFIG_MM_REGIONS # define CONFIG_MM_REGIONS 3 @@ -192,9 +203,9 @@ #else # error "CONFIG_MM_REGIONS > 4 but I do not know what some of the region(s) are" # undef CONFIG_MM_REGIONS -# if defined(CONFIG_STM32F7_FMC_SRAM) && defined(HAVE_DTCM) +# if defined(CONFIG_ARCH_HAVE_HEAP2) && defined(HAVE_DTCM) # define CONFIG_MM_REGIONS 4 -# elif defined(CONFIG_STM32F7_FMC_SRAM) || defined(HAVE_DTCM) +# elif defined(CONFIG_ARCH_HAVE_HEAP2) || defined(HAVE_DTCM) # define CONFIG_MM_REGIONS 3 # else # define CONFIG_MM_REGIONS 2 @@ -405,10 +416,10 @@ void up_addregion(void) kumm_addregion((FAR void *)DTCM_START, DTCM_END-DTCM_START); #endif -#ifdef CONFIG_STM32F7_FMC_SRAM +#ifdef CONFIG_ARCH_HAVE_HEAP2 #if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP) - /* Allow user-mode access to the FMC SRAM user heap memory */ + /* Allow user-mode access to the FMC RAM user heap memory */ stm32_mpu_uheap((uintptr_t)CONFIG_HEAP2_BASE, CONFIG_HEAP2_SIZE); @@ -418,7 +429,7 @@ void up_addregion(void) up_heap_color((FAR void *)CONFIG_HEAP2_BASE, CONFIG_HEAP2_SIZE); - /* Add the external FMC SRAM user heap region. */ + /* Add the external FMC RAM user heap region. */ kumm_addregion((FAR void *)CONFIG_HEAP2_BASE, CONFIG_HEAP2_SIZE); #endif diff --git a/arch/arm/src/stm32f7/stm32_ltdc.c b/arch/arm/src/stm32f7/stm32_ltdc.c index 36c1d628f61..fdd5a6a9470 100644 --- a/arch/arm/src/stm32f7/stm32_ltdc.c +++ b/arch/arm/src/stm32f7/stm32_ltdc.c @@ -111,33 +111,22 @@ #define STM32_LTDC_AWCR_AAW LTDC_AWCR_AAW(STM32_LTDC_LxWHPCR_WHSPPOS) /* LTDC_TWCR register */ - -#define STM32_LTDC_TWCR_TOTALH LTDC_TWCR_TOTALH(BOARD_LTDC_VSYNC + \ - BOARD_LTDC_VBP + \ - STM32_LTDC_HEIGHT + BOARD_LTDC_VFP - 1) +#define STM32_LTDC_TOTALHEIGHT (BOARD_LTDC_VSYNC + \ + BOARD_LTDC_VBP + \ + STM32_LTDC_HEIGHT + BOARD_LTDC_VFP - 1) +#define STM32_LTDC_TWCR_TOTALH LTDC_TWCR_TOTALH(STM32_LTDC_TOTALHEIGHT) #define STM32_LTDC_TWCR_TOTALW LTDC_TWCR_TOTALW(BOARD_LTDC_HSYNC + \ BOARD_LTDC_HBP + \ STM32_LTDC_WIDTH + BOARD_LTDC_HFP - 1) -/* Global GCR register */ - -/* Synchronisation and Polarity */ - +/* Global GCR register: Synchronisation Polarity */ #define STM32_LTDC_GCR_PCPOL BOARD_LTDC_GCR_PCPOL #define STM32_LTDC_GCR_DEPOL BOARD_LTDC_GCR_DEPOL #define STM32_LTDC_GCR_VSPOL BOARD_LTDC_GCR_VSPOL #define STM32_LTDC_GCR_HSPOL BOARD_LTDC_GCR_HSPOL -/* Dither */ - -#define STM32_LTDC_GCR_DEN BOARD_LTDC_GCR_DEN -#define STM32_LTDC_GCR_DBW LTDC_GCR_GBW(BOARD_LTDC_GCR_DBW) -#define STM32_LTDC_GCR_DGW LTDC_GCR_DGW(BOARD_LTDC_GCR_DGW) -#define STN32_LTDC_GCR_DRW LTDC_GCR_DBW(BOARD_LTDC_GCR_DRW) - /* LIPCR register */ - -#define STM32_LTDC_LIPCR_LIPOS LTDC_LIPCR_LIPOS(STM32_LTDC_TWCR_TOTALW) +#define STM32_LTDC_LIPCR_LIPOS LTDC_LIPCR_LIPOS(STM32_LTDC_TOTALHEIGHT) /* Configuration ************************************************************/ @@ -974,17 +963,15 @@ static void stm32_ltdc_periphconfig(void) stm32_ltdc_gpioconfig(); #endif - /* Configure APB2 LTDC clock external */ - + /* APB2 LTDC clock is expected to be externally preconfigured */ reginfo("configured RCC_APB2ENR=%08x\n", getreg32(STM32_RCC_APB2ENR)); - /* Configure the SAI PLL external to provide the LCD_CLK */ - + /* SAI PLL is expected to be externally preconfigured to provide the LCD_CLK */ reginfo("configured RCC_PLLSAI=%08x\n", getreg32(STM32_RCC_PLLSAICFGR)); - /* Configure dedicated clock external */ - - reginfo("configured RCC_DCKCFGR=%08x\n", getreg32(STM32_RCC_DCKCFGR)); + /* Dedicated clocks are expected to be externally preconfigured */ + reginfo("configured RCC_DCKCFGR1=%08x\n", getreg32(STM32_RCC_DCKCFGR1)); + reginfo("configured RCC_DCKCFGR2=%08x\n", getreg32(STM32_RCC_DCKCFGR2)); /* Configure LTDC_SSCR */ @@ -1014,9 +1001,10 @@ static void stm32_ltdc_periphconfig(void) putreg32(regval, STM32_LTDC_TWCR); reginfo("configured LTDC_TWCR=%08x\n", getreg32(STM32_LTDC_TWCR)); - /* Configure LTDC_GCR */ - - regval = (STM32_LTDC_GCR_PCPOL | STM32_LTDC_GCR_DEPOL + /* Configure signal polarities */ + regval = getreg32(STM32_LTDC_GCR); + regval &= ~(LTDC_GCR_PCPOL | LTDC_GCR_DEPOL | LTDC_GCR_VSPOL | LTDC_GCR_HSPOL); + regval |= (STM32_LTDC_GCR_PCPOL | STM32_LTDC_GCR_DEPOL | STM32_LTDC_GCR_VSPOL | STM32_LTDC_GCR_HSPOL); reginfo("set LTDC_GCR=%08x\n", regval); putreg32(regval, STM32_LTDC_GCR); @@ -1073,8 +1061,7 @@ static void stm32_ltdc_dither(bool enable, regval &= ~LTDC_GCR_DEN; } - regval &= ~(!LTDC_GCR_DEN | LTDC_GCR_DRW(0) | - LTDC_GCR_DGW(0) | LTDC_GCR_DBW(0)); + regval &= ~(LTDC_GCR_DBW_MASK | LTDC_GCR_DGW_MASK | LTDC_GCR_DRW_MASK); regval |= (LTDC_GCR_DRW(red) | LTDC_GCR_DGW(green) | LTDC_GCR_DBW(blue)); reginfo("set LTDC_GCR=%08x\n", regval); @@ -3441,6 +3428,21 @@ FAR struct ltdc_layer_s *stm32_ltdcgetlayer(int lid) } #endif /* CONFIG_STM32F7_LTDC_INTERFACE */ + +/**************************************************************************** + * Name: stm32_ltdcreset + * + * Description: + * Reset LTDC via APB2RSTR + * + * + ****************************************************************************/ +void stm32_ltdcreset(void) +{ + *((uint32_t *)(STM32_RCC_APB2RSTR)) |= RCC_APB2RSTR_LTDCRST; + *((uint32_t *)(STM32_RCC_APB2RSTR)) &= ~RCC_APB2RSTR_LTDCRST; +} + /**************************************************************************** * Name: stm32_ltdcinitialize * diff --git a/arch/arm/src/stm32f7/stm32_ltdc.h b/arch/arm/src/stm32f7/stm32_ltdc.h old mode 100755 new mode 100644 index c0e46986363..ea6821ec5b3 --- a/arch/arm/src/stm32f7/stm32_ltdc.h +++ b/arch/arm/src/stm32f7/stm32_ltdc.h @@ -106,9 +106,29 @@ struct stm32_ltdc_s * include/nuttx/video/fb.h. */ -int stm32_ltdcinitialize(void); +/**************************************************************************** + * Name: stm32_ltdcreset + * + * Description: + * Reset LTDC via APB2RSTR + * + * + ****************************************************************************/ +void stm32_ltdcreset(void); + +/**************************************************************************** + * Name: stm32_ltdcinitialize + * + * Description: + * Initialize the ltdc controller + * + * Return: + * OK + * + ****************************************************************************/ +int stm32_ltdcinitialize(void); FAR struct fb_vtable_s *stm32_ltdcgetvplane(int vplane); -void stm32_ltdcuninitialize(void); +void stm32_ltdcuninitialize(void); /************************************************************************************ * Name: stm32_ltdcgetlayer diff --git a/arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c b/arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c index 682523f789f..25f8c33e9b6 100644 --- a/arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c +++ b/arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c @@ -644,6 +644,12 @@ static inline void rcc_enableapb2(void) regval |= RCC_APB2ENR_LTDCEN; #endif +#ifdef CONFIG_STM32F7_DSIHOST + /* LTDC clock enable */ + + regval |= RCC_APB2ENR_DSIEN; +#endif + putreg32(regval, STM32_RCC_APB2ENR); /* Enable peripherals */ } @@ -877,7 +883,7 @@ static void stm32_stdclockconfig(void) { } #endif -#if defined(CONFIG_STM32F7_LTDC) || defined(CONFIG_STM32F7_PLLI2S) +#if defined(CONFIG_STM32F7_PLLI2S) || (STM32_RCC_DCKCFGR1_SAI1SRC == RCC_DCKCFGR1_SAI1SEL(1)) || (STM32_RCC_DCKCFGR1_SAI2SRC == RCC_DCKCFGR1_SAI2SEL(1)) /* Configure PLLI2S */ @@ -892,6 +898,19 @@ static void stm32_stdclockconfig(void) | STM32_RCC_PLLSAICFGR_PLLSAIR); putreg32(regval, STM32_RCC_PLLI2SCFGR); + /* Enable PLLI2S */ + + regval = getreg32(STM32_RCC_CR); + regval |= RCC_CR_PLLI2SON; + putreg32(regval, STM32_RCC_CR); + + /* Wait until the PLLI2S is ready */ + + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLI2SRDY) == 0) + { + } +#endif + regval = getreg32(STM32_RCC_DCKCFGR2); regval &= ~( RCC_DCKCFGR2_USART1SEL_MASK | RCC_DCKCFGR2_USART2SEL_MASK @@ -931,19 +950,6 @@ static void stm32_stdclockconfig(void) putreg32(regval, STM32_RCC_DCKCFGR2); - /* Enable PLLI2S */ - - regval = getreg32(STM32_RCC_CR); - regval |= RCC_CR_PLLI2SON; - putreg32(regval, STM32_RCC_CR); - - /* Wait until the PLLI2S is ready */ - - while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLI2SRDY) == 0) - { - } -#endif - #if defined(CONFIG_STM32F7_IWDG) || defined(CONFIG_STM32F7_RTC_LSICLOCK) /* Low speed internal clock source LSI */