From cbdcb2deed2b2437bf47d49960d5d02e299f2ecc Mon Sep 17 00:00:00 2001 From: Juha Niskanen Date: Tue, 14 Aug 2018 06:57:06 -0600 Subject: [PATCH] configs/stm32l4r9ai-disco: Fix HSE clock config and clock board to maximum 120 MHz --- configs/stm32l4r9ai-disco/README.txt | 203 ++++-------------- configs/stm32l4r9ai-disco/include/board.h | 41 +--- .../include/stm32l4r9ai-disco-clocking.h | 133 +++++++----- configs/stm32l4r9ai-disco/nsh/defconfig | 2 +- 4 files changed, 124 insertions(+), 255 deletions(-) diff --git a/configs/stm32l4r9ai-disco/README.txt b/configs/stm32l4r9ai-disco/README.txt index ae8eb766c9f..b8b252b24cf 100644 --- a/configs/stm32l4r9ai-disco/README.txt +++ b/configs/stm32l4r9ai-disco/README.txt @@ -11,11 +11,13 @@ STM32L4R9AI: Microprocessor: 32-bit ARM Cortex M4 at 120MHz STM32L4R9AI Memory: 2048 KB Flash and 192+64+384 KB SRAM - ADC: 1x12-bit, 2.4 MSPS A/D converter: up to 24 channels + ADC: 1x12-bit, 5 MSPS A/D converter: up to 14 external channels + DAC: 2 channels + DFSDM: 4 filters, 8 channels DMA: 16-stream DMA controllers with FIFOs and burst support Timers: Up to 11 timers: up to eight 16-bit, two 32-bit timers, two watchdog timers, and a SysTick timer - GPIO: Up to 51 I/O ports with interrupt capability + GPIO: Up to 131 I/O ports with interrupt capability I2C: Up to 4 x I2C interfaces USARTs: Up to 3 USARTs, 2 UARTs, 1 LPUART SPIs: Up to 3 SPIs @@ -23,23 +25,21 @@ STM32L4R9AI: CAN interface SDIO interface OCTOSPI interface + Camera interface USB: USB 2.0 full-speed device/host/OTG controller with on-chip PHY CRC calculation unit RTC Board features: - Peripherals: 2 led, 1 d-pad joystick, 2 x LED, LCD, USC OTG FS, SAI stereo - Digital Microphone, MEMS Accelerometer, Magnetometer, - Gyroscope, 512 Mbit OCTOSPI Flash, current ammeter + Peripherals: 1 d-pad joystick, 2 x LED, AMOLED display, USC OTG FS, + 2 x MEMS Digital Microphones, SAI codec, 16 Mbit PSRAM, + 512 Mbit OCTOSPI Flash, current ammeter Debug: Serial wire debug and JTAG interfaces Uses a STM32F103 to provide a ST-Link for programming, debug similar to the OpenOcd FTDI function - USB to JTAG front-end. - See http://mbed.org/platforms/ST-Nucleo-L476RG for more - information about these boards. - Contents ======== @@ -56,39 +56,22 @@ Contents mbed ==== - The Nucleo-F401RE includes boot loader from mbed: + The STM32L4R9AI-DISCO includes boot loader from mbed: - https://mbed.org/platforms/ST-Nucleo-F401RE/ https://mbed.org/handbook/Homepage Using the mbed loader: - 1. Connect the Nucleo-F4x1RE to the host PC using the USB connector. - 2. A new file system will appear called NUCLEO; open it with Windows + 1. Connect the board to the host PC using the USB connector. + 2. A new file system will appear called DIS_L4R9AI; open it with Windows Explorer (assuming that you are using Windows). 3. Drag and drop nuttx.bin into the MBED window. This will load the - nuttx.bin binary into the Nucleo-F4x1RE. The NUCLEO window will - close then re-open and the Nucleo-F4x1RE will be running the new code. + nuttx.bin binary into the board. The DIS_L49RAIO window will + close then re-open and the board will be running the new code. Hardware ======== - GPIO - ---- - SERIAL_TX=PA_2 USER_BUTTON=PC_13 - SERIAL_RX=PA_3 LED1 =PA_5 - - A0=PA_0 USART2RX D0=PA_3 D8 =PA_9 - A1=PA_1 USART2TX D1=PA_2 D9 =PC_7 - A2=PA_4 D2=PA_10 WIFI_CS=D10=PB_6 SPI_CS - A3=PB_0 WIFI_INT=D3=PB_3 D11=PA_7 SPI_MOSI - A4=PC_1 SDCS=D4=PB_5 D12=PA_6 SPI_MISO - A5=PC_0 WIFI_EN=D5=PB_4 LED1=D13=PA_5 SPI_SCK - LED2=D6=PB_10 I2C1_SDA=D14=PB_9 Probe - D7=PA_8 I2C1_SCL=D15=PB_8 Probe - - From: https://mbed.org/platforms/ST-Nucleo-F401RE/ - Buttons ------- B1 USER: the user button is connected to the I/O PC13 (pin 2) of the STM32 @@ -96,17 +79,16 @@ Hardware LEDs ---- - The Nucleo F401RE and Nucleo F411RE provide a single user LED, LD2. LD2 - is the green LED connected to Arduino signal D13 corresponding to MCU I/O - PA5 (pin 21) or PB13 (pin 34) depending on the STM32target. - + The STM32L4R9AI-DISCO board provides two user LEDs, LD1 (orange) and LD2 (green). + PB0 is LD1 (orange) + PH4 is LD2 (green) - When the I/O is HIGH value, the LED is on. - When the I/O is LOW, the LED is off. These LEDs are not used by the board port unless CONFIG_ARCH_LEDS is defined. In that case, the usage by the board port is defined in - include/board.h and src/sam_leds.c. The LEDs are used to encode OS-related - events as follows when the red LED (PE24) is available: + include/board.h and src/stm32_autoleds.c. The LEDs are used to encode OS-related + events as follows when the green LED (PH4) is available: SYMBOL Meaning LD2 ------------------- ----------------------- ----------- @@ -120,8 +102,8 @@ Hardware LED_PANIC The system has crashed Blinking LED_IDLE MCU is is sleep mode Not used - Thus if LD2, NuttX has successfully booted and is, apparently, running - normally. If LD2 is flashing at approximately 2Hz, then a fatal error + Thus if LD2 is on, NuttX has successfully booted and is, apparently, + running normally. If LD2 is flashing at approximately 2Hz, then a fatal error has been detected and the system has halted. Serial Consoles @@ -150,7 +132,7 @@ Serial Consoles To configure USART1 as the console: - CONFIG_STM32_USART1=y + CONFIG_STM32L4_USART1=y CONFIG_USART1_SERIALDRIVER=y CONFIG_USART1_SERIAL_CONSOLE=y CONFIG_USART1_RXBUFSIZE=256 @@ -169,8 +151,6 @@ Serial Consoles TXD: PA2 CN9 pin 2(See SB13, 14, 62, 63). CN10 pin 35 PD5 - UART2 is the default in all of these configurations. - TTL to RS-232 converter connection: Nucleo CN9 STM32F4x1RE @@ -189,7 +169,7 @@ Serial Consoles To configure USART2 as the console: - CONFIG_STM32_USART2=y + CONFIG_STM32L4_USART2=y CONFIG_USART2_SERIALDRIVER=y CONFIG_USART2_SERIAL_CONSOLE=y CONFIG_USART2_RXBUFSIZE=256 @@ -199,26 +179,24 @@ Serial Consoles CONFIG_USART2_PARITY=0 CONFIG_USART2_2STOP=0 - USART6 + UART4 ------ Pins and Connectors: - RXD: PC7 CN5 pin2, CN10 pin 19 - PA12 CN10, pin 12 - TXD: PC6 CN10, pin 4 - PA11 CN10, pin 14 + RXD: PA1 -> CN11 D5 + TXD: PA0 -> CN17 A4 - To configure USART6 as the console: + To configure USART4 as the console: - CONFIG_STM32_USART6=y - CONFIG_USART6_SERIALDRIVER=y - CONFIG_USART6_SERIAL_CONSOLE=y - CONFIG_USART6_RXBUFSIZE=256 - CONFIG_USART6_TXBUFSIZE=256 - CONFIG_USART6_BAUD=115200 - CONFIG_USART6_BITS=8 - CONFIG_USART6_PARITY=0 - CONFIG_USART6_2STOP=0 + CONFIG_STM32L4_UART4=y + CONFIG_USART4_SERIALDRIVER=y + CONFIG_USART4_SERIAL_CONSOLE=y + CONFIG_USART4_RXBUFSIZE=512 + CONFIG_USART4_TXBUFSIZE=256 + CONFIG_USART4_BAUD=2000000 + CONFIG_USART4_BITS=8 + CONFIG_USART4_PARITY=0 + CONFIG_USART4_2STOP=0 Virtual COM Port ---------------- @@ -246,97 +224,6 @@ Serial Consoles As shipped, SB62 and SB63 are open and SB13 and SB14 closed, so the virtual COM port is enabled. -Shields -======= - - RS-232 from Cutedigi.com - ------------------------ - Supports a single RS-232 connected via - - Nucleo CN9 STM32F4x1RE Cutedigi - ----------- ------------ -------- - Pin 1 PA3 USART2_RX RXD - Pin 2 PA2 USART2_TX TXD - - Support for this shield is enabled by selecting USART2 and configuring - SB13, 14, 62, and 63 as described above under "Serial Consoles" - - Itead Joystick Shield - --------------------- - See http://imall.iteadstudio.com/im120417014.html for more information - about this joystick. - - Itead Joystick Connection: - - --------- ----------------- --------------------------------- - ARDUINO ITEAD NUCLEO-F4x1 - PIN NAME SIGNAL SIGNAL - --------- ----------------- --------------------------------- - D3 Button E Output PB3 - D4 Button D Output PB5 - D5 Button C Output PB4 - D6 Button B Output PB10 - D7 Button A Output PA8 - D8 Button F Output PA9 - D9 Button G Output PC7 - A0 Joystick Y Output PA0 ADC1_0 - A1 Joystick X Output PA1 ADC1_1 - --------- ----------------- --------------------------------- - - All buttons are pulled on the shield. A sensed low value indicates - when the button is pressed. - - NOTE: Button F cannot be used with the default USART1 configuration - because PA9 is configured for USART1_RX by default. Use select - different USART1 pins in the board.h file or select a different - USART or select CONFIG_NUCLEO_F401RE_AJOY_MINBUTTONS which will - eliminate all but buttons A, B, and C. - - Itead Joystick Signal interpretation: - - --------- ----------------------- --------------------------- - BUTTON TYPE NUTTX ALIAS - --------- ----------------------- --------------------------- - Button A Large button A JUMP/BUTTON 3 - Button B Large button B FIRE/BUTTON 2 - Button C Joystick select button SELECT/BUTTON 1 - Button D Tiny Button D BUTTON 6 - Button E Tiny Button E BUTTON 7 - Button F Large Button F BUTTON 4 - Button G Large Button G BUTTON 5 - --------- ----------------------- --------------------------- - - Itead Joystick configuration settings: - - System Type -> STM32 Peripheral Support - CONFIG_STM32_ADC1=y : Enable ADC1 driver support - - Drivers - CONFIG_ANALOG=y : Should be automatically selected - CONFIG_ADC=y : Should be automatically selected - CONFIG_INPUT=y : Select input device support - CONFIG_AJOYSTICK=y : Select analog joystick support - - There is nothing in the configuration that currently uses the joystick. - For testing, you can add the following configuration options to enable the - analog joystick example at apps/examples/ajoystick: - - CONFIG_NSH_ARCHINIT=y - CONFIG_EXAMPLES_AJOYSTICK=y - CONFIG_EXAMPLES_AJOYSTICK_DEVNAME="/dev/ajoy0" - CONFIG_EXAMPLES_AJOYSTICK_SIGNO=13 - - STATUS: - 2014-12-04: - - Without ADC DMA support, it is not possible to sample both X and Y - with a single ADC. Right now, only one axis is being converted. - - There is conflicts with some of the Arduino data pins and the - default USART1 configuration. I am currently running with USART1 - but with CONFIG_NUCLEO_F401RE_AJOY_MINBUTTONS to eliminate the - conflict. - - Current showstopper: I appear to be getting infinite interrupts as - soon as joystick button interrupts are enabled. - Configurations ============== @@ -424,8 +311,8 @@ Configurations nsh: --- Configures the NuttShell (nsh) located at apps/examples/nsh for the - Nucleo-F401RE board. The Configuration enables the serial interfaces - on UART2. Support for builtin applications is enabled, but in the base + STM32L4R9AI-DISCO board. The Configuration enables the serial interfaces + on UART4. Support for builtin applications is enabled, but in the base configuration no builtin applications are selected (see NOTES below). NOTES: @@ -433,11 +320,8 @@ Configurations 1. This configuration uses the mconf-based configuration tool. To change this configuration using that tool, you should: - a. Build and install the kconfig-mconf tool. See nuttx/README.txt - see additional README.txt files in the NuttX tools repository. - - b. Execute 'make menuconfig' in nuttx/ in order to start the - reconfiguration process. + Execute 'make menuconfig' in nuttx/ in order to start the + reconfiguration process. 2. By default, this configuration uses the Generic ARM EABI toolchain for Linux. That can easily be reconfigured, of course. @@ -445,14 +329,11 @@ Configurations CONFIG_HOST_LINUX=y : Builds under Linux CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIL=y : Generic EABI toolchain for Linux - 3. Although the default console is USART2 (which would correspond to - the Virtual COM port) I have done all testing with the console - device configured for USART1 (see instruction above under "Serial - Consoles). I have been using a TTL-to-RS-232 converter. + 3. The default console is UART4 - 4. This example has been used to verify the OTGFS functionality. USB is + 4. This example can be used to verify the OTGFS functionality. USB is not enabled in the default configuration but can be enabled with the - following settings: + following settings: (TODO: need to test!) CONFIG_STM32L4_OTGFS=y diff --git a/configs/stm32l4r9ai-disco/include/board.h b/configs/stm32l4r9ai-disco/include/board.h index faf0ba4c41e..4aecf071f70 100644 --- a/configs/stm32l4r9ai-disco/include/board.h +++ b/configs/stm32l4r9ai-disco/include/board.h @@ -158,51 +158,12 @@ #define GPIO_SPI1_MOSI GPIO_SPI1_MOSI_1 #define GPIO_SPI1_SCK GPIO_SPI1_SCK_1 -/* SPI2 is used for several peripherals on the Discovery board, including - * L3GD20 - 3 axis Gyroscope - * LSM303CTR - eCompass, comprising an accelerometer and magnetometer - */ +/* XXX is SPI2 used on Disco? */ #define GPIO_SPI2_MISO GPIO_SPI2_MISO_3 #define GPIO_SPI2_MOSI GPIO_SPI2_MOSI_3 #define GPIO_SPI2_SCK GPIO_SPI2_SCK_3 -/* PD7; gyroscope CS */ - -#define GPIO_SPI_CS_GYRO_OFF \ - (GPIO_INPUT | GPIO_PULLDOWN | GPIO_SPEED_2MHz | \ - GPIO_PORTD | GPIO_PIN7) -#define GPIO_SPI_CS_GYRO \ - (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_2MHz | \ - GPIO_OUTPUT_SET | GPIO_PORTD | GPIO_PIN7) - -/* PE0; accelerometer CS */ - -#define GPIO_SPI_CS_ACCEL_OFF \ - (GPIO_INPUT | GPIO_PULLDOWN | GPIO_SPEED_2MHz | \ - GPIO_PORTE | GPIO_PIN0) -#define GPIO_SPI_CS_ACCEL \ - (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_2MHz | \ - GPIO_OUTPUT_SET | GPIO_PORTE | GPIO_PIN0) - -/* PC0; magnetometer CS */ - -#define GPIO_SPI_CS_MAGNETO_OFF \ - (GPIO_INPUT | GPIO_PULLDOWN | GPIO_SPEED_2MHz | \ - GPIO_PORTC | GPIO_PIN0) -#define GPIO_SPI_CS_MAGNETO \ - (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_2MHz | \ - GPIO_OUTPUT_SET | GPIO_PORTC | GPIO_PIN0) - -/* XXX these will need to be set up when these get implemented: - * PD2 gyro INT1 - * PB8 gyro INT2/DRDY - * - * PE1 accel INT - * PC2 magneto DRDY - * PC1 magneto INT - */ - /* LEDs * * The STM32L4R9AI-DISCO board provides two user LEDs, LD1 (orange) and LD2 (green). diff --git a/configs/stm32l4r9ai-disco/include/stm32l4r9ai-disco-clocking.h b/configs/stm32l4r9ai-disco/include/stm32l4r9ai-disco-clocking.h index 567b13e1c3b..a8e07f76350 100644 --- a/configs/stm32l4r9ai-disco/include/stm32l4r9ai-disco-clocking.h +++ b/configs/stm32l4r9ai-disco/include/stm32l4r9ai-disco-clocking.h @@ -52,22 +52,30 @@ /* Clocking *************************************************************************/ /* The stm32l4r9ai-disco supports both HSE and LSE crystals. As shipped, the HSE - * crystal is not populated. Therefore the stm32l4r9ai-disco will need to run off the - * 16MHz HSI clock, or the 32khz-synced MSI, unless you install the HSE xtal. + * is a 16 MHz crystal X2. Therefore the stm32l4r9ai-disco can run off the 16MHz + * HSI clock, or the MSI, or the HSE. Here we configure HSE to give us 120MHz system + * clock (maximum supported for STM32L4+ chips) instead of the more traditional 80MHz + * that is used by most STM32L4 boards supported by NuttX. */ /* HSI - 16 MHz RC factory-trimmed * LSI - 32 KHz RC * MSI - variable up to 48 MHz, synchronized to LSE - * HSE - not installed + * HSE - 16 MHz installed * LSE - 32.768 kHz installed */ #define STM32L4_HSI_FREQUENCY 16000000ul #define STM32L4_LSI_FREQUENCY 32000 #define STM32L4_LSE_FREQUENCY 32768 +#define STM32L4_HSE_FREQUENCY 16000000ul -#define BOARD_AHB_FREQUENCY 80000000ul +#define STM32L4_SYSCLK_FREQUENCY 120000000ul +#define BOARD_AHB_FREQUENCY STM32L4_SYSCLK_FREQUENCY + +/* Higher SYSCLK reguires more flash wait states. */ + +#define BOARD_FLASH_WAITSTATES 5 /* XXX there needs to be independent selections for the System Clock Mux and * the PLL Source Mux; currently System Clock Mux always is PLL, and PLL @@ -77,10 +85,8 @@ #if 0 # define HSI_CLOCK_CONFIG 1 /* HSI-16 clock configuration */ -#elif 0 -/* Make sure you actually installed one! */ - -# define HSE_CLOCK_CONFIG 1 /* HSE with 8 MHz xtal */ +#elif 1 +# define HSE_CLOCK_CONFIG 1 /* HSE with 16 MHz xtal */ #else # define MSI_CLOCK_CONFIG 1 /* MSI @ 4 MHz autotrimmed via LSE */ #endif @@ -89,20 +95,19 @@ #define STM32L4_BOARD_USEHSI 1 -/* Prescaler common to all PLL inputs; will be 1 (XXX source is implicitly - as per comment above HSI) */ +/* Prescaler common to all PLL inputs; will be 1 */ #define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) /* 'main' PLL config; we use this to generate our system clock via the R - * output. We set it up as 16 MHz / 1 * 10 / 2 = 80 MHz + * output. We set it up as 16 MHz / 1 * 15 / 2 = 120 MHz * * XXX NOTE: currently the main PLL is implicitly turned on and is implicitly * the system clock; this should be configurable since not all applications may * want things done this way. */ -#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(10) +#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(15) #define STM32L4_PLLCFG_PLLP 0 #undef STM32L4_PLLCFG_PLLP_ENABLED #define STM32L4_PLLCFG_PLLQ RCC_PLLCFG_PLLQ_2 @@ -138,8 +143,6 @@ #define STM32L4_PLLSAI2CFG_PLLR 0 #undef STM32L4_PLLSAI2CFG_PLLR_ENABLED -#define STM32L4_SYSCLK_FREQUENCY 80000000ul - /* CLK48 will come from PLLSAI1 (implicitly Q) */ #define STM32L4_USE_CLK48 1 @@ -149,31 +152,35 @@ #define STM32L4_USE_LSE 1 -/* AHB clock (HCLK) is SYSCLK (80MHz) */ +/* AHB clock (HCLK) is SYSCLK (120 MHz) */ #define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ #define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY #define STM32L4_BOARD_HCLK STM32L4_HCLK_FREQUENCY /* Same as above, to satisfy compiler */ -/* APB1 clock (PCLK1) is HCLK/1 (80MHz) */ +/* APB1 clock (PCLK1) is HCLK/1 (120 MHz) */ #define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ -#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY/1) +#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1) -/* Timers driven from APB1 will be twice PCLK1 */ -/* REVISIT : this can be configured */ +/* The timer clock frequencies are automatically defined by hardware. + * If the APB prescaler equals 1, the timer clock frequencies are set to the + * same frequency as that of the APB domain. Otherwise they are set to twice. + * + * REVISIT : this can be configured + */ -#define STM32L4_APB1_TIM2_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM3_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM4_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM5_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM6_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM7_CLKIN (2*STM32L4_PCLK1_FREQUENCY) +#define STM32L4_APB1_TIM2_CLKIN (STM32L4_PCLK1_FREQUENCY) +#define STM32L4_APB1_TIM3_CLKIN (STM32L4_PCLK1_FREQUENCY) +#define STM32L4_APB1_TIM4_CLKIN (STM32L4_PCLK1_FREQUENCY) +#define STM32L4_APB1_TIM5_CLKIN (STM32L4_PCLK1_FREQUENCY) +#define STM32L4_APB1_TIM6_CLKIN (STM32L4_PCLK1_FREQUENCY) +#define STM32L4_APB1_TIM7_CLKIN (STM32L4_PCLK1_FREQUENCY) -/* APB2 clock (PCLK2) is HCLK (80MHz) */ +/* APB2 clock (PCLK2) is HCLK (120 MHz) */ #define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ -#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY/1) +#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1) /* The timer clock frequencies are automatically defined by hardware. * If the APB prescaler equals 1, the timer clock frequencies are set to the @@ -191,30 +198,42 @@ #define STM32L4_BOARD_USEHSE 1 -/* XXX sysclk mux = pllclk */ - -/* XXX pll source mux = hse */ - /* Prescaler common to all PLL inputs */ #define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) -/* 'main' PLL config; we use this to generate our system clock */ +/* 'main' PLL config; we use this to generate our system clock via the R + * output. We set it up as 16 MHz / 1 * 15 / 2 = 120 MHz + * + * XXX NOTE: currently the main PLL is implicitly turned on and is implicitly + * the system clock; this should be configurable since not all applications may + * want things done this way. + */ -#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(20) +#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(15) #define STM32L4_PLLCFG_PLLP 0 #undef STM32L4_PLLCFG_PLLP_ENABLED -#define STM32L4_PLLCFG_PLLQ 0 -#undef STM32L4_PLLCFG_PLLQ_ENABLED +#define STM32L4_PLLCFG_PLLQ RCC_PLLCFG_PLLQ_2 +#define STM32L4_PLLCFG_PLLQ_ENABLED #define STM32L4_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 #define STM32L4_PLLCFG_PLLR_ENABLED -/* 'SAIPLL1' is used to generate the 48 MHz clock */ +/* 'SAIPLL1' is used to generate the 48 MHz clock, since we can't + * do that with the main PLL's N value. We set N = 12, and enable + * the Q output (ultimately for CLK48) with /4. So, + * 16 MHz / 1 * 12 / 4 = 48 MHz + * + * XXX NOTE: currently the SAIPLL /must/ be explicitly selected in the + * menuconfig, or else all this is a moot point, and the various 48 MHz + * peripherals will not work (RNG at present). I would suggest removing + * that option from Kconfig altogether, and simply making it an option + * that is selected via a #define here, like all these other params. + */ #define STM32L4_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) #define STM32L4_PLLSAI1CFG_PLLP 0 #undef STM32L4_PLLSAI1CFG_PLLP_ENABLED -#define STM32L4_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_2 +#define STM32L4_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_4 #define STM32L4_PLLSAI1CFG_PLLQ_ENABLED #define STM32L4_PLLSAI1CFG_PLLR 0 #undef STM32L4_PLLSAI1CFG_PLLR_ENABLED @@ -227,11 +246,9 @@ #define STM32L4_PLLSAI2CFG_PLLR 0 #undef STM32L4_PLLSAI2CFG_PLLR_ENABLED -#define STM32L4_SYSCLK_FREQUENCY 80000000ul - /* Enable CLK48; get it from PLLSAI1 */ -#define STM32L4_USE_CLK48 +#define STM32L4_USE_CLK48 1 #define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 /* Enable LSE (for the RTC) */ @@ -271,25 +288,37 @@ #define STM32L4_BOARD_USEMSI 1 #define STM32L4_BOARD_MSIRANGE RCC_CR_MSIRANGE_4M -/* XXX sysclk mux = pllclk */ - -/* XXX pll source mux = msi */ - /* Prescaler common to all PLL inputs */ #define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) -/* 'main' PLL config; we use this to generate our system clock */ +/* 'main' PLL config; we use this to generate our system clock via the R + * output. We set it up as 4 MHz / 1 * 60 / 2 = 120 MHz + * + * XXX NOTE: currently the main PLL is implicitly turned on and is implicitly + * the system clock; this should be configurable since not all applications may + * want things done this way. + */ -#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(40) +#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(60) #define STM32L4_PLLCFG_PLLP 0 #undef STM32L4_PLLCFG_PLLP_ENABLED -#define STM32L4_PLLCFG_PLLQ 0 -#undef STM32L4_PLLCFG_PLLQ_ENABLED +#define STM32L4_PLLCFG_PLLQ RCC_PLLCFG_PLLQ_2 +#define STM32L4_PLLCFG_PLLQ_ENABLED #define STM32L4_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 #define STM32L4_PLLCFG_PLLR_ENABLED -/* 'SAIPLL1' is used to generate the 48 MHz clock */ +/* 'SAIPLL1' is used to generate the 48 MHz clock, since we can't + * do that with the main PLL's N value. We set N = 12, and enable + * the Q output (ultimately for CLK48) with /4. So, + * 4 MHz / 1 * 24 / 2 = 48 MHz + * + * XXX NOTE: currently the SAIPLL /must/ be explicitly selected in the + * menuconfig, or else all this is a moot point, and the various 48 MHz + * peripherals will not work (RNG at present). I would suggest removing + * that option from Kconfig altogether, and simply making it an option + * that is selected via a #define here, like all these other params. + */ #define STM32L4_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(24) #define STM32L4_PLLSAI1CFG_PLLP 0 @@ -307,11 +336,9 @@ #define STM32L4_PLLSAI2CFG_PLLR 0 #undef STM32L4_PLLSAI2CFG_PLLR_ENABLED -#define STM32L4_SYSCLK_FREQUENCY 80000000ul - /* Enable CLK48; get it from PLLSAI1 */ -#define STM32L4_USE_CLK48 +#define STM32L4_USE_CLK48 1 #define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 /* Enable LSE (for the RTC) */ @@ -344,7 +371,7 @@ #define STM32L4_APB2_TIM1_CLKIN (STM32L4_PCLK2_FREQUENCY) #define STM32L4_APB2_TIM8_CLKIN (STM32L4_PCLK2_FREQUENCY) -#endif +#endif /* clock selection */ /* The timer clock frequencies are automatically defined by hardware. * If the APB prescaler equals 1, the timer clock frequencies are set to the same diff --git a/configs/stm32l4r9ai-disco/nsh/defconfig b/configs/stm32l4r9ai-disco/nsh/defconfig index 58764193354..84212c09786 100644 --- a/configs/stm32l4r9ai-disco/nsh/defconfig +++ b/configs/stm32l4r9ai-disco/nsh/defconfig @@ -14,7 +14,7 @@ CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_IOCTL=y CONFIG_BOARDCTL_UNIQUEID=y CONFIG_BOARDCTL_UNIQUEID_SIZE=12 -CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BOARD_LOOPSPERMSEC=9234 CONFIG_BUILTIN=y CONFIG_DEV_LOOP=y CONFIG_DEV_ZERO=y