arch/x86_64: do not demand a TSC frequency for a clock that has none.

g_x86_64_timer_freq is assigned only under ARCH_INTEL64_TSC_DEADLINE or
ARCH_INTEL64_TSC, and is read only by the two intel64_tsc_*.c files those
options build.  With the HPET as the system clock it stays 0, which is
correct and harmless -- but x86_64_timer_calibrate_freq() panics on 0
unconditionally, so the board dies during x86_64_lowsetup().

Require a frequency only where something needs one, which is
ARCH_INTEL64_HAVE_TSC.

The failure mode is worth recording, because it gives nothing to work from:
the PANIC() happens before x86_64_earlyserialinit(), and the panic handler
itself then triple-faults, because _assert() reads up_interrupt_context() --
a %gs-relative load -- and the GS base is not programmed until
x86_64_cpu_priv_set().  The console stays completely empty and the machine
resets.

Impact: runtime, ARCH_INTEL64_HPET_ALARM only.  Configurations with a TSC
are unchanged -- the PANIC() is still compiled for them.

Assisted-by: Claude:claude-opus-5
Signed-off-by: Marco Casaroli <marco.casaroli@gmail.com>

arch/x86_64/src/intel64/intel64_freq.c

@@ -150,10 +150,12 @@ void x86_64_timer_calibrate_freq(void)
   g_x86_64_timer_freq = CONFIG_ARCH_INTEL64_APIC_FREQ_KHZ * 1000ul;
 #endif
 
+#ifdef CONFIG_ARCH_INTEL64_HAVE_TSC
   if (g_x86_64_timer_freq == 0)
     {
       /* The TSC frequency is not available */
 
       PANIC();
     }
+#endif
 }