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arch/arm/src/am335x: Changes related to Control Module

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This commit is contained in:
Petro Karashchenko 2019-07-09 15:38:38 -06:00 • committed by Gregory Nutt
parent eed706d458
commit c9ff188f3e
4 changed files with 257 additions and 259 deletions
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2
arch/arm/src/am335x/am335x_gpio.h
View file

@ -45,7 +45,7 @@
#include <stdint.h>
#include <stdbool.h>
#include "hardware/am335x_control.h"
#include "hardware/am335x_scm.h"
#include "hardware/am335x_gpio.h"
/************************************************************************************

2
arch/arm/src/am335x/am335x_pinmux.h
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@ -42,7 +42,7 @@
#include <nuttx/config.h>
#include "hardware/am335x_control.h"
#include "hardware/am335x_scm.h"
#include "hardware/am335x_pinmux.h"
/****************************************************************************

13
arch/arm/src/am335x/am335x_sysclk.c
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@ -43,24 +43,13 @@
#include <errno.h>
#include "up_arch.h"
#include "hardware/am335x_memorymap.h"
#include "hardware/am335x_scm.h"
#include "am335x_sysclk.h"
/****************************************************************************
* Pre-processor definitions
****************************************************************************/
/* REVISIT: These belong in a control module register header file */
#define AM335X_SCM_CTRL_STATUS_OFFSET 0x40
#define AM335X_SCM_CTRL_STATUS (AM335X_CONTROL_MODULE_VADDR + AM335X_SCM_CTRL_STATUS_OFFSET)
#define SCM_CTRL_STATUS_SYSBOOT1_SHIFT (22) /* Bits 22-23: Crystal clock frequency selection */
#define SCM_CTRL_STATUS_SYSBOOT1_MASK (3 << SCM_CTRL_STATUS_SYSBOOT1_SHIFT)
# define SCM_CTRL_STATUS_SYSBOOT1_19p2MHZ (0 << SCM_CTRL_STATUS_SYSBOOT1_SHIFT)
# define SCM_CTRL_STATUS_SYSBOOT1_24MHZ (1 << SCM_CTRL_STATUS_SYSBOOT1_SHIFT)
# define SCM_CTRL_STATUS_SYSBOOT1_25MHZ (2 << SCM_CTRL_STATUS_SYSBOOT1_SHIFT)
# define SCM_CTRL_STATUS_SYSBOOT1_26MHZ (3 << SCM_CTRL_STATUS_SYSBOOT1_SHIFT)
/****************************************************************************
* Public Functions
****************************************************************************/

499
arch/arm/src/am335x/hardware/am335x_control.h → arch/arm/src/am335x/hardware/am335x_scm.h
View file

@ -1,5 +1,5 @@
/********************************************************************************************
* arch/arm/src/am335x/hardware/am335x_control.h
* arch/arm/src/am335x/hardware/am335x_scm.h
*
* Copyright (C) 2018 Petro Karashchenko. All rights reserved.
* Author: Petro Karashchenko <petro.karashchenko@gmail.com>
@ -33,8 +33,8 @@
*
********************************************************************************************/
#ifndef __ARCH_ARM_SRC_AM335X_HARDWARE_AM335X_CONTROL_H
#define __ARCH_ARM_SRC_AM335X_HARDWARE_AM335X_CONTROL_H
#ifndef __ARCH_ARM_SRC_AM335X_HARDWARE_AM335X_SCM_H
#define __ARCH_ARM_SRC_AM335X_HARDWARE_AM335X_SCM_H
/********************************************************************************************
* Included Files
@ -49,95 +49,95 @@
/* Control Module Register Offsets **********************************************************/
#define AM335X_CONTROL_SYS_CONF_OFFSET 0x0010
#define AM335X_CONTROL_STATUS_OFFSET 0x0040
#define AM335X_CONTROL_EMIF_SDRAM_CONF_OFFSET 0x0110
#define AM335X_CORE_SLDO_CTRL_OFFSET 0x0428
#define AM335X_MPU_SLDO_CTRL_OFFSET 0x042C
#define AM335X_CLK32KDIVRATIO_CTRL_OFFSET 0x0444
#define AM335X_BANDGAP_CTRL_OFFSET 0x0448
#define AM335X_BANDGAP_TRIM_OFFSET 0x044C
#define AM335X_PLL_CLKINPULOW_CTRL_OFFSET 0x0458
#define AM335X_MOSC_CTRL_OFFSET 0x0468
#define AM335X_DEEPSLEEP_CTRL_OFFSET 0x0470
#define AM335X_DPLL_PWR_SW_STATUS_OFFSET 0x050C
#define AM335X_DEVICE_ID_OFFSET 0x0600
#define AM335X_DEV_FEATURE_OFFSET 0x0604
#define AM335X_INIT_PRIORITY_0_OFFSET 0x0608
#define AM335X_INIT_PRIORITY_1_OFFSET 0x060C
#define AM335X_TPTC_CFG_OFFSET 0x0614
#define AM335X_USB_CTRL0_OFFSET 0x0620
#define AM335X_USB_STS0_OFFSET 0x0624
#define AM335X_USB_CTRL1_OFFSET 0x0628
#define AM335X_USB_STS1_OFFSET 0x062C
#define AM335X_MAC_ID0_LO_OFFSET 0x0630
#define AM335X_MAC_ID0_HI_OFFSET 0x0634
#define AM335X_MAC_ID1_LO_OFFSET 0x0638
#define AM335X_MAC_ID1_HI_OFFSET 0x063C
#define AM335X_DCAN_RAMINIT_OFFSET 0x0644
#define AM335X_USB_WKUP_CTRL_OFFSET 0x0648
#define AM335X_GMII_SEL_OFFSET 0x0650
#define AM335X_PWMSS_CTRL_OFFSET 0x0664
#define AM335X_MREGPRIO_0_OFFSET 0x0670
#define AM335X_MREGPRIO_1_OFFSET 0x0674
#define AM335X_HW_EVENT_SEL_GRP1_OFFSET 0x0690
#define AM335X_HW_EVENT_SEL_GRP2_OFFSET 0x0694
#define AM335X_HW_EVENT_SEL_GRP3_OFFSET 0x0698
#define AM335X_HW_EVENT_SEL_GRP4_OFFSET 0x069C
#define AM335X_SMRT_CTRL_OFFSET 0x06A0
#define AM335X_MPUSS_HW_DEBUG_SEL_OFFSET 0x06A4
#define AM335X_MPUSS_HW_DBG_INFO_OFFSET 0x06A8
#define AM335X_VDD_MPU_OPP_050_OFFSET 0x0770
#define AM335X_VDD_MPU_OPP_100_OFFSET 0x0774
#define AM335X_VDD_MPU_OPP_120_OFFSET 0x0778
#define AM335X_VDD_MPU_OPP_TURBO_OFFSET 0x077C
#define AM335X_VDD_CORE_OPP_050_OFFSET 0x07B8
#define AM335X_VDD_CORE_OPP_100_OFFSET 0x07BC
#define AM335X_BB_SCALE_OFFSET 0x07D0
#define AM335X_USB_VID_PID_OFFSET 0x07F4
#define AM335X_EFUSE_SMA_OFFSET 0x07FC
#define AM335X_SCM_CTRL_SYS_CONF_OFFSET 0x0010
#define AM335X_SCM_CTRL_STATUS_OFFSET 0x0040
#define AM335X_SCM_CTRL_EMIF_SDRAM_CONF_OFFSET 0x0110
#define AM335X_SCM_CORE_SLDO_CTRL_OFFSET 0x0428
#define AM335X_SCM_MPU_SLDO_CTRL_OFFSET 0x042c
#define AM335X_SCM_CLK32KDIVRATIO_CTRL_OFFSET 0x0444
#define AM335X_SCM_BANDGAP_CTRL_OFFSET 0x0448
#define AM335X_SCM_BANDGAP_TRIM_OFFSET 0x044c
#define AM335X_SCM_PLL_CLKINPULOW_CTRL_OFFSET 0x0458
#define AM335X_SCM_MOSC_CTRL_OFFSET 0x0468
#define AM335X_SCM_DEEPSLEEP_CTRL_OFFSET 0x0470
#define AM335X_SCM_DPLL_PWR_SW_STATUS_OFFSET 0x050c
#define AM335X_SCM_DEVICE_ID_OFFSET 0x0600
#define AM335X_SCM_DEV_FEATURE_OFFSET 0x0604
#define AM335X_SCM_INIT_PRIORITY_0_OFFSET 0x0608
#define AM335X_SCM_INIT_PRIORITY_1_OFFSET 0x060c
#define AM335X_SCM_TPTC_CFG_OFFSET 0x0614
#define AM335X_SCM_USB_CTRL0_OFFSET 0x0620
#define AM335X_SCM_USB_STS0_OFFSET 0x0624
#define AM335X_SCM_USB_CTRL1_OFFSET 0x0628
#define AM335X_SCM_USB_STS1_OFFSET 0x062c
#define AM335X_SCM_MAC_ID0_LO_OFFSET 0x0630
#define AM335X_SCM_MAC_ID0_HI_OFFSET 0x0634
#define AM335X_SCM_MAC_ID1_LO_OFFSET 0x0638
#define AM335X_SCM_MAC_ID1_HI_OFFSET 0x063c
#define AM335X_SCM_DCAN_RAMINIT_OFFSET 0x0644
#define AM335X_SCM_USB_WKUP_CTRL_OFFSET 0x0648
#define AM335X_SCM_GMII_SEL_OFFSET 0x0650
#define AM335X_SCM_PWMSS_CTRL_OFFSET 0x0664
#define AM335X_SCM_MREGPRIO_0_OFFSET 0x0670
#define AM335X_SCM_MREGPRIO_1_OFFSET 0x0674
#define AM335X_SCM_HW_EVENT_SEL_GRP1_OFFSET 0x0690
#define AM335X_SCM_HW_EVENT_SEL_GRP2_OFFSET 0x0694
#define AM335X_SCM_HW_EVENT_SEL_GRP3_OFFSET 0x0698
#define AM335X_SCM_HW_EVENT_SEL_GRP4_OFFSET 0x069c
#define AM335X_SCM_SMRT_CTRL_OFFSET 0x06a0
#define AM335X_SCM_MPUSS_HW_DEBUG_SEL_OFFSET 0x06a4
#define AM335X_SCM_MPUSS_HW_DBG_INFO_OFFSET 0x06a8
#define AM335X_SCM_VDD_MPU_OPP_050_OFFSET 0x0770
#define AM335X_SCM_VDD_MPU_OPP_100_OFFSET 0x0774
#define AM335X_SCM_VDD_MPU_OPP_120_OFFSET 0x0778
#define AM335X_SCM_VDD_MPU_OPP_TURBO_OFFSET 0x077c
#define AM335X_SCM_VDD_CORE_OPP_050_OFFSET 0x07b8
#define AM335X_SCM_VDD_CORE_OPP_100_OFFSET 0x07bc
#define AM335X_SCM_BB_SCALE_OFFSET 0x07d0
#define AM335X_SCM_USB_VID_PID_OFFSET 0x07f4
#define AM335X_SCM_EFUSE_SMA_OFFSET 0x07fc
#define AM335X_CQDETECT_STATUS_OFFSET 0x0E00
#define AM335X_DDR_IO_CTRL_OFFSET 0x0E04
#define AM335X_VTP_CTRL_OFFSET 0x0E0C
#define AM335X_VREF_CTRL_OFFSET 0x0E14
#define AM335X_TPCC_EVT_MUX_0_3_OFFSET 0x0F90
#define AM335X_TPCC_EVT_MUX_4_7_OFFSET 0x0F94
#define AM335X_TPCC_EVT_MUX_8_11_OFFSET 0x0F98
#define AM335X_TPCC_EVT_MUX_12_15_OFFSET 0x0F9C
#define AM335X_TPCC_EVT_MUX_16_19_OFFSET 0x0FA0
#define AM335X_TPCC_EVT_MUX_20_23_OFFSET 0x0FA4
#define AM335X_TPCC_EVT_MUX_24_27_OFFSET 0x0FA8
#define AM335X_TPCC_EVT_MUX_28_31_OFFSET 0x0FAC
#define AM335X_TPCC_EVT_MUX_32_35_OFFSET 0x0FB0
#define AM335X_TPCC_EVT_MUX_36_39_OFFSET 0x0FB4
#define AM335X_TPCC_EVT_MUX_40_43_OFFSET 0x0FB8
#define AM335X_TPCC_EVT_MUX_44_47_OFFSET 0x0FBC
#define AM335X_TPCC_EVT_MUX_48_51_OFFSET 0x0FC0
#define AM335X_TPCC_EVT_MUX_52_55_OFFSET 0x0FC4
#define AM335X_TPCC_EVT_MUX_56_59_OFFSET 0x0FC8
#define AM335X_TPCC_EVT_MUX_60_63_OFFSET 0x0FCC
#define AM335X_TIMER_EVT_CAPT_OFFSET 0x0FD0
#define AM335X_ECAP_EVT_CAPT_OFFSET 0x0FD4
#define AM335X_ADC_EVT_CAPT_OFFSET 0x0FD8
#define AM335X_RESET_ISO_OFFSET 0x1000
#define AM335X_DPLL_PWR_SW_CTRL_OFFSET 0x1318
#define AM335X_DDR_CKE_CTRL_OFFSET 0x131C
#define AM335X_SMA2_OFFSET 0x1320
#define AM335X_M3_TXEV_EOI_OFFSET 0x1324
#define AM335X_IPC_MSG_REG0_OFFSET 0x1328
#define AM335X_IPC_MSG_REG1_OFFSET 0x132C
#define AM335X_IPC_MSG_REG2_OFFSET 0x1330
#define AM335X_IPC_MSG_REG3_OFFSET 0x1334
#define AM335X_IPC_MSG_REG4_OFFSET 0x1338
#define AM335X_IPC_MSG_REG5_OFFSET 0x133C
#define AM335X_IPC_MSG_REG6_OFFSET 0x1340
#define AM335X_IPC_MSG_REG7_OFFSET 0x1344
#define AM335X_DDR_CMD0_IOCTRL_OFFSET 0x1404
#define AM335X_DDR_CMD1_IOCTRL_OFFSET 0x1408
#define AM335X_DDR_CMD2_IOCTRL_OFFSET 0x140C
#define AM335X_DDR_DATA0_IOCTRL_OFFSET 0x1440
#define AM335X_DDR_DATA1_IOCTRL_OFFSET 0x1444
#define AM335X_SCM_CQDETECT_STATUS_OFFSET 0x0e00
#define AM335X_SCM_DDR_IO_CTRL_OFFSET 0x0e04
#define AM335X_SCM_VTP_CTRL_OFFSET 0x0e0c
#define AM335X_SCM_VREF_CTRL_OFFSET 0x0e14
#define AM335X_SCM_TPCC_EVT_MUX_0_3_OFFSET 0x0f90
#define AM335X_SCM_TPCC_EVT_MUX_4_7_OFFSET 0x0f94
#define AM335X_SCM_TPCC_EVT_MUX_8_11_OFFSET 0x0f98
#define AM335X_SCM_TPCC_EVT_MUX_12_15_OFFSET 0x0f9c
#define AM335X_SCM_TPCC_EVT_MUX_16_19_OFFSET 0x0fa0
#define AM335X_SCM_TPCC_EVT_MUX_20_23_OFFSET 0x0fa4
#define AM335X_SCM_TPCC_EVT_MUX_24_27_OFFSET 0x0fa8
#define AM335X_SCM_TPCC_EVT_MUX_28_31_OFFSET 0x0fac
#define AM335X_SCM_TPCC_EVT_MUX_32_35_OFFSET 0x0fb0
#define AM335X_SCM_TPCC_EVT_MUX_36_39_OFFSET 0x0fb4
#define AM335X_SCM_TPCC_EVT_MUX_40_43_OFFSET 0x0fb8
#define AM335X_SCM_TPCC_EVT_MUX_44_47_OFFSET 0x0fbc
#define AM335X_SCM_TPCC_EVT_MUX_48_51_OFFSET 0x0fc0
#define AM335X_SCM_TPCC_EVT_MUX_52_55_OFFSET 0x0fc4
#define AM335X_SCM_TPCC_EVT_MUX_56_59_OFFSET 0x0fc8
#define AM335X_SCM_TPCC_EVT_MUX_60_63_OFFSET 0x0fcc
#define AM335X_SCM_TIMER_EVT_CAPT_OFFSET 0x0fd0
#define AM335X_SCM_ECAP_EVT_CAPT_OFFSET 0x0fd4
#define AM335X_SCM_ADC_EVT_CAPT_OFFSET 0x0fd8
#define AM335X_SCM_RESET_ISO_OFFSET 0x1000
#define AM335X_SCM_DPLL_PWR_SW_CTRL_OFFSET 0x1318
#define AM335X_SCM_DDR_CKE_CTRL_OFFSET 0x131c
#define AM335X_SCM_SMA2_OFFSET 0x1320
#define AM335X_SCM_M3_TXEV_EOI_OFFSET 0x1324
#define AM335X_SCM_IPC_MSG_REG0_OFFSET 0x1328
#define AM335X_SCM_IPC_MSG_REG1_OFFSET 0x132c
#define AM335X_SCM_IPC_MSG_REG2_OFFSET 0x1330
#define AM335X_SCM_IPC_MSG_REG3_OFFSET 0x1334
#define AM335X_SCM_IPC_MSG_REG4_OFFSET 0x1338
#define AM335X_SCM_IPC_MSG_REG5_OFFSET 0x133c
#define AM335X_SCM_IPC_MSG_REG6_OFFSET 0x1340
#define AM335X_SCM_IPC_MSG_REG7_OFFSET 0x1344
#define AM335X_SCM_DDR_CMD0_IOCTRL_OFFSET 0x1404
#define AM335X_SCM_DDR_CMD1_IOCTRL_OFFSET 0x1408
#define AM335X_SCM_DDR_CMD2_IOCTRL_OFFSET 0x140c
#define AM335X_SCM_DDR_DATA0_IOCTRL_OFFSET 0x1440
#define AM335X_SCM_DDR_DATA1_IOCTRL_OFFSET 0x1444
/* Pad Control Registers */
/* Pad Control Register Indices (used by software for table lookups) */
@ -277,220 +277,220 @@
#define AM335X_PADCTL_GPMC_AD0_OFFSET 0x0800
#define AM335X_PADCTL_GPMC_AD1_OFFSET 0x0804
#define AM335X_PADCTL_GPMC_AD2_OFFSET 0x0808
#define AM335X_PADCTL_GPMC_AD3_OFFSET 0x080C
#define AM335X_PADCTL_GPMC_AD3_OFFSET 0x080c
#define AM335X_PADCTL_GPMC_AD4_OFFSET 0x0810
#define AM335X_PADCTL_GPMC_AD5_OFFSET 0x0814
#define AM335X_PADCTL_GPMC_AD6_OFFSET 0x0818
#define AM335X_PADCTL_GPMC_AD7_OFFSET 0x081C
#define AM335X_PADCTL_GPMC_AD7_OFFSET 0x081c
#define AM335X_PADCTL_GPMC_AD8_OFFSET 0x0820
#define AM335X_PADCTL_GPMC_AD9_OFFSET 0x0824
#define AM335X_PADCTL_GPMC_AD10_OFFSET 0x0828
#define AM335X_PADCTL_GPMC_AD11_OFFSET 0x082C
#define AM335X_PADCTL_GPMC_AD11_OFFSET 0x082c
#define AM335X_PADCTL_GPMC_AD12_OFFSET 0x0830
#define AM335X_PADCTL_GPMC_AD13_OFFSET 0x0834
#define AM335X_PADCTL_GPMC_AD14_OFFSET 0x0838
#define AM335X_PADCTL_GPMC_AD15_OFFSET 0x083C
#define AM335X_PADCTL_GPMC_AD15_OFFSET 0x083c
#define AM335X_PADCTL_GPMC_A0_OFFSET 0x0840
#define AM335X_PADCTL_GPMC_A1_OFFSET 0x0844
#define AM335X_PADCTL_GPMC_A2_OFFSET 0x0848
#define AM335X_PADCTL_GPMC_A3_OFFSET 0x084C
#define AM335X_PADCTL_GPMC_A3_OFFSET 0x084c
#define AM335X_PADCTL_GPMC_A4_OFFSET 0x0850
#define AM335X_PADCTL_GPMC_A5_OFFSET 0x0854
#define AM335X_PADCTL_GPMC_A6_OFFSET 0x0858
#define AM335X_PADCTL_GPMC_A7_OFFSET 0x085C
#define AM335X_PADCTL_GPMC_A7_OFFSET 0x085c
#define AM335X_PADCTL_GPMC_A8_OFFSET 0x0860
#define AM335X_PADCTL_GPMC_A9_OFFSET 0x0864
#define AM335X_PADCTL_GPMC_A10_OFFSET 0x0868
#define AM335X_PADCTL_GPMC_A11_OFFSET 0x086C
#define AM335X_PADCTL_GPMC_A11_OFFSET 0x086c
#define AM335X_PADCTL_GPMC_WAIT0_OFFSET 0x0870
#define AM335X_PADCTL_GPMC_WPN_OFFSET 0x0874
#define AM335X_PADCTL_GPMC_BEN1_OFFSET 0x0878
#define AM335X_PADCTL_GPMC_CSN0_OFFSET 0x087C
#define AM335X_PADCTL_GPMC_CSN0_OFFSET 0x087c
#define AM335X_PADCTL_GPMC_CSN1_OFFSET 0x0880
#define AM335X_PADCTL_GPMC_CSN2_OFFSET 0x0884
#define AM335X_PADCTL_GPMC_CSN3_OFFSET 0x0888
#define AM335X_PADCTL_GPMC_CLK_OFFSET 0x088C
#define AM335X_PADCTL_GPMC_CLK_OFFSET 0x088c
#define AM335X_PADCTL_GPMC_ADVN_ALE_OFFSET 0x0890
#define AM335X_PADCTL_GPMC_OEN_REN_OFFSET 0x0894
#define AM335X_PADCTL_GPMC_WEN_OFFSET 0x0898
#define AM335X_PADCTL_GPMC_BEN0_CLE_OFFSET 0x089C
#define AM335X_PADCTL_LCD_DATA0_OFFSET 0x08A0
#define AM335X_PADCTL_LCD_DATA1_OFFSET 0x08A4
#define AM335X_PADCTL_LCD_DATA2_OFFSET 0x08A8
#define AM335X_PADCTL_LCD_DATA3_OFFSET 0x08AC
#define AM335X_PADCTL_LCD_DATA4_OFFSET 0x08B0
#define AM335X_PADCTL_LCD_DATA5_OFFSET 0x08B4
#define AM335X_PADCTL_LCD_DATA6_OFFSET 0x08B8
#define AM335X_PADCTL_LCD_DATA7_OFFSET 0x08BC
#define AM335X_PADCTL_LCD_DATA8_OFFSET 0x08C0
#define AM335X_PADCTL_LCD_DATA9_OFFSET 0x08C4
#define AM335X_PADCTL_LCD_DATA10_OFFSET 0x08C8
#define AM335X_PADCTL_LCD_DATA11_OFFSET 0x08CC
#define AM335X_PADCTL_LCD_DATA12_OFFSET 0x08D0
#define AM335X_PADCTL_LCD_DATA13_OFFSET 0x08D4
#define AM335X_PADCTL_LCD_DATA14_OFFSET 0x08D8
#define AM335X_PADCTL_LCD_DATA15_OFFSET 0x08DC
#define AM335X_PADCTL_LCD_VSYNC_OFFSET 0x08E0
#define AM335X_PADCTL_LCD_HSYNC_OFFSET 0x08E4
#define AM335X_PADCTL_LCD_PCLK_OFFSET 0x08E8
#define AM335X_PADCTL_LCD_AC_BIAS_EN_OFFSET 0x08EC
#define AM335X_PADCTL_MMC0_DAT3_OFFSET 0x08F0
#define AM335X_PADCTL_MMC0_DAT2_OFFSET 0x08F4
#define AM335X_PADCTL_MMC0_DAT1_OFFSET 0x08F8
#define AM335X_PADCTL_MMC0_DAT0_OFFSET 0x08FC
#define AM335X_PADCTL_GPMC_BEN0_CLE_OFFSET 0x089c
#define AM335X_PADCTL_LCD_DATA0_OFFSET 0x08a0
#define AM335X_PADCTL_LCD_DATA1_OFFSET 0x08a4
#define AM335X_PADCTL_LCD_DATA2_OFFSET 0x08a8
#define AM335X_PADCTL_LCD_DATA3_OFFSET 0x08ac
#define AM335X_PADCTL_LCD_DATA4_OFFSET 0x08b0
#define AM335X_PADCTL_LCD_DATA5_OFFSET 0x08b4
#define AM335X_PADCTL_LCD_DATA6_OFFSET 0x08b8
#define AM335X_PADCTL_LCD_DATA7_OFFSET 0x08bc
#define AM335X_PADCTL_LCD_DATA8_OFFSET 0x08c0
#define AM335X_PADCTL_LCD_DATA9_OFFSET 0x08c4
#define AM335X_PADCTL_LCD_DATA10_OFFSET 0x08c8
#define AM335X_PADCTL_LCD_DATA11_OFFSET 0x08cc
#define AM335X_PADCTL_LCD_DATA12_OFFSET 0x08d0
#define AM335X_PADCTL_LCD_DATA13_OFFSET 0x08d4
#define AM335X_PADCTL_LCD_DATA14_OFFSET 0x08d8
#define AM335X_PADCTL_LCD_DATA15_OFFSET 0x08dc
#define AM335X_PADCTL_LCD_VSYNC_OFFSET 0x08e0
#define AM335X_PADCTL_LCD_HSYNC_OFFSET 0x08e4
#define AM335X_PADCTL_LCD_PCLK_OFFSET 0x08e8
#define AM335X_PADCTL_LCD_AC_BIAS_EN_OFFSET 0x08ec
#define AM335X_PADCTL_MMC0_DAT3_OFFSET 0x08f0
#define AM335X_PADCTL_MMC0_DAT2_OFFSET 0x08f4
#define AM335X_PADCTL_MMC0_DAT1_OFFSET 0x08f8
#define AM335X_PADCTL_MMC0_DAT0_OFFSET 0x08fc
#define AM335X_PADCTL_MMC0_CLK_OFFSET 0x0900
#define AM335X_PADCTL_MMC0_CMD_OFFSET 0x0904
#define AM335X_PADCTL_MII1_COL_OFFSET 0x0908
#define AM335X_PADCTL_MII1_CRS_OFFSET 0x090C
#define AM335X_PADCTL_MII1_CRS_OFFSET 0x090c
#define AM335X_PADCTL_MII1_RX_ER_OFFSET 0x0910
#define AM335X_PADCTL_MII1_TX_EN_OFFSET 0x0914
#define AM335X_PADCTL_MII1_RX_DV_OFFSET 0x0918
#define AM335X_PADCTL_MII1_TXD3_OFFSET 0x091C
#define AM335X_PADCTL_MII1_TXD3_OFFSET 0x091c
#define AM335X_PADCTL_MII1_TXD2_OFFSET 0x0920
#define AM335X_PADCTL_MII1_TXD1_OFFSET 0x0924
#define AM335X_PADCTL_MII1_TXD0_OFFSET 0x0928
#define AM335X_PADCTL_MII1_TX_CLK_OFFSET 0x092C
#define AM335X_PADCTL_MII1_TX_CLK_OFFSET 0x092c
#define AM335X_PADCTL_MII1_RX_CLK_OFFSET 0x0930
#define AM335X_PADCTL_MII1_RXD3_OFFSET 0x0934
#define AM335X_PADCTL_MII1_RXD2_OFFSET 0x0938
#define AM335X_PADCTL_MII1_RXD1_OFFSET 0x093C
#define AM335X_PADCTL_MII1_RXD1_OFFSET 0x093c
#define AM335X_PADCTL_MII1_RXD0_OFFSET 0x0940
#define AM335X_PADCTL_RMII1_REF_CLK_OFFSET 0x0944
#define AM335X_PADCTL_MDIO_OFFSET 0x0948
#define AM335X_PADCTL_MDC_OFFSET 0x094C
#define AM335X_PADCTL_MDC_OFFSET 0x094c
#define AM335X_PADCTL_SPI0_SCLK_OFFSET 0x0950
#define AM335X_PADCTL_SPI0_D0_OFFSET 0x0954
#define AM335X_PADCTL_SPI0_D1_OFFSET 0x0958
#define AM335X_PADCTL_SPI0_CS0_OFFSET 0x095C
#define AM335X_PADCTL_SPI0_CS0_OFFSET 0x095c
#define AM335X_PADCTL_SPI0_CS1_OFFSET 0x0960
#define AM335X_PADCTL_ECAP0_IN_PWM0_OUT_OFFSET 0x0964
#define AM335X_PADCTL_UART0_CTSN_OFFSET 0x0968
#define AM335X_PADCTL_UART0_RTSN_OFFSET 0x096C
#define AM335X_PADCTL_UART0_RTSN_OFFSET 0x096c
#define AM335X_PADCTL_UART0_RXD_OFFSET 0x0970
#define AM335X_PADCTL_UART0_TXD_OFFSET 0x0974
#define AM335X_PADCTL_UART1_CTSN_OFFSET 0x0978
#define AM335X_PADCTL_UART1_RTSN_OFFSET 0x097C
#define AM335X_PADCTL_UART1_RTSN_OFFSET 0x097c
#define AM335X_PADCTL_UART1_RXD_OFFSET 0x0980
#define AM335X_PADCTL_UART1_TXD_OFFSET 0x0984
#define AM335X_PADCTL_I2C0_SDA_OFFSET 0x0988
#define AM335X_PADCTL_I2C0_SCL_OFFSET 0x098C
#define AM335X_PADCTL_I2C0_SCL_OFFSET 0x098c
#define AM335X_PADCTL_MCASP0_ACLKX_OFFSET 0x0990
#define AM335X_PADCTL_MCASP0_FSX_OFFSET 0x0994
#define AM335X_PADCTL_MCASP0_AXR0_OFFSET 0x0998
#define AM335X_PADCTL_MCASP0_AHCLKR_OFFSET 0x099C
#define AM335X_PADCTL_MCASP0_ACLKR_OFFSET 0x09A0
#define AM335X_PADCTL_MCASP0_FSR_OFFSET 0x09A4
#define AM335X_PADCTL_MCASP0_AXR1_OFFSET 0x09A8
#define AM335X_PADCTL_MCASP0_AhCLKX_OFFSET 0x09AC
#define AM335X_PADCTL_XDMA_EVENT_INTR0_OFFSET 0x09B0
#define AM335X_PADCTL_XDMA_EVENT_INTR1_OFFSET 0x09B4
#define AM335X_PADCTL_WARMRSTN_OFFSET 0x09B8
#define AM335X_PADCTL_NNMI_OFFSET 0x09C0
#define AM335X_PADCTL_TMS_OFFSET 0x09D0
#define AM335X_PADCTL_TDI_OFFSET 0x09D4
#define AM335X_PADCTL_TDO_OFFSET 0x09D8
#define AM335X_PADCTL_TCK_OFFSET 0x09DC
#define AM335X_PADCTL_TRSTN_OFFSET 0x09E0
#define AM335X_PADCTL_EMU0_OFFSET 0x09E4
#define AM335X_PADCTL_EMU1_OFFSET 0x09E8
#define AM335X_PADCTL_RTC_PWRONRSTN_OFFSET 0x09F8
#define AM335X_PADCTL_PMIC_POWER_EN_OFFSET 0x09FC
#define AM335X_PADCTL_EXT_WAKEUP_OFFSET 0x0A00
#define AM335X_PADCTL_RTC_KALDO_ENN_OFFSET 0x0A04
#define AM335X_PADCTL_USB0_DRVVBUS_OFFSET 0x0A1C
#define AM335X_PADCTL_USB1_DRVVBUS_OFFSET 0x0A34
#define AM335X_PADCTL_MCASP0_AHCLKR_OFFSET 0x099c
#define AM335X_PADCTL_MCASP0_ACLKR_OFFSET 0x09a0
#define AM335X_PADCTL_MCASP0_FSR_OFFSET 0x09a4
#define AM335X_PADCTL_MCASP0_AXR1_OFFSET 0x09a8
#define AM335X_PADCTL_MCASP0_AhCLKX_OFFSET 0x09ac
#define AM335X_PADCTL_XDMA_EVENT_INTR0_OFFSET 0x09b0
#define AM335X_PADCTL_XDMA_EVENT_INTR1_OFFSET 0x09b4
#define AM335X_PADCTL_WARMRSTN_OFFSET 0x09b8
#define AM335X_PADCTL_NNMI_OFFSET 0x09c0
#define AM335X_PADCTL_TMS_OFFSET 0x09d0
#define AM335X_PADCTL_TDI_OFFSET 0x09d4
#define AM335X_PADCTL_TDO_OFFSET 0x09d8
#define AM335X_PADCTL_TCK_OFFSET 0x09dc
#define AM335X_PADCTL_TRSTN_OFFSET 0x09e0
#define AM335X_PADCTL_EMU0_OFFSET 0x09e4
#define AM335X_PADCTL_EMU1_OFFSET 0x09e8
#define AM335X_PADCTL_RTC_PWRONRSTN_OFFSET 0x09f8
#define AM335X_PADCTL_PMIC_POWER_EN_OFFSET 0x09fc
#define AM335X_PADCTL_EXT_WAKEUP_OFFSET 0x0a00
#define AM335X_PADCTL_RTC_KALDO_ENN_OFFSET 0x0a04
#define AM335X_PADCTL_USB0_DRVVBUS_OFFSET 0x0a1c
#define AM335X_PADCTL_USB1_DRVVBUS_OFFSET 0x0a34
/* Control Module Register Addresses ********************************************************/
#define AM335X_CONTROL_SYS_CONF (AM335X_CONTROL_MODULE_VADDR + AM335X_CONTROL_SYS_CONF_OFFSET)
#define AM335X_CONTROL_STATUS (AM335X_CONTROL_MODULE_VADDR + AM335X_CONTROL_STATUS_OFFSET)
#define AM335X_CONTROL_EMIF_SDRAM_CONF (AM335X_CONTROL_MODULE_VADDR + AM335X_CONTROL_EMIF_SDRAM_CONF_OFFSET)
#define AM335X_CORE_SLDO_CTRL (AM335X_CONTROL_MODULE_VADDR + AM335X_CORE_SLDO_CTRL_OFFSET)
#define AM335X_MPU_SLDO_CTRL (AM335X_CONTROL_MODULE_VADDR + AM335X_MPU_SLDO_CTRL_OFFSET)
#define AM335X_CLK32KDIVRATIO_CTRL (AM335X_CONTROL_MODULE_VADDR + AM335X_CLK32KDIVRATIO_CTRL_OFFSET)
#define AM335X_BANDGAP_CTRL (AM335X_CONTROL_MODULE_VADDR + AM335X_BANDGAP_CTRL_OFFSET)
#define AM335X_BANDGAP_TRIM (AM335X_CONTROL_MODULE_VADDR + AM335X_BANDGAP_TRIM_OFFSET)
#define AM335X_PLL_CLKINPULOW_CTRL (AM335X_CONTROL_MODULE_VADDR + AM335X_PLL_CLKINPULOW_CTRL_OFFSET)
#define AM335X_MOSC_CTRL (AM335X_CONTROL_MODULE_VADDR + AM335X_MOSC_CTRL_OFFSET)
#define AM335X_DEEPSLEEP_CTRL (AM335X_CONTROL_MODULE_VADDR + AM335X_DEEPSLEEP_CTRL_OFFSET)
#define AM335X_DPLL_PWR_SW_STATUS (AM335X_CONTROL_MODULE_VADDR + AM335X_DPLL_PWR_SW_STATUS_OFFSET)
#define AM335X_DEVICE_ID (AM335X_CONTROL_MODULE_VADDR + AM335X_DEVICE_ID_OFFSET)
#define AM335X_DEV_FEATURE (AM335X_CONTROL_MODULE_VADDR + AM335X_DEV_FEATURE_OFFSET)
#define AM335X_INIT_PRIORITY_0 (AM335X_CONTROL_MODULE_VADDR + AM335X_INIT_PRIORITY_0_OFFSET)
#define AM335X_INIT_PRIORITY_1 (AM335X_CONTROL_MODULE_VADDR + AM335X_INIT_PRIORITY_1_OFFSET)
#define AM335X_TPTC_CFG (AM335X_CONTROL_MODULE_VADDR + AM335X_TPTC_CFG_OFFSET)
#define AM335X_USB_CTRL0 (AM335X_CONTROL_MODULE_VADDR + AM335X_USB_CTRL0_OFFSET)
#define AM335X_USB_STS0 (AM335X_CONTROL_MODULE_VADDR + AM335X_USB_STS0_OFFSET)
#define AM335X_USB_CTRL1 (AM335X_CONTROL_MODULE_VADDR + AM335X_USB_CTRL1_OFFSET)
#define AM335X_USB_STS1 (AM335X_CONTROL_MODULE_VADDR + AM335X_USB_STS1_OFFSET)
#define AM335X_MAC_ID0_LO (AM335X_CONTROL_MODULE_VADDR + AM335X_MAC_ID0_LO_OFFSET)
#define AM335X_MAC_ID0_HI (AM335X_CONTROL_MODULE_VADDR + AM335X_MAC_ID0_HI_OFFSET)
#define AM335X_MAC_ID1_LO (AM335X_CONTROL_MODULE_VADDR + AM335X_MAC_ID1_LO_OFFSET)
#define AM335X_MAC_ID1_HI (AM335X_CONTROL_MODULE_VADDR + AM335X_MAC_ID1_HI_OFFSET)
#define AM335X_DCAN_RAMINIT (AM335X_CONTROL_MODULE_VADDR + AM335X_DCAN_RAMINIT_OFFSET)
#define AM335X_USB_WKUP_CTRL (AM335X_CONTROL_MODULE_VADDR + AM335X_USB_WKUP_CTRL_OFFSET)
#define AM335X_GMII_SEL (AM335X_CONTROL_MODULE_VADDR + AM335X_GMII_SEL_OFFSET)
#define AM335X_PWMSS_CTRL (AM335X_CONTROL_MODULE_VADDR + AM335X_PWMSS_CTRL_OFFSET)
#define AM335X_MREGPRIO_0 (AM335X_CONTROL_MODULE_VADDR + AM335X_MREGPRIO_0_OFFSET)
#define AM335X_MREGPRIO_1 (AM335X_CONTROL_MODULE_VADDR + AM335X_MREGPRIO_1_OFFSET)
#define AM335X_HW_EVENT_SEL_GRP1 (AM335X_CONTROL_MODULE_VADDR + AM335X_HW_EVENT_SEL_GRP1_OFFSET)
#define AM335X_HW_EVENT_SEL_GRP2 (AM335X_CONTROL_MODULE_VADDR + AM335X_HW_EVENT_SEL_GRP2_OFFSET)
#define AM335X_HW_EVENT_SEL_GRP3 (AM335X_CONTROL_MODULE_VADDR + AM335X_HW_EVENT_SEL_GRP3_OFFSET)
#define AM335X_HW_EVENT_SEL_GRP4 (AM335X_CONTROL_MODULE_VADDR + AM335X_HW_EVENT_SEL_GRP4_OFFSET)
#define AM335X_SMRT_CTRL (AM335X_CONTROL_MODULE_VADDR + AM335X_SMRT_CTRL_OFFSET)
#define AM335X_MPUSS_HW_DEBUG_SEL (AM335X_CONTROL_MODULE_VADDR + AM335X_MPUSS_HW_DEBUG_SEL_OFFSET)
#define AM335X_MPUSS_HW_DBG_INFO (AM335X_CONTROL_MODULE_VADDR + AM335X_MPUSS_HW_DBG_INFO_OFFSET)
#define AM335X_VDD_MPU_OPP_050 (AM335X_CONTROL_MODULE_VADDR + AM335X_VDD_MPU_OPP_050_OFFSET)
#define AM335X_VDD_MPU_OPP_100 (AM335X_CONTROL_MODULE_VADDR + AM335X_VDD_MPU_OPP_100_OFFSET)
#define AM335X_VDD_MPU_OPP_120 (AM335X_CONTROL_MODULE_VADDR + AM335X_VDD_MPU_OPP_120_OFFSET)
#define AM335X_VDD_MPU_OPP_TURBO (AM335X_CONTROL_MODULE_VADDR + AM335X_VDD_MPU_OPP_TURBO_OFFSET)
#define AM335X_VDD_CORE_OPP_050 (AM335X_CONTROL_MODULE_VADDR + AM335X_VDD_CORE_OPP_050_OFFSET)
#define AM335X_VDD_CORE_OPP_100 (AM335X_CONTROL_MODULE_VADDR + AM335X_VDD_CORE_OPP_100_OFFSET)
#define AM335X_BB_SCALE (AM335X_CONTROL_MODULE_VADDR + AM335X_BB_SCALE_OFFSET)
#define AM335X_USB_VID_PID (AM335X_CONTROL_MODULE_VADDR + AM335X_USB_VID_PID_OFFSET)
#define AM335X_EFUSE_SMA (AM335X_CONTROL_MODULE_VADDR + AM335X_EFUSE_SMA_OFFSET)
#define AM335X_SCM_CTRL_SYS_CONF (AM335X_CONTROL_MODULE_VADDR + AM335X_SCM_CTRL_SYS_CONF_OFFSET)
#define AM335X_SCM_CTRL_STATUS (AM335X_CONTROL_MODULE_VADDR + AM335X_SCM_CTRL_STATUS_OFFSET)
#define AM335X_SCM_CTRL_EMIF_SDRAM_CONF (AM335X_CONTROL_MODULE_VADDR + AM335X_SCM_CTRL_EMIF_SDRAM_CONF_OFFSET)
#define AM335X_SCM_CORE_SLDO_CTRL (AM335X_CONTROL_MODULE_VADDR + AM335X_SCM_CORE_SLDO_CTRL_OFFSET)
#define AM335X_SCM_MPU_SLDO_CTRL (AM335X_CONTROL_MODULE_VADDR + AM335X_SCM_MPU_SLDO_CTRL_OFFSET)
#define AM335X_SCM_CLK32KDIVRATIO_CTRL (AM335X_CONTROL_MODULE_VADDR + AM335X_SCM_CLK32KDIVRATIO_CTRL_OFFSET)
#define AM335X_SCM_BANDGAP_CTRL (AM335X_CONTROL_MODULE_VADDR + AM335X_SCM_BANDGAP_CTRL_OFFSET)
#define AM335X_SCM_BANDGAP_TRIM (AM335X_CONTROL_MODULE_VADDR + AM335X_SCM_BANDGAP_TRIM_OFFSET)
#define AM335X_SCM_PLL_CLKINPULOW_CTRL (AM335X_CONTROL_MODULE_VADDR + AM335X_SCM_PLL_CLKINPULOW_CTRL_OFFSET)
#define AM335X_SCM_MOSC_CTRL (AM335X_CONTROL_MODULE_VADDR + AM335X_SCM_MOSC_CTRL_OFFSET)
#define AM335X_SCM_DEEPSLEEP_CTRL (AM335X_CONTROL_MODULE_VADDR + AM335X_SCM_DEEPSLEEP_CTRL_OFFSET)
#define AM335X_SCM_DPLL_PWR_SW_STATUS (AM335X_CONTROL_MODULE_VADDR + AM335X_SCM_DPLL_PWR_SW_STATUS_OFFSET)
#define AM335X_SCM_DEVICE_ID (AM335X_CONTROL_MODULE_VADDR + AM335X_SCM_DEVICE_ID_OFFSET)
#define AM335X_SCM_DEV_FEATURE (AM335X_CONTROL_MODULE_VADDR + AM335X_SCM_DEV_FEATURE_OFFSET)
#define AM335X_SCM_INIT_PRIORITY_0 (AM335X_CONTROL_MODULE_VADDR + AM335X_SCM_INIT_PRIORITY_0_OFFSET)
#define AM335X_SCM_INIT_PRIORITY_1 (AM335X_CONTROL_MODULE_VADDR + AM335X_SCM_INIT_PRIORITY_1_OFFSET)
#define AM335X_SCM_TPTC_CFG (AM335X_CONTROL_MODULE_VADDR + AM335X_SCM_TPTC_CFG_OFFSET)
#define AM335X_SCM_USB_CTRL0 (AM335X_CONTROL_MODULE_VADDR + AM335X_SCM_USB_CTRL0_OFFSET)
#define AM335X_SCM_USB_STS0 (AM335X_CONTROL_MODULE_VADDR + AM335X_SCM_USB_STS0_OFFSET)
#define AM335X_SCM_USB_CTRL1 (AM335X_CONTROL_MODULE_VADDR + AM335X_SCM_USB_CTRL1_OFFSET)
#define AM335X_SCM_USB_STS1 (AM335X_CONTROL_MODULE_VADDR + AM335X_SCM_USB_STS1_OFFSET)
#define AM335X_SCM_MAC_ID0_LO (AM335X_CONTROL_MODULE_VADDR + AM335X_SCM_MAC_ID0_LO_OFFSET)
#define AM335X_SCM_MAC_ID0_HI (AM335X_CONTROL_MODULE_VADDR + AM335X_SCM_MAC_ID0_HI_OFFSET)
#define AM335X_SCM_MAC_ID1_LO (AM335X_CONTROL_MODULE_VADDR + AM335X_SCM_MAC_ID1_LO_OFFSET)
#define AM335X_SCM_MAC_ID1_HI (AM335X_CONTROL_MODULE_VADDR + AM335X_SCM_MAC_ID1_HI_OFFSET)
#define AM335X_SCM_DCAN_RAMINIT (AM335X_CONTROL_MODULE_VADDR + AM335X_SCM_DCAN_RAMINIT_OFFSET)
#define AM335X_SCM_USB_WKUP_CTRL (AM335X_CONTROL_MODULE_VADDR + AM335X_SCM_USB_WKUP_CTRL_OFFSET)
#define AM335X_SCM_GMII_SEL (AM335X_CONTROL_MODULE_VADDR + AM335X_SCM_GMII_SEL_OFFSET)
#define AM335X_SCM_PWMSS_CTRL (AM335X_CONTROL_MODULE_VADDR + AM335X_SCM_PWMSS_CTRL_OFFSET)
#define AM335X_SCM_MREGPRIO_0 (AM335X_CONTROL_MODULE_VADDR + AM335X_SCM_MREGPRIO_0_OFFSET)
#define AM335X_SCM_MREGPRIO_1 (AM335X_CONTROL_MODULE_VADDR + AM335X_SCM_MREGPRIO_1_OFFSET)
#define AM335X_SCM_HW_EVENT_SEL_GRP1 (AM335X_CONTROL_MODULE_VADDR + AM335X_SCM_HW_EVENT_SEL_GRP1_OFFSET)
#define AM335X_SCM_HW_EVENT_SEL_GRP2 (AM335X_CONTROL_MODULE_VADDR + AM335X_SCM_HW_EVENT_SEL_GRP2_OFFSET)
#define AM335X_SCM_HW_EVENT_SEL_GRP3 (AM335X_CONTROL_MODULE_VADDR + AM335X_SCM_HW_EVENT_SEL_GRP3_OFFSET)
#define AM335X_SCM_HW_EVENT_SEL_GRP4 (AM335X_CONTROL_MODULE_VADDR + AM335X_SCM_HW_EVENT_SEL_GRP4_OFFSET)
#define AM335X_SCM_SMRT_CTRL (AM335X_CONTROL_MODULE_VADDR + AM335X_SCM_SMRT_CTRL_OFFSET)
#define AM335X_SCM_MPUSS_HW_DEBUG_SEL (AM335X_CONTROL_MODULE_VADDR + AM335X_SCM_MPUSS_HW_DEBUG_SEL_OFFSET)
#define AM335X_SCM_MPUSS_HW_DBG_INFO (AM335X_CONTROL_MODULE_VADDR + AM335X_SCM_MPUSS_HW_DBG_INFO_OFFSET)
#define AM335X_SCM_VDD_MPU_OPP_050 (AM335X_CONTROL_MODULE_VADDR + AM335X_SCM_VDD_MPU_OPP_050_OFFSET)
#define AM335X_SCM_VDD_MPU_OPP_100 (AM335X_CONTROL_MODULE_VADDR + AM335X_SCM_VDD_MPU_OPP_100_OFFSET)
#define AM335X_SCM_VDD_MPU_OPP_120 (AM335X_CONTROL_MODULE_VADDR + AM335X_SCM_VDD_MPU_OPP_120_OFFSET)
#define AM335X_SCM_VDD_MPU_OPP_TURBO (AM335X_CONTROL_MODULE_VADDR + AM335X_SCM_VDD_MPU_OPP_TURBO_OFFSET)
#define AM335X_SCM_VDD_CORE_OPP_050 (AM335X_CONTROL_MODULE_VADDR + AM335X_SCM_VDD_CORE_OPP_050_OFFSET)
#define AM335X_SCM_VDD_CORE_OPP_100 (AM335X_CONTROL_MODULE_VADDR + AM335X_SCM_VDD_CORE_OPP_100_OFFSET)
#define AM335X_SCM_BB_SCALE (AM335X_CONTROL_MODULE_VADDR + AM335X_SCM_BB_SCALE_OFFSET)
#define AM335X_SCM_USB_VID_PID (AM335X_CONTROL_MODULE_VADDR + AM335X_SCM_USB_VID_PID_OFFSET)
#define AM335X_SCM_EFUSE_SMA (AM335X_CONTROL_MODULE_VADDR + AM335X_SCM_EFUSE_SMA_OFFSET)
#define AM335X_CQDETECT_STATUS (AM335X_CONTROL_MODULE_VADDR + AM335X_CQDETECT_STATUS_OFFSET)
#define AM335X_DDR_IO_CTRL (AM335X_CONTROL_MODULE_VADDR + AM335X_DDR_IO_CTRL_OFFSET)
#define AM335X_VTP_CTRL (AM335X_CONTROL_MODULE_VADDR + AM335X_VTP_CTRL_OFFSET)
#define AM335X_VREF_CTRL (AM335X_CONTROL_MODULE_VADDR + AM335X_VREF_CTRL_OFFSET)
#define AM335X_TPCC_EVT_MUX_0_3 (AM335X_CONTROL_MODULE_VADDR + AM335X_TPCC_EVT_MUX_0_3_OFFSET)
#define AM335X_TPCC_EVT_MUX_4_7 (AM335X_CONTROL_MODULE_VADDR + AM335X_TPCC_EVT_MUX_4_7_OFFSET)
#define AM335X_TPCC_EVT_MUX_8_11 (AM335X_CONTROL_MODULE_VADDR + AM335X_TPCC_EVT_MUX_8_11_OFFSET)
#define AM335X_TPCC_EVT_MUX_12_15 (AM335X_CONTROL_MODULE_VADDR + AM335X_TPCC_EVT_MUX_12_15_OFFSET)
#define AM335X_TPCC_EVT_MUX_16_19 (AM335X_CONTROL_MODULE_VADDR + AM335X_TPCC_EVT_MUX_16_19_OFFSET)
#define AM335X_TPCC_EVT_MUX_20_23 (AM335X_CONTROL_MODULE_VADDR + AM335X_TPCC_EVT_MUX_20_23_OFFSET)
#define AM335X_TPCC_EVT_MUX_24_27 (AM335X_CONTROL_MODULE_VADDR + AM335X_TPCC_EVT_MUX_24_27_OFFSET)
#define AM335X_TPCC_EVT_MUX_28_31 (AM335X_CONTROL_MODULE_VADDR + AM335X_TPCC_EVT_MUX_28_31_OFFSET)
#define AM335X_TPCC_EVT_MUX_32_35 (AM335X_CONTROL_MODULE_VADDR + AM335X_TPCC_EVT_MUX_32_35_OFFSET)
#define AM335X_TPCC_EVT_MUX_36_39 (AM335X_CONTROL_MODULE_VADDR + AM335X_TPCC_EVT_MUX_36_39_OFFSET)
#define AM335X_TPCC_EVT_MUX_40_43 (AM335X_CONTROL_MODULE_VADDR + AM335X_TPCC_EVT_MUX_40_43_OFFSET)
#define AM335X_TPCC_EVT_MUX_44_47 (AM335X_CONTROL_MODULE_VADDR + AM335X_TPCC_EVT_MUX_44_47_OFFSET)
#define AM335X_TPCC_EVT_MUX_48_51 (AM335X_CONTROL_MODULE_VADDR + AM335X_TPCC_EVT_MUX_48_51_OFFSET)
#define AM335X_TPCC_EVT_MUX_52_55 (AM335X_CONTROL_MODULE_VADDR + AM335X_TPCC_EVT_MUX_52_55_OFFSET)
#define AM335X_TPCC_EVT_MUX_56_59 (AM335X_CONTROL_MODULE_VADDR + AM335X_TPCC_EVT_MUX_56_59_OFFSET)
#define AM335X_TPCC_EVT_MUX_60_63 (AM335X_CONTROL_MODULE_VADDR + AM335X_TPCC_EVT_MUX_60_63_OFFSET)
#define AM335X_TIMER_EVT_CAPT (AM335X_CONTROL_MODULE_VADDR + AM335X_TIMER_EVT_CAPT_OFFSET)
#define AM335X_ECAP_EVT_CAPT (AM335X_CONTROL_MODULE_VADDR + AM335X_ECAP_EVT_CAPT_OFFSET)
#define AM335X_ADC_EVT_CAPT (AM335X_CONTROL_MODULE_VADDR + AM335X_ADC_EVT_CAPT_OFFSET)
#define AM335X_RESET_ISO (AM335X_CONTROL_MODULE_VADDR + AM335X_RESET_ISO_OFFSET)
#define AM335X_DPLL_PWR_SW_CTRL (AM335X_CONTROL_MODULE_VADDR + AM335X_DPLL_PWR_SW_CTRL_OFFSET)
#define AM335X_DDR_CKE_CTRL (AM335X_CONTROL_MODULE_VADDR + AM335X_DDR_CKE_CTRL_OFFSET)
#define AM335X_SMA2 (AM335X_CONTROL_MODULE_VADDR + AM335X_SMA2_OFFSET)
#define AM335X_M3_TXEV_EOI (AM335X_CONTROL_MODULE_VADDR + AM335X_M3_TXEV_EOI_OFFSET)
#define AM335X_IPC_MSG_REG0 (AM335X_CONTROL_MODULE_VADDR + AM335X_IPC_MSG_REG0_OFFSET)
#define AM335X_IPC_MSG_REG1 (AM335X_CONTROL_MODULE_VADDR + AM335X_IPC_MSG_REG1_OFFSET)
#define AM335X_IPC_MSG_REG2 (AM335X_CONTROL_MODULE_VADDR + AM335X_IPC_MSG_REG2_OFFSET)
#define AM335X_IPC_MSG_REG3 (AM335X_CONTROL_MODULE_VADDR + AM335X_IPC_MSG_REG3_OFFSET)
#define AM335X_IPC_MSG_REG4 (AM335X_CONTROL_MODULE_VADDR + AM335X_IPC_MSG_REG4_OFFSET)
#define AM335X_IPC_MSG_REG5 (AM335X_CONTROL_MODULE_VADDR + AM335X_IPC_MSG_REG5_OFFSET)
#define AM335X_IPC_MSG_REG6 (AM335X_CONTROL_MODULE_VADDR + AM335X_IPC_MSG_REG6_OFFSET)
#define AM335X_IPC_MSG_REG7 (AM335X_CONTROL_MODULE_VADDR + AM335X_IPC_MSG_REG7_OFFSET)
#define AM335X_DDR_CMD0_IOCTRL (AM335X_CONTROL_MODULE_VADDR + AM335X_DDR_CMD0_IOCTRL_OFFSET)
#define AM335X_DDR_CMD1_IOCTRL (AM335X_CONTROL_MODULE_VADDR + AM335X_DDR_CMD1_IOCTRL_OFFSET)
#define AM335X_DDR_CMD2_IOCTRL (AM335X_CONTROL_MODULE_VADDR + AM335X_DDR_CMD2_IOCTRL_OFFSET)
#define AM335X_DDR_DATA0_IOCTRL (AM335X_CONTROL_MODULE_VADDR + AM335X_DDR_DATA0_IOCTRL_OFFSET)
#define AM335X_DDR_DATA1_IOCTRL (AM335X_CONTROL_MODULE_VADDR + AM335X_DDR_DATA1_IOCTRL_OFFSET)
#define AM335X_SCM_CQDETECT_STATUS (AM335X_CONTROL_MODULE_VADDR + AM335X_SCM_CQDETECT_STATUS_OFFSET)
#define AM335X_SCM_DDR_IO_CTRL (AM335X_CONTROL_MODULE_VADDR + AM335X_SCM_DDR_IO_CTRL_OFFSET)
#define AM335X_SCM_VTP_CTRL (AM335X_CONTROL_MODULE_VADDR + AM335X_SCM_VTP_CTRL_OFFSET)
#define AM335X_SCM_VREF_CTRL (AM335X_CONTROL_MODULE_VADDR + AM335X_SCM_VREF_CTRL_OFFSET)
#define AM335X_SCM_TPCC_EVT_MUX_0_3 (AM335X_CONTROL_MODULE_VADDR + AM335X_SCM_TPCC_EVT_MUX_0_3_OFFSET)
#define AM335X_SCM_TPCC_EVT_MUX_4_7 (AM335X_CONTROL_MODULE_VADDR + AM335X_SCM_TPCC_EVT_MUX_4_7_OFFSET)
#define AM335X_SCM_TPCC_EVT_MUX_8_11 (AM335X_CONTROL_MODULE_VADDR + AM335X_SCM_TPCC_EVT_MUX_8_11_OFFSET)
#define AM335X_SCM_TPCC_EVT_MUX_12_15 (AM335X_CONTROL_MODULE_VADDR + AM335X_SCM_TPCC_EVT_MUX_12_15_OFFSET)
#define AM335X_SCM_TPCC_EVT_MUX_16_19 (AM335X_CONTROL_MODULE_VADDR + AM335X_SCM_TPCC_EVT_MUX_16_19_OFFSET)
#define AM335X_SCM_TPCC_EVT_MUX_20_23 (AM335X_CONTROL_MODULE_VADDR + AM335X_SCM_TPCC_EVT_MUX_20_23_OFFSET)
#define AM335X_SCM_TPCC_EVT_MUX_24_27 (AM335X_CONTROL_MODULE_VADDR + AM335X_SCM_TPCC_EVT_MUX_24_27_OFFSET)
#define AM335X_SCM_TPCC_EVT_MUX_28_31 (AM335X_CONTROL_MODULE_VADDR + AM335X_SCM_TPCC_EVT_MUX_28_31_OFFSET)
#define AM335X_SCM_TPCC_EVT_MUX_32_35 (AM335X_CONTROL_MODULE_VADDR + AM335X_SCM_TPCC_EVT_MUX_32_35_OFFSET)
#define AM335X_SCM_TPCC_EVT_MUX_36_39 (AM335X_CONTROL_MODULE_VADDR + AM335X_SCM_TPCC_EVT_MUX_36_39_OFFSET)
#define AM335X_SCM_TPCC_EVT_MUX_40_43 (AM335X_CONTROL_MODULE_VADDR + AM335X_SCM_TPCC_EVT_MUX_40_43_OFFSET)
#define AM335X_SCM_TPCC_EVT_MUX_44_47 (AM335X_CONTROL_MODULE_VADDR + AM335X_SCM_TPCC_EVT_MUX_44_47_OFFSET)
#define AM335X_SCM_TPCC_EVT_MUX_48_51 (AM335X_CONTROL_MODULE_VADDR + AM335X_SCM_TPCC_EVT_MUX_48_51_OFFSET)
#define AM335X_SCM_TPCC_EVT_MUX_52_55 (AM335X_CONTROL_MODULE_VADDR + AM335X_SCM_TPCC_EVT_MUX_52_55_OFFSET)
#define AM335X_SCM_TPCC_EVT_MUX_56_59 (AM335X_CONTROL_MODULE_VADDR + AM335X_SCM_TPCC_EVT_MUX_56_59_OFFSET)
#define AM335X_SCM_TPCC_EVT_MUX_60_63 (AM335X_CONTROL_MODULE_VADDR + AM335X_SCM_TPCC_EVT_MUX_60_63_OFFSET)
#define AM335X_SCM_TIMER_EVT_CAPT (AM335X_CONTROL_MODULE_VADDR + AM335X_SCM_TIMER_EVT_CAPT_OFFSET)
#define AM335X_SCM_ECAP_EVT_CAPT (AM335X_CONTROL_MODULE_VADDR + AM335X_SCM_ECAP_EVT_CAPT_OFFSET)
#define AM335X_SCM_ADC_EVT_CAPT (AM335X_CONTROL_MODULE_VADDR + AM335X_SCM_ADC_EVT_CAPT_OFFSET)
#define AM335X_SCM_RESET_ISO (AM335X_CONTROL_MODULE_VADDR + AM335X_SCM_RESET_ISO_OFFSET)
#define AM335X_SCM_DPLL_PWR_SW_CTRL (AM335X_CONTROL_MODULE_VADDR + AM335X_SCM_DPLL_PWR_SW_CTRL_OFFSET)
#define AM335X_SCM_DDR_CKE_CTRL (AM335X_CONTROL_MODULE_VADDR + AM335X_SCM_DDR_CKE_CTRL_OFFSET)
#define AM335X_SCM_SMA2 (AM335X_CONTROL_MODULE_VADDR + AM335X_SCM_SMA2_OFFSET)
#define AM335X_SCM_M3_TXEV_EOI (AM335X_CONTROL_MODULE_VADDR + AM335X_SCM_M3_TXEV_EOI_OFFSET)
#define AM335X_SCM_IPC_MSG_REG0 (AM335X_CONTROL_MODULE_VADDR + AM335X_SCM_IPC_MSG_REG0_OFFSET)
#define AM335X_SCM_IPC_MSG_REG1 (AM335X_CONTROL_MODULE_VADDR + AM335X_SCM_IPC_MSG_REG1_OFFSET)
#define AM335X_SCM_IPC_MSG_REG2 (AM335X_CONTROL_MODULE_VADDR + AM335X_SCM_IPC_MSG_REG2_OFFSET)
#define AM335X_SCM_IPC_MSG_REG3 (AM335X_CONTROL_MODULE_VADDR + AM335X_SCM_IPC_MSG_REG3_OFFSET)
#define AM335X_SCM_IPC_MSG_REG4 (AM335X_CONTROL_MODULE_VADDR + AM335X_SCM_IPC_MSG_REG4_OFFSET)
#define AM335X_SCM_IPC_MSG_REG5 (AM335X_CONTROL_MODULE_VADDR + AM335X_SCM_IPC_MSG_REG5_OFFSET)
#define AM335X_SCM_IPC_MSG_REG6 (AM335X_CONTROL_MODULE_VADDR + AM335X_SCM_IPC_MSG_REG6_OFFSET)
#define AM335X_SCM_IPC_MSG_REG7 (AM335X_CONTROL_MODULE_VADDR + AM335X_SCM_IPC_MSG_REG7_OFFSET)
#define AM335X_SCM_DDR_CMD0_IOCTRL (AM335X_CONTROL_MODULE_VADDR + AM335X_SCM_DDR_CMD0_IOCTRL_OFFSET)
#define AM335X_SCM_DDR_CMD1_IOCTRL (AM335X_CONTROL_MODULE_VADDR + AM335X_SCM_DDR_CMD1_IOCTRL_OFFSET)
#define AM335X_SCM_DDR_CMD2_IOCTRL (AM335X_CONTROL_MODULE_VADDR + AM335X_SCM_DDR_CMD2_IOCTRL_OFFSET)
#define AM335X_SCM_DDR_DATA0_IOCTRL (AM335X_CONTROL_MODULE_VADDR + AM335X_SCM_DDR_DATA0_IOCTRL_OFFSET)
#define AM335X_SCM_DDR_DATA1_IOCTRL (AM335X_CONTROL_MODULE_VADDR + AM335X_SCM_DDR_DATA1_IOCTRL_OFFSET)
/* Pad Control Registers */
@ -624,6 +624,15 @@
/* Control Module Register Bit Definitions **************************************************/
/* Control Status Fields */
#define SCM_CTRL_STATUS_SYSBOOT1_SHIFT (22) /* Bits 22-23: Crystal clock frequency selection */
#define SCM_CTRL_STATUS_SYSBOOT1_MASK (3 << SCM_CTRL_STATUS_SYSBOOT1_SHIFT)
# define SCM_CTRL_STATUS_SYSBOOT1_19p2MHZ (0 << SCM_CTRL_STATUS_SYSBOOT1_SHIFT)
# define SCM_CTRL_STATUS_SYSBOOT1_24MHZ (1 << SCM_CTRL_STATUS_SYSBOOT1_SHIFT)
# define SCM_CTRL_STATUS_SYSBOOT1_25MHZ (2 << SCM_CTRL_STATUS_SYSBOOT1_SHIFT)
# define SCM_CTRL_STATUS_SYSBOOT1_26MHZ (3 << SCM_CTRL_STATUS_SYSBOOT1_SHIFT)
/* PAD Control Fields */
#define PADCTL_MUXMODE_SHIFT (0) /* Bits 0-2: Functional signal mux select */
#define PADCTL_MUXMODE_MASK (7 << PADCTL_MUXMODE_SHIFT)
@ -643,4 +652,4 @@
#define PADCTL_RXACTIVE (1 << 5) /* Bit 5: Receiver enabled */
#define PADCTL_SLEWCTRL (1 << 6) /* Bit 6: Select between faster or slower slew rate */
#endif /* __ARCH_ARM_SRC_AM335X_HARDWARE_AM335X_CONTROL_H */
#endif /* __ARCH_ARM_SRC_AM335X_HARDWARE_AM335X_SCM_H */