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SAMV7 SPI slave: Add output queuing and interrupt handling
This commit is contained in:
Gregory Nutt
parent
5f4224115a
commit
c7eaa00ed4
2 changed files with 340 additions and 27 deletions
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@ -608,6 +608,18 @@ config SAMV7_SPI_DMADEBUG
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endif # SAMV7_SPI_MASTER
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if SAMV7_SPI_SLAVE
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comment "SPI Master Configuration"
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config SAMV7_SPI_SLAVE_QSIZE
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int "Output queue size"
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default 8
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---help---
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The number of words that an be retained in the controller driver's
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output queue.
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endif # SAMV7_SPI_SLAVE
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config SAMV7_SPI_REGDEBUG
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bool "SPI Register level debug"
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depends on DEBUG
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@ -48,6 +48,7 @@
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#include <nuttx/arch.h>
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#include <nuttx/kmalloc.h>
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#include <nuttx/irq.h>
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#include <nuttx/spi/slave.h>
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#include "up_arch.h"
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@ -68,6 +69,45 @@
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****************************************************************************/
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/* Configuration ************************************************************/
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#ifndef CONFIG_SAMV7_SPI_SLAVE_QSIZE
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# define CONFIG_SAMV7_SPI_SLAVE_QSIZE 8
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#endif
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/* Pin configurations ******************************************************/
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/* We don't know which ones must be defined until run time */
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#ifndef GPIO_SPI0_NPCS0
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# define GPIO_SPI0_NPCS0 0
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#endif
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#ifndef GPIO_SPI0_NPCS1
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# define GPIO_SPI0_NPCS1 0
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#endif
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#ifndef GPIO_SPI0_NPCS2
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# define GPIO_SPI0_NPCS2 0
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#endif
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#ifndef GPIO_SPI0_NPCS3
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# define GPIO_SPI0_NPCS3 0
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#endif
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#ifndef GPIO_SPI1_NPCS0
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# define GPIO_SPI1_NPCS0 0
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#endif
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#ifndef GPIO_SPI1_NPCS1
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# define GPIO_SPI1_NPCS1 0
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#endif
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#ifndef GPIO_SPI1_NPCS2
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# define GPIO_SPI1_NPCS2 0
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#endif
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#ifndef GPIO_SPI1_NPCS3
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# define GPIO_SPI1_NPCS3 0
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#endif
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/* Debug *******************************************************************/
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/* Check if SPI debug is enabled (non-standard.. no support in
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* include/debug.h
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@ -101,11 +141,20 @@ struct sam_spics_s
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struct spi_sctrlr_s sctrlr; /* Externally visible part of the SPI slave
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* controller interface */
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FAR struct spi_sdev_s *sdev; /* Bound SPI slave device interface */
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gpio_pinset_t csconfig; /* Chip select pin configuration */
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uint8_t mode; /* Mode 0,1,2,3 */
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uint8_t nbits; /* Width of word in bits (8 to 16) */
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uint8_t spino; /* SPI controller number (0 or 1) */
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uint8_t cs; /* Chip select number */
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uint8_t csno; /* Chip select number */
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uint16_t outval; /* Default shift-out value */
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/* Output queue */
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uint8_t head; /* Location of next value */
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uint8_t tail; /* Index of first value */
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uint16_t outq[CONFIG_SAMV7_SPI_SLAVE_QSIZE];
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};
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/* The overall state of one SPI controller */
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@ -115,6 +164,8 @@ struct sam_spidev_s
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uint32_t base; /* SPI controller register base address */
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sem_t spisem; /* Assures mutually exclusive access to SPI */
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bool initialized; /* TRUE: Controller has been initialized */
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int16_t irq; /* SPI IRQ number */
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xcpt_t handler; /* SPI interrupt handler */
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/* Debug stuff */
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@ -154,6 +205,18 @@ static void spi_dumpregs(struct sam_spidev_s *spidev, const char *msg);
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static void spi_semtake(struct sam_spidev_s *spidev);
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#define spi_semgive(spidev) (sem_post(&(spidev)->spisem))
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/* Interrupt Handling */
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static int spi_interrupt(FAR struct sam_spidev_s *spidev);
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#ifdef CONFIG_SAMV7_SPI0_SLAVE
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static int spi0_interrupt(int irq, FAR void *context);
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#endif
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#ifdef CONFIG_SAMV7_SPI1_SLAVE
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static int spi1_interrupt(int irq, FAR void *context);
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#endif
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/* SPI Helpers */
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static inline void spi_flush(struct sam_spidev_s *spidev);
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static inline uint32_t spi_cs2pcs(struct sam_spics_s *spics);
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static void spi_setmode(FAR struct sam_spics_s *spics,
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@ -163,11 +226,13 @@ static void spi_setbits(FAR struct sam_spics_s *spics,
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/* SPI slave controller methods */
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static void spi_bind(FAR struct spi_sctrlr_s *sctrlr,
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static void spi_bind(FAR struct spi_sctrlr_s *sctrlr,
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FAR struct spi_sdev_s *sdev, enum spi_smode_e mode,
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int nbits);
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static void spi_unbind(FAR struct spi_sctrlr_s *sctrlr);
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static void spi_setdata(FAR struct spi_sctrlr_s *sctrlr, uint16_t data);
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static int spi_enqueue(FAR struct spi_sctrlr_s *sctrlr, uint16_t data);
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static bool spi_qfull(FAR struct spi_sctrlr_s *sctrlr);
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static void spi_qflush(FAR struct spi_sctrlr_s *sctrlr);
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/****************************************************************************
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* Private Data
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@ -181,17 +246,34 @@ static const uint8_t g_csroffset[4] =
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SAM_SPI_CSR2_OFFSET, SAM_SPI_CSR3_OFFSET
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};
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/* CS pin configurations */
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#ifdef CONFIG_SAMV7_SPI0_SLAVE
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static gpio_pinset_t g_spi0_csconfig[SAM_SPI_NCS] =
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{
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GPIO_SPI0_NPCS0, GPIO_SPI0_NPCS1, GPIO_SPI0_NPCS2, GPIO_SPI0_NPCS3
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};
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#endif
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#ifdef CONFIG_SAMV7_SPI1_SLAVE
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static gpio_pinset_t g_spi1_csconfig[SAM_SPI_NCS] =
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{
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GPIO_SPI1_NPCS0, GPIO_SPI1_NPCS1, GPIO_SPI1_NPCS2, GPIO_SPI1_NPCS3
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};
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#endif
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/* SPI slave controller driver operations */
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static const struct spi_sctrlrops_s g_sctrlr_ops =
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{
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.bind = spi_bind,
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.unbind = spi_unbind,
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.setdata = spi_setdata,
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.enqueue = spi_enqueue,
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.qfull = spi_qfull,
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.qflush = spi_qflush,
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};
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#ifdef CONFIG_SAMV7_SPI0_SLAVE
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/* This is the overall state of the SPI0 controller */
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static struct sam_spidev_s g_spi0_sctrlr;
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@ -398,6 +480,68 @@ static void spi_semtake(struct sam_spidev_s *spidev)
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while (ret < 0);
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}
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/****************************************************************************
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* Name: spi_flush
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*
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* Description:
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* Make sure that there are now dangling SPI transfer in progress
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*
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* Input Parameters:
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* spics - SPI controller CS state
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*
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* Returned Value:
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* Standard interrupt return value.
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*
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****************************************************************************/
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static int spi_interrupt(FAR struct sam_spidev_s *spidev)
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{
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#warning Missing logic
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return OK;
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}
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/****************************************************************************
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* Name: spi0_interrupt
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*
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* Description:
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* SPI0 interrupt handler
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*
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* Input Parameters:
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* Standard interrupt input parameters
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*
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* Returned Value:
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* Standard interrupt return value.
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*
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****************************************************************************/
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#ifdef CONFIG_SAMV7_SPI0_SLAVE
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static int spi0_interrupt(int irq, FAR void *context)
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{
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return spi_interrupt(&g_spi0_sctrlr);
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}
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#endif
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/****************************************************************************
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* Name: spi1_interrupt
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*
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* Description:
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* SPI1 interrupt handler
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*
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* Input Parameters:
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* Standard interrupt input parameters
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*
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* Returned Value:
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* Standard interrupt return value.
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*
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****************************************************************************/
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#ifdef CONFIG_SAMV7_SPI1_SLAVE
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static int spi1_interrupt(int irq, FAR void *context)
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{
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return spi_interrupt(&g_spi1_sctrlr);
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}
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#endif
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/****************************************************************************
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* Name: spi_flush
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*
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@ -456,7 +600,7 @@ static inline void spi_flush(struct sam_spidev_s *spidev)
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static inline uint32_t spi_cs2pcs(struct sam_spics_s *spics)
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{
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return ((uint32_t)1 << (spics->cs)) - 1;
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return ((uint32_t)1 << (spics->csno)) - 1;
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}
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/****************************************************************************
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@ -481,7 +625,7 @@ static void spi_setmode(FAR struct sam_spics_s *spics,
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uint32_t regval;
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unsigned int offset;
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spivdbg("cs=%d mode=%d\n", spics->cs, mode);
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spivdbg("csno=%d mode=%d\n", spics->csno, mode);
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/* Has the mode changed? */
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@ -497,7 +641,7 @@ static void spi_setmode(FAR struct sam_spics_s *spics,
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* 3 1 0
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*/
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offset = (unsigned int)g_csroffset[spics->cs];
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offset = (unsigned int)g_csroffset[spics->csno];
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regval = spi_getreg(spidev, offset);
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regval &= ~(SPI_CSR_CPOL | SPI_CSR_NCPHA);
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@ -554,7 +698,7 @@ static void spi_setbits(FAR struct sam_spics_s *spics,
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uint32_t regval;
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unsigned int offset;
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spivdbg("cs=%d nbits=%d\n", spics->cs, nbits);
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spivdbg("csno=%d nbits=%d\n", spics->csno, nbits);
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DEBUGASSERT(spics && nbits > 7 && nbits < 17);
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/* Has the number of bits changed? */
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@ -563,7 +707,7 @@ static void spi_setbits(FAR struct sam_spics_s *spics,
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{
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/* Yes... Set number of bits appropriately */
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offset = (unsigned int)g_csroffset[spics->cs];
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offset = (unsigned int)g_csroffset[spics->csno];
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regval = spi_getreg(spidev, offset);
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regval &= ~SPI_CSR_BITS_MASK;
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regval |= SPI_CSR_BITS(nbits);
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@ -608,7 +752,7 @@ static void spi_bind(FAR struct spi_sctrlr_s *sctrlr,
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spivdbg("sdev=%p mode=%d nbits=%d\n", sdv, mode, nbits);
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DEBUGASSERT(spics != NULL && spics->sdev == NULL);
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DEBUGASSERT(spics != NULL && spics->sdev == NULL && sdev != NULL);
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spidev = spi_device(spics);
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/* Get exclusive access to the SPI device */
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@ -621,6 +765,23 @@ static void spi_bind(FAR struct spi_sctrlr_s *sctrlr,
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spics->sdev = sdev;
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/* Call the slaved device's cmddata() method to indicate the initial
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* state of any command/data selection.
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*/
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#warning Missing logic
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SPI_SDEV_CMDDATA(sdev, false);
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/* Discard any queued data */
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spics->head = 0;
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spics->tail = 0;
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/* Call the slave device's getdata() method to get the value that will
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* be shifted out the SPI clock is detected.
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*/
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spics->outval = SPI_SDEV_GETDATA(sdev);
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/* Setup to begin normal SPI operation */
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spi_setmode(spics, spidev, mode);
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@ -669,12 +830,12 @@ static void spi_unbind(FAR struct spi_sctrlr_s *sctrlr)
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}
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/****************************************************************************
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* Name: spi_setdata
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* Name: spi_enqueue
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*
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* Description:
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* Set the next value to be shifted out from the interface. This primes
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* the controller driver for the next transfer but has no effect on any
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* in-process or currently "committed" transfers
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* Enqueue the next value to be shifted out from the interface. This adds
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* the word the controller driver for a subsequent transfer but has no
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* effect on anyin-process or currently "committed" transfers
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*
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* Input Parameters:
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* sctrlr - SPI slave controller interface instance
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@ -683,14 +844,19 @@ static void spi_unbind(FAR struct spi_sctrlr_s *sctrlr)
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* provided to the bind() methods.
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*
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* Returned Value:
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* none
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* Zero if the word was successfully queue; A negated errno valid is
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* returned on any failure to enqueue the word (such as if the queue is
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* full).
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*
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****************************************************************************/
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static void spi_setdata(FAR struct spi_sctrlr_s *sctrlr, uint16_t data)
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static int spi_enqueue(FAR struct spi_sctrlr_s *sctrlr, uint16_t data)
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{
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FAR struct sam_spics_s *spics = (FAR struct sam_spics_s *)sctrlr;
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FAR struct sam_spidev_s *spidev;
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irqstate_t flags;
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int next;
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int ret;
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spivdbg("data=%04x\n", data);
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@ -701,12 +867,124 @@ static void spi_setdata(FAR struct spi_sctrlr_s *sctrlr, uint16_t data)
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spi_semtake(spidev);
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/* Save this new word as the next word to shifted out. The current word
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* written to the TX data registers is "committed" and will not be
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* overwritten.
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/* Check if this word would overflow the circular buffer
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*
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* Interrupts are disabled briefly.
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*/
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#warning Missing Logic
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flags = irqsave();
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next = spics->head + 1;
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if (next >= CONFIG_SAMV7_SPI_SLAVE_QSIZE)
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{
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next = 0;
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}
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if (next == spics->tail)
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{
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ret = -ENOSPC;
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}
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else
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{
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/* Save this new word as the next word to shifted out. The current
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* word written to the TX data registers is "committed" and will not
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* be overwritten.
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*/
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spics->head = data;
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spics->head = next;
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ret = OK;
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}
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irqrestore(flags);
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spi_semgive(spidev);
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return ret;
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}
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/****************************************************************************
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* Name: spi_qfull
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*
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* Description:
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* Return true if the queue is full or false if there is space to add an
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* additional word to the queue.
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*
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* Input Parameters:
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* sctrlr - SPI slave controller interface instance
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*
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* Returned Value:
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* true if the output wueue is full
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*
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****************************************************************************/
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static bool spi_qfull(FAR struct spi_sctrlr_s *sctrlr)
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{
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FAR struct sam_spics_s *spics = (FAR struct sam_spics_s *)sctrlr;
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FAR struct sam_spidev_s *spidev;
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irqstate_t flags;
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int next;
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bool ret;
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DEBUGASSERT(spics != NULL && spics->sdev != NULL);
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spidev = spi_device(spics);
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/* Get exclusive access to the SPI device */
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spi_semtake(spidev);
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/* Check if another word would overflow the circular buffer
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*
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* Interrupts are disabled briefly.
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*/
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flags = irqsave();
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next = spics->head + 1;
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if (next >= CONFIG_SAMV7_SPI_SLAVE_QSIZE)
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{
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next = 0;
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}
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ret = (next == spics->tail);
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irqrestore(flags);
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spi_semgive(spidev);
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return ret;
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}
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/****************************************************************************
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* Name: spi_qflush
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*
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* Description:
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* Discard all saved values in the output queue. On return from this
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* function the output queue will be empty. Any in-progress or otherwise
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* "committed" output values may not be flushed.
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*
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* Input Parameters:
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* sctrlr - SPI slave controller interface instance
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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static void spi_qflush(FAR struct spi_sctrlr_s *sctrlr)
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{
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FAR struct sam_spics_s *spics = (FAR struct sam_spics_s *)sctrlr;
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FAR struct sam_spidev_s *spidev;
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irqstate_t flags;
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spivdbg("data=%04x\n", data);
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DEBUGASSERT(spics != NULL && spics->sdev != NULL);
|
||||
spidev = spi_device(spics);
|
||||
|
||||
/* Get exclusive access to the SPI device */
|
||||
|
||||
spi_semtake(spidev);
|
||||
|
||||
/* Mark the buffer empty, momentarily disabling interrupts */
|
||||
|
||||
flags = irqsave();
|
||||
spics->head = 0;
|
||||
spics->tail = 0;
|
||||
irqrestore(flags);
|
||||
spi_semgive(spidev);
|
||||
}
|
||||
|
||||
|
|
@ -721,7 +999,8 @@ static void spi_setdata(FAR struct spi_sctrlr_s *sctrlr, uint16_t data)
|
|||
* Initialize the selected SPI port in slave mode.
|
||||
*
|
||||
* Input Parameter:
|
||||
* cs - Chip select number (identifying the "logical" SPI port)
|
||||
* port - Chip select number identifying the "logical" SPI port. Includes
|
||||
* incoded port and chip select inforomation.
|
||||
*
|
||||
* Returned Value:
|
||||
* Valid SPI device structure reference on success; a NULL on failure
|
||||
|
|
@ -773,7 +1052,7 @@ struct spi_sctrlr_s *up_spi_slave_initialize(int port)
|
|||
|
||||
/* Save the chip select and SPI controller numbers */
|
||||
|
||||
spics->cs = csno;
|
||||
spics->csno = csno;
|
||||
spics->spino = spino;
|
||||
|
||||
/* Get the SPI device structure associated with the chip select */
|
||||
|
|
@ -792,9 +1071,15 @@ struct spi_sctrlr_s *up_spi_slave_initialize(int port)
|
|||
#endif
|
||||
#if defined(CONFIG_SAMV7_SPI0_SLAVE)
|
||||
{
|
||||
/* Set the SPI0 register base address */
|
||||
/* Set the SPI0 register base address and interrupt information */
|
||||
|
||||
spidev->base = SAM_SPI0_BASE,
|
||||
spidev->base = SAM_SPI0_BASE,
|
||||
spidev->irq = SAM_IRQ_SPI0;
|
||||
spidev->handler = spi0_interrupt;
|
||||
|
||||
/* Chip select pin configuration */
|
||||
|
||||
spics->csconfig = g_spi0_csconfig[csno];
|
||||
|
||||
/* Enable peripheral clocking to SPI0 */
|
||||
|
||||
|
|
@ -814,9 +1099,15 @@ struct spi_sctrlr_s *up_spi_slave_initialize(int port)
|
|||
#endif
|
||||
#if defined(CONFIG_SAMV7_SPI1_SLAVE)
|
||||
{
|
||||
/* Set the SPI1 register base address */
|
||||
/* Set the SPI1 register base address and interrupt information */
|
||||
|
||||
spidev->base = SAM_SPI1_BASE,
|
||||
spidev->base = SAM_SPI1_BASE,
|
||||
spidev->irq = SAM_IRQ_SPI1;
|
||||
spidev->handler = spi1_interrupt;
|
||||
|
||||
/* Chip select pin configuration */
|
||||
|
||||
spics->csconfig = g_spi1_csconfig[csno];
|
||||
|
||||
/* Enable peripheral clocking to SPI1 */
|
||||
|
||||
|
|
@ -832,6 +1123,11 @@ struct spi_sctrlr_s *up_spi_slave_initialize(int port)
|
|||
}
|
||||
#endif
|
||||
|
||||
/* Configure the CS pin */
|
||||
|
||||
DEBUGASSERT(spics->csconfig != 0);
|
||||
sam_configgpio(spics->csconfig);
|
||||
|
||||
/* Disable SPI clocking */
|
||||
|
||||
spi_putreg(spidev, SPI_CR_SPIDIS, SAM_SPI_CR_OFFSET);
|
||||
|
|
@ -863,6 +1159,11 @@ struct spi_sctrlr_s *up_spi_slave_initialize(int port)
|
|||
sem_init(&spidev->spisem, 0, 1);
|
||||
spidev->initialized = true;
|
||||
|
||||
/* Attach and enable interrupts at the NVIC */
|
||||
|
||||
DEBUGVERIFY(irq_attach(spidev->irq, spidev->handler));
|
||||
up_enable_irq(spidev->irq);
|
||||
|
||||
spi_dumpregs(spidev, "After initialization");
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue