From c7d53cb927c72e960cffefa806783f9571fbe03f Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 10 Jul 2014 12:03:10 -0600 Subject: [PATCH] SAMA5D4-EK: LCDC works (with a few color problems) --- arch/arm/src/sama5/chip/sam_lcdc.h | 2 +- arch/arm/src/sama5/sam_lcd.c | 6 ++++-- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/arch/arm/src/sama5/chip/sam_lcdc.h b/arch/arm/src/sama5/chip/sam_lcdc.h index 447bed1f07a..8d311e06f93 100644 --- a/arch/arm/src/sama5/chip/sam_lcdc.h +++ b/arch/arm/src/sama5/chip/sam_lcdc.h @@ -1,7 +1,7 @@ /************************************************************************************ * arch/arm/src/sama5/chip/sam_lcdc.h * - * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Copyright (C) 2013-2014 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without diff --git a/arch/arm/src/sama5/sam_lcd.c b/arch/arm/src/sama5/sam_lcd.c index b3201fa66bd..d8ce51b717e 100644 --- a/arch/arm/src/sama5/sam_lcd.c +++ b/arch/arm/src/sama5/sam_lcd.c @@ -1281,8 +1281,8 @@ static void sam_dmasetup(int lid, struct sam_dscr_s *dscr, uint8_t *buffer) /* 31.6.2.2 Programming a DMA Channel: * * 4. Write the DSCR.CHXNEXT register with the address location - * of the descriptor structure and set DFETCH field of the - * DSCR.CHXCTRL register to one. + * of the descriptor structure and set DFETCH field of the + * DSCR.CHXCTRL register to one. */ sam_putreg(g_layeraddr[lid], physbuffer); @@ -2267,6 +2267,7 @@ static void sam_lcd_enable(void) regval = LCDC_LCDCFG5_HSPOL | LCDC_LCDCFG5_VSPOL | LCDC_LCDCFG5_VSPDLYS | LCDC_LCDCFG5_DISPDLY | LCDC_LCDCFG5_GUARDTIME(BOARD_LCDC_GUARDTIME); + #if BOARD_LCDC_OUTPUT_BPP == 16 regval |= LCDC_LCDCFG5_MODE_12BPP; #elif BOARD_LCDC_OUTPUT_BPP == 16 @@ -2278,6 +2279,7 @@ static void sam_lcd_enable(void) #else # error Unknown or undefined output resolution #endif + sam_putreg(SAM_LCDC_LCDCFG5, regval); regval = BOARD_LCDC_PWMPS | BOARD_LCDC_PWMPOL |