diff --git a/arch/arm/src/sam34/Kconfig b/arch/arm/src/sam34/Kconfig
index bcc5ebab9c3..79288bfcb0a 100644
--- a/arch/arm/src/sam34/Kconfig
+++ b/arch/arm/src/sam34/Kconfig
@@ -423,15 +423,97 @@ config SAM34_HSMCI
 
 endmenu
 
+if ARCH_CHIP_SAM4L
+menu "AT91SAM3/4 Clock Configuration"
+
 config SAM32_RESET_PERIPHCLKS
 	bool "Enable all peripheral clocks on reset"
 	default n
-	depends on ARCH_CHIP_SAM4L
 	---help---
 		By default, only a few necessary peripheral clocks are enabled at
 		reset. If this setting is enabled, then all clocking will be enabled
 		to all of the selected peripherals on reset.
 
+config SAM34_OSC0
+	bool "External oscillator 0"
+	default n
+	---help---
+		Oscillator 0 might be automatically selected for several reasons:
+		Oscillator 0 might be the system clock or the source clock for
+		either PLL0 or DFPLL.  It might also be needed if OSC0 is the source
+		clock for GCLK9.  By selecting SAM34_OSC0, you can also force the
+		clock to be enabled at boot time for other uses.
+
+config SAM34_OSC32K
+	bool "32.768KHz external oscillator"
+	default n
+	---help---
+		The 32K oscillator might be automatically selected for several
+		reasons: The 32K oscillator may be the source clock for DFPLL0 or
+		the source clock for GLK9 that might be used to driver PLL0.  By
+		selecting SAM34_OSC32K, you can also force the clock to be enabled
+		at boot time.  OSC32 may needed by other devices as well (AST, WDT,
+		PICUART, RTC).
+
+config SAM34_RC80M
+	bool "80MHz RC oscillator"
+	default n
+	---help---
+		The 80MHz RC oscillator might be automatically selected for several
+		reasons: This might be the system clock or the source clock for the
+		DFPLL or it could be the source for GCLK9 that drives PLL0. By
+		selecting SAM34_RC80M, you can also force the clock to be enabled at
+		boot time for other uses.
+
+config SAM34_RCFAST
+	bool "Fast RC oscillator"
+	default n
+	---help---
+		The fast RC oscillator might be automatically selected for several
+		reasons: The 12/8/4 fast RC oscillator may be used as the system
+		clock or as the source for GLCK9 that drives PLL0. If not then, it
+		may be enabled by setting the SAM34_RCFASTxM configuration variable.
+
+if SAM34_RCFAST
+choice
+	prompt "Fast RC Oscillator Speed"
+	default SAM34_RCFAST8M
+
+config SAM34_RCFAST12M
+	bool "12MHz"
+
+config SAM34_RCFAST8M
+	bool "8MHz"
+
+config SAM34_RCFAST4M
+	bool "4MHz
+
+endchoice
+endif
+
+config SAM34_RC1M
+	bool "1MHz RC oscillator"
+	default n
+	---help---
+		The 1MHz RC oscillator might be automatically selected for several
+		reasons: The 1MHz RC oscillator may be used as the system block or
+		may be the source clock for GLCK9 that drives PLL0.  By selecting
+		SAM34_RC1M, you can also force the clock to be enabled at boot time
+		for other purposes.
+
+config SAM34_RC32K
+	bool "32KHz RC oscillator"
+	default n
+	---help---
+		The 32KHz RC oscillator might be automatically selected for several
+		reasons: The 32KHz RC oscillator may be used as the input to DFLL0
+		or as the input to GCLK9 that drives PLL0. By selecting SAM34_RC32K,
+		you can also force the clock to be enabled at boot time for other
+		purposes.
+
+endmenu
+endif
+
 comment "AT91SAM3/4 USART Configuration"
 
 config USART0_ISUART
@@ -459,6 +541,7 @@ config USART3_ISUART
 	select ARCH_HAVE_USART2
 
 comment "AT91SAM3/4 GPIO Interrupt Configuration"
+
 config GPIO_IRQ
 	bool "GPIO pin interrupts"
 	---help---
diff --git a/arch/arm/src/sam34/chip/sam4l_lcdca.h b/arch/arm/src/sam34/chip/sam4l_lcdca.h
index 671f5807d3c..7e17ba347ef 100644
--- a/arch/arm/src/sam34/chip/sam4l_lcdca.h
+++ b/arch/arm/src/sam34/chip/sam4l_lcdca.h
@@ -141,14 +141,13 @@
 #  define LCDCA_CFG_DUTY_1TO3      (3 << LCDCA_CFG_DUTY_SHIFT) /* 1/3, 1/3, COM[0:2] */
 #define LCDCA_CFG_FCST_SHIFT       (16)      /* Bits 16-21: Fine Contrast */
 #define LCDCA_CFG_FCST_MASK        (63 << LCDCA_CFG_FCST_SHIFT)
-#  define LCDCA_CFG_FCST(n)        (((n) & 63) << LCDCA_CFG_FCST_SHIFT) /* n = -32..31 */
+#  define LCDCA_CFG_FCST(n)        (((uint32_t)(n) & 63) << LCDCA_CFG_FCST_SHIFT) /* n = -32..31 */
 #define LCDCA_CFG_NSU_SHIFT        (24)      /* Bits 24-29: Number of Segment Terminals in Use */
 #define LCDCA_CFG_NSU_MASK         (63 << LCDCA_CFG_NSU_SHIFT)
 #  define LCDCA_CFG_NSU(n)         ((n) << LCDCA_CFG_NSU_SHIFT) /* n=0-40 */
 
 /* Timing Register */
 
-
 #define LCDCA_TIM_PRESC            (1 << 0)  /* Bit 0:  LCD Prescaler Select */
 #define LCDCA_TIM_CLKDIV_SHIFT     (1)       /* Bits 1-3: LCD Clock Division */
 #define LCDCA_TIM_CLKDIV_MASK      (7 << LCDCA_TIM_CLKDIV_SHIFT)
@@ -184,11 +183,13 @@
  * memory for segments 0-31).
  */
 
+#define LCDCA_DRL_MASK             0xffffffff
+
 /* Data Register High 0-3 (8 bits data, each bit defines a segment value in display
  * memory for segments 32-39)
  */
 
-#define LCDCA_DRH0_MASK            0xff
+#define LCDCA_DRH_MASK             0xff
 
 /* Indirect Access Data Register */