From bc794bcafeaad9760b0f4c09826b65bf050511c7 Mon Sep 17 00:00:00 2001 From: Alin Jerpelea Date: Fri, 26 Mar 2021 17:08:45 +0100 Subject: [PATCH] arch: arm: s32k1xx: fix nxstyle errors Fix nxstyle errors to pass CI Signed-off-by: Alin Jerpelea --- arch/arm/src/s32k1xx/chip.h | 34 +- .../arm/src/s32k1xx/hardware/s32k116_pinmux.h | 26 +- .../arm/src/s32k1xx/hardware/s32k118_pinmux.h | 27 +- .../arm/src/s32k1xx/hardware/s32k142_pinmux.h | 29 +- .../arm/src/s32k1xx/hardware/s32k144_pinmux.h | 28 +- .../arm/src/s32k1xx/hardware/s32k146_pinmux.h | 27 +- .../arm/src/s32k1xx/hardware/s32k148_pinmux.h | 29 +- arch/arm/src/s32k1xx/hardware/s32k1xx_cmu.h | 19 +- arch/arm/src/s32k1xx/hardware/s32k1xx_crc.h | 19 +- .../arm/src/s32k1xx/hardware/s32k1xx_dmamux.h | 19 +- arch/arm/src/s32k1xx/hardware/s32k1xx_edma.h | 53 ++- arch/arm/src/s32k1xx/hardware/s32k1xx_enet.h | 67 +++- arch/arm/src/s32k1xx/hardware/s32k1xx_ewm.h | 20 +- .../src/s32k1xx/hardware/s32k1xx_flashcfg.h | 34 +- .../src/s32k1xx/hardware/s32k1xx_flexcan.h | 22 +- arch/arm/src/s32k1xx/hardware/s32k1xx_ftfc.h | 26 +- arch/arm/src/s32k1xx/hardware/s32k1xx_ftm.h | 18 +- arch/arm/src/s32k1xx/hardware/s32k1xx_gpio.h | 18 +- arch/arm/src/s32k1xx/hardware/s32k1xx_lmem.h | 21 +- arch/arm/src/s32k1xx/hardware/s32k1xx_lpi2c.h | 32 +- arch/arm/src/s32k1xx/hardware/s32k1xx_lpspi.h | 35 +- .../arm/src/s32k1xx/hardware/s32k1xx_lpuart.h | 25 +- arch/arm/src/s32k1xx/hardware/s32k1xx_mcm.h | 33 +- .../src/s32k1xx/hardware/s32k1xx_memorymap.h | 12 +- arch/arm/src/s32k1xx/hardware/s32k1xx_mpu.h | 33 +- arch/arm/src/s32k1xx/hardware/s32k1xx_pcc.h | 27 +- .../arm/src/s32k1xx/hardware/s32k1xx_pinmux.h | 30 +- arch/arm/src/s32k1xx/hardware/s32k1xx_pmc.h | 18 +- arch/arm/src/s32k1xx/hardware/s32k1xx_port.h | 25 +- arch/arm/src/s32k1xx/hardware/s32k1xx_rcm.h | 21 +- arch/arm/src/s32k1xx/hardware/s32k1xx_rtc.h | 18 +- arch/arm/src/s32k1xx/hardware/s32k1xx_scg.h | 35 +- arch/arm/src/s32k1xx/hardware/s32k1xx_sim.h | 40 +- arch/arm/src/s32k1xx/hardware/s32k1xx_smc.h | 21 +- arch/arm/src/s32k1xx/hardware/s32k1xx_wdog.h | 20 +- .../s32k1xx/s32k11x/s32k11x_clockmapping.c | 4 + .../s32k1xx/s32k11x/s32k11x_periphfeatures.c | 15 +- .../src/s32k1xx/s32k11x/s32k11x_timerisr.c | 3 +- .../s32k1xx/s32k14x/s32k14x_clockmapping.c | 4 + .../arm/src/s32k1xx/s32k14x/s32k14x_clrpend.c | 10 +- arch/arm/src/s32k1xx/s32k14x/s32k14x_irq.h | 2 +- .../s32k1xx/s32k14x/s32k14x_periphfeatures.c | 14 +- arch/arm/src/s32k1xx/s32k1xx_clockconfig.c | 160 +++++--- arch/arm/src/s32k1xx/s32k1xx_clockconfig.h | 2 +- arch/arm/src/s32k1xx/s32k1xx_config.h | 24 +- arch/arm/src/s32k1xx/s32k1xx_edma.h | 156 ++++---- arch/arm/src/s32k1xx/s32k1xx_eeeprom.c | 73 ++-- arch/arm/src/s32k1xx/s32k1xx_eeeprom.h | 28 +- arch/arm/src/s32k1xx/s32k1xx_enet.h | 39 +- arch/arm/src/s32k1xx/s32k1xx_flashcfg.c | 5 + arch/arm/src/s32k1xx/s32k1xx_flexcan.h | 24 +- arch/arm/src/s32k1xx/s32k1xx_lowputc.c | 13 +- arch/arm/src/s32k1xx/s32k1xx_lpspi.c | 372 ++++++++++-------- arch/arm/src/s32k1xx/s32k1xx_lpspi.h | 104 ++--- arch/arm/src/s32k1xx/s32k1xx_periphclocks.c | 72 ++-- arch/arm/src/s32k1xx/s32k1xx_periphclocks.h | 32 +- arch/arm/src/s32k1xx/s32k1xx_pin.h | 105 ++--- arch/arm/src/s32k1xx/s32k1xx_pindma.c | 16 +- arch/arm/src/s32k1xx/s32k1xx_pingpio.c | 1 + arch/arm/src/s32k1xx/s32k1xx_progmem.c | 67 ++-- arch/arm/src/s32k1xx/s32k1xx_progmem.h | 16 +- arch/arm/src/s32k1xx/s32k1xx_pwm.c | 88 +++-- arch/arm/src/s32k1xx/s32k1xx_pwm.h | 30 +- arch/arm/src/s32k1xx/s32k1xx_start.h | 32 +- 64 files changed, 1411 insertions(+), 1061 deletions(-) diff --git a/arch/arm/src/s32k1xx/chip.h b/arch/arm/src/s32k1xx/chip.h index d97b8fbec3a..5c98b77593c 100644 --- a/arch/arm/src/s32k1xx/chip.h +++ b/arch/arm/src/s32k1xx/chip.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/s32k1xx/chip.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,26 +16,28 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_S32K1XX_CHIP_H #define __ARCH_ARM_SRC_S32K1XX_CHIP_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include -/* Include the memory map and the chip definitions file. Other chip hardware files - * should then include this file for the proper setup. +/* Include the memory map and the chip definitions file. + * Other chip hardware files should then include this file for the proper + * setup. */ #include #include "hardware/s32k1xx_memorymap.h" -/* The common ARMv6/7-M vector handling logic expects the following definitions in - * this file. ARMV6/7M_PERIPHERAL_INTERRUPTS provides the number of supported +/* The common ARMv6/7-M vector handling logic expects the following + * definitions in this file. + * ARMV6/7M_PERIPHERAL_INTERRUPTS provides the number of supported * external interrupts which, for this architecture, is provided in the * arch/s32k1xx/irq.h header file. */ @@ -48,20 +50,20 @@ #define ARMV7M_DCACHE_LINESIZE 16 /* 16 bytes (4 words) */ #define ARMV7M_ICACHE_LINESIZE 16 /* 16 bytes (4 words) */ -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_S32K1XX_CHIP_H */ diff --git a/arch/arm/src/s32k1xx/hardware/s32k116_pinmux.h b/arch/arm/src/s32k1xx/hardware/s32k116_pinmux.h index 8f748805719..5976a0b8456 100644 --- a/arch/arm/src/s32k1xx/hardware/s32k116_pinmux.h +++ b/arch/arm/src/s32k1xx/hardware/s32k116_pinmux.h @@ -1,4 +1,4 @@ -/******************************************************************************************** +/**************************************************************************** * arch/arm/src/s32k1xx/hardware/s32k116_pinmux.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,31 +16,33 @@ * License for the specific language governing permissions and limitations * under the License. * - ********************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_S32K1XX_HARDWARE_S32K116_PINMUX_H #define __ARCH_ARM_SRC_S32K1XX_HARDWARE_S32K116_PINMUX_H -/******************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" -/******************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************/ + ****************************************************************************/ -/* In most cases, there are alternative configurations for various pins. Those alternative - * pins are labeled with a suffix like _1, _2, etc. in order to distinguish them. Logic in - * the board.h file must select the correct pin configuration for the board by defining a pin +/* In most cases, there are alternative configurations for various pins. + * Those alternative pins are labeled with a suffix like _1, _2, etc. in + * order to distinguish them. Logic in the board.h file must select the + * correct pin configuration for the board by defining a pin * configuration (with no suffix) that maps to the correct alternative. * - * WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! - * Additional effort is required to select specific GPIO options such as frequency, - * and pull-up/down! Just the basics are defined for most pins in the initial version of + * WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! + * Additional effort is required to select specific GPIO options such as + * frequency, and pull-up/down! Just the basics are defined for most pins + * in the initial version of * this file. */ diff --git a/arch/arm/src/s32k1xx/hardware/s32k118_pinmux.h b/arch/arm/src/s32k1xx/hardware/s32k118_pinmux.h index 3bf748623f8..5de49b7db7b 100644 --- a/arch/arm/src/s32k1xx/hardware/s32k118_pinmux.h +++ b/arch/arm/src/s32k1xx/hardware/s32k118_pinmux.h @@ -1,4 +1,4 @@ -/******************************************************************************************** +/**************************************************************************** * arch/arm/src/s32k1xx/hardware/s32k118_pinmux.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,37 +16,38 @@ * License for the specific language governing permissions and limitations * under the License. * - ********************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_S32K1XX_HARDWARE_S32K118_PINMUX_H #define __ARCH_ARM_SRC_S32K1XX_HARDWARE_S32K118_PINMUX_H -/******************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" -/******************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************/ + ****************************************************************************/ -/* In most cases, there are alternative configurations for various pins. Those alternative - * pins are labeled with a suffix like _1, _2, etc. in order to distinguish them. Logic in - * the board.h file must select the correct pin configuration for the board by defining a pin +/* In most cases, there are alternative configurations for various pins. + * Those alternative pins are labeled with a suffix like _1, _2, etc. in + * order to distinguish them. Logic in the board.h file must select the + * correct pin configuration for the board by defining a pin * configuration (with no suffix) that maps to the correct alternative. * - * WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! - * Additional effort is required to select specific GPIO options such as frequency, - * and pull-up/down! Just the basics are defined for most pins in the initial version of + * WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! + * Additional effort is required to select specific GPIO options such as + * frequency, and pull-up/down! + * Just the basics are defined for most pins in the initial version of * this file. */ /* ADC */ - #define PIN_ADC0_SE0 (PIN_ANALOG | PIN_PORTA | PIN0) #define PIN_ADC0_SE1 (PIN_ANALOG | PIN_PORTA | PIN1) #define PIN_ADC0_SE2 (PIN_ANALOG | PIN_PORTA | PIN6) diff --git a/arch/arm/src/s32k1xx/hardware/s32k142_pinmux.h b/arch/arm/src/s32k1xx/hardware/s32k142_pinmux.h index 72cfd2b649d..04b9eb0e13b 100644 --- a/arch/arm/src/s32k1xx/hardware/s32k142_pinmux.h +++ b/arch/arm/src/s32k1xx/hardware/s32k142_pinmux.h @@ -1,4 +1,4 @@ -/******************************************************************************************** +/**************************************************************************** * arch/arm/src/s32k1xx/hardware/s32k142_pinmux.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,32 +16,33 @@ * License for the specific language governing permissions and limitations * under the License. * - ********************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_S32K1XX_HARDWARE_S32K142_PINMUX_H #define __ARCH_ARM_SRC_S32K1XX_HARDWARE_S32K142_PINMUX_H -/******************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" -/******************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************/ + ****************************************************************************/ -/* In most cases, there are alternative configurations for various pins. Those alternative - * pins are labeled with a suffix like _1, _2, etc. in order to distinguish them. Logic in - * the board.h file must select the correct pin configuration for the board by defining a pin - * configuration (with no suffix) that maps to the correct alternative. +/* In most cases, there are alternative configurations for various pins. + * Those alternative pins are labeled with a suffix like _1, _2, etc. in + * order to distinguish them. Logic in the board.h file must select the + * correct pin configuration for the board by defining a pin configuration + *(with no suffix) that maps to the correct alternative. * - * WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! - * Additional effort is required to select specific GPIO options such as frequency, - * and pull-up/down! Just the basics are defined for most pins in the initial version of - * this file. + * WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! + * Additional effort is required to select specific GPIO options such as + * frequency, and pull-up/down! Just the basics are defined for most pins + * in the initial version of this file. */ /* ADC */ diff --git a/arch/arm/src/s32k1xx/hardware/s32k144_pinmux.h b/arch/arm/src/s32k1xx/hardware/s32k144_pinmux.h index 706c2cd25ea..df52a15e771 100644 --- a/arch/arm/src/s32k1xx/hardware/s32k144_pinmux.h +++ b/arch/arm/src/s32k1xx/hardware/s32k144_pinmux.h @@ -1,4 +1,4 @@ -/******************************************************************************************** +/**************************************************************************** * arch/arm/src/s32k1xx/hardware/s32k144_pinmux.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,31 +16,33 @@ * License for the specific language governing permissions and limitations * under the License. * - ********************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_S32K1XX_HARDWARE_S32K144_PINMUX_H #define __ARCH_ARM_SRC_S32K1XX_HARDWARE_S32K144_PINMUX_H -/******************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" -/******************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************/ + ****************************************************************************/ -/* In most cases, there are alternative configurations for various pins. Those alternative - * pins are labeled with a suffix like _1, _2, etc. in order to distinguish them. Logic in - * the board.h file must select the correct pin configuration for the board by defining a pin - * configuration (with no suffix) that maps to the correct alternative. +/* In most cases, there are alternative configurations for various pins. + * Those alternative pins are labeled with a suffix like _1, _2, etc. in + * order to distinguish them. Logic in the board.h file must select the + * correct pin configuration for the board by defining a pin configuration + *(with no suffix) that maps to the correct alternative. * - * WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! - * Additional effort is required to select specific GPIO options such as frequency, - * and pull-up/down! Just the basics are defined for most pins in the initial version of + * WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! + * Additional effort is required to select specific GPIO options such as + * frequency, and pull-up/down! + * Just the basics are defined for most pins in the initial version of * this file. */ diff --git a/arch/arm/src/s32k1xx/hardware/s32k146_pinmux.h b/arch/arm/src/s32k1xx/hardware/s32k146_pinmux.h index 9dbd11a57d9..5c5e7ed588a 100644 --- a/arch/arm/src/s32k1xx/hardware/s32k146_pinmux.h +++ b/arch/arm/src/s32k1xx/hardware/s32k146_pinmux.h @@ -1,4 +1,4 @@ -/******************************************************************************************** +/**************************************************************************** * arch/arm/src/s32k1xx/hardware/s32k146_pinmux.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,32 +16,33 @@ * License for the specific language governing permissions and limitations * under the License. * - ********************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_S32K1XX_HARDWARE_S32K146_PINMUX_H #define __ARCH_ARM_SRC_S32K1XX_HARDWARE_S32K146_PINMUX_H -/******************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" -/******************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************/ + ****************************************************************************/ -/* In most cases, there are alternative configurations for various pins. Those alternative - * pins are labeled with a suffix like _1, _2, etc. in order to distinguish them. Logic in - * the board.h file must select the correct pin configuration for the board by defining a pin +/* In most cases, there are alternative configurations for various pins. + * Those alternative pins are labeled with a suffix like _1, _2, etc. in + * order to distinguish them. Logic in the board.h file must select the + * correct pin configuration for the board by defining a pin * configuration (with no suffix) that maps to the correct alternative. * - * WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! - * Additional effort is required to select specific GPIO options such as frequency, - * and pull-up/down! Just the basics are defined for most pins in the initial version of - * this file. + * WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! + * Additional effort is required to select specific GPIO options such as + * frequency, and pull-up/down! Just the basics are defined for most pins + * in the initial version of this file. */ /* ADC */ diff --git a/arch/arm/src/s32k1xx/hardware/s32k148_pinmux.h b/arch/arm/src/s32k1xx/hardware/s32k148_pinmux.h index 76cfdc74b6f..aee6e5b6933 100644 --- a/arch/arm/src/s32k1xx/hardware/s32k148_pinmux.h +++ b/arch/arm/src/s32k1xx/hardware/s32k148_pinmux.h @@ -1,4 +1,4 @@ -/******************************************************************************************** +/**************************************************************************** * arch/arm/src/s32k1xx/hardware/s32k148_pinmux.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,32 +16,33 @@ * License for the specific language governing permissions and limitations * under the License. * - ********************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_S32K1XX_HARDWARE_S32K148_PINMUX_H #define __ARCH_ARM_SRC_S32K1XX_HARDWARE_S32K148_PINMUX_H -/******************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" -/******************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************/ + ****************************************************************************/ -/* In most cases, there are alternative configurations for various pins. Those alternative - * pins are labeled with a suffix like _1, _2, etc. in order to distinguish them. Logic in - * the board.h file must select the correct pin configuration for the board by defining a pin - * configuration (with no suffix) that maps to the correct alternative. +/* In most cases, there are alternative configurations for various pins. + * Those alternative pins are labeled with a suffix like _1, _2, etc. in + * order to distinguish them. Logic in the board.h file must select the + * correct pin configuration for the board by defining a pin configuration + *(with no suffix) that maps to the correct alternative. * - * WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! - * Additional effort is required to select specific GPIO options such as frequency, - * and pull-up/down! Just the basics are defined for most pins in the initial version of - * this file. + * WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! + * Additional effort is required to select specific GPIO options such as + * frequency, and pull-up/down! Just the basics are defined for most pins + * in the initial version of this file. */ /* ADC */ diff --git a/arch/arm/src/s32k1xx/hardware/s32k1xx_cmu.h b/arch/arm/src/s32k1xx/hardware/s32k1xx_cmu.h index 01b76d381c8..785ff4972f2 100644 --- a/arch/arm/src/s32k1xx/hardware/s32k1xx_cmu.h +++ b/arch/arm/src/s32k1xx/hardware/s32k1xx_cmu.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/s32k1xx/hardware/s32k1xx_cmu.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,23 +16,23 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_S32K1XX_HARDWARE_S32K1XX_CMU_H #define __ARCH_ARM_SRC_S32K1XX_HARDWARE_S32K1XX_CMU_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* CMU Register Offsets *************************************************************/ +/* CMU Register Offsets *****************************************************/ #define S32K1XX_CMU_GCR_OFFSET 0x0000 /* Global Configuration Register */ #define S32K1XX_CMU_RCCR_OFFSET 0x0004 /* Reference Count Configuration Register */ @@ -41,7 +41,7 @@ #define S32K1XX_CMU_SR_OFFSET 0x0010 /* Status Register */ #define S32K1XX_CMU_IER_OFFSET 0x0014 /* Interrupt Enable Register */ -/* CMU Register Addresses ***********************************************************/ +/* CMU Register Addresses ***************************************************/ #define S32K1XX_CMU_GCR (S32K1XX_CMU_BASE + S32K1XX_CMU_GCR_OFFSET) #define S32K1XX_CMU_RCCR (S32K1XX_CMU_BASE + S32K1XX_CMU_RCCR_OFFSET) @@ -50,7 +50,7 @@ #define S32K1XX_CMU_SR (S32K1XX_CMU_BASE + S32K1XX_CMU_SR_OFFSET) #define S32K1XX_CMU_IER (S32K1XX_CMU_BASE + S32K1XX_CMU_IER_OFFSET) -/* CMU Register Bitfield Definitions ************************************************/ +/* CMU Register Bitfield Definitions ****************************************/ /* Global Configuration Register */ @@ -83,6 +83,7 @@ # define CMU_SR_STATE_INIT (1 << CMU_SR_STATE_SHIFT) /* Initialization state */ # define CMU_SR_STATE_INITWAIT (2 << CMU_SR_STATE_SHIFT) /* Initialization wait state */ # define CMU_SR_STATE_FREQCHECK (3 << CMU_SR_STATE_SHIFT) /* Frequency check state */ + #define CMU_SR_RS (1 << 4) /* Bit 4: Run Status */ /* Interrupt Enable Register */ diff --git a/arch/arm/src/s32k1xx/hardware/s32k1xx_crc.h b/arch/arm/src/s32k1xx/hardware/s32k1xx_crc.h index cdcfa732539..b61c0b424f5 100644 --- a/arch/arm/src/s32k1xx/hardware/s32k1xx_crc.h +++ b/arch/arm/src/s32k1xx/hardware/s32k1xx_crc.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/s32k1xx/hardware/s32k1xx_crc.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,35 +16,35 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_S32K1XX_HARDWARE_S32K1XX_CRC_H #define __ARCH_ARM_SRC_S32K1XX_HARDWARE_S32K1XX_CRC_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* CRC Register Offsets *************************************************************/ +/* CRC Register Offsets *****************************************************/ #define S32K1XX_CRC_DATA_OFFSET 0x0000 /* CRC Data register */ #define S32K1XX_CRC_GPOLY_OFFSET 0x0004 /* CRC Polynomial register */ #define S32K1XX_CRC_CTRL_OFFSET 0x0008 /* CRC Control register */ -/* CRC Register Addresses ***********************************************************/ +/* CRC Register Addresses ***************************************************/ #define S32K1XX_CRC_DATA (S32K1XX_CRC_BASE + S32K1XX_CRC_DATA_OFFSET) #define S32K1XX_CRC_GPOLY (S32K1XX_CRC_BASE + S32K1XX_CRC_GPOLY_OFFSET) #define S32K1XX_CRC_CTRL (S32K1XX_CRC_BASE + S32K1XX_CRC_CTRL_OFFSET) -/* CRC Register Bitfield Definitions ************************************************/ +/* CRC Register Bitfield Definitions ****************************************/ /* CRC Data register */ @@ -83,6 +83,7 @@ # define CRC_CTRL_TOTR_BITS (1 << CRC_CTRL_TOTR_SHIFT) /* Bits in bytes are transposed */ # define CRC_CTRL_TOTR_BOTH (2 << CRC_CTRL_TOTR_SHIFT) /* Both bits in bytes and bytes transposed */ # define CRC_CTRL_TOTR_BYTES (3 << CRC_CTRL_TOTR_SHIFT) /* Bytes are transposed */ + #define CRC_CTRL_TOT_SHIFT (30) /* Bits 30-31: Type Of Transpose For Writes */ #define CRC_CTRL_TOT_MASK (3 << CRC_CTRL_TOT_SHIFT) # define CRC_CTRL_TOT_NONE (0 << CRC_CTRL_TOT_SHIFT) /* No transposition */ diff --git a/arch/arm/src/s32k1xx/hardware/s32k1xx_dmamux.h b/arch/arm/src/s32k1xx/hardware/s32k1xx_dmamux.h index 17506dde226..577bb2d0e80 100644 --- a/arch/arm/src/s32k1xx/hardware/s32k1xx_dmamux.h +++ b/arch/arm/src/s32k1xx/hardware/s32k1xx_dmamux.h @@ -1,4 +1,4 @@ -/******************************************************************************************** +/**************************************************************************** * arch/arm/src/s32k1xx/hardware/s32k1xx_dmamux.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,21 +16,21 @@ * License for the specific language governing permissions and limitations * under the License. * - *******************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_S32K1XX_HARDWARE_S32K1XX_DMAMUX_H #define __ARCH_ARM_SRC_S32K1XX_HARDWARE_S32K1XX_DMAMUX_H -/******************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************/ + ****************************************************************************/ #include #include -/******************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************/ + ****************************************************************************/ /* Number of DMA channels */ @@ -40,21 +40,22 @@ # define S32K1XX_NDMACH 16 #endif -/* DMAMUX Register Offsets ******************************************************************/ +/* DMAMUX Register Offsets **************************************************/ #define S32K1XX_DMAMUX_CHCFG_OFFSET(n) (n) /* Channel Configuration register, n=1..15 */ -/* DMAMUX Register Addresses ****************************************************************/ +/* DMAMUX Register Addresses ************************************************/ #define S32K1XX_DMAMUX_CHCFG(n) (S32K1XX_DMAMUX_BASE + S32K1XX_DMAMUX_CHCFG_OFFSET(n)) n=1..15 */ -/* DMAMUX Register Bitfield Definitions *****************************************************/ +/* DMAMUX Register Bitfield Definitions *************************************/ /* Channel Configuration register, n=1..15 */ #define DMAMUX_CHCFG_SOURCE_SHIFT (0) /* Bits 0-5: DMA Channel Source (Slot) */ #define DMAMUX_CHCFG_SOURCE_MASK (0x3f << DMAMUX_CHCFG_SOURCE_SHIFT) # define DMAMUX_CHCFG_SOURCE(s) ((uint32_t)(s) << DMAMUX_CHCFG_SOURCE_SHIFT) /* chip-specific */ + #define DMAMUX_CHCFG_TRIG (1 << 6) /* Bit 6: DMA Channel Trigger Enable */ #define DMAMUX_CHCFG_ENBL (1 << 7) /* Bit 7: DMA Channel Enable */ diff --git a/arch/arm/src/s32k1xx/hardware/s32k1xx_edma.h b/arch/arm/src/s32k1xx/hardware/s32k1xx_edma.h index e5cfeaa9a04..1d8604584c3 100644 --- a/arch/arm/src/s32k1xx/hardware/s32k1xx_edma.h +++ b/arch/arm/src/s32k1xx/hardware/s32k1xx_edma.h @@ -1,4 +1,4 @@ -/**************************************************************************************************** +/**************************************************************************** * arch/arm/src/s32k1xx/hardware/s32k1xx_edma.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,21 +16,21 @@ * License for the specific language governing permissions and limitations * under the License. * - ****************************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_S32K1XX_HARDWARE_S32K1XX_EDMA_H #define __ARCH_ARM_SRC_S32K1XX_HARDWARE_S32K1XX_EDMA_H -/**************************************************************************************************** +/**************************************************************************** * Included Files - ****************************************************************************************************/ + ****************************************************************************/ #include #include "hardware/s32k1xx_memorymap.h" -/**************************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ****************************************************************************************************/ + ****************************************************************************/ #if defined(CONFIG_ARCH_CHIP_S32K11X) # define S32K1XX_EDMA_NCHANNELS 4 @@ -40,7 +40,7 @@ # error "Unknown number of DMA channels for this S32K1xx part" #endif -/* eDMA Register Offsets ****************************************************************************/ +/* eDMA Register Offsets ****************************************************/ #define S32K1XX_EDMA_CR_OFFSET 0x0000 /* Control */ #define S32K1XX_EDMA_ES_OFFSET 0x0004 /* Error Status */ @@ -297,7 +297,7 @@ #define S32K1XX_EDMA_TCD15_CSR_OFFSET 0x11fc /* TCD Control and Status */ #define S32K1XX_EDMA_TCD15_BITER_ELINK_OFFSET 0x11fe /* TCD Beginning Minor Loop Link, Major Loop Count */ -/* eDMA Register Addresses **************************************************************************/ +/* eDMA Register Addresses **************************************************/ #define S32K1XX_EDMA_CR (S32K1XX_EDMA_BASE + S32K1XX_EDMA_CR_OFFSET) #define S32K1XX_EDMA_ES (S32K1XX_EDMA_BASE + S32K1XX_EDMA_ES_OFFSET) @@ -542,9 +542,10 @@ #define S32K1XX_EDMA_TCD15_CSR (S32K1XX_EDMA_BASE + S32K1XX_EDMA_TCD15_CSR_OFFSET) #define S32K1XX_EDMA_TCD15_BITER_ELINK (S32K1XX_EDMA_BASE + S32K1XX_EDMA_TCD15_BITER_ELINK_OFFSET) -/* eDMA Bit-Field Definitions ***********************************************************************/ +/* eDMA Bit-Field Definitions ***********************************************/ /* Control */ + /* Bit 0: Reserved */ #define EDMA_CR_EDBG (1 << 1) /* Bit 1: Enable Debug */ #define EDMA_CR_ERCA (1 << 2) /* Bit 2: Enable Round Robin Channel Arbitration */ @@ -672,10 +673,12 @@ #define EDMA_HRS(n) ((uint32_t)1 << (n)) /* Bit n: Hardware Request Status * Channel n */ + /* Enable Asynchronous Request in Stop */ #define EDMA_EARS(n) ((uint32_t)1 << (n)) /* Bit n: Enable asynchronous DMA * request in stop mode for channel n */ + /* Channel n Priority */ #define EDMA_DCHPRI_CHPRI_SHIFT (0) /* Bits 0-3: Channel n Arbitration Priority */ @@ -686,6 +689,7 @@ #define EDMA_DCHPRI_ECP (1 << 7) /* Bit 7: Enable Channel Preemption */ /* TCD Source Address (32-bit address) */ + /* TCD Signed Source Address Offset (16-bit offset) */ /* TCD Transfer Attributes */ @@ -704,6 +708,7 @@ # define EDMA_TCD_ATTR_DSIZE_32BIT (TCD_ATTR_SIZE_32BIT << EDMA_TCD_ATTR_DSIZE_SHIFT) /* 32-bit */ # define EDMA_TCD_ATTR_DSIZE_64BIT (TCD_ATTR_SIZE_64BIT << EDMA_TCD_ATTR_DSIZE_SHIFT) /* 64-bit */ # define EDMA_TCD_ATTR_DSIZE_256BIT (TCD_ATTR_SIZE_256BIT << EDMA_TCD_ATTR_DSIZE_SHIFT) /* 32-byte burst */ + #define EDMA_TCD_ATTR_DMOD_SHIFT (3) /* Bits 3-7: Destination Address Modulo */ #define EDMA_TCD_ATTR_DMOD_MASK (31 << EDMA_TCD_ATTR_DMOD_SHIFT) # define EDMA_TCD_ATTR_DMOD(n) ((uint32_t)(n) << EDMA_TCD_ATTR_DMOD_SHIFT) @@ -715,14 +720,17 @@ # define EDMA_TCD_ATTR_SSIZE_32BIT (TCD_ATTR_SIZE_32BIT << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 32-bit */ # define EDMA_TCD_ATTR_SSIZE_64BIT (TCD_ATTR_SIZE_64BIT << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 64-bit */ # define EDMA_TCD_ATTR_SSIZE_256BIT (TCD_ATTR_SIZE_256BIT << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 32-byte burst */ + #define EDMA_TCD_ATTR_SMOD_SHIFT (11) /* Bits 11-15: Source Address Modulo */ #define EDMA_TCD_ATTR_SMOD_MASK (31 << EDMA_TCD_ATTR_SMOD_SHIFT) # define EDMA_TCD_ATTR_SMOD(n) ((uint32_t)(n) << EDMA_TCD_ATTR_SMOD_SHIFT) /* TCD Signed Minor Loop Offset / Byte Count */ + /* Minor Byte Count (Minor Loop Mapping Disabled -- 32-bit byte count) */ /* TCD Signed Minor Loop Offset / Byte Count */ + /* Minor Byte Count (Minor Loop Mapping Enabled, offset disabled) */ #define EDMA_TCD_NBYTES_ML_NBYTES_SHIFT (0) /* Bits 0-29: Minor Byte Transfer Count */ @@ -732,6 +740,7 @@ #define EDMA_TCD_NBYTES_ML_SMLOE (1 << 31) /* Bit 31: Source Minor Loop Offset Enable */ /* TCD Signed Minor Loop Offset / Byte Count */ + /* Minor Byte Count (Minor Loop Mapping Enabled, offset enabled) */ #define EDMA_TCD_NBYTES_MLOFF_NBYTES_SHIFT (0) /* Bits 0-9: Minor Byte Transfer Count */ @@ -744,7 +753,9 @@ #define EDMA_TCD_NBYTES_MLOFF_SMLOE (1 << 31) /* Bit 31: Source Minor Loop Offset Enable */ /* TCD Last Source Address Adjustment (32-bit address adjustment) */ + /* TCD Destination Address (32-bit address) */ + /* TCD Signed Destination Address Offset (16-bit signed address offset) */ /* TCD Current Minor Loop Link, Major Loop Count (Channel linking disabled) */ @@ -755,7 +766,9 @@ #define EDMA_TCD_CITER_ELINK (1 << 15) /* Bit 15: Enable channel-to-channel linking * on minor-loop complete */ -/* TCD Current Minor Loop Link, Major Loop Count (Channel linking enabled) */ +/* TCD Current Minor Loop Link, Major Loop Count + * (Channel linking enabled) + */ #define EDMA_TCD_CITER_ELINK_CITER_SHIFT (0) /* Bit 0-8: Current major iteration count */ #define EDMA_TCD_CITER_ELINK_CITER_MASK (0x1ff << EDMA_TCD_CITER_ELINK_CITER_SHIFT) @@ -767,7 +780,9 @@ #define EDMA_TCD_CITER_ELINK_ELINK (1 << 15) /* Bit 15: Enable channel-to-channel linking * on minor-loop complete */ -/* TCD Last Destination Address Adjustment/Scatter Gather Address (32-bit address) */ +/* TCD Last Destination Address Adjustment/Scatter Gather Address + * (32-bit address) + */ /* TCD Control and Status */ @@ -794,7 +809,9 @@ # define EDMA_TCD_CSR_BWC_8CYCLES (3 << EDMA_TCD_CSR_BWC_SHIFT) /* eDMA engine stalls for 8 * cycles after each R/W */ -/* TCD Beginning Minor Loop Link, Major Loop Count (Channel linking disabled) */ +/* TCD Beginning Minor Loop Link, Major Loop Count + * (Channel linking disabled) + */ #define EDMA_TCD_BITER_BITER_SHIFT (0) /* Bit 0-14: Starting Major Iteration Count */ #define EDMA_TCD_BITER_BITER_MASK (0x7fff << EDMA_TCD_BITER_BITER_SHIFT) @@ -802,7 +819,9 @@ #define EDMA_TCD_BITER_ELINK (1 << 15) /* Bit 15: Enable channel-to-channel linking * on minor-loop complete */ -/* TCD Beginning Minor Loop Link, Major Loop Count (Channel linking enabled) */ +/* TCD Beginning Minor Loop Link, Major Loop Count + * (Channel linking enabled) + */ #define EDMA_TCD_BITER_ELINK_BITER_SHIFT (0) /* Bit 0-8: Current major iteration count */ #define EDMA_TCD_BITER_ELINK_BITER_MASK (0x1ff << EDMA_TCD_BITER_ELINK_BITER_SHIFT) @@ -814,11 +833,13 @@ #define EDMA_TCD_BITER_ELINK_ELINK (1 << 15) /* Bit 15: Enable channel-to-channel linking * on minor-loop complete */ -/**************************************************************************************************** +/**************************************************************************** * Public Types - ****************************************************************************************************/ + ****************************************************************************/ -/* In-memory representation of the 32-byte Transfer Control Descriptor (TCD) */ +/* In-memory representation of the 32-byte Transfer Control Descriptor + * (TCD) + */ struct s32k1xx_edmatcd_s { diff --git a/arch/arm/src/s32k1xx/hardware/s32k1xx_enet.h b/arch/arm/src/s32k1xx/hardware/s32k1xx_enet.h index e9f2904bc54..8192f2478e8 100644 --- a/arch/arm/src/s32k1xx/hardware/s32k1xx_enet.h +++ b/arch/arm/src/s32k1xx/hardware/s32k1xx_enet.h @@ -1,4 +1,4 @@ -/***************************************************************************** +/**************************************************************************** * arch/arm/src/s32k1xx/hardware/s32k1xx_enet.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,23 +16,23 @@ * License for the specific language governing permissions and limitations * under the License. * - *****************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_S32K1XX_HARDWARE_S32K1XX_ENET_H #define __ARCH_ARM_SRC_S32K1XX_HARDWARE_S32K1XX_ENET_H -/***************************************************************************** +/**************************************************************************** * Included Files - *****************************************************************************/ + ****************************************************************************/ #include #include "hardware/s32k1xx_memorymap.h" -/***************************************************************************** +/**************************************************************************** * Pre-processor Definitions - *****************************************************************************/ + ****************************************************************************/ -/* Register Offsets **********************************************************/ +/* Register Offsets *********************************************************/ #define S32K1XX_ENET_EIR_OFFSET 0x0004 /* Interrupt Event Register */ #define S32K1XX_ENET_EIMR_OFFSET 0x0008 /* Interrupt Mask Register */ @@ -87,7 +87,7 @@ #define S32K1XX_ENET_TCSR3_OFFSET 0x0620 /* Timer Control Status Register */ #define S32K1XX_ENET_TCCR3_OFFSET 0x0624 /* Timer Compare Capture Register */ -/* Register Addresses ********************************************************/ +/* Register Addresses *******************************************************/ #define S32K1XX_ENET_EIR (S32K1XX_ENET_BASE+S32K1XX_ENET_EIR_OFFSET) #define S32K1XX_ENET_EIMR (S32K1XX_ENET_BASE+S32K1XX_ENET_EIMR_OFFSET) @@ -140,9 +140,10 @@ #define S32K1XX_ENET_TCSR3 (S32K1XX_ENET_BASE+S32K1XX_ENET_TCSR3_OFFSET) #define S32K1XX_ENET_TCCR3 (S32K1XX_ENET_BASE+S32K1XX_ENET_TCCR3_OFFSET) -/* Register Bit Definitions **************************************************/ +/* Register Bit Definitions *************************************************/ /* Interrupt Event Register, Interrupt Mask Register */ + /* Bits 0-14: Reserved */ #define ENET_INT_TS_TIMER (1 << 15) /* Bit 15: Timestamp timer */ #define ENET_INT_TS_AVAIL (1 << 16) /* Bit 16: Transmit timestamp available */ @@ -161,14 +162,19 @@ #define ENET_INT_BABT (1 << 29) /* Bit 29: Babbling Transmit Error */ #define ENET_INT_BABR (1 << 30) /* Bit 30: Babbling Receive Error */ /* Bit 31: Reserved */ + /* Receive Descriptor Active Register */ + /* Bits 0-23: Reserved */ #define ENET_RDAR (1 << 24) /* Bit 24: Receive descriptor active */ /* Bits 25-31: Reserved */ + /* Transmit Descriptor Active Register */ + /* Bits 0-23: Reserved */ #define ENET_TDAR (1 << 24) /* Bit 24: Transmit descriptor active */ /* Bits 25-31: Reserved */ + /* Ethernet Control Register */ #define ENET_ECR_RESET (1 << 0) /* Bit 0: Ethernet MAC reset */ @@ -201,10 +207,12 @@ # define ENET_MMFR_OP_WRMII (1 << ENET_MMFR_OP_SHIFT) /* Write frame, MII management frame */ # define ENET_MMFR_OP_RDMII (2 << ENET_MMFR_OP_SHIFT) /* Read frame, MII management frame */ # define ENET_MMFR_OP_RdNOTMII (3 << ENET_MMFR_OP_SHIFT) /* Read frame, not MII compliant */ + #define ENET_MMFR_ST_SHIFT (30) /* Bits 30-31: Start of frame delimiter */ #define ENET_MMFR_ST_MASK (3 << ENET_MMFR_ST_SHIFT) /* MII Speed Control Register */ + /* Bit 0: Reserved */ #define ENET_MSCR_MII_SPEED_SHIFT (1) /* Bits 1-6: MII speed */ #define ENET_MSCR_MII_SPEED_MASK (63 << ENET_MSCR_MII_SPEED_SHIFT) @@ -215,9 +223,11 @@ # define ENET_MSCR_HOLDTIME_2CYCLES (1 << ENET_MSCR_HOLDTIME_SHIFT) /* 2 internal module clock cycles */ # define ENET_MSCR_HOLDTIME_3CYCLES (2 << ENET_MSCR_HOLDTIME_SHIFT) /* 3 internal module clock cycles */ # define ENET_MSCR_HOLDTIME_8CYCLES (7 << ENET_MSCR_HOLDTIME_SHIFT) /* 8 internal module clock cycles */ + /* Bits 11-31: Reserved */ /* MIB Control Register */ + /* Bits 0-28: Reserved */ #define ENET_MIBC_MIB_CLEAR (1 << 29) /* Bit 29: MIB clear */ #define ENET_MIBC_MIB_IDLE (1 << 30) /* Bit 30: MIB idle */ @@ -255,11 +265,13 @@ #define ENET_TCR_ADDSEL_SHIFT (5) /* Bits 5-7: Source MAC address select on transmit */ #define ENET_TCR_ADDSEL_MASK (7 << ENET_TCR_ADDSEL_SHIFT) # define ENET_TCR_ADDSEL_PADDR12 (0 << ENET_TCR_ADDSEL_SHIFT) /* Node MAC address programmed on PADDR1/2 registers */ + #define ENET_TCT_ADDINS (1 << 8) /* Bit 8: Set MAC Address On Transmit */ #define ENET_TCR_CRCFWD (1 << 9) /* Bit 9: Forward frame from application with CRC */ /* Bits 10-31: Reserved */ /* Physical Address Lower/Upper Register (32-bits of 48-address) */ + /* Physical Address Upper Register */ #define ENET_PAUR_TYPE_SHIFT (0) /* Bits 0-15: Type field in PAUSE frame */ @@ -274,8 +286,13 @@ #define ENET_OPD_OPCODE_SHIFT (16) /* Bits 16-31: Opcode field in PAUSE frames */ #define ENET_OPD_OPCODE_MASK (0xffff << ENET_OPD_OPCODE_SHIFT) -/* Descriptor Individual Upper/Lower Address Register (64-bit address in two 32-bit registers) */ -/* Descriptor Group Upper/Lower Address Register (64-bit address in two 32-bit registers) */ +/* Descriptor Individual Upper/Lower Address Register + * (64-bit address in two 32-bit registers) + */ + +/* Descriptor Group Upper/Lower Address Register + * (64-bit address in two 32-bit registers) + */ /* Transmit Interrupt Coalescing Register */ @@ -306,16 +323,19 @@ /* Bits 9-31: Reserved */ /* Receive Descriptor Ring Start Register */ + /* Bits 0-2: Reserved */ #define ENET_RDSR_SHIFT (3) /* Bits 3-31: Start of the receive buffer descriptor queue */ #define ENET_RDSR_MASK (0xfffffff8) /* Transmit Buffer Descriptor Ring Start Register */ + /* Bits 0-2: Reserved */ #define ENET_TDSR_SHIFT (3) /* Bits 3-31: Start of the transmit buffer descriptor queue */ #define ENET_TDSR_MASK (0xfffffff8) /* Maximum Receive Buffer Size Register */ + /* Bits 14-31: Reserved */ #define ENET_MRBR_SHIFT (4) /* Bits 4-13: Receive buffer size in bytes */ #define ENET_MRBR_MASK (0x3ff << ENET_MRBR_SHIFT) @@ -366,6 +386,7 @@ #define ENET_TAFL_MASK (0xff << ENET_TAFL_SHIFT) /* Bits 8-31: Reserved */ + /* Transmit Inter-Packet Gap */ #define ENET_TIPG_SHIFT (0) /* Bits 0-4: Value of the transmit FIFO section empty threshold */ @@ -414,13 +435,17 @@ /* Bits 14-31: Reserved */ /* Timer Value Register (32-bit timer value) */ + /* Timer Offset Register (32-bit offset value) */ + /* Timer Period Register (32-bit timer period) */ /* Timer Correction Register */ #define ENET_ATCOR_MASK (0x7fffffff) /* Bits 0-3: Correction counter wrap-around value */ + /* Bit 31: Reserved */ + /* Time-Stamping Clock Period Register */ #define ENET_ATINC_INC_SHIFT (0) /* Bits 0-6: Clock period of the timestamping clock (ts_clk) in nanoseconds */ @@ -458,13 +483,15 @@ # define ENET_TCSR_TMODE_OCCLRSET (10 << ENET_TCSR_TMODE_SHIFT) /* Output Compare, clear on compare, set on overflow */ # define ENET_TCSR_TMODE_PCPULSEL (14 << ENET_TCSR_TMODE_SHIFT) /* Output Compare, pulse low on compare */ # define ENET_TCSR_TMODE_PCPULSEH (15 << ENET_TCSR_TMODE_SHIFT) /* Output Compare, pulse high on compare */ + #define ENET_TCSR_TIE (1 << 6) /* Bit 6: Timer interrupt enable */ #define ENET_TCSR_TF (1 << 7) /* Bit 7: Timer Flag */ /* Bits 8-31: Reserved */ /* Timer Compare Capture Register (32-bit compare value) */ -/* Buffer Descriptors ********************************************************/ +/* Buffer Descriptors *******************************************************/ + /* Endian-independent descriptor offsets */ #define DESC_STATUS1_OFFSET (0) @@ -610,11 +637,11 @@ # define RXDESC_BDU (1 << 7) #endif -/***************************************************************************** +/**************************************************************************** * Public Types - *****************************************************************************/ + ****************************************************************************/ -/* Buffer Descriptors ********************************************************/ +/* Buffer Descriptors *******************************************************/ /* Legacy Buffer Descriptor */ @@ -671,12 +698,12 @@ struct enet_desc_s #endif /* S32K1XX_USE_DBSWAP */ #endif /* CONFIG_ENET_ENHANCEDBD */ -/***************************************************************************** +/**************************************************************************** * Public Data - *****************************************************************************/ + ****************************************************************************/ -/***************************************************************************** - * Public Functions - *****************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_S32K1XX_HARDWARE_S32K1XX_ENET_H */ diff --git a/arch/arm/src/s32k1xx/hardware/s32k1xx_ewm.h b/arch/arm/src/s32k1xx/hardware/s32k1xx_ewm.h index 0987b3d9cdb..ef7f77c295a 100644 --- a/arch/arm/src/s32k1xx/hardware/s32k1xx_ewm.h +++ b/arch/arm/src/s32k1xx/hardware/s32k1xx_ewm.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/s32k1xx/hardware/s32k1xx_ewm.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,23 +16,23 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_S32K1XX_HARDWARE_S32K1XX_EWM_H #define __ARCH_ARM_SRC_S32K1XX_HARDWARE_S32K1XX_EWM_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* EWM Register Offsets *************************************************************/ +/* EWM Register Offsets *****************************************************/ #define S32K1XX_EWM_CTRL_OFFSET 0x0000 /* Control Register */ #define S32K1XX_EWM_SERV_OFFSET 0x0001 /* Service Register */ @@ -40,7 +40,7 @@ #define S32K1XX_EWM_CMPH_OFFSET 0x0003 /* Compare High Register */ #define S32K1XX_EWM_CLKPRESCALER_OFFSET 0x0005 /* Clock Prescaler Register */ -/* EWM Register Addresses ***********************************************************/ +/* EWM Register Addresses ***************************************************/ #define S32K1XX_EWM_CTRL (S32K1XX_EWM_BASE + S32K1XX_EWM_CTRL_OFFSET) #define S32K1XX_EWM_SERV (S32K1XX_EWM_BASE + S32K1XX_EWM_SERV_OFFSET) @@ -48,7 +48,7 @@ #define S32K1XX_EWM_CMPH (S32K1XX_EWM_BASE + S32K1XX_EWM_CMPH_OFFSET) #define S32K1XX_EWM_CLKPRESCALER (S32K1XX_EWM_BASE + S32K1XX_EWM_CLKPRESCALER_OFFSET) -/* EWM Register Bitfield Definitions ************************************************/ +/* EWM Register Bitfield Definitions ****************************************/ /* Control Register */ @@ -63,7 +63,9 @@ #define EWM_SERV_BYTE1 0x2c /* Compare Low Register (8-bit COMPAREL value) */ + /* Compare High Register (8-bit COMPAREH value) */ + /* Clock Prescaler Register (8-bit CLK_DIV value) */ #endif /* __ARCH_ARM_SRC_S32K1XX_HARDWARE_S32K1XX_EWM_H */ diff --git a/arch/arm/src/s32k1xx/hardware/s32k1xx_flashcfg.h b/arch/arm/src/s32k1xx/hardware/s32k1xx_flashcfg.h index fe0b108328c..4aaffb15896 100644 --- a/arch/arm/src/s32k1xx/hardware/s32k1xx_flashcfg.h +++ b/arch/arm/src/s32k1xx/hardware/s32k1xx_flashcfg.h @@ -1,4 +1,4 @@ -/******************************************************************************************** +/**************************************************************************** * arch/arm/src/s32k1xx/hardware/s32k1xx_flashcfg.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,23 +16,23 @@ * License for the specific language governing permissions and limitations * under the License. * - ********************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_S32K1XX_HARDWARE_S32K1XX_FLASHCFG_H #define __ARCH_ARM_SRC_S32K1XX_HARDWARE_S32K1XX_FLASHCFG_H -/******************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************/ + ****************************************************************************/ #include #include -/******************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************/ + ****************************************************************************/ -/* FLASHCFG Register Offsets ****************************************************************/ +/* FLASHCFG Register Offsets ************************************************/ #define S32K1XX_FLASHCFG_BACKDOOR1_OFFSET 0x0000 /* Backdoor Comparison Key 1 */ #define S32K1XX_FLASHCFG_BACKDOOR2_OFFSET 0x0004 /* Backdoor Comparison Key 2 */ @@ -42,7 +42,7 @@ #define S32K1XX_FLASHCFG_FEPROT_OFFSET 0x000e /* EEPROM protection byte */ #define S32K1XX_FLASHCFG_FDPROT_OFFSET 0x000f /* Data flash protection byte */ -/* FLASHCFG Register Addresses ***************************************************************/ +/* FLASHCFG Register Addresses **********************************************/ #define S32K1XX_FLASHCFG_BACKDOOR1 (S32K1XX_FLASHCFG_BASE + S32K1XX_FLASHCFG_BACKDOOR1_OFFSET) #define S32K1XX_FLASHCFG_BACKDOOR2 (S32K1XX_FLASHCFG_BASE + S32K1XX_FLASHCFG_BACKDOOR2_OFFSET) @@ -52,9 +52,10 @@ #define S32K1XX_FLASHCFG_FEPROT (S32K1XX_FLASHCFG_BASE + S32K1XX_FLASHCFG_FEPROT_OFFSET) #define S32K1XX_FLASHCFG_FDPROT (S32K1XX_FLASHCFG_BASE + S32K1XX_FLASHCFG_FDPROT_OFFSET) -/* FLASHCFG Register Bitfield Definitions ***************************************************/ +/* FLASHCFG Register Bitfield Definitions ***********************************/ /* Backdoor Comparison Key 1 (32-bits) */ + /* Backdoor Comparison Key 2 (32-bits) */ /* Program flash protection bytes @@ -96,22 +97,25 @@ # define FLASHCFG_FSEC_KEYEN_ENABLED (2 << FLASHCFG_FSEC_KEYEN_SHIFT) # define FLASHCFG_FSEC_KEYEN_DISABLED3 (3 << FLASHCFG_FSEC_KEYEN_SHIFT) -/* Flash nonvolatile option byte (8-bits, Refer to the device's Chip Configuration details - * for the definition and use of these bits. +/* Flash nonvolatile option byte (8-bits, Refer to the device's Chip + * Configuration details for the definition and use of these bits. */ -/* EEPROM protection byte. Each EPROT bit covers one-eighth of the configured EEPROM data */ +/* EEPROM protection byte. + * Each EPROT bit covers one-eighth of the configured EEPROM data + */ #define FLASHCFG_FEPROT(n) (1 << (n)) -/* Data flash protection byte. Each DPROT bit protects one-eighth of the partitioned data +/* Data flash protection byte. + * Each DPROT bit protects one-eighth of the partitioned data * flash memory space. */ #define FLASHCFG_FDPROT(n) (1 << (n)) -/******************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************/ + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_S32K1XX_HARDWARE_S32K1XX_FLASHCFG_H */ diff --git a/arch/arm/src/s32k1xx/hardware/s32k1xx_flexcan.h b/arch/arm/src/s32k1xx/hardware/s32k1xx_flexcan.h index ea0c67d99f0..5f2ec953e5d 100644 --- a/arch/arm/src/s32k1xx/hardware/s32k1xx_flexcan.h +++ b/arch/arm/src/s32k1xx/hardware/s32k1xx_flexcan.h @@ -1,4 +1,4 @@ -/************************************************************************************************************ +/**************************************************************************** * arch/arm/src/s32k1xx/hardware/s32k1xx_flexcan.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,23 +16,23 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_S32K1XX_HARDWARE_S32K1XX_FLEXCAN_H #define __ARCH_ARM_SRC_S32K1XX_HARDWARE_S32K1XX_FLEXCAN_H -/************************************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************************************/ + ****************************************************************************/ #include #include -/************************************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************************************/ + ****************************************************************************/ -/* Register Offsets *****************************************************************************************/ +/* Register Offsets *********************************************************/ #define S32K1XX_CAN_MCR_OFFSET 0x0000 /* Module Configuration Register */ #define S32K1XX_CAN_CTRL1_OFFSET 0x0004 /* Control 1 Register */ @@ -132,7 +132,7 @@ #define S32K1XX_CAN_FDCBT_OFFSET 0x0c04 /* CAN FD Bit Timing register */ #define S32K1XX_CAN_FDCRC_OFFSET 0x0c08 /* CAN FD CRC register */ -/* Register Addresses ***************************************************************************************/ +/* Register Addresses *******************************************************/ #define S32K1XX_CAN0_MCR (S32K1XX_FLEXCAN0_BASE + S32K1XX_CAN_MCR_OFFSET) #define S32K1XX_CAN0_CTRL1 (S32K1XX_FLEXCAN0_BASE + S32K1XX_CAN_CTRL1_OFFSET) @@ -321,7 +321,7 @@ #define S32K1XX_CAN1_FDCBT (S32K1XX_FLEXCAN1_BASE + S32K1XX_CAN_FDCBT_OFFSET) #define S32K1XX_CAN1_FDCRC (S32K1XX_FLEXCAN1_BASE + S32K1XX_CAN_FDCRC_OFFSET) -/* Register Bit Definitions *********************************************************************************/ +/* Register Bit Definitions *************************************************/ /* Module Configuration Register */ @@ -579,7 +579,9 @@ /* Pretended Networking Payload Low Filter 2 Payload Low Mask register */ #define CAN_PL2_PLMASK_LO_ -/* Pretended Networking Payload High Filter 2 low order bits / Payload High Mask register */ +/* Pretended Networking Payload High Filter 2 low order bits / + * Payload High Mask register + */ #define CAN_PL2_PLMASK_HI_ /* Wake Up Message Buffer register for C/S */ diff --git a/arch/arm/src/s32k1xx/hardware/s32k1xx_ftfc.h b/arch/arm/src/s32k1xx/hardware/s32k1xx_ftfc.h index 5eeeab493a1..0776c7a591f 100644 --- a/arch/arm/src/s32k1xx/hardware/s32k1xx_ftfc.h +++ b/arch/arm/src/s32k1xx/hardware/s32k1xx_ftfc.h @@ -1,4 +1,4 @@ -/***************************************************************************************************** +/**************************************************************************** * arch/arm/src/s32k1xx/hardware/s32k1xx_ftfc.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,25 +16,25 @@ * License for the specific language governing permissions and limitations * under the License. * - *****************************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_S32K1XX_HARDWARE_S32K1XX_FTFC_H #define __ARCH_ARM_SRC_S32K1XX_HARDWARE_S32K1XX_FTFC_H -/***************************************************************************************************** +/**************************************************************************** * Included Files - *****************************************************************************************************/ + ****************************************************************************/ #include #include -/***************************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - *****************************************************************************************************/ + ****************************************************************************/ -/* FTFC Register Offsets *****************************************************************************/ +/* FTFC Register Offsets ****************************************************/ -/* FTFC Register Offsets *****************************************************************************/ +/* FTFC Register Offsets ****************************************************/ #define S32K1XX_FTFC_FSTAT_OFFSET 0x0000 #define S32K1XX_FTFC_FCNFG_OFFSET 0x0001 @@ -59,10 +59,10 @@ #define S32K1XX_FTFC_FEPROT_OFFSET 0x0016 #define S32K1XX_FTFC_FDPROT_OFFSET 0x0017 #define S32K1XX_FTFC_FCSESTAT_OFFSET 0x002c -#define S32K1XX_FTFC_FERSTAT_OFFSET 0x002e -#define S32K1XX_FTFC_FERCNFG_OFFSET 0x002f +#define S32K1XX_FTFC_FERSTAT_OFFSET 0x002e +#define S32K1XX_FTFC_FERCNFG_OFFSET 0x002f -/* FTFC Register Addresses ***************************************************************************/ +/* FTFC Register Addresses **************************************************/ #define S32K1XX_FTFC_FSTAT (S32K1XX_FTFC_BASE + S32K1XX_FTFC_FSTAT_OFFSET) #define S32K1XX_FTFC_FCNFG (S32K1XX_FTFC_BASE + S32K1XX_FTFC_FCNFG_OFFSET) @@ -90,7 +90,7 @@ #define S32K1XX_FTFC_FERSTAT (S32K1XX_FTFC_BASE + S32K1XX_FTFC_FERSTAT_OFFSET) #define S32K1XX_FTFC_FERCNFG (S32K1XX_FTFC_BASE + S32K1XX_FTFC_FERCNFG_OFFSET) -/* FTFC Register Bitfield Definitions ****************************************************************/ +/* FTFC Register Bitfield Definitions ***************************************/ #define FTTC_FSTAT_MGSTAT0 (1 << 0) #define FTTC_FSTAT_FPVIOL (1 << 4) @@ -101,7 +101,7 @@ #define FTTC_FCNFG_EEERDY (1 << 0) #define FTTC_FCNFG_RAMRDY (1 << 1) -/* Flash controller command numbers ******************************************************************/ +/* Flash controller command numbers *****************************************/ #define S32K1XX_FTFC_VERIFY_BLOCK 0x00 /* RD1BLK*/ #define S32K1XX_FTFC_VERIFY_SECTION 0x01 /* RD1SEC*/ diff --git a/arch/arm/src/s32k1xx/hardware/s32k1xx_ftm.h b/arch/arm/src/s32k1xx/hardware/s32k1xx_ftm.h index 932f87e554b..7caade8a9cf 100644 --- a/arch/arm/src/s32k1xx/hardware/s32k1xx_ftm.h +++ b/arch/arm/src/s32k1xx/hardware/s32k1xx_ftm.h @@ -1,4 +1,4 @@ -/***************************************************************************************************** +/**************************************************************************** * arch/arm/src/s32k1xx/hardware/s32k1xx_ftm.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,22 +16,22 @@ * License for the specific language governing permissions and limitations * under the License. * - *****************************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_S32K1XX_HARDWARE_S32K1XX_FTM_H #define __ARCH_ARM_SRC_S32K1XX_HARDWARE_S32K1XX_FTM_H -/***************************************************************************************************** +/**************************************************************************** * Included Files - *****************************************************************************************************/ + ****************************************************************************/ #include "hardware/s32k1xx_memorymap.h" -/***************************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - *****************************************************************************************************/ + ****************************************************************************/ -/* Register Offsets **********************************************************************************/ +/* Register Offsets *********************************************************/ #define S32K1XX_FTM_SC_OFFSET 0x0000 /* Status And Control register offset */ #define S32K1XX_FTM_CNT_OFFSET 0x0004 /* Counter register offset */ @@ -92,7 +92,7 @@ #define S32K1XX_FTM_CNSC_OFFSET(n) (0x000c + (n) * 0x0008) /* Channel (n) Status And Control register offset */ #define S32K1XX_FTM_CNV_OFFSET(n) (0x0010 + (n) * 0x0008) /* Channel (n) Value register offset */ -/* Register Addresses ********************************************************************************/ +/* Register Addresses *******************************************************/ /* FTM0 registers */ @@ -558,7 +558,7 @@ #define S32K1XX_FTM7_C6V_MIRROR (S32K1XX_FTM7_BASE + S32K1XX_FTM_C6V_MIRROR_OFFSET) /* FTM7 Mirror of Channel 6 Match Value register */ #define S32K1XX_FTM7_C7V_MIRROR (S32K1XX_FTM7_BASE + S32K1XX_FTM_C7V_MIRROR_OFFSET) /* FTM7 Mirror of Channel 7 Match Value register */ -/* Register Bit Definitions **************************************************************************/ +/* Register Bit Definitions *************************************************/ /* Status And Control register */ diff --git a/arch/arm/src/s32k1xx/hardware/s32k1xx_gpio.h b/arch/arm/src/s32k1xx/hardware/s32k1xx_gpio.h index 592a5a5219a..526f67fbd6a 100644 --- a/arch/arm/src/s32k1xx/hardware/s32k1xx_gpio.h +++ b/arch/arm/src/s32k1xx/hardware/s32k1xx_gpio.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/s32k1xx/hardware/s32k1xx_gpio.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,21 +16,21 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_S32K1XX_HARDWARE_S32K1XX_GPIO_H #define __ARCH_ARM_SRC_S32K1XX_HARDWARE_S32K1XX_GPIO_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ #define S32K1XX_GPIOA (0) #define S32K1XX_GPIOB (1) @@ -39,7 +39,7 @@ #define S32K1XX_GPIOE (4) #define S32K1XX_NGPIO (5) -/* GPIO Register Offsets *************************************************************/ +/* GPIO Register Offsets ****************************************************/ #define S32K1XX_GPIO_PDOR_OFFSET 0x0000 /* Port Data Output Register */ #define S32K1XX_GPIO_PSOR_OFFSET 0x0004 /* Port Set Output Register */ @@ -49,7 +49,7 @@ #define S32K1XX_GPIO_PDDR_OFFSET 0x0014 /* Port Data Direction Register */ #define S32K1XX_GPIO_PIDR_OFFSET 0x0018 /* Port Input Disable Register */ -/* GPIO Register Addresses ***********************************************************/ +/* GPIO Register Addresses **************************************************/ #define S32K1XX_GPIO_PDOR(g) (S32K1XX_GPIO_BASE(g) + S32K1XX_GPIO_PDOR_OFFSET) #define S32K1XX_GPIO_PSOR(g) (S32K1XX_GPIO_BASE(g) + S32K1XX_GPIO_PSOR_OFFSET) @@ -99,7 +99,7 @@ #define S32K1XX_GPIOE_PDDR (S32K1XX_GPIOE_BASE + S32K1XX_GPIO_PDDR_OFFSET) #define S32K1XX_GPIOE_PIDR (S32K1XX_GPIOE_BASE + S32K1XX_GPIO_PIDR_OFFSET) -/* GPIO Register Bitfield Definitions ************************************************/ +/* GPIO Register Bitfield Definitions ***************************************/ /* Port Data Output Register */ diff --git a/arch/arm/src/s32k1xx/hardware/s32k1xx_lmem.h b/arch/arm/src/s32k1xx/hardware/s32k1xx_lmem.h index 319516d9e34..8339516e218 100644 --- a/arch/arm/src/s32k1xx/hardware/s32k1xx_lmem.h +++ b/arch/arm/src/s32k1xx/hardware/s32k1xx_lmem.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/s32k1xx/hardware/s32k1xx_lmem.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,25 +16,25 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_S32K1XX_HARDWARE_S32K1XX_LMEM_H #define __ARCH_ARM_SRC_S32K1XX_HARDWARE_S32K1XX_LMEM_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include #ifdef CONFIG_S32K1XX_HAVE_LMEM -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* LMEM Register Offsets ************************************************************/ +/* LMEM Register Offsets ****************************************************/ #define S32K1XX_LMEM_PCCCR_OFFSET 0x0000 /* Cache control register */ #define S32K1XX_LMEM_PCCLCR_OFFSET 0x0004 /* Cache line control register */ @@ -42,7 +42,7 @@ #define S32K1XX_LMEM_PCCCVR_OFFSET 0x000c /* Cache read/write value register */ #define S32K1XX_LMEM_PCCRMR_OFFSET 0x0020 /* Cache regions mode register */ -/* LMEM Register Addresses **********************************************************/ +/* LMEM Register Addresses **************************************************/ #define S32K1XX_LMEM_PCCCR (S32K1XX_LMEM_BASE + S32K1XX_LMEM_PCCCR_OFFSET) #define S32K1XX_LMEM_PCCLCR (S32K1XX_LMEM_BASE + S32K1XX_LMEM_PCCLCR_OFFSET) @@ -50,7 +50,7 @@ #define S32K1XX_LMEM_PCCCVR (S32K1XX_LMEM_BASE + S32K1XX_LMEM_PCCCVR_OFFSET) #define S32K1XX_LMEM_PCCRMR (S32K1XX_LMEM_BASE + S32K1XX_LMEM_PCCRMR_OFFSET) -/* LMEM Register Bitfield Definitions ***********************************************/ +/* LMEM Register Bitfield Definitions ***************************************/ /* Cache control register */ @@ -69,6 +69,7 @@ #define LMEM_PCCLCR_CACHEADDR_SHIFT (2) /* Bits 2-13: Cache address */ #define LMEM_PCCLCR_CACHEADDR_MASK (0x7ff << LMEM_PCCLCR_CACHEADDR_SHIFT) # define LMEM_PCCLCR_CACHEADDR(n) ((uint32_t)(n) << LMEM_PCCLCR_CACHEADDR_SHIFT) + #define LMEM_PCCLCR_WSEL (1 << 14) /* Bit 14: Way select */ # define LMEM_PCCLCR_WSEL_WAY0 (0) /* Way0 */ # define LMEM_PCCLCR_WSEL_WAY1 (1 << 14) /* Way1 */ @@ -85,6 +86,7 @@ # define LMEM_PCCLCR_LCMD_INVLD (1 << LMEM_PCCLCR_LCMD_SHIFT) /* Invalidate */ # define LMEM_PCCLCR_LCMD_PUSH (2 << LMEM_PCCLCR_LCMD_SHIFT) /* Push */ # define LMEM_PCCLCR_LCMD_CLEAR (3 << LMEM_PCCLCR_LCMD_SHIFT) /* Clear */ + #define LMEM_PCCLCR_LADSEL (1 << 26) /* Bit 26: Line Address Select */ # define LMEM_PCCLCR_LADSEL_CACHE (0) /* Cache address */ # define LMEM_PCCLCR_LADSEL_PHYS (1 << 26) /* Physical address */ @@ -95,6 +97,7 @@ /* Cache search address register */ #define LMEM_PCCSAR_LGO (1 << 0) /* Bit 0: Initiate Cache Line Command */ + #define LMEM_PCCSAR_PHYADDR_MASK (0xfffffffc) /* Bits 2-31: Physical Address (Bits 2-31) */ /* Cache read/write value register (32-bit data) */ diff --git a/arch/arm/src/s32k1xx/hardware/s32k1xx_lpi2c.h b/arch/arm/src/s32k1xx/hardware/s32k1xx_lpi2c.h index c01b77d8a5e..261d49ce544 100644 --- a/arch/arm/src/s32k1xx/hardware/s32k1xx_lpi2c.h +++ b/arch/arm/src/s32k1xx/hardware/s32k1xx_lpi2c.h @@ -1,4 +1,4 @@ -/************************************************************************************************************ +/**************************************************************************** * arch/arm/src/s32k1xx/hardware/s32k1xx_lpi2c.h * * Copyright (C) 2019 Gregory Nutt. All rights reserved. @@ -32,23 +32,23 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ************************************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_S32K1XX_HARDWARE_S32K1XX_LPI2C_H #define __ARCH_ARM_SRC_S32K1XX_HARDWARE_S32K1XX_LPI2C_H -/************************************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************************************/ + ****************************************************************************/ #include #include "hardware/s32k1xx_memorymap.h" -/************************************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************************************/ + ****************************************************************************/ -/* Register offsets *****************************************************************************************/ +/* Register offsets *********************************************************/ #define S32K1XX_LPI2C_VERID_OFFSET 0x0000 /* Version ID Register offset */ #define S32K1XX_LPI2C_PARAM_OFFSET 0x0004 /* Parameter Register offset */ @@ -79,7 +79,7 @@ #define S32K1XX_LPI2C_STDR_OFFSET 0x0160 /* Slave Transmit Data Register offset */ #define S32K1XX_LPI2C_SRDR_OFFSET 0x0170 /* Slave Receive Data Register offset */ -/* Register addresses ***************************************************************************************/ +/* Register addresses *******************************************************/ /* LPI2C0 Registers */ @@ -143,7 +143,7 @@ #define S32K1XX_LPI2C1_STDR (S32K1XX_LPI2C1_BASE + S32K1XX_LPI2C_STDR_OFFSET) /* Slave Transmit Data Register */ #define S32K1XX_LPI2C1_SRDR (S32K1XX_LPI2C1_BASE + S32K1XX_LPI2C_SRDR_OFFSET) /* Slave Receive Data Register */ -/* Register bit definitions *********************************************************************************/ +/* Register bit definitions *************************************************/ /* LPI2C Version ID Register */ @@ -267,7 +267,7 @@ #define LPI2C_MCFGR1_AUTOSTOP (1 << 8) /* Automatic STOP Generation Bit */ #define LPI2C_MCFGR1_IGNACK (1 << 9) /* Ignore NACK Bit */ #define LPI2C_MCFGR1_TIMECFG (1 << 10) /* Timeout Configuration Bit */ - /* Bits 15-11 Reserved */ + /* Bits 15-11 Reserved */ #define LPI2C_MCFGR1_MATCFG_SHIFT (16) #define LPI2C_MCFGR1_MATCFG_MASK (7 << LPI2C_MCFGR1_MATCFG_SHIFT) /* Match Configuration Bit Mask */ # define LPI2C_MCFGR1_MATCFG(n) ((n << LPI2C_MCFGR1_MATCFG_SHIFT) & LPI2C_MCFGR1_MATCFG_MASK) @@ -309,6 +309,7 @@ #define LPI2C_MCFG2_FILTSDA_DISABLE (0 << LPI2C_MCFG2_FILTSDA_SHIFT) # define LPI2C_MCFG2_FILTSDA_CYCLES(n) ((n << LPI2C_MCFG2_FILTSDA_SHIFT) & LPI2C_MCFG2_FILTSDA_MASK) /* Bits 31-28 Reserved */ + /* LPI2C Master Config Register 3 */ /* Bits 7-0 Reserved */ @@ -370,20 +371,26 @@ #define LPI2C_MFCR_TXWATER_SHIFT (0) #define LPI2C_MFCR_TXWATER_MASK (3 << LPI2C_MFCR_TXWATER_SHIFT) /* Transmit FIFO Watermark*/ + # define LPI2C_MFCR_TXWATER(n) ((n << LPI2C_MFCR_TXWATER_SHIFT) & LPI2C_MFCR_TXWATER_MASK) /* Transmit FIFO Watermark*/ + /* Bits 15-2 Reserved */ #define LPI2C_MFCR_RXWATER_SHIFT (16) #define LPI2C_MFCR_RXWATER_MASK (3 << LPI2C_MFCR_RXWATER_SHIFT) /* Receive FIFO Watermark */ + # define LPI2C_MFCR_RXWATER(n) ((n << LPI2C_MFCR_RXWATER_SHIFT) & LPI2C_MFCR_RXWATER_MASK) /* Transmit FIFO Watermark*/ + /* Bits 31-18 Reserved */ /* LPI2C Master FIFO Status Register */ #define LPI2C_MFSR_TXCOUNT_SHIFT (0) #define LPI2C_MFSR_TXCOUNT_MASK (3 << LPI2C_MFSR_TXCOUNT_SHIFT) /* Transmit FIFO Count */ + /* Bits 15-2 Reserved */ #define LPI2C_MFSR_RXCOUNT_SHIFT (16) #define LPI2C_MFSR_RXCOUNT_MASK (3 << LPI2C_MFSR_RXCOUNT_SHIFT) /* Receive FIFO Count */ + /* Bits 31-18 Reserved */ /* LPI2C Master Transmit Data Register */ @@ -408,9 +415,11 @@ #define LPI2C_MRDR_DATA_SHIFT (0) #define LPI2C_MRDR_DATA_MASK (0xff << LPI2C_MRDR_DATA_SHIFT) /* Receive Data */ + /* Bits 13-8 Reserved */ #define LPI2C_MRDR_RXEMPTY_SHIFT (14) #define LPI2C_MRDR_RXEMPTY_MASK (1 << LPI2C_MRDR_RXEMPTY_SHIFT) /* Rx Empty */ + /* Bits 31-15 Reserved */ /* LPI2C Slave Control Register */ @@ -531,7 +540,8 @@ /* LPI2C Slave Address Status Register */ #define LPI2C_SASR_RADDR_MASK (0x7ff << 0) /* Received Address */ - /* Bits 16-11 Reserved */ + + /* Bits 16-11 Reserved */ #define LPI2C_SASR_ANV (1 << 14) /* Address Not Valid */ /* Bits 31-15 Reserved */ diff --git a/arch/arm/src/s32k1xx/hardware/s32k1xx_lpspi.h b/arch/arm/src/s32k1xx/hardware/s32k1xx_lpspi.h index 36b6bac6d4e..5ebeb77e84e 100644 --- a/arch/arm/src/s32k1xx/hardware/s32k1xx_lpspi.h +++ b/arch/arm/src/s32k1xx/hardware/s32k1xx_lpspi.h @@ -1,4 +1,4 @@ -/**************************************************************************************************** +/**************************************************************************** * arch/arm/src/s32k1xx/hardware/s32k1xx_lpspi.h * * Copyright (C) 2019 Gregory Nutt. All rights reserved. @@ -32,23 +32,23 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ****************************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_S32K1XX_HARDWARE_S32K1XX_LPSPI_H #define __ARCH_ARM_SRC_S32K1XX_HARDWARE_S32K1XX_LPSPI_H -/**************************************************************************************************** +/**************************************************************************** * Included Files - ****************************************************************************************************/ + ****************************************************************************/ #include #include "hardware/s32k1xx_memorymap.h" -/**************************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ***************************************************************************************************/ + ****************************************************************************/ -/* Register offsets *********************************************************************************/ +/* Register offsets *********************************************************/ #define S32K1XX_LPSPI_VERID_OFFSET 0x0000 /* Version ID Register offset */ #define S32K1XX_LPSPI_PARAM_OFFSET 0x0004 /* Parameter Register offset */ @@ -68,7 +68,7 @@ #define S32K1XX_LPSPI_RSR_OFFSET 0x0070 /* Receive Status Register offset */ #define S32K1XX_LPSPI_RDR_OFFSET 0x0074 /* Receive Data Register offset */ -/* Register addresses *******************************************************************************/ +/* Register addresses *******************************************************/ #define S32K1XX_LPSPI0_VERID (S32K1XX_LPSPI0_BASE + S32K1XX_LPSPI_VERID_OFFSET) #define S32K1XX_LPSPI0_PARAM (S32K1XX_LPSPI0_BASE + S32K1XX_LPSPI_PARAM_OFFSET) @@ -124,7 +124,7 @@ #define S32K1XX_LPSPI2_RSR (S32K1XX_LPSPI2_BASE + S32K1XX_LPSPI_RSR_OFFSET) #define S32K1XX_LPSPI2_RDR (S32K1XX_LPSPI2_BASE + S32K1XX_LPSPI_RDR_OFFSET) -/* Register bit definitions *************************************************************************/ +/* Register bit definitions *************************************************/ /* Version ID Register */ @@ -221,6 +221,7 @@ #define LPSPI_CFGR1_PCSPOL_MASK (0xf << LPSPI_CFGR1_PCSPOL_SHIFT) # define LPSPI_CFGR1_PCSPOL_LOW (0 << LPSPI_CFGR1_PCSPOL_SHIFT) /* The Peripheral Chip Select pin PCSx is active low */ # define LPSPI_CFGR1_PCSPOL_HIGH (1 << LPSPI_CFGR1_PCSPOL_SHIFT) /* The Peripheral Chip Select pin PCSx is active high */ + /* Bits 12-15: Reserved */ #define LPSPI_CFGR1_MATCFG_SHIFT (16) /* Bits 16-18: Match Configuration */ #define LPSPI_CFGR1_MATCFG_MASK (7 << LPSPI_CFGR1_MATCFG_SHIFT) @@ -233,13 +234,14 @@ # define LPSPI_CFGR1_PINCFG_SOUT_SOUT (2 << LPSPI_CFGR1_PINCFG_SHIFT) /* SOUT is used for both input and output data */ # define LPSPI_CFGR1_PINCFG_SOUT_SIN (3 << LPSPI_CFGR1_PINCFG_SHIFT) /* SOUT is used for input data and SIN is used for output data */ # define LPSPI_CFGR1_PINCFG(n) ((uint32_t)(n) << LPSPI_CFGR1_PINCFG_SHIFT) -#define LPSPI_CFGR1_OUTCFG (1 << 26) /* Bit 26: Output Config */ -# define LPSPI_CFGR1_OUTCFG_RETAIN (0 << 26) /* Output data retains last value when chip select is negated */ + +#define LPSPI_CFGR1_OUTCFG (1 << 26) /* Bit 26: Output Config */ +# define LPSPI_CFGR1_OUTCFG_RETAIN (0 << 26) /* Output data retains last value when chip select is negated */ # define LPSPI_CFGR1_OUTCFG_TRISTATE (1 << 26) /* Output data is tristated when chip select is negated */ -#define LPSPI_CFGR1_PCSCFG (1 << 27) /* Bit 27: Peripheral Chip Select Configuration */ -# define LPSPI_CFGR1_PCSCFG_EN (0 << 27) /* PCS[3:2] are enabled */ -# define LPSPI_CFGR1_PCSCFG_DIS (1 << 27) /* PCS[3:2] are disabled */ - /* Bits 28-31: Reserved */ +#define LPSPI_CFGR1_PCSCFG (1 << 27) /* Bit 27: Peripheral Chip Select Configuration */ +# define LPSPI_CFGR1_PCSCFG_EN (0 << 27) /* PCS[3:2] are enabled */ +# define LPSPI_CFGR1_PCSCFG_DIS (1 << 27) /* PCS[3:2] are disabled */ + /* Bits 28-31: Reserved */ /* Data Match Register 0 */ @@ -303,6 +305,7 @@ # define LPSPI_TCR_WIDTH_1BIT (0 << LPSPI_TCR_WIDTH_SHIFT) /* 1 bit transfer */ # define LPSPI_TCR_WIDTH_2BIT (1 << LPSPI_TCR_WIDTH_SHIFT) /* 2 bit transfer */ # define LPSPI_TCR_WIDTH_4BIT (2 << LPSPI_TCR_WIDTH_SHIFT) /* 4 bit transfer */ + #define LPSPI_TCR_TXMSK (1 << 18) /* Bit 18: Transmit Data Mask */ #define LPSPI_TCR_RXMSK (1 << 19) /* Bit 19: Receive Data Mask */ #define LPSPI_TCR_CONTC (1 << 20) /* Bit 20: Continuing Command */ @@ -316,6 +319,7 @@ # define LPSPI_TCR_PCS_1 (1 << LPSPI_TCR_PCS_SHIFT) /* Transfer using LPSPI_PCS[1] */ # define LPSPI_TCR_PCS_2 (2 << LPSPI_TCR_PCS_SHIFT) /* Transfer using LPSPI_PCS[2] */ # define LPSPI_TCR_PCS_3 (3 << LPSPI_TCR_PCS_SHIFT) /* Transfer using LPSPI_PCS[3] */ + /* Bit 26: Reserved */ #define LPSPI_TCR_PRESCALE_SHIFT (27) /* Bits 27-29: Prescaler Value */ #define LPSPI_TCR_PRESCALE_MASK (7 << LPSPI_TCR_PRESCALE_SHIFT) @@ -328,6 +332,7 @@ # define LPSPI_TCR_PRESCALE_64 (6 << LPSPI_TCR_PRESCALE_SHIFT) /* Divide by 64 */ # define LPSPI_TCR_PRESCALE_128 (7 << LPSPI_TCR_PRESCALE_SHIFT) /* Divide by 128 */ # define LPSPI_TCR_PRESCALE(n) ((uint32_t)(n) << LPSPI_TCR_PRESCALE_SHIFT) + #define LPSPI_TCR_CPHA (1 << 30) /* Bit 30: Clock Phase */ # define LPSPI_TCR_CPHA_CPT_LEAD (0 << 30) /* Data captured - leading edge of SCK and changed - following edge of SCK */ # define LPSPI_TCR_CPHA_CPT_FOLLOW (1 << 30) /* Data changed - leading edge of SCK and captured - following edge of SCK */ diff --git a/arch/arm/src/s32k1xx/hardware/s32k1xx_lpuart.h b/arch/arm/src/s32k1xx/hardware/s32k1xx_lpuart.h index 16b6fd57c67..4b6eb38823d 100644 --- a/arch/arm/src/s32k1xx/hardware/s32k1xx_lpuart.h +++ b/arch/arm/src/s32k1xx/hardware/s32k1xx_lpuart.h @@ -1,4 +1,4 @@ -/******************************************************************************************** +/**************************************************************************** * arch/arm/src/s32k1xx/hardware/s32k1xx_lpuart.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,23 +16,23 @@ * License for the specific language governing permissions and limitations * under the License. * - ********************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_S32K1XX_HARDWARE_S32K1XX_LPUART_H #define __ARCH_ARM_SRC_S32K1XX_HARDWARE_S32K1XX_LPUART_H -/******************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************/ + ****************************************************************************/ #include #include "hardware/s32k1xx_memorymap.h" -/******************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************/ + ****************************************************************************/ -/* Register offsets *************************************************************************/ +/* Register offsets *********************************************************/ #define S32K1XX_LPUART_VERID_OFFSET 0x0000 /* Version ID Register */ #define S32K1XX_LPUART_PARAM_OFFSET 0x0004 /* Parameter Register */ @@ -47,7 +47,7 @@ #define S32K1XX_LPUART_FIFO_OFFSET 0x0028 /* LPUART FIFO Register */ #define S32K1XX_LPUART_WATER_OFFSET 0x002c /* LPUART Watermark Register */ -/* Register addresses ***********************************************************************/ +/* Register addresses *******************************************************/ #define S32K1XX_LPUART0_VERID (S32K1XX_LPUART0_BASE + S32K1XX_LPUART_VERID_OFFSET) #define S32K1XX_LPUART0_PARAM (S32K1XX_LPUART0_BASE + S32K1XX_LPUART_PARAM_OFFSET) @@ -88,7 +88,7 @@ #define S32K1XX_LPUART2_FIFO (S32K1XX_LPUART2_BASE + S32K1XX_LPUART_FIFO_OFFSET) #define S32K1XX_LPUART2_WATER (S32K1XX_LPUART2_BASE + S32K1XX_LPUART_WATER_OFFSET) -/* Register bit definitions *****************************************************************/ +/* Register bit definitions *************************************************/ /* Version ID Register */ @@ -96,6 +96,7 @@ #define LPUART_VERID_FEATURE_MASK (0xffff << LPUART_VERID_FEATURE_SHIFT) # define LPUART_VERID_FEATURE_STD (1 << LPUART_VERID_FEATURE_SHIFT) /* Standard feature set */ # define LPUART_VERID_FEATURE_MODEM (3 << LPUART_VERID_FEATURE_SHIFT) /* MODEM/IrDA support */ + #define LPUART_VERID_MINOR_SHIFT (16) /* Bits 16-23: Minor Version Number */ #define LPUART_VERID_MINOR_MASK (0xff << LPUART_VERID_MINOR_SHIFT) #define LPUART_VERID_MAJOR_SHIFT (24) /* Bits 24-31: Major Version Number */ @@ -123,6 +124,7 @@ # define LPUART_PINCFG_TRGSEL_RXD (1 << LPUART_PINCFG_TRGSEL_SHIFT) /* Trigger used instead of RXD pin */ # define LPUART_PINCFG_TRGSEL_CTSB (2 << LPUART_PINCFG_TRGSEL_SHIFT) /* Trigger used instead of CTS_B pin */ # define LPUART_PINCFG_TRGSEL_TXDMOD (3 << LPUART_PINCFG_TRGSEL_SHIFT) /* Trigger used to modulate the TXD output */ + /* Bits 2-31: Reserved */ /* LPUART Baud Rate Register */ @@ -142,6 +144,7 @@ # define LPUART_BAUD_MATCFG_ONOFF (2 << LPUART_BAUD_MATCFG_SHIFT) /* Match On and Match Off */ # define LPUART_BAUD_MATCFG_RWUENAB (3 << LPUART_BAUD_MATCFG_SHIFT) /* Enables RWU on Data Match and Match * On/Off for transmitter CTS input */ + /* Bit 20: Reserved */ #define LPUART_BAUD_RDMAE (1 << 21) /* Bit 21: Receiver Full DMA Enable */ /* Bit 22: Reserved */ @@ -149,6 +152,7 @@ #define LPUART_BAUD_OSR_SHIFT (24) /* Bits 24-28: Oversampling Ratio */ #define LPUART_BAUD_OSR_MASK (15 << LPUART_BAUD_OSR_SHIFT) # define LPUART_BAUD_OSR(n) ((uint32_t)((n) - 1) << LPUART_BAUD_OSR_SHIFT) /* n=4..32 */ + #define LPUART_BAUD_M10 (1 << 29) /* Bit 20: 10-bit Mode select */ #define LPUART_BAUD_MAEN2 (1 << 30) /* Bit 30: Match Address Mode Enable 2 */ #define LPUART_BAUD_MAEN1 (1 << 31) /* Bit 31: Match Address Mode Enable 1 */ @@ -197,6 +201,7 @@ # define LPUART_CTRL_IDLECFG_32 (5 << LPUART_CTRL_IDLECFG_SHIFT) /* 32 idle characters */ # define LPUART_CTRL_IDLECFG_64 (6 << LPUART_CTRL_IDLECFG_SHIFT) /* 64 idle characters */ # define LPUART_CTRL_IDLECFG_128 (7 << LPUART_CTRL_IDLECFG_SHIFT) /* 128 idle characters */ + #define LPUART_CTRL_M7 (1 << 11) /* Bit 11: 7-Bit Mode Select */ /* Bits 12-13: Reserved */ #define LPUART_CTRL_MA2IE (1 << 14) /* Bit 14: Match 2 Interrupt Enable */ @@ -267,6 +272,7 @@ #define LPUART_MODIR_TNP_SHIFT (16) /* Bits 16-17: Transmitter narrow pulse */ #define LPUART_MODIR_TNP_MASK (3 << LPUART_MODIR_TNP_SHIFT) # define LPUART_MODIR_TNP(n) ((uint32_t)((n) - 1) << LPUART_MODIR_TNP_SHIFT) /* n/OSR */ + #define LPUART_MODIR_IREN (1 << 18) /* Bit nn: Infrared enable */ /* Bits 19-31: Reserved */ @@ -282,6 +288,7 @@ # define LPUART_FIFO_RXFIFOSIZE_64 (5 << LPUART_FIFO_RXFIFOSIZE_SHIFT) /* 64 datawords */ # define LPUART_FIFO_RXFIFOSIZE_128 (6 << LPUART_FIFO_RXFIFOSIZE_SHIFT) /* 128 datawords */ # define LPUART_FIFO_RXFIFOSIZE_256 (7 << LPUART_FIFO_RXFIFOSIZE_SHIFT) /* 256 datawords */ + #define LPUART_FIFO_RXFE (1 << 3) /* Bit 3: Receive FIFO Enable */ #define LPUART_FIFO_TXFIFOSIZE_SHIFT (4) /* Bits 4-6: Transmit FIFO. Buffer Depth */ #define LPUART_FIFO_TXFIFOSIZE_MASK (7 << LPUART_FIFO_TXFIFOSIZE_SHIFT) diff --git a/arch/arm/src/s32k1xx/hardware/s32k1xx_mcm.h b/arch/arm/src/s32k1xx/hardware/s32k1xx_mcm.h index 7f8bdffd16f..2f36dd2f3ff 100644 --- a/arch/arm/src/s32k1xx/hardware/s32k1xx_mcm.h +++ b/arch/arm/src/s32k1xx/hardware/s32k1xx_mcm.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/s32k1xx/hardware/s32k1xx_mcm.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,25 +16,25 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_S32K1XX_HARDWARE_S32K1XX_CMU_H #define __ARCH_ARM_SRC_S32K1XX_HARDWARE_S32K1XX_CMU_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include #ifdef CONFIG_ARCH_CHIP_S32K14X -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ -/* CMU Register Offsets *************************************************************/ +/* CMU Register Offsets *****************************************************/ #define S32K1XX_MCM_PLASC_BASE 0x0008 /* Crossbar Switch (AXBS) Slave Configuration */ #define S32K1XX_MCM_PLAMC_BASE 0x000a /* Crossbar Switch (AXBS) Master Configuration */ @@ -52,7 +52,7 @@ #define S32K1XX_MCM_LMFDHR_BASE 0x04a0 /* LMEM Fault Data High Register */ #define S32K1XX_MCM_LMFDLR_BASE 0x04a4 /* LMEM Fault Data Low Register */ -/* CMU Register Addresses ***********************************************************/ +/* CMU Register Addresses ***************************************************/ #define S32K1XX_MCM_PLASC (S32K1XX_MCM_BASE + S32K1XX_MCM_PLASC_BASE) #define S32K1XX_MCM_PLAMC (S32K1XX_MCM_BASE + S32K1XX_MCM_PLAMC_BASE) @@ -70,7 +70,7 @@ #define S32K1XX_MCM_LMFDHR (S32K1XX_MCM_BASE + S32K1XX_MCM_LMFDHR_BASE) #define S32K1XX_MCM_LMFDLR (S32K1XX_MCM_BASE + S32K1XX_MCM_LMFDLR_BASE) -/* CMU Register Bitfield Definitions ************************************************/ +/* CMU Register Bitfield Definitions ****************************************/ /* Crossbar Switch (AXBS) Slave Configuration (16-bit) */ @@ -87,6 +87,7 @@ # define MCM_CPCR_HLT_FSM_WTREQ (0 << MCM_CPCR_HLT_FSM_ST_SHIFT) /* Waiting for request */ # define MCM_CPCR_HLT_FSM_WTIDLE (1 << MCM_CPCR_HLT_FSM_ST_SHIFT) /* Waiting for platform idle */ # define MCM_CPCR_HLT_FSM_STALLED (2 << MCM_CPCR_HLT_FSM_ST_SHIFT) /* Platform stalled */ + #define MCM_CPCR_AXBS_HLT_REQ (1 << 2) /* Bit 2: AXBS Halt Request */ #define MCM_CPCR_AXBS_HLTD (1 << 3) /* Bit 3: AXBS Halted */ #define MCM_CPCR_FMC_PF_IDLE (1 << 4) /* Bit 4: Flash Memory Controller Program Flash Idle */ @@ -97,12 +98,14 @@ # define MCM_CPCR_SRAMUAP_RR (0 << MCM_CPCR_SRAMUAP_SHIFT) /* Round robin */ # define MCM_CPCR_SRAMUAP_SRR (1 << MCM_CPCR_SRAMUAP_SHIFT) /* Special round robin (favors SRAM backdoor) */# define MCM_CPCR_SRAMUAP_FIXEDP (2 << MCM_CPCR_SRAMUAP_SHIFT) /* Fixed priority. Processor has highest */ # define MCM_CPCR_SRAMUAP_FIXEDB (3 << MCM_CPCR_SRAMUAP_SHIFT) /* Fixed priority. Backdoor has highest */ + #define MCM_CPCR_SRAMUWP (1 << 26) /* Bit 26: SRAM_U Write Protect */ #define MCM_CPCR_SRAMLAP_SHIFT (28) /* Bits 28-29: SRAM_L Arbitration Priority */ #define MCM_CPCR_SRAMLAP_MASK (3 << MCM_CPCR_SRAMLAP_SHIFT) # define MCM_CPCR_SRAMLAP_RR (0 << MCM_CPCR_SRAMLAP_SHIFT) /* Round robin */ # define MCM_CPCR_SRAMLAP_SRR (1 << MCM_CPCR_SRAMLAP_SHIFT) /* Special round robin (favors SRAM backdoor) */# define MCM_CPCR_SRAMLAP_FIXEDP (2 << MCM_CPCR_SRAMLAP_SHIFT) /* Fixed priority. Processor has highest */ # define MCM_CPCR_SRAMLAP_FIXEDB (3 << MCM_CPCR_SRAMLAP_SHIFT) /* Fixed priority. Backdoor has highest */ + #define MCM_CPCR_SRAMLWP (1 << 30) /* Bit 30: SRAM_L Write Protect */ /* Interrupt Status and Control Register */ @@ -138,25 +141,30 @@ #define MCM_LMDR_CF0_MASK (15 << MCM_LMDR_CF0_SHIFT) # define MCM_LMDR_CF0_EEWG (0 << MCM_LMDR_CF0_SHIFT) /* CF0[0]: ECC Enable Write Generation */ # define MCM_LMDR_CF0_EERC (1 << MCM_LMDR_CF0_SHIFT) /* CF0[1]: ECC Enable Read Check */ + #define MCM_LMDR2_CF1_SHIFT (4) /* Bits 4-7: Control Field 1 (LMDR2) */ #define MCM_LMDR2_CF1_MASK (15 << MCM_LMDR2_CF1_SHIFT) # define MCM_LMDR2_CF1_PCPME (2 << MCM_LMDR2_CF1_SHIFT) /* CF1[1]: PC Parity Miss Enable */ # define MCM_LMDR2_CF1_PCPFE (8 << MCM_LMDR2_CF1_SHIFT) /* CF1[3]: PC Parity Fault Enable */ + #define MCM_LMDR_MT_SHIFT (13) /* Bits 13-15: Memory Type */ #define MCM_LMDR_MT_MASK (7 << MCM_LMDR_MT_SHIFT) # define MCM_LMDR_MT_SRAML (0 << MCM_LMDR_MT_SHIFT) /* SRAM_L (LMDR0 and LMDR1) */ # define MCM_LMDR_MT_SRAMU (1 << MCM_LMDR_MT_SHIFT) /* SRAM_U (LMDR0 and LMDR1) */ # define MCM_LMDR2_MT_PCCACHE (2 << MCM_LMDR_MT_SHIFT) /* PC Cache (LMDR2) */ + #define MCM_LMDR_LOCK (1 << 16) /* Bit 16: Lock */ #define MCM_LMDR_DPW_SHIFT (17) /* Bits 17-19: LMEM Data Path Width */ #define MCM_LMDR_DPW_MASK (7 << MCM_LMDR_DPW_SHIFT) # define MCM_LMDR_DPW_ 2BITS (2 << MCM_LMDR_DPW_SHIFT) /* LMEMn 32-bits wide */ # define MCM_LMDR_DPW_64BITS (3 << MCM_LMDR_DPW_SHIFT) /* LMEMn 64-bits wide */ + #define MCM_LMDR_WY_SHIFT (20) /* Bits 20-23: Level 1 Cache Ways */ #define MCM_LMDR_WY_MASK (15 << MCM_LMDR_WY_SHIFT) # define MCM_LMDR_WY_NOCACHE (0 << MCM_LMDR_WY_SHIFT) /* No Cache */ # define MCM_LMDR_WY_2WAY (2 << MCM_LMDR_WY_SHIFT) /* 2-Way Set Associative */ # define MCM_LMDR_WY_4WAY (4 << MCM_LMDR_WY_SHIFT) /* 4-Way Set Associative */ + #define MCM_LMDR_LMSZ_SHIFT (24) /* Bits 24-27: LMEM Size */ #define MCM_LMDR_LMSZ_MASK (15 << MCM_LMDR_LMSZ_SHIFT) # define MCM_LMDR_LMSZ_ MASK (0 << MCM_LMDR_LMSZ_SHIFT) /* No LMEMn (0 KB) */ @@ -176,6 +184,7 @@ # define MCM_LMDR_LMSZ_ MASK (14 << MCM_LMDR_LMSZ_SHIFT) /* 8192 KB LMEMn (LMDR0, LMDR1) */ # define MCM_LMDR_LMSZ_ MASK (15 << MCM_LMDR_LMSZ_SHIFT) /* 16384 KB LMEMn (LMDR0, LMDR1) */ # define MCM_LMDR2_LMSZ_ MASK (4 << MCM_LMDR_LMSZ_SHIFT) /* 4 KB LMEMn (LMDR2) */ + #define MCM_LMDR_LMSZH (1 << 28) /* Bit 28: LMEM Size Hole */ #define MCM_LMDR_V (1 << 31) /* Bit 31: Local Memory Valid */ @@ -207,6 +216,7 @@ # define MCM_LMPEIR_PEELOC_CSRAMU (9 << MCM_LMPEIR_PEELOC_SHIFT) /* 1-bit correctable ECC event from SRAM_U */ # define MCM_LMPEIR_PEELOC_PCTAG (14 << MCM_LMPEIR_PEELOC_SHIFT) /* PC tag parity error */ # define MCM_LMPEIR_PEELOC_PCDATA (15 << MCM_LMPEIR_PEELOC_SHIFT) /* PC data parity error */ + #define MCM_LMPEIR_V (1 << 31) /* Bit 31: Valid Bit */ /* LMEM Fault Address Register */ @@ -217,12 +227,14 @@ # define MCM_LMFAR_PEFPRT_SUPERVISOR (2 << MCM_LMFAR_PEFPRT_SHIFT) /* FATR[1]: Mode: 0=User mode, 1=Supervisor mode */ # define MCM_LMFAR_PEFPRT_BUFFERABLE (4 << MCM_LMFAR_PEFPRT_SHIFT) /* FATR[2]: Bufferable: 0=Non-bufferable, 1=Bufferable */ # define MCM_LMFAR_PEFPRT_CACHEABLE (8 << MCM_LMFAR_PEFPRT_SHIFT) /* FATR[3]: Cacheable: 0=Non-cacheable, 1=Cacheable */ + #define MCM_LMFAR_PEFSIZE_SHIFT (4) /* Bits 4-6: Parity/ECC Fault Master Size */ #define MCM_LMFAR_PEFSIZE_MASK (7 << MCM_LMFAR_PEFSIZE_SHIFT) # define MCM_LMFAR_PEFSIZE_8BIT (0 << MCM_LMFAR_PEFSIZE_SHIFT) /* 8-bit access */ # define MCM_LMFAR_PEFSIZE_16BIT (1 << MCM_LMFAR_PEFSIZE_SHIFT) /* 16-bit access */ # define MCM_LMFAR_PEFSIZE_32BIT (2 << MCM_LMFAR_PEFSIZE_SHIFT) /* 32-bit access */ # define MCM_LMFAR_PEFSIZE_64BIT (3 << MCM_LMFAR_PEFSIZE_SHIFT) /* 64-bit access */ + #define MCM_LMFAR_PEFW (1 << 7) /* Bit 7: Parity/ECC Fault Write */ #define MCM_LMFAR_PEFMST_SHIFT (8) /* Bits 8-15: Parity/ECC Fault Master Number */ #define MCM_LMFAR_PEFMST_MASK (0xff << MCM_LMFAR_PEFMST_SHIFT) @@ -237,12 +249,14 @@ # define MCM_LMFATR_PEFPRT_SUPERVISOR (2 << MCM_LMFATR_PEFPRT_SHIFT) /* FATR[1]: Mode: 0=User mode, 1=Supervisor mode */ # define MCM_LMFATR_PEFPRT_BUFFERABLE (4 << MCM_LMFATR_PEFPRT_SHIFT) /* FATR[2]: Bufferable: 0=Non-bufferable, 1=Bufferable */ # define MCM_LMFATR_PEFPRT_CACHEABLE (8 << MCM_LMFATR_PEFPRT_SHIFT) /* FATR[3]: Cacheable: 0=Non-cacheable, 1=Cacheable */ + #define MCM_LMFATR_PEFSIZE_SHIFT (4) /* Bits 4-6: Parity/ECC Fault Master Size */ #define MCM_LMFATR_PEFSIZE_MASK (7 << MCM_LMFATR_PEFSIZE_SHIFT) # define MCM_LMFATR_PEFSIZE_8BIT (0 << MCM_LMFATR_PEFSIZE_SHIFT) /* 8-bit access */ # define MCM_LMFATR_PEFSIZE_16BIT (1 << MCM_LMFATR_PEFSIZE_SHIFT) /* 16-bit access */ # define MCM_LMFATR_PEFSIZE_32BIT (2 << MCM_LMFATR_PEFSIZE_SHIFT) /* 32-bit access */ # define MCM_LMFATR_PEFSIZE_64BIT (3 << MCM_LMFATR_PEFSIZE_SHIFT) /* 64-bit access */ + #define MCM_LMFATR_PEFW (1 << 7) /* Bit 7: Parity/ECC Fault Write */ #define MCM_LMFATR_PEFMST_SHIFT (8) /* Bits 8-15: Parity/ECC Fault Master Number */ #define MCM_LMFATR_PEFMST_MASK (0xff << MCM_LMFATR_PEFMST_SHIFT) @@ -250,6 +264,7 @@ #define MCM_LMFATR_OVR (1 << 31) /* Bit 31: Overrun */ /* LMEM Fault Data High Register (32-bit address data) */ + /* LMEM Fault Data Low Register (32-bit address data) */ #endif /* CONFIG_ARCH_CHIP_S32K14X */ diff --git a/arch/arm/src/s32k1xx/hardware/s32k1xx_memorymap.h b/arch/arm/src/s32k1xx/hardware/s32k1xx_memorymap.h index d9557239c8a..dc7e6f5b628 100644 --- a/arch/arm/src/s32k1xx/hardware/s32k1xx_memorymap.h +++ b/arch/arm/src/s32k1xx/hardware/s32k1xx_memorymap.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/s32k1xx/hardware/s32k1xx_memorymap.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,20 +16,20 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_S32K1XX_HARDWARE_S32K1XX_MEMORYMAP_H #define __ARCH_ARM_SRC_S32K1XX_HARDWARE_S32K1XX_MEMORYMAP_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ #define S32K1XX_AIPS_LITE_BASE 0x40000000 /* Peripheral bridge (AIPS-Lite) */ # define S32K1XX_FLASHCFG_BASE 0x40000400 /* FLASH Configuration bytes */ diff --git a/arch/arm/src/s32k1xx/hardware/s32k1xx_mpu.h b/arch/arm/src/s32k1xx/hardware/s32k1xx_mpu.h index 2b7d96a2789..b3daea34ec4 100644 --- a/arch/arm/src/s32k1xx/hardware/s32k1xx_mpu.h +++ b/arch/arm/src/s32k1xx/hardware/s32k1xx_mpu.h @@ -1,4 +1,4 @@ -/**************************************************************************************************** +/**************************************************************************** * arch/arm/src/s32k1xx/hardware/s32k1xx_mpu.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,26 +16,26 @@ * License for the specific language governing permissions and limitations * under the License. * - ****************************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_S32K1XX_HARDWARE_S32K1XX_MPU_H #define __ARCH_ARM_SRC_S32K1XX_HARDWARE_S32K1XX_MPU_H -/**************************************************************************************************** +/**************************************************************************** * Included Files - ****************************************************************************************************/ + ****************************************************************************/ #include #include -/**************************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ****************************************************************************************************/ + ****************************************************************************/ #define S32K1XX_MPU_NSLAVE_PORTS 5 #define S32K1XX_MPU_NREGIONS 16 -/* MPU Register Offsets *****************************************************************************/ +/* MPU Register Offsets *****************************************************/ #define S32K1XX_MPU_CESR_OFFSET 0x000 /* Control/Error Status Register */ #define S32K1XX_MPU_SLAVEPORT_OFFSET(s) (0x0010 + ((s) << 3)) /* Slave port s offset, s=0..4 */ @@ -48,7 +48,7 @@ # define S32K1XX_MPU_RGD_WORD3_OFFSET 0x000c /* Region n descriptor word 3 */ #define S32K1XX_MPU_RGDAAC_OFFSET(r) (0x0800 + ((r) << 2)) /* Region n descriptor alternate access control */ -/* MPU Register Addresses ***************************************************************************/ +/* MPU Register Addresses ***************************************************/ #define S32K1XX_MPU_CESR (S32K1XX_MPU_BASE + S32K1XX_MPU_CESR_OFFSET) #define S32K1XX_MPU_SLAVEPORT_BASE(s) (S32K1XX_MPU_BASE + S32K1XX_MPU_SLAVEPORT_OFFSET(s)) @@ -61,7 +61,7 @@ # define S32K1XX_MPU_RGD_WORD3(r) (S32K1XX_MPU_RGD_BASE(r) + S32K1XX_MPU_RGD_WORD3_OFFSET) #define S32K1XX_MPU_RGDAAC(r) (S32K1XX_MPU_BASE + S32K1XX_MPU_RGDAAC_OFFSET(r)) -/* MPU Register Bitfield Definitions ****************************************************************/ +/* MPU Register Bitfield Definitions ****************************************/ /* Control/Error Status Register */ @@ -71,6 +71,7 @@ # define MPU_CESR_NRGD_8 (0 << MPU_CESR_NRGD_SHIFT) /* 8 region descriptors */ # define MPU_CESR_NRGD_12 (1 << MPU_CESR_NRGD_SHIFT) /* 12 region descriptors */ # define MPU_CESR_NRGD_16 (2 << MPU_CESR_NRGD_SHIFT) /* 16 region descriptors */ + #define MPU_CESR_NSP_SHIFT (12) /* Bits 12-15: Number Of Slave Ports */ #define MPU_CESR_NSP_MASK (15 << MPU_CESR_NSP_SHIFT) #define MPU_CESR_HRL_SHIFT (16) /* Bits 16-19: Hardware Revision Level */ @@ -94,6 +95,7 @@ # define MPU_EDR_EATTR_DUSER (1 << MPU_EDR_EATTR_SHIFT) /* User mode, data access */ # define MPU_EDR_EATTR_ISUPER (2 << MPU_EDR_EATTR_SHIFT) /* Supervisor mode, instruction access */ # define MPU_EDR_EATTR_DSUPER (3 << MPU_EDR_EATTR_SHIFT) /* Supervisor mode, data access */ + #define MPU_EDR_EMN_SHIFT (4) /* Bits 4-7: Error Master Number */ #define MPU_EDR_EMN_MASK (15 << MPU_EDR_EMN_SHIFT) #define MPU_EDR_EPID_SHIFT (8) /* Bits 8-15: Error Process Identification */ @@ -122,41 +124,48 @@ # define MPU_RGD_WORD2_M0SM_RX (1 << MPU_RGD_WORD2_M0SM_SHIFT) /* Read and execute allowed */ # define MPU_RGD_WORD2_M0SM_RW (2 << MPU_RGD_WORD2_M0SM_SHIFT) /* Read and write allowed */ # define MPU_RGD_WORD2_M0SM_M0UM (3 << MPU_RGD_WORD2_M0SM_SHIFT) /* Same as User mode defined in M0UM */ + #define MPU_RGD_WORD2_M0PE (1 << 5) /* Bit 5: Bus Master 0 Process Identifier enable */ #define MPU_RGD_WORD2_M1UM_SHIFT (6) /* Bits 6-8: Bus Master 1 User Mode Access Control */ #define MPU_RGD_WORD2_M1UM_MASK (7 << MPU_RGD_WORD2_M1UM_SHIFT) # define MPU_RGD_WORD2_M1UM_XACCESS (1 << MPU_RGD_WORD2_M1UM_SHIFT) # define MPU_RGD_WORD2_M1UM_WACCESS (2 << MPU_RGD_WORD2_M1UM_SHIFT) # define MPU_RGD_WORD2_M1UM_RACCESS (4 << MPU_RGD_WORD2_M1UM_SHIFT) + #define MPU_RGD_WORD2_M1SM_SHIFT (9) /* Bits 9-10: Bus Master 1 Supervisor Mode Access Control */ #define MPU_RGD_WORD2_M1SM_MASK (3 << MPU_RGD_WORD2_M1SM_SHIFT) # define MPU_RGD_WORD2_M1SM_RWX (0 << MPU_RGD_WORD2_M1SM_SHIFT) /* Read, write and execute allowed */ # define MPU_RGD_WORD2_M1SM_RX (1 << MPU_RGD_WORD2_M1SM_SHIFT) /* Read and execute allowed */ # define MPU_RGD_WORD2_M1SM_RW (2 << MPU_RGD_WORD2_M1SM_SHIFT) /* Read and write allowed */ # define MPU_RGD_WORD2_M1SM_M1UM (3 << MPU_RGD_WORD2_M1SM_SHIFT) /* Same as User mode defined in M1UM */ + #define MPU_RGD_WORD2_M1PE (1 << 11) /* Bit 11: Bus Master 1 Process Identifier enable */ #define MPU_RGD_WORD2_M2UM_SHIFT (12) /* Bits 12-14: Bus Master 2 User Mode Access control */ #define MPU_RGD_WORD2_M2UM_MASK (7 << MPU_RGD_WORD2_M2UM_SHIFT) # define MPU_RGD_WORD2_M2UM_XACCESS (1 << MPU_RGD_WORD2_M2UM_SHIFT) # define MPU_RGD_WORD2_M2UM_WACCESS (2 << MPU_RGD_WORD2_M2UM_SHIFT) # define MPU_RGD_WORD2_M2UM_RACCESS (4 << MPU_RGD_WORD2_M2UM_SHIFT) + #define MPU_RGD_WORD2_M2SM_SHIFT (15) /* Bits 15-16: Bus Master 2 Supervisor Mode Access Control */ #define MPU_RGD_WORD2_M2SM_MASK (3 << MPU_RGD_WORD2_M2SM_SHIFT) # define MPU_RGD_WORD2_M2SM_RWX (0 << MPU_RGD_WORD2_M2SM_SHIFT) /* Read, write and execute allowed */ # define MPU_RGD_WORD2_M2SM_RX (1 << MPU_RGD_WORD2_M2SM_SHIFT) /* Read and execute allowed */ # define MPU_RGD_WORD2_M2SM_RW (2 << MPU_RGD_WORD2_M2SM_SHIFT) /* Read and write allowed */ # define MPU_RGD_WORD2_M2SM_M2UM (3 << MPU_RGD_WORD2_M2SM_SHIFT) /* Same as User mode defined in M2UM */ + #define MPU_RGD_WORD2_M3UM_SHIFT (18) /* Bits 18-20: Bus Master 3 User Mode Access Control */ #define MPU_RGD_WORD2_M3UM_MASK (7 << MPU_RGD_WORD2_M3UM_SHIFT) # define MPU_RGD_WORD2_M3UM_XACCESS (1 << MPU_RGD_WORD2_M3UM_SHIFT) # define MPU_RGD_WORD2_M3UM_WACCESS (2 << MPU_RGD_WORD2_M3UM_SHIFT) # define MPU_RGD_WORD2_M3UM_RACCESS (4 << MPU_RGD_WORD2_M3UM_SHIFT) + #define MPU_RGD_WORD2_M3SM_SHIFT (21) /* Bits 21-22: Bus Master 3 Supervisor Mode Access Control */ #define MPU_RGD_WORD2_M3SM_MASK (3 << MPU_RGD_WORD2_M3SM_SHIFT) # define MPU_RGD_WORD2_M3SM_RWX (0 << MPU_RGD_WORD2_M3SM_SHIFT) /* Read, write and execute allowed */ # define MPU_RGD_WORD2_M3SM_RX (1 << MPU_RGD_WORD2_M3SM_SHIFT) /* Read and execute allowed */ # define MPU_RGD_WORD2_M3SM_RW (2 << MPU_RGD_WORD2_M3SM_SHIFT) /* Read and write allowed */ # define MPU_RGD_WORD2_M3SM_M3UM (3 << MPU_RGD_WORD2_M3SM_SHIFT) /* Same as User mode defined in M3UM */ + #define MPU_RGD_WORD2_M4WE (1 << 24) /* Bit 24: Bus Master 4 Write Enable */ #define MPU_RGD_WORD2_M4RE (1 << 25) /* Bit 25: Bus Master 4 Read Enable */ #define MPU_RGD_WORD2_M5RE (1 << 27) /* Bit 27: Bus Master 5 Read Enable */ @@ -189,6 +198,7 @@ # define MPU_RGDAAC_M0SM_RX (1 << MPU_RGDAAC_M0SM_SHIFT) /* Read and execute allowed */ # define MPU_RGDAAC_M0SM_RW (2 << MPU_RGDAAC_M0SM_SHIFT) /* Read and write allowed */ # define MPU_RGDAAC_M0SM_M0UM (3 << MPU_RGDAAC_M0SM_SHIFT) /* Same as User mode defined in M0UM */ + #define MPU_RGDAAC_M0PE (1 << 5) /* Bit 5: Bus Master 0 Process Identifier enable */ #define MPU_RGDAAC_M1UM_SHIFT (6) /* Bits 6-8: Bus Master 1 User Mode Access Control */ #define MPU_RGDAAC_M1UM_MASK (7 << MPU_RGDAAC_M1UM_SHIFT) @@ -201,29 +211,34 @@ # define MPU_RGDAAC_M1SM_RX (1 << MPU_RGDAAC_M1SM_SHIFT) /* Read and execute allowed */ # define MPU_RGDAAC_M1SM_RW (2 << MPU_RGDAAC_M1SM_SHIFT) /* Read and write allowed */ # define MPU_RGDAAC_M1SM_M1UM (3 << MPU_RGDAAC_M1SM_SHIFT) /* Same as User mode defined in M1UM */ + #define MPU_RGDAAC_M1PE (1 << 11) /* Bit 11: Bus Master 1 Process Identifier enable */ #define MPU_RGDAAC_M2UM_SHIFT (12) /* Bits 12-14: Bus Master 2 User Mode Access control */ #define MPU_RGDAAC_M2UM_MASK (7 << MPU_RGDAAC_M2UM_SHIFT) # define MPU_RGDAAC_M2UM_XACCESS (1 << MPU_RGDAAC_M2UM_SHIFT) # define MPU_RGDAAC_M2UM_WACCESS (2 << MPU_RGDAAC_M2UM_SHIFT) # define MPU_RGDAAC_M2UM_RACCESS (4 << MPU_RGDAAC_M2UM_SHIFT) + #define MPU_RGDAAC_M2SM_SHIFT (15) /* Bits 15-16: Bus Master 2 Supervisor Mode Access Control */ #define MPU_RGDAAC_M2SM_MASK (3 << MPU_RGDAAC_M2SM_SHIFT) # define MPU_RGDAAC_M2SM_RWX (0 << MPU_RGDAAC_M2SM_SHIFT) /* Read, write and execute allowed */ # define MPU_RGDAAC_M2SM_RX (1 << MPU_RGDAAC_M2SM_SHIFT) /* Read and execute allowed */ # define MPU_RGDAAC_M2SM_RW (2 << MPU_RGDAAC_M2SM_SHIFT) /* Read and write allowed */ # define MPU_RGDAAC_M2SM_M2UM (3 << MPU_RGDAAC_M2SM_SHIFT) /* Same as User mode defined in M2UM */ + #define MPU_RGDAAC_M3UM_SHIFT (18) /* Bits 18-20: Bus Master 3 User Mode Access Control */ #define MPU_RGDAAC_M3UM_MASK (7 << MPU_RGDAAC_M3UM_SHIFT) # define MPU_RGDAAC_M3UM_XACCESS (1 << MPU_RGDAAC_M3UM_SHIFT) # define MPU_RGDAAC_M3UM_WACCESS (2 << MPU_RGDAAC_M3UM_SHIFT) # define MPU_RGDAAC_M3UM_RACCESS (4 << MPU_RGDAAC_M3UM_SHIFT) + #define MPU_RGDAAC_M3SM_SHIFT (21) /* Bits 21-22: Bus Master 3 Supervisor Mode Access Control */ #define MPU_RGDAAC_M3SM_MASK (3 << MPU_RGDAAC_M3SM_SHIFT) # define MPU_RGDAAC_M3SM_RWX (0 << MPU_RGDAAC_M3SM_SHIFT) /* Read, write and execute allowed */ # define MPU_RGDAAC_M3SM_RX (1 << MPU_RGDAAC_M3SM_SHIFT) /* Read and execute allowed */ # define MPU_RGDAAC_M3SM_RW (2 << MPU_RGDAAC_M3SM_SHIFT) /* Read and write allowed */ # define MPU_RGDAAC_M3SM_M3UM (3 << MPU_RGDAAC_M3SM_SHIFT) /* Same as User mode defined in M3UM */ + #define MPU_RGDAAC_M4WE (1 << 24) /* Bit 24: Bus Master 4 Write Enable */ #define MPU_RGDAAC_M4RE (1 << 25) /* Bit 25: Bus Master 4 Read Enable */ #define MPU_RGDAAC_M5RE (1 << 27) /* Bit 27: Bus Master 5 Read Enable */ diff --git a/arch/arm/src/s32k1xx/hardware/s32k1xx_pcc.h b/arch/arm/src/s32k1xx/hardware/s32k1xx_pcc.h index 9e3debdc15b..8578f973420 100644 --- a/arch/arm/src/s32k1xx/hardware/s32k1xx_pcc.h +++ b/arch/arm/src/s32k1xx/hardware/s32k1xx_pcc.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/s32k1xx/hardware/s32k1xx_pcc.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,23 +16,23 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_S32K1XX_HARDWARE_S32K1XX_PCC_H #define __ARCH_ARM_SRC_S32K1XX_HARDWARE_S32K1XX_PCC_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* PCC Register Offsets *************************************************************/ +/* PCC Register Offsets *****************************************************/ #define S32K1XX_PCC_FTFC_OFFSET 0x0080 /* PCC FTFC Register */ #define S32K1XX_PCC_DMAMUX_OFFSET 0x0084 /* PCC DMAMUX Register */ @@ -78,7 +78,7 @@ #define S32K1XX_PCC_QSPI_OFFSET 0x01d8 /* PCC QSPI Register */ #define S32K1XX_PCC_ENET_OFFSET 0x01e4 /* PCC ENET Register */ -/* PCC Register Addresses ***********************************************************/ +/* PCC Register Addresses ***************************************************/ #define S32K1XX_PCC_FTFC (S32K1XX_PCC_BASE + S32K1XX_PCC_FTFC_OFFSET) #define S32K1XX_PCC_DMAMUX (S32K1XX_PCC_BASE + S32K1XX_PCC_DMAMUX_OFFSET) @@ -124,15 +124,16 @@ #define S32K1XX_PCC_QSPI (S32K1XX_PCC_BASE + S32K1XX_PCC_QSPI_OFFSET) #define S32K1XX_PCC_ENET (S32K1XX_PCC_BASE + S32K1XX_PCC_ENET_OFFSET) -/* PCC Register Bitfield Definitions ************************************************/ +/* PCC Register Bitfield Definitions ****************************************/ -/* The form of each PCC register is the same as follows. Some register, however, do - * not support all of the fields: +/* The form of each PCC register is the same as follows. + * Some register, however, do not support all of the fields: * * PCD - ENET * FRAC - ENET - * PCS - FTM3, ADC0, ADC1, LPSPI0, LPSPI1, LPSPI2, LPIT, FTM0, FTM2, FTM4, FTM6, - * FTM7, LPTMR0, FLEXIO, LPI2C0, LPCI2C1, UART0, UART1, UART2, ENET + * PCS - FTM3, ADC0, ADC1, LPSPI0, LPSPI1, LPSPI2, LPIT, + * FTM0, FTM2, FTM4, FTM6, FTM7, LPTMR0, FLEXIO, LPI2C0, LPCI2C1, + * UART0, UART1, UART2, ENET * CGC - All PCC registers * PR - All PCC registers */ diff --git a/arch/arm/src/s32k1xx/hardware/s32k1xx_pinmux.h b/arch/arm/src/s32k1xx/hardware/s32k1xx_pinmux.h index c9173e84e5c..02dc07dc6ef 100644 --- a/arch/arm/src/s32k1xx/hardware/s32k1xx_pinmux.h +++ b/arch/arm/src/s32k1xx/hardware/s32k1xx_pinmux.h @@ -1,4 +1,4 @@ -/******************************************************************************************** +/**************************************************************************** * arch/arm/src/s32k1xx/hardware/s32k1xx_pinmux.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,20 +16,22 @@ * License for the specific language governing permissions and limitations * under the License. * - ********************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_S32K1XX_HARDWARE_S32K1XX_PINMUX_H #define __ARCH_ARM_SRC_S32K1XX_HARDWARE_S32K1XX_PINMUX_H -/******************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" -/* This file is just a wrapper around pin muxing header files for the select S32K1xx family. */ +/* This file is just a wrapper around pin muxing header files for the select + * S32K1xx family. + */ #if defined(CONFIG_ARCH_CHIP_S32K116) # include "hardware/s32k116_pinmux.h" @@ -47,20 +49,20 @@ # error "No pin multiplexing for this S32K1xx part" #endif -/******************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** +/**************************************************************************** * Public Types - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** +/**************************************************************************** * Public Data - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** - * Public Functions - ********************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_S32K1XX_HARDWARE_S32K1XX_PINMUX_H */ diff --git a/arch/arm/src/s32k1xx/hardware/s32k1xx_pmc.h b/arch/arm/src/s32k1xx/hardware/s32k1xx_pmc.h index 6b326b143d3..d3e20430c85 100644 --- a/arch/arm/src/s32k1xx/hardware/s32k1xx_pmc.h +++ b/arch/arm/src/s32k1xx/hardware/s32k1xx_pmc.h @@ -1,4 +1,4 @@ -/********************************************************************************************* +/**************************************************************************** * arch/arm/src/s32k1xx/hardware/s32k1xx_pmc.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,37 +16,37 @@ * License for the specific language governing permissions and limitations * under the License. * - *********************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_S32K1XX_HARDWARE_S32K1XX_PMC_H #define __ARCH_ARM_SRC_S32K1XX_HARDWARE_S32K1XX_PMC_H -/********************************************************************************************* +/**************************************************************************** * Included Files - *********************************************************************************************/ + ****************************************************************************/ #include #include -/********************************************************************************************* +/**************************************************************************** * Pre-processor Definitions - *********************************************************************************************/ + ****************************************************************************/ -/* PMC Register Offsets **********************************************************************/ +/* PMC Register Offsets *****************************************************/ #define S32K1XX_PMC_LVDSC1_OFFSET 0x0000 /* Low Voltage Detect Status and Control 1 Register */ #define S32K1XX_PMC_LVDSC2_OFFSET 0x0001 /* Low Voltage Detect Status and Control 2 Register */ #define S32K1XX_PMC_REGSC_OFFSET 0x0002 /* Regulator Status and Control Register */ #define S32K1XX_PMC_LPOTRIM_OFFSET 0x0004 /* Low Power Oscillator Trim Register */ -/* PMC Register Addresses ********************************************************************/ +/* PMC Register Addresses ***************************************************/ #define S32K1XX_PMC_LVDSC1 (S32K1XX_PMC_BASE + S32K1XX_PMC_LVDSC1_OFFSET) #define S32K1XX_PMC_LVDSC2 (S32K1XX_PMC_BASE + S32K1XX_PMC_LVDSC2_OFFSET) #define S32K1XX_PMC_REGSC (S32K1XX_PMC_BASE + S32K1XX_PMC_REGSC_OFFSET) #define S32K1XX_PMC_LPOTRIM (S32K1XX_PMC_BASE + S32K1XX_PMC_LPOTRIM_OFFSET) -/* PMC Register Bitfield Definitions *********************************************************/ +/* PMC Register Bitfield Definitions ****************************************/ /* Low Voltage Detect Status and Control 1 Register */ diff --git a/arch/arm/src/s32k1xx/hardware/s32k1xx_port.h b/arch/arm/src/s32k1xx/hardware/s32k1xx_port.h index a258953fc15..3200c4f0f4d 100644 --- a/arch/arm/src/s32k1xx/hardware/s32k1xx_port.h +++ b/arch/arm/src/s32k1xx/hardware/s32k1xx_port.h @@ -1,4 +1,4 @@ -/**************************************************************************************************** +/**************************************************************************** * arch/arm/src/s32k1xx/hardware/s32k1xx_port.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,21 +16,21 @@ * License for the specific language governing permissions and limitations * under the License. * - ****************************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_S32K1XX_HARDWARE_S32K1XX_PORT_H #define __ARCH_ARM_SRC_S32K1XX_HARDWARE_S32K1XX_PORT_H -/**************************************************************************************************** +/**************************************************************************** * Included Files - ****************************************************************************************************/ + ****************************************************************************/ #include #include -/**************************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ****************************************************************************************************/ + ****************************************************************************/ #define S32K1XX_PORTA 0 #define S32K1XX_PORTB 1 @@ -39,9 +39,10 @@ #define S32K1XX_PORTE 4 #define S32K1XX_NPORTS 5 -/* PORT Register Offsets ****************************************************************************/ +/* PORT Register Offsets ****************************************************/ #define S32K1XX_PORT_PCR_OFFSET(n) (0 + ((n) << 2)) /* Pin Control Register n=0..31 */ + #define S32K1XX_PORT_GPCLR_OFFSET 0x0080 /* Global Pin Control Low Register */ #define S32K1XX_PORT_GPCHR_OFFSET 0x0084 /* Global Pin Control High Register */ #define S32K1XX_PORT_GICLR_OFFSET 0x0088 /* Global Interrupt Control Low Register */ @@ -51,7 +52,7 @@ #define S32K1XX_PORT_DFCR_OFFSET 0x00c4 /* Digital Filter Clock Register */ #define S32K1XX_PORT_DFWR_OFFSET 0x00c8 /* Digital Filter Width Register */ -/* PORT Register Addresses **************************************************************************/ +/* PORT Register Addresses **************************************************/ #define S32K1XX_PORT_PCR_BASE(p,n) (S32K1XX_PORT_BASE(p) + S32K1XX_PORT_PCR_OFFSET(n)) #define S32K1XX_PORT_GPCLR(p) (S32K1XX_PORT_BASE(p) + S32K1XX_PORT_GPCLR_OFFSET) @@ -113,7 +114,7 @@ #define S32K1XX_PORTE_DFCR (S32K1XX_PORTE_BASE + S32K1XX_PORT_DFCR_OFFSET) #define S32K1XX_PORTE_DFWR (S32K1XX_PORTE_BASE + S32K1XX_PORT_DFWR_OFFSET) -/* PORT Register Bitfield Definitions ***************************************************************/ +/* PORT Register Bitfield Definitions ***************************************/ /* Pin Control Register n=0..31 */ @@ -133,6 +134,7 @@ # define PORT_PCR_MUX_ALT5 (5 << PORT_PCR_MUX_SHIFT) /* Alternative 5 (chip-specific) */ # define PORT_PCR_MUX_ALT6 (6 << PORT_PCR_MUX_SHIFT) /* Alternative 6 (chip-specific) */ # define PORT_PCR_MUX_ALT7 (7 << PORT_PCR_MUX_SHIFT) /* Alternative 7 (chip-specific) */ + #define PORT_PCR_LK (1 << 15) /* Bit 15: Lock Register */ #define PORT_PCR_IRQC_SHIFT (16) /* Bits 16-19: Interrupt Configuration */ #define PORT_PCR_IRQC_MASK (15 << PORT_PCR_IRQC_SHIFT) @@ -145,6 +147,7 @@ # define PORT_PCR_IRQC_FALLING (10 << PORT_PCR_IRQC_SHIFT) /* ISF flag and Interrupt on falling-edge */ # define PORT_PCR_IRQC_BOTH (11 << PORT_PCR_IRQC_SHIFT) /* ISF flag and Interrupt on either edge */ # define PORT_PCR_IRQC_ONE (12 << PORT_PCR_IRQC_SHIFT) /* ISF flag and Interrupt when logic 1 */ + #define PORT_PCR_ISF (1 << 24) /* Bit 24: Interrupt Status Flag */ /* Global Pin Control Low Register */ @@ -152,6 +155,7 @@ #define PORT_GPCLR_GPWD_SHIFT (0) /* Bits 0-15: Global Pin Write Data */ #define PORT_GPCLR_GPWD_MASK (0xffff << PORT_GPCLR_GPWD_SHIFT) # define PORT_GPCLR_GPWD_PIN(n) ((uint32_t)(n) << PORT_GPCLR_GPWD_SHIFT) /* Pin n=0..15 */ + #define PORT_GPCLR_GPWE_SHIFT (16) /* Bits 16-31: Global Pin Write Enable */ #define PORT_GPCLR_GPWE_MASK (0xffff << PORT_GPCLR_GPWE_SHIFT) # define PORT_GPCLR_GPWE_PIN(n) ((uint32_t)(n) << PORT_GPCLR_GPWE_SHIFT) /* Pin n=0..15 */ @@ -161,6 +165,7 @@ #define PORT_GPCHR_GPWD_SHIFT (0) /* Bits 0-15: Global Pin Write Data */ #define PORT_GPCHR_GPWD_MASK (0xffff << PORT_GPCHR_GPWD_SHIFT) # define PORT_GPCHR_GPWD_PIN(n) ((uint32_t)((n) - 16) << PORT_GPCHR_GPWD_SHIFT) /* Pin n=16..31 */ + #define PORT_GPCHR_GPWE_SHIFT (16) /* Bits 16-31: Global Pin Write Enable */ #define PORT_GPCHR_GPWE_MASK (0xffff << PORT_GPCHR_GPWE_SHIFT) # define PORT_GPCHR_GPWE_PIN(n) ((uint32_t)((n) - 16) << PORT_GPCHR_GPWE_SHIFT) /* Pin n=16..31 */ @@ -170,6 +175,7 @@ #define PORT_GICLR_GIWD_SHIFT (0) /* Bits 0-15: Global Interrupt Write Data */ #define PORT_GICLR_GIWD_MASK (0xffff << PORT_GICLR_GIWD_SHIFT) # define PORT_GICLR_GIWD_PIN(n) ((uint32_t)(n) << PORT_GICLR_GIWD_SHIFT) /* Pin n=0..15 */ + #define PORT_GICLR_GIWE_SHIFT (16) /* Bits 16-31: Global Interrupt Write Enable */ #define PORT_GICLR_GIWE_MASK (0xffff << PORT_GICLR_GIWE_SHIFT) # define PORT_GICLR_GIWE_PIN(n) ((uint32_t)(n) << PORT_GICLR_GIWE_SHIFT) /* Pin n=0..15 */ @@ -179,6 +185,7 @@ #define PORT_GICHR_GIWD_SHIFT (0) /* Bits 0-15: Global Interrupt Write Data */ #define PORT_GICHR_GIWD_MASK (0xffff << PORT_GICHR_GIWD_SHIFT) # define PORT_GICHR_GIWD_PIN(n) ((uint32_t)((n) - 16) << PORT_GICHR_GIWD_SHIFT) /* Pin n=16..31 */ + #define PORT_GICHR_GIWE_SHIFT (16) /* Bits 16-31: Global Interrupt Write Enable */ #define PORT_GICHR_GIWE_MASK (0xffff << PORT_GICHR_GIWE_SHIFT) # define PORT_GICHR_GIWE_PIN(n) ((uint32_t)((n) - 16) << PORT_GICHR_GIWE_SHIFT) /* Pin n=16..31 */ diff --git a/arch/arm/src/s32k1xx/hardware/s32k1xx_rcm.h b/arch/arm/src/s32k1xx/hardware/s32k1xx_rcm.h index 45527898071..61dcf04cb2c 100644 --- a/arch/arm/src/s32k1xx/hardware/s32k1xx_rcm.h +++ b/arch/arm/src/s32k1xx/hardware/s32k1xx_rcm.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/s32k1xx/hardware/s32k1xx_rcm.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,23 +16,23 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_S32K1XX_HARDWARE_S32K1XX_RCM_H #define __ARCH_ARM_SRC_S32K1XX_HARDWARE_S32K1XX_RCM_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* RCM Register Offsets *************************************************************/ +/* RCM Register Offsets *****************************************************/ #define S32K1XX_RCM_VERID_OFFSET 0x0000 /* Version ID Register */ #define S32K1XX_RCM_PARAM_OFFSET 0x0004 /* Parameter Register */ @@ -41,7 +41,7 @@ #define S32K1XX_RCM_SSRS_OFFSET 0x0018 /* Sticky System Reset Status Register */ #define S32K1XX_RCM_SRIE_OFFSET 0x001c /* System Reset Interrupt Enable Register */ -/* RCM Register Addresses ***********************************************************/ +/* RCM Register Addresses ***************************************************/ #define S32K1XX_RCM_VERID (S32K1XX_RCM_BASE + S32K1XX_RCM_VERID_OFFSET) #define S32K1XX_RCM_PARAM (S32K1XX_RCM_BASE + S32K1XX_RCM_PARAM_OFFSET) @@ -50,13 +50,14 @@ #define S32K1XX_RCM_SSRS (S32K1XX_RCM_BASE + S32K1XX_RCM_SSRS_OFFSET) #define S32K1XX_RCM_SRIE (S32K1XX_RCM_BASE + S32K1XX_RCM_SRIE_OFFSET) -/* RCM Register Bitfield Definitions ************************************************/ +/* RCM Register Bitfield Definitions ****************************************/ /* Version ID Register */ #define RCM_VERID_FEATURE_SHIFT (0) /* Bits 0-15: Feature Specification Number */ #define RCM_VERID_FEATURE_MASK (0xffff << RCM_VERID_FEATURE_SHIFT) # define RCM_VERID_FEATURE_STD (3 << RCM_VERID_FEATURE_SHIFT) /* Standard feature set*/ + #define RCM_VERID_MINOR_SHIFT (16) /* Bits 16-23: Minor Version Number */ #define RCM_VERID_MINOR_MASK (0xff << RCM_VERID_MINOR_SHIFT) #define RCM_VERID_MAJOR_SHIFT (24) /* Bits 24-31: Major Version Number */ @@ -102,6 +103,7 @@ # define RCM_RPC_RSTFLTSRW_DISABLE (0 << RCM_RPC_RSTFLTSRW_SHIFT) /* All filtering disabled */ # define RCM_RPC_RSTFLTSRW_BUSCLK (1 << RCM_RPC_RSTFLTSRW_SHIFT) /* Bus clock filter enabled for normal operation */ # define RCM_RPC_RSTFLTSRW_LPOCLK (2 << RCM_RPC_RSTFLTSRW_SHIFT) /* LPO clock filter enabled for normal operation */ + #define RCM_RPC_RSTFLTSS (1 << 2) /* Bit 2: Reset Pin Filter Select in Stop Mode */ #define RCM_RPC_RSTFLTSEL_SHIFT (8) /* Bits 8-12: Reset Pin Filter Bus Clock Select */ #define RCM_RPC_RSTFLTSEL_MASK (31 << RCM_RPC_RSTFLTSEL_SHIFT) @@ -130,6 +132,7 @@ # define RCM_SRIE_DELAY_34 (1 << RCM_SRIE_DELAY_SHIFT) /* 34 LPO cycles */ # define RCM_SRIE_DELAY_130 (2 << RCM_SRIE_DELAY_SHIFT) /* 130 LPO cycles */ # define RCM_SRIE_DELAY_514 (3 << RCM_SRIE_DELAY_SHIFT) /* 514 LPO cycles */ + #define RCM_SRIE_LOC (1 << 2) /* Bit 2: Loss-of-Clock Interrupt */ #define RCM_SRIE_LOL (1 << 3) /* Bit 3: Loss-of-Lock Interrupt */ #define RCM_SRIE_CMU_LOC (1 << 4) /* Bit 4: CMU Loss-of-Clock Reset Interrupt */ diff --git a/arch/arm/src/s32k1xx/hardware/s32k1xx_rtc.h b/arch/arm/src/s32k1xx/hardware/s32k1xx_rtc.h index 297f98d3aa7..e6c2ec165df 100644 --- a/arch/arm/src/s32k1xx/hardware/s32k1xx_rtc.h +++ b/arch/arm/src/s32k1xx/hardware/s32k1xx_rtc.h @@ -1,4 +1,4 @@ -/**************************************************************************************************** +/**************************************************************************** * arch/arm/src/s32k1xx/hardware/s32k1xx_rtc.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,23 +16,23 @@ * License for the specific language governing permissions and limitations * under the License. * - ****************************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_S32K1XX_HARDWARE_S32K1XX_RTC_H #define __ARCH_ARM_SRC_S32K1XX_HARDWARE_S32K1XX_RTC_H -/**************************************************************************************************** +/**************************************************************************** * Included Files - ****************************************************************************************************/ + ****************************************************************************/ #include #include -/**************************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ****************************************************************************************************/ + ****************************************************************************/ -/* RTC Register Offsets *****************************************************************************/ +/* RTC Register Offsets *****************************************************/ #define S32K1XX_RTC_TSR_OFFSET 0x0000 /* Time Seconds register */ #define S32K1XX_RTC_TPR_OFFSET 0x0004 /* Time Prescaler Register */ @@ -43,7 +43,7 @@ #define S32K1XX_RTC_LR_OFFSET 0x0018 /* Lock Register */ #define S32K1XX_RTC_IER_OFFSET 0x001C /* Interrupt Enable Register */ -/* RTC Register Addresses ***************************************************************************/ +/* RTC Register Addresses ***************************************************/ #define S32K1XX_RTC_TSR (S32K1XX_RTC_BASE + S32K1XX_RTC_TSR_OFFSET) #define S32K1XX_RTC_TPR (S32K1XX_RTC_BASE + S32K1XX_RTC_TPR_OFFSET) @@ -54,7 +54,7 @@ #define S32K1XX_RTC_LR (S32K1XX_RTC_BASE + S32K1XX_RTC_LR_OFFSET) #define S32K1XX_RTC_IER (S32K1XX_RTC_BASE + S32K1XX_RTC_IER_OFFSET) -/* RTC Register Bitfield Definitions ****************************************************************/ +/* RTC Register Bitfield Definitions ****************************************/ /* TSR Bit Fields */ diff --git a/arch/arm/src/s32k1xx/hardware/s32k1xx_scg.h b/arch/arm/src/s32k1xx/hardware/s32k1xx_scg.h index 2065813c678..f7afd10e468 100644 --- a/arch/arm/src/s32k1xx/hardware/s32k1xx_scg.h +++ b/arch/arm/src/s32k1xx/hardware/s32k1xx_scg.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/s32k1xx/hardware/s32k1xx_scg.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,23 +16,23 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_S32K1XX_HARDWARE_S32K1XX_SCG_H #define __ARCH_ARM_SRC_S32K1XX_HARDWARE_S32K1XX_SCG_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* SCG Register Offsets *************************************************************/ +/* SCG Register Offsets *****************************************************/ #define S32K1XX_SCG_VERID_OFFSET 0x0000 /* Version ID Register */ #define S32K1XX_SCG_PARAM_OFFSET 0x0004 /* Parameter Register */ @@ -54,7 +54,7 @@ #define S32K1XX_SCG_SPLLDIV_OFFSET 0x0604 /* System PLL Divide Register */ #define S32K1XX_SCG_SPLLCFG_OFFSET 0x0608 /* System PLL Configuration Register */ -/* SCG Register Addresses ***********************************************************/ +/* SCG Register Addresses ***************************************************/ #define S32K1XX_SCG_VERID (S32K1XX_SCG_BASE + S32K1XX_SCG_VERID_OFFSET) #define S32K1XX_SCG_PARAM (S32K1XX_SCG_BASE + S32K1XX_SCG_PARAM_OFFSET) @@ -76,7 +76,7 @@ #define S32K1XX_SCG_SPLLDIV (S32K1XX_SCG_BASE + S32K1XX_SCG_SPLLDIV_OFFSET) #define S32K1XX_SCG_SPLLCFG (S32K1XX_SCG_BASE + S32K1XX_SCG_SPLLCFG_OFFSET) -/* SCG Register Bitfield Definitions ************************************************/ +/* SCG Register Bitfield Definitions ****************************************/ /* Version ID Register (32-bit version number) */ @@ -95,12 +95,15 @@ #define SCG_CSR_DIVSLOW_SHIFT (0) /* Bits 0-3: Slow Clock Divide Ratio */ #define SCG_CSR_DIVSLOW_MASK (15 << SCG_CSR_DIVSLOW_SHIFT) # define SCG_CSR_DIVSLOW(n) ((uint32_t)((n) - 1) << SCG_CSR_DIVSLOW_SHIFT) /* n=1-8 */ + #define SCG_CSR_DIVBUS_SHIFT (4) /* Bits 4-7: Bus Clock Divide Ratio */ #define SCG_CSR_DIVBUS_MASK (15 << SCG_CSR_DIVBUS_SHIFT) # define SCG_CSR_DIVBUS(n) ((uint32_t)((n) - 1) << SCG_CSR_DIVBUS_SHIFT) /* n=1-16 */ + #define SCG_CSR_DIVCORE_SHIFT (16) /* Bits 16-19: Core Clock Divide Ratio */ #define SCG_CSR_DIVCORE_MASK (15 << SCG_CSR_DIVCORE_SHIFT) # define SCG_CSR_DIVCORE(n) ((uint32_t)((n) - 1) << SCG_CSR_DIVCORE_SHIFT) /* n=1-16 */ + #define SCG_CSR_SCS_SHIFT (24) /* Bits 24-27: System clock source */ #define SCG_CSR_SCS_MASK (15 << SCG_CSR_SCS_SHIFT) # define SCG_CSR_SCS_SOSC (1 << SCG_CSR_SCS_SHIFT) /* System OSC (SOSC_CLK) */ @@ -113,12 +116,15 @@ #define SCG_RCCR_DIVSLOW_SHIFT (0) /* Bits 0-3: Slow Clock Divide Ratio */ #define SCG_RCCR_DIVSLOW_MASK (15 << SCG_RCCR_DIVSLOW_SHIFT) # define SCG_RCCR_DIVSLOW(n) ((uint32_t)((n) - 1) << SCG_RCCR_DIVSLOW_SHIFT) /* n=1-8 */ + #define SCG_RCCR_DIVBUS_SHIFT (4) /* Bits 4-7: Bus Clock Divide Ratio */ #define SCG_RCCR_DIVBUS_MASK (15 << SCG_RCCR_DIVBUS_SHIFT) # define SCG_RCCR_DIVBUS(n) ((uint32_t)((n) - 1) << SCG_RCCR_DIVBUS_SHIFT) /* n=1-16 */ + #define SCG_RCCR_DIVCORE_SHIFT (16) /* Bits 16-19: Core Clock Divide Ratio */ #define SCG_RCCR_DIVCORE_MASK (15 << SCG_RCCR_DIVCORE_SHIFT) # define SCG_RCCR_DIVCORE(n) ((uint32_t)((n) - 1) << SCG_RCCR_DIVCORE_SHIFT) /* n=1-16 */ + #define SCG_RCCR_SCS_SHIFT (24) /* Bits 24-27: System clock source */ #define SCG_RCCR_SCS_MASK (15 << SCG_RCCR_SCS_SHIFT) # define SCG_RCCR_SCS_SOSC (1 << SCG_RCCR_SCS_SHIFT) /* System OSC (SOSC_CLK) */ @@ -131,12 +137,15 @@ #define SCG_VCCR_DIVSLOW_SHIFT (0) /* Bits 0-3: Slow Clock Divide Ratio */ #define SCG_VCCR_DIVSLOW_MASK (15 << SCG_VCCR_DIVSLOW_SHIFT) # define SCG_VCCR_DIVSLOW(n) ((uint32_t)((n) - 1) << SCG_VCCR_DIVSLOW_SHIFT) /* n=1-8 */ + #define SCG_VCCR_DIVBUS_SHIFT (4) /* Bits 4-7: Bus Clock Divide Ratio */ #define SCG_VCCR_DIVBUS_MASK (15 << SCG_VCCR_DIVBUS_SHIFT) # define SCG_VCCR_DIVBUS(n) ((uint32_t)((n) - 1) << SCG_VCCR_DIVBUS_SHIFT) /* n=1-16 */ + #define SCG_VCCR_DIVCORE_SHIFT (16) /* Bits 16-19: Core Clock Divide Ratio */ #define SCG_VCCR_DIVCORE_MASK (15 << SCG_VCCR_DIVCORE_SHIFT) # define SCG_VCCR_DIVCORE(n) ((uint32_t)((n) - 1) << SCG_VCCR_DIVCORE_SHIFT) /* n=1-16 */ + #define SCG_VCCR_SCS_SHIFT (24) /* Bits 24-27: System clock source */ #define SCG_VCCR_SCS_MASK (15 << SCG_VCCR_SCS_SHIFT) # define SCG_VCCR_SCS_SIRC (2 << SCG_VCCR_SCS_SHIFT) /* Slow IRC (SIRC_CLK) */ @@ -146,12 +155,15 @@ #define SCG_HCCR_DIVSLOW_SHIFT (0) /* Bits 0-3: Slow Clock Divide Ratio */ #define SCG_HCCR_DIVSLOW_MASK (15 << SCG_HCCR_DIVSLOW_SHIFT) # define SCG_HCCR_DIVSLOW(n) ((uint32_t)((n) - 1) << SCG_HCCR_DIVSLOW_SHIFT) /* n=1-8 */ + #define SCG_HCCR_DIVBUS_SHIFT (4) /* Bits 4-7: Bus Clock Divide Ratio */ #define SCG_HCCR_DIVBUS_MASK (15 << SCG_HCCR_DIVBUS_SHIFT) # define SCG_HCCR_DIVBUS(n) ((uint32_t)((n) - 1) << SCG_HCCR_DIVBUS_SHIFT) /* n=1-16 */ + #define SCG_HCCR_DIVCORE_SHIFT (16) /* Bits 16-19: Core Clock Divide Ratio */ #define SCG_HCCR_DIVCORE_MASK (15 << SCG_HCCR_DIVCORE_SHIFT) # define SCG_HCCR_DIVCORE(n) ((uint32_t)((n) - 1) << SCG_HCCR_DIVCORE_SHIFT) /* n=1-16 */ + #define SCG_HCCR_SCS_SHIFT (24) /* Bits 24-27: System clock source */ #define SCG_HCCR_SCS_MASK (15 << SCG_HCCR_SCS_SHIFT) # define SCG_HCCR_SCS_FIRC (3 << SCG_HCCR_SCS_SHIFT) /* Fast IRC (FIRC_CLK) */ @@ -190,6 +202,7 @@ # define SCG_SOSCDIV_SOSCDIV1_DIV16 (5 << SCG_SOSCDIV_SOSCDIV1_SHIFT) /* Divide by 16 */ # define SCG_SOSCDIV_SOSCDIV1_DIV32 (6 << SCG_SOSCDIV_SOSCDIV1_SHIFT) /* Divide by 32 */ # define SCG_SOSCDIV_SOSCDIV1_DIV64 (7 << SCG_SOSCDIV_SOSCDIV1_SHIFT) /* Divide by 64 */ + #define SCG_SOSCDIV_SOSCDIV2_SHIFT (8) /* Bits 8-10: System OSC Clock Divide 2 */ #define SCG_SOSCDIV_SOSCDIV2_MASK (7 << SCG_SOSCDIV_SOSCDIV2_SHIFT) # define SCG_SOSCDIV_SOSCDIV2(n) ((uint32_t)(n) << SCG_SOSCDIV_SOSCDIV2_SHIFT) @@ -235,6 +248,7 @@ # define SCG_SIRCDIV_SIRCDIV1_DIV16 (5 << SCG_SIRCDIV_SIRCDIV1_SHIFT) /* Divide by 16 */ # define SCG_SIRCDIV_SIRCDIV1_DIV32 (6 << SCG_SIRCDIV_SIRCDIV1_SHIFT) /* Divide by 32 */ # define SCG_SIRCDIV_SIRCDIV1_DIV64 (7 << SCG_SIRCDIV_SIRCDIV1_SHIFT) /* Divide by 64 */ + #define SCG_SIRCDIV_SIRCDIV2_SHIFT (8) /* Bits 8-10: Slow IRC Clock Divide 2 */ #define SCG_SIRCDIV_SIRCDIV2_MASK (7 << SCG_SIRCDIV_SIRCDIV2_SHIFT) # define SCG_SIRCDIV_SIRCDIV2(n) ((uint32_t)(n) << SCG_SIRCDIV_SIRCDIV2_SHIFT) @@ -275,6 +289,7 @@ # define SCG_FIRCDIV_FIRCDIV1_DIV16 (5 << SCG_FIRCDIV_FIRCDIV1_SHIFT) /* Divide by 16 */ # define SCG_FIRCDIV_FIRCDIV1_DIV32 (6 << SCG_FIRCDIV_FIRCDIV1_SHIFT) /* Divide by 32 */ # define SCG_FIRCDIV_FIRCDIV1_DIV64 (7 << SCG_FIRCDIV_FIRCDIV1_SHIFT) /* Divide by 64 */ + #define SCG_FIRCDIV_FIRCDIV2_SHIFT (8) /* Bits 8-10: Fast IRC Clock Divide 2 */ #define SCG_FIRCDIV_FIRCDIV2_MASK (7 << SCG_FIRCDIV_FIRCDIV2_SHIFT) # define SCG_FIRCDIV_FIRCDIV2(n) ((uint32_t)(n) << SCG_FIRCDIV_FIRCDIV2_SHIFT) @@ -315,6 +330,7 @@ # define SCG_SPLLDIV_SPLLDIV1_DIV16 (5 << SCG_SPLLDIV_SPLLDIV1_SHIFT) /* Divide by 16 */ # define SCG_SPLLDIV_SPLLDIV1_DIV32 (6 << SCG_SPLLDIV_SPLLDIV1_SHIFT) /* Divide by 32 */ # define SCG_SPLLDIV_SPLLDIV1_DIV64 (7 << SCG_SPLLDIV_SPLLDIV1_SHIFT) /* Divide by 64 */ + #define SCG_SPLLDIV_SPLLDIV2_SHIFT (8) /* Bits 8-10: System PLL Clock Divide 2 */ #define SCG_SPLLDIV_SPLLDIV2_MASK (7 << SCG_SPLLDIV_SPLLDIV2_SHIFT) # define SCG_SPLLDIV_SPLLDIV2(n) ((uint32_t)(n) << SCG_SPLLDIV_SPLLDIV2_SHIFT) @@ -332,6 +348,7 @@ #define SCG_SPLLCFG_PREDIV_SHIFT (8) /* Bits 8-10: PLL Reference Clock Divider */ #define SCG_SPLLCFG_PREDIV_MASK (7 << SCG_SPLLCFG_PREDIV_SHIFT) # define SCG_SPLLCFG_PREDIV(n) ((uint32_t)((n) - 1) << SCG_SPLLCFG_PREDIV_SHIFT) /* n=1..8 */ + #define SCG_SPLLCFG_MULT_SHIFT (16) /* Bits 16-20: System PLL Multiplier */ #define SCG_SPLLCFG_MULT_MASK (31 << SCG_SPLLCFG_MULT_SHIFT) # define SCG_SPLLCFG_MULT(n) ((uint32_t)((n) - 16) << SCG_SPLLCFG_MULT_SHIFT) /* n=16..47 */ diff --git a/arch/arm/src/s32k1xx/hardware/s32k1xx_sim.h b/arch/arm/src/s32k1xx/hardware/s32k1xx_sim.h index ef16763eccf..ff4e67b5a22 100644 --- a/arch/arm/src/s32k1xx/hardware/s32k1xx_sim.h +++ b/arch/arm/src/s32k1xx/hardware/s32k1xx_sim.h @@ -1,4 +1,4 @@ -/**************************************************************************************************** +/**************************************************************************** * arch/arm/src/s32k1xx/hardware/s32k1xx_sim.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,23 +16,23 @@ * License for the specific language governing permissions and limitations * under the License. * - ****************************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_S32K1XX_HARDWARE_S32K1XX_SIM_H #define __ARCH_ARM_SRC_S32K1XX_HARDWARE_S32K1XX_SIM_H -/**************************************************************************************************** +/**************************************************************************** * Included Files - ****************************************************************************************************/ + ****************************************************************************/ #include #include -/**************************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ****************************************************************************************************/ + ****************************************************************************/ -/* SIM Register Offsets *****************************************************************************/ +/* SIM Register Offsets *****************************************************/ #define S32K1XX_SIM_CHIPCTL_OFFSET 0x0004 /* Chip Control register */ #define S32K1XX_SIM_FTMOPT0_OFFSET 0x000c /* FTM Option Register 0 */ @@ -50,7 +50,7 @@ #define S32K1XX_SIM_CLKDIV4_OFFSET 0x0068 /* System Clock Divider Register 4 */ #define S32K1XX_SIM_MISCTRL1_OFFSET 0x006c /* Miscellaneous Control register 1 */ -/* SIM Register Addresses ***************************************************************************/ +/* SIM Register Addresses ***************************************************/ #define S32K1XX_SIM_CHIPCTL (S32K1XX_SIM_BASE + S32K1XX_SIM_CHIPCTL_OFFSET) #define S32K1XX_SIM_FTMOPT0 (S32K1XX_SIM_BASE + S32K1XX_SIM_FTMOPT0_OFFSET) @@ -68,7 +68,7 @@ #define S32K1XX_SIM_CLKDIV4 (S32K1XX_SIM_BASE + S32K1XX_SIM_CLKDIV4_OFFSET) #define S32K1XX_SIM_MISCTRL1 (S32K1XX_SIM_BASE + S32K1XX_SIM_MISCTRL1_OFFSET) -/* SIM Register Bitfield Definitions ****************************************************************/ +/* SIM Register Bitfield Definitions ****************************************/ /* Chip Control register */ @@ -95,9 +95,11 @@ # define SIM_CHIPCTL_CLKOUTSEL_QSPI_SFIF_CLK (13 << SIM_CHIPCTL_CLKOUTSEL_SHIFT) /* (S32K148) */ # define SIM_CHIPCTL_CLKOUTSEL_RTC_CLK (14 << SIM_CHIPCTL_CLKOUTSEL_SHIFT) # define SIM_CHIPCTL_CLKOUTSEL_QSPI_2xSFIF_CLK (15 << SIM_CHIPCTL_CLKOUTSEL_SHIFT) /* S32K148) */ + #define SIM_CHIPCTL_CLKOUTDIV_SHIFT (8) /* Bits 8-10: CLKOUT Divide Ratio */ #define SIM_CHIPCTL_CLKOUTDIV_MASK (7 << SIM_CHIPCTL_CLKOUTDIV_SHIFT) # define SIM_CHIPCTL_CLKOUTDIV(n) ((uint32_t)((n) - 1) << SIM_CHIPCTL_CLKOUTDIV_SHIFT) /* n=1..8 */ + #define SIM_CHIPCTL_CLKOUTEN (1 << 11) /* Bit 11: CLKOUT enable */ #define SIM_CHIPCTL_TRACECLK_SEL (1 << 12) /* Bit 12: Debug trace clock select */ #define SIM_CHIPCTL_PDB_BB_SEL (1 << 13) /* Bit 13: PDB back-to-back select */ @@ -109,6 +111,7 @@ # define SIM_CHIPCTL_ADC_SUPPLY_VDD_3V (3 << SIM_CHIPCTL_ADC_SUPPLY_SHIFT) /* 3.3V Oscillator Regulator Output */ # define SIM_CHIPCTL_ADC_SUPPLY_VDD_FLASH_3V (4 << SIM_CHIPCTL_ADC_SUPPLY_SHIFT) /* 3.3V flash regulator output */ # define SIM_CHIPCTL_ADC_SUPPLY_VDD_LV (5 << SIM_CHIPCTL_ADC_SUPPLY_SHIFT) /* 1.2V core regulator output */ + #define SIM_CHIPCTL_ADC_SUPPLYEN (1 << 19) /* Bit 19: Enable supply montorign ADC0 channel 0 */ #define SIM_CHIPCTL_SRAMU_RETEN (1 << 20) /* Bit 20: SRAMU retention */ #define SIM_CHIPCTL_SRAML_RETEN (1 << 21) /* Bit 21: SRAML retention */ @@ -119,14 +122,17 @@ #define SIM_FTMOPT0_FTM0FLTxSEL_MASK (7 << SIM_FTMOPT0_FTM0FLTxSEL_SHIFT) # define SIM_FTMOPT0_FTM0FLTxSEL_FTM0_FLTx (0 << SIM_FTMOPT0_FTM0FLTxSEL_SHIFT) /* FTM0_FLTx pin */ # define SIM_FTMOPT0_FTM0FLTxSEL_TRGMUX_FTM0 (1 << SIM_FTMOPT0_FTM0FLTxSEL_SHIFT) /* TRGMUX_FTM0 out */ + #define SIM_FTMOPT0_FTM1FLTxSEL_SHIFT (4) /* Bits 4-6: FTM1 Fault X Select */ #define SIM_FTMOPT0_FTM1FLTxSEL_MASK (7 << SIM_FTMOPT0_FTM1FLTxSEL_SHIFT) # define SIM_FTMOPT0_FTM1FLTxSEL_FTM1_FLTx (0 << SIM_FTMOPT0_FTM1FLTxSEL_SHIFT) /* FTM1_FLTx pin */ # define SIM_FTMOPT0_FTM1FLTxSEL_TRGMUX_FTM1 (1 << SIM_FTMOPT0_FTM1FLTxSEL_SHIFT) /* TRGMUX_FTM1 out */ + #define SIM_FTMOPT0_FTM2FLTxSEL_SHIFT (8) /* Bits 8-10: FTM2 Fault X Select */ #define SIM_FTMOPT0_FTM2FLTxSEL_MASK (7 << SIM_FTMOPT0_FTM2FLTxSEL_SHIFT) # define SIM_FTMOPT0_FTM2FLTxSEL_FTM2_FLTx (0 << SIM_FTMOPT0_FTM2FLTxSEL_SHIFT) /* FTM2_FLTx pin */ # define SIM_FTMOPT0_FTM2FLTxSEL_TRGMUX_FTM2 (1 << SIM_FTMOPT0_FTM2FLTxSEL_SHIFT) /* TRGMUX_FTM2 out */ + #define SIM_FTMOPT0_FTM3FLTxSEL_SHIFT (0) /* Bits 0-2: FTM3 Fault X Select */ #define SIM_FTMOPT0_FTM3FLTxSEL_MASK (7 << SIM_FTMOPT0_FTM3FLTxSEL_SHIFT) # define SIM_FTMOPT0_FTM3FLTxSEL_FTM3_FLTx (0 << SIM_FTMOPT0_FTM3FLTxSEL_SHIFT) /* FTM3_FLTx pin */ @@ -172,6 +178,7 @@ # define SIM_LPOCLKS_LPOCLKSEL_NO_CLOCK (1 << SIM_LPOCLKS_LPOCLKSEL_SHIFT) /* No clock */ # define SIM_LPOCLKS_LPOCLKSEL_32KHz_LPO_CLK (2 << SIM_LPOCLKS_LPOCLKSEL_SHIFT) /* 32kHz LPO_CLK derived from 128 kHz LPO_CLK */ # define SIM_LPOCLKS_LPOCLKSEL_1KHz_LPO_CLK (3 << SIM_LPOCLKS_LPOCLKSEL_SHIFT) /* 1kHz LPO_CLK derived from 128 kHz LPO_CLK */ + #define SIM_LPOCLKS_RTCCLKSEL_SHIFT (4) /* Bits 4-5: 32kHz clock source select */ #define SIM_LPOCLKS_RTCCLKSEL_MASK (3 << SIM_LPOCLKS_RTCCLKSEL_SHIFT) # define SIM_LPOCLKS_RTCCLKSEL(n) ((uint32_t)(n) << SIM_LPOCLKS_RTCCLKSEL_SHIFT) @@ -192,11 +199,13 @@ # define SIM_ADCOPT_ADC0SWPRETRG_SWPRETRG1 (5 << SIM_ADCOPT_ADC0SWPRETRG_SHIFT) /* Software pretrigger 1 */ # define SIM_ADCOPT_ADC0SWPRETRG_SWPRETRG2 (6 << SIM_ADCOPT_ADC0SWPRETRG_SHIFT) /* Software pretrigger 2 */ # define SIM_ADCOPT_ADC0SWPRETRG_SWPRETRG3 (7 << SIM_ADCOPT_ADC0SWPRETRG_SHIFT) /* Software pretrigger 3 */ + #define SIM_ADCOPT_ADC0PRETRGSEL_SHIFT (4) /* Bits 4-5: ADC0 pretrigger source select */ #define SIM_ADCOPT_ADC0PRETRGSEL_MASK (3 << SIM_ADCOPT_ADC0PRETRGSEL_SHIFT) # define SIM_ADCOPT_ADC0PRETRGSEL_PDB (0 << SIM_ADCOPT_ADC0PRETRGSEL_SHIFT) /* PDB pretrigger */ # define SIM_ADCOPT_ADC0PRETRGSEL_TRGMUX (1 << SIM_ADCOPT_ADC0PRETRGSEL_SHIFT) /* TRGMUX pretrigger */ # define SIM_ADCOPT_ADC0PRETRGSEL_SW (2 << SIM_ADCOPT_ADC0PRETRGSEL_SHIFT) /* Software pretrigger */ + #define SIM_ADCOPT_ADC1TRGSEL (1 << 8) /* Bit 8: ADC1 trigger source select */ # define SIM_ADCOPT_ADC1TRGSEL_PDB (0) /* PDB output */ # define SIM_ADCOPT_ADC1TRGSEL_TRGMUX (1 << 8) /* TRGMUX output */ @@ -207,6 +216,7 @@ # define SIM_ADCOPT_ADC1SWPRETRG_SWPRETRG1 (5 << SIM_ADCOPT_ADC1SWPRETRG_SHIFT) /* Software pretrigger 1 */ # define SIM_ADCOPT_ADC1SWPRETRG_SWPRETRG2 (6 << SIM_ADCOPT_ADC1SWPRETRG_SHIFT) /* Software pretrigger 2 */ # define SIM_ADCOPT_ADC1SWPRETRG_SWPRETRG3 (7 << SIM_ADCOPT_ADC1SWPRETRG_SHIFT) /* Software pretrigger 3 */ + #define SIM_ADCOPT_ADC1PRETRGSEL_SHIFT (12) /* Bits 12-13: ADC1 pretrigger source select */ #define SIM_ADCOPT_ADC1PRETRGSEL_MASK (3 << SIM_ADCOPT_ADC1PRETRGSEL_SHIFT) # define SIM_ADCOPT_ADC1PRETRGSEL_PDB (0 << SIM_ADCOPT_ADC1PRETRGSEL_SHIFT) /* PDB pretrigger */ @@ -223,10 +233,12 @@ #define SIM_FTMOPT1_FTM1CH0SEL_MASK (3 << SIM_FTMOPT1_FTM1CH0SEL_SHIFT) # define SIM_FTMOPT1_FTM1CH0SEL_FTM1_CH0 (0 << SIM_FTMOPT1_FTM1CH0SEL_SHIFT) /* FTM1_CH0 input */ # define SIM_FTMOPT1_FTM1CH0SEL_CMP0 (1 << SIM_FTMOPT1_FTM1CH0SEL_SHIFT) /* CMP0 output */ + #define SIM_FTMOPT1_FTM2CH0SEL_SHIFT (6) /* Bits 6-7: FTM2 CH0 Select */ #define SIM_FTMOPT1_FTM2CH0SEL_MASK (3 << SIM_FTMOPT1_FTM2CH0SEL_SHIFT) # define SIM_FTMOPT1_FTM1CH0SEL_FTM2_CH0 (0 << SIM_FTMOPT1_FTM1CH0SEL_SHIFT) /* FTM2_CH0 input */ # define SIM_FTMOPT1_FTM1CH0SEL_CMP0 (1 << SIM_FTMOPT1_FTM1CH0SEL_SHIFT) /* CMP0 output */ + #define SIM_FTMOPT1_FTM2CH1SEL (1 << 8) /* Bit 8: FTM2 CH1 Select */ #define SIM_FTMOPT1_FTM4SYNCBIT (1 << 11) /* Bit 11: FTM4 Sync Bit */ #define SIM_FTMOPT1_FTM5SYNCBIT (1 << 12) /* Bit 12: FTM5 Sync Bit */ @@ -243,6 +255,7 @@ # define SIM_FTMOPT1_FTM0_OUTSEL_CHAN5 (32 << SIM_FTMOPT1_FTM0_OUTSEL_SHIFT) /* Modulation with FTM1_CH5 */ # define SIM_FTMOPT1_FTM0_OUTSEL_CHAN6 (64 << SIM_FTMOPT1_FTM0_OUTSEL_SHIFT) /* Modulation with FTM1_CH6 */ # define SIM_FTMOPT1_FTM0_OUTSEL_CHAN7 (128 << SIM_FTMOPT1_FTM0_OUTSEL_SHIFT) /* Modulation with FTM1_CH7 */ + #define SIM_FTMOPT1_FTM3_OUTSEL_SHIFT (16) /* Bits 16-23: FTM3 channel modulation select with FTM2_CH1 */ #define SIM_FTMOPT1_FTM3_OUTSEL_MASK (0xff << SIM_FTMOPT1_FTM3_OUTSEL_SHIFT) # define SIM_FTMOPT1_FTM3_OUTSEL_CHAN0 (1 << SIM_FTMOPT1_FTM3_OUTSEL_SHIFT) /* Modulation with FTM2_CH0 */ @@ -282,7 +295,7 @@ # define SIM_SDID_FEATURES_FLEXIO (1 << 5) /* Bit 5: FlexIO */ # define SIM_SDID_FEATURES_ISO_CANFD (1 << 6) /* Bit 6: ISO CAN-FD */ # define SIM_SDID_FEATURES_SECURITY (1 << 7) /* Bit 7: Security */ -#define SIM_SDID_PACKAGE_SHIFT (8) /* Bits 8-11: Package */ +#define SIM_SDID_PACKAGE_SHIFT (8) /* Bits 8-11: Package */ #define SIM_SDID_PACKAGE_MASK (15 << SIM_SDID_PACKAGE_SHIFT) # define SIM_SDID_PACKAGE_32QFN (1 << SIM_SDID_PACKAGE_SHIFT) /* 32 QFN */ # define SIM_SDID_PACKAGE_48LQFP (2 << SIM_SDID_PACKAGE_SHIFT) /* 48 LQFP */ @@ -291,6 +304,7 @@ # define SIM_SDID_PACKAGE_144LQFP (6 << SIM_SDID_PACKAGE_SHIFT) /* 144 LQFP */ # define SIM_SDID_PACKAGE_176LQFP (7 << SIM_SDID_PACKAGE_SHIFT) /* 176 LQFP */ # define SIM_SDID_PACKAGE_100MAPBGA (8 << SIM_SDID_PACKAGE_SHIFT) /* 100 MAP BGA */ + #define SIM_SDID_REVID_SHIFT (12) /* Bits 12-15: Device revision number */ #define SIM_SDID_REVID_MASK (15 << SIM_SDID_REVID_SHIFT) #define SIM_SDID_RAMSIZE_SHIFT (16) /* Bits 16-19: RAM size */ @@ -305,6 +319,7 @@ # define SIM_SDID_RAMSIZE_192KB (11 << SIM_SDID_RAMSIZE_SHIFT) /* S32K148 */ # define SIM_SDID_RAMSIZE_256KB (15 << SIM_SDID_RAMSIZE_SHIFT) /* S32K148 */ # define SIM_SDID_RAMSIZE_256KB (15 << SIM_SDID_RAMSIZE_SHIFT) /* S32K148 */ + #define SIM_SDID_DERIVATE_SHIFT (20) /* Bits 20-23: Derivate */ #define SIM_SDID_DERIVATE_MASK (15 << SIM_SDID_DERIVATE_SHIFT) #define SIM_SDID_SUBSERIES_SHIFT (24) /* Bits 24-27: Subseries */ @@ -337,10 +352,12 @@ # define SIM_FCFG1_EEERAMSIZE_32B (9 << SIM_FCFG1_EEERAMSIZE_SHIFT) /* 32 Bytes */ # define SIM_FCFG1_EEERAMSIZE_0B (15 << SIM_FCFG1_EEERAMSIZE_SHIFT) /* 0 Bytes */ - /* Unique Identification Register High (32-bit UIDH[96-127]) */ + /* Unique Identification Register Mid-High (32-bit UIDH[64-95]) */ + /* Unique Identification Register Mid Low (32-bit UIDH[32-63]) */ + /* Unique Identification Register Low (32-bit UIDH[0-31]) */ /* System Clock Divider Register 4 */ @@ -349,6 +366,7 @@ #define SIM_CLKDIV4_TRACEDIV_SHIFT (1) /* Bits 1-3: Trace Clock Divider value */ #define SIM_CLKDIV4_TRACEDIV_MASK (7 << SIM_CLKDIV4_TRACEDIV_SHIFT) # define SIM_CLKDIV4_TRACEDIV(n) ((uint32_t)((n) - 1) << SIM_CLKDIV4_TRACEDIV_SHIFT) /* n=1..8 */ + #define SIM_CLKDIV4_TRACEDIVEN (1 << 28) /* Bit 28: Debug Trace Divider control */ /* Miscellaneous Control register 1 */ diff --git a/arch/arm/src/s32k1xx/hardware/s32k1xx_smc.h b/arch/arm/src/s32k1xx/hardware/s32k1xx_smc.h index 6359d196115..5da2137a15c 100644 --- a/arch/arm/src/s32k1xx/hardware/s32k1xx_smc.h +++ b/arch/arm/src/s32k1xx/hardware/s32k1xx_smc.h @@ -1,4 +1,4 @@ -/******************************************************************************************** +/**************************************************************************** * arch/arm/src/s32k1xx/hardware/s32k1xx_smc.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,23 +16,23 @@ * License for the specific language governing permissions and limitations * under the License. * - ********************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_S32K1XX_HARDWARE_S32K1XX_SMC_H #define __ARCH_ARM_SRC_S32K1XX_HARDWARE_S32K1XX_SMC_H -/******************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************/ + ****************************************************************************/ #include #include -/******************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************/ + ****************************************************************************/ -/* SMC Register Offsets *********************************************************************/ +/* SMC Register Offsets *****************************************************/ #define S32K1XX_SMC_VERID_OFFSET 0x0000 /* SMC Version ID Register */ #define S32K1XX_SMC_PARAM_OFFSET 0x0004 /* SMC Parameter Register */ @@ -41,7 +41,7 @@ #define S32K1XX_SMC_STOPCTRL_OFFSET 0x0010 /* SMC Stop Control Register */ #define S32K1XX_SMC_PMSTAT_OFFSET 0x0014 /* SMC Power Mode Status register */ -/* SMC Register Addresses *******************************************************************/ +/* SMC Register Addresses ***************************************************/ #define S32K1XX_SMC_VERID (S32K1XX_SMC_BASE + S32K1XX_SMC_VERID_OFFSET) #define S32K1XX_SMC_PARAM (S32K1XX_SMC_BASE + S32K1XX_SMC_PARAM_OFFSET) @@ -50,19 +50,19 @@ #define S32K1XX_SMC_STOPCTRL (S32K1XX_SMC_BASE + S32K1XX_SMC_STOPCTRL_OFFSET) #define S32K1XX_SMC_PMSTAT (S32K1XX_SMC_BASE + S32K1XX_SMC_PMSTAT_OFFSET) -/* SMC Register Bitfield Definitions ********************************************************/ +/* SMC Register Bitfield Definitions ****************************************/ /* SMC Version ID Register */ #define SMC_VERID_FEATURE_SHIFT (0) /* Bits 0-15: Feature Identification Number */ #define SMC_VERID_FEATURE_MASK (0xffff << SMC_VERID_FEATURE_SHIFT) # define SMC_VERID_FEATURE_STD (1 << SMC_VERID_FEATURE_SHIFT) /* Standard feature set */ + #define SMC_VERID_MINOR_SHIFT (16) /* Bits 16-23: Minor Version Number */ #define SMC_VERID_MINOR_MASK (0xff << SMC_VERID_MINOR_SHIFT) #define SMC_VERID_MAJOR_SHIFT (24) /* Bits 24-31: Major Version Number */ #define SMC_VERID_MAJOR_MASK (0xff << SMC_VERID_MAJOR_SHIFT) - /* SMC Parameter Register */ #define SMC_PARAM_EHSRUN (1 << 0) /* Bit 0: Existence of HSRUN feature */ @@ -81,6 +81,7 @@ #define SMC_PMCTRL_STOPM_MASK (7 << SMC_PMCTRL_STOPM_SHIFT) # define SMC_PMCTRL_STOPM_STOP (0 << SMC_PMCTRL_STOPM_SHIFT) /* Normal Stop */ # define SMC_PMCTRL_STOPM_VLPS (2 << SMC_PMCTRL_STOPM_SHIFT) /* Very-Low-Power Stop */ + #define SMC_PMCTRL_VLPSA (1 << 3) /* Bit 3: Very Low Power Stop Aborted */ #define SMC_PMCTRL_RUNM_SHIFT (5) /* Bits 5-6: Run Mode Control */ #define SMC_PMCTRL_RUNM_MASK (3 << SMC_PMCTRL_RUNM_SHIFT) diff --git a/arch/arm/src/s32k1xx/hardware/s32k1xx_wdog.h b/arch/arm/src/s32k1xx/hardware/s32k1xx_wdog.h index 3a02e892330..16aa0d9449b 100644 --- a/arch/arm/src/s32k1xx/hardware/s32k1xx_wdog.h +++ b/arch/arm/src/s32k1xx/hardware/s32k1xx_wdog.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/s32k1xx/hardware/s32k1xx_wdog.h * * Copyright (C) 2019 Gregory Nutt. All rights reserved. @@ -50,37 +50,37 @@ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF * THE POSSIBILITY OF SUCH DAMAGE. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_S32K1XX_HARDWARE_S32K1XX_WDOG_H #define __ARCH_ARM_SRC_S32K1XX_HARDWARE_S32K1XX_WDOG_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* WDOG Register Offsets ************************************************************/ +/* WDOG Register Offsets ****************************************************/ #define S32K1XX_WDOG_CS_OFFSET 0x0000 /* Watchdog Control and Status Register */ #define S32K1XX_WDOG_CNT_OFFSET 0x0004 /* Watchdog Counter Register */ #define S32K1XX_WDOG_TOVAL_OFFSET 0x0008 /* Watchdog Timeout Value Register */ #define S32K1XX_WDOG_WIN_OFFSET 0x000c /* Watchdog Window Register */ -/* WDOG Register Addresses **********************************************************/ +/* WDOG Register Addresses **************************************************/ #define S32K1XX_WDOG_CS (S32K1XX_WDOG_BASE + S32K1XX_WDOG_CS_OFFSET) #define S32K1XX_WDOG_CNT (S32K1XX_WDOG_BASE + S32K1XX_WDOG_CNT_OFFSET) #define S32K1XX_WDOG_TOVAL (S32K1XX_WDOG_BASE + S32K1XX_WDOG_TOVAL_OFFSET) #define S32K1XX_WDOG_WIN (S32K1XX_WDOG_BASE + S32K1XX_WDOG_WIN_OFFSET) -/* WDOG Register Bitfield Definitions ***********************************************/ +/* WDOG Register Bitfield Definitions ***************************************/ /* Watchdog Control and Status Register */ @@ -93,6 +93,7 @@ # define WDOG_CS_TST_USER (1 << WDOG_CS_TST_SHIFT) /* Watchdog user mode enabled */ # define WDOG_CS_TST_LOWBYTE (2 << WDOG_CS_TST_SHIFT) /* Watchdog low byte test mode */ # define WDOG_CS_TST_HIGHBYTE (3 << WDOG_CS_TST_SHIFT) /* Watchdog high byte test mode */ + #define WDOG_CS_UPDATE (1 << 5) /* Bit 5: Allow updates */ #define WDOG_CS_INT (1 << 6) /* Bit 6: Watchdog Interrupt */ #define WDOG_CS_EN (1 << 7) /* Bit 7: Watchdog Enable */ @@ -102,6 +103,7 @@ # define WDOG_CS_CLK_LPOCLK (1 << WDOG_CS_CLK_SHIFT) /* LPO clock */ # define WDOG_CS_CLK_INTCLK (2 << WDOG_CS_CLK_SHIFT) /* INTCLK (internal clock) */ # define WDOG_CS_CLK_ERCLK (3 << WDOG_CS_CLK_SHIFT) /* ERCLK (external reference clock) */ + #define WDOG_CS_RCS (1 << 10) /* Bit 10: Reconfiguration Success */ #define WDOG_CS_ULK (1 << 11) /* Bit 11: Unlock status */ #define WDOG_CS_PRES (1 << 12) /* Bit 12: Watchdog prescalr */ diff --git a/arch/arm/src/s32k1xx/s32k11x/s32k11x_clockmapping.c b/arch/arm/src/s32k1xx/s32k11x/s32k11x_clockmapping.c index 62083aa539a..24aedb4b2d0 100644 --- a/arch/arm/src/s32k1xx/s32k11x/s32k11x_clockmapping.c +++ b/arch/arm/src/s32k1xx/s32k11x/s32k11x_clockmapping.c @@ -111,3 +111,7 @@ const uint16_t g_clkname_mapping[] = PCC_INVALID_INDEX, /* End of ASYNCH DIV2 clocks 68 */ PCC_INVALID_INDEX, /* End of PCC clocks 69 */ }; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ diff --git a/arch/arm/src/s32k1xx/s32k11x/s32k11x_periphfeatures.c b/arch/arm/src/s32k1xx/s32k11x/s32k11x_periphfeatures.c index c4c66a8b086..ef29913f8b4 100644 --- a/arch/arm/src/s32k1xx/s32k11x/s32k11x_periphfeatures.c +++ b/arch/arm/src/s32k1xx/s32k11x/s32k11x_periphfeatures.c @@ -1,4 +1,4 @@ -/******************************************************************************************************************************************** +/**************************************************************************** * arch/arm/src/s32k1xx/s32k11x/s32k11x_periphfeatures.c * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,11 +16,11 @@ * License for the specific language governing permissions and limitations * under the License. * - ********************************************************************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************************************************************/ + ****************************************************************************/ #include @@ -28,7 +28,7 @@ /**************************************************************************** * Public Data - ********************************************************************************************************************************************/ + ****************************************************************************/ /* Peripheral Features. * @@ -110,3 +110,8 @@ const uint8_t g_periph_features[] = (NO_PERIPHERAL_FEATURE), /* End of ASYNCH DIV2 clocks 68 */ (NO_PERIPHERAL_FEATURE) /* End of PCC clocks 69 */ }; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + diff --git a/arch/arm/src/s32k1xx/s32k11x/s32k11x_timerisr.c b/arch/arm/src/s32k1xx/s32k11x/s32k11x_timerisr.c index 3cfb3cc9444..e0b96ad3b0d 100644 --- a/arch/arm/src/s32k1xx/s32k11x/s32k11x_timerisr.c +++ b/arch/arm/src/s32k1xx/s32k11x/s32k11x_timerisr.c @@ -136,7 +136,8 @@ void up_timer_initialize(void) /* Enable SysTick interrupts */ - putreg32((SYSTICK_CSR_TICKINT | SYSTICK_CSR_ENABLE |SYSTICK_CSR_CLKSOURCE), + putreg32((SYSTICK_CSR_TICKINT | SYSTICK_CSR_ENABLE | + SYSTICK_CSR_CLKSOURCE), ARMV6M_SYSTICK_CSR); /* And enable the timer interrupt */ diff --git a/arch/arm/src/s32k1xx/s32k14x/s32k14x_clockmapping.c b/arch/arm/src/s32k1xx/s32k14x/s32k14x_clockmapping.c index eb376a05f43..c5288b1818b 100644 --- a/arch/arm/src/s32k1xx/s32k14x/s32k14x_clockmapping.c +++ b/arch/arm/src/s32k1xx/s32k14x/s32k14x_clockmapping.c @@ -133,3 +133,7 @@ const uint16_t g_clkname_mapping[] = PCC_INVALID_INDEX, /* End of ASYNCH DIV2 clocks 90 */ PCC_INVALID_INDEX /* End of PCC clocks 91 */ }; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ diff --git a/arch/arm/src/s32k1xx/s32k14x/s32k14x_clrpend.c b/arch/arm/src/s32k1xx/s32k14x/s32k14x_clrpend.c index 7f1b9f4b6e5..512d745fd8e 100644 --- a/arch/arm/src/s32k1xx/s32k14x/s32k14x_clrpend.c +++ b/arch/arm/src/s32k1xx/s32k14x/s32k14x_clrpend.c @@ -39,12 +39,12 @@ * Name: s32k14x_clrpend * * Description: - * Clear a pending interrupt at the NVIC. This does not seem to be required - * for most interrupts. Don't know why... but the S32K14x Ethernet EMAC - * interrupt definitely needs it! + * Clear a pending interrupt at the NVIC. This does not seem to be + * required for most interrupts. Don't know why... + * but the S32K14x Ethernet EMAC interrupt definitely needs it! * - * This function is logically a part of s32k14x_irq.c, but I will keep it in - * a separate file so that it will not increase the footprint on S32K14x + * This function is logically a part of s32k14x_irq.c, but I will keep it + * in a separate file so that it will not increase the footprint on S32K14x * platforms that do not need this function. * ****************************************************************************/ diff --git a/arch/arm/src/s32k1xx/s32k14x/s32k14x_irq.h b/arch/arm/src/s32k1xx/s32k14x/s32k14x_irq.h index 8ef4bfaf07e..1beeff009db 100644 --- a/arch/arm/src/s32k1xx/s32k14x/s32k14x_irq.h +++ b/arch/arm/src/s32k1xx/s32k14x/s32k14x_irq.h @@ -28,7 +28,7 @@ #include /**************************************************************************** - * Public Functions + * Public Functions Prototypes ****************************************************************************/ /**************************************************************************** diff --git a/arch/arm/src/s32k1xx/s32k14x/s32k14x_periphfeatures.c b/arch/arm/src/s32k1xx/s32k14x/s32k14x_periphfeatures.c index 509a68b2a3a..08f6a3890a4 100644 --- a/arch/arm/src/s32k1xx/s32k14x/s32k14x_periphfeatures.c +++ b/arch/arm/src/s32k1xx/s32k14x/s32k14x_periphfeatures.c @@ -1,4 +1,4 @@ -/******************************************************************************************************************************************** +/**************************************************************************** * arch/arm/src/s32k1xx/s32k14x/s32k14x_periphfeatures.c * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,11 +16,11 @@ * License for the specific language governing permissions and limitations * under the License. * - ********************************************************************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************************************************************/ + ****************************************************************************/ #include @@ -28,7 +28,7 @@ /**************************************************************************** * Public Data - ********************************************************************************************************************************************/ + ****************************************************************************/ /* Peripheral Features. * @@ -132,3 +132,7 @@ const uint8_t g_periph_features[] = (NO_PERIPHERAL_FEATURE), /* End of ASYNCH DIV2 clocks 90 */ (NO_PERIPHERAL_FEATURE), /* End of PCC clocks 91 */ }; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ diff --git a/arch/arm/src/s32k1xx/s32k1xx_clockconfig.c b/arch/arm/src/s32k1xx/s32k1xx_clockconfig.c index 00c7108be8f..04e806ee25c 100644 --- a/arch/arm/src/s32k1xx/s32k1xx_clockconfig.c +++ b/arch/arm/src/s32k1xx/s32k1xx_clockconfig.c @@ -163,8 +163,10 @@ static const uint8_t g_tmp_sysclk[TMP_SYS_CLK_NO][TMP_SYS_DIV_NO] = /* The maximum clock frequencies of system clocks in all power modes */ +/* SYS_CLK BUS_CLK SLOW_CLK */ + static const uint32_t g_vlpr_maxsysclks[MODES_MAX_NO][SYS_CLK_MAX_NO] = -{/* SYS_CLK BUS_CLK SLOW_CLK */ +{ { 0ul, 0ul, 0ul }, /* Invalid entry */ { 4000000ul, 4000000ul, 1000000ul }, /* Maximum frequencies when system clock is SOSC */ { 4000000ul, 4000000ul, 1000000ul }, /* Maximum frequencies when system clock is SIRC */ @@ -174,8 +176,10 @@ static const uint32_t g_vlpr_maxsysclks[MODES_MAX_NO][SYS_CLK_MAX_NO] = { 4000000ul, 4000000ul, 1000000ul }, /* Maximum frequencies when system clock is SPLL */ }; +/* SYS_CLK BUS_CLK SLOW_CLK */ + static const uint32_t g_run_maxsysclks[MODES_MAX_NO][SYS_CLK_MAX_NO] = -{/* SYS_CLK BUS_CLK SLOW_CLK */ +{ { 0ul, 0ul, 0ul }, /* Invalid entry */ { 80000000ul, 48000000ul, 26670000ul }, /* Maximum frequencies when system clock is SOSC */ { 80000000ul, 48000000ul, 26670000ul }, /* Maximum frequencies when system clock is SIRC */ @@ -185,8 +189,11 @@ static const uint32_t g_run_maxsysclks[MODES_MAX_NO][SYS_CLK_MAX_NO] = { 80000000ul, 40000000ul, 26670000ul }, /* Maximum frequencies when system clock is SPLL */ }; #ifdef CONFIG_S32K1XX_HAVE_HSRUN + +/* SYS_CLK BUS_CLK SLOW_CLK */ + static const uint32_t g_hsrun_maxsysclks[MODES_MAX_NO][SYS_CLK_MAX_NO] = -{/* SYS_CLK BUS_CLK SLOW_CLK */ +{ { 0ul, 0ul, 0ul }, /* Invalid entry */ { 112000000ul, 56000000ul, 28000000ul }, /* Maximum frequencies when system clock is SOSC */ { 112000000ul, 56000000ul, 28000000ul }, /* Maximum frequencies when system clock is SIRC */ @@ -225,7 +232,8 @@ static uint32_t g_tclkfreq[NUMBER_OF_TCLK_INPUTS]; /* TCLKx clocks */ static inline uint32_t s32k1xx_get_scgclk_source(void) { - return ((getreg32(S32K1XX_SCG_CSR) & SCG_CSR_SCS_MASK) >> SCG_CSR_SCS_SHIFT); + return ((getreg32(S32K1XX_SCG_CSR) & SCG_CSR_SCS_MASK) >> + SCG_CSR_SCS_SHIFT); } /**************************************************************************** @@ -400,8 +408,10 @@ static uint32_t s32k1xx_get_spllfreq(void) if (freq != 0) { regval = getreg32(S32K1XX_SCG_SPLLCFG); - prediv = ((regval & SCG_SPLLCFG_PREDIV_MASK) >> SCG_SPLLCFG_PREDIV_SHIFT) + 1; - mult = ((regval & SCG_SPLLCFG_MULT_MASK) >> SCG_SPLLCFG_MULT_SHIFT) + 16; + prediv = ((regval & SCG_SPLLCFG_PREDIV_MASK) >> + SCG_SPLLCFG_PREDIV_SHIFT) + 1; + mult = ((regval & SCG_SPLLCFG_MULT_MASK) >> + SCG_SPLLCFG_MULT_SHIFT) + 16; freq /= prediv; freq *= mult; @@ -463,7 +473,7 @@ static uint32_t s32k1xx_get_srcfreq(enum scg_system_clock_src_e src) } /**************************************************************************** - * Name: s32k1xx_set_sysclk_configuration + * Name: s32k1xx_set_sysclk_cfg * * Description: * This function sets the system configuration for the specified mode. @@ -479,13 +489,15 @@ static uint32_t s32k1xx_get_srcfreq(enum scg_system_clock_src_e src) ****************************************************************************/ static int -s32k1xx_set_sysclk_configuration(enum scg_system_clock_mode_e mode, - const struct scg_system_clock_config_s *config) +s32k1xx_set_sysclk_cfg(enum scg_system_clock_mode_e mode, + const struct scg_system_clock_config_s *config) { uint32_t srcfreq = 0; uint32_t sysfreq_mul = (uint32_t)config->divcore; - uint32_t busfreq_mul = (uint32_t)config->divcore * (uint32_t)config->divbus; - uint32_t slowfreq_mul = (uint32_t)config->divcore * (uint32_t)config->divslow; + uint32_t busfreq_mul = (uint32_t)config->divcore * + (uint32_t)config->divbus; + uint32_t slowfreq_mul = (uint32_t)config->divcore * + (uint32_t)config->divslow; uint32_t regval; int ret = OK; @@ -496,16 +508,22 @@ s32k1xx_set_sysclk_configuration(enum scg_system_clock_mode_e mode, switch (mode) { case SCG_SYSTEM_CLOCK_MODE_RUN: /* Run mode */ + /* Verify the frequencies of sys, bus and slow clocks. */ - if ((srcfreq > - (sysfreq_mul * (g_run_maxsysclks[(uint32_t)config->src][CORE_CLK_INDEX] >> 4))) || - (srcfreq > - (busfreq_mul * (g_run_maxsysclks[(uint32_t)config->src][BUS_CLK_INDEX] >> 4))) || - (srcfreq > - (slowfreq_mul * (g_run_maxsysclks[(uint32_t)config->src][SLOW_CLK_INDEX] >> 4)))) + if ((srcfreq > (sysfreq_mul * + (g_run_maxsysclks[(uint32_t)config->src][CORE_CLK_INDEX] >> + 4))) || + (srcfreq > (busfreq_mul * + (g_run_maxsysclks[(uint32_t)config->src][BUS_CLK_INDEX] >> + 4))) || + (srcfreq > (slowfreq_mul * + (g_run_maxsysclks[(uint32_t)config->src][SLOW_CLK_INDEX] >> + 4)))) { - /* Configuration for the next system clock source is not valid. */ + /* Configuration for the next system clock source is not + * valid. + */ ret = -EINVAL; } @@ -524,14 +542,19 @@ s32k1xx_set_sysclk_configuration(enum scg_system_clock_mode_e mode, /* Verify the frequencies of sys, bus and slow clocks. */ - if ((srcfreq > - (sysfreq_mul * (g_vlpr_maxsysclks[(uint32_t)config->src][CORE_CLK_INDEX] >> 4))) || - (srcfreq > - (busfreq_mul * (g_vlpr_maxsysclks[(uint32_t)config->src][BUS_CLK_INDEX] >> 4))) || - (srcfreq > - (slowfreq_mul * (g_vlpr_maxsysclks[(uint32_t)config->src][SLOW_CLK_INDEX] >> 4)))) + if ((srcfreq > (sysfreq_mul * + (g_vlpr_maxsysclks[(uint32_t)config->src][CORE_CLK_INDEX] >> + 4))) || + (srcfreq > (busfreq_mul * + (g_vlpr_maxsysclks[(uint32_t)config->src][BUS_CLK_INDEX] >> + 4))) || + (srcfreq > (slowfreq_mul * + (g_vlpr_maxsysclks[(uint32_t)config->src][SLOW_CLK_INDEX] >> + 4)))) { - /* Configuration for the next system clock source is not valid. */ + /* Configuration for the next system clock source is not + * valid. + */ ret = -EINVAL; } @@ -552,14 +575,19 @@ s32k1xx_set_sysclk_configuration(enum scg_system_clock_mode_e mode, /* Verify the frequencies of sys, bus and slow clocks. */ - if ((srcfreq > - (sysfreq_mul * (g_hsrun_maxsysclks[(uint32_t)config->src][CORE_CLK_INDEX] >> 4))) || - (srcfreq > - (busfreq_mul * (g_hsrun_maxsysclks[(uint32_t)config->src][BUS_CLK_INDEX] >> 4))) || - (srcfreq > - (slowfreq_mul * (g_hsrun_maxsysclks[(uint32_t)config->src][SLOW_CLK_INDEX] >> 4)))) + if ((srcfreq > (sysfreq_mul * + (g_hsrun_maxsysclks[(uint32_t)config->src][CORE_CLK_INDEX] >> + 4))) || + (srcfreq > (busfreq_mul * + (g_hsrun_maxsysclks[(uint32_t)config->src][BUS_CLK_INDEX] >> + 4))) || + (srcfreq > (slowfreq_mul * + (g_hsrun_maxsysclks[(uint32_t)config->src][SLOW_CLK_INDEX] >> + 4)))) { - /* Configuration for the next system clock source is not valid. */ + /* Configuration for the next system clock source is not + * valid. + */ ret = -EINVAL; } @@ -618,7 +646,7 @@ s32k1xx_transition_systemclock(const struct scg_system_clock_config_s *cfg) /* Update run mode configuration */ - ret = s32k1xx_set_sysclk_configuration(run_mode, cfg); + ret = s32k1xx_set_sysclk_cfg(run_mode, cfg); if (ret == OK) { /* Wait for system clock to transition. @@ -1106,7 +1134,8 @@ static int s32k1xx_spll_config(bool enable, /* Pre-divider checking. */ srcfreq /= spllcfg->prediv; - DEBUGASSERT(srcfreq >= SCG_SPLL_REF_MIN && srcfreq <= SCG_SPLL_REF_MAX); + DEBUGASSERT(srcfreq >= SCG_SPLL_REF_MIN && + srcfreq <= SCG_SPLL_REF_MAX); /* Now start to set up PLL clock. */ @@ -1120,7 +1149,9 @@ static int s32k1xx_spll_config(bool enable, SCG_SPLLCFG_MULT(spllcfg->mult); putreg32(regval, S32K1XX_SCG_SPLLCFG); - /* Step 3. Enable clock, configure monitor, lock register. */ + /* Step 3. + * Enable clock, configure monitor, lock register. + */ regval = SCG_SPLLCSR_SPLLEN; @@ -1272,7 +1303,9 @@ static int s32k1xx_configure_scgmodules(const struct scg_config_s *scgcfg) } #endif - /* SOSC is enabled and SPLL configuration for system clock source is not valid */ + /* SOSC is enabled and SPLL configuration for system clock source + * is not valid + */ if (scgcfg->sosc.initialize && (ret == -ENOENT)) { @@ -1283,7 +1316,9 @@ static int s32k1xx_configure_scgmodules(const struct scg_config_s *scgcfg) ret = s32k1xx_transition_systemclock(&sysclkcfg); } - /* SIRC is enabled and SOSC configuration for system clock source is not valid */ + /* SIRC is enabled and SOSC configuration for system clock + * source is not valid + */ if (scgcfg->sirc.initialize && (ret == -ENOENT)) { @@ -1310,7 +1345,7 @@ static int s32k1xx_configure_scgmodules(const struct scg_config_s *scgcfg) sysclkcfg.divcore = next->divcore; sysclkcfg.divbus = next->divbus; sysclkcfg.divslow = next->divslow; - ret = s32k1xx_transition_systemclock(&sysclkcfg); + ret = s32k1xx_transition_systemclock(&sysclkcfg); } } } @@ -1400,19 +1435,19 @@ static int s32k1xx_scg_config(const struct scg_config_s *scgcfg) { /* Configure SCG clock modes */ - ret = s32k1xx_set_sysclk_configuration(SCG_SYSTEM_CLOCK_MODE_RUN, - &scgcfg->clockmode.rccr); + ret = s32k1xx_set_sysclk_cfg(SCG_SYSTEM_CLOCK_MODE_RUN, + &scgcfg->clockmode.rccr); if (ret == OK) { - ret = s32k1xx_set_sysclk_configuration(SCG_SYSTEM_CLOCK_MODE_VLPR, - &scgcfg->clockmode.vccr); + ret = s32k1xx_set_sysclk_cfg(SCG_SYSTEM_CLOCK_MODE_VLPR, + &scgcfg->clockmode.vccr); } #ifdef CONFIG_S32K1XX_HAVE_HSRUN if (ret == OK) { - ret = s32k1xx_set_sysclk_configuration(SCG_SYSTEM_CLOCK_MODE_HSRUN, - &scgcfg->clockmode.hccr); + ret = s32k1xx_set_sysclk_cfg(SCG_SYSTEM_CLOCK_MODE_HSRUN, + &scgcfg->clockmode.hccr); } #endif } @@ -1743,11 +1778,14 @@ uint32_t s32k1xx_get_coreclk(void) #ifdef CONFIG_S32K1XX_HAVE_SPLL case SCG_CSR_SPLL_FIRC: /* System PLL */ + /* Coreclock = Fxtal * mult / (2 * prediv) */ regval = getreg32(S32K1XX_SCG_SPLLCFG); - prediv = ((regval & SCG_SPLLCFG_PREDIV_MASK) >> SCG_SPLLCFG_PREDIV_SHIFT) + 1; - mult = ((regval & SCG_SPLLCFG_MULT_MASK) >> SCG_SPLLCFG_MULT_SHIFT) + 16; + prediv = ((regval & SCG_SPLLCFG_PREDIV_MASK) >> + SCG_SPLLCFG_PREDIV_SHIFT) + 1; + mult = ((regval & SCG_SPLLCFG_MULT_MASK) >> + SCG_SPLLCFG_MULT_SHIFT) + 16; coreclk = ((BOARD_XTAL_FREQUENCY / 2) * mult) / prediv; break; @@ -1802,12 +1840,14 @@ uint32_t s32k1xx_get_sysclk(enum scg_system_clock_type_e type) break; case SCG_SYSTEM_CLOCK_BUS: - divider = ((regval & SCG_CSR_DIVBUS_MASK) >> SCG_CSR_DIVBUS_SHIFT) + 1; + divider = ((regval & SCG_CSR_DIVBUS_MASK) >> + SCG_CSR_DIVBUS_SHIFT) + 1; freq /= divider; break; case SCG_SYSTEM_CLOCK_SLOW: - divider = ((regval & SCG_CSR_DIVSLOW_MASK) >> SCG_CSR_DIVSLOW_SHIFT) + 1; + divider = ((regval & SCG_CSR_DIVSLOW_MASK) >> + SCG_CSR_DIVSLOW_SHIFT) + 1; freq /= divider; break; @@ -1851,7 +1891,8 @@ uint32_t s32k1xx_get_asnchfreq(enum clock_names_e clksrc, { freq = s32k1xx_get_fircfreq(); regval = getreg32(S32K1XX_SCG_FIRCDIV); - div = (regval & SCG_FIRCDIV_FIRCDIV1_MASK) >> SCG_FIRCDIV_FIRCDIV1_SHIFT; + div = (regval & SCG_FIRCDIV_FIRCDIV1_MASK) >> + SCG_FIRCDIV_FIRCDIV1_SHIFT; } break; @@ -1859,7 +1900,8 @@ uint32_t s32k1xx_get_asnchfreq(enum clock_names_e clksrc, { freq = s32k1xx_get_sircfreq(); regval = getreg32(S32K1XX_SCG_SIRCDIV); - div = (regval & SCG_SIRCDIV_SIRCDIV1_MASK) >> SCG_SIRCDIV_SIRCDIV1_SHIFT; + div = (regval & SCG_SIRCDIV_SIRCDIV1_MASK) >> + SCG_SIRCDIV_SIRCDIV1_SHIFT; } break; @@ -1867,7 +1909,8 @@ uint32_t s32k1xx_get_asnchfreq(enum clock_names_e clksrc, { freq = s32k1xx_get_soscfreq(); regval = getreg32(S32K1XX_SCG_SOSCDIV); - div = (regval & SCG_SOSCDIV_SOSCDIV1_MASK) >> SCG_SOSCDIV_SOSCDIV1_SHIFT; + div = (regval & SCG_SOSCDIV_SOSCDIV1_MASK) >> + SCG_SOSCDIV_SOSCDIV1_SHIFT; } break; @@ -1876,7 +1919,8 @@ uint32_t s32k1xx_get_asnchfreq(enum clock_names_e clksrc, { freq = s32k1xx_get_spllfreq(); regval = getreg32(S32K1XX_SCG_SPLLDIV); - div = (regval & SCG_SPLLDIV_SPLLDIV1_MASK) >> SCG_SPLLDIV_SPLLDIV1_SHIFT; + div = (regval & SCG_SPLLDIV_SPLLDIV1_MASK) >> + SCG_SPLLDIV_SPLLDIV1_SHIFT; } break; #endif @@ -1901,7 +1945,8 @@ uint32_t s32k1xx_get_asnchfreq(enum clock_names_e clksrc, { freq = s32k1xx_get_fircfreq(); regval = getreg32(S32K1XX_SCG_FIRCDIV); - div = (regval & SCG_FIRCDIV_FIRCDIV2_MASK) >> SCG_FIRCDIV_FIRCDIV2_SHIFT; + div = (regval & SCG_FIRCDIV_FIRCDIV2_MASK) >> + SCG_FIRCDIV_FIRCDIV2_SHIFT; } break; @@ -1909,14 +1954,16 @@ uint32_t s32k1xx_get_asnchfreq(enum clock_names_e clksrc, { freq = s32k1xx_get_sircfreq(); regval = getreg32(S32K1XX_SCG_SIRCDIV); - div = (regval & SCG_SIRCDIV_SIRCDIV2_MASK) >> SCG_SIRCDIV_SIRCDIV2_SHIFT; + div = (regval & SCG_SIRCDIV_SIRCDIV2_MASK) >> + SCG_SIRCDIV_SIRCDIV2_SHIFT; } break; case SOSC_CLK: { freq = s32k1xx_get_soscfreq(); regval = getreg32(S32K1XX_SCG_SOSCDIV); - div = (regval & SCG_SOSCDIV_SOSCDIV2_MASK) >> SCG_SOSCDIV_SOSCDIV2_SHIFT; + div = (regval & SCG_SOSCDIV_SOSCDIV2_MASK) >> + SCG_SOSCDIV_SOSCDIV2_SHIFT; } break; #ifdef CONFIG_S32K1XX_HAVE_SPLL @@ -1924,7 +1971,8 @@ uint32_t s32k1xx_get_asnchfreq(enum clock_names_e clksrc, { freq = s32k1xx_get_spllfreq(); regval = getreg32(S32K1XX_SCG_SPLLDIV); - div = (regval & SCG_SPLLDIV_SPLLDIV2_MASK) >> SCG_SPLLDIV_SPLLDIV2_SHIFT; + div = (regval & SCG_SPLLDIV_SPLLDIV2_MASK) >> + SCG_SPLLDIV_SPLLDIV2_SHIFT; } break; #endif diff --git a/arch/arm/src/s32k1xx/s32k1xx_clockconfig.h b/arch/arm/src/s32k1xx/s32k1xx_clockconfig.h index 6dcbd860845..05fdf2e8bd9 100644 --- a/arch/arm/src/s32k1xx/s32k1xx_clockconfig.h +++ b/arch/arm/src/s32k1xx/s32k1xx_clockconfig.h @@ -412,7 +412,7 @@ struct sim_clock_config_s struct peripheral_clock_config_s; /* Forward reference */ struct pcc_config_s { - unsigned int count; /* Number of peripherals to be configured */ + unsigned int count; /* Number of peripherals to be configured */ const struct peripheral_clock_config_s *pclks; /* The peripheral clock configuration array */ }; diff --git a/arch/arm/src/s32k1xx/s32k1xx_config.h b/arch/arm/src/s32k1xx/s32k1xx_config.h index 78e3e60295b..a0033c2983c 100644 --- a/arch/arm/src/s32k1xx/s32k1xx_config.h +++ b/arch/arm/src/s32k1xx/s32k1xx_config.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/s32k1xx/s32k1xx_config.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,22 +16,22 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_S32K1XX_S32K1XX_CONFIG_H #define __ARCH_ARM_SRC_S32K1XX_S32K1XX_CONFIG_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* Configuration *********************************************************************/ +/* Configuration ************************************************************/ #undef HAVE_LPUART0 #undef HAVE_LPUART1 @@ -56,8 +56,8 @@ # define HAVE_LPUART_DEVICE 1 #endif -/* Is there a serial console? There should be at most one defined. It could be on - * any LPUARTn, n=0,1,2,3 +/* Is there a serial console? There should be at most one defined. + * It could be on any LPUARTn, n=0,1,2,3 */ #undef HAVE_LPUART_CONSOLE @@ -105,8 +105,8 @@ #define S32K1XX_ENET_HAS_DBSWAP 1 -/************************************************************************************ - * Public Functions - ************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_S32K1XX_S32K1XX_CONFIG_H */ diff --git a/arch/arm/src/s32k1xx/s32k1xx_edma.h b/arch/arm/src/s32k1xx/s32k1xx_edma.h index c2c486539cc..8874b04e89a 100644 --- a/arch/arm/src/s32k1xx/s32k1xx_edma.h +++ b/arch/arm/src/s32k1xx/s32k1xx_edma.h @@ -1,11 +1,12 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/s32k1xx/s32k1xx_edma.h * * Copyright (C) 2019 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * - * This file was leveraged from the NuttX i.MXRT port. Portions of that eDMA logic - * derived from NXP sample code which has a compatible BSD 3-clause license: + * This file was leveraged from the NuttX i.MXRT port. + * Portions of that eDMA logic derived from NXP sample code which has + * a compatible BSD 3-clause license: * * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP @@ -38,7 +39,7 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_S32K1XX_S32K1XX_EDMAC_H #define __ARCH_ARM_SRC_S32K1XX_S32K1XX_EDMAC_H @@ -65,46 +66,48 @@ * int ret; * ret = s32k1xx_dmach_xfrsetup(handle, &config); * - * 4. If you are setting up a scatter gather DMA (with CONFIG_S32K1XX_EDMA_NTCD > 0), - * then repeat steps 2 and 3 for each segment of the transfer. + * 4. If you are setting up a scatter gather DMA + * (with CONFIG_S32K1XX_EDMA_NTCD > 0), then repeat steps 2 and 3 for + * each segment of the transfer. * * 5. Start the DMA: * * ret = s32k1xx_dmach_start(handle, my_callback_func, priv); * - * Where my_callback_func() is called when the DMA completes or an error occurs. - * 'priv' represents some internal driver state that will be provided with the - * callback. + * Where my_callback_func() is called when the DMA completes or an error + * occurs. 'priv' represents some internal driver state that will be + * provided with the callback. * - * 6. If you need to stop the DMA and free resources (such as if a timeout occurs), - * then: + * 6. If you need to stop the DMA and free resources (such as if a timeout + * occurs), then: * * i mxrt_dmach_stop(handle); * - * 7. The callback will be received when the DMA completes (or an error occurs). - * After that, you may free the DMA channel, or re-use it on subsequent DMAs. + * 7. The callback will be received when the DMA completes (or an error + * occurs). After that, you may free the DMA channel, or re-use it on + * subsequent DMAs. * * s32k1xx_dmach_free(handle); * * Almost non-invasive debug instrumentation is available. You may call - * s32k1xx_dmasample() to save the current state of the eDMA registers at any given - * point in time. At some later, postmortem analysis, you can dump the content of - * the buffered registers with s32k1xx_dmadump(). s32k1xx_dmasample() is also - * available for monitoring DMA progress. + * s32k1xx_dmasample() to save the current state of the eDMA registers at + * any given point in time. At some later, postmortem analysis, you can + * dump the content of the buffered registers with s32k1xx_dmadump(). + * s32k1xx_dmasample() is also available for monitoring DMA progress. */ -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include #include "hardware/s32k1xx_edma.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ /* Configuration flags. * @@ -119,12 +122,13 @@ # define EDMA_CONFIG_LINKTYPE_MINORLINK (1 << EDMA_CONFIG_LINKTYPE_SHIFT) /* Channel link after each minor loop */ # define EDMA_CONFIG_LINKTYPE_MAJORLINK (2 << EDMA_CONFIG_LINKTYPE_SHIFT) /* Channel link when major loop count exhausted */ -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ typedef FAR void *DMACH_HANDLE; -typedef void (*edma_callback_t)(DMACH_HANDLE handle, void *arg, bool done, int result); +typedef void (*edma_callback_t)(DMACH_HANDLE handle, + void *arg, bool done, int result); /* eDMA transfer type */ @@ -135,7 +139,9 @@ enum s32k1xx_edma_xfrtype_e EDMA_MEM2PERIPH, /* Transfer from memory to peripheral */ }; -/* This structure holds the source/destination transfer attribute configuration. */ +/* This structure holds the source/destination transfer attribute + * configuration. + */ struct s32k1xx_edma_xfrconfig_s { @@ -158,7 +164,9 @@ struct s32k1xx_edma_xfrconfig_s #endif }; -/* The following is used for sampling DMA registers when CONFIG DEBUG_DMA is selected */ +/* The following is used for sampling DMA registers when CONFIG DEBUG_DMA + * is selected + */ #ifdef CONFIG_DEBUG_DMA struct s32k1xx_dmaregs_s @@ -199,15 +207,15 @@ struct s32k1xx_dmaregs_s }; #endif /* CONFIG_DEBUG_DMA */ -/************************************************************************************ +/**************************************************************************** * Inline Functions - ************************************************************************************/ + ****************************************************************************/ #ifndef __ASSEMBLY__ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ #undef EXTERN #if defined(__cplusplus) @@ -218,9 +226,9 @@ extern "C" #define EXTERN extern #endif -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ /**************************************************************************** * Name: s32k1xx_dmach_alloc @@ -231,7 +239,8 @@ extern "C" * * Input Parameters: * dmamux - DMAMUX configuration see DMAMUX channel configuration register - * bit-field definitions in hardware/s32k1xx_dmamux.h. Settings include: + * bit-field definitions in hardware/s32k1xx_dmamux.h. + * Settings include: * * DMAMUX_CHCFG_SOURCE Chip-specific DMA source (required) * DMAMUX_CHCFG_AON DMA Channel Always Enable (optional) @@ -257,30 +266,33 @@ extern "C" DMACH_HANDLE s32k1xx_dmach_alloc(uint32_t dmamux, uint8_t dchpri); -/************************************************************************************ +/**************************************************************************** * Name: s32k1xx_dmach_free * * Description: - * Release a DMA channel. NOTE: The 'handle' used in this argument must NEVER be - * used again until s32k1xx_dmach_alloc() is called again to re-gain a valid handle. + * Release a DMA channel. + * NOTE: The 'handle' used in this argument must NEVER be used again + * until s32k1xx_dmach_alloc() is called again to re-gain a valid handle. * * Returned Value: * None * - ************************************************************************************/ + ****************************************************************************/ void s32k1xx_dmach_free(DMACH_HANDLE handle); -/************************************************************************************ +/**************************************************************************** * Name: s32k1xx_dmach_xfrsetup * * Description: * This function adds the eDMA transfer to the DMA sequence. The request * is setup according to the content of the transfer configuration - * structure. For "normal" DMA, s32k1xx_dmach_xfrsetup is called only once. + * structure. For "normal" DMA, s32k1xx_dmach_xfrsetup is called only + * once. * Scatter/gather DMA is accomplished by calling this function repeatedly, * once for each transfer in the sequence. Scatter/gather DMA processing - * is enabled automatically when the second transfer configuration is received. + * is enabled automatically when the second transfer configuration is + * received. * * This function may be called multiple times to handle multiple, * discontinuous transfers (scatter-gather) @@ -294,52 +306,56 @@ void s32k1xx_dmach_free(DMACH_HANDLE handle); * Zero (OK) is returned on success; a negated errno value is returned on * any failure. * - ************************************************************************************/ + ****************************************************************************/ int s32k1xx_dmach_xfrsetup(DMACH_HANDLE *handle, const struct s32k1xx_edma_xfrconfig_s *config); -/************************************************************************************ +/**************************************************************************** * Name: s32k1xx_dmach_start * * Description: - * Start the DMA transfer by enabling the channel DMA request. This function - * should be called after the final call to s32k1xx_dmasetup() in order to avoid - * race conditions. + * Start the DMA transfer by enabling the channel DMA request. + * This function should be called after the final call to + * s32k1xx_dmasetup() in order to avoid race conditions. * - * At the conclusion of each major DMA loop, a callback to the user-provided - * function is made: |For "normal" DMAs, this will correspond to the DMA DONE - * interrupt; for scatter gather DMAs, multiple interrupts will be generated - * with the final being the DONE interrupt. + * At the conclusion of each major DMA loop, a callback to the + * user-provided function is made: |For "normal" DMAs, this will + * correspond to the DMA DONE interrupt; for scatter gather DMAs, multiple + * interrupts will be generated with the final being the DONE interrupt. * - * At the conclusion of the DMA, the DMA channel is reset, all TCDs are freed, and - * the callback function is called with the the success/fail result of the DMA. + * At the conclusion of the DMA, the DMA channel is reset, all TCDs are + * freed, and the callback function is called with the the success/fail + * result of the DMA. * - * NOTE: On Rx DMAs (peripheral-to-memory or memory-to-memory), it is necessary - * to invalidate the destination memory. That is not done automatically by the - * DMA module. Invalidation of the destination memory regions is the - * responsibility of the caller. + * NOTE: + * On Rx DMAs (peripheral-to-memory or memory-to-memory), it is necessary + * to invalidate the destination memory. That is not done automatically + * by the DMA module. Invalidation of the destination memory regions is + * the responsibility of the caller. * * Input Parameters: * handle - DMA channel handle created by s32k1xx_dmach_alloc() - * callback - The callback to be invoked when the DMA is completes or is aborted. + * callback - The callback to be invoked when the DMA is completes or is + * aborted. * arg - An argument that accompanies the callback * * Returned Value: * Zero (OK) is returned on success; a negated errno value is returned on * any failure. * - ************************************************************************************/ + ****************************************************************************/ -int s32k1xx_dmach_start(DMACH_HANDLE handle, edma_callback_t callback, void *arg); +int s32k1xx_dmach_start(DMACH_HANDLE handle, + edma_callback_t callback, void *arg); -/************************************************************************************ +/**************************************************************************** * Name: s32k1xx_dmach_stop * * Description: - * Cancel the DMA. After s32k1xx_dmach_stop() is called, the DMA channel is reset, - * all TCDs are freed, and s32k1xx_dmarx/txsetup() must be called before - * s32k1xx_dmach_start() can be called again + * Cancel the DMA. After s32k1xx_dmach_stop() is called, the DMA channel + * is reset, all TCDs are freed, and s32k1xx_dmarx/txsetup() must be called + * before s32k1xx_dmach_start() can be called again * * Input Parameters: * handle - DMA channel handle created by s32k1xx_dmach_alloc() @@ -347,11 +363,11 @@ int s32k1xx_dmach_start(DMACH_HANDLE handle, edma_callback_t callback, void *arg * Returned Value: * None. * - ************************************************************************************/ + ****************************************************************************/ void s32k1xx_dmach_stop(DMACH_HANDLE handle); -/************************************************************************************ +/**************************************************************************** * Name: s32k1xx_dmach_getcount * * Description: @@ -374,7 +390,7 @@ void s32k1xx_dmach_stop(DMACH_HANDLE handle); * initial value of NBYTES (for example copied before enabling the channel) * is needed. The formula to calculate it is shown below: * - * RemainingBytes = RemainingMajorLoopCount * NBYTES(initially configured) + * RemainingBytes = RemainingMajorLoopCount * NBYTES(initially configured) * * Input Parameters: * handle - DMA channel handle created by s32k1xx_dmach_alloc() @@ -382,17 +398,17 @@ void s32k1xx_dmach_stop(DMACH_HANDLE handle); * Returned Value: * Major loop count which has not been transferred yet for the current TCD. * - ************************************************************************************/ + ****************************************************************************/ unsigned int s32k1xx_dmach_getcount(DMACH_HANDLE *handle); -/************************************************************************************ +/**************************************************************************** * Name: s32k1xx_dmasample * * Description: * Sample DMA register contents * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_DEBUG_DMA void s32k1xx_dmasample(DMACH_HANDLE handle, struct s32k1xx_dmaregs_s *regs); @@ -400,13 +416,13 @@ void s32k1xx_dmasample(DMACH_HANDLE handle, struct s32k1xx_dmaregs_s *regs); # define s32k1xx_dmasample(handle,regs) #endif -/************************************************************************************ +/**************************************************************************** * Name: s32k1xx_dmadump * * Description: * Dump previously sampled DMA register contents * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_DEBUG_DMA void s32k1xx_dmadump(const struct s32k1xx_dmaregs_s *regs, const char *msg); diff --git a/arch/arm/src/s32k1xx/s32k1xx_eeeprom.c b/arch/arm/src/s32k1xx/s32k1xx_eeeprom.c index d8bb58db406..750deb19a90 100644 --- a/arch/arm/src/s32k1xx/s32k1xx_eeeprom.c +++ b/arch/arm/src/s32k1xx/s32k1xx_eeeprom.c @@ -1,4 +1,4 @@ -/****************************************************************************** +/**************************************************************************** * arch/arm/src/s32k1xx/s32k1xx_eeeprom.c * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,11 +16,11 @@ * License for the specific language governing permissions and limitations * under the License. * - ******************************************************************************/ + ****************************************************************************/ -/****************************************************************************** +/**************************************************************************** * Included Files - ******************************************************************************/ + ****************************************************************************/ #include @@ -46,9 +46,9 @@ #include #include -/****************************************************************************** +/**************************************************************************** * Private Types - ******************************************************************************/ + ****************************************************************************/ struct eeed_struct_s { @@ -60,9 +60,9 @@ struct eeed_struct_s FAR uint8_t *eeed_buffer; /* FlexRAM memory */ }; -/****************************************************************************** +/**************************************************************************** * Private Function Prototypes - ******************************************************************************/ + ****************************************************************************/ #ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS static int eeed_open(FAR struct inode *inode); @@ -84,9 +84,9 @@ static int eeed_ioctl(FAR struct inode *inode, int cmd, static int eeed_unlink(FAR struct inode *inode); #endif -/****************************************************************************** +/**************************************************************************** * Private Data - ******************************************************************************/ + ****************************************************************************/ static const struct block_operations g_bops = { @@ -106,9 +106,9 @@ static const struct block_operations g_bops = #endif }; -/****************************************************************************** +/**************************************************************************** * Private Functions - ******************************************************************************/ + ****************************************************************************/ static inline void wait_ftfc_ready() { @@ -142,12 +142,12 @@ static uint32_t execute_ftfc_command() return retval; } -/****************************************************************************** +/**************************************************************************** * Name: eeed_open * * Description: Open the block device * - ******************************************************************************/ + ****************************************************************************/ #ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS static int eeed_open(FAR struct inode *inode) @@ -167,12 +167,12 @@ static int eeed_open(FAR struct inode *inode) } #endif -/****************************************************************************** +/**************************************************************************** * Name: eeed_close * * Description: close the block device * - ******************************************************************************/ + ****************************************************************************/ #ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS static int eeed_close(FAR struct inode *inode) @@ -192,12 +192,12 @@ static int eeed_close(FAR struct inode *inode) } #endif -/****************************************************************************** +/**************************************************************************** * Name: eeed_read * * Description: Read the specified number of sectors * - ******************************************************************************/ + ****************************************************************************/ static ssize_t eeed_read(FAR struct inode *inode, unsigned char *buffer, blkcnt_t start_sector, unsigned int nsectors) @@ -228,15 +228,16 @@ static ssize_t eeed_read(FAR struct inode *inode, unsigned char *buffer, return -EINVAL; } -/****************************************************************************** +/**************************************************************************** * Name: eeed_write * * Description: Write the specified number of sectors * - ******************************************************************************/ + ****************************************************************************/ -static ssize_t eeed_write(FAR struct inode *inode, const unsigned char *buffer, - blkcnt_t start_sector, unsigned int nsectors) +static ssize_t eeed_write(FAR struct inode *inode, + const unsigned char *buffer, + blkcnt_t start_sector, unsigned int nsectors) { struct eeed_struct_s *dev; @@ -272,12 +273,12 @@ static ssize_t eeed_write(FAR struct inode *inode, const unsigned char *buffer, return -EFBIG; } -/****************************************************************************** +/**************************************************************************** * Name: eeed_geometry * * Description: Return device geometry * - ******************************************************************************/ + ****************************************************************************/ static int eeed_geometry(FAR struct inode *inode, struct geometry *geometry) { @@ -306,13 +307,13 @@ static int eeed_geometry(FAR struct inode *inode, struct geometry *geometry) return -EINVAL; } -/****************************************************************************** +/**************************************************************************** * Name: eeed_ioctl * * Description: * Return device geometry * - ******************************************************************************/ + ****************************************************************************/ static int eeed_ioctl(FAR struct inode *inode, int cmd, unsigned long arg) { @@ -336,13 +337,13 @@ static int eeed_ioctl(FAR struct inode *inode, int cmd, unsigned long arg) return -ENOTTY; } -/****************************************************************************** +/**************************************************************************** * Name: eeed_unlink * * Description: * The block driver has been unlinked. * - ******************************************************************************/ + ****************************************************************************/ #ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS static int eeed_unlink(FAR struct inode *inode) @@ -360,24 +361,24 @@ static int eeed_unlink(FAR struct inode *inode) } #endif -/****************************************************************************** +/**************************************************************************** * Public Functions - ******************************************************************************/ + ****************************************************************************/ -/****************************************************************************** +/**************************************************************************** * Name: s32k1xx_eeeprom_register * * Description: * Non-standard function to register a eeeprom * * Input Parameters: - * minor: Selects suffix of device named /dev/eeepromN, N={1,2,3...} - * size: The size of eeprom in bytes + * minor: Selects suffix of device named /dev/eeepromN, N={1,2,3...} + * size: The size of eeprom in bytes * * Returned Value: * Zero on success; a negated errno value on failure. * - ******************************************************************************/ + ****************************************************************************/ int s32k1xx_eeeprom_register(int minor, uint32_t size) { @@ -413,14 +414,14 @@ int s32k1xx_eeeprom_register(int minor, uint32_t size) return ret; } -/****************************************************************************** +/**************************************************************************** * Name: s32k1xx_eeeprom_init * * Description: * Init FTFC flash controller to run in Enhanced EEPROM mode * * - ******************************************************************************/ + ****************************************************************************/ void s32k1xx_eeeprom_init() { diff --git a/arch/arm/src/s32k1xx/s32k1xx_eeeprom.h b/arch/arm/src/s32k1xx/s32k1xx_eeeprom.h index 6009f183a7d..545c15c95b6 100644 --- a/arch/arm/src/s32k1xx/s32k1xx_eeeprom.h +++ b/arch/arm/src/s32k1xx/s32k1xx_eeeprom.h @@ -1,4 +1,4 @@ -/****************************************************************************** +/**************************************************************************** * arch/arm/src/s32k1xx/s32k1xx_eeeprom.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,14 +16,14 @@ * License for the specific language governing permissions and limitations * under the License. * - ******************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_S32K1XX_EEEPROM_H #define __ARCH_ARM_SRC_S32K1XX_EEEPROM_H -/****************************************************************************** +/**************************************************************************** * Included Files - ******************************************************************************/ + ****************************************************************************/ #include #include @@ -35,39 +35,39 @@ #include "arm_internal.h" #include "s32k1xx_config.h" -/****************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ******************************************************************************/ + ****************************************************************************/ -/****************************************************************************** +/**************************************************************************** * Public Function Prototypes - ******************************************************************************/ + ****************************************************************************/ -/****************************************************************************** +/**************************************************************************** * Name: s32k1xx_eeeprom_init * * Description: * Init FTFC flash controller to run in Enhanced EEPROM mode * * - ******************************************************************************/ + ****************************************************************************/ void s32k1xx_eeeprom_init(void); -/****************************************************************************** +/**************************************************************************** * Name: s32k1xx_eeeprom_register * * Description: * Non-standard function to register a eeeprom * * Input Parameters: - * minor: Selects suffix of device named /dev/eeepromN, N={1,2,3...} - * size: The size of eeprom in bytes + * minor: Selects suffix of device named /dev/eeepromN, N={1,2,3...} + * size: The size of eeprom in bytes * * Returned Value: * Zero on success; a negated errno value on failure. * - ******************************************************************************/ + ****************************************************************************/ int s32k1xx_eeeprom_register(int minor, uint32_t size); #endif /* __ARCH_ARM_SRC_S32K1XX_EEEPROM_H */ diff --git a/arch/arm/src/s32k1xx/s32k1xx_enet.h b/arch/arm/src/s32k1xx/s32k1xx_enet.h index 7aa0d167958..31bcde7f63c 100644 --- a/arch/arm/src/s32k1xx/s32k1xx_enet.h +++ b/arch/arm/src/s32k1xx/s32k1xx_enet.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/s32k1xx/s32k1xx_enet.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,14 +16,14 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_S32K1XX_S32K1XX_ENET_H #define __ARCH_ARM_SRC_S32K1XX_S32K1XX_ENET_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include @@ -31,17 +31,17 @@ #ifdef CONFIG_S32K1XX_ENET -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ /* Definitions for use with s32k1xx_phy_boardinitialize */ #define EMAC_INTF 0 -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ #ifndef __ASSEMBLY__ @@ -56,7 +56,7 @@ extern "C" #if !defined(CONFIG_NETDEV_LATEINIT) -/************************************************************************************ +/**************************************************************************** * Function: arm_netinitialize * * Description: @@ -74,13 +74,13 @@ extern "C" * Assumptions: * Called very early in the initialization sequence. * - ************************************************************************************/ + ****************************************************************************/ void arm_netinitialize(void); #else -/************************************************************************************ +/**************************************************************************** * Function: s32k1xx_netinitialize * * Description: @@ -95,21 +95,22 @@ void arm_netinitialize(void); * * Assumptions: * - ************************************************************************************/ + ****************************************************************************/ int s32k1xx_netinitialize(int intf); #endif -/************************************************************************************ +/**************************************************************************** * Function: s32k1xx_phy_boardinitialize * * Description: - * Some boards require specialized initialization of the PHY before it can be - * used. This may include such things as configuring GPIOs, resetting the PHY, - * etc. If CONFIG_S32K1XX_ENET_PHYINIT is defined in the configuration then the - * board specific logic must provide s32k1xx_phyinitialize(); The i.MX RT Ethernet - * driver will call this function one time before it first uses the PHY. + * Some boards require specialized initialization of the PHY before it can + * be be used. This may include such things as configuring GPIOs, + * resetting the PHY, etc. If CONFIG_S32K1XX_ENET_PHYINIT is defined in + * the configuration then the board specific logic must provide + * s32k1xx_phyinitialize(); The i.MX RT Ethernet driver will call this + * function one time before it first uses the PHY. * * Input Parameters: * intf - Always zero for now. @@ -117,7 +118,7 @@ int s32k1xx_netinitialize(int intf); * Returned Value: * OK on success; Negated errno on failure. * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_S32K1XX_ENET_PHYINIT int s32k1xx_phy_boardinitialize(int intf); diff --git a/arch/arm/src/s32k1xx/s32k1xx_flashcfg.c b/arch/arm/src/s32k1xx/s32k1xx_flashcfg.c index b643cfb785e..a77f4d8e7d3 100644 --- a/arch/arm/src/s32k1xx/s32k1xx_flashcfg.c +++ b/arch/arm/src/s32k1xx/s32k1xx_flashcfg.c @@ -53,3 +53,8 @@ const uint8_t g_flashcfg[16] __attribute__((section(".flashcfg"))) = (uint8_t)CONFIG_S32K1XX_FLASHCFG_FEPROT, /* 0x040e */ (uint8_t)CONFIG_S32K1XX_FLASHCFG_FDPROT /* 0x040f */ }; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + diff --git a/arch/arm/src/s32k1xx/s32k1xx_flexcan.h b/arch/arm/src/s32k1xx/s32k1xx_flexcan.h index 7c177ca77f3..072042c7559 100644 --- a/arch/arm/src/s32k1xx/s32k1xx_flexcan.h +++ b/arch/arm/src/s32k1xx/s32k1xx_flexcan.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/s32k1xx/s32k1xx_flexcan.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,14 +16,14 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_S32K1XX_S32K1XX_FLEXCAN_H #define __ARCH_ARM_SRC_S32K1XX_S32K1XX_FLEXCAN_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include @@ -31,13 +31,13 @@ #ifdef CONFIG_S32K1XX_FLEXCAN -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ #ifndef __ASSEMBLY__ @@ -52,7 +52,7 @@ extern "C" #if !defined(CONFIG_NETDEV_LATEINIT) -/************************************************************************************ +/**************************************************************************** * Function: arm_netinitialize * * Description: @@ -70,13 +70,13 @@ extern "C" * Assumptions: * Called very early in the initialization sequence. * - ************************************************************************************/ + ****************************************************************************/ void arm_netinitialize(void); #else -/************************************************************************************ +/**************************************************************************** * Function: s32k1xx_caninitialize * * Description: @@ -91,7 +91,7 @@ void arm_netinitialize(void); * * Assumptions: * - ************************************************************************************/ + ****************************************************************************/ int s32k1xx_caninitialize(int intf); diff --git a/arch/arm/src/s32k1xx/s32k1xx_lowputc.c b/arch/arm/src/s32k1xx/s32k1xx_lowputc.c index 52ab3016cb3..6d0fed6e5e8 100644 --- a/arch/arm/src/s32k1xx/s32k1xx_lowputc.c +++ b/arch/arm/src/s32k1xx/s32k1xx_lowputc.c @@ -269,9 +269,11 @@ int s32k1xx_lpuart_configure(uint32_t base, /* Select the better value between srb and (sbr + 1) */ - if (temp_diff > (config->baud - (lpuart_freq / (temp_osr * (temp_sbr + 1))))) + if (temp_diff > + (config->baud - (lpuart_freq / (temp_osr * (temp_sbr + 1))))) { - temp_diff = config->baud - (lpuart_freq / (temp_osr * (temp_sbr + 1))); + temp_diff = config->baud - + (lpuart_freq / (temp_osr * (temp_sbr + 1))); temp_sbr++; } @@ -394,13 +396,16 @@ void s32k1xx_lowputc(int ch) { } - /* If the character to output is a newline, then pre-pend a carriage return */ + /* If the character to output is a newline, + * then pre-pend a carriage return + */ if (ch == '\n') { /* Send the carriage return by writing it into the UART_TXD register. */ - putreg32((uint32_t)'\r', S32K1XX_CONSOLE_BASE + S32K1XX_LPUART_DATA_OFFSET); + putreg32((uint32_t)'\r', + S32K1XX_CONSOLE_BASE + S32K1XX_LPUART_DATA_OFFSET); /* Wait for the transmit register to be emptied. When the TXFE bit is * non-zero, the TX Buffer FIFO is empty. diff --git a/arch/arm/src/s32k1xx/s32k1xx_lpspi.c b/arch/arm/src/s32k1xx/s32k1xx_lpspi.c index f50ed6bc405..5ecf4357b6e 100644 --- a/arch/arm/src/s32k1xx/s32k1xx_lpspi.c +++ b/arch/arm/src/s32k1xx/s32k1xx_lpspi.c @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/s32k1xx/s32k1xx_lpspi.c * * Copyright (C) 2019 Gregory Nutt. All rights reserved. @@ -32,34 +32,34 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ - * The external functions, s32k1xx_lpspi0/1/2select and s32k1xx_lpspi0/1/2status - * must be provided by board-specific logic. They are implementations of the select - * and status methods of the SPI interface defined by struct s32k1xx_lpspi_ops_s (see - * include/nuttx/spi/spi.h). All other methods (including - * s32k1xx_lpspibus_initialize()) are provided by common S32K1XX logic. To use this - * common SPI logic on your board: +/**************************************************************************** + * The external functions, s32k1xx_lpspi0/1/2select and + * s32k1xx_lpspi0/1/2status must be provided by board-specific logic. They + * are implementations of the select and status methods of the SPI interface + * defined by struct s32k1xx_lpspi_ops_s (see include/nuttx/spi/spi.h). + * All other methods (including s32k1xx_lpspibus_initialize()) are provided + * by common S32K1XX logic. To use this common SPI logic on your board: * - * 1. Provide logic in s32k1xx_boardinitialize() to configure SPI chip select - * pins. + * 1. Provide logic in s32k1xx_boardinitialize() to configure SPI chip + * select pins. * 2. Provide s32k1xx_lpspi0/1/2select() and s32k1xx_lpspi0/1/2status() - * functions in your board-specific logic. These functions will perform chip - * selection and status operations using GPIOs in the way your board is - * configured. - * 3. Add a calls to s32k1xx_lpspibus_initialize() in your low level application - * initialization logic - * 4. The handle returned by s32k1xx_lpspibus_initialize() may then be used to bind - * the SPI driver to higher level logic (e.g., calling - * mmcsd_lpspislotinitialize(), for example, will bind the SPI driver to - * the SPI MMC/SD driver). + * functions in your board-specific logic. These functions will perform + * chip selection and status operations using GPIOs in the way your + * board is configured. + * 3. Add a calls to s32k1xx_lpspibus_initialize() in your low level + * application initialization logic + * 4. The handle returned by s32k1xx_lpspibus_initialize() may then be + * used to bind the SPI driver to higher level logic (e.g., calling + * mmcsd_lpspislotinitialize(), for example, will bind the SPI driver + * to the SPI MMC/SD driver). * - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include @@ -93,11 +93,11 @@ #if defined(CONFIG_S32K1XX_LPSPI0) || defined(CONFIG_S32K1XX_LPSPI1) || \ defined(CONFIG_S32K1XX_LPSPI2) -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* Configuration ********************************************************************/ +/* Configuration ************************************************************/ /* SPI interrupts */ @@ -115,9 +115,9 @@ # error "Cannot enable both interrupt mode and DMA mode for SPI" #endif -/************************************************************************************ +/**************************************************************************** * Private Types - ************************************************************************************/ + ****************************************************************************/ struct s32k1xx_lpspidev_s { @@ -140,25 +140,34 @@ enum s32k1xx_delay_e LPSPI_BETWEEN_TRANSFER /* Delay between transfers. */ }; -/************************************************************************************ +/**************************************************************************** * Private Function Prototypes - ************************************************************************************/ + ****************************************************************************/ /* Helpers */ -static inline uint32_t s32k1xx_lpspi_getreg32(FAR struct s32k1xx_lpspidev_s *priv, - uint8_t offset); -static inline void s32k1xx_lpspi_putreg32(FAR struct s32k1xx_lpspidev_s *priv, - uint8_t offset, uint32_t value); -static inline uint32_t s32k1xx_lpspi_readword(FAR struct s32k1xx_lpspidev_s *priv); -static inline void s32k1xx_lpspi_writeword(FAR struct s32k1xx_lpspidev_s *priv, - uint16_t byte); -static inline bool s32k1xx_lpspi_9to16bitmode(FAR struct s32k1xx_lpspidev_s *priv); +static inline +uint32_t s32k1xx_lpspi_getreg32(FAR struct s32k1xx_lpspidev_s *priv, + uint8_t offset); +static inline +void s32k1xx_lpspi_putreg32(FAR struct s32k1xx_lpspidev_s *priv, + uint8_t offset, uint32_t value); +static inline +uint32_t s32k1xx_lpspi_readword(FAR struct s32k1xx_lpspidev_s *priv); +static inline +void s32k1xx_lpspi_writeword(FAR struct s32k1xx_lpspidev_s *priv, + uint16_t byte); +static inline +bool s32k1xx_lpspi_9to16bitmode(FAR struct s32k1xx_lpspidev_s *priv); static uint32_t s32k1xx_lpspi_pckfreq(uintptr_t base); -static inline void s32k1xx_lpspi_set_delays(FAR struct s32k1xx_lpspidev_s - *priv, uint32_t delay_ns, enum s32k1xx_delay_e type); -static inline void s32k1xx_lpspi_set_delay_scaler(FAR struct - s32k1xx_lpspidev_s *priv, uint32_t scaler, enum s32k1xx_delay_e type); +static inline +void s32k1xx_lpspi_set_delays(FAR struct s32k1xx_lpspidev_s *priv, + uint32_t delay_ns, + enum s32k1xx_delay_e type); +static inline +void s32k1xx_lpspi_set_delay_scaler(FAR struct s32k1xx_lpspidev_s *priv, + uint32_t scaler, + enum s32k1xx_delay_e type); /* SPI methods */ @@ -178,17 +187,19 @@ static void s32k1xx_lpspi_exchange(FAR struct spi_dev_s *dev, #ifndef CONFIG_SPI_EXCHANGE static void s32k1xx_lpspi_sndblock(FAR struct spi_dev_s *dev, FAR const void *txbuffer, size_t nwords); -static void s32k1xx_lpspi_recvblock(FAR struct spi_dev_s *dev, FAR void *rxbuffer, - size_t nwords); +static void s32k1xx_lpspi_recvblock(FAR struct spi_dev_s *dev, + FAR void *rxbuffer, + size_t nwords); #endif /* Initialization */ -static void s32k1xx_lpspi_bus_initialize(FAR struct s32k1xx_lpspidev_s *priv); +static void +s32k1xx_lpspi_bus_initialize(FAR struct s32k1xx_lpspidev_s *priv); -/************************************************************************************ +/**************************************************************************** * Private Data - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_S32K1XX_LPSPI0 static const struct spi_ops_s g_spi0ops = @@ -328,11 +339,11 @@ static struct s32k1xx_lpspidev_s g_lpspi2dev = }; #endif -/************************************************************************************ +/**************************************************************************** * Private Functions - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Name: s32k1xx_lpspi_getreg8 * * Description: @@ -345,15 +356,16 @@ static struct s32k1xx_lpspidev_s g_lpspi2dev = * Returned Value: * The contents of the 8-bit register * - ************************************************************************************/ + ****************************************************************************/ -static inline uint8_t s32k1xx_lpspi_getreg8(FAR struct s32k1xx_lpspidev_s *priv, - uint8_t offset) +static inline +uint8_t s32k1xx_lpspi_getreg8(FAR struct s32k1xx_lpspidev_s *priv, + uint8_t offset) { return getreg8(priv->spibase + offset); } -/************************************************************************************ +/**************************************************************************** * Name: s32k1xx_lpspi_putreg8 * * Description: @@ -364,7 +376,7 @@ static inline uint8_t s32k1xx_lpspi_getreg8(FAR struct s32k1xx_lpspidev_s *priv, * offset - offset to the register of interest * value - the 8-bit value to be written * - ************************************************************************************/ + ****************************************************************************/ static inline void s32k1xx_lpspi_putreg8(FAR struct s32k1xx_lpspidev_s *priv, uint8_t offset, uint8_t value) @@ -372,7 +384,7 @@ static inline void s32k1xx_lpspi_putreg8(FAR struct s32k1xx_lpspidev_s *priv, putreg8(value, priv->spibase + offset); } -/************************************************************************************ +/**************************************************************************** * Name: s32k1xx_lpspi_getreg * * Description: @@ -385,15 +397,16 @@ static inline void s32k1xx_lpspi_putreg8(FAR struct s32k1xx_lpspidev_s *priv, * Returned Value: * The contents of the 32-bit register * - ************************************************************************************/ + ****************************************************************************/ -static inline uint32_t s32k1xx_lpspi_getreg32(FAR struct s32k1xx_lpspidev_s *priv, - uint8_t offset) +static inline +uint32_t s32k1xx_lpspi_getreg32(FAR struct s32k1xx_lpspidev_s *priv, + uint8_t offset) { return getreg32(priv->spibase + offset); } -/************************************************************************************ +/**************************************************************************** * Name: s32k1xx_lpspi_putreg * * Description: @@ -407,15 +420,16 @@ static inline uint32_t s32k1xx_lpspi_getreg32(FAR struct s32k1xx_lpspidev_s *pri * Returned Value: * The contents of the 32-bit register * - ************************************************************************************/ + ****************************************************************************/ -static inline void s32k1xx_lpspi_putreg32(FAR struct s32k1xx_lpspidev_s *priv, - uint8_t offset, uint32_t value) +static inline +void s32k1xx_lpspi_putreg32(FAR struct s32k1xx_lpspidev_s *priv, + uint8_t offset, uint32_t value) { putreg32(value, priv->spibase + offset); } -/************************************************************************************ +/**************************************************************************** * Name: s32k1xx_lpspi_readword * * Description: @@ -427,13 +441,15 @@ static inline void s32k1xx_lpspi_putreg32(FAR struct s32k1xx_lpspidev_s *priv, * Returned Value: * word as read * - ************************************************************************************/ + ****************************************************************************/ -static inline uint32_t s32k1xx_lpspi_readword(FAR struct s32k1xx_lpspidev_s *priv) +static inline +uint32_t s32k1xx_lpspi_readword(FAR struct s32k1xx_lpspidev_s *priv) { /* Wait until the receive buffer is not empty */ - while ((s32k1xx_lpspi_getreg32(priv, S32K1XX_LPSPI_SR_OFFSET) & LPSPI_SR_RDF) == 0) + while ((s32k1xx_lpspi_getreg32(priv, S32K1XX_LPSPI_SR_OFFSET) & + LPSPI_SR_RDF) == 0) { } @@ -442,7 +458,7 @@ static inline uint32_t s32k1xx_lpspi_readword(FAR struct s32k1xx_lpspidev_s *pri return (uint32_t) s32k1xx_lpspi_getreg32(priv, S32K1XX_LPSPI_RDR_OFFSET); } -/************************************************************************************ +/**************************************************************************** * Name: s32k1xx_lpspi_writeword * * Description: @@ -455,14 +471,16 @@ static inline uint32_t s32k1xx_lpspi_readword(FAR struct s32k1xx_lpspidev_s *pri * Returned Value: * None * - ************************************************************************************/ + ****************************************************************************/ -static inline void s32k1xx_lpspi_writeword(FAR struct s32k1xx_lpspidev_s *priv, - uint16_t word) +static inline +void s32k1xx_lpspi_writeword(FAR struct s32k1xx_lpspidev_s *priv, + uint16_t word) { /* Wait until the transmit buffer is empty */ - while ((s32k1xx_lpspi_getreg32(priv, S32K1XX_LPSPI_SR_OFFSET) & LPSPI_SR_TDF) == 0) + while ((s32k1xx_lpspi_getreg32(priv, S32K1XX_LPSPI_SR_OFFSET) & + LPSPI_SR_TDF) == 0) { } @@ -471,7 +489,7 @@ static inline void s32k1xx_lpspi_writeword(FAR struct s32k1xx_lpspidev_s *priv, s32k1xx_lpspi_putreg32(priv, S32K1XX_LPSPI_TDR_OFFSET, word); } -/************************************************************************************ +/**************************************************************************** * Name: s32k1xx_lpspi_readbyte * * Description: @@ -483,13 +501,15 @@ static inline void s32k1xx_lpspi_writeword(FAR struct s32k1xx_lpspidev_s *priv, * Returned Value: * Byte as read * - ************************************************************************************/ + ****************************************************************************/ -static inline uint8_t s32k1xx_lpspi_readbyte(FAR struct s32k1xx_lpspidev_s *priv) +static inline +uint8_t s32k1xx_lpspi_readbyte(FAR struct s32k1xx_lpspidev_s *priv) { /* Wait until the receive buffer is not empty */ - while ((s32k1xx_lpspi_getreg32(priv, S32K1XX_LPSPI_SR_OFFSET) & LPSPI_SR_RDF) == 0) + while ((s32k1xx_lpspi_getreg32(priv, S32K1XX_LPSPI_SR_OFFSET) & + LPSPI_SR_RDF) == 0) { } @@ -498,7 +518,7 @@ static inline uint8_t s32k1xx_lpspi_readbyte(FAR struct s32k1xx_lpspidev_s *priv return s32k1xx_lpspi_getreg8(priv, S32K1XX_LPSPI_RDR_OFFSET); } -/************************************************************************************ +/**************************************************************************** * Name: s32k1xx_lpspi_writebyte * * Description: @@ -511,14 +531,16 @@ static inline uint8_t s32k1xx_lpspi_readbyte(FAR struct s32k1xx_lpspidev_s *priv * Returned Value: * None * - ************************************************************************************/ + ****************************************************************************/ -static inline void s32k1xx_lpspi_writebyte(FAR struct s32k1xx_lpspidev_s *priv, - uint8_t byte) +static inline +void s32k1xx_lpspi_writebyte(FAR struct s32k1xx_lpspidev_s *priv, + uint8_t byte) { /* Wait until the transmit buffer is empty */ - while ((s32k1xx_lpspi_getreg32(priv, S32K1XX_LPSPI_SR_OFFSET) & LPSPI_SR_TDF) == 0) + while ((s32k1xx_lpspi_getreg32(priv, S32K1XX_LPSPI_SR_OFFSET) & + LPSPI_SR_TDF) == 0) { } @@ -527,7 +549,7 @@ static inline void s32k1xx_lpspi_writebyte(FAR struct s32k1xx_lpspidev_s *priv, s32k1xx_lpspi_putreg8(priv, S32K1XX_LPSPI_TDR_OFFSET, byte); } -/************************************************************************************ +/**************************************************************************** * Name: s32k1xx_lpspi_9to16bitmode * * Description: @@ -539,9 +561,10 @@ static inline void s32k1xx_lpspi_writebyte(FAR struct s32k1xx_lpspidev_s *priv, * Returned Value: * true: >8 bit mode-bit mode, false: <= 8-bit mode * - ************************************************************************************/ + ****************************************************************************/ -static inline bool s32k1xx_lpspi_9to16bitmode(FAR struct s32k1xx_lpspidev_s *priv) +static inline +bool s32k1xx_lpspi_9to16bitmode(FAR struct s32k1xx_lpspidev_s *priv) { bool ret; @@ -558,7 +581,7 @@ static inline bool s32k1xx_lpspi_9to16bitmode(FAR struct s32k1xx_lpspidev_s *pri return ret; } -/************************************************************************************ +/**************************************************************************** * Name: s32k1xx_lpspi_modifyreg * * Description: @@ -573,7 +596,7 @@ static inline bool s32k1xx_lpspi_9to16bitmode(FAR struct s32k1xx_lpspidev_s *pri * Returned Value: * None * - ************************************************************************************/ + ****************************************************************************/ static void s32k1xx_lpspi_modifyreg32(FAR struct s32k1xx_lpspidev_s *priv, uint8_t offset, uint32_t clrbits, @@ -582,7 +605,7 @@ static void s32k1xx_lpspi_modifyreg32(FAR struct s32k1xx_lpspidev_s *priv, modifyreg32(priv->spibase + offset, clrbits, setbits); } -/************************************************************************************ +/**************************************************************************** * Name: s32k1xx_lpspi_pckfreq * * Description: @@ -592,9 +615,10 @@ static void s32k1xx_lpspi_modifyreg32(FAR struct s32k1xx_lpspidev_s *priv, * base - The base address of the LPSPI peripheral registers * * Returned Value: - * The frequency of the LPSPI functional input frequency (or zero on a failure) + * The frequency of the LPSPI functional input frequency + * (or zero on a failure) * - ************************************************************************************/ + ****************************************************************************/ static uint32_t s32k1xx_lpspi_pckfreq(uintptr_t base) { @@ -640,7 +664,7 @@ static uint32_t s32k1xx_lpspi_pckfreq(uintptr_t base) return pccclk; } -/************************************************************************************ +/**************************************************************************** * Name: s32k1xx_lpspi_set_delays * * Description: @@ -654,7 +678,7 @@ static uint32_t s32k1xx_lpspi_pckfreq(uintptr_t base) * Returned Value: * None * - ************************************************************************************/ + ****************************************************************************/ static inline void s32k1xx_lpspi_set_delay_scaler(FAR struct s32k1xx_lpspidev_s *priv, @@ -678,15 +702,16 @@ static inline void s32k1xx_lpspi_set_delay_scaler(FAR struct break; case LPSPI_BETWEEN_TRANSFER: - s32k1xx_lpspi_modifyreg32(priv, S32K1XX_LPSPI_CCR_OFFSET, LPSPI_CCR_DBT_MASK, - 0); + s32k1xx_lpspi_modifyreg32(priv, S32K1XX_LPSPI_CCR_OFFSET, + LPSPI_CCR_DBT_MASK, + 0); s32k1xx_lpspi_modifyreg32(priv, S32K1XX_LPSPI_CCR_OFFSET, 0, LPSPI_CCR_DBT(scaler)); break; } } -/************************************************************************************ +/**************************************************************************** * Name: s32k1xx_lpspi_set_delays * * Description: @@ -700,11 +725,12 @@ static inline void s32k1xx_lpspi_set_delay_scaler(FAR struct * Returned Value: * None * - ************************************************************************************/ + ****************************************************************************/ -static inline void s32k1xx_lpspi_set_delays(FAR struct s32k1xx_lpspidev_s *priv, - uint32_t delay_ns, - enum s32k1xx_delay_e type) +static inline +void s32k1xx_lpspi_set_delays(FAR struct s32k1xx_lpspidev_s *priv, + uint32_t delay_ns, + enum s32k1xx_delay_e type) { uint32_t inclock; uint64_t real_delay; @@ -725,7 +751,8 @@ static inline void s32k1xx_lpspi_set_delays(FAR struct s32k1xx_lpspidev_s *priv, /* Get the pre-scaled input clock */ clock_div_prescaler = inclock / - (1 << ((s32k1xx_lpspi_getreg32(priv, S32K1XX_LPSPI_TCR_OFFSET) & + (1 << ((s32k1xx_lpspi_getreg32(priv, + S32K1XX_LPSPI_TCR_OFFSET) & LPSPI_TCR_PRESCALE_MASK) >> LPSPI_TCR_PRESCALE_SHIFT)); min_diff = 0xffffffff; @@ -736,10 +763,10 @@ static inline void s32k1xx_lpspi_set_delays(FAR struct s32k1xx_lpspidev_s *priv, if (type == LPSPI_BETWEEN_TRANSFER) { - /* First calculate the initial, default delay, note min delay is 2 clock - * cycles. Due to large size of * calculated values (uint64_t), we need - * to break up the calculation into several steps to ensure * accurate - * calculated results + /* First calculate the initial, default delay, note min delay is 2 + * clock cycles. Due to large size of * calculated values (uint64_t), + * we need to break up the calculation into several steps to ensure + * accurate calculated results */ initial_delay_ns = 1000000000U; @@ -796,18 +823,18 @@ static inline void s32k1xx_lpspi_set_delays(FAR struct s32k1xx_lpspidev_s *priv, for (scaler = 0; (scaler < 256) && min_diff; scaler++) { /* Calculate the real delay value as we cycle through the scaler - * values. Due to large size of calculated values (uint64_t), we need - * to break up the calculation into several steps to ensure accurate - * calculated results + * values. Due to large size of calculated values (uint64_t), + * we need to break up the calculation into several steps to ensure + * accurate calculated results */ real_delay = 1000000000U; real_delay *= (scaler + 1 + additional_scaler); real_delay /= clock_div_prescaler; - /* calculate the delay difference based on the conditional statement - * that states that the calculated delay must not be less then the - * desired delay + /* calculate the delay difference based on the conditional + * statement that states that the calculated delay must not be less + * then the desired delay */ if (real_delay >= delay_ns) @@ -828,7 +855,7 @@ static inline void s32k1xx_lpspi_set_delays(FAR struct s32k1xx_lpspidev_s *priv, } } -/************************************************************************************ +/**************************************************************************** * Name: s32k1xx_lpspi_lock * * Description: @@ -847,7 +874,7 @@ static inline void s32k1xx_lpspi_set_delays(FAR struct s32k1xx_lpspidev_s *priv, * Returned Value: * None * - ************************************************************************************/ + ****************************************************************************/ static int s32k1xx_lpspi_lock(FAR struct spi_dev_s *dev, bool lock) { @@ -866,7 +893,7 @@ static int s32k1xx_lpspi_lock(FAR struct spi_dev_s *dev, bool lock) return ret; } -/************************************************************************************ +/**************************************************************************** * Name: s32k1xx_lpspi_setfrequency * * Description: @@ -879,7 +906,7 @@ static int s32k1xx_lpspi_lock(FAR struct spi_dev_s *dev, bool lock) * Returned Value: * Returns the actual frequency selected * - ************************************************************************************/ + ****************************************************************************/ static uint32_t s32k1xx_lpspi_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency) @@ -904,10 +931,12 @@ static uint32_t s32k1xx_lpspi_setfrequency(FAR struct spi_dev_s *dev, { /* Disable LPSPI if it is enabled */ - men = s32k1xx_lpspi_getreg32(priv, S32K1XX_LPSPI_CR_OFFSET) & LPSPI_CR_MEN; + men = s32k1xx_lpspi_getreg32(priv, S32K1XX_LPSPI_CR_OFFSET) & + LPSPI_CR_MEN; if (men) { - s32k1xx_lpspi_modifyreg32(priv, S32K1XX_LPSPI_CR_OFFSET, LPSPI_CR_MEN, 0); + s32k1xx_lpspi_modifyreg32(priv, S32K1XX_LPSPI_CR_OFFSET, + LPSPI_CR_MEN, 0); } /* Get the frequency of the LPSPI functional input clock */ @@ -980,7 +1009,7 @@ static uint32_t s32k1xx_lpspi_setfrequency(FAR struct spi_dev_s *dev, return priv->actual; } -/************************************************************************************ +/**************************************************************************** * Name: s32k1xx_lpspi_setmode * * Description: @@ -993,9 +1022,10 @@ static uint32_t s32k1xx_lpspi_setfrequency(FAR struct spi_dev_s *dev, * Returned Value: * Returns the actual frequency selected * - ************************************************************************************/ + ****************************************************************************/ -static void s32k1xx_lpspi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode) +static void s32k1xx_lpspi_setmode(FAR struct spi_dev_s *dev, + enum spi_mode_e mode) { FAR struct s32k1xx_lpspidev_s *priv = (FAR struct s32k1xx_lpspidev_s *)dev; uint32_t setbits; @@ -1010,10 +1040,12 @@ static void s32k1xx_lpspi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mod { /* Disable LPSPI if it is enabled */ - men = s32k1xx_lpspi_getreg32(priv, S32K1XX_LPSPI_CR_OFFSET) & LPSPI_CR_MEN; + men = s32k1xx_lpspi_getreg32(priv, S32K1XX_LPSPI_CR_OFFSET) & + LPSPI_CR_MEN; if (men) { - s32k1xx_lpspi_modifyreg32(priv, S32K1XX_LPSPI_CR_OFFSET, LPSPI_CR_MEN, 0); + s32k1xx_lpspi_modifyreg32(priv, S32K1XX_LPSPI_CR_OFFSET, + LPSPI_CR_MEN, 0); } switch (mode) @@ -1042,7 +1074,8 @@ static void s32k1xx_lpspi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mod return; } - s32k1xx_lpspi_modifyreg32(priv, S32K1XX_LPSPI_TCR_OFFSET, clrbits, setbits); + s32k1xx_lpspi_modifyreg32(priv, S32K1XX_LPSPI_TCR_OFFSET, + clrbits, setbits); while ((s32k1xx_lpspi_getreg32(priv, S32K1XX_LPSPI_RSR_OFFSET) & LPSPI_RSR_RXEMPTY) != LPSPI_RSR_RXEMPTY) @@ -1060,12 +1093,13 @@ static void s32k1xx_lpspi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mod if (men) { - s32k1xx_lpspi_modifyreg32(priv, S32K1XX_LPSPI_CR_OFFSET, 0, LPSPI_CR_MEN); + s32k1xx_lpspi_modifyreg32(priv, S32K1XX_LPSPI_CR_OFFSET, + 0, LPSPI_CR_MEN); } } } -/************************************************************************************ +/**************************************************************************** * Name: s32k1xx_lpspi_setbits * * Description: @@ -1078,7 +1112,7 @@ static void s32k1xx_lpspi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mod * Returned Value: * None * - ************************************************************************************/ + ****************************************************************************/ static void s32k1xx_lpspi_setbits(FAR struct spi_dev_s *dev, int nbits) { @@ -1099,10 +1133,12 @@ static void s32k1xx_lpspi_setbits(FAR struct spi_dev_s *dev, int nbits) /* Disable LPSPI if it is enabled */ - men = s32k1xx_lpspi_getreg32(priv, S32K1XX_LPSPI_CR_OFFSET) & LPSPI_CR_MEN; + men = s32k1xx_lpspi_getreg32(priv, S32K1XX_LPSPI_CR_OFFSET) & + LPSPI_CR_MEN; if (men) { - s32k1xx_lpspi_modifyreg32(priv, S32K1XX_LPSPI_CR_OFFSET, LPSPI_CR_MEN, 0); + s32k1xx_lpspi_modifyreg32(priv, S32K1XX_LPSPI_CR_OFFSET, + LPSPI_CR_MEN, 0); } regval = s32k1xx_lpspi_getreg32(priv, S32K1XX_LPSPI_TCR_OFFSET); @@ -1111,7 +1147,9 @@ static void s32k1xx_lpspi_setbits(FAR struct spi_dev_s *dev, int nbits) s32k1xx_lpspi_putreg32(priv, S32K1XX_LPSPI_TCR_OFFSET, regval); - /* Save the selection so that subsequent re-configurations will be faster. */ + /* Save the selection so that subsequent re-configurations will + * be faster. + */ priv->nbits = nbits; @@ -1119,12 +1157,13 @@ static void s32k1xx_lpspi_setbits(FAR struct spi_dev_s *dev, int nbits) if (men) { - s32k1xx_lpspi_modifyreg32(priv, S32K1XX_LPSPI_CR_OFFSET, 0, LPSPI_CR_MEN); + s32k1xx_lpspi_modifyreg32(priv, S32K1XX_LPSPI_CR_OFFSET, + 0, LPSPI_CR_MEN); } } } -/************************************************************************************ +/**************************************************************************** * Name: s32k1xx_lpspi_hwfeatures * * Description: @@ -1138,7 +1177,7 @@ static void s32k1xx_lpspi_setbits(FAR struct spi_dev_s *dev, int nbits) * Zero (OK) if the selected H/W features are enabled; A negated errno * value if any H/W feature is not supportable. * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_SPI_HWFEATURES static int s32k1xx_lpspi_hwfeatures(FAR struct spi_dev_s *dev, @@ -1164,7 +1203,8 @@ static int s32k1xx_lpspi_hwfeatures(FAR struct spi_dev_s *dev, clrbits = LPSPI_TCR_LSBF; } - s32k1xx_lpspi_modifyreg32(priv, S32K1XX_LPSPI_TCR_OFFSET, clrbits, setbits); + s32k1xx_lpspi_modifyreg32(priv, S32K1XX_LPSPI_TCR_OFFSET, + clrbits, setbits); /* Other H/W features are not supported */ @@ -1175,7 +1215,7 @@ static int s32k1xx_lpspi_hwfeatures(FAR struct spi_dev_s *dev, } #endif -/************************************************************************************ +/**************************************************************************** * Name: s32k1xx_lpspi_send * * Description: @@ -1189,7 +1229,7 @@ static int s32k1xx_lpspi_hwfeatures(FAR struct spi_dev_s *dev, * Returned Value: * response * - ************************************************************************************/ + ****************************************************************************/ static uint32_t s32k1xx_lpspi_send(FAR struct spi_dev_s *dev, uint32_t wd) { @@ -1201,8 +1241,8 @@ static uint32_t s32k1xx_lpspi_send(FAR struct spi_dev_s *dev, uint32_t wd) s32k1xx_lpspi_writeword(priv, wd); - while ((s32k1xx_lpspi_getreg32(priv, S32K1XX_LPSPI_SR_OFFSET) & LPSPI_SR_RDF) != - LPSPI_SR_RDF); + while ((s32k1xx_lpspi_getreg32(priv, S32K1XX_LPSPI_SR_OFFSET) & + LPSPI_SR_RDF) != LPSPI_SR_RDF); ret = s32k1xx_lpspi_readword(priv); @@ -1219,7 +1259,7 @@ static uint32_t s32k1xx_lpspi_send(FAR struct spi_dev_s *dev, uint32_t wd) return ret; } -/************************************************************************************ +/**************************************************************************** * Name: s32k1xx_lpspi_exchange (no DMA). aka s32k1xx_lpspi_exchange_nodma * * Description: @@ -1238,12 +1278,13 @@ static uint32_t s32k1xx_lpspi_send(FAR struct spi_dev_s *dev, uint32_t wd) * Returned Value: * None * - ************************************************************************************/ + ****************************************************************************/ #if !defined(CONFIG_S32K1XX_LPSPI_DMA) || defined(CONFIG_S32K1XX_DMACAPABLE) #if !defined(CONFIG_S32K1XX_LPSPI_DMA) static void s32k1xx_lpspi_exchange(FAR struct spi_dev_s *dev, - FAR const void *txbuffer, FAR void *rxbuffer, + FAR const void *txbuffer, + FAR void *rxbuffer, size_t nwords) #else static void s32k1xx_lpspi_exchange_nodma(FAR struct spi_dev_s *dev, @@ -1327,7 +1368,7 @@ static void s32k1xx_lpspi_exchange_nodma(FAR struct spi_dev_s *dev, } #endif /* !CONFIG_S32K1XX_LPSPI_DMA || CONFIG_S32K1XX_DMACAPABLE */ -/************************************************************************************ +/**************************************************************************** * Name: s32k1xx_lpspi_sndblock * * Description: @@ -1336,16 +1377,16 @@ static void s32k1xx_lpspi_exchange_nodma(FAR struct spi_dev_s *dev, * Input Parameters: * dev - Device-specific state data * txbuffer - A pointer to the buffer of data to be sent - * nwords - the length of data to send from the buffer in number of words. - * The wordsize is determined by the number of bits-per-word - * selected for the SPI interface. If nbits <= 8, the data is - * packed into uint8_t's; if nbits >8, the data is packed into - * uint16_t's + * nwords - the length of data to send from the buffer in number of + * words. The wordsize is determined by the number of + * bits-per-word selected for the SPI interface. If nbits <= 8, + * the data is packed into uint8_t's; if nbits >8, the data is + * packed into uint16_t's * * Returned Value: * None * - ************************************************************************************/ + ****************************************************************************/ #ifndef CONFIG_SPI_EXCHANGE static void s32k1xx_lpspi_sndblock(FAR struct spi_dev_s *dev, @@ -1356,7 +1397,7 @@ static void s32k1xx_lpspi_sndblock(FAR struct spi_dev_s *dev, } #endif -/************************************************************************************ +/**************************************************************************** * Name: s32k1xx_lpspi_recvblock * * Description: @@ -1365,19 +1406,20 @@ static void s32k1xx_lpspi_sndblock(FAR struct spi_dev_s *dev, * Input Parameters: * dev - Device-specific state data * rxbuffer - A pointer to the buffer in which to receive data - * nwords - the length of data that can be received in the buffer in number - * of words. The wordsize is determined by the number of bits-per-word - * selected for the SPI interface. If nbits <= 8, the data is - * packed into uint8_t's; if nbits >8, the data is packed into - * uint16_t's + * nwords - the length of data that can be received in the buffer in + * number of words. The wordsize is determined by the number + * of bits-per-word selected for the SPI interface. If + * nbits <= 8, the data is packed into uint8_t's; if nbits >8, + * the data is packed into uint16_t's * * Returned Value: * None * - ************************************************************************************/ + ****************************************************************************/ #ifndef CONFIG_SPI_EXCHANGE -static void s32k1xx_lpspi_recvblock(FAR struct spi_dev_s *dev, FAR void *rxbuffer, +static void s32k1xx_lpspi_recvblock(FAR struct spi_dev_s *dev, + FAR void *rxbuffer, size_t nwords) { spiinfo("rxbuffer=%p nwords=%d\n", rxbuffer, nwords); @@ -1385,12 +1427,12 @@ static void s32k1xx_lpspi_recvblock(FAR struct spi_dev_s *dev, FAR void *rxbuffe } #endif -/************************************************************************************ +/**************************************************************************** * Name: s32k1xx_lpspi_bus_initialize * * Description: - * Initialize the selected SPI bus in its default state (Master, 8-bit, mode 0, - * etc.) + * Initialize the selected SPI bus in its default state (Master, 8-bit, + * mode 0, etc.) * * Input Parameters: * priv - private SPI device structure @@ -1398,14 +1440,15 @@ static void s32k1xx_lpspi_recvblock(FAR struct spi_dev_s *dev, FAR void *rxbuffe * Returned Value: * None * - ************************************************************************************/ + ****************************************************************************/ static void s32k1xx_lpspi_bus_initialize(struct s32k1xx_lpspidev_s *priv) { uint32_t reg = 0; - /* NOTE: Clocking to the LPSPI peripheral must be provided by board-specific logic - * as part of the clock configuration logic. + /* NOTE: + * Clocking to the LPSPI peripheral must be provided by board-specific + * logic as part of the clock configuration logic. */ /* Reset to known status */ @@ -1427,7 +1470,8 @@ static void s32k1xx_lpspi_bus_initialize(struct s32k1xx_lpspidev_s *priv) /* Set Configuration Register 1 related setting. */ reg = s32k1xx_lpspi_getreg32(priv, S32K1XX_LPSPI_CFGR1_OFFSET); - reg &= ~(LPSPI_CFGR1_OUTCFG | LPSPI_CFGR1_PINCFG_MASK | LPSPI_CFGR1_NOSTALL); + reg &= ~(LPSPI_CFGR1_OUTCFG | + LPSPI_CFGR1_PINCFG_MASK | LPSPI_CFGR1_NOSTALL); reg |= LPSPI_CFGR1_OUTCFG_RETAIN | LPSPI_CFGR1_PINCFG_SIN_SOUT; s32k1xx_lpspi_putreg32(priv, S32K1XX_LPSPI_CFGR1_OFFSET, reg); @@ -1455,11 +1499,11 @@ static void s32k1xx_lpspi_bus_initialize(struct s32k1xx_lpspidev_s *priv) s32k1xx_lpspi_modifyreg32(priv, S32K1XX_LPSPI_CR_OFFSET, 0, LPSPI_CR_MEN); } -/************************************************************************************ +/**************************************************************************** * Public Functions - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Name: s32k1xx_lpspibus_initialize * * Description: @@ -1471,7 +1515,7 @@ static void s32k1xx_lpspi_bus_initialize(struct s32k1xx_lpspidev_s *priv) * Returned Value: * Valid SPI device structure reference on success; a NULL on failure * - ************************************************************************************/ + ****************************************************************************/ FAR struct spi_dev_s *s32k1xx_lpspibus_initialize(int bus) { diff --git a/arch/arm/src/s32k1xx/s32k1xx_lpspi.h b/arch/arm/src/s32k1xx/s32k1xx_lpspi.h index 1f378b55dad..257e89dd471 100644 --- a/arch/arm/src/s32k1xx/s32k1xx_lpspi.h +++ b/arch/arm/src/s32k1xx/s32k1xx_lpspi.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/s32k1xx/s32k1xx_lpspi.h * * Copyright (C) 2019 Gregory Nutt. All rights reserved. @@ -31,14 +31,14 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_S32K1XX_S32K1XX_LPSPI_H #define __ARCH_ARM_SRC_S32K1XX_S32K1XX_LPSPI_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include @@ -49,9 +49,9 @@ #include "chip.h" #include "hardware/s32k1xx_lpspi.h" -/************************************************************************************ - * Public Functions - ************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #ifndef __ASSEMBLY__ @@ -66,7 +66,7 @@ extern "C" struct spi_dev_s; /* Forward reference */ -/************************************************************************************ +/**************************************************************************** * Name: s32k1xx_lpspibus_initialize * * Description: @@ -78,67 +78,74 @@ struct spi_dev_s; /* Forward reference */ * Returned Value: * Valid SPI device structure reference on success; a NULL on failure * - ************************************************************************************/ + ****************************************************************************/ FAR struct spi_dev_s *s32k1xx_lpspibus_initialize(int bus); -/************************************************************************************ +/**************************************************************************** * Name: s32k1xx_lpspi0/1/2/select and s32k1xx_lpspi0/1/2/status * * Description: - * The external functions, s32k1xx_lpspi001/2/select, s32k1xx_lpspi0/1/2/status, - * and s32k1xx_lpspi0/1/2/cmddata must be provided by board-specific logic. - * These are implementations of the select, status, and cmddata methods of the SPI - * interface defined by struct spi_ops_s (see include/nuttx/spi/spi.h). All other - * methods (including s32k1xx_lpspibus_initialize()) are provided by common + * The external functions, s32k1xx_lpspi001/2/select, + * s32k1xx_lpspi0/1/2/status, and s32k1xx_lpspi0/1/2/cmddata must be + * provided by board-specific logic. These are implementations of the + * select, status, and cmddata methods of the SPI interface defined by + * struct spi_ops_s (see include/nuttx/spi/spi.h). All other methods + * (including s32k1xx_lpspibus_initialize()) are provided by common * S32K1XX logic. To use this common SPI logic on your board: * - * 1. Provide logic in s32k1xx_boardinitialize() to configure SPI chip select - * pins. + * 1. Provide logic in s32k1xx_boardinitialize() to configure SPI chip + * select pins. * 2. Provide s32k1xx_lpspi0/1/2/select() and s32k1xx_lpspi0/1/2/status() - * functions in your board-specific logic. These functions will perform chip - * selection and status operations using GPIOs in the way your board is - * configured. - * 3. If CONFIG_SPI_CMDDATA is defined in your NuttX configuration file, then - * provide s32k1xx_lpspi0/1/2/cmddata() functions in your board-specific logic. - * These functions will perform cmd/data selection operations using GPIOs in - * the way your board is configured. - * 4. Add a calls to s32k1xx_lpspibus_initialize() in your low level application - * initialization logic - * 5. The handle returned by s32k1xx_lpspibus_initialize() may then be used to - * bind the SPI driver to higher level logic (e.g., calling + * functions in your board-specific logic. These functions will + * perform chip selection and status operations using GPIOs in the way + * your board is configured. + * 3. If CONFIG_SPI_CMDDATA is defined in your NuttX configuration file, + * then provide s32k1xx_lpspi0/1/2/cmddata() functions in your + * board-specific logic. These functions will perform cmd/data selection + * operations using GPIOs in the way your board is configured. + * 4. Add a calls to s32k1xx_lpspibus_initialize() in your low level + * application initialization logic + * 5. The handle returned by s32k1xx_lpspibus_initialize() may then be + * used to bind the SPI driver to higher level logic (e.g., calling * mmcsd_spislotinitialize(), for example, will bind the SPI driver to * the SPI MMC/SD driver). * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_S32K1XX_LPSPI0 -void s32k1xx_lpspi0select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected); +void s32k1xx_lpspi0select(FAR struct spi_dev_s *dev, + uint32_t devid, bool selected); uint8_t s32k1xx_lpspi0status(FAR struct spi_dev_s *dev, uint32_t devid); -int s32k1xx_lpspi0cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd); +int s32k1xx_lpspi0cmddata(FAR struct spi_dev_s *dev, + uint32_t devid, bool cmd); #endif #ifdef CONFIG_S32K1XX_LPSPI1 -void s32k1xx_lpspi1select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected); +void s32k1xx_lpspi1select(FAR struct spi_dev_s *dev, + uint32_t devid, bool selected); uint8_t s32k1xx_lpspi1status(FAR struct spi_dev_s *dev, uint32_t devid); -int s32k1xx_lpspi1cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd); +int s32k1xx_lpspi1cmddata(FAR struct spi_dev_s *dev, + uint32_t devid, bool cmd); #endif #ifdef CONFIG_S32K1XX_LPSPI2 -void s32k1xx_lpspi2select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected); +void s32k1xx_lpspi2select(FAR struct spi_dev_s *dev, + uint32_t devid, bool selected); uint8_t s32k1xx_lpspi2status(FAR struct spi_dev_s *dev, uint32_t devid); -int s32k1xx_lpspi2cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd); +int s32k1xx_lpspi2cmddata(FAR struct spi_dev_s *dev, + uint32_t devid, bool cmd); #endif -/************************************************************************************ +/**************************************************************************** * Name: s32k1xx_lpspi0/1/2/register * * Description: - * If the board supports a card detect callback to inform the SPI-based MMC/SD - * driver when an SD card is inserted or removed, then CONFIG_SPI_CALLBACK should - * be defined and the following function(s) must be implemented. These functions - * implements the registercallback method of the SPI interface (see - * include/nuttx/spi/spi.h for details) + * If the board supports a card detect callback to inform the SPI-based + * MMC/SD driver when an SD card is inserted or removed, then + * CONFIG_SPI_CALLBACK should be defined and the following function(s) + * must be implemented. These functions implements the registercallback + * method of the SPI interface (see include/nuttx/spi/spi.h for details) * * Input Parameters: * dev - Device-specific state data @@ -152,18 +159,21 @@ int s32k1xx_lpspi2cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd); #ifdef CONFIG_SPI_CALLBACK #ifdef CONFIG_S32K1XX_LPSPI0 -int s32k1xx_lpspi0register(FAR struct spi_dev_s *dev, spi_mediachange_t callback, - FAR void *arg); +int s32k1xx_lpspi0register(FAR struct spi_dev_s *dev, + spi_mediachange_t callback, + FAR void *arg); #endif #ifdef CONFIG_S32K1XX_LPSPI1 -int s32k1xx_lpspi1register(FAR struct spi_dev_s *dev, spi_mediachange_t callback, - FAR void *arg); +int s32k1xx_lpspi1register(FAR struct spi_dev_s *dev, + spi_mediachange_t callback, + FAR void *arg); #endif #ifdef CONFIG_S32K1XX_LPSPI2 -int s32k1xx_lpspi2register(FAR struct spi_dev_s *dev, spi_mediachange_t callback, - FAR void *arg); +int s32k1xx_lpspi2register(FAR struct spi_dev_s *dev, + spi_mediachange_t callback, + FAR void *arg); #endif #endif diff --git a/arch/arm/src/s32k1xx/s32k1xx_periphclocks.c b/arch/arm/src/s32k1xx/s32k1xx_periphclocks.c index cfb623e84aa..c05b61896d2 100644 --- a/arch/arm/src/s32k1xx/s32k1xx_periphclocks.c +++ b/arch/arm/src/s32k1xx/s32k1xx_periphclocks.c @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/s32k1xx/s32k1xx_periphclocks.c * * Copyright (C) 2019 Gregory Nutt. All rights reserved. @@ -50,11 +50,11 @@ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF * THE POSSIBILITY OF SUCH DAMAGE. * - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include @@ -68,11 +68,11 @@ #include "s32k1xx_clockconfig.h" #include "s32k1xx_periphclocks.h" -/************************************************************************************ +/**************************************************************************** * Private Functions - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Name: s32k1xx_get_pclkctrl * * Description: @@ -86,11 +86,13 @@ * Address of peripheral control register. NULL is returned if the clock * name does not map to a PCC control register. * - ************************************************************************************/ + ****************************************************************************/ static uint32_t *s32k1xx_get_pclkctrl(enum clock_names_e clkname) { - /* Map the clock name to an index to the corresponding PCC control register. */ + /* Map the clock name to an index to the corresponding PCC control + * register. + */ uintptr_t index = (uintptr_t)g_clkname_mapping[clkname]; @@ -104,7 +106,7 @@ static uint32_t *s32k1xx_get_pclkctrl(enum clock_names_e clkname) return NULL; } -/************************************************************************************ +/**************************************************************************** * Name: s32k1xx_pclk_disable * * Description: @@ -117,7 +119,7 @@ static uint32_t *s32k1xx_get_pclkctrl(enum clock_names_e clkname) * Returned Value: * None * - ************************************************************************************/ + ****************************************************************************/ static void s32k1xx_pclk_disable(enum clock_names_e clkname) { @@ -127,7 +129,7 @@ static void s32k1xx_pclk_disable(enum clock_names_e clkname) *ctrlp &= ~PCC_CGC; } -/************************************************************************************ +/**************************************************************************** * Name: s32k1xx_set_pclkctrl * * Description: @@ -139,7 +141,7 @@ static void s32k1xx_pclk_disable(enum clock_names_e clkname) * Returned Value: * None * - ************************************************************************************/ + ****************************************************************************/ static inline void s32k1xx_set_pclkctrl(const struct peripheral_clock_config_s *pclk) @@ -173,7 +175,7 @@ s32k1xx_set_pclkctrl(const struct peripheral_clock_config_s *pclk) *ctrlp = regval; } -/************************************************************************************ +/**************************************************************************** * Name: s32k1xx_get_pclkfreq_divided * * Description: @@ -186,10 +188,11 @@ s32k1xx_set_pclkctrl(const struct peripheral_clock_config_s *pclk) * Returned Value: * None * - ************************************************************************************/ + ****************************************************************************/ -static uint32_t s32k1xx_get_pclkfreq_divided(enum clock_names_e clkname, - enum scg_async_clock_type_e divider) +static uint32_t +s32k1xx_get_pclkfreq_divided(enum clock_names_e clkname, + enum scg_async_clock_type_e divider) { uint32_t *ctrlp; uint32_t frequency = 0; @@ -246,11 +249,11 @@ static uint32_t s32k1xx_get_pclkfreq_divided(enum clock_names_e clkname, return frequency; } -/************************************************************************************ +/**************************************************************************** * Public Functions - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Name: s32k1xx_periphclocks * * Description: @@ -263,7 +266,7 @@ static uint32_t s32k1xx_get_pclkfreq_divided(enum clock_names_e clkname, * Returned Value: * None * - ************************************************************************************/ + ****************************************************************************/ void s32k1xx_periphclocks(unsigned int count, const struct peripheral_clock_config_s *pclks) @@ -284,7 +287,7 @@ void s32k1xx_periphclocks(unsigned int count, } } -/************************************************************************************ +/**************************************************************************** * Name: s32k1xx_get_pclkfreq * * Description: @@ -301,7 +304,7 @@ void s32k1xx_periphclocks(unsigned int count, * any failure. -ENODEV is returned if the clock is not enabled or is not * being clocked. * - ************************************************************************************/ + ****************************************************************************/ int s32k1xx_get_pclkfreq(enum clock_names_e clkname, uint32_t *frequency) { @@ -323,7 +326,8 @@ int s32k1xx_get_pclkfreq(enum clock_names_e clkname, uint32_t *frequency) busclk = s32k1xx_get_sysclk(SCG_SYSTEM_CLOCK_BUS); ret = (busclk == 0) ? -ENODEV : OK; } - else if ((g_periph_features[clkname] & HAS_INT_CLOCK_FROM_SYS_CLOCK) != 0) + else if ((g_periph_features[clkname] & + HAS_INT_CLOCK_FROM_SYS_CLOCK) != 0) { uint32_t sysclk; @@ -332,7 +336,8 @@ int s32k1xx_get_pclkfreq(enum clock_names_e clkname, uint32_t *frequency) sysclk = s32k1xx_get_sysclk(SCG_SYSTEM_CLOCK_CORE); ret = (sysclk == 0) ? -ENODEV : OK; } - else if ((g_periph_features[clkname] & HAS_INT_CLOCK_FROM_SLOW_CLOCK) != 0) + else if ((g_periph_features[clkname] & + HAS_INT_CLOCK_FROM_SLOW_CLOCK) != 0) { uint32_t slowclk; @@ -354,21 +359,26 @@ int s32k1xx_get_pclkfreq(enum clock_names_e clkname, uint32_t *frequency) { /* Check whether peripheral has protocol clock (functional clock) */ - if ((g_periph_features[clkname] & (HAS_PROTOCOL_CLOCK_FROM_ASYNC1 | - HAS_PROTOCOL_CLOCK_FROM_ASYNC2)) != 0) + if ((g_periph_features[clkname] & + (HAS_PROTOCOL_CLOCK_FROM_ASYNC1 | + HAS_PROTOCOL_CLOCK_FROM_ASYNC2)) != 0) { - if ((g_periph_features[clkname] & HAS_PROTOCOL_CLOCK_FROM_ASYNC1) != 0) + if ((g_periph_features[clkname] & + HAS_PROTOCOL_CLOCK_FROM_ASYNC1) != 0) { /* Check whether the functional clock is clocked */ - freq = s32k1xx_get_pclkfreq_divided(clkname, SCG_ASYNC_CLOCK_DIV1); + freq = s32k1xx_get_pclkfreq_divided(clkname, + SCG_ASYNC_CLOCK_DIV1); } - if ((g_periph_features[clkname] & HAS_PROTOCOL_CLOCK_FROM_ASYNC2) != 0) + if ((g_periph_features[clkname] & + HAS_PROTOCOL_CLOCK_FROM_ASYNC2) != 0) { /* Check whether the functional clock is clocked */ - freq = s32k1xx_get_pclkfreq_divided(clkname, SCG_ASYNC_CLOCK_DIV2); + freq = s32k1xx_get_pclkfreq_divided(clkname, + SCG_ASYNC_CLOCK_DIV2); } if (freq == 0) diff --git a/arch/arm/src/s32k1xx/s32k1xx_periphclocks.h b/arch/arm/src/s32k1xx/s32k1xx_periphclocks.h index 07b137e7a13..028a99a6109 100644 --- a/arch/arm/src/s32k1xx/s32k1xx_periphclocks.h +++ b/arch/arm/src/s32k1xx/s32k1xx_periphclocks.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/s32k1xx/s32k1xx_periphclocks.h * * Copyright (C) 2019 Gregory Nutt. All rights reserved. @@ -50,14 +50,14 @@ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF * THE POSSIBILITY OF SUCH DAMAGE. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_S32K1XX_S32K1XX_PERIPHCLOCKS_H #define __ARCH_ARM_SRC_S32K1XX_S32K1XX_PERIPHCLOCKS_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include @@ -78,9 +78,9 @@ # include "s32k14x/s32k14x_clocknames.h" #endif -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ /* Values for peripheral_clock_source_t. An enumeration is not appropriate * because some of the values are duplicates. @@ -165,9 +165,9 @@ #define HAS_INT_CLOCK_FROM_SYS_CLOCK (1 << 6) /* Clock is provided by the sys clock */ #define HAS_INT_CLOCK_FROM_SLOW_CLOCK (1 << 7) /* Clock is provided by the slow clock */ -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ typedef uint8_t peripheral_clock_source_t; /* See CLK_SRC_* definitions */ @@ -179,8 +179,8 @@ enum peripheral_clock_frac_e struct peripheral_clock_config_s { - /* clkname is the name of the peripheral clock. It must be one of the values - * defined in the chip specific xxxxxx_configname.h header file. + /* clkname is the name of the peripheral clock. It must be one of the + * values defined in the chip specific xxxxxx_configname.h header file. */ enum clock_names_e clkname; /* Peripheral clock name */ @@ -192,9 +192,9 @@ struct peripheral_clock_config_s #ifndef __ASSEMBLY__ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ #undef EXTERN #if defined(__cplusplus) @@ -224,11 +224,11 @@ EXTERN const uint16_t g_clkname_mapping[]; EXTERN const uint8_t g_periph_features[]; -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Name: s32k1xx_periphclocks * * Description: @@ -241,7 +241,7 @@ EXTERN const uint8_t g_periph_features[]; * Returned Value: * None * - ************************************************************************************/ + ****************************************************************************/ void s32k1xx_periphclocks(unsigned int count, const struct peripheral_clock_config_s *pclks); diff --git a/arch/arm/src/s32k1xx/s32k1xx_pin.h b/arch/arm/src/s32k1xx/s32k1xx_pin.h index bea8978a62a..0cce8d10fe5 100644 --- a/arch/arm/src/s32k1xx/s32k1xx_pin.h +++ b/arch/arm/src/s32k1xx/s32k1xx_pin.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/s32k1xx/s32k1xx_pin.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,14 +16,14 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_S32K1XX_S32K1XX_PIN_H #define __ARCH_ARM_SRC_S32K1XX_S32K1XX_PIN_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include @@ -37,11 +37,11 @@ #include "arm_internal.h" #include "hardware/s32k1xx_port.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* Bit-encoded input to s32k1xx_pinconfig() *****************************************/ +/* Bit-encoded input to s32k1xx_pinconfig() *********************************/ /* General form (32-bits, only 22 bits are unused in the encoding): * @@ -86,8 +86,8 @@ #define _PIN_MODE_ALT6 (6 << _PIN_MODE_SHIFT) /* 110 Alternative 6 */ #define _PIN_MODE_ALT7 (7 << _PIN_MODE_SHIFT) /* 111 Alternative 7 */ -/* Options for all digital modes (Alternatives 1-7). None of the digital - * options apply if the analog mode is selected. +/* Options for all digital modes (Alternatives 1-7). + * None of the digital options apply if the analog mode is selected. */ #define _PIN_IO_MASK (1 << _PIN_OPTIONS_SHIFT) /* xxx1 Digital input/output mask */ @@ -102,9 +102,11 @@ # define _PIN_OUTPUT_LOWDRIVE (1 << _PIN_OPTIONS_SHIFT) /* 0xx1 Output with low drive strength */ # define _PIN_OUTPUT_HIGHDRIVE (9 << _PIN_OPTIONS_SHIFT) /* 1xx1 Output with high drive strength */ -/* End-user pin modes and configurations. Notes: (1) None of the digital options - * are available for the analog mode, (2) digital settings may be combined (OR'ed) - * provided that input-only and output-only options are not intermixed. +/* End-user pin modes and configurations. + * Notes: + * (1) None of the digital options are available for the analog mode, + * (2) digital settings may be combined (OR'ed) provided that input-only + * and output-only options are not intermixed. */ #define PIN_ANALOG _PIN_MODE_ANALOG @@ -276,15 +278,15 @@ #define PIN30 (30 << _PIN_SHIFT) #define PIN31 (31 << _PIN_SHIFT) -/************************************************************************************ +/**************************************************************************** * Inline Functions - ************************************************************************************/ + ****************************************************************************/ #ifndef __ASSEMBLY__ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ #undef EXTERN #if defined(__cplusplus) @@ -295,26 +297,27 @@ extern "C" #define EXTERN extern #endif -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Name: s32k1xx_pinconfig * * Description: * Configure a pin based on bit-encoded description of the pin. * - ************************************************************************************/ + ****************************************************************************/ int s32k1xx_pinconfig(uint32_t cfgset); -/************************************************************************************ +/**************************************************************************** * Name: s32k1xx_pinfilter * * Description: * Configure the digital filter associated with a port. The digital filter - * capabilities of the PORT module are available in all digital pin muxing modes. + * capabilities of the PORT module are available in all digital pin muxing + * modes. * * Input Parameters: * port - See S32K1XX_PORTn definitions in s32k1xx_port.h @@ -322,37 +325,38 @@ int s32k1xx_pinconfig(uint32_t cfgset); * false: Digital Filters are clocked by the 1 kHz LPO clock * width - Filter Length * - ************************************************************************************/ + ****************************************************************************/ int s32k1xx_pinfilter(unsigned int port, bool lpo, unsigned int width); -/************************************************************************************ +/**************************************************************************** * Name: s32k1xx_gpiowrite * * Description: * Write one or zero to the selected GPIO pin * - ************************************************************************************/ + ****************************************************************************/ void s32k1xx_gpiowrite(uint32_t pinset, bool value); -/************************************************************************************ +/**************************************************************************** * Name: s32k1xx_gpioread * * Description: * Read one or zero from the selected GPIO pin * - ************************************************************************************/ + ****************************************************************************/ bool s32k1xx_gpioread(uint32_t pinset); -/************************************************************************************ +/**************************************************************************** * Name: s32k1xx_pinirq_initialize * * Description: - * Initialize logic to support a second level of interrupt decoding for GPIO pins. + * Initialize logic to support a second level of interrupt decoding for + * GPIO pins. * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_S32K1XX_GPIOIRQ void s32k1xx_pinirq_initialize(void); @@ -360,37 +364,39 @@ void s32k1xx_pinirq_initialize(void); # define s32k1xx_pinirq_initialize() #endif -/************************************************************************************ +/**************************************************************************** * Name: s32k1xx_pinirqattach * * Description: * Attach a pin interrupt handler. The normal initialization sequence is: * - * 1. Call s32k1xx_pinconfig() to configure the interrupting pin (pin interrupts - * will be disabled. - * 2. Call s32k1xx_pinirqattach() to attach the pin interrupt handling function. + * 1. Call s32k1xx_pinconfig() to configure the interrupting pin + * (pin interrupts will be disabled. + * 2. Call s32k1xx_pinirqattach() to attach the pin interrupt handling + * function. * 3. Call s32k1xx_pinirqenable() to enable interrupts on the pin. * * Input Parameters: * pinset - Pin configuration * pinisr - Pin interrupt service routine - * arg - An argument that will be provided to the interrupt service routine. + * arg - An argument that will be provided to the interrupt service + * routine. * * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned on any - * failure to indicate the nature of the failure. + * Zero (OK) is returned on success; a negated errno value is returned on + * any failure to indicate the nature of the failure. * - ************************************************************************************/ + ****************************************************************************/ int s32k1xx_pinirqattach(uint32_t pinset, xcpt_t pinisr, void *arg); -/************************************************************************************ +/**************************************************************************** * Name: s32k1xx_pinirqenable * * Description: * Enable the interrupt for specified pin IRQ * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_S32K1XX_GPIOIRQ void s32k1xx_pinirqenable(uint32_t pinset); @@ -398,13 +404,13 @@ void s32k1xx_pinirqenable(uint32_t pinset); # define s32k1xx_pinirqenable(pinset) #endif -/************************************************************************************ +/**************************************************************************** * Name: s32k1xx_pinirqdisable * * Description: * Disable the interrupt for specified pin * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_S32K1XX_GPIOIRQ void s32k1xx_pinirqdisable(uint32_t pinset); @@ -412,37 +418,38 @@ void s32k1xx_pinirqdisable(uint32_t pinset); # define s32k1xx_pinirqdisable(pinset) #endif -/************************************************************************************ +/**************************************************************************** * Name: s32k1xx_pindmaenable * * Description: * Enable DMA for specified pin * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_S32K1XX_DMA void s32k1xx_pindmaenable(uint32_t pinset); #endif -/************************************************************************************ +/**************************************************************************** * Name: s32k1xx_pindmadisable * * Description: * Disable DMA for specified pin * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_S32K1XX_DMA void s32k1xx_pindmadisable(uint32_t pinset); #endif -/************************************************************************************ +/**************************************************************************** * Function: s32k1xx_pindump * * Description: - * Dump all GPIO registers associated with the base address of the provided pinset. + * Dump all GPIO registers associated with the base address of the provided + * pinset. * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_DEBUG_GPIO_INFO void s32k1xx_pindump(uint32_t pinset, const char *msg); diff --git a/arch/arm/src/s32k1xx/s32k1xx_pindma.c b/arch/arm/src/s32k1xx/s32k1xx_pindma.c index e27d4e68070..b43abee3795 100644 --- a/arch/arm/src/s32k1xx/s32k1xx_pindma.c +++ b/arch/arm/src/s32k1xx/s32k1xx_pindma.c @@ -42,13 +42,13 @@ * Public Functions ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Name: s32k1xx_pindmaenable * * Description: * Enable DMA for specified pin * - ************************************************************************************/ + ****************************************************************************/ void s32k1xx_pindmaenable(uint32_t pinset) { @@ -69,7 +69,9 @@ void s32k1xx_pindmaenable(uint32_t pinset) base = S32K1XX_PORT_BASE(port); - /* Modify the IRQC field of the port PCR register in order to enable DMA. */ + /* Modify the IRQC field of the port PCR register in order to + * enable DMA. + */ regval = getreg32(base + S32K1XX_PORT_PCR_OFFSET(pin)); regval &= ~PORT_PCR_IRQC_MASK; @@ -96,13 +98,13 @@ void s32k1xx_pindmaenable(uint32_t pinset) } } -/************************************************************************************ +/**************************************************************************** * Name: s32k1xx_pindmadisable * * Description: * Disable DMA for specified pin * - ************************************************************************************/ + ****************************************************************************/ void s32k1xx_pindmadisable(uint32_t pinset) { @@ -123,7 +125,9 @@ void s32k1xx_pindmadisable(uint32_t pinset) base = S32K1XX_PORT_BASE(port); - /* Clear the IRQC field of the port PCR register in order to disable DMA. */ + /* Clear the IRQC field of the port PCR register in order to + * disable DMA. + */ regval = getreg32(base + S32K1XX_PORT_PCR_OFFSET(pin)); regval &= ~PORT_PCR_IRQC_MASK; diff --git a/arch/arm/src/s32k1xx/s32k1xx_pingpio.c b/arch/arm/src/s32k1xx/s32k1xx_pingpio.c index 7096f60ab65..bb7224524d5 100644 --- a/arch/arm/src/s32k1xx/s32k1xx_pingpio.c +++ b/arch/arm/src/s32k1xx/s32k1xx_pingpio.c @@ -115,5 +115,6 @@ bool s32k1xx_gpioread(uint32_t pinset) regval = getreg32(base + S32K1XX_GPIO_PDIR_OFFSET); ret = ((regval & (1 << pin)) != 0); } + return ret; } diff --git a/arch/arm/src/s32k1xx/s32k1xx_progmem.c b/arch/arm/src/s32k1xx/s32k1xx_progmem.c index 91d8b760589..7b18ffcd104 100644 --- a/arch/arm/src/s32k1xx/s32k1xx_progmem.c +++ b/arch/arm/src/s32k1xx/s32k1xx_progmem.c @@ -1,4 +1,4 @@ -/****************************************************************************** +/**************************************************************************** * arch/arm/src/s32k1xx/s32k1xx_progmem.c * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,11 +16,11 @@ * License for the specific language governing permissions and limitations * under the License. * - ******************************************************************************/ + ****************************************************************************/ -/****************************************************************************** +/**************************************************************************** * Included Files - ******************************************************************************/ + ****************************************************************************/ #include @@ -39,17 +39,17 @@ #include /* Include last: has dependencies */ -/****************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ******************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_MTD_SMART # warning FlexNVM does not support back-to-back programming \ thus SmartFS willt not work #endif -/****************************************************************************** +/**************************************************************************** * Private Data - ******************************************************************************/ + ****************************************************************************/ union fccob_flash_addr { @@ -63,9 +63,9 @@ union fccob_flash_addr } fccobs; }; -/****************************************************************************** +/**************************************************************************** * Private Functions - ******************************************************************************/ + ****************************************************************************/ static inline void wait_ftfc_ready() { @@ -101,70 +101,71 @@ static uint32_t execute_ftfc_command() } } -/****************************************************************************** +/**************************************************************************** * Public Functions - ******************************************************************************/ + ****************************************************************************/ -/****************************************************************************** +/**************************************************************************** * Name: up_progmem_neraseblocks * * Description: * Return number of erase blocks * - ******************************************************************************/ + ****************************************************************************/ size_t up_progmem_neraseblocks(void) { return S32K1XX_PROGMEM_SECTOR_COUNT; } -/****************************************************************************** +/**************************************************************************** * Name: up_progmem_isuniform * * Description: * Is program memory uniform or page size differs? * - ******************************************************************************/ + ****************************************************************************/ bool up_progmem_isuniform(void) { return true; } -/****************************************************************************** +/**************************************************************************** * Name: up_progmem_pagesize * * Description: * Return read/write page size * - ******************************************************************************/ + ****************************************************************************/ size_t up_progmem_pagesize(size_t page) { return (size_t)S32K1XX_PROGMEM_PAGE_SIZE; } -/****************************************************************************** +/**************************************************************************** * Name: up_progmem_erasesize * * Description: * Return erase block size * - ******************************************************************************/ + ****************************************************************************/ size_t up_progmem_erasesize(size_t block) { return (size_t)S32K1XX_PROGMEM_BLOCK_SECTOR_SIZE; } -/****************************************************************************** +/**************************************************************************** * Name: up_progmem_getpage * * Description: * Address to read/write page conversion * * Input Parameters: - * addr - Address with or without flash offset (absolute or aligned to page0) + * addr - Address with or without flash offset (absolute or aligned to + * page0) * * Returned Value: * Page or negative value on error. The following errors are reported @@ -172,7 +173,7 @@ size_t up_progmem_erasesize(size_t block) * * -EFAULT: On invalid address * - ******************************************************************************/ + ****************************************************************************/ ssize_t up_progmem_getpage(size_t addr) { @@ -184,7 +185,7 @@ ssize_t up_progmem_getpage(size_t addr) return (size_t)(addr / S32K1XX_PROGMEM_PAGE_SIZE); } -/****************************************************************************** +/**************************************************************************** * Name: up_progmem_getaddress * * Description: @@ -196,7 +197,7 @@ ssize_t up_progmem_getpage(size_t addr) * Returned Value: * Base address of given page, SIZE_MAX if page index is not valid. * - ******************************************************************************/ + ****************************************************************************/ size_t up_progmem_getaddress(size_t page) { @@ -204,7 +205,7 @@ size_t up_progmem_getaddress(size_t page) + (page * S32K1XX_PROGMEM_PAGE_SIZE)); } -/****************************************************************************** +/**************************************************************************** * Name: up_progmem_eraseblock * * Description: @@ -214,8 +215,8 @@ size_t up_progmem_getaddress(size_t page) * block - The erase block index to be erased. * * Returned Value: - * block size or negative value on error. The following errors are reported - * (errno is not set!): + * block size or negative value on error. The following errors are + * reported (errno is not set!): * * -EFAULT: On invalid page * -EIO: On unsuccessful erase @@ -224,7 +225,7 @@ size_t up_progmem_getaddress(size_t page) * -EPERM: If operation is not permitted due to some other constraints * (i.e. some internal block is not running etc.) * - ******************************************************************************/ + ****************************************************************************/ ssize_t up_progmem_eraseblock(size_t block) { @@ -258,7 +259,7 @@ ssize_t up_progmem_eraseblock(size_t block) return (ssize_t)S32K1XX_PROGMEM_BLOCK_SECTOR_SIZE; } -/****************************************************************************** +/**************************************************************************** * Name: up_progmem_ispageerased * * Description: @@ -274,7 +275,7 @@ ssize_t up_progmem_eraseblock(size_t block) * The following errors are reported: * -EFAULT: On invalid page * - ******************************************************************************/ + ****************************************************************************/ ssize_t up_progmem_ispageerased(size_t page) { @@ -299,7 +300,7 @@ ssize_t up_progmem_ispageerased(size_t page) return (ssize_t)(S32K1XX_PROGMEM_PAGE_SIZE - i); } -/****************************************************************************** +/**************************************************************************** * Name: up_progmem_write * * Description: @@ -328,7 +329,7 @@ ssize_t up_progmem_ispageerased(size_t page) * EPERM: If operation is not permitted due to some other constraints * (i.e. some internal block is not running etc.) * - ******************************************************************************/ + ****************************************************************************/ ssize_t up_progmem_write(size_t addr, FAR const void *buf, size_t count) { diff --git a/arch/arm/src/s32k1xx/s32k1xx_progmem.h b/arch/arm/src/s32k1xx/s32k1xx_progmem.h index c0150af2434..07a914a3c55 100644 --- a/arch/arm/src/s32k1xx/s32k1xx_progmem.h +++ b/arch/arm/src/s32k1xx/s32k1xx_progmem.h @@ -1,4 +1,4 @@ -/****************************************************************************** +/**************************************************************************** * arch/arm/src/s32k1xx/s32k1xx_progmem.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,14 +16,14 @@ * License for the specific language governing permissions and limitations * under the License. * - ******************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_S32K1XX_PROGMEM_H #define __ARCH_ARM_SRC_S32K1XX_PROGMEM_H -/****************************************************************************** +/**************************************************************************** * Included Files - ******************************************************************************/ + ****************************************************************************/ #include #include @@ -35,9 +35,9 @@ #include "arm_internal.h" #include "s32k1xx_config.h" -/****************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ******************************************************************************/ + ****************************************************************************/ #define DFLASH_SIZE CONFIG_PROGMEM_SIZE @@ -71,9 +71,9 @@ #define S32K1XX_PROGMEM_DFLASH_WRITE_UNIT_SIZE 8 -/****************************************************************************** +/**************************************************************************** * Public Function Prototypes - ******************************************************************************/ + ****************************************************************************/ void s32k1xx_progmem_init(); diff --git a/arch/arm/src/s32k1xx/s32k1xx_pwm.c b/arch/arm/src/s32k1xx/s32k1xx_pwm.c index e8edb8cde66..b5785a0d23b 100644 --- a/arch/arm/src/s32k1xx/s32k1xx_pwm.c +++ b/arch/arm/src/s32k1xx/s32k1xx_pwm.c @@ -1,4 +1,4 @@ -/***************************************************************************** +/**************************************************************************** * arch/arm/src/s32k1xx/s32k1xx_pwm.c * * Copyright (C) 2013, 2016, 2017 Gregory Nutt. All rights reserved. @@ -34,11 +34,11 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - *****************************************************************************/ + ****************************************************************************/ -/***************************************************************************** +/**************************************************************************** * Included Files - *****************************************************************************/ + ****************************************************************************/ #include @@ -74,13 +74,13 @@ defined(CONFIG_S32K1XX_FTM4_PWM) || defined(CONFIG_S32K1XX_FTM5_PWM) || \ defined(CONFIG_S32K1XX_FTM6_PWM) || defined(CONFIG_S32K1XX_FTM7_PWM) -/***************************************************************************** +/**************************************************************************** * Pre-processor Definitions - *****************************************************************************/ + ****************************************************************************/ -/* PWM/Timer Definitions *****************************************************/ +/* PWM/Timer Definitions ****************************************************/ -/* Debug *********************************************************************/ +/* Debug ********************************************************************/ #ifdef CONFIG_DEBUG_PWM_INFO # define pwm_dumpgpio(p,m) s32k1xx_pindump(p,m) @@ -88,9 +88,9 @@ # define pwm_dumpgpio(p,m) #endif -/***************************************************************************** +/**************************************************************************** * Private Types - *****************************************************************************/ + ****************************************************************************/ /* This structure represents the state of one PWM timer */ @@ -104,9 +104,9 @@ struct s32k1xx_pwmtimer_s uint32_t pclk; /* The frequency of the peripheral clock */ }; -/***************************************************************************** +/**************************************************************************** * Static Function Prototypes - *****************************************************************************/ + ****************************************************************************/ /* Register access */ @@ -138,9 +138,9 @@ static int pwm_stop(FAR struct pwm_lowerhalf_s *dev); static int pwm_ioctl(FAR struct pwm_lowerhalf_s *dev, int cmd, unsigned long arg); -/***************************************************************************** +/**************************************************************************** * Private Data - *****************************************************************************/ + ****************************************************************************/ /* This is the list of lower half PWM driver methods used by the upper half * driver. @@ -243,11 +243,11 @@ static struct s32k1xx_pwmtimer_s g_pwm7dev = }; #endif -/***************************************************************************** +/**************************************************************************** * Private Functions - *****************************************************************************/ + ****************************************************************************/ -/***************************************************************************** +/**************************************************************************** * Name: pwm_getreg * * Description: @@ -260,14 +260,14 @@ static struct s32k1xx_pwmtimer_s g_pwm7dev = * Returned Value: * The current contents of the specified register * - *****************************************************************************/ + ****************************************************************************/ static uint32_t pwm_getreg(struct s32k1xx_pwmtimer_s *priv, int offset) { return getreg32(priv->base + offset); } -/***************************************************************************** +/**************************************************************************** * Name: pwm_putreg * * Description: @@ -280,7 +280,7 @@ static uint32_t pwm_getreg(struct s32k1xx_pwmtimer_s *priv, int offset) * Returned Value: * None * - *****************************************************************************/ + ****************************************************************************/ static void pwm_putreg(struct s32k1xx_pwmtimer_s *priv, int offset, uint32_t value) @@ -288,7 +288,7 @@ static void pwm_putreg(struct s32k1xx_pwmtimer_s *priv, int offset, putreg32(value, priv->base + offset); } -/***************************************************************************** +/**************************************************************************** * Name: pwm_dumpregs * * Description: @@ -300,10 +300,11 @@ static void pwm_putreg(struct s32k1xx_pwmtimer_s *priv, int offset, * Returned Value: * None * - *****************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_DEBUG_PWM_INFO -static void pwm_dumpregs(struct s32k1xx_pwmtimer_s *priv, FAR const char *msg) +static void pwm_dumpregs(struct s32k1xx_pwmtimer_s *priv, + FAR const char *msg) { pwminfo("%s:\n", msg); pwminfo(" FTM%d_SC: %04x FTM%d_CNT: %04x FTM%d_MOD: %04x\n", @@ -340,7 +341,7 @@ static void pwm_dumpregs(struct s32k1xx_pwmtimer_s *priv, FAR const char *msg) } #endif -/***************************************************************************** +/**************************************************************************** * Name: pwm_timer * * Description: @@ -353,7 +354,7 @@ static void pwm_dumpregs(struct s32k1xx_pwmtimer_s *priv, FAR const char *msg) * Returned Value: * Zero on success; a negated errno value on failure * - *****************************************************************************/ + ****************************************************************************/ static int pwm_timer(FAR struct s32k1xx_pwmtimer_s *priv, FAR const struct pwm_info_s *info) @@ -367,7 +368,10 @@ static int pwm_timer(FAR struct s32k1xx_pwmtimer_s *priv, uint32_t cv; uint8_t i; - static const uint8_t presc_values[8] = {1, 2, 4, 8, 16, 32, 64, 128}; + static const uint8_t presc_values[8] = + { + 1, 2, 4, 8, 16, 32, 64, 128 + }; /* Register contents */ @@ -379,8 +383,8 @@ static int pwm_timer(FAR struct s32k1xx_pwmtimer_s *priv, DEBUGASSERT(info->frequency > 0 && info->duty > 0 && info->duty < uitoub16(100)); - /* Calculate optimal values for the timer prescaler and for the timer modulo - * register. If' frequency' is the desired frequency, then + /* Calculate optimal values for the timer prescaler and for the timer + * modulo register. If' frequency' is the desired frequency, then * * modulo = tpmclk / frequency * tpmclk = pclk / presc @@ -542,7 +546,7 @@ static int pwm_timer(FAR struct s32k1xx_pwmtimer_s *priv, return OK; } -/***************************************************************************** +/**************************************************************************** * Name: pwm_setup * * Description: @@ -560,7 +564,7 @@ static int pwm_timer(FAR struct s32k1xx_pwmtimer_s *priv, * AHB1 or 2 clocking for the GPIOs and timer has already been configured * by the RCC logic at power up. * - *****************************************************************************/ + ****************************************************************************/ static int pwm_setup(FAR struct pwm_lowerhalf_s *dev) { @@ -580,7 +584,7 @@ static int pwm_setup(FAR struct pwm_lowerhalf_s *dev) return OK; } -/***************************************************************************** +/**************************************************************************** * Name: pwm_shutdown * * Description: @@ -594,7 +598,7 @@ static int pwm_setup(FAR struct pwm_lowerhalf_s *dev) * Returned Value: * Zero on success; a negated errno value on failure * - *****************************************************************************/ + ****************************************************************************/ static int pwm_shutdown(FAR struct pwm_lowerhalf_s *dev) { @@ -615,7 +619,7 @@ static int pwm_shutdown(FAR struct pwm_lowerhalf_s *dev) return OK; } -/***************************************************************************** +/**************************************************************************** * Name: pwm_start * * Description: @@ -628,7 +632,7 @@ static int pwm_shutdown(FAR struct pwm_lowerhalf_s *dev) * Returned Value: * Zero on success; a negated errno value on failure * - *****************************************************************************/ + ****************************************************************************/ static int pwm_start(FAR struct pwm_lowerhalf_s *dev, FAR const struct pwm_info_s *info) @@ -637,7 +641,7 @@ static int pwm_start(FAR struct pwm_lowerhalf_s *dev, return pwm_timer(priv, info); } -/***************************************************************************** +/**************************************************************************** * Name: pwm_stop * * Description: @@ -654,7 +658,7 @@ static int pwm_start(FAR struct pwm_lowerhalf_s *dev, * method is also called from the timer interrupt handler when a repetition * count expires... automatically stopping the timer. * - *****************************************************************************/ + ****************************************************************************/ static int pwm_stop(FAR struct pwm_lowerhalf_s *dev) { @@ -721,7 +725,7 @@ static int pwm_stop(FAR struct pwm_lowerhalf_s *dev) return OK; } -/***************************************************************************** +/**************************************************************************** * Name: pwm_ioctl * * Description: @@ -735,7 +739,7 @@ static int pwm_stop(FAR struct pwm_lowerhalf_s *dev) * Returned Value: * Zero on success; a negated errno value on failure * - *****************************************************************************/ + ****************************************************************************/ static int pwm_ioctl(FAR struct pwm_lowerhalf_s *dev, int cmd, unsigned long arg) @@ -750,11 +754,11 @@ static int pwm_ioctl(FAR struct pwm_lowerhalf_s *dev, int cmd, return -ENOTTY; } -/***************************************************************************** +/**************************************************************************** * Public Functions - *****************************************************************************/ + ****************************************************************************/ -/***************************************************************************** +/**************************************************************************** * Name: s32k1xx_pwminitialize * * Description: @@ -767,7 +771,7 @@ static int pwm_ioctl(FAR struct pwm_lowerhalf_s *dev, int cmd, * On success, a pointer to the S32K1XX lower half PWM driver is returned. * NULL is returned on any failure. * - *****************************************************************************/ + ****************************************************************************/ FAR struct pwm_lowerhalf_s *s32k1xx_pwminitialize(int timer) { diff --git a/arch/arm/src/s32k1xx/s32k1xx_pwm.h b/arch/arm/src/s32k1xx/s32k1xx_pwm.h index 9ec5a00653a..1a452531bfc 100644 --- a/arch/arm/src/s32k1xx/s32k1xx_pwm.h +++ b/arch/arm/src/s32k1xx/s32k1xx_pwm.h @@ -1,4 +1,4 @@ -/***************************************************************************** +/**************************************************************************** * arch/arm/src/s32k1xx/s32k1xx_pwm.h * * Copyright (C) 2013, 2016, 2017 Gregory Nutt. All rights reserved. @@ -34,24 +34,24 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - *****************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_S32K1XX_S32K1XX_PWM_H #define __ARCH_ARM_SRC_S32K1XX_S32K1XX_PWM_H -/***************************************************************************** +/**************************************************************************** * Included Files - *****************************************************************************/ + ****************************************************************************/ #include #include "chip.h" -/***************************************************************************** +/**************************************************************************** * Pre-processor Definitions - *****************************************************************************/ + ****************************************************************************/ -/* Configuration *************************************************************/ +/* Configuration ************************************************************/ /* Timer devices may be used for different purposes. One special purpose is * to generate modulated outputs for such things as motor control. If @@ -296,13 +296,13 @@ # endif #endif -/***************************************************************************** +/**************************************************************************** * Public Types - *****************************************************************************/ + ****************************************************************************/ -/***************************************************************************** +/**************************************************************************** * Public Data - *****************************************************************************/ + ****************************************************************************/ #ifndef __ASSEMBLY__ @@ -315,11 +315,11 @@ extern "C" #define EXTERN extern #endif -/***************************************************************************** +/**************************************************************************** * Public Function Prototypes - *****************************************************************************/ + ****************************************************************************/ -/***************************************************************************** +/**************************************************************************** * Name: s32k1xx_pwminitialize * * Description: @@ -332,7 +332,7 @@ extern "C" * On success, a pointer to the S32K1XX lower half PWM driver is returned. * NULL is returned on any failure. * - *****************************************************************************/ + ****************************************************************************/ FAR struct pwm_lowerhalf_s *s32k1xx_pwminitialize(int timer); diff --git a/arch/arm/src/s32k1xx/s32k1xx_start.h b/arch/arm/src/s32k1xx/s32k1xx_start.h index e85f36f2be0..13e7f0f6dd0 100644 --- a/arch/arm/src/s32k1xx/s32k1xx_start.h +++ b/arch/arm/src/s32k1xx/s32k1xx_start.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/s32k1xx/s32k1xx_start.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,14 +16,14 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_S32K1XX_S32K1XX_START_H #define __ARCH_ARM_SRC_S32K1XX_S32K1XX_START_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include @@ -35,32 +35,32 @@ #include "arm_internal.h" #include "chip.h" -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ #ifndef __ASSEMBLY__ -/* Each S32K1xx board must provide the following initialized structure. This is - * needed to establish the initial board clocking. +/* Each S32K1xx board must provide the following initialized structure. + * This is needed to establish the initial board clocking. */ extern const struct clock_configuration_s g_initial_clkconfig; -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Name: s32k1xx_board_initialize * * Description: - * All S32K1XX architectures must provide the following entry point. This entry - * point is called early in the initialization -- after clocking and memory have - * been configured but before caches have been enabled and before any devices have - * been initialized. + * All S32K1XX architectures must provide the following entry point. + * This entry point is called early in the initialization -- after + * clocking and memory have been configured but before caches have been + * enabled and before any devices have been initialized. * - ************************************************************************************/ + ****************************************************************************/ void s32k1xx_board_initialize(void);