diff --git a/arch/arm/src/common/stm32/hardware/stm32_exti_m33_v1.h b/arch/arm/src/common/stm32/hardware/stm32_exti_m33_v1.h index ec9cf3315bb..13d612e596c 100644 --- a/arch/arm/src/common/stm32/hardware/stm32_exti_m33_v1.h +++ b/arch/arm/src/common/stm32/hardware/stm32_exti_m33_v1.h @@ -50,7 +50,7 @@ # define STM32_EXTI_NLINES 54 #elif defined(CONFIG_STM32_STM32H53XXX) # define STM32_EXTI_NLINES 59 -#elif defined(CONFIG_STM32_STM32H563XX) +#elif defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32_STM32H57XXX) # define STM32_EXTI_NLINES 58 #else # error "Unsupported STM32 M33 EXTI line inventory" diff --git a/arch/arm/src/common/stm32/stm32_gpio_m33_v1.h b/arch/arm/src/common/stm32/stm32_gpio_m33_v1.h index e6300bc141e..c818e60bf74 100644 --- a/arch/arm/src/common/stm32/stm32_gpio_m33_v1.h +++ b/arch/arm/src/common/stm32/stm32_gpio_m33_v1.h @@ -191,6 +191,7 @@ # define GPIO_PORTF (5 << GPIO_PORT_SHIFT) /* GPIOF */ # define GPIO_PORTG (6 << GPIO_PORT_SHIFT) /* GPIOG */ # define GPIO_PORTH (7 << GPIO_PORT_SHIFT) /* GPIOH */ +# define GPIO_PORTI (8 << GPIO_PORT_SHIFT) /* GPIOI */ /* This identifies the bit in the port: * diff --git a/arch/arm/src/stm32h5/CMakeLists.txt b/arch/arm/src/stm32h5/CMakeLists.txt index 6598f35ea90..d483e540538 100644 --- a/arch/arm/src/stm32h5/CMakeLists.txt +++ b/arch/arm/src/stm32h5/CMakeLists.txt @@ -37,13 +37,11 @@ endif() list( APPEND SRCS - stm32_gpio.c stm32_lowputc.c stm32_rcc.c stm32_pwr.c stm32_lse.c stm32_lsi.c - stm32_exti_gpio.c stm32_sdmmc.c) if(CONFIG_STM32_USART) diff --git a/arch/arm/src/stm32h5/Kconfig b/arch/arm/src/stm32h5/Kconfig index b0e730ab570..5af91140a54 100644 --- a/arch/arm/src/stm32h5/Kconfig +++ b/arch/arm/src/stm32h5/Kconfig @@ -10,6 +10,8 @@ comment "STM32H5 Configuration Options" config STM32_H5_PERIPHERALS bool default y + select STM32_HAVE_IP_EXTI_M33_V1 + select STM32_HAVE_IP_GPIO_M33_V1 select STM32_HAVE_DMA1 select STM32_HAVE_DMA2 select STM32_HAVE_I2C1 diff --git a/arch/arm/src/stm32h5/Make.defs b/arch/arm/src/stm32h5/Make.defs index ad800675824..ee23773c917 100644 --- a/arch/arm/src/stm32h5/Make.defs +++ b/arch/arm/src/stm32h5/Make.defs @@ -40,9 +40,9 @@ endif # Required STM32H5 files -CHIP_CSRCS += stm32_gpio.c stm32_lowputc.c stm32_rcc.c +CHIP_CSRCS += stm32_lowputc.c stm32_rcc.c CHIP_CSRCS += stm32_pwr.c -CHIP_CSRCS += stm32_lse.c stm32_lsi.c stm32_exti_gpio.c stm32_sdmmc.c +CHIP_CSRCS += stm32_lse.c stm32_lsi.c stm32_sdmmc.c ifeq ($(CONFIG_STM32_USART),y) CHIP_CSRCS += stm32_serial.c diff --git a/arch/arm/src/stm32h5/hardware/stm32_exti.h b/arch/arm/src/stm32h5/hardware/stm32_exti.h deleted file mode 100644 index b4df54763aa..00000000000 --- a/arch/arm/src/stm32h5/hardware/stm32_exti.h +++ /dev/null @@ -1,89 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32h5/hardware/stm32_exti.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32_EXTI_H -#define __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32_EXTI_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include "chip.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Register Offsets *********************************************************/ - -#define STM32_EXTI_RTSR1_OFFSET 0x0000 /* Rising Trigger Selection 1 */ -#define STM32_EXTI_FTSR1_OFFSET 0x0004 /* Falling Trigger Selection 1 */ -#define STM32_EXTI_SWIER1_OFFSET 0x0008 /* Software Interrupt Event 1 */ -#define STM32_EXTI_RPR1_OFFSET 0x000c /* Rising Edge Pending 1 */ -#define STM32_EXTI_FPR1_OFFSET 0x0010 /* Falling Edge Pending 1 */ -#define STM32_EXTI_SECCFGR1_OFFSET 0x0014 /* Security Configuration 1 */ -#define STM32_EXTI_PRIVCFGR1_OFFSET 0x0018 /* Privilege Configuration 1 */ -#define STM32_EXTI_RTSR2_OFFSET 0x0020 /* Rising Trigger Selection 2 */ -#define STM32_EXTI_FTSR2_OFFSET 0x0024 /* Falling Trigger Selection 2 */ -#define STM32_EXTI_SWIER2_OFFSET 0x0028 /* Software Interrupt Event 2 */ -#define STM32_EXTI_RPR2_OFFSET 0x002c /* Rising Edge Pending 2 */ -#define STM32_EXTI_FPR2_OFFSET 0x0030 /* Falling Edge Pending 2 */ -#define STM32_EXTI_SECCFGR2_OFFSET 0x0034 /* Security Configuration 2 */ -#define STM32_EXTI_PRIVCFGR2_OFFSET 0x0038 /* Privilege Configuration 2 */ -#define STM32_EXTI_EXTICR1_OFFSET 0x0060 /* External Interrupt Selection 1 */ -#define STM32_EXTI_EXTICR2_OFFSET 0x0064 /* External Interrupt Selection 2 */ -#define STM32_EXTI_EXTICR3_OFFSET 0x0068 /* External Interrupt Selection 3 */ -#define STM32_EXTI_EXTICR4_OFFSET 0x006C /* External Interrupt Selection 4 */ -#define STM32_EXTI_LOCKR_OFFSET 0x0070 /* Lock */ -#define STM32_EXTI_IMR1_OFFSET 0x0080 /* CPU Wakeup with Interrupt Mask 1 */ -#define STM32_EXTI_EMR1_OFFSET 0x0084 /* CPU Wakeup with Event Mask 1 */ -#define STM32_EXTI_IMR2_OFFSET 0x0090 /* CPU Wakeup with Interrupt Mask 2 */ -#define STM32_EXTI_EMR2_OFFSET 0x0094 /* CPU Wakeup with Event Mask 2 */ - -/* Register Addresses *******************************************************/ - -#define STM32_EXTI_RTSR1 (STM32_EXTI_BASE + STM32_EXTI_RTSR1_OFFSET) -#define STM32_EXTI_FTSR1 (STM32_EXTI_BASE + STM32_EXTI_FTSR1_OFFSET) -#define STM32_EXTI_SWIER1 (STM32_EXTI_BASE + STM32_EXTI_SWIER1_OFFSET) -#define STM32_EXTI_RPR1 (STM32_EXTI_BASE + STM32_EXTI_RPR1_OFFSET) -#define STM32_EXTI_FPR1 (STM32_EXTI_BASE + STM32_EXTI_FPR1_OFFSET) -#define STM32_EXTI_SECCFGR1 (STM32_EXTI_BASE + STM32_EXTI_SECCFGR1_OFFSET) -#define STM32_EXTI_PRIVCFGR1 (STM32_EXTI_BASE + STM32_EXTI_PRIVCFGR1_OFFSET) -#define STM32_EXTI_RTSR2 (STM32_EXTI_BASE + STM32_EXTI_RTSR2_OFFSET) -#define STM32_EXTI_FTSR2 (STM32_EXTI_BASE + STM32_EXTI_FTSR2_OFFSET) -#define STM32_EXTI_SWIER2 (STM32_EXTI_BASE + STM32_EXTI_SWIER2_OFFSET) -#define STM32_EXTI_RPR2 (STM32_EXTI_BASE + STM32_EXTI_RPR2_OFFSET) -#define STM32_EXTI_FPR2 (STM32_EXTI_BASE + STM32_EXTI_FPR2_OFFSET) -#define STM32_EXTI_SECCFGR2 (STM32_EXTI_BASE + STM32_EXTI_SECCFGR2_OFFSET) -#define STM32_EXTI_PRIVCFGR2 (STM32_EXTI_BASE + STM32_EXTI_PRIVCFGR2_OFFSET) -#define STM32_EXTI_EXTICR1 (STM32_EXTI_BASE + STM32_EXTI_EXTICR1_OFFSET) -#define STM32_EXTI_EXTICR2 (STM32_EXTI_BASE + STM32_EXTI_EXTICR2_OFFSET) -#define STM32_EXTI_EXTICR3 (STM32_EXTI_BASE + STM32_EXTI_EXTICR3_OFFSET) -#define STM32_EXTI_EXTICR4 (STM32_EXTI_BASE + STM32_EXTI_EXTICR4_OFFSET) -#define STM32_EXTI_LOCKR (STM32_EXTI_BASE + STM32_EXTI_LOCKR_OFFSET) -#define STM32_EXTI_IMR1 (STM32_EXTI_BASE + STM32_EXTI_IMR1_OFFSET) -#define STM32_EXTI_EMR1 (STM32_EXTI_BASE + STM32_EXTI_EMR1_OFFSET) -#define STM32_EXTI_IMR2 (STM32_EXTI_BASE + STM32_EXTI_IMR2_OFFSET) -#define STM32_EXTI_EMR2 (STM32_EXTI_BASE + STM32_EXTI_EMR2_OFFSET) - -#endif /* __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32_EXTI_H */ diff --git a/arch/arm/src/stm32h5/hardware/stm32_gpio.h b/arch/arm/src/stm32h5/hardware/stm32_gpio.h deleted file mode 100644 index a024da347a0..00000000000 --- a/arch/arm/src/stm32h5/hardware/stm32_gpio.h +++ /dev/null @@ -1,42 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32h5/hardware/stm32_gpio.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32_GPIO_H -#define __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32_GPIO_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include "chip.h" - -#if defined(CONFIG_STM32_STM32H50XXX) || \ - defined(CONFIG_STM32_STM32H52XXX) || \ - defined(CONFIG_STM32_STM32H53XXX) || \ - defined(CONFIG_STM32_STM32H56XXX) || \ - defined(CONFIG_STM32_STM32H57XXX) -# include "hardware/stm32h5xxx_gpio.h" -#else -# error "Unsupported STM32 H5 PWR" -#endif -#endif /* __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32_GPIO_H */ \ No newline at end of file diff --git a/arch/arm/src/stm32h5/hardware/stm32h5xxx_gpio.h b/arch/arm/src/stm32h5/hardware/stm32h5xxx_gpio.h deleted file mode 100644 index 9718063e461..00000000000 --- a/arch/arm/src/stm32h5/hardware/stm32h5xxx_gpio.h +++ /dev/null @@ -1,404 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32h5/hardware/stm32h5xxx_gpio.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32H5XXX_GPIO_H -#define __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32H5XXX_GPIO_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Register Offsets *********************************************************/ - -#define STM32_GPIO_MODER_OFFSET 0x0000 /* GPIO port mode register */ -#define STM32_GPIO_OTYPER_OFFSET 0x0004 /* GPIO port output type register */ -#define STM32_GPIO_OSPEED_OFFSET 0x0008 /* GPIO port output speed register */ -#define STM32_GPIO_PUPDR_OFFSET 0x000c /* GPIO port pull-up/pull-down register */ -#define STM32_GPIO_IDR_OFFSET 0x0010 /* GPIO port input data register */ -#define STM32_GPIO_ODR_OFFSET 0x0014 /* GPIO port output data register */ -#define STM32_GPIO_BSRR_OFFSET 0x0018 /* GPIO port bit set/reset register */ -#define STM32_GPIO_LCKR_OFFSET 0x001c /* GPIO port configuration lock register */ -#define STM32_GPIO_AFRL_OFFSET 0x0020 /* GPIO alternate function low register */ -#define STM32_GPIO_AFRH_OFFSET 0x0024 /* GPIO alternate function high register */ -#define STM32_GPIO_BRR_OFFSET 0x0028 /* GPIO port bit reset register */ -#define STM32_GPIO_BRR_OFFSET 0x0028 /* GPIO port bit reset register */ -#define STM32_GPIO_HSLVR_OFFSET 0x002c /* GPIO high-speed low-voltage register */ -#define STM32_GPIO_SECCFGR_OFFSET 0x0030 /* GPIO secure configuration register */ - -/* Register Addresses *******************************************************/ - -#if STM32_NPORTS > 0 -# define STM32_GPIOA_MODER (STM32_GPIOA_BASE + STM32_GPIO_MODER_OFFSET) -# define STM32_GPIOA_OTYPER (STM32_GPIOA_BASE + STM32_GPIO_OTYPER_OFFSET) -# define STM32_GPIOA_OSPEED (STM32_GPIOA_BASE + STM32_GPIO_OSPEED_OFFSET) -# define STM32_GPIOA_PUPDR (STM32_GPIOA_BASE + STM32_GPIO_PUPDR_OFFSET) -# define STM32_GPIOA_IDR (STM32_GPIOA_BASE + STM32_GPIO_IDR_OFFSET) -# define STM32_GPIOA_ODR (STM32_GPIOA_BASE + STM32_GPIO_ODR_OFFSET) -# define STM32_GPIOA_BSRR (STM32_GPIOA_BASE + STM32_GPIO_BSRR_OFFSET) -# define STM32_GPIOA_LCKR (STM32_GPIOA_BASE + STM32_GPIO_LCKR_OFFSET) -# define STM32_GPIOA_AFRL (STM32_GPIOA_BASE + STM32_GPIO_AFRL_OFFSET) -# define STM32_GPIOA_AFRH (STM32_GPIOA_BASE + STM32_GPIO_AFRH_OFFSET) -# define STM32_GPIOA_BRR (STM32_GPIOA_BASE + STM32_GPIO_BRR_OFFSET) -# define STM32_GPIOA_HSLVR (STM32_GPIOA_BASE + STM32_GPIO_HSLVR_OFFSET) -# define STM32_GPIOA_SECCFGR (STM32_GPIOA_BASE + STM32_GPIO_SECCFGR_OFFSET) -#endif - -#if STM32_NPORTS > 1 -# define STM32_GPIOB_MODER (STM32_GPIOB_BASE + STM32_GPIO_MODER_OFFSET) -# define STM32_GPIOB_OTYPER (STM32_GPIOB_BASE + STM32_GPIO_OTYPER_OFFSET) -# define STM32_GPIOB_OSPEED (STM32_GPIOB_BASE + STM32_GPIO_OSPEED_OFFSET) -# define STM32_GPIOB_PUPDR (STM32_GPIOB_BASE + STM32_GPIO_PUPDR_OFFSET) -# define STM32_GPIOB_IDR (STM32_GPIOB_BASE + STM32_GPIO_IDR_OFFSET) -# define STM32_GPIOB_ODR (STM32_GPIOB_BASE + STM32_GPIO_ODR_OFFSET) -# define STM32_GPIOB_BSRR (STM32_GPIOB_BASE + STM32_GPIO_BSRR_OFFSET) -# define STM32_GPIOB_LCKR (STM32_GPIOB_BASE + STM32_GPIO_LCKR_OFFSET) -# define STM32_GPIOB_AFRL (STM32_GPIOB_BASE + STM32_GPIO_AFRL_OFFSET) -# define STM32_GPIOB_AFRH (STM32_GPIOB_BASE + STM32_GPIO_AFRH_OFFSET) -# define STM32_GPIOB_BRR (STM32_GPIOB_BASE + STM32_GPIO_BRR_OFFSET) -# define STM32_GPIOA_HSLVR (STM32_GPIOA_BASE + STM32_GPIO_HSLVR_OFFSET) -# define STM32_GPIOB_SECCFGR (STM32_GPIOB_BASE + STM32_GPIO_SECCFGR_OFFSET) -#endif - -#if STM32_NPORTS > 2 -# define STM32_GPIOC_MODER (STM32_GPIOC_BASE + STM32_GPIO_MODER_OFFSET) -# define STM32_GPIOC_OTYPER (STM32_GPIOC_BASE + STM32_GPIO_OTYPER_OFFSET) -# define STM32_GPIOC_OSPEED (STM32_GPIOC_BASE + STM32_GPIO_OSPEED_OFFSET) -# define STM32_GPIOC_PUPDR (STM32_GPIOC_BASE + STM32_GPIO_PUPDR_OFFSET) -# define STM32_GPIOC_IDR (STM32_GPIOC_BASE + STM32_GPIO_IDR_OFFSET) -# define STM32_GPIOC_ODR (STM32_GPIOC_BASE + STM32_GPIO_ODR_OFFSET) -# define STM32_GPIOC_BSRR (STM32_GPIOC_BASE + STM32_GPIO_BSRR_OFFSET) -# define STM32_GPIOC_LCKR (STM32_GPIOC_BASE + STM32_GPIO_LCKR_OFFSET) -# define STM32_GPIOC_AFRL (STM32_GPIOC_BASE + STM32_GPIO_AFRL_OFFSET) -# define STM32_GPIOC_AFRH (STM32_GPIOC_BASE + STM32_GPIO_AFRH_OFFSET) -# define STM32_GPIOC_BRR (STM32_GPIOC_BASE + STM32_GPIO_BRR_OFFSET) -# define STM32_GPIOA_HSLVR (STM32_GPIOA_BASE + STM32_GPIO_HSLVR_OFFSET) -# define STM32_GPIOC_SECCFGR (STM32_GPIOC_BASE + STM32_GPIO_SECCFGR_OFFSET) -#endif - -#if STM32_NPORTS > 3 -# define STM32_GPIOD_MODER (STM32_GPIOD_BASE + STM32_GPIO_MODER_OFFSET) -# define STM32_GPIOD_OTYPER (STM32_GPIOD_BASE + STM32_GPIO_OTYPER_OFFSET) -# define STM32_GPIOD_OSPEED (STM32_GPIOD_BASE + STM32_GPIO_OSPEED_OFFSET) -# define STM32_GPIOD_PUPDR (STM32_GPIOD_BASE + STM32_GPIO_PUPDR_OFFSET) -# define STM32_GPIOD_IDR (STM32_GPIOD_BASE + STM32_GPIO_IDR_OFFSET) -# define STM32_GPIOD_ODR (STM32_GPIOD_BASE + STM32_GPIO_ODR_OFFSET) -# define STM32_GPIOD_BSRR (STM32_GPIOD_BASE + STM32_GPIO_BSRR_OFFSET) -# define STM32_GPIOD_LCKR (STM32_GPIOD_BASE + STM32_GPIO_LCKR_OFFSET) -# define STM32_GPIOD_AFRL (STM32_GPIOD_BASE + STM32_GPIO_AFRL_OFFSET) -# define STM32_GPIOD_AFRH (STM32_GPIOD_BASE + STM32_GPIO_AFRH_OFFSET) -# define STM32_GPIOD_BRR (STM32_GPIOD_BASE + STM32_GPIO_BRR_OFFSET) -# define STM32_GPIOA_HSLVR (STM32_GPIOA_BASE + STM32_GPIO_HSLVR_OFFSET) -# define STM32_GPIOD_SECCFGR (STM32_GPIOD_BASE + STM32_GPIO_SECCFGR_OFFSET) -#endif - -#if STM32_NPORTS > 4 -# define STM32_GPIOE_MODER (STM32_GPIOE_BASE + STM32_GPIO_MODER_OFFSET) -# define STM32_GPIOE_OTYPER (STM32_GPIOE_BASE + STM32_GPIO_OTYPER_OFFSET) -# define STM32_GPIOE_OSPEED (STM32_GPIOE_BASE + STM32_GPIO_OSPEED_OFFSET) -# define STM32_GPIOE_PUPDR (STM32_GPIOE_BASE + STM32_GPIO_PUPDR_OFFSET) -# define STM32_GPIOE_IDR (STM32_GPIOE_BASE + STM32_GPIO_IDR_OFFSET) -# define STM32_GPIOE_ODR (STM32_GPIOE_BASE + STM32_GPIO_ODR_OFFSET) -# define STM32_GPIOE_BSRR (STM32_GPIOE_BASE + STM32_GPIO_BSRR_OFFSET) -# define STM32_GPIOE_LCKR (STM32_GPIOE_BASE + STM32_GPIO_LCKR_OFFSET) -# define STM32_GPIOE_AFRL (STM32_GPIOE_BASE + STM32_GPIO_AFRL_OFFSET) -# define STM32_GPIOE_AFRH (STM32_GPIOE_BASE + STM32_GPIO_AFRH_OFFSET) -# define STM32_GPIOE_BRR (STM32_GPIOE_BASE + STM32_GPIO_BRR_OFFSET) -# define STM32_GPIOA_HSLVR (STM32_GPIOA_BASE + STM32_GPIO_HSLVR_OFFSET) -# define STM32_GPIOE_SECCFGR (STM32_GPIOE_BASE + STM32_GPIO_SECCFGR_OFFSET) -#endif - -#if STM32_NPORTS > 5 -# define STM32_GPIOF_MODER (STM32_GPIOF_BASE + STM32_GPIO_MODER_OFFSET) -# define STM32_GPIOF_OTYPER (STM32_GPIOF_BASE + STM32_GPIO_OTYPER_OFFSET) -# define STM32_GPIOF_OSPEED (STM32_GPIOF_BASE + STM32_GPIO_OSPEED_OFFSET) -# define STM32_GPIOF_PUPDR (STM32_GPIOF_BASE + STM32_GPIO_PUPDR_OFFSET) -# define STM32_GPIOF_IDR (STM32_GPIOF_BASE + STM32_GPIO_IDR_OFFSET) -# define STM32_GPIOF_ODR (STM32_GPIOF_BASE + STM32_GPIO_ODR_OFFSET) -# define STM32_GPIOF_BSRR (STM32_GPIOF_BASE + STM32_GPIO_BSRR_OFFSET) -# define STM32_GPIOF_LCKR (STM32_GPIOF_BASE + STM32_GPIO_LCKR_OFFSET) -# define STM32_GPIOF_AFRL (STM32_GPIOF_BASE + STM32_GPIO_AFRL_OFFSET) -# define STM32_GPIOF_AFRH (STM32_GPIOF_BASE + STM32_GPIO_AFRH_OFFSET) -# define STM32_GPIOF_BRR (STM32_GPIOF_BASE + STM32_GPIO_BRR_OFFSET) -# define STM32_GPIOA_HSLVR (STM32_GPIOA_BASE + STM32_GPIO_HSLVR_OFFSET) -# define STM32_GPIOF_SECCFGR (STM32_GPIOF_BASE + STM32_GPIO_SECCFGR_OFFSET) -#endif - -#if STM32_NPORTS > 6 -# define STM32_GPIOG_MODER (STM32_GPIOG_BASE + STM32_GPIO_MODER_OFFSET) -# define STM32_GPIOG_OTYPER (STM32_GPIOG_BASE + STM32_GPIO_OTYPER_OFFSET) -# define STM32_GPIOG_OSPEED (STM32_GPIOG_BASE + STM32_GPIO_OSPEED_OFFSET) -# define STM32_GPIOG_PUPDR (STM32_GPIOG_BASE + STM32_GPIO_PUPDR_OFFSET) -# define STM32_GPIOG_IDR (STM32_GPIOG_BASE + STM32_GPIO_IDR_OFFSET) -# define STM32_GPIOG_ODR (STM32_GPIOG_BASE + STM32_GPIO_ODR_OFFSET) -# define STM32_GPIOG_BSRR (STM32_GPIOG_BASE + STM32_GPIO_BSRR_OFFSET) -# define STM32_GPIOG_LCKR (STM32_GPIOG_BASE + STM32_GPIO_LCKR_OFFSET) -# define STM32_GPIOG_AFRL (STM32_GPIOG_BASE + STM32_GPIO_AFRL_OFFSET) -# define STM32_GPIOG_AFRH (STM32_GPIOG_BASE + STM32_GPIO_AFRH_OFFSET) -# define STM32_GPIOG_BRR (STM32_GPIOG_BASE + STM32_GPIO_BRR_OFFSET) -# define STM32_GPIOA_HSLVR (STM32_GPIOA_BASE + STM32_GPIO_HSLVR_OFFSET) -# define STM32_GPIOG_SECCFGR (STM32_GPIOG_BASE + STM32_GPIO_SECCFGR_OFFSET) -#endif - -#if STM32_NPORTS > 7 -# define STM32_GPIOH_MODER (STM32_GPIOH_BASE + STM32_GPIO_MODER_OFFSET) -# define STM32_GPIOH_OTYPER (STM32_GPIOH_BASE + STM32_GPIO_OTYPER_OFFSET) -# define STM32_GPIOH_OSPEED (STM32_GPIOH_BASE + STM32_GPIO_OSPEED_OFFSET) -# define STM32_GPIOH_PUPDR (STM32_GPIOH_BASE + STM32_GPIO_PUPDR_OFFSET) -# define STM32_GPIOH_IDR (STM32_GPIOH_BASE + STM32_GPIO_IDR_OFFSET) -# define STM32_GPIOH_ODR (STM32_GPIOH_BASE + STM32_GPIO_ODR_OFFSET) -# define STM32_GPIOH_BSRR (STM32_GPIOH_BASE + STM32_GPIO_BSRR_OFFSET) -# define STM32_GPIOH_LCKR (STM32_GPIOH_BASE + STM32_GPIO_LCKR_OFFSET) -# define STM32_GPIOH_AFRL (STM32_GPIOH_BASE + STM32_GPIO_AFRL_OFFSET) -# define STM32_GPIOH_AFRH (STM32_GPIOH_BASE + STM32_GPIO_AFRH_OFFSET) -# define STM32_GPIOH_BRR (STM32_GPIOH_BASE + STM32_GPIO_BRR_OFFSET) -# define STM32_GPIOH_HSLVR (STM32_GPIOA_BASE + STM32_GPIO_HSLVR_OFFSET) -# define STM32_GPIOH_SECCFGR (STM32_GPIOH_BASE + STM32_GPIO_SECCFGR_OFFSET) -#endif - -#if STM32_NPORTS > 8 -# define STM32_GPIOI_MODER (STM32_GPIOI_BASE + STM32_GPIO_MODER_OFFSET) -# define STM32_GPIOI_OTYPER (STM32_GPIOI_BASE + STM32_GPIO_OTYPER_OFFSET) -# define STM32_GPIOI_OSPEED (STM32_GPIOI_BASE + STM32_GPIO_OSPEED_OFFSET) -# define STM32_GPIOI_PUPDR (STM32_GPIOI_BASE + STM32_GPIO_PUPDR_OFFSET) -# define STM32_GPIOI_IDR (STM32_GPIOI_BASE + STM32_GPIO_IDR_OFFSET) -# define STM32_GPIOI_ODR (STM32_GPIOI_BASE + STM32_GPIO_ODR_OFFSET) -# define STM32_GPIOI_BSRR (STM32_GPIOI_BASE + STM32_GPIO_BSRR_OFFSET) -# define STM32_GPIOI_LCKR (STM32_GPIOI_BASE + STM32_GPIO_LCKR_OFFSET) -# define STM32_GPIOI_AFRL (STM32_GPIOI_BASE + STM32_GPIO_AFRL_OFFSET) -# define STM32_GPIOI_AFRH (STM32_GPIOI_BASE + STM32_GPIO_AFRH_OFFSET) -# define STM32_GPIOI_BRR (STM32_GPIOI_BASE + STM32_GPIO_BRR_OFFSET) -# define STM32_GPIOI_HSLVR (STM32_GPIOA_BASE + STM32_GPIO_HSLVR_OFFSET) -# define STM32_GPIOI_SECCFGR (STM32_GPIOI_BASE + STM32_GPIO_SECCFGR_OFFSET) -#endif - -/* Register Bitfield Definitions ********************************************/ - -/* GPIO port mode register */ - -#define GPIO_MODER_INPUT (0) /* Input */ -#define GPIO_MODER_OUTPUT (1) /* General purpose output mode */ -#define GPIO_MODER_ALT (2) /* Alternate mode */ -#define GPIO_MODER_ANALOG (3) /* Analog mode */ - -#define GPIO_MODER_SHIFT(n) ((n) << 1) -#define GPIO_MODER_MASK(n) (3 << GPIO_MODER_SHIFT(n)) - -#define GPIO_MODER0_SHIFT (0) -#define GPIO_MODER0_MASK (3 << GPIO_MODER0_SHIFT) -#define GPIO_MODER1_SHIFT (2) -#define GPIO_MODER1_MASK (3 << GPIO_MODER1_SHIFT) -#define GPIO_MODER2_SHIFT (4) -#define GPIO_MODER2_MASK (3 << GPIO_MODER2_SHIFT) -#define GPIO_MODER3_SHIFT (6) -#define GPIO_MODER3_MASK (3 << GPIO_MODER3_SHIFT) -#define GPIO_MODER4_SHIFT (8) -#define GPIO_MODER4_MASK (3 << GPIO_MODER4_SHIFT) -#define GPIO_MODER5_SHIFT (10) -#define GPIO_MODER5_MASK (3 << GPIO_MODER5_SHIFT) -#define GPIO_MODER6_SHIFT (12) -#define GPIO_MODER6_MASK (3 << GPIO_MODER6_SHIFT) -#define GPIO_MODER7_SHIFT (14) -#define GPIO_MODER7_MASK (3 << GPIO_MODER7_SHIFT) -#define GPIO_MODER8_SHIFT (16) -#define GPIO_MODER8_MASK (3 << GPIO_MODER8_SHIFT) -#define GPIO_MODER9_SHIFT (18) -#define GPIO_MODER9_MASK (3 << GPIO_MODER9_SHIFT) -#define GPIO_MODER10_SHIFT (20) -#define GPIO_MODER10_MASK (3 << GPIO_MODER10_SHIFT) -#define GPIO_MODER11_SHIFT (22) -#define GPIO_MODER11_MASK (3 << GPIO_MODER11_SHIFT) -#define GPIO_MODER12_SHIFT (24) -#define GPIO_MODER12_MASK (3 << GPIO_MODER12_SHIFT) -#define GPIO_MODER13_SHIFT (26) -#define GPIO_MODER13_MASK (3 << GPIO_MODER13_SHIFT) -#define GPIO_MODER14_SHIFT (28) -#define GPIO_MODER14_MASK (3 << GPIO_MODER14_SHIFT) -#define GPIO_MODER15_SHIFT (30) -#define GPIO_MODER15_MASK (3 << GPIO_MODER15_SHIFT) - -/* GPIO port output type register */ - -#define GPIO_OTYPER_OD(n) (1 << (n)) /* 1=Output open-drain */ -#define GPIO_OTYPER_PP(n) (0) /* 0=Output push-pull */ - -/* GPIO port output speed register */ - -#define GPIO_OSPEED_2MHZ (0) /* 2 MHz Low speed */ -#define GPIO_OSPEED_25MHZ (1) /* 25 MHz Medium speed */ -#define GPIO_OSPEED_50MHZ (2) /* 50 MHz High speed */ -#define GPIO_OSPEED_100MHZ (3) /* 100 MHz Very High speed on 30 pF (80 MHz Output max speed on 15 pF) */ - -#define GPIO_OSPEED_SHIFT(n) ((n) << 1) -#define GPIO_OSPEED_MASK(n) (3 << GPIO_OSPEED_SHIFT(n)) - -#define GPIO_OSPEED0_SHIFT (0) -#define GPIO_OSPEED0_MASK (3 << GPIO_OSPEED0_SHIFT) -#define GPIO_OSPEED1_SHIFT (2) -#define GPIO_OSPEED1_MASK (3 << GPIO_OSPEED1_SHIFT) -#define GPIO_OSPEED2_SHIFT (4) -#define GPIO_OSPEED2_MASK (3 << GPIO_OSPEED2_SHIFT) -#define GPIO_OSPEED3_SHIFT (6) -#define GPIO_OSPEED3_MASK (3 << GPIO_OSPEED3_SHIFT) -#define GPIO_OSPEED4_SHIFT (8) -#define GPIO_OSPEED4_MASK (3 << GPIO_OSPEED4_SHIFT) -#define GPIO_OSPEED5_SHIFT (10) -#define GPIO_OSPEED5_MASK (3 << GPIO_OSPEED5_SHIFT) -#define GPIO_OSPEED6_SHIFT (12) -#define GPIO_OSPEED6_MASK (3 << GPIO_OSPEED6_SHIFT) -#define GPIO_OSPEED7_SHIFT (14) -#define GPIO_OSPEED7_MASK (3 << GPIO_OSPEED7_SHIFT) -#define GPIO_OSPEED8_SHIFT (16) -#define GPIO_OSPEED8_MASK (3 << GPIO_OSPEED8_SHIFT) -#define GPIO_OSPEED9_SHIFT (18) -#define GPIO_OSPEED9_MASK (3 << GPIO_OSPEED9_SHIFT) -#define GPIO_OSPEED10_SHIFT (20) -#define GPIO_OSPEED10_MASK (3 << GPIO_OSPEED10_SHIFT) -#define GPIO_OSPEED11_SHIFT (22) -#define GPIO_OSPEED11_MASK (3 << GPIO_OSPEED11_SHIFT) -#define GPIO_OSPEED12_SHIFT (24) -#define GPIO_OSPEED12_MASK (3 << GPIO_OSPEED12_SHIFT) -#define GPIO_OSPEED13_SHIFT (26) -#define GPIO_OSPEED13_MASK (3 << GPIO_OSPEED13_SHIFT) -#define GPIO_OSPEED14_SHIFT (28) -#define GPIO_OSPEED14_MASK (3 << GPIO_OSPEED14_SHIFT) -#define GPIO_OSPEED15_SHIFT (30) -#define GPIO_OSPEED15_MASK (3 << GPIO_OSPEED15_SHIFT) - -/* GPIO port pull-up/pull-down register */ - -#define GPIO_PUPDR_NONE (0) /* No pull-up, pull-down */ -#define GPIO_PUPDR_PULLUP (1) /* Pull-up */ -#define GPIO_PUPDR_PULLDOWN (2) /* Pull-down */ - -#define GPIO_PUPDR_SHIFT(n) ((n) << 1) -#define GPIO_PUPDR_MASK(n) (3 << GPIO_PUPDR_SHIFT(n)) - -#define GPIO_PUPDR0_SHIFT (0) -#define GPIO_PUPDR0_MASK (3 << GPIO_PUPDR0_SHIFT) -#define GPIO_PUPDR1_SHIFT (2) -#define GPIO_PUPDR1_MASK (3 << GPIO_PUPDR1_SHIFT) -#define GPIO_PUPDR2_SHIFT (4) -#define GPIO_PUPDR2_MASK (3 << GPIO_PUPDR2_SHIFT) -#define GPIO_PUPDR3_SHIFT (6) -#define GPIO_PUPDR3_MASK (3 << GPIO_PUPDR3_SHIFT) -#define GPIO_PUPDR4_SHIFT (8) -#define GPIO_PUPDR4_MASK (3 << GPIO_PUPDR4_SHIFT) -#define GPIO_PUPDR5_SHIFT (10) -#define GPIO_PUPDR5_MASK (3 << GPIO_PUPDR5_SHIFT) -#define GPIO_PUPDR6_SHIFT (12) -#define GPIO_PUPDR6_MASK (3 << GPIO_PUPDR6_SHIFT) -#define GPIO_PUPDR7_SHIFT (14) -#define GPIO_PUPDR7_MASK (3 << GPIO_PUPDR7_SHIFT) -#define GPIO_PUPDR8_SHIFT (16) -#define GPIO_PUPDR8_MASK (3 << GPIO_PUPDR8_SHIFT) -#define GPIO_PUPDR9_SHIFT (18) -#define GPIO_PUPDR9_MASK (3 << GPIO_PUPDR9_SHIFT) -#define GPIO_PUPDR10_SHIFT (20) -#define GPIO_PUPDR10_MASK (3 << GPIO_PUPDR10_SHIFT) -#define GPIO_PUPDR11_SHIFT (22) -#define GPIO_PUPDR11_MASK (3 << GPIO_PUPDR11_SHIFT) -#define GPIO_PUPDR12_SHIFT (24) -#define GPIO_PUPDR12_MASK (3 << GPIO_PUPDR12_SHIFT) -#define GPIO_PUPDR13_SHIFT (26) -#define GPIO_PUPDR13_MASK (3 << GPIO_PUPDR13_SHIFT) -#define GPIO_PUPDR14_SHIFT (28) -#define GPIO_PUPDR14_MASK (3 << GPIO_PUPDR14_SHIFT) -#define GPIO_PUPDR15_SHIFT (30) -#define GPIO_PUPDR15_MASK (3 << GPIO_PUPDR15_SHIFT) - -/* GPIO port input data register */ - -#define GPIO_IDR(n) (1 << (n)) - -/* GPIO port output data register */ - -#define GPIO_ODR(n) (1 << (n)) - -/* GPIO port bit set/reset register */ - -#define GPIO_BSRR_SET(n) (1 << (n)) -#define GPIO_BSRR_RESET(n) (1 << ((n)+16)) - -/* GPIO port configuration lock register */ - -#define GPIO_LCKR(n) (1 << (n)) -#define GPIO_LCKK (1 << 16) /* Lock key */ - -/* GPIO alternate function low/high register */ - -#define GPIO_AFR_SHIFT(n) ((n) << 2) -#define GPIO_AFR_MASK(n) (15 << GPIO_AFR_SHIFT(n)) - -#define GPIO_AFRL0_SHIFT (0) -#define GPIO_AFRL0_MASK (15 << GPIO_AFRL0_SHIFT) -#define GPIO_AFRL1_SHIFT (4) -#define GPIO_AFRL1_MASK (15 << GPIO_AFRL1_SHIFT) -#define GPIO_AFRL2_SHIFT (8) -#define GPIO_AFRL2_MASK (15 << GPIO_AFRL2_SHIFT) -#define GPIO_AFRL3_SHIFT (12) -#define GPIO_AFRL3_MASK (15 << GPIO_AFRL3_SHIFT) -#define GPIO_AFRL4_SHIFT (16) -#define GPIO_AFRL4_MASK (15 << GPIO_AFRL4_SHIFT) -#define GPIO_AFRL5_SHIFT (20) -#define GPIO_AFRL5_MASK (15 << GPIO_AFRL5_SHIFT) -#define GPIO_AFRL6_SHIFT (24) -#define GPIO_AFRL6_MASK (15 << GPIO_AFRL6_SHIFT) -#define GPIO_AFRL7_SHIFT (28) -#define GPIO_AFRL7_MASK (15 << GPIO_AFRL7_SHIFT) - -#define GPIO_AFRH8_SHIFT (0) -#define GPIO_AFRH8_MASK (15 << GPIO_AFRH8_SHIFT) -#define GPIO_AFRH9_SHIFT (4) -#define GPIO_AFRH9_MASK (15 << GPIO_AFRH9_SHIFT) -#define GPIO_AFRH10_SHIFT (8) -#define GPIO_AFRH10_MASK (15 << GPIO_AFRH10_SHIFT) -#define GPIO_AFRH11_SHIFT (12) -#define GPIO_AFRH11_MASK (15 << GPIO_AFRH11_SHIFT) -#define GPIO_AFRH12_SHIFT (16) -#define GPIO_AFRH12_MASK (15 << GPIO_AFRH12_SHIFT) -#define GPIO_AFRH13_SHIFT (20) -#define GPIO_AFRH13_MASK (15 << GPIO_AFRH13_SHIFT) -#define GPIO_AFRH14_SHIFT (24) -#define GPIO_AFRH14_MASK (15 << GPIO_AFRH14_SHIFT) -#define GPIO_AFRH15_SHIFT (28) -#define GPIO_AFRH15_MASK (15 << GPIO_AFRH15_SHIFT) - -/* GPIO port bit reset register */ - -#define GPIO_BRR_SET(n) (1 << (n)) - -/* GPIO high-speed low-voltage register */ - -#define GPIO_HSLV_SET(n) (1 << (n)) - -/* GPIO port secure configuration register */ - -#define GPIO_SECCFGR_SET(n) (1 << (n)) - -#endif /* __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32H5XXX_GPIO_H */ diff --git a/arch/arm/src/stm32h5/stm32_exti.h b/arch/arm/src/stm32h5/stm32_exti.h deleted file mode 100644 index 7e20aa28d6a..00000000000 --- a/arch/arm/src/stm32h5/stm32_exti.h +++ /dev/null @@ -1,155 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32h5/stm32_exti.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32H5_STM32_EXTI_H -#define __ARCH_ARM_SRC_STM32H5_STM32_EXTI_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include "chip.h" -#include "hardware/stm32_exti.h" - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_gpiosetevent - * - * Description: - * Sets/clears GPIO based event and interrupt triggers. - * - * Input Parameters: - * pinset - GPIO pin configuration - * risingedge - Enables interrupt on rising edges - * fallingedge - Enables interrupt on falling edges - * event - Generate event when set - * func - When non-NULL, generate interrupt - * arg - Argument passed to the interrupt callback - * - * Returned Value: - * Zero (OK) is returned on success, otherwise a negated errno value is - * returned to indicate the nature of the failure. - * - ****************************************************************************/ - -int stm32_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, - bool event, xcpt_t func, void *arg); - -/**************************************************************************** - * Name: stm32_exti_alarm - * - * Description: - * Sets/clears EXTI alarm interrupt. - * - * Input Parameters: - * - rising/falling edge: enables interrupt on rising/falling edges - * - event: generate event when set - * - func: when non-NULL, generate interrupt - * - arg: Argument passed to the interrupt callback - * - * Returned Value: - * Zero (OK) on success; a negated errno value on failure indicating the - * nature of the failure. - * - ****************************************************************************/ - -#ifdef CONFIG_RTC_ALARM -int stm32_exti_alarm(bool risingedge, bool fallingedge, bool event, - xcpt_t func, void *arg); -#endif - -/**************************************************************************** - * Name: stm32_exti_wakeup - * - * Description: - * Sets/clears EXTI wakeup interrupt. - * - * Input Parameters: - * - rising/falling edge: enables interrupt on rising/falling edges - * - event: generate event when set - * - func: when non-NULL, generate interrupt - * - arg: Argument passed to the interrupt callback - * - * Returned Value: - * Zero (OK) on success; a negated errno value on failure indicating the - * nature of the failure. - * - ****************************************************************************/ - -#ifdef CONFIG_RTC_PERIODIC -int stm32_exti_wakeup(bool risingedge, bool fallingedge, bool event, - xcpt_t func, void *arg); -#endif - -/**************************************************************************** - * Name: stm32_exti_comp - * - * Description: - * Sets/clears comparator based events and interrupt triggers. - * - * Input Parameters: - * - cmp: comparator - * - rising/falling edge: enables interrupt on rising/falling edges - * - event: generate event when set - * - func: when non-NULL, generate interrupt - * - arg: Argument passed to the interrupt callback - * - * Returned Value: - * Zero (OK) returned on success; a negated errno value is returned on - * failure. - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_COMP -int stm32_exti_comp(int cmp, bool risingedge, bool fallingedge, - bool event, xcpt_t func, void *arg); -#endif - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32H5_STM32_EXTI_H */ diff --git a/arch/arm/src/stm32h5/stm32_exti_gpio.c b/arch/arm/src/stm32h5/stm32_exti_gpio.c deleted file mode 100644 index 81e44b35d3e..00000000000 --- a/arch/arm/src/stm32h5/stm32_exti_gpio.c +++ /dev/null @@ -1,214 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32h5/stm32_exti_gpio.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include - -#include -#include -#include -#include -#include - -#include - -#include "arm_internal.h" -#include "chip.h" -#include "stm32_gpio.h" -#include "stm32_exti.h" - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -struct gpio_callback_s -{ - xcpt_t callback; /* Callback entry point */ - void *arg; /* The argument that accompanies the callback */ -}; - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* Interrupt handlers attached to each EXTI */ - -static struct gpio_callback_s g_gpio_handlers[16]; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Interrupt Service Routine - Dispatcher - ****************************************************************************/ - -static int stm32_exti0_15_isr(int irq, void *context, void *arg) -{ - int ret = OK; - int exti; - - exti = irq - STM32_IRQ_EXTI0; - DEBUGASSERT((exti >= 0) && (exti <= 15)); - - /* Clear the pending interrupt for both rising and falling edges. */ - - putreg32(0x0001 << exti, STM32_EXTI_RPR1); - putreg32(0x0001 << exti, STM32_EXTI_FPR1); - - /* And dispatch the interrupt to the handler */ - - if (g_gpio_handlers[exti].callback != NULL) - { - xcpt_t callback = g_gpio_handlers[exti].callback; - void *cbarg = g_gpio_handlers[exti].arg; - - ret = callback(irq, context, cbarg); - } - - return ret; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_gpiosetevent - * - * Description: - * Sets/clears GPIO based event and interrupt triggers. - * - * Input Parameters: - * pinset - GPIO pin configuration - * risingedge - Enables interrupt on rising edges - * fallingedge - Enables interrupt on falling edges - * event - Generate event when set - * func - When non-NULL, generate interrupt - * arg - Argument passed to the interrupt callback - * - * Returned Value: - * Zero (OK) is returned on success, otherwise a negated errno value is - * returned to indicate the nature of the failure. - * - ****************************************************************************/ - -int stm32_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, - bool event, xcpt_t func, void *arg) -{ - uint32_t pin = pinset & GPIO_PIN_MASK; - uint32_t port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - uint32_t exti = 1 << pin; - int irq = STM32_IRQ_EXTI0 + pin; - int ret; - - g_gpio_handlers[pin].callback = func; - g_gpio_handlers[pin].arg = arg; - - /* Set the mux for this EXTI to the correct bank */ - - /* Which EXTICR# does this port land on? (0-3) */ - - uint32_t exticrn = pin / 4; - - /* Which EXTI## field does this port land on? (0-3) */ - - uint32_t shift = (pin % 4) * 8; - - /* Shift our clear and set bits into place */ - - uint32_t extin_clrbits = 0b11111111 << shift; - uint32_t extin_setbits; - - if (func) - { - extin_setbits = port << shift; - } - else - { - extin_setbits = 0; - } - - /* Set or clear the MUX port according to the given port */ - - uint32_t reg = STM32_EXTI_BASE + STM32_EXTI_EXTICR1_OFFSET - + (0x04 * exticrn); - modifyreg32(reg, extin_clrbits, extin_setbits); - - /* Install external interrupt handlers */ - - if (func) - { - irq_attach(irq, stm32_exti0_15_isr, NULL); - up_enable_irq(irq); - } - else - { - /* remove any leftover callback */ - - ret = irq_detach(irq); - if (ret < 0) - { - return ret; - } - - /* disable the interrupt */ - - up_disable_irq(irq); - } - - /* Configure GPIO, enable EXTI line enabled if event or interrupt is - * enabled. - */ - - if (event || func) - { - pinset |= GPIO_EXTI; - } - - stm32_configgpio(pinset); - - /* Configure rising/falling edges */ - - modifyreg32(STM32_EXTI_RTSR1, - risingedge ? 0 : exti, - risingedge ? exti : 0); - modifyreg32(STM32_EXTI_FTSR1, - fallingedge ? 0 : exti, - fallingedge ? exti : 0); - - /* Enable Events and Interrupts */ - - modifyreg32(STM32_EXTI_EMR1, - event ? 0 : exti, - event ? exti : 0); - modifyreg32(STM32_EXTI_IMR1, - func ? 0 : exti, - func ? exti : 0); - - return OK; -} diff --git a/arch/arm/src/stm32h5/stm32_gpio.c b/arch/arm/src/stm32h5/stm32_gpio.c deleted file mode 100644 index 088df75e4f9..00000000000 --- a/arch/arm/src/stm32h5/stm32_gpio.c +++ /dev/null @@ -1,409 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32h5/stm32_gpio.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include - -#include -#include -#include - -#include "arm_internal.h" -#include "chip.h" -#include "stm32_gpio.h" - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static spinlock_t g_configgpio_lock = SP_UNLOCKED; - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/* Base addresses for each GPIO block */ - -const uint32_t g_gpiobase[STM32_NPORTS] = -{ -#if STM32_NPORTS > 0 - STM32_GPIOA_BASE, -#endif -#if STM32_NPORTS > 1 - STM32_GPIOB_BASE, -#endif -#if STM32_NPORTS > 2 - STM32_GPIOC_BASE, -#endif -#if STM32_NPORTS > 3 - STM32_GPIOD_BASE, -#endif -#if STM32_NPORTS > 4 - STM32_GPIOE_BASE, -#endif -#if STM32_NPORTS > 5 - STM32_GPIOF_BASE, -#endif -#if STM32_NPORTS > 6 - STM32_GPIOG_BASE, -#endif -#if STM32_NPORTS > 7 - STM32_GPIOH_BASE, -#endif -#if STM32_NPORTS > 8 - STM32_GPIOI_BASE, -#endif -}; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Function: stm32_gpioinit - * - * Description: - * Based on configuration within the .config file, it does: - * - Remaps positions of alternative functions. - * - * Typically called from stm32h5_start(). - * - * Assumptions: - * This function is called early in the initialization sequence so that - * no mutual exclusion is necessary. - * - ****************************************************************************/ - -void stm32_gpioinit(void) -{ -} - -/**************************************************************************** - * Name: stm32_configgpio - * - * Description: - * Configure a GPIO pin based on bit-encoded description of the pin. - * Once it is configured as Alternative (GPIO_ALT|GPIO_CNF_AFPP|...) - * function, it must be unconfigured with stm32_unconfiggpio() with - * the same cfgset first before it can be set to non-alternative function. - * - * Returned Value: - * OK on success - * A negated errno value on invalid port, or when pin is locked as ALT - * function. - * - * To-Do: Auto Power Enable - ****************************************************************************/ - -int stm32_configgpio(uint32_t cfgset) -{ - uintptr_t base; - uint32_t regval; - uint32_t setting; - unsigned int regoffset; - unsigned int port; - unsigned int pin; - unsigned int pos; - unsigned int pinmode; - irqstate_t flags; - - /* Verify that this hardware supports the select GPIO port */ - - port = (cfgset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - if (port >= STM32_NPORTS) - { - return -EINVAL; - } - - /* Get the port base address */ - - base = g_gpiobase[port]; - - /* Get the pin number and select the port configuration register for that - * pin - */ - - pin = (cfgset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; - - /* Set up the mode register (and remember whether the pin mode) */ - - switch (cfgset & GPIO_MODE_MASK) - { - default: - case GPIO_INPUT: /* Input mode */ - pinmode = GPIO_MODER_INPUT; - break; - - case GPIO_OUTPUT: /* General purpose output mode */ - - /* Set the initial output value */ - - stm32_gpiowrite(cfgset, (cfgset & GPIO_OUTPUT_SET) != 0); - pinmode = GPIO_MODER_OUTPUT; - break; - - case GPIO_ALT: /* Alternate function mode */ - pinmode = GPIO_MODER_ALT; - break; - - case GPIO_ANALOG: /* Analog mode */ - pinmode = GPIO_MODER_ANALOG; - break; - } - - /* Interrupts must be disabled from here on out so that we have mutually - * exclusive access to all of the GPIO configuration registers. - */ - - flags = spin_lock_irqsave(&g_configgpio_lock); - - /* Now apply the configuration to the mode register */ - - regval = getreg32(base + STM32_GPIO_MODER_OFFSET); - regval &= ~GPIO_MODER_MASK(pin); - regval |= ((uint32_t)pinmode << GPIO_MODER_SHIFT(pin)); - putreg32(regval, base + STM32_GPIO_MODER_OFFSET); - - /* Set up the pull-up/pull-down configuration (all but analog pins) */ - - setting = GPIO_PUPDR_NONE; - if (pinmode != GPIO_MODER_ANALOG) - { - switch (cfgset & GPIO_PUPD_MASK) - { - default: - case GPIO_FLOAT: /* No pull-up, pull-down */ - break; - - case GPIO_PULLUP: /* Pull-up */ - setting = GPIO_PUPDR_PULLUP; - break; - - case GPIO_PULLDOWN: /* Pull-down */ - setting = GPIO_PUPDR_PULLDOWN; - break; - } - } - - regval = getreg32(base + STM32_GPIO_PUPDR_OFFSET); - regval &= ~GPIO_PUPDR_MASK(pin); - regval |= (setting << GPIO_PUPDR_SHIFT(pin)); - putreg32(regval, base + STM32_GPIO_PUPDR_OFFSET); - - /* Set the alternate function (Only alternate function pins) */ - - if (pinmode == GPIO_MODER_ALT) - { - setting = (cfgset & GPIO_AF_MASK) >> GPIO_AF_SHIFT; - } - else - { - setting = 0; - } - - if (pin < 8) - { - regoffset = STM32_GPIO_AFRL_OFFSET; - pos = pin; - } - else - { - regoffset = STM32_GPIO_AFRH_OFFSET; - pos = pin - 8; - } - - regval = getreg32(base + regoffset); - regval &= ~GPIO_AFR_MASK(pos); - regval |= (setting << GPIO_AFR_SHIFT(pos)); - putreg32(regval, base + regoffset); - - /* Set speed (Only outputs and alternate function pins) */ - - if (pinmode == GPIO_MODER_OUTPUT || pinmode == GPIO_MODER_ALT) - { - switch (cfgset & GPIO_SPEED_MASK) - { - default: - case GPIO_SPEED_2MHZ: /* 2 MHz Low speed output */ - setting = GPIO_OSPEED_2MHZ; - break; - - case GPIO_SPEED_25MHZ: /* 25 MHz Medium speed output */ - setting = GPIO_OSPEED_25MHZ; - break; - - case GPIO_SPEED_50MHZ: /* 50 MHz High speed output */ - setting = GPIO_OSPEED_50MHZ; - break; - - case GPIO_SPEED_100MHZ: /* 100 MHz Very High speed output */ - setting = GPIO_OSPEED_100MHZ; - break; - } - } - else - { - setting = 0; - } - - regval = getreg32(base + STM32_GPIO_OSPEED_OFFSET); - regval &= ~GPIO_OSPEED_MASK(pin); - regval |= (setting << GPIO_OSPEED_SHIFT(pin)); - putreg32(regval, base + STM32_GPIO_OSPEED_OFFSET); - - /* Set push-pull/open-drain (Only outputs and alternate function pins) */ - - regval = getreg32(base + STM32_GPIO_OTYPER_OFFSET); - setting = GPIO_OTYPER_OD(pin); - - if ((pinmode == GPIO_MODER_OUTPUT || pinmode == GPIO_MODER_ALT) && - (cfgset & GPIO_OPENDRAIN) != 0) - { - regval |= setting; - } - else - { - regval &= ~setting; - } - - putreg32(regval, base + STM32_GPIO_OTYPER_OFFSET); - - spin_unlock_irqrestore(&g_configgpio_lock, flags); - return OK; -} - -/**************************************************************************** - * Name: stm32_unconfiggpio - * - * Description: - * Unconfigure a GPIO pin based on bit-encoded description of the pin, set - * it into default HiZ state (and possibly mark it's unused) and unlock it - * whether it was previously selected as alternative function - * (GPIO_ALT|GPIO_CNF_AFPP|...). - * - * This is a safety function and prevents hardware from shocks, as - * unexpected write to the Timer Channel Output GPIO to fixed '1' or '0' - * while it should operate in PWM mode could produce excessive on-board - * currents and trigger over-current/alarm function. - * - * Returned Value: - * OK on success - * A negated errno value on invalid port - * - * To-Do: Auto Power Disable - ****************************************************************************/ - -int stm32_unconfiggpio(uint32_t cfgset) -{ - /* Reuse port and pin number and set it to default HiZ INPUT */ - - cfgset &= GPIO_PORT_MASK | GPIO_PIN_MASK; - cfgset |= GPIO_INPUT | GPIO_FLOAT; - - /* To-Do: Mark its unuse for automatic power saving options */ - - return stm32_configgpio(cfgset); -} - -/**************************************************************************** - * Name: stm32_gpiowrite - * - * Description: - * Write one or zero to the selected GPIO pin - * - ****************************************************************************/ - -void stm32_gpiowrite(uint32_t pinset, bool value) -{ - uint32_t base; - uint32_t bit; - unsigned int port; - unsigned int pin; - - port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - if (port < STM32_NPORTS) - { - /* Get the port base address */ - - base = g_gpiobase[port]; - - /* Get the pin number */ - - pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; - - /* Set or clear the output on the pin */ - - if (value) - { - bit = GPIO_BSRR_SET(pin); - } - else - { - bit = GPIO_BSRR_RESET(pin); - } - - putreg32(bit, base + STM32_GPIO_BSRR_OFFSET); - } -} - -/**************************************************************************** - * Name: stm32_gpioread - * - * Description: - * Read one or zero from the selected GPIO pin - * - ****************************************************************************/ - -bool stm32_gpioread(uint32_t pinset) -{ - uint32_t base; - unsigned int port; - unsigned int pin; - - port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - if (port < STM32_NPORTS) - { - /* Get the port base address */ - - base = g_gpiobase[port]; - - /* Get the pin number and return the input state of that pin */ - - pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; - return ((getreg32(base + STM32_GPIO_IDR_OFFSET) & (1 << pin)) != 0); - } - - return 0; -} diff --git a/arch/arm/src/stm32h5/stm32_gpio.h b/arch/arm/src/stm32h5/stm32_gpio.h deleted file mode 100644 index 4be301eec4d..00000000000 --- a/arch/arm/src/stm32h5/stm32_gpio.h +++ /dev/null @@ -1,352 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32h5/stm32_gpio.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32H5_STM32_GPIO_H -#define __ARCH_ARM_SRC_STM32H5_STM32_GPIO_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#ifndef __ASSEMBLY__ -# include -# include -#endif - -#include -#include - -#include "chip.h" - -#if defined(CONFIG_STM32_STM32H5XXXX) -# include "hardware/stm32_gpio.h" -#else -# error "Unsupported STM32H5 chip" -#endif - -/**************************************************************************** - * Pre-Processor Declarations - ****************************************************************************/ - -/* Bit-encoded input to stm32_configgpio() */ - -/* Each port bit of the general-purpose I/O (GPIO) ports can be individually - * configured by software in several modes: - * - * - Input floating - * - Input pull-up - * - Input-pull-down - * - Output open-drain with pull-up or pull-down capability - * - Output push-pull with pull-up or pull-down capability - * - Alternate function push-pull with pull-up or pull-down capability - * - Alternate function open-drain with pull-up or pull-down capability - * - Analog - * - * 20-bit Encoding: 1111 1111 1100 0000 0000 - * 9876 5432 1098 7654 3210 - * ---- ---- ---- ---- ---- - * Inputs: MMUU .... ...X PPPP BBBB - * Outputs: MMUU .... FFOV PPPP BBBB - * Alternate Functions: MMUU AAAA FFO. PPPP BBBB - * Analog: MM.. .... .... PPPP BBBB - */ - -/* Mode: - * - * 1111 1111 1100 0000 0000 - * 9876 5432 1098 7654 3210 - * ---- ---- ---- ---- ---- - * MM.. .... .... .... .... - */ - -#define GPIO_MODE_SHIFT (18) /* Bits 18-19: GPIO port mode */ -#define GPIO_MODE_MASK (3 << GPIO_MODE_SHIFT) -# define GPIO_INPUT (0 << GPIO_MODE_SHIFT) /* Input mode */ -# define GPIO_OUTPUT (1 << GPIO_MODE_SHIFT) /* General purpose output mode */ -# define GPIO_ALT (2 << GPIO_MODE_SHIFT) /* Alternate function mode */ -# define GPIO_ANALOG (3 << GPIO_MODE_SHIFT) /* Analog mode */ - -/* Input/output pull-ups/downs (not used with analog): - * - * 1111 1111 1100 0000 0000 - * 9876 5432 1098 7654 3210 - * ---- ---- ---- ---- ---- - * ..UU .... .... .... .... - */ - -#define GPIO_PUPD_SHIFT (16) /* Bits 16-17: Pull-up/pull down */ -#define GPIO_PUPD_MASK (3 << GPIO_PUPD_SHIFT) -# define GPIO_FLOAT (0 << GPIO_PUPD_SHIFT) /* No pull-up, pull-down */ -# define GPIO_PULLUP (1 << GPIO_PUPD_SHIFT) /* Pull-up */ -# define GPIO_PULLDOWN (2 << GPIO_PUPD_SHIFT) /* Pull-down */ - -/* Alternate Functions: - * - * 1111 1111 1100 0000 0000 - * 9876 5432 1098 7654 3210 - * ---- ---- ---- ---- ---- - * .... AAAA .... .... .... - */ - -#define GPIO_AF_SHIFT (12) /* Bits 12-15: Alternate function */ -#define GPIO_AF_MASK (15 << GPIO_AF_SHIFT) -# define GPIO_AF(n) ((n) << GPIO_AF_SHIFT) -# define GPIO_AF0 (0 << GPIO_AF_SHIFT) -# define GPIO_AF1 (1 << GPIO_AF_SHIFT) -# define GPIO_AF2 (2 << GPIO_AF_SHIFT) -# define GPIO_AF3 (3 << GPIO_AF_SHIFT) -# define GPIO_AF4 (4 << GPIO_AF_SHIFT) -# define GPIO_AF5 (5 << GPIO_AF_SHIFT) -# define GPIO_AF6 (6 << GPIO_AF_SHIFT) -# define GPIO_AF7 (7 << GPIO_AF_SHIFT) -# define GPIO_AF8 (8 << GPIO_AF_SHIFT) -# define GPIO_AF9 (9 << GPIO_AF_SHIFT) -# define GPIO_AF10 (10 << GPIO_AF_SHIFT) -# define GPIO_AF11 (11 << GPIO_AF_SHIFT) -# define GPIO_AF12 (12 << GPIO_AF_SHIFT) -# define GPIO_AF13 (13 << GPIO_AF_SHIFT) -# define GPIO_AF14 (14 << GPIO_AF_SHIFT) -# define GPIO_AF15 (15 << GPIO_AF_SHIFT) - -/* Output/Alt function frequency selection: - * - * 1111 1111 1100 0000 0000 - * 9876 5432 1098 7654 3210 - * ---- ---- ---- ---- ---- - * .... .... FF.. .... .... - */ - -#define GPIO_SPEED_SHIFT (10) /* Bits 10-11: GPIO frequency selection */ -#define GPIO_SPEED_MASK (3 << GPIO_SPEED_SHIFT) -# define GPIO_SPEED_2MHZ (0 << GPIO_SPEED_SHIFT) /* 2 MHz Low speed output */ -# define GPIO_SPEED_25MHZ (1 << GPIO_SPEED_SHIFT) /* 25 MHz Medium speed output */ -# define GPIO_SPEED_50MHZ (2 << GPIO_SPEED_SHIFT) /* 50 MHz High speed output */ -# define GPIO_SPEED_100MHZ (3 << GPIO_SPEED_SHIFT) /* 100 MHz Very High speed output */ - -/* Output/Alt function type selection: - * - * 1111 1111 1100 0000 0000 - * 9876 5432 1098 7654 3210 - * ---- ---- ---- ---- ---- - * .... .... ..O. .... .... - */ - -#define GPIO_OPENDRAIN (1 << 9) /* Bit9: 1=Open-drain output */ -#define GPIO_PUSHPULL (0) /* Bit9: 0=Push-pull output */ - -/* If the pin is a GPIO digital output, then this identifies the initial - * output value. If the pin is an input, this bit is overloaded to provide - * the qualifier to distinguish input pull-up and -down: - * - * 1111 1111 1100 0000 0000 - * 9876 5432 1098 7654 3210 - * ---- ---- ---- ---- ---- - * .... .... ...V .... .... - */ - -#define GPIO_OUTPUT_SET (1 << 8) /* Bit 8: If output, initial value of output */ -#define GPIO_OUTPUT_CLEAR (0) - -/* External interrupt selection (GPIO inputs only): - * - * 1111 1111 1100 0000 0000 - * 9876 5432 1098 7654 3210 - * ---- ---- ---- ---- ---- - * .... .... ...X .... .... - */ - -#define GPIO_EXTI (1 << 8) /* Bit 8: Configure as EXTI interrupt */ - -/* This identifies the GPIO port: - * - * 1111 1111 1100 0000 0000 - * 9876 5432 1098 7654 3210 - * ---- ---- ---- ---- ---- - * .... .... .... PPPP .... - */ - -#define GPIO_PORT_SHIFT (4) /* Bit 4-7: Port number */ -#define GPIO_PORT_MASK (15 << GPIO_PORT_SHIFT) -# define GPIO_PORTA (0 << GPIO_PORT_SHIFT) /* GPIOA */ -# define GPIO_PORTB (1 << GPIO_PORT_SHIFT) /* GPIOB */ -# define GPIO_PORTC (2 << GPIO_PORT_SHIFT) /* GPIOC */ -# define GPIO_PORTD (3 << GPIO_PORT_SHIFT) /* GPIOD */ -# define GPIO_PORTE (4 << GPIO_PORT_SHIFT) /* GPIOE */ -# define GPIO_PORTF (5 << GPIO_PORT_SHIFT) /* GPIOF */ -# define GPIO_PORTG (6 << GPIO_PORT_SHIFT) /* GPIOG */ -# define GPIO_PORTH (7 << GPIO_PORT_SHIFT) /* GPIOH */ -# define GPIO_PORTI (8 << GPIO_PORT_SHIFT) /* GPIOI*/ - -/* This identifies the bit in the port: - * - * 1111 1111 1100 0000 0000 - * 9876 5432 1098 7654 3210 - * ---- ---- ---- ---- ---- - * .... .... .... .... BBBB - */ - -#define GPIO_PIN_SHIFT (0) /* Bits 0-3: GPIO number: 0-15 */ -#define GPIO_PIN_MASK (15 << GPIO_PIN_SHIFT) -# define GPIO_PIN0 (0 << GPIO_PIN_SHIFT) -# define GPIO_PIN1 (1 << GPIO_PIN_SHIFT) -# define GPIO_PIN2 (2 << GPIO_PIN_SHIFT) -# define GPIO_PIN3 (3 << GPIO_PIN_SHIFT) -# define GPIO_PIN4 (4 << GPIO_PIN_SHIFT) -# define GPIO_PIN5 (5 << GPIO_PIN_SHIFT) -# define GPIO_PIN6 (6 << GPIO_PIN_SHIFT) -# define GPIO_PIN7 (7 << GPIO_PIN_SHIFT) -# define GPIO_PIN8 (8 << GPIO_PIN_SHIFT) -# define GPIO_PIN9 (9 << GPIO_PIN_SHIFT) -# define GPIO_PIN10 (10 << GPIO_PIN_SHIFT) -# define GPIO_PIN11 (11 << GPIO_PIN_SHIFT) -# define GPIO_PIN12 (12 << GPIO_PIN_SHIFT) -# define GPIO_PIN13 (13 << GPIO_PIN_SHIFT) -# define GPIO_PIN14 (14 << GPIO_PIN_SHIFT) -# define GPIO_PIN15 (15 << GPIO_PIN_SHIFT) - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/* Base addresses for each GPIO block */ - -EXTERN const uint32_t g_gpiobase[STM32_NPORTS]; - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_configgpio - * - * Description: - * Configure a GPIO pin based on bit-encoded description of the pin. - * Once it is configured as Alternative (GPIO_ALT|GPIO_CNF_AFPP|...) - * function, it must be unconfigured with stm32_unconfiggpio() with - * the same cfgset first before it can be set to non-alternative function. - * - * Returned Value: - * OK on success - * ERROR on invalid port, or when pin is locked as ALT function. - * - ****************************************************************************/ - -int stm32_configgpio(uint32_t cfgset); - -/**************************************************************************** - * Name: stm32_unconfiggpio - * - * Description: - * Unconfigure a GPIO pin based on bit-encoded description of the pin, set - * it into default HiZ state (and possibly mark it's unused) and unlock it - * whether it was previously selected as alternative function - * (GPIO_ALT|GPIO_CNF_AFPP|...). - * - * This is a safety function and prevents hardware from shocks, as - * unexpected write to the Timer Channel Output GPIO to fixed '1' or '0' - * while it should operate in PWM mode could produce excessive on-board - * currents and trigger over-current/alarm function. - * - * Returned Value: - * OK on success - * ERROR on invalid port - * - ****************************************************************************/ - -int stm32_unconfiggpio(uint32_t cfgset); - -/**************************************************************************** - * Name: stm32_gpiowrite - * - * Description: - * Write one or zero to the selected GPIO pin - * - ****************************************************************************/ - -void stm32_gpiowrite(uint32_t pinset, bool value); - -/**************************************************************************** - * Name: stm32_gpioread - * - * Description: - * Read one or zero from the selected GPIO pin - * - ****************************************************************************/ - -bool stm32_gpioread(uint32_t pinset); - -/**************************************************************************** - * Name: stm32_gpiosetevent - * - * Description: - * Sets/clears GPIO based event and interrupt triggers. - * - * Input Parameters: - * pinset - GPIO pin configuration - * risingedge - Enables interrupt on rising edges - * fallingedge - Enables interrupt on falling edges - * event - Generate event when set - * func - When non-NULL, generate interrupt - * arg - Argument passed to the interrupt callback - * - * Returned Value: - * Zero (OK) is returned on success, otherwise a negated errno value is - * returned to indicate the nature of the failure. - * - ****************************************************************************/ - -int stm32_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, - bool event, xcpt_t func, void *arg); - -/**************************************************************************** - * Function: stm32_gpioinit - * - * Description: - * Based on configuration within the .config file, it does: - * - Remaps positions of alternative functions. - * - * Typically called from stm32h5_start(). - * - ****************************************************************************/ - -void stm32_gpioinit(void); - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32H5_STM32_GPIO_H */