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stm32: Add workaround for flash data cache corruption on read-while-write
This is a know hardware issue on some STM32 see the errata of your model and if you make use of both memory banks you should enable it.
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2 changed files with 29 additions and 0 deletions
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@ -2633,6 +2633,12 @@ config STM32_FLASH_PREFETCH
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on F1 parts). Some early revisions of F4 parts do not support FLASH pre-fetch
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properly and enabling this option may interfere with ADC accuracy.
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config STM32_FLASH_WORKAROUND_DATA_CACHE_CORRUPTION_ON_RWW
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bool "Enable the workaround to fix flash data cache corruption when reading from one flash bank while writing on other flash bank"
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default n
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---help---
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See your STM32 errata to check if your STM32 is affected by this problem.
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choice
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prompt "JTAG Configuration"
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default STM32_JTAG_DISABLE
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@ -130,6 +130,20 @@ static void flash_lock(void)
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modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_LOCK);
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}
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static void data_cache_disable(void)
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{
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modifyreg32(STM32_FLASH_ACR, FLASH_ACR_DCEN, 0);
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}
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static void data_cache_enable(void)
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{
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/* reset data cache */
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modifyreg32(STM32_FLASH_ACR, 0, FLASH_ACR_DCRST);
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/* enable data cache */
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modifyreg32(STM32_FLASH_ACR, 0, FLASH_ACR_DCEN);
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}
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/************************************************************************************
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* Public Functions
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************************************************************************************/
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@ -384,6 +398,10 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t count)
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flash_unlock();
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#if defined(CONFIG_STM32_FLASH_WORKAROUND_DATA_CACHE_CORRUPTION_ON_RWW)
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data_cache_disable();
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#endif
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modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_PG);
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#if defined(CONFIG_STM32_STM32F40XX)
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@ -417,6 +435,11 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t count)
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}
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modifyreg32(STM32_FLASH_CR, FLASH_CR_PG, 0);
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#if defined(CONFIG_STM32_FLASH_WORKAROUND_DATA_CACHE_CORRUPTION_ON_RWW)
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data_cache_enable();
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#endif
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sem_unlock();
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return written;
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}
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