diff --git a/arch/avr/src/avrdx/Kconfig b/arch/avr/src/avrdx/Kconfig index b3e630204b3..a2fe57d9618 100644 --- a/arch/avr/src/avrdx/Kconfig +++ b/arch/avr/src/avrdx/Kconfig @@ -8,17 +8,55 @@ comment "AVR DA/DB Configuration Options" # Hidden configuration options selected by specific chip # Available serial ports -config AVR_HAS_USART_2 +config AVR_HAVE_USART_2 bool default n + ---help--- + Chip has USART 2 (and also 0 and 1) -config AVR_HAS_USART_4 +config AVR_HAVE_USART_4 bool default n + ---help--- + Chip has USART 4 (and also 3) -config AVR_HAS_USART_5 +config AVR_HAVE_USART_5 bool default n + ---help--- + Chip has USART 5 + +# Available alternate pinouts for serial ports +# USART0 omitted, all chips have that +config AVR_HAVE_USART1_ALT1 + bool + default n + ---help--- + Chip has alternate pin position for USART 1 + +config AVR_HAVE_USART2_ALT1 + bool + default n + ---help--- + Chip has alternate pin position for USART 2 + +config AVR_HAVE_USART3_ALT1 + bool + default n + ---help--- + Chip has alternate pin position for USART 3 + +config AVR_HAVE_USART4_ALT1 + bool + default n + ---help--- + Chip has alternate pin position for USART 4 + +config AVR_HAVE_USART5_ALT1 + bool + default n + ---help--- + Chip has alternate pin position for USART 5 # Available I/O ports (only those not common for all devices) config AVR_HAS_PORTB @@ -40,16 +78,21 @@ choice config ARCH_CHIP_AVR128DA28 bool "AVR128DA28" select AVR_HAS_RAMPZ - select AVR_HAS_USART_2 + select AVR_HAVE_USART_2 ---help--- Atmel AVR128DA28 8-bit AVR. config ARCH_CHIP_AVR128DA64 bool "AVR128DA64" select AVR_HAS_RAMPZ - select AVR_HAS_USART_2 - select AVR_HAS_USART_4 - select AVR_HAS_USART_5 + select AVR_HAVE_USART_2 + select AVR_HAVE_USART1_ALT1 + select AVR_HAVE_USART2_ALT1 + select AVR_HAVE_USART_4 + select AVR_HAVE_USART3_ALT1 + select AVR_HAVE_USART4_ALT1 + select AVR_HAVE_USART_5 + select AVR_HAVE_USART5_ALT1 select AVR_HAS_PORTB select AVR_HAS_PORTE select AVR_HAS_PORTG @@ -59,9 +102,14 @@ config ARCH_CHIP_AVR128DA64 config ARCH_CHIP_AVR128DB64 bool "AVR128DB64" select AVR_HAS_RAMPZ - select AVR_HAS_USART_2 - select AVR_HAS_USART_4 - select AVR_HAS_USART_5 + select AVR_HAVE_USART_2 + select AVR_HAVE_USART1_ALT1 + select AVR_HAVE_USART2_ALT1 + select AVR_HAVE_USART_4 + select AVR_HAVE_USART3_ALT1 + select AVR_HAVE_USART4_ALT1 + select AVR_HAVE_USART_5 + select AVR_HAVE_USART5_ALT1 select AVR_HAS_PORTB select AVR_HAS_PORTE select AVR_HAS_PORTG @@ -87,98 +135,199 @@ config AVR_USART0 bool "Enable serial driver for USART0" select USART0_SERIALDRIVER select ARCH_HAVE_SERIAL_TERMIOS - depends on AVR_HAS_USART_2 + depends on AVR_HAVE_USART_2 depends on SERIAL ---help--- Enable serial driver on USART0 -config AVR_USART0_ALT - bool "Activate USART0 alternative pinout" +choice AVR_USART0_MUX + prompt "USART0 pin selection" depends on AVR_USART0 + default AVR_USART0_DEFAULT + ---help--- + Select which I/O pins will be driven by USART0 interface. + Refer to I/O Multiplexing and Port Multiplexer sections + in chip documentation for specifics. + +config AVR_USART0_DEFAULT + bool "Default USART0 pinout" + +config AVR_USART0_ALT + bool "Alternate USART0 pinout" ---help--- Board is wired to use alternative I/O pins, 4-5 instead of 0-1 for TxD/RxD +config AVR_USART0_NONE + bool "Not connected" + +endchoice + config AVR_USART1 bool "Enable serial driver for USART1" select USART1_SERIALDRIVER select ARCH_HAVE_SERIAL_TERMIOS - depends on AVR_HAS_USART_2 + depends on AVR_HAVE_USART_2 depends on SERIAL ---help--- Enable serial driver on USART1 -config AVR_USART1_ALT - bool "Activate USART1 alternative pinout" +choice AVR_USART1_MUX + prompt "USART1 pin selection" depends on AVR_USART1 + default AVR_USART1_DEFAULT + ---help--- + Select which I/O pins will be driven by USART1 interface. + Refer to I/O Multiplexing and Port Multiplexer sections + in chip documentation for specifics. + +config AVR_USART1_DEFAULT + bool "Default USART1 pinout" + +config AVR_USART1_ALT + depends on AVR_HAVE_USART1_ALT1 + bool "Alternate USART1 pinout" ---help--- Board is wired to use alternative I/O pins, 4-5 instead of 0-1 for TxD/RxD +config AVR_USART1_NONE + bool "Not connected" + +endchoice + config AVR_USART2 bool "Enable serial driver for USART2" select USART2_SERIALDRIVER select ARCH_HAVE_SERIAL_TERMIOS - depends on AVR_HAS_USART_2 + depends on AVR_HAVE_USART_2 depends on SERIAL ---help--- Enable serial driver on USART2 -config AVR_USART2_ALT - bool "Activate USART2 alternative pinout" +choice AVR_USART2_MUX + prompt "USART2 pin selection" depends on AVR_USART2 + default AVR_USART2_DEFAULT + ---help--- + Select which I/O pins will be driven by USART2 interface. + Refer to I/O Multiplexing and Port Multiplexer sections + in chip documentation for specifics. + +config AVR_USART2_DEFAULT + bool "Default USART2 pinout" + +config AVR_USART2_ALT + depends on AVR_HAVE_USART2_ALT1 + bool "Alternate USART2 pinout" ---help--- Board is wired to use alternative I/O pins, 4-5 instead of 0-1 for TxD/RxD +config AVR_USART2_NONE + bool "Not connected" + +endchoice + config AVR_USART3 bool "Enable serial driver for USART3" select USART3_SERIALDRIVER select ARCH_HAVE_SERIAL_TERMIOS - depends on AVR_HAS_USART_4 + depends on AVR_HAVE_USART_4 depends on SERIAL ---help--- Enable serial driver on USART3 -config AVR_USART3_ALT - bool "Activate USART3 alternative pinout" +choice AVR_USART3_MUX + prompt "USART3 pin selection" depends on AVR_USART3 + default AVR_USART3_DEFAULT + ---help--- + Select which I/O pins will be driven by USART3 interface. + Refer to I/O Multiplexing and Port Multiplexer sections + in chip documentation for specifics. + +config AVR_USART3_DEFAULT + bool "Default USART3 pinout" + +config AVR_USART3_ALT + depends on AVR_HAVE_USART3_ALT1 + bool "Alternate USART3 pinout" ---help--- Board is wired to use alternative I/O pins, 4-5 instead of 0-1 for TxD/RxD +config AVR_USART3_NONE + bool "Not connected" + +endchoice + config AVR_USART4 bool "Enable serial driver for USART4" select USART4_SERIALDRIVER select ARCH_HAVE_SERIAL_TERMIOS - depends on AVR_HAS_USART_4 + depends on AVR_HAVE_USART_4 depends on SERIAL ---help--- Enable serial driver on USART1 -config AVR_USART4_ALT - bool "Activate USART4 alternative pinout" +choice AVR_USART4_MUX + prompt "USART4 pin selection" depends on AVR_USART4 + default AVR_USART4_DEFAULT + ---help--- + Select which I/O pins will be driven by USART4 interface. + Refer to I/O Multiplexing and Port Multiplexer sections + in chip documentation for specifics. + +config AVR_USART4_DEFAULT + bool "Default USART4 pinout" + +config AVR_USART4_ALT + depends on AVR_HAVE_USART4_ALT1 + bool "Alternate USART4 pinout" ---help--- Board is wired to use alternative I/O pins, 4-5 instead of 0-1 for TxD/RxD +config AVR_USART4_NONE + bool "Not connected" + +endchoice + config AVR_USART5 bool "Enable serial driver for USART5" select USART5_SERIALDRIVER select ARCH_HAVE_SERIAL_TERMIOS - depends on AVR_HAS_USART_5 + depends on AVR_HAVE_USART_5 depends on SERIAL ---help--- Enable serial driver on USART5 -config AVR_USART5_ALT - bool "Activate USART5 alternative pinout" +choice AVR_USART5_MUX + prompt "USART5 pin selection" depends on AVR_USART5 + default AVR_USART5_DEFAULT + ---help--- + Select which I/O pins will be driven by USART5 interface. + Refer to I/O Multiplexing and Port Multiplexer sections + in chip documentation for specifics. + +config AVR_USART5_DEFAULT + bool "Default USART5 pinout" + +config AVR_USART5_ALT + depends on AVR_HAVE_USART5_ALT1 + bool "Alternate USART5 pinout" ---help--- Board is wired to use alternative I/O pins, 4-5 instead of 0-1 for TxD/RxD +config AVR_USART5_NONE + bool "Not connected" + +endchoice + endmenu # AVR DA/DB Peripheral Selections choice diff --git a/arch/avr/src/avrdx/avrdx_lowconsole.c b/arch/avr/src/avrdx/avrdx_lowconsole.c index 64dc9da05e7..7cc95fb0290 100644 --- a/arch/avr/src/avrdx/avrdx_lowconsole.c +++ b/arch/avr/src/avrdx/avrdx_lowconsole.c @@ -65,7 +65,7 @@ #ifdef CONFIG_MCU_SERIAL static const IOBJ uint32_t avrdx_usart_baud[] = { -# ifdef CONFIG_AVR_HAS_USART_2 +# ifdef CONFIG_AVR_HAVE_USART_2 # if defined(CONFIG_USART0_SERIALDRIVER) CONFIG_USART0_BAUD, @@ -85,9 +85,9 @@ static const IOBJ uint32_t avrdx_usart_baud[] = 0 # endif - # endif /* ifdef CONFIG_AVR_HAS_USART_2 */ + # endif /* ifdef CONFIG_AVR_HAVE_USART_2 */ -# ifdef CONFIG_AVR_HAS_USART_4 +# ifdef CONFIG_AVR_HAVE_USART_4 # if defined(CONFIG_USART3_SERIALDRIVER) , CONFIG_USART3_BAUD # else @@ -98,15 +98,15 @@ static const IOBJ uint32_t avrdx_usart_baud[] = # else , 0 # endif -# endif /* ifdef CONFIG_AVR_HAS_USART_4 */ +# endif /* ifdef CONFIG_AVR_HAVE_USART_4 */ -# ifdef CONFIG_AVR_HAS_USART_5 +# ifdef CONFIG_AVR_HAVE_USART_5 # if defined(CONFIG_USART5_SERIALDRIVER) , CONFIG_USART5_BAUD # else , 0 # endif -# endif /* ifdef CONFIG_AVR_HAS_USART_5 */ +# endif /* ifdef CONFIG_AVR_HAVE_USART_5 */ }; /* Peripheral settings for USARTn.CTRLC. Combined from multiple Kconfig @@ -115,7 +115,7 @@ static const IOBJ uint32_t avrdx_usart_baud[] = static const IOBJ uint8_t avrdx_usart_ctrlc[] = { -# ifdef CONFIG_AVR_HAS_USART_2 +# ifdef CONFIG_AVR_HAVE_USART_2 /* USART0 */ @@ -219,11 +219,11 @@ static const IOBJ uint8_t avrdx_usart_ctrlc[] = 0 # endif /* if defined(CONFIG_USART2_SERIALDRIVER) */ -# endif /* ifdef CONFIG_AVR_HAS_USART_2 */ +# endif /* ifdef CONFIG_AVR_HAVE_USART_2 */ /* Definitions for chips that have USART4 */ -# ifdef CONFIG_AVR_HAS_USART_4 +# ifdef CONFIG_AVR_HAVE_USART_4 /* USART3 */ @@ -293,11 +293,11 @@ static const IOBJ uint8_t avrdx_usart_ctrlc[] = , 0 # endif /* if defined(CONFIG_USART4_SERIALDRIVER) */ -# endif /* ifdef CONFIG_AVR_HAS_USART_4 */ +# endif /* ifdef CONFIG_AVR_HAVE_USART_4 */ /* Definitions for chips that have USART5 */ -# ifdef CONFIG_AVR_HAS_USART_5 +# ifdef CONFIG_AVR_HAVE_USART_5 /* USART5 */ @@ -333,7 +333,7 @@ static const IOBJ uint8_t avrdx_usart_ctrlc[] = , 0 # endif /* if defined(CONFIG_USART5_SERIALDRIVER) */ -# endif /* ifdef CONFIG_AVR_HAS_USART_5 */ +# endif /* ifdef CONFIG_AVR_HAVE_USART_5 */ }; #endif /* ifdef CONFIG_MCU_SERIAL */ @@ -406,6 +406,7 @@ void avrdx_usart_reset(struct avrdx_uart_priv_s *priv) void avrdx_usart_configure(struct avrdx_uart_priv_s *priv) { + volatile uint8_t *portmux_reg; irqstate_t irqstate; uint32_t baud_temp; /* Being calculated, needs 32 bits */ uint32_t temp32; @@ -471,7 +472,33 @@ void avrdx_usart_configure(struct avrdx_uart_priv_s *priv) usart->CTRLC = avrdx_usart_ctrlc[priv->usart_n]; - /* 3. configure TXD pin as output */ + /* 3. configure port multiplexer and set TXD pin as output */ + +# ifdef PORTMUX_USARTROUTEB + if (priv->usart_n < 4) +# endif + { + portmux_reg = &(PORTMUX.USARTROUTEA); + } +# ifdef PORTMUX_USARTROUTEB + else + { + portmux_reg = &(PORTMUX.USARTROUTEB); + } +# endif + + /* In theory, only the kernel should manipulate this register + * and the value written is static (chosen by configuration.) + * That means there should be no need to reset it. Still doing it, + * runaway application may do accidental writes. + */ + + *(portmux_reg) = \ + (\ + *(portmux_reg) & \ + ~(avrdx_usart_portmux_masks[priv->usart_n]) \ + ) | \ + avrdx_usart_portmux_bits[priv->usart_n]; AVRDX_USART_PORT(priv->usart_n).DIRSET = \ avrdx_usart_tx_pins[priv->usart_n]; diff --git a/arch/avr/src/avrdx/avrdx_peripherals.c b/arch/avr/src/avrdx/avrdx_peripherals.c index 92639a73403..a7442280f39 100644 --- a/arch/avr/src/avrdx/avrdx_peripherals.c +++ b/arch/avr/src/avrdx/avrdx_peripherals.c @@ -78,16 +78,16 @@ static const IOBJ uint8_t avrdx_main_pdiv[] = \ const IOBJ uint8_t avrdx_usart_ports[] = { -# ifdef CONFIG_AVR_HAS_USART_2 +# ifdef CONFIG_AVR_HAVE_USART_2 AVRDX_GPIO_PORTA_IDX, /* A, C, F */ AVRDX_GPIO_PORTC_IDX, AVRDX_GPIO_PORTF_IDX # endif -# ifdef CONFIG_AVR_HAS_USART_4 +# ifdef CONFIG_AVR_HAVE_USART_4 , AVRDX_GPIO_PORTB_IDX /* B, E */ , AVRDX_GPIO_PORTE_IDX # endif -# ifdef CONFIG_AVR_HAS_USART_5 +# ifdef CONFIG_AVR_HAVE_USART_5 , AVRDX_GPIO_PORTG_IDX /* port G */ # endif }; @@ -100,7 +100,7 @@ const IOBJ uint8_t avrdx_usart_ports[] = const IOBJ uint8_t avrdx_usart_tx_pins[] = { -# ifdef CONFIG_AVR_HAS_USART_2 +# ifdef CONFIG_AVR_HAVE_USART_2 # if !defined(CONFIG_AVR_USART0_ALT) PIN0_bm , # else @@ -118,7 +118,7 @@ const IOBJ uint8_t avrdx_usart_tx_pins[] = # endif # endif -# ifdef CONFIG_AVR_HAS_USART_4 +# ifdef CONFIG_AVR_HAVE_USART_4 # if !defined(CONFIG_AVR_USART3_ALT) , PIN0_bm # else @@ -131,7 +131,7 @@ const IOBJ uint8_t avrdx_usart_tx_pins[] = # endif # endif -# ifdef CONFIG_AVR_HAS_USART_5 +# ifdef CONFIG_AVR_HAVE_USART_5 # if !defined(CONFIG_AVR_USART5_ALT) , PIN0_bm # else @@ -175,6 +175,127 @@ const IOBJ uint8_t avrdx_gpio_irq_vectors[] = #endif }; +/* This array holds bits to be set in PORTMUX.USARTROUTEx registers + * depending on if the alternate pin position was configured. + * (Index is port index.) + */ + +const IOBJ uint8_t avrdx_usart_portmux_bits[] = +{ +# ifdef CONFIG_AVR_HAVE_USART_2 + +# ifdef CONFIG_AVR_USART0 +# if defined(CONFIG_AVR_USART0_DEFAULT) + PORTMUX_USART0_DEFAULT_GC, +# elif defined(CONFIG_AVR_USART0_ALT) + PORTMUX_USART0_ALT1_GC, +# elif defined(CONFIG_AVR_USART0_NONE) + PORTMUX_USART0_NONE_GC, +# else +# error Kconfig error, no option is set +# endif +# else /* AVR_USART0 not active, value will not be used */ + PORTMUX_USART0_DEFAULT_GC, +# endif + +# ifdef CONFIG_AVR_USART1 +# if defined(CONFIG_AVR_USART1_DEFAULT) + PORTMUX_USART1_DEFAULT_GC, +# elif defined(CONFIG_AVR_USART1_ALT) + PORTMUX_USART1_ALT1_GC, +# elif defined(CONFIG_AVR_USART1_NONE) + PORTMUX_USART1_NONE_GC, +# else +# error Kconfig error, no option is set +# endif +# else /* AVR_USART1 not active, value will not be used */ + PORTMUX_USART1_DEFAULT_GC, +# endif + +# ifdef CONFIG_AVR_USART2 +# if defined(CONFIG_AVR_USART2_DEFAULT) + PORTMUX_USART2_DEFAULT_GC +# elif defined(CONFIG_AVR_USART2_ALT) + PORTMUX_USART2_ALT1_GC +# elif defined(CONFIG_AVR_USART2_NONE) + PORTMUX_USART2_NONE_GC +# else +# error Kconfig error, no option is set +# endif +# else /* AVR_USART2 not active, value will not be used */ + PORTMUX_USART2_DEFAULT_GC +# endif + +# endif /* ifdef CONFIG_AVR_HAVE_USART_2 */ + +# ifdef CONFIG_AVR_HAVE_USART_4 + +# ifdef CONFIG_AVR_USART3 +# if defined(CONFIG_AVR_USART3_DEFAULT) + , PORTMUX_USART3_DEFAULT_GC +# elif defined(CONFIG_AVR_USART3_ALT) + , PORTMUX_USART3_ALT1_GC +# elif defined(CONFIG_AVR_USART3_NONE) + , PORTMUX_USART3_NONE_GC +# else +# error Kconfig error, no option is set +# endif +# else /* AVR_USART3 not active, value will not be used */ + , PORTMUX_USART3_DEFAULT_GC +# endif + +# ifdef CONFIG_AVR_USART4 +# if defined(CONFIG_AVR_USART4_DEFAULT) + , PORTMUX_USART4_DEFAULT_GC +# elif defined(CONFIG_AVR_USART4_ALT) + , PORTMUX_USART4_ALT1_GC +# elif defined(CONFIG_AVR_USART4_NONE) + , PORTMUX_USART4_NONE_GC +# else +# error Kconfig error, no option is set +# endif +# else /* AVR_USART4 not active, value will not be used */ + , PORTMUX_USART4_DEFAULT_GC +# endif + +# endif /* ifdef CONFIG_AVR_HAVE_USART_4 */ + +# ifdef CONFIG_AVR_HAVE_USART_5 + +# ifdef CONFIG_AVR_USART5 +# if defined(CONFIG_AVR_USART5_DEFAULT) + , PORTMUX_USART5_DEFAULT_GC +# elif defined(CONFIG_AVR_USART5_ALT) + , PORTMUX_USART5_ALT1_GC +# elif defined(CONFIG_AVR_USART5_NONE) + , PORTMUX_USART5_NONE_GC +# else +# error Kconfig error, no option is set +# endif +# else /* AVR_USART5 not active, value will not be used */ + , PORTMUX_USART5_DEFAULT_GC +# endif + +# endif /* ifdef CONFIG_AVR_HAVE_USART_5 */ +}; + +/* This array holds masks for bits affecting specific USART + * peripheral in PORTMUX.USARTROUTEx registers. (Index is port index.) + */ + +const IOBJ uint8_t avrdx_usart_portmux_masks[] = +{ +# ifdef CONFIG_AVR_HAVE_USART_2 + PORTMUX_USART0_GM, PORTMUX_USART1_GM, PORTMUX_USART2_GM +# endif +# ifdef CONFIG_AVR_HAVE_USART_4 + , PORTMUX_USART3_GM, PORTMUX_USART4_GM +# endif +# ifdef CONFIG_AVR_HAVE_USART_5 + , PORTMUX_USART5_GM +# endif +}; + /**************************************************************************** * Private Functions ****************************************************************************/ diff --git a/arch/avr/src/avrdx/avrdx_serial.c b/arch/avr/src/avrdx/avrdx_serial.c index 308b960949a..ee559c02ccc 100644 --- a/arch/avr/src/avrdx/avrdx_serial.c +++ b/arch/avr/src/avrdx/avrdx_serial.c @@ -156,13 +156,13 @@ static bool avrdx_usart_txempty(struct uart_dev_s *dev); static const IOBJ uint8_t avrdx_usart_rx_interrupts[] = { -# ifdef CONFIG_AVR_HAS_USART_2 +# ifdef CONFIG_AVR_HAVE_USART_2 AVRDX_IRQ_USART0_RXC, AVRDX_IRQ_USART1_RXC, AVRDX_IRQ_USART2_RXC # endif -# ifdef CONFIG_AVR_HAS_USART_4 +# ifdef CONFIG_AVR_HAVE_USART_4 , AVRDX_IRQ_USART3_RXC, AVRDX_IRQ_USART4_RXC # endif -# ifdef CONFIG_AVR_HAS_USART_5 +# ifdef CONFIG_AVR_HAVE_USART_5 , AVRDX_IRQ_USART5_RXC # endif }; @@ -171,13 +171,13 @@ static const IOBJ uint8_t avrdx_usart_rx_interrupts[] = static const IOBJ uint8_t avrdx_usart_dre_interrupts[] = { -# ifdef CONFIG_AVR_HAS_USART_2 +# ifdef CONFIG_AVR_HAVE_USART_2 AVRDX_IRQ_USART0_DRE, AVRDX_IRQ_USART1_DRE, AVRDX_IRQ_USART2_DRE # endif -# ifdef CONFIG_AVR_HAS_USART_4 +# ifdef CONFIG_AVR_HAVE_USART_4 , AVRDX_IRQ_USART3_DRE, AVRDX_IRQ_USART4_DRE # endif -# ifdef CONFIG_AVR_HAS_USART_5 +# ifdef CONFIG_AVR_HAVE_USART_5 , AVRDX_IRQ_USART5_DRE # endif }; @@ -221,11 +221,11 @@ static const struct uart_ops_s g_usart_ops = */ # ifdef CONFIG_MCU_SERIAL -# if defined(CONFIG_AVR_HAS_USART_5) +# if defined(CONFIG_AVR_HAVE_USART_5) static uart_dev_t *g_usart_ports[6]; -# elif defined(CONFIG_AVR_HAS_USART_4) +# elif defined(CONFIG_AVR_HAVE_USART_4) static uart_dev_t *g_usart_ports[5]; -# elif defined(CONFIG_AVR_HAS_USART_2) +# elif defined(CONFIG_AVR_HAVE_USART_2) static uart_dev_t *g_usart_ports[3]; # endif # endif diff --git a/arch/avr/src/avrdx/avrdx_serial.h b/arch/avr/src/avrdx/avrdx_serial.h index b231fecf80e..27ec7c52998 100644 --- a/arch/avr/src/avrdx/avrdx_serial.h +++ b/arch/avr/src/avrdx/avrdx_serial.h @@ -89,6 +89,8 @@ extern "C" EXTERN const IOBJ uint8_t avrdx_usart_ports[]; EXTERN const IOBJ uint8_t avrdx_usart_tx_pins[]; +EXTERN const IOBJ uint8_t avrdx_usart_portmux_bits[]; +EXTERN const IOBJ uint8_t avrdx_usart_portmux_masks[]; #endif diff --git a/arch/avr/src/avrdx/iodefs/avr128da28.h b/arch/avr/src/avrdx/iodefs/avr128da28.h index 53b0a7fc376..554bf88dc3b 100644 --- a/arch/avr/src/avrdx/iodefs/avr128da28.h +++ b/arch/avr/src/avrdx/iodefs/avr128da28.h @@ -37,6 +37,21 @@ # error "Do not include this file directly, use avrdx_iodefs.h instead" #endif +/* PORTMUX.USARTROUTEA */ + +#define PORTMUX_USART0_DEFAULT_GC (0) +#define PORTMUX_USART0_ALT1_GC (PORTMUX_USART0_0_bm ) +#define PORTMUX_USART0_NONE_GC (PORTMUX_USART0_1_bm | PORTMUX_USART0_0_bm) +#define PORTMUX_USART0_GM (PORTMUX_USART0_1_bm | PORTMUX_USART0_0_bm) + +#define PORTMUX_USART1_DEFAULT_GC (0) +#define PORTMUX_USART1_NONE_GC (PORTMUX_USART1_1_bm | PORTMUX_USART1_0_bm) +#define PORTMUX_USART1_GM (PORTMUX_USART1_1_bm | PORTMUX_USART1_0_bm) + +#define PORTMUX_USART2_DEFAULT_GC (0) +#define PORTMUX_USART2_NONE_GC (PORTMUX_USART2_1_bm | PORTMUX_USART2_0_bm) +#define PORTMUX_USART2_GM (PORTMUX_USART2_1_bm | PORTMUX_USART2_0_bm) + /* PORT.PINCONFIG */ #define PORT_ISC_GM ( PORT_ISC_0_bm | PORT_ISC_1_bm | PORT_ISC_2_bm ) diff --git a/arch/avr/src/avrdx/iodefs/avr128da64.h b/arch/avr/src/avrdx/iodefs/avr128da64.h index a07b7990bb9..1996e7a1045 100644 --- a/arch/avr/src/avrdx/iodefs/avr128da64.h +++ b/arch/avr/src/avrdx/iodefs/avr128da64.h @@ -37,6 +37,40 @@ # error "Do not include this file directly, use avrdx_iodefs.h instead" #endif +/* PORTMUX.USARTROUTEA */ + +#define PORTMUX_USART0_DEFAULT_GC (0) +#define PORTMUX_USART0_ALT1_GC (PORTMUX_USART0_0_bm ) +#define PORTMUX_USART0_NONE_GC (PORTMUX_USART0_1_bm | PORTMUX_USART0_0_bm) +#define PORTMUX_USART0_GM (PORTMUX_USART0_1_bm | PORTMUX_USART0_0_bm) + +#define PORTMUX_USART1_DEFAULT_GC (0) +#define PORTMUX_USART1_ALT1_GC (PORTMUX_USART1_0_bm) +#define PORTMUX_USART1_NONE_GC (PORTMUX_USART1_1_bm | PORTMUX_USART1_0_bm) +#define PORTMUX_USART1_GM (PORTMUX_USART1_1_bm | PORTMUX_USART1_0_bm) + +#define PORTMUX_USART2_DEFAULT_GC (0) +#define PORTMUX_USART2_ALT1_gc (PORTMUX_USART2_0_bm) +#define PORTMUX_USART2_NONE_GC (PORTMUX_USART2_1_bm | PORTMUX_USART2_0_bm) +#define PORTMUX_USART2_GM (PORTMUX_USART2_1_bm | PORTMUX_USART2_0_bm) + +#define PORTMUX_USART3_DEFAULT_GC (0) +#define PORTMUX_USART3_ALT1_GC (PORTMUX_USART3_0_bm) +#define PORTMUX_USART3_NONE_GC (PORTMUX_USART3_1_bm | PORTMUX_USART3_0_bm) +#define PORTMUX_USART3_GM (PORTMUX_USART3_1_bm | PORTMUX_USART3_0_bm) + +/* PORTMUX.USARTROUTEB */ + +#define PORTMUX_USART4_DEFAULT_GC (0) +#define PORTMUX_USART4_ALT1_GC (PORTMUX_USART4_0_bm) +#define PORTMUX_USART4_NONE_GC (PORTMUX_USART4_1_bm | PORTMUX_USART4_0_bm) +#define PORTMUX_USART4_GM (PORTMUX_USART4_1_bm | PORTMUX_USART4_0_bm) + +#define PORTMUX_USART5_DEFAULT_GC (0) +#define PORTMUX_USART5_ALT1_GC (PORTMUX_USART5_0_bm) +#define PORTMUX_USART5_NONE_GC (PORTMUX_USART5_1_bm | PORTMUX_USART5_0_bm) +#define PORTMUX_USART5_GM (PORTMUX_USART5_1_bm | PORTMUX_USART5_0_bm) + /* PORT.PINCONFIG */ #define PORT_ISC_GM ( PORT_ISC_0_bm | PORT_ISC_1_bm | PORT_ISC_2_bm ) diff --git a/arch/avr/src/avrdx/iodefs/avr128db64.h b/arch/avr/src/avrdx/iodefs/avr128db64.h index aa94f9bc1dc..ba709c26b2f 100644 --- a/arch/avr/src/avrdx/iodefs/avr128db64.h +++ b/arch/avr/src/avrdx/iodefs/avr128db64.h @@ -37,6 +37,40 @@ # error "Do not include this file directly, use avrdx_iodefs.h instead" #endif +/* PORTMUX.USARTROUTEA */ + +#define PORTMUX_USART0_DEFAULT_GC (0) +#define PORTMUX_USART0_ALT1_GC (PORTMUX_USART0_0_bm ) +#define PORTMUX_USART0_NONE_GC (PORTMUX_USART0_1_bm | PORTMUX_USART0_0_bm) +#define PORTMUX_USART0_GM (PORTMUX_USART0_1_bm | PORTMUX_USART0_0_bm) + +#define PORTMUX_USART1_DEFAULT_GC (0) +#define PORTMUX_USART1_ALT1_GC (PORTMUX_USART1_0_bm) +#define PORTMUX_USART1_NONE_GC (PORTMUX_USART1_1_bm | PORTMUX_USART1_0_bm) +#define PORTMUX_USART1_GM (PORTMUX_USART1_1_bm | PORTMUX_USART1_0_bm) + +#define PORTMUX_USART2_DEFAULT_GC (0) +#define PORTMUX_USART2_ALT1_gc (PORTMUX_USART2_0_bm) +#define PORTMUX_USART2_NONE_GC (PORTMUX_USART2_1_bm | PORTMUX_USART2_0_bm) +#define PORTMUX_USART2_GM (PORTMUX_USART2_1_bm | PORTMUX_USART2_0_bm) + +#define PORTMUX_USART3_DEFAULT_GC (0) +#define PORTMUX_USART3_ALT1_GC (PORTMUX_USART3_0_bm) +#define PORTMUX_USART3_NONE_GC (PORTMUX_USART3_1_bm | PORTMUX_USART3_0_bm) +#define PORTMUX_USART3_GM (PORTMUX_USART3_1_bm | PORTMUX_USART3_0_bm) + +/* PORTMUX.USARTROUTEB */ + +#define PORTMUX_USART4_DEFAULT_GC (0) +#define PORTMUX_USART4_ALT1_GC (PORTMUX_USART4_0_bm) +#define PORTMUX_USART4_NONE_GC (PORTMUX_USART4_1_bm | PORTMUX_USART4_0_bm) +#define PORTMUX_USART4_GM (PORTMUX_USART4_1_bm | PORTMUX_USART4_0_bm) + +#define PORTMUX_USART5_DEFAULT_GC (0) +#define PORTMUX_USART5_ALT1_GC (PORTMUX_USART5_0_bm) +#define PORTMUX_USART5_NONE_GC (PORTMUX_USART5_1_bm | PORTMUX_USART5_0_bm) +#define PORTMUX_USART5_GM (PORTMUX_USART5_1_bm | PORTMUX_USART5_0_bm) + /* PORT.PINCONFIG */ #define PORT_ISC_GM ( PORT_ISC_0_bm | PORT_ISC_1_bm | PORT_ISC_2_bm )