From dc4ac48aad19b791247eef851c3d648cb19a5ada Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Tue, 14 Mar 2017 11:56:29 -0600 Subject: [PATCH 01/21] arch/arm/src/xmc4: Initial, partial support for Infineon XMC4xxx --- arch/arm/Kconfig | 16 + arch/arm/src/xmc4/Kconfig | 328 +++++++ arch/arm/src/xmc4/Make.defs | 141 +++ arch/arm/src/xmc4/chip.h | 77 ++ arch/arm/src/xmc4/xmc4_allocateheap.c | 193 +++++ arch/arm/src/xmc4/xmc4_clockconfig.c | 74 ++ arch/arm/src/xmc4/xmc4_clrpend.c | 102 +++ arch/arm/src/xmc4/xmc4_config.h | 198 +++++ arch/arm/src/xmc4/xmc4_dma.c | 0 arch/arm/src/xmc4/xmc4_dma.h | 218 +++++ arch/arm/src/xmc4/xmc4_gpio.c | 0 arch/arm/src/xmc4/xmc4_gpio.h | 0 arch/arm/src/xmc4/xmc4_i2c.c | 0 arch/arm/src/xmc4/xmc4_i2c.h | 87 ++ arch/arm/src/xmc4/xmc4_idle.c | 105 +++ arch/arm/src/xmc4/xmc4_irq.c | 588 +++++++++++++ arch/arm/src/xmc4/xmc4_lowputc.c | 235 +++++ arch/arm/src/xmc4/xmc4_mpuinit.c | 124 +++ arch/arm/src/xmc4/xmc4_mpuinit.h | 78 ++ arch/arm/src/xmc4/xmc4_pwm.c | 0 arch/arm/src/xmc4/xmc4_pwm.h | 100 +++ arch/arm/src/xmc4/xmc4_serial.c | 1146 +++++++++++++++++++++++++ arch/arm/src/xmc4/xmc4_spi.h | 165 ++++ arch/arm/src/xmc4/xmc4_start.c | 355 ++++++++ arch/arm/src/xmc4/xmc4_timerisr.c | 152 ++++ arch/arm/src/xmc4/xmc4_userspace.c | 107 +++ arch/arm/src/xmc4/xmc4_userspace.h | 64 ++ 27 files changed, 4653 insertions(+) create mode 100644 arch/arm/src/xmc4/Kconfig create mode 100644 arch/arm/src/xmc4/Make.defs create mode 100644 arch/arm/src/xmc4/chip.h create mode 100644 arch/arm/src/xmc4/xmc4_allocateheap.c create mode 100644 arch/arm/src/xmc4/xmc4_clockconfig.c create mode 100644 arch/arm/src/xmc4/xmc4_clrpend.c create mode 100644 arch/arm/src/xmc4/xmc4_config.h create mode 100644 arch/arm/src/xmc4/xmc4_dma.c create mode 100644 arch/arm/src/xmc4/xmc4_dma.h create mode 100644 arch/arm/src/xmc4/xmc4_gpio.c create mode 100644 arch/arm/src/xmc4/xmc4_gpio.h create mode 100644 arch/arm/src/xmc4/xmc4_i2c.c create mode 100644 arch/arm/src/xmc4/xmc4_i2c.h create mode 100644 arch/arm/src/xmc4/xmc4_idle.c create mode 100644 arch/arm/src/xmc4/xmc4_irq.c create mode 100644 arch/arm/src/xmc4/xmc4_lowputc.c create mode 100644 arch/arm/src/xmc4/xmc4_mpuinit.c create mode 100644 arch/arm/src/xmc4/xmc4_mpuinit.h create mode 100644 arch/arm/src/xmc4/xmc4_pwm.c create mode 100644 arch/arm/src/xmc4/xmc4_pwm.h create mode 100644 arch/arm/src/xmc4/xmc4_serial.c create mode 100644 arch/arm/src/xmc4/xmc4_spi.h create mode 100644 arch/arm/src/xmc4/xmc4_start.c create mode 100644 arch/arm/src/xmc4/xmc4_timerisr.c create mode 100644 arch/arm/src/xmc4/xmc4_userspace.c create mode 100644 arch/arm/src/xmc4/xmc4_userspace.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index fd44dcff077..21334e71178 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -270,6 +270,19 @@ config ARCH_CHIP_TMS570 ---help--- TI TMS570 family +config ARCH_CHIP_XMC4 + bool "Infineon XMC4xxx" + select ARCH_HAVE_CMNVECTOR + select ARCH_CORTEXM4 + select ARCH_HAVE_MPU + select ARCH_HAVE_RAMFUNCS + select ARCH_HAVE_I2CRESET + select ARM_HAVE_MPU_UNIFIED + select ARMV7M_CMNVECTOR + select ARMV7M_HAVE_STACKCHECK + ---help--- + Infineon XMC4xxx(ARM Cortex-M4) architectures + config ARCH_CHIP_MOXART bool "MoxART" select ARCH_ARM7TDMI @@ -692,6 +705,9 @@ endif if ARCH_CHIP_TMS570 source arch/arm/src/tms570/Kconfig endif +if ARCH_CHIP_XMC4 +source arch/arm/src/xmc4/Kconfig +endif if ARCH_CHIP_MOXART source arch/arm/src/moxart/Kconfig endif diff --git a/arch/arm/src/xmc4/Kconfig b/arch/arm/src/xmc4/Kconfig new file mode 100644 index 00000000000..116d56d14f2 --- /dev/null +++ b/arch/arm/src/xmc4/Kconfig @@ -0,0 +1,328 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +comment "XMC4xxx Configuration Options" + +choice + prompt "XMC4xxx Chip Selection" + default ARCH_CHIP_XMC4500 + depends on ARCH_CHIP_XMC4 + +config ARCH_CHIP_XMC4500 + bool "XMC4500" + +endchoice + +# These "hidden" settings determine is a peripheral option is available for +# the selection MCU + + +# When there are multiple instances of a device, these "hidden" settings +# will automatically be selected and will represent the 'OR' of the +# instances selected. + +config XMC4_USIC + bool + default n + +config XMC4_USCI_UART + bool + default n + select MCU_SERIAL + +config XMC4_USCI_LIN + bool + default n + +config XMC4_USCI_SPI + bool + default n + +config XMC4_USCI_I2C + bool + default n + +config XMC4_USCI_I2S + bool + default n + +# Chip families + +menu "ARCH_CHIP_XMC4 Peripheral Support" + +config XMC4_USIC0 + bool "USIC0" + default n + select XMC4_USIC + ---help--- + Support USIC0 + +config XMC4_USIC1 + bool "USIC1" + default n + ---help--- + Support USIC1 + +config XMC4_USIC2 + bool "USIC3" + default n + select XMC4_USIC + ---help--- + Support USIC2 + +config XMC4_USIC3 + bool "USIC3" + default n + select XMC4_USIC + ---help--- + Support USIC3 + +config XMC4_USIC4 + bool "USIC4" + default n + select XMC4_USIC + ---help--- + Support USIC4 + +config XMC4_USIC5 + bool "USIC5" + default n + select XMC4_USIC + ---help--- + Support USIC5 + +endmenu + +menu "XMC4xxx USIC Configuration" + depends on XMC4_USIC + +choice + prompt "USIC0 Configuration" + default XMC4_USIC0_ISUART + depends on XMC4_USIC0 + +config XMC4_USIC0_ISUART + bool "UART" + select UART0_SERIALDRIVER + select XMC4_USCI_UART + ---help--- + Configure USIC0 as a UART + +config XMC4_USIC0_ISLIN + bool "LIN" + select XMC4_USCI_LIN + ---help--- + Configure USIC0 as a LIN UART + +config XMC4_USIC0_ISSPI + bool "SPI" + select XMC4_USCI_SPI + ---help--- + Configure USIC0 For SPI communications + +config XMC4_USIC0_ISI2C + bool "I2C" + select XMC4_USCI_I2C + ---help--- + Configure USIC0 For I2C communications + +config XMC4_USIC0_ISI2S + bool "I2S" + select XMC4_USCI_I2S + ---help--- + Configure USIC0 For I2S audio + +endchoice # USIC0 Configuration + +choice + prompt "USIC1 Configuration" + default XMC4_USIC1_ISUART + depends on XMC4_USIC1 + +config XMC4_USIC1_ISUART + bool "UART" + select UART1_SERIALDRIVER + select XMC4_USCI_UART + ---help--- + Configure USIC1 as a UART + +config XMC4_USIC1_ISLIN + bool "LIN" + select XMC4_USCI_LIN + ---help--- + Configure USIC1 as a LIN UART + +config XMC4_USIC1_ISSPI + bool "SPI" + select XMC4_USCI_SPI + ---help--- + Configure USIC1 For SPI communications + +config XMC4_USIC1_ISI2C + bool "I2C" + select XMC4_USCI_I2C + ---help--- + Configure USIC1 For I2C communications + +config XMC4_USIC1_ISI2S + bool "I2S" + select XMC4_USCI_I2S + ---help--- + Configure USIC1 For I2S audio + +endchoice # USIC1 Configuration + +choice + prompt "USIC2 Configuration" + default XMC4_USIC2_ISUART + depends on XMC4_USIC2 + +config XMC4_USIC2_ISUART + bool "UART" + select UART2_SERIALDRIVER + select XMC4_USCI_UART + ---help--- + Configure USIC2 as a UART + +config XMC4_USIC2_ISLIN + bool "LIN" + select XMC4_USCI_LIN + ---help--- + Configure USIC2 as a LIN UART + +config XMC4_USIC2_ISSPI + bool "SPI" + select XMC4_USCI_SPI + ---help--- + Configure USIC2 For SPI communications + +config XMC4_USIC2_ISI2C + bool "I2C" + select XMC4_USCI_I2C + ---help--- + Configure USIC2 For I2C communications + +config XMC4_USIC2_ISI2S + bool "I2S" + select XMC4_USCI_I2S + ---help--- + Configure USIC2 For I2S audio + +endchoice # USIC2 Configuration + +choice + prompt "USIC3 Configuration" + default XMC4_USIC3_ISUART + depends on XMC4_USIC3 + +config XMC4_USIC3_ISUART + bool "UART" + select UART3_SERIALDRIVER + select XMC4_USCI_UART + ---help--- + Configure USIC3 as a UART + +config XMC4_USIC3_ISLIN + bool "LIN" + select XMC4_USCI_LIN + ---help--- + Configure USIC3 as a LIN UART + +config XMC4_USIC3_ISSPI + bool "SPI" + select XMC4_USCI_SPI + ---help--- + Configure USIC3 For SPI communications + +config XMC4_USIC3_ISI2C + bool "I2C" + select XMC4_USCI_I2C + ---help--- + Configure USIC3 For I2C communications + +config XMC4_USIC3_ISI2S + bool "I2S" + select XMC4_USCI_I2S + ---help--- + Configure USIC3 For I2S audio + +endchoice # USIC3 Configuration + +choice + prompt "USIC4 Configuration" + default XMC4_USIC4_ISUART + depends on XMC4_USIC4 + +config XMC4_USIC4_ISUART + bool "UART" + select UART4_SERIALDRIVER + select XMC4_USCI_UART + ---help--- + Configure USIC4 as a UART + +config XMC4_USIC4_ISLIN + bool "LIN" + select XMC4_USCI_LIN + ---help--- + Configure USIC4 as a LIN UART + +config XMC4_USIC4_ISSPI + bool "SPI" + select XMC4_USCI_SPI + ---help--- + Configure USIC4 For SPI communications + +config XMC4_USIC4_ISI2C + bool "I2C" + select XMC4_USCI_I2C + ---help--- + Configure USIC4 For I2C communications + +config XMC4_USIC4_ISI2S + bool "I2S" + select XMC4_USCI_I2S + ---help--- + Configure USIC4 For I2S audio + +endchoice # USIC4 Configuration + +choice + prompt "USIC5 Configuration" + default XMC4_USIC5_ISUART + depends on XMC4_USIC5 + +config XMC4_USIC5_ISUART + bool "UART" + select UART0_SERIALDRIVER + select XMC4_USCI_UART + ---help--- + Configure USIC5 as a UART + +config XMC4_USIC5_ISLIN + bool "LIN" + select XMC4_USCI_LIN + ---help--- + Configure USIC5 as a LIN UART + +config XMC4_USIC5_ISSPI + bool "SPI" + select XMC4_USCI_SPI + ---help--- + Configure USIC5 For SPI communications + +config XMC4_USIC5_ISI2C + bool "I2C" + select XMC4_USCI_I2C + ---help--- + Configure USIC5 For I2C communications + +config XMC4_USIC5_ISI2S + bool "I2S" + select XMC4_USCI_I2S + ---help--- + Configure USIC5 For I2S audio + +endchoice # USIC5 Configuration +endmenu # XMC4xxx USIC Configuration diff --git a/arch/arm/src/xmc4/Make.defs b/arch/arm/src/xmc4/Make.defs new file mode 100644 index 00000000000..79497388a49 --- /dev/null +++ b/arch/arm/src/xmc4/Make.defs @@ -0,0 +1,141 @@ +############################################################################ +# arch/arm/src/kinetis/Make.defs +# +# Copyright (C) 2017 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +ifeq ($(CONFIG_ARMV7M_CMNVECTOR),y) +HEAD_ASRC = +else +HEAD_ASRC = xmc4_vectors.S +endif + +CMN_UASRCS = +CMN_UCSRCS = + +CMN_ASRCS = up_saveusercontext.S up_fullcontextrestore.S up_switchcontext.S +CMN_ASRCS += up_testset.S vfork.S + +CMN_CSRCS = up_assert.c up_blocktask.c up_copyfullstate.c up_createstack.c +CMN_CSRCS += up_mdelay.c up_udelay.c up_exit.c up_initialize.c up_memfault.c +CMN_CSRCS += up_initialstate.c up_interruptcontext.c up_modifyreg8.c +CMN_CSRCS += up_modifyreg16.c up_modifyreg32.c up_releasestack.c +CMN_CSRCS += up_reprioritizertr.c up_schedulesigaction.c up_releasepending.c +CMN_CSRCS += up_sigdeliver.c up_stackframe.c up_unblocktask.c up_usestack.c +CMN_CSRCS += up_doirq.c up_hardfault.c up_svcall.c up_vfork.c +CMN_CSRCS += up_systemreset.c + +ifeq ($(CONFIG_ARMV7M_STACKCHECK),y) +CMN_CSRCS += up_stackcheck.c +endif + +ifeq ($(CONFIG_ARMV7M_CMNVECTOR),y) +ifeq ($(CONFIG_ARMV7M_LAZYFPU),y) +CMN_ASRCS += up_lazyexception.S +else +CMN_ASRCS += up_exception.S +endif +CMN_CSRCS += up_vectors.c +endif + +ifeq ($(CONFIG_ARCH_RAMVECTORS),y) +CMN_CSRCS += up_ramvec_initialize.c up_ramvec_attach.c +endif + +ifeq ($(CONFIG_BUILD_PROTECTED),y) +CMN_CSRCS += up_mpu.c up_task_start.c up_pthread_start.c +ifneq ($(CONFIG_DISABLE_SIGNALS),y) +CMN_CSRCS += up_signal_dispatch.c +CMN_UASRCS += up_signal_handler.S +endif +endif + +ifeq ($(CONFIG_STACK_COLORATION),y) +CMN_CSRCS += up_checkstack.c +endif + +# Use of common/up_etherstub.c is deprecated. The preferred mechanism is to +# use CONFIG_NETDEV_LATEINIT=y to suppress the call to up_netinitialize() in +# up_initialize(). Then this stub would not be needed. + +ifeq ($(CONFIG_NET),y) +ifneq ($(CONFIG_XMC4_ENET),y) +CMN_CSRCS += up_etherstub.c +endif +endif + +ifeq ($(CONFIG_ARCH_FPU),y) +CMN_ASRCS += up_fpu.S +ifneq ($(CONFIG_ARMV7M_CMNVECTOR),y) +CMN_CSRCS += up_copyarmstate.c +else ifeq ($(CONFIG_ARMV7M_LAZYFPU),y) +CMN_CSRCS += up_copyarmstate.c +endif +endif + +ifeq ($(CONFIG_ARMV7M_ITMSYSLOG),y) +CMN_CSRCS += up_itm_syslog.c +endif + +# Required XMC4xxx files + +CHIP_ASRCS = + +CHIP_CSRCS = xmc4_allocateheap.c xmc4_clockconfig.c xmc4_clrpend.c +CHIP_CSRCS += xmc4_idle.c xmc4_irq.c xmc4_lowputc.c xmc4_gpio.c +CHIP_CSRCS += xmc4_serialinit.c xmc4_serial.c xmc4_start.c xmc4_uid.c + +# Configuration-dependent Kinetis files + +ifneq ($(CONFIG_SCHED_TICKLESS),y) +CHIP_CSRCS += xmc4_timerisr.c +endif + +ifeq ($(CONFIG_BUILD_PROTECTED),y) +CHIP_CSRCS += xmc4_userspace.c xmc4_mpuinit.c +endif + +ifeq ($(CONFIG_DEBUG_GPIO_INFO),y) +CHIP_CSRCS += xmc4_pindump.c +endif + +ifeq ($(CONFIG_XMC4_DMA),y) +CHIP_CSRCS += xmc4_dma.c +endif + +ifeq ($(CONFIG_PWM),y) +CHIP_CSRCS += xmc4_pwm.c +endif + +ifeq ($(CONFIG_I2C),y) +CHIP_CSRCS += xmc4_i2c.c +endif diff --git a/arch/arm/src/xmc4/chip.h b/arch/arm/src/xmc4/chip.h new file mode 100644 index 00000000000..ef746cfcc93 --- /dev/null +++ b/arch/arm/src/xmc4/chip.h @@ -0,0 +1,77 @@ +/************************************************************************************ + * arch/arm/src/xmc4/chip.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_XMC4_CHIP_H +#define __ARCH_ARM_SRC_XMC4_CHIP_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/* Include the memory map and the chip definitions file. Other chip hardware files + * should then include this file for the proper setup. + */ + +#include +#include +#include "chip/xmc4_memorymap.h" + +/* If the common ARMv7-M vector handling logic is used, then it expects the + * following definition in this file that provides the number of supported external + * interrupts which, for this architecture, is provided in the arch/xmc4/chip.h + * header file. + */ + +#define ARMV7M_PERIPHERAL_INTERRUPTS NR_INTERRUPTS + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_XMC4_CHIP_H */ diff --git a/arch/arm/src/xmc4/xmc4_allocateheap.c b/arch/arm/src/xmc4/xmc4_allocateheap.c new file mode 100644 index 00000000000..cdbc8ef2d18 --- /dev/null +++ b/arch/arm/src/xmc4/xmc4_allocateheap.c @@ -0,0 +1,193 @@ +/**************************************************************************** + * arch/arm/src/xmc4/xmc4_allocateheap.c + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include +#include + +#include + +#include "mpu.h" +#include "up_arch.h" +#include "up_internal.h" +#include "xmc4_mpuinit.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_allocate_heap + * + * Description: + * This function will be called to dynamically set aside the heap region. + * + * For the kernel build (CONFIG_BUILD_PROTECTED=y) with both kernel- and + * user-space heaps (CONFIG_MM_KERNEL_HEAP=y), this function provides the + * size of the unprotected, user-space heap. + * + * If a protected kernel-space heap is provided, the kernel heap must be + * allocated (and protected) by an analogous up_allocate_kheap(). + * + * The following memory map is assumed for the flat build: + * + * .data region. Size determined at link time. + * .bss region Size determined at link time. + * IDLE thread stack. Size determined by CONFIG_IDLETHREAD_STACKSIZE. + * Heap. Extends to the end of SRAM. + * + * The following memory map is assumed for the kernel build: + * + * Kernel .data region. Size determined at link time. + * Kernel .bss region Size determined at link time. + * Kernel IDLE thread stack. Size determined by CONFIG_IDLETHREAD_STACKSIZE. + * Padding for alignment + * User .data region. Size determined at link time. + * User .bss region Size determined at link time. + * Kernel heap. Size determined by CONFIG_MM_KERNEL_HEAPSIZE. + * User heap. Extends to the end of SRAM. + * + ****************************************************************************/ + +void up_allocate_heap(FAR void **heap_start, size_t *heap_size) +{ +#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP) + /* Get the unaligned size and position of the user-space heap. + * This heap begins after the user-space .bss section at an offset + * of CONFIG_MM_KERNEL_HEAPSIZE (subject to alignment). + */ + + uintptr_t ubase = (uintptr_t)USERSPACE->us_bssend + CONFIG_MM_KERNEL_HEAPSIZE; + size_t usize = CONFIG_RAM_END - ubase; + int log2; + + DEBUGASSERT(ubase < (uintptr_t)CONFIG_RAM_END); + + /* Adjust that size to account for MPU alignment requirements. + * NOTE that there is an implicit assumption that the CONFIG_RAM_END + * is aligned to the MPU requirement. + */ + + log2 = (int)mpu_log2regionfloor(usize); + DEBUGASSERT((CONFIG_RAM_END & ((1 << log2) - 1)) == 0); + + usize = (1 << log2); + ubase = CONFIG_RAM_END - usize; + + /* Return the user-space heap settings */ + + board_autoled_on(LED_HEAPALLOCATE); + *heap_start = (FAR void *)ubase; + *heap_size = usize; + + /* Allow user-mode access to the user heap memory */ + + xmc4_mpu_uheap((uintptr_t)ubase, usize); +#else + + /* Return the heap settings */ + + board_autoled_on(LED_HEAPALLOCATE); + *heap_start = (FAR void *)g_idle_topstack; + *heap_size = CONFIG_RAM_END - g_idle_topstack; +#endif +} + +/**************************************************************************** + * Name: up_allocate_kheap + * + * Description: + * For the kernel build (CONFIG_BUILD_PROTECTED=y) with both kernel- and + * user-space heaps (CONFIG_MM_KERNEL_HEAP=y), this function allocates + * (and protects) the kernel-space heap. + * + ****************************************************************************/ + +#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP) +void up_allocate_kheap(FAR void **heap_start, size_t *heap_size) +{ + /* Get the unaligned size and position of the user-space heap. + * This heap begins after the user-space .bss section at an offset + * of CONFIG_MM_KERNEL_HEAPSIZE (subject to alignment). + */ + + uintptr_t ubase = (uintptr_t)USERSPACE->us_bssend + CONFIG_MM_KERNEL_HEAPSIZE; + size_t usize = CONFIG_RAM_END - ubase; + int log2; + + DEBUGASSERT(ubase < (uintptr_t)CONFIG_RAM_END); + + /* Adjust that size to account for MPU alignment requirements. + * NOTE that there is an implicit assumption that the CONFIG_RAM_END + * is aligned to the MPU requirement. + */ + + log2 = (int)mpu_log2regionfloor(usize); + DEBUGASSERT((CONFIG_RAM_END & ((1 << log2) - 1)) == 0); + + usize = (1 << log2); + ubase = CONFIG_RAM_END - usize; + + /* Return the kernel heap settings (i.e., the part of the heap region + * that was not dedicated to the user heap). + */ + + *heap_start = (FAR void *)USERSPACE->us_bssend; + *heap_size = ubase - (uintptr_t)USERSPACE->us_bssend; +} +#endif diff --git a/arch/arm/src/xmc4/xmc4_clockconfig.c b/arch/arm/src/xmc4/xmc4_clockconfig.c new file mode 100644 index 00000000000..67efe53651d --- /dev/null +++ b/arch/arm/src/xmc4/xmc4_clockconfig.c @@ -0,0 +1,74 @@ +/**************************************************************************** + * arch/arm/src/xmc4/xmc4_clock_config.c + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "up_arch.h" + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: xmc4_clock_config + * + * Description: + * Called to initialize the XMC4xxx chip. This does whatever setup is + * needed to put the MCU in a usable state. This includes the + * initialization of clocking using the settings in board.h. + * + ****************************************************************************/ + +void xmc4_clock_config(void) +{ +} diff --git a/arch/arm/src/xmc4/xmc4_clrpend.c b/arch/arm/src/xmc4/xmc4_clrpend.c new file mode 100644 index 00000000000..2eab7d6ffa2 --- /dev/null +++ b/arch/arm/src/xmc4/xmc4_clrpend.c @@ -0,0 +1,102 @@ +/**************************************************************************** + * arch/arm/src/xmc4/xmc4_clrpend.c + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include "nvic.h" +#include "up_arch.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: xmc4_clrpend + * + * Description: + * Clear a pending interrupt at the NVIC. This does not seem to be required + * for most interrupts. Don't know why... + * + * I keep it in a separate file so that it will not increase the footprint + * on Kinetis platforms that do not need this function. + * + ****************************************************************************/ + +void xmc4_clrpend(int irq) +{ + /* Check for external interrupt */ + + if (irq >= XMC4_IRQ_FIRST) + { + if (irq < (XMC4_IRQ_FIRST+32)) + { + putreg32(1 << (irq - XMC4_IRQ_FIRST), NVIC_IRQ0_31_CLRPEND); + } + else if (irq < (XMC4_IRQ_FIRST+64)) + { + putreg32(1 << (irq - XMC4_IRQ_FIRST - 32), NVIC_IRQ32_63_CLRPEND); + } + else if (irq < (XMC4_IRQ_FIRST+96)) + { + putreg32(1 << (irq - XMC4_IRQ_FIRST - 64), NVIC_IRQ64_95_CLRPEND); + } + else if (irq < NR_IRQS) + { + putreg32(1 << (irq - XMC4_IRQ_FIRST - 96), NVIC_IRQ96_127_CLRPEND); + } + } +} diff --git a/arch/arm/src/xmc4/xmc4_config.h b/arch/arm/src/xmc4/xmc4_config.h new file mode 100644 index 00000000000..e81932569ec --- /dev/null +++ b/arch/arm/src/xmc4/xmc4_config.h @@ -0,0 +1,198 @@ +/************************************************************************************ + * arch/arm/src/xmc4/xmc4_config.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_XMC4_XMC4_CONFIG_H +#define __ARCH_ARM_SRC_XMC4_XMC4_CONFIG_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include +#include + +#include "chip.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Configuration *********************************************************************/ +/* Make sure that no unsupported UARTs are enabled */ + +#ifndef CONFIG_XMC4_USIC0 +# undef CONFIG_XMC4_USIC0_ISUART +#endif +#ifndef CONFIG_XMC4_USIC1 +# undef CONFIG_XMC4_USIC1_ISUART +#endif +#ifndef CONFIG_XMC4_USIC2 +# undef CONFIG_XMC4_USIC2_ISUART +#endif +#ifndef CONFIG_XMC4_USIC3 +# undef CONFIG_XMC4_USIC3_ISUART +#endif +#ifndef CONFIG_XMC4_USIC4 +# undef CONFIG_XMC4_USIC4_ISUART +#endif +#ifndef CONFIG_XMC4_USIC5 +# undef CONFIG_XMC4_USIC5_ISUART +#endif + +/* Are any UARTs enabled? */ + +#undef HAVE_UART_DEVICE +#if defined(CONFIG_XMC4_USIC0_ISUART) || defined(CONFIG_XMC4_USIC1_ISUART) || \ + defined(CONFIG_XMC4_USIC2_ISUART) || defined(CONFIG_XMC4_USIC3_ISUART) || \ + defined(CONFIG_XMC4_USIC3_ISUART) || defined(CONFIG_XMC4_USIC4_ISUART) +# define HAVE_UART_DEVICE 1 +#endif + +/* Is there a serial console? There should be at most one defined. It could be on + * any UARTn, n=0,1,2,3,4,5 + */ + +#undef HAVE_UART_CONSOLE + +#if defined(CONFIG_CONSOLE_SYSLOG) +# undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART1_SERIAL_CONSOLE +# undef CONFIG_UART2_SERIAL_CONSOLE +# undef CONFIG_UART3_SERIAL_CONSOLE +# undef CONFIG_UART4_SERIAL_CONSOLE +# undef CONFIG_UART5_SERIAL_CONSOLE +#else +# if defined(CONFIG_UART0_SERIAL_CONSOLE) && defined(CONFIG_XMC4_USIC0_ISUART) +# undef CONFIG_UART1_SERIAL_CONSOLE +# undef CONFIG_UART2_SERIAL_CONSOLE +# undef CONFIG_UART3_SERIAL_CONSOLE +# undef CONFIG_UART4_SERIAL_CONSOLE +# undef CONFIG_UART5_SERIAL_CONSOLE +# define HAVE_UART_CONSOLE 1 +# elif defined(CONFIG_UART1_SERIAL_CONSOLE) && defined(CONFIG_XMC4_USIC1_ISUART) +# undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART2_SERIAL_CONSOLE +# undef CONFIG_UART3_SERIAL_CONSOLE +# undef CONFIG_UART4_SERIAL_CONSOLE +# undef CONFIG_UART5_SERIAL_CONSOLE +# define HAVE_UART_CONSOLE 1 +# elif defined(CONFIG_UART2_SERIAL_CONSOLE) && defined(CONFIG_XMC4_USIC2_ISUART) +# undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART1_SERIAL_CONSOLE +# undef CONFIG_UART3_SERIAL_CONSOLE +# undef CONFIG_UART4_SERIAL_CONSOLE +# undef CONFIG_UART5_SERIAL_CONSOLE +# define HAVE_UART_CONSOLE 1 +# elif defined(CONFIG_UART3_SERIAL_CONSOLE) && defined(CONFIG_XMC4_USIC3_ISUART) +# undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART1_SERIAL_CONSOLE +# undef CONFIG_UART2_SERIAL_CONSOLE +# undef CONFIG_UART4_SERIAL_CONSOLE +# undef CONFIG_UART5_SERIAL_CONSOLE +# define HAVE_UART_CONSOLE 1 +# elif defined(CONFIG_UART4_SERIAL_CONSOLE) && defined(CONFIG_XMC4_USIC4_ISUART) +# undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART1_SERIAL_CONSOLE +# undef CONFIG_UART2_SERIAL_CONSOLE +# undef CONFIG_UART3_SERIAL_CONSOLE +# undef CONFIG_UART5_SERIAL_CONSOLE +# define HAVE_UART_CONSOLE 1 +# elif defined(CONFIG_UART5_SERIAL_CONSOLE) && defined(CONFIG_XMC4_USIC5_ISUART) +# undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART1_SERIAL_CONSOLE +# undef CONFIG_UART2_SERIAL_CONSOLE +# undef CONFIG_UART3_SERIAL_CONSOLE +# undef CONFIG_UART4_SERIAL_CONSOLE +# define HAVE_UART_CONSOLE 1 +# else +# ifdef CONFIG_DEV_CONSOLE +# warning "No valid CONFIG_[LP]UART[n]_SERIAL_CONSOLE Setting" +# endif +# undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART1_SERIAL_CONSOLE +# undef CONFIG_UART2_SERIAL_CONSOLE +# undef CONFIG_UART3_SERIAL_CONSOLE +# undef CONFIG_UART4_SERIAL_CONSOLE +# undef CONFIG_UART5_SERIAL_CONSOLE +# endif +#endif + +/* Check UART flow control (Not yet supported) */ + +# undef CONFIG_UART0_FLOWCONTROL +# undef CONFIG_UART1_FLOWCONTROL +# undef CONFIG_UART2_FLOWCONTROL +# undef CONFIG_UART3_FLOWCONTROL +# undef CONFIG_UART4_FLOWCONTROL +# undef CONFIG_UART5_FLOWCONTROL + +/* UART Default Interrupt Priorities */ + +#ifndef CONFIG_XMC4_UART0PRIO +# define CONFIG_XMC4_UART0PRIO NVIC_SYSH_PRIORITY_DEFAULT +#endif +#ifndef CONFIG_XMC4_UART1PRIO +# define CONFIG_XMC4_UART1PRIO NVIC_SYSH_PRIORITY_DEFAULT +#endif +#ifndef CONFIG_XMC4_UART2PRIO +# define CONFIG_XMC4_UART2PRIO NVIC_SYSH_PRIORITY_DEFAULT +#endif +#ifndef CONFIG_XMC4_UART3PRIO +# define CONFIG_XMC4_UART3PRIO NVIC_SYSH_PRIORITY_DEFAULT +#endif +#ifndef CONFIG_XMC4_UART4PRIO +# define CONFIG_XMC4_UART4PRIO NVIC_SYSH_PRIORITY_DEFAULT +#endif +#ifndef CONFIG_XMC4_UART5PRIO +# define CONFIG_XMC4_UART5PRIO NVIC_SYSH_PRIORITY_DEFAULT +#endif + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Inline Functions + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_XMC4_XMC4_CONFIG_H */ diff --git a/arch/arm/src/xmc4/xmc4_dma.c b/arch/arm/src/xmc4/xmc4_dma.c new file mode 100644 index 00000000000..e69de29bb2d diff --git a/arch/arm/src/xmc4/xmc4_dma.h b/arch/arm/src/xmc4/xmc4_dma.h new file mode 100644 index 00000000000..8f2edba4326 --- /dev/null +++ b/arch/arm/src/xmc4/xmc4_dma.h @@ -0,0 +1,218 @@ +/**************************************************************************** + * arch/arm/src/xmc4/xmc4_dma.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_XMC4_XMC4_DMA_H +#define __ARCH_ARM_SRC_XMC4_XMC4_DMA_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include "chip/xmc4_dma.h" + +/**************************************************************************** + * Pre-processor Declarations + ****************************************************************************/ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +typedef FAR void *DMA_HANDLE; +typedef void (*dma_callback_t)(DMA_HANDLE handle, void *arg, int result); + +/* The following is used for sampling DMA registers when CONFIG DEBUG_DMA is selected */ + +#ifdef CONFIG_DEBUG_DMA +struct xmc4_dmaglobalregs_s +{ +#warning "Missing logic" + /* Global Registers */ +}; + +struct xmc4_dmachanregs_s +{ +#warning "Missing logic" + /* Channel Registers */ +}; + +struct xmc4_dmaregs_s +{ + /* Global Registers */ + + struct xmc4_dmaglobalregs_s gbl; + + /* Channel Registers */ + + struct xmc4_dmachanregs_s ch; +}; +#endif + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/**************************************************************************** + * Name: xmc4_dmainitialize + * + * Description: + * Initialize the GPDMA subsystem. + * + * Returned Value: + * None + * + ****************************************************************************/ + +void xmc4_dmainitilaize(void); + +/**************************************************************************** + * Name: xmc4_dmachannel + * + * Description: + * Allocate a DMA channel. This function sets aside a DMA channel and + * gives the caller exclusive access to the DMA channel. + * + * Returned Value: + * One success, this function returns a non-NULL, void* DMA channel + * handle. NULL is returned on any failure. This function can fail only + * if no DMA channel is available. + * + ****************************************************************************/ + +DMA_HANDLE xmc4_dmachannel(void); + +/**************************************************************************** + * Name: xmc4_dmafree + * + * Description: + * Release a DMA channel. NOTE: The 'handle' used in this argument must + * NEVER be used again until xmc4_dmachannel() is called again to re-gain + * a valid handle. + * + * Returned Value: + * None + * + ****************************************************************************/ + +void xmc4_dmafree(DMA_HANDLE handle); + +/**************************************************************************** + * Name: xmc4_dmasetup + * + * Description: + * Configure DMA for one transfer. + * + ****************************************************************************/ + +int xmc4_dmarxsetup(DMA_HANDLE handle, uint32_t control, uint32_t config, + uint32_t srcaddr, uint32_t destaddr, size_t nbytes); + +/**************************************************************************** + * Name: xmc4_dmastart + * + * Description: + * Start the DMA transfer + * + ****************************************************************************/ + +int xmc4_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg); + +/**************************************************************************** + * Name: xmc4_dmastop + * + * Description: + * Cancel the DMA. After xmc4_dmastop() is called, the DMA channel is + * reset and xmc4_dmasetup() must be called before xmc4_dmastart() can be + * called again + * + ****************************************************************************/ + +void xmc4_dmastop(DMA_HANDLE handle); + +/**************************************************************************** + * Name: xmc4_dmasample + * + * Description: + * Sample DMA register contents + * + ****************************************************************************/ + +#ifdef CONFIG_DEBUG_DMA +void xmc4_dmasample(DMA_HANDLE handle, struct xmc4_dmaregs_s *regs); +#else +# define xmc4_dmasample(handle,regs) +#endif + +/**************************************************************************** + * Name: xmc4_dmadump + * + * Description: + * Dump previously sampled DMA register contents + * + ****************************************************************************/ + +#ifdef CONFIG_DEBUG_DMA +void xmc4_dmadump(DMA_HANDLE handle, const struct xmc4_dmaregs_s *regs, + const char *msg); +#else +# define xmc4_dmadump(handle,regs,msg) +#endif + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_ARM_SRC_XMC4_XMC4_DMA_H */ diff --git a/arch/arm/src/xmc4/xmc4_gpio.c b/arch/arm/src/xmc4/xmc4_gpio.c new file mode 100644 index 00000000000..e69de29bb2d diff --git a/arch/arm/src/xmc4/xmc4_gpio.h b/arch/arm/src/xmc4/xmc4_gpio.h new file mode 100644 index 00000000000..e69de29bb2d diff --git a/arch/arm/src/xmc4/xmc4_i2c.c b/arch/arm/src/xmc4/xmc4_i2c.c new file mode 100644 index 00000000000..e69de29bb2d diff --git a/arch/arm/src/xmc4/xmc4_i2c.h b/arch/arm/src/xmc4/xmc4_i2c.h new file mode 100644 index 00000000000..f4a167b713d --- /dev/null +++ b/arch/arm/src/xmc4/xmc4_i2c.h @@ -0,0 +1,87 @@ +/**************************************************************************** + * arch/arm/src/xmc4/xmc4_i2c.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_XMC4_XMC4_I2C_H +#define __ARCH_ARM_SRC_XMC4_XMC4_I2C_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include "chip/xmc4_i2c.h" + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: xmc4_i2cbus_initialize + * + * Description: + * Initialize the selected I2C port. And return a unique instance of struct + * struct i2c_master_s. This function may be called to obtain multiple + * instances of the interface, each of which may be set up with a + * different frequency and slave address. + * + * Input Parameter: + * Port number (for hardware that has multiple I2C interfaces) + * + * Returned Value: + * Valid I2C device structure reference on succcess; a NULL on failure + * + ****************************************************************************/ + +FAR struct i2c_master_s *xmc4_i2cbus_initialize(int port); + +/**************************************************************************** + * Name: xmc4_i2cbus_uninitialize + * + * Description: + * De-initialize the selected I2C port, and power down the device. + * + * Input Parameter: + * Device structure as returned by the lpc43_i2cbus_initialize() + * + * Returned Value: + * OK on success, ERROR when internal reference count mismatch or dev + * points to invalid hardware device. + * + ****************************************************************************/ + +int xmc4_i2cbus_uninitialize(FAR struct i2c_master_s *dev); + +#endif /* __ARCH_ARM_SRC_XMC4_XMC4_I2C_H */ diff --git a/arch/arm/src/xmc4/xmc4_idle.c b/arch/arm/src/xmc4/xmc4_idle.c new file mode 100644 index 00000000000..411324311f5 --- /dev/null +++ b/arch/arm/src/xmc4/xmc4_idle.c @@ -0,0 +1,105 @@ +/**************************************************************************** + * arch/arm/src/xmc4/xmc4_idle.c + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include +#include + +#include "up_internal.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Does the board support an IDLE LED to indicate that the board is in the + * IDLE state? + */ + +#if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE) +# define BEGIN_IDLE() board_autoled_on(LED_IDLE) +# define END_IDLE() board_autoled_off(LED_IDLE) +#else +# define BEGIN_IDLE() +# define END_IDLE() +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_idle + * + * Description: + * up_idle() is the logic that will be executed when their is no other + * ready-to-run task. This is processor idle time and will continue until + * some interrupt occurs to cause a context switch from the idle task. + * + * Processing in this state may be processor-specific. e.g., this is where + * power management operations might be performed. + * + ****************************************************************************/ + +void up_idle(void) +{ +#if defined(CONFIG_SUPPRESS_INTERRUPTS) || defined(CONFIG_SUPPRESS_TIMER_INTS) + /* If the system is idle and there are no timer interrupts, then process + * "fake" timer interrupts. Hopefully, something will wake up. + */ + + sched_process_timer(); +#else + + /* Sleep until an interrupt occurs to save power */ + + BEGIN_IDLE(); + asm("WFI"); + END_IDLE(); +#endif +} diff --git a/arch/arm/src/xmc4/xmc4_irq.c b/arch/arm/src/xmc4/xmc4_irq.c new file mode 100644 index 00000000000..17725b8c608 --- /dev/null +++ b/arch/arm/src/xmc4/xmc4_irq.c @@ -0,0 +1,588 @@ +/**************************************************************************** + * arch/arm/src/xmc4/xmc4_irq.c + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "nvic.h" +#include "ram_vectors.h" +#include "up_arch.h" +#include "up_internal.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Get a 32-bit version of the default priority */ + +#define DEFPRIORITY32 \ + (NVIC_SYSH_PRIORITY_DEFAULT << 24 | \ + NVIC_SYSH_PRIORITY_DEFAULT << 16 | \ + NVIC_SYSH_PRIORITY_DEFAULT << 8 | \ + NVIC_SYSH_PRIORITY_DEFAULT) + +/* Given the address of a NVIC ENABLE register, this is the offset to + * the corresponding CLEAR ENABLE register. + */ + +#define NVIC_ENA_OFFSET (0) +#define NVIC_CLRENA_OFFSET (NVIC_IRQ0_31_CLEAR - NVIC_IRQ0_31_ENABLE) + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* g_current_regs[] holds a references to the current interrupt level + * register storage structure. If is non-NULL only during interrupt + * processing. Access to g_current_regs[] must be through the macro + * CURRENT_REGS for portability. + */ + +volatile uint32_t *g_current_regs[1]; + +/* This is the address of the exception vector table (determined by the + * linker script). + */ + +extern uint32_t _vectors[]; + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: xmc4_dump_nvic + * + * Description: + * Dump some interesting NVIC registers + * + ****************************************************************************/ + +#if defined(CONFIG_DEBUG_IRQ_INFO) +static void xmc4_dump_nvic(const char *msg, int irq) +{ + irqstate_t flags; + + flags = enter_critical_section(); + + irqinfo("NVIC (%s, irq=%d):\n", msg, irq); + irqinfo(" INTCTRL: %08x VECTAB: %08x\n", + getreg32(NVIC_INTCTRL), getreg32(NVIC_VECTAB)); +#if 0 + irqinfo(" SYSH ENABLE MEMFAULT: %08x BUSFAULT: %08x USGFAULT: %08x SYSTICK: %08x\n", + getreg32(NVIC_SYSHCON_MEMFAULTENA), getreg32(NVIC_SYSHCON_BUSFAULTENA), + getreg32(NVIC_SYSHCON_USGFAULTENA), getreg32(NVIC_SYSTICK_CTRL_ENABLE)); +#endif + irqinfo(" IRQ ENABLE: %08x %08x %08x %08x\n", + getreg32(NVIC_IRQ0_31_ENABLE), getreg32(NVIC_IRQ32_63_ENABLE), + getreg32(NVIC_IRQ64_95_ENABLE), getreg32(NVIC_IRQ96_127_ENABLE)); + irqinfo(" SYSH_PRIO: %08x %08x %08x\n", + getreg32(NVIC_SYSH4_7_PRIORITY), getreg32(NVIC_SYSH8_11_PRIORITY), + getreg32(NVIC_SYSH12_15_PRIORITY)); + irqinfo(" IRQ PRIO: %08x %08x %08x %08x\n", + getreg32(NVIC_IRQ0_3_PRIORITY), getreg32(NVIC_IRQ4_7_PRIORITY), + getreg32(NVIC_IRQ8_11_PRIORITY), getreg32(NVIC_IRQ12_15_PRIORITY)); + irqinfo(" %08x %08x %08x %08x\n", + getreg32(NVIC_IRQ16_19_PRIORITY), getreg32(NVIC_IRQ20_23_PRIORITY), + getreg32(NVIC_IRQ24_27_PRIORITY), getreg32(NVIC_IRQ28_31_PRIORITY)); + irqinfo(" %08x %08x %08x %08x\n", + getreg32(NVIC_IRQ32_35_PRIORITY), getreg32(NVIC_IRQ36_39_PRIORITY), + getreg32(NVIC_IRQ40_43_PRIORITY), getreg32(NVIC_IRQ44_47_PRIORITY)); + irqinfo(" %08x %08x %08x %08x\n", + getreg32(NVIC_IRQ48_51_PRIORITY), getreg32(NVIC_IRQ52_55_PRIORITY), + getreg32(NVIC_IRQ56_59_PRIORITY), getreg32(NVIC_IRQ60_63_PRIORITY)); + irqinfo(" %08x %08x %08x %08x\n", + getreg32(NVIC_IRQ64_67_PRIORITY), getreg32(NVIC_IRQ68_71_PRIORITY), + getreg32(NVIC_IRQ72_75_PRIORITY), getreg32(NVIC_IRQ76_79_PRIORITY)); + irqinfo(" %08x %08x %08x %08x\n", + getreg32(NVIC_IRQ80_83_PRIORITY), getreg32(NVIC_IRQ84_87_PRIORITY), + getreg32(NVIC_IRQ88_91_PRIORITY), getreg32(NVIC_IRQ92_95_PRIORITY)); + irqinfo(" %08x %08x %08x %08x\n", + getreg32(NVIC_IRQ96_99_PRIORITY), getreg32(NVIC_IRQ100_103_PRIORITY), + getreg32(NVIC_IRQ104_107_PRIORITY), getreg32(NVIC_IRQ108_111_PRIORITY)); +#if NR_VECTORS > 111 + irqinfo(" %08x %08x\n", + getreg32(NVIC_IRQ112_115_PRIORITY), getreg32(NVIC_IRQ116_119_PRIORITY)); +#endif + + leave_critical_section(flags); +} +#else +# define xmc4_dump_nvic(msg, irq) +#endif + +/**************************************************************************** + * Name: xmc4_nmi, xmc4_busfault, xmc4_usagefault, xmc4_pendsv, + * xmc4_dbgmonitor, xmc4_pendsv, xmc4_reserved + * + * Description: + * Handlers for various execptions. None are handled and all are fatal + * error conditions. The only advantage these provided over the default + * unexpected interrupt handler is that they provide a diagnostic output. + * + ****************************************************************************/ + +#ifdef CONFIG_DEBUG_FEATURES +static int xmc4_nmi(int irq, FAR void *context, FAR void *arg) +{ + (void)up_irq_save(); + _err("PANIC!!! NMI received\n"); + PANIC(); + return 0; +} + +static int xmc4_busfault(int irq, FAR void *context, FAR void *arg) +{ + (void)up_irq_save(); + _err("PANIC!!! Bus fault recived\n"); + PANIC(); + return 0; +} + +static int xmc4_usagefault(int irq, FAR void *context, FAR void *arg) +{ + (void)up_irq_save(); + _err("PANIC!!! Usage fault received\n"); + PANIC(); + return 0; +} + +static int xmc4_pendsv(int irq, FAR void *context, FAR void *arg) +{ + (void)up_irq_save(); + _err("PANIC!!! PendSV received\n"); + PANIC(); + return 0; +} + +static int xmc4_dbgmonitor(int irq, FAR void *context, FAR void *arg) +{ + (void)up_irq_save(); + _err("PANIC!!! Debug Monitor received\n"); + PANIC(); + return 0; +} + +static int xmc4_reserved(int irq, FAR void *context, FAR void *arg) +{ + (void)up_irq_save(); + _err("PANIC!!! Reserved interrupt\n"); + PANIC(); + return 0; +} +#endif + +/**************************************************************************** + * Name: xmc4_prioritize_syscall + * + * Description: + * Set the priority of an exception. This function may be needed + * internally even if support for prioritized interrupts is not enabled. + * + ****************************************************************************/ + +#ifdef CONFIG_ARMV7M_USEBASEPRI +static inline void xmc4_prioritize_syscall(int priority) +{ + uint32_t regval; + + /* SVCALL is system handler 11 */ + + regval = getreg32(NVIC_SYSH8_11_PRIORITY); + regval &= ~NVIC_SYSH_PRIORITY_PR11_MASK; + regval |= (priority << NVIC_SYSH_PRIORITY_PR11_SHIFT); + putreg32(regval, NVIC_SYSH8_11_PRIORITY); +} +#endif + +/**************************************************************************** + * Name: xmc4_irqinfo + * + * Description: + * Given an IRQ number, provide the register and bit setting to enable or + * disable the irq. + * + ****************************************************************************/ + +static int xmc4_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit, + uintptr_t offset) +{ + DEBUGASSERT(irq >= XMC4_IRQ_NMI && irq < NR_IRQS); + + /* Check for external interrupt */ + + if (irq >= XMC4_IRQ_FIRST) + { + if (irq < (XMC4_IRQ_FIRST+32)) + { + *regaddr = (NVIC_IRQ0_31_ENABLE + offset); + *bit = 1 << (irq - XMC4_IRQ_FIRST); + } + else if (irq < (XMC4_IRQ_FIRST+64)) + { + *regaddr = (NVIC_IRQ32_63_ENABLE + offset); + *bit = 1 << (irq - XMC4_IRQ_FIRST - 32); + } + else if (irq < (XMC4_IRQ_FIRST+96)) + { + *regaddr = (NVIC_IRQ64_95_ENABLE + offset); + *bit = 1 << (irq - XMC4_IRQ_FIRST - 64); + } + else if (irq < NR_IRQS) + { + *regaddr = (NVIC_IRQ96_127_ENABLE + offset); + *bit = 1 << (irq - XMC4_IRQ_FIRST - 96); + } + else + { + return ERROR; /* Invalid irq */ + } + } + + /* Handle processor exceptions. Only a few can be disabled */ + + else + { + *regaddr = NVIC_SYSHCON; + if (irq == XMC4_IRQ_MEMFAULT) + { + *bit = NVIC_SYSHCON_MEMFAULTENA; + } + else if (irq == XMC4_IRQ_BUSFAULT) + { + *bit = NVIC_SYSHCON_BUSFAULTENA; + } + else if (irq == XMC4_IRQ_USAGEFAULT) + { + *bit = NVIC_SYSHCON_USGFAULTENA; + } + else if (irq == XMC4_IRQ_SYSTICK) + { + *regaddr = NVIC_SYSTICK_CTRL; + *bit = NVIC_SYSTICK_CTRL_ENABLE; + } + else + { + return ERROR; /* Invalid or unsupported exception */ + } + } + + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_irqinitialize + ****************************************************************************/ + +void up_irqinitialize(void) +{ + uintptr_t regaddr; + int nintlines; + int i; + + /* The NVIC ICTR register (bits 0-4) holds the number of of interrupt + * lines that the NVIC supports, defined in groups of 32. That is, + * the total number of interrupt lines is up to (32*(INTLINESNUM+1)). + * + * 0 -> 32 interrupt lines, 1 enable register, 8 priority registers + * 1 -> 64 " " " ", 2 enable registers, 16 priority registers + * 2 -> 96 " " " ", 3 enable regsiters, 24 priority registers + * ... + */ + + nintlines = (getreg32(NVIC_ICTR) & NVIC_ICTR_INTLINESNUM_MASK) + 1; + + /* Disable all interrupts. There are nintlines interrupt enable + * registers. + */ + + for (i = nintlines, regaddr = NVIC_IRQ0_31_ENABLE; + i > 0; + i--, regaddr += 4) + { + putreg32(0, regaddr); + } + + /* Make sure that we are using the correct vector table. The default + * vector address is 0x0000:0000 but if we are executing code that is + * positioned in SRAM or in external FLASH, then we may need to reset + * the interrupt vector so that it refers to the table in SRAM or in + * external FLASH. + */ + + putreg32((uint32_t)_vectors, NVIC_VECTAB); + +#ifdef CONFIG_ARCH_RAMVECTORS + /* If CONFIG_ARCH_RAMVECTORS is defined, then we are using a RAM-based + * vector table that requires special initialization. + */ + + up_ramvec_initialize(); +#endif + + /* Set all interrupts (and exceptions) to the default priority */ + + putreg32(DEFPRIORITY32, NVIC_SYSH4_7_PRIORITY); + putreg32(DEFPRIORITY32, NVIC_SYSH8_11_PRIORITY); + putreg32(DEFPRIORITY32, NVIC_SYSH12_15_PRIORITY); + + /* Now set all of the interrupt lines to the default priority. There are + * nintlines * 8 priority registers. + */ + + for (i = (nintlines << 3), regaddr = NVIC_IRQ0_3_PRIORITY; + i > 0; + i--, regaddr += 4) + { + putreg32(DEFPRIORITY32, regaddr); + } + + /* currents_regs is non-NULL only while processing an interrupt */ + + CURRENT_REGS = NULL; + + /* Attach the SVCall and Hard Fault exception handlers. The SVCall + * exception is used for performing context switches; The Hard Fault + * must also be caught because a SVCall may show up as a Hard Fault + * under certain conditions. + */ + + irq_attach(XMC4_IRQ_SVCALL, up_svcall, NULL); + irq_attach(XMC4_IRQ_HARDFAULT, up_hardfault, NULL); + + /* Set the priority of the SVCall interrupt */ + +#ifdef CONFIG_ARCH_IRQPRIO + /* up_prioritize_irq(XMC4_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */ +#endif +#ifdef CONFIG_ARMV7M_USEBASEPRI + xmc4_prioritize_syscall(NVIC_SYSH_SVCALL_PRIORITY); +#endif + + /* If the MPU is enabled, then attach and enable the Memory Management + * Fault handler. + */ + +#ifdef CONFIG_ARM_MPU + irq_attach(XMC4_IRQ_MEMFAULT, up_memfault, NULL); + up_enable_irq(XMC4_IRQ_MEMFAULT); +#endif + + /* Attach all other processor exceptions (except reset and sys tick) */ + +#ifdef CONFIG_DEBUG_FEATURES + irq_attach(XMC4_IRQ_NMI, xmc4_nmi, NULL); +#ifndef CONFIG_ARM_MPU + irq_attach(XMC4_IRQ_MEMFAULT, up_memfault, NULL); +#endif + irq_attach(XMC4_IRQ_BUSFAULT, xmc4_busfault, NULL); + irq_attach(XMC4_IRQ_USAGEFAULT, xmc4_usagefault, NULL); + irq_attach(XMC4_IRQ_PENDSV, xmc4_pendsv, NULL); + irq_attach(XMC4_IRQ_DBGMONITOR, xmc4_dbgmonitor, NULL); + irq_attach(XMC4_IRQ_RESERVED, xmc4_reserved, NULL); +#endif + + xmc4_dump_nvic("initial", NR_IRQS); + + /* Initialize logic to support a second level of interrupt decoding for + * configured pin interrupts. + */ + +#ifdef CONFIG_XMC4_GPIOIRQ + xmc4_gpioirq_initialize(); +#endif + + /* And finally, enable interrupts */ + +#ifndef CONFIG_SUPPRESS_INTERRUPTS + up_irq_enable(); +#endif +} + +/**************************************************************************** + * Name: up_disable_irq + * + * Description: + * Disable the IRQ specified by 'irq' + * + ****************************************************************************/ + +void up_disable_irq(int irq) +{ + uintptr_t regaddr; + uint32_t regval; + uint32_t bit; + + if (xmc4_irqinfo(irq, ®addr, &bit, NVIC_CLRENA_OFFSET) == 0) + { + /* Modify the appropriate bit in the register to disable the interrupt. + * For normal interrupts, we need to set the bit in the associated + * Interrupt Clear Enable register. For other exceptions, we need to + * clear the bit in the System Handler Control and State Register. + */ + + if (irq >= XMC4_IRQ_FIRST) + { + putreg32(bit, regaddr); + } + else + { + regval = getreg32(regaddr); + regval &= ~bit; + putreg32(regval, regaddr); + } + } + + xmc4_dump_nvic("disable", irq); +} + +/**************************************************************************** + * Name: up_enable_irq + * + * Description: + * Enable the IRQ specified by 'irq' + * + ****************************************************************************/ + +void up_enable_irq(int irq) +{ + uintptr_t regaddr; + uint32_t regval; + uint32_t bit; + + if (xmc4_irqinfo(irq, ®addr, &bit, NVIC_ENA_OFFSET) == 0) + { + /* Modify the appropriate bit in the register to enable the interrupt. + * For normal interrupts, we need to set the bit in the associated + * Interrupt Set Enable register. For other exceptions, we need to + * set the bit in the System Handler Control and State Register. + */ + + if (irq >= XMC4_IRQ_FIRST) + { + putreg32(bit, regaddr); + } + else + { + regval = getreg32(regaddr); + regval |= bit; + putreg32(regval, regaddr); + } + } + + xmc4_dump_nvic("enable", irq); +} + +/**************************************************************************** + * Name: up_ack_irq + * + * Description: + * Acknowledge the IRQ + * + ****************************************************************************/ + +void up_ack_irq(int irq) +{ +#if 0 /* Does not appear to be necessary in most cases */ + xmc4_clrpend(irq); +#endif +} + +/**************************************************************************** + * Name: up_prioritize_irq + * + * Description: + * Set the priority of an IRQ. + * + * Since this API is not supported on all architectures, it should be + * avoided in common implementations where possible. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQPRIO +int up_prioritize_irq(int irq, int priority) +{ + uint32_t regaddr; + uint32_t regval; + int shift; + + DEBUGASSERT(irq >= XMC4_IRQ_MEMFAULT && irq < NR_IRQS && + (unsigned)priority <= NVIC_SYSH_PRIORITY_MIN); + + if (irq < XMC4_IRQ_FIRST) + { + /* NVIC_SYSH_PRIORITY() maps {0..15} to one of three priority + * registers (0-3 are invalid) + */ + + regaddr = NVIC_SYSH_PRIORITY(irq); + irq -= 4; + } + else + { + /* NVIC_IRQ_PRIORITY() maps {0..} to one of many priority registers */ + + irq -= XMC4_IRQ_FIRST; + regaddr = NVIC_IRQ_PRIORITY(irq); + } + + regval = getreg32(regaddr); + shift = ((irq & 3) << 3); + regval &= ~(0xff << shift); + regval |= (priority << shift); + putreg32(regval, regaddr); + + xmc4_dump_nvic("prioritize", irq); + return OK; +} +#endif diff --git a/arch/arm/src/xmc4/xmc4_lowputc.c b/arch/arm/src/xmc4/xmc4_lowputc.c new file mode 100644 index 00000000000..8fe2f4094b8 --- /dev/null +++ b/arch/arm/src/xmc4/xmc4_lowputc.c @@ -0,0 +1,235 @@ +/**************************************************************************** + * arch/arm/src/xmc4/xmc4_lowputc.c + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include + +#include "up_internal.h" +#include "up_arch.h" + +#include "xmc4_config.h" +#include "chip/xmc4_uart.h" +#include "chip/xmc4_pinmux.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Select UART parameters for the selected console */ + +#if defined(HAVE_UART_CONSOLE) +# if defined(CONFIG_UART0_SERIAL_CONSOLE) +# define CONSOLE_BASE XMC4_UART0_BASE +# define CONSOLE_FREQ BOARD_CORECLK_FREQ +# define CONSOLE_BAUD CONFIG_UART0_BAUD +# define CONSOLE_BITS CONFIG_UART0_BITS +# define CONSOLE_2STOP CONFIG_UART0_2STOP +# define CONSOLE_PARITY CONFIG_UART0_PARITY +# elif defined(CONFIG_UART1_SERIAL_CONSOLE) +# define CONSOLE_BASE XMC4_UART1_BASE +# define CONSOLE_FREQ BOARD_CORECLK_FREQ +# define CONSOLE_BAUD CONFIG_UART1_BAUD +# define CONSOLE_BITS CONFIG_UART1_BITS +# define CONSOLE_2STOP CONFIG_UART1_2STOP +# define CONSOLE_PARITY CONFIG_UART1_PARITY +# elif defined(CONFIG_UART2_SERIAL_CONSOLE) +# define CONSOLE_BASE XMC4_UART2_BASE +# define CONSOLE_FREQ BOARD_BUS_FREQ +# define CONSOLE_BAUD CONFIG_UART2_BAUD +# define CONSOLE_BITS CONFIG_UART2_BITS +# define CONSOLE_2STOP CONFIG_UART2_2STOP +# define CONSOLE_PARITY CONFIG_UART2_PARITY +# elif defined(CONFIG_UART3_SERIAL_CONSOLE) +# define CONSOLE_BASE XMC4_UART3_BASE +# define CONSOLE_FREQ BOARD_BUS_FREQ +# define CONSOLE_BAUD CONFIG_UART3_BAUD +# define CONSOLE_BITS CONFIG_UART3_BITS +# define CONSOLE_2STOP CONFIG_UART3_2STOP +# define CONSOLE_PARITY CONFIG_UART3_PARITY +# elif defined(CONFIG_UART4_SERIAL_CONSOLE) +# define CONSOLE_BASE XMC4_UART4_BASE +# define CONSOLE_FREQ BOARD_BUS_FREQ +# define CONSOLE_BAUD CONFIG_UART4_BAUD +# define CONSOLE_BITS CONFIG_UART4_BITS +# define CONSOLE_2STOP CONFIG_UART4_2STOP +# define CONSOLE_PARITY CONFIG_UART4_PARITY +# elif defined(CONFIG_UART5_SERIAL_CONSOLE) +# define CONSOLE_BASE XMC4_UART5_BASE +# define CONSOLE_FREQ BOARD_BUS_FREQ +# define CONSOLE_BAUD CONFIG_UART5_BAUD +# define CONSOLE_BITS CONFIG_UART5_BITS +# define CONSOLE_2STOP CONFIG_UART5_2STOP +# define CONSOLE_PARITY CONFIG_UART5_PARITY +# elif defined(HAVE_UART_CONSOLE) +# error "No CONFIG_UARTn_SERIAL_CONSOLE Setting" +# endif +#endif /* HAVE_UART_CONSOLE */ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_lowputc + * + * Description: + * Output one byte on the serial console + * + ****************************************************************************/ + +void up_lowputc(char ch) +{ +#ifdef HAVE_UART_CONSOLE + /* Wait until the transmit data register is "empty" (TDRE). This state + * depends on the TX watermark setting and may not mean that the transmit + * buffer is truly empty. It just means that we can now add another + * character to the transmit buffer without exceeding the watermark. + * + * NOTE: UART0 has an 8-byte deep FIFO; the other UARTs have no FIFOs + * (1-deep). There appears to be no way to know when the FIFO is not + * full (other than reading the FIFO length and comparing the FIFO count). + * Hence, the FIFOs are not used in this implementation and, as a result + * TDRE indeed mean that the single output buffer is available. + * + * Performance on UART0 could be improved by enabling the FIFO and by + * redesigning all of the FIFO status logic. + */ +#warning Missing logic + + /* Then write the character to the UART data register */ + +#warning Missing logic +} + +/**************************************************************************** + * Name: xmc4_lowsetup + * + * Description: + * This performs basic initialization of the UART used for the serial + * console. Its purpose is to get the console output available as soon + * as possible. + * + ****************************************************************************/ + +void xmc4_lowsetup(void) +{ + uint32_t regval; + + /* Enable peripheral clocking for all enabled UARTs. */ +#wanring Missing logic + + /* Configure UART pins for the all enabled UARTs */ + + /* Configure the console (only) now. Other UARTs will be configured + * when the serial driver is opened. + */ + + xmc4_uart_configure(CONSOLE_BASE, CONSOLE_BAUD, CONSOLE_FREQ, \ + CONSOLE_PARITY, CONSOLE_BITS, CONSOLE_2STOP); +#endif /* HAVE_UART_DEVICE */ +} + +/**************************************************************************** + * Name: xmc4_uart_reset + * + * Description: + * Reset a UART. + * + ****************************************************************************/ + +#ifdef HAVE_UART_DEVICE +void xmc4_uart_reset(uintptr_t uart_base) +{ + uint8_t regval; + + /* Just disable the transmitter and receiver */ +#warning Missing logic +} +#endif + +/**************************************************************************** + * Name: xmc4_uart_configure + * + * Description: + * Configure a UART as a RS-232 UART. + * + ****************************************************************************/ + +#ifdef HAVE_UART_DEVICE +void xmc4_uart_configure(uintptr_t uart_base, uint32_t baud, + uint32_t clock, unsigned int parity, + unsigned int nbits, unsigned int stop2) +{ + /* Disable the transmitter and receiver throughout the reconfiguration */ +#warning Missing logic + + /* Configure number of bits, stop bits and parity */ +#warning Missing logic + + /* Check for odd parity */ +#warning Missing logic + + /* Check for even parity */ +#warning Missing logic + + /* Check for 9-bit operation */ +#warning Missing logic + + /* Calculate baud settings (truncating) */ +#warning Missing logic + + /* Configure FIFOs */ +#warning Missing logic + + /* Enable RX and TX FIFOs */ +#warning Missing logic + + /* Now we can (re-)enable the transmitter and receiver */ +#warning Missing logic +} +#endif + diff --git a/arch/arm/src/xmc4/xmc4_mpuinit.c b/arch/arm/src/xmc4/xmc4_mpuinit.c new file mode 100644 index 00000000000..9cd22451be4 --- /dev/null +++ b/arch/arm/src/xmc4/xmc4_mpuinit.c @@ -0,0 +1,124 @@ +/**************************************************************************** + * arch/arm/src/xmc4/xmc4_mpuinit.c + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include + +#include "mpu.h" +#include "xmc4_mpuinit.h" + +#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_ARM_MPU) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef MAX +# define MAX(a,b) a > b ? a : b +#endif + +#ifndef MIN +# define MIN(a,b) a < b ? a : b +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: xmc4_mpuinitialize + * + * Description: + * Configure the MPU to permit user-space access to only restricted SAM3U + * resources. + * + ****************************************************************************/ + +void xmc4_mpuinitialize(void) +{ + uintptr_t datastart = MIN(USERSPACE->us_datastart, USERSPACE->us_bssstart); + uintptr_t dataend = MAX(USERSPACE->us_dataend, USERSPACE->us_bssend); + + DEBUGASSERT(USERSPACE->us_textend >= USERSPACE->us_textstart && + dataend >= datastart); + + /* Show MPU information */ + + mpu_showtype(); + + /* Configure user flash and SRAM space */ + + mpu_user_flash(USERSPACE->us_textstart, + USERSPACE->us_textend - USERSPACE->us_textstart); + + mpu_user_intsram(datastart, dataend - datastart); + + /* Then enable the MPU */ + + mpu_control(true, false, true); +} + +/**************************************************************************** + * Name: xmc4_mpu_uheap + * + * Description: + * Map the user-heap region. + * + * This logic may need an extension to handle external SDRAM). + * + ****************************************************************************/ + +void xmc4_mpu_uheap(uintptr_t start, size_t size) +{ + mpu_user_intsram(start, size); +} + +#endif /* CONFIG_BUILD_PROTECTED && CONFIG_ARM_MPU */ + diff --git a/arch/arm/src/xmc4/xmc4_mpuinit.h b/arch/arm/src/xmc4/xmc4_mpuinit.h new file mode 100644 index 00000000000..f318424bad7 --- /dev/null +++ b/arch/arm/src/xmc4/xmc4_mpuinit.h @@ -0,0 +1,78 @@ +/************************************************************************************ + * arch/arm/src/xmc4/xmc4_mpuinit.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_XMC4_XMC4_MPUINIT_H +#define __ARCH_ARM_SRC_XMC4_XMC4_MPUINIT_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/**************************************************************************** + * Name: xmc4_mpuinitialize + * + * Description: + * Configure the MPU to permit user-space access to only unrestricted MCU + * resources. + * + ****************************************************************************/ + +#ifdef CONFIG_BUILD_PROTECTED +void xmc4_mpuinitialize(void); +#else +# define xmc4_mpuinitialize() +#endif + +/**************************************************************************** + * Name: xmc4_mpu_uheap + * + * Description: + * Map the user heap region. + * + ****************************************************************************/ + +#ifdef CONFIG_BUILD_PROTECTED +void xmc4_mpu_uheap(uintptr_t start, size_t size); +#else +# define xmc4_mpu_uheap(start,size) +#endif + +#endif /* __ARCH_ARM_SRC_XMC4_XMC4_MPUINIT_H */ diff --git a/arch/arm/src/xmc4/xmc4_pwm.c b/arch/arm/src/xmc4/xmc4_pwm.c new file mode 100644 index 00000000000..e69de29bb2d diff --git a/arch/arm/src/xmc4/xmc4_pwm.h b/arch/arm/src/xmc4/xmc4_pwm.h new file mode 100644 index 00000000000..4de5b5f56aa --- /dev/null +++ b/arch/arm/src/xmc4/xmc4_pwm.h @@ -0,0 +1,100 @@ +/************************************************************************************ + * arch/arm/src/xmc4/xmc4_pwm.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_XMC4_XMC4_PWM_H +#define __ARCH_ARM_SRC_XMC4_XMC4_PWM_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include "chip.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Configuration ********************************************************************/ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: xmc4_pwm_initialize + * + * Description: + * Initialize one timer for use with the upper_level PWM driver. + * + * Input Parameters: + * timer - A number identifying the timer use. + * + * Returned Value: + * On success, a pointer to the kinetis lower half PWM driver is returned. + * NULL is returned on any failure. + * + ************************************************************************************/ + +FAR struct pwm_lowerhalf_s *xmc4_pwm_initialize(int timer); + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* CONFIG_XMC4_FTMx_PWM */ +#endif /* __ARCH_ARM_SRC_XMC4_XMC4_PWM_H */ diff --git a/arch/arm/src/xmc4/xmc4_serial.c b/arch/arm/src/xmc4/xmc4_serial.c new file mode 100644 index 00000000000..b90f1c19ff1 --- /dev/null +++ b/arch/arm/src/xmc4/xmc4_serial.c @@ -0,0 +1,1146 @@ +/**************************************************************************** + * arch/arm/src/xmc4/xmc4_serial.c + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include + +#include "up_arch.h" +#include "up_internal.h" + +#include "xmc4_config.h" +#include "chip.h" +#include "chip/xmc4_uart.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ +/* Some sanity checks *******************************************************/ +/* Is there at least one UART enabled and configured as a RS-232 device? */ + +#ifndef HAVE_UART_DEVICE +# warning "No UARTs enabled" +#endif + +/* If we are not using the serial driver for the console, then we still must + * provide some minimal implementation of up_putc. + */ + +#if defined(HAVE_UART_DEVICE) && defined(USE_SERIALDRIVER) + +/* Which UART with be tty0/console and which tty1-4? The console will always + * be ttyS0. If there is no console then will use the lowest numbered UART. + */ + +/* First pick the console and ttys0. This could be any of UART0-5 */ + +#if defined(CONFIG_UART0_SERIAL_CONSOLE) +# define CONSOLE_DEV g_uart0port /* UART0 is console */ +# define TTYS0_DEV g_uart0port /* UART0 is ttyS0 */ +# define UART0_ASSIGNED 1 +#elif defined(CONFIG_UART1_SERIAL_CONSOLE) +# define CONSOLE_DEV g_uart1port /* UART1 is console */ +# define TTYS0_DEV g_uart1port /* UART1 is ttyS0 */ +# define UART1_ASSIGNED 1 +#elif defined(CONFIG_UART2_SERIAL_CONSOLE) +# define CONSOLE_DEV g_uart2port /* UART2 is console */ +# define TTYS0_DEV g_uart2port /* UART2 is ttyS0 */ +# define UART2_ASSIGNED 1 +#elif defined(CONFIG_UART3_SERIAL_CONSOLE) +# define CONSOLE_DEV g_uart3port /* UART3 is console */ +# define TTYS0_DEV g_uart3port /* UART3 is ttyS0 */ +# define UART3_ASSIGNED 1 +#elif defined(CONFIG_UART4_SERIAL_CONSOLE) +# define CONSOLE_DEV g_uart4port /* UART4 is console */ +# define TTYS0_DEV g_uart4port /* UART4 is ttyS0 */ +# define UART4_ASSIGNED 1 +#elif defined(CONFIG_UART5_SERIAL_CONSOLE) +# define CONSOLE_DEV g_uart5port /* UART5 is console */ +# define TTYS5_DEV g_uart5port /* UART5 is ttyS0 */ +# define UART5_ASSIGNED 1 +#else +# undef CONSOLE_DEV /* No console */ +# if defined(CONFIG_XMC4_USIC0_ISUART) +# define TTYS0_DEV g_uart0port /* UART0 is ttyS0 */ +# define UART0_ASSIGNED 1 +# elif defined(CONFIG_XMC4_USIC1_ISUART) +# define TTYS0_DEV g_uart1port /* UART1 is ttyS0 */ +# define UART1_ASSIGNED 1 +# elif defined(CONFIG_XMC4_USIC2_ISUART) +# define TTYS0_DEV g_uart2port /* UART2 is ttyS0 */ +# define UART2_ASSIGNED 1 +# elif defined(CONFIG_XMC4_USIC3_ISUART) +# define TTYS0_DEV g_uart3port /* UART3 is ttyS0 */ +# define UART3_ASSIGNED 1 +# elif defined(CONFIG_XMC4_USIC4_ISUART) +# define TTYS0_DEV g_uart4port /* UART4 is ttyS0 */ +# define UART4_ASSIGNED 1 +# elif defined(CONFIG_XMC4_USIC5_ISUART) +# define TTYS0_DEV g_uart5port /* UART5 is ttyS0 */ +# define UART5_ASSIGNED 1 +# endif +#endif + +/* Pick ttys1. This could be any of UART0-5 excluding the console UART. */ + +#if defined(CONFIG_XMC4_USIC0_ISUART) && !defined(UART0_ASSIGNED) +# define TTYS1_DEV g_uart0port /* UART0 is ttyS1 */ +# define UART0_ASSIGNED 1 +#elif defined(CONFIG_XMC4_USIC1_ISUART) && !defined(UART1_ASSIGNED) +# define TTYS1_DEV g_uart1port /* UART1 is ttyS1 */ +# define UART1_ASSIGNED 1 +#elif defined(CONFIG_XMC4_USIC2_ISUART) && !defined(UART2_ASSIGNED) +# define TTYS1_DEV g_uart2port /* UART2 is ttyS1 */ +# define UART2_ASSIGNED 1 +#elif defined(CONFIG_XMC4_USIC3_ISUART) && !defined(UART3_ASSIGNED) +# define TTYS1_DEV g_uart3port /* UART3 is ttyS1 */ +# define UART3_ASSIGNED 1 +#elif defined(CONFIG_XMC4_USIC4_ISUART) && !defined(UART4_ASSIGNED) +# define TTYS1_DEV g_uart4port /* UART4 is ttyS1 */ +# define UART4_ASSIGNED 1 +#elif defined(CONFIG_XMC4_USIC5_ISUART) && !defined(UART5_ASSIGNED) +# define TTYS1_DEV g_uart5port /* UART5 is ttyS1 */ +# define UART5_ASSIGNED 1 +#endif + +/* Pick ttys2. This could be one of UART1-5. It can't be UART0 because that + * was either assigned as ttyS0 or ttys1. One of UART 1-5 could also be the + * console. + */ + +#if defined(CONFIG_XMC4_USIC1_ISUART) && !defined(UART1_ASSIGNED) +# define TTYS2_DEV g_uart1port /* UART1 is ttyS2 */ +# define UART1_ASSIGNED 1 +#elif defined(CONFIG_XMC4_USIC2_ISUART) && !defined(UART2_ASSIGNED) +# define TTYS2_DEV g_uart2port /* UART2 is ttyS2 */ +# define UART2_ASSIGNED 1 +#elif defined(CONFIG_XMC4_USIC3_ISUART) && !defined(UART3_ASSIGNED) +# define TTYS2_DEV g_uart3port /* UART3 is ttyS2 */ +# define UART3_ASSIGNED 1 +#elif defined(CONFIG_XMC4_USIC4_ISUART) && !defined(UART4_ASSIGNED) +# define TTYS2_DEV g_uart4port /* UART4 is ttyS2 */ +# define UART4_ASSIGNED 1 +#elif defined(CONFIG_XMC4_USIC5_ISUART) && !defined(UART5_ASSIGNED) +# define TTYS2_DEV g_uart5port /* UART5 is ttyS2 */ +# define UART5_ASSIGNED 1 +#endif + +/* Pick ttys3. This could be one of UART2-5. It can't be UART0-1 because + * those have already been assigned to ttsyS0, 1, or 2. One of + * UART 2-5 could also be the console. + */ + +#if defined(CONFIG_XMC4_USIC2_ISUART) && !defined(UART2_ASSIGNED) +# define TTYS3_DEV g_uart2port /* UART2 is ttyS3 */ +# define UART2_ASSIGNED 1 +#elif defined(CONFIG_XMC4_USIC3_ISUART) && !defined(UART3_ASSIGNED) +# define TTYS3_DEV g_uart3port /* UART3 is ttyS3 */ +# define UART3_ASSIGNED 1 +#elif defined(CONFIG_XMC4_USIC4_ISUART) && !defined(UART4_ASSIGNED) +# define TTYS3_DEV g_uart4port /* UART4 is ttyS3 */ +# define UART4_ASSIGNED 1 +#elif defined(CONFIG_XMC4_USIC5_ISUART) && !defined(UART5_ASSIGNED) +# define TTYS3_DEV g_uart5port /* UART5 is ttyS3 */ +# define UART5_ASSIGNED 1 +#endif + +/* Pick ttys4. This could be one of UART3-5. It can't be UART0-2 because + * those have already been assigned to ttsyS0, 1, 2 or 3. One of + * UART 3-5 could also be the console. + */ + +#if defined(CONFIG_XMC4_USIC3_ISUART) && !defined(UART3_ASSIGNED) +# define TTYS4_DEV g_uart3port /* UART3 is ttyS4 */ +# define UART3_ASSIGNED 1 +#elif defined(CONFIG_XMC4_USIC4_ISUART) && !defined(UART4_ASSIGNED) +# define TTYS4_DEV g_uart4port /* UART4 is ttyS4 */ +# define UART4_ASSIGNED 1 +#elif defined(CONFIG_XMC4_USIC5_ISUART) && !defined(UART5_ASSIGNED) +# define TTYS4_DEV g_uart5port /* UART5 is ttyS4 */ +# define UART5_ASSIGNED 1 +#endif + +/* Pick ttys5. This could be one of UART4-5. It can't be UART0-3 because + * those have already been assigned to ttsyS0, 1, 2, 3 or 4. One of + * UART 4-5 could also be the console. + */ + +#if defined(CONFIG_XMC4_USIC4_ISUART) && !defined(UART4_ASSIGNED) +# define TTYS5_DEV g_uart4port /* UART4 is ttyS5 */ +# define UART4_ASSIGNED 1 +#elif defined(CONFIG_XMC4_USIC5_ISUART) && !defined(UART5_ASSIGNED) +# define TTYS5_DEV g_uart5port /* UART5 is ttyS5 */ +# define UART5_ASSIGNED 1 +#endif + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct xmc4_dev_s +{ + uintptr_t uartbase; /* Base address of UART registers */ + uint32_t baud; /* Configured baud */ + uint32_t clock; /* Clocking frequency of the UART module */ + uint8_t irqs; /* Status IRQ associated with this UART (for enable) */ + uint8_t ie; /* Interrupts enabled */ + uint8_t parity; /* 0=none, 1=odd, 2=even */ + uint8_t bits; /* Number of bits (8 or 9) */ + uint8_t stop2; /* Use 2 stop bits */ +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static int xmc4_setup(struct uart_dev_s *dev); +static void xmc4_shutdown(struct uart_dev_s *dev); +static int xmc4_attach(struct uart_dev_s *dev); +static void xmc4_detach(struct uart_dev_s *dev); +static int xmc4_interrupt(int irq, void *context, FAR void *arg); +static int xmc4_ioctl(struct file *filep, int cmd, unsigned long arg); +static int xmc4_receive(struct uart_dev_s *dev, uint32_t *status); +static void xmc4_rxint(struct uart_dev_s *dev, bool enable); +static bool xmc4_rxavailable(struct uart_dev_s *dev); +static void xmc4_send(struct uart_dev_s *dev, int ch); +static void xmc4_txint(struct uart_dev_s *dev, bool enable); +static bool xmc4_txready(struct uart_dev_s *dev); +static bool xmc4_txempty(struct uart_dev_s *dev); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const struct uart_ops_s g_uart_ops = +{ + .setup = xmc4_setup, + .shutdown = xmc4_shutdown, + .attach = xmc4_attach, + .detach = xmc4_detach, + .ioctl = xmc4_ioctl, + .receive = xmc4_receive, + .rxint = xmc4_rxint, + .rxavailable = xmc4_rxavailable, +#ifdef CONFIG_SERIAL_IFLOWCONTROL + .rxflowcontrol = NULL, +#endif + .send = xmc4_send, + .txint = xmc4_txint, + .txready = xmc4_txready, + .txempty = xmc4_txempty, +}; + +/* I/O buffers */ + +#ifdef CONFIG_XMC4_USIC0_ISUART +static char g_uart0rxbuffer[CONFIG_UART0_RXBUFSIZE]; +static char g_uart0txbuffer[CONFIG_UART0_TXBUFSIZE]; +#endif +#ifdef CONFIG_XMC4_USIC1_ISUART +static char g_uart1rxbuffer[CONFIG_UART1_RXBUFSIZE]; +static char g_uart1txbuffer[CONFIG_UART1_TXBUFSIZE]; +#endif +#ifdef CONFIG_XMC4_USIC2_ISUART +static char g_uart2rxbuffer[CONFIG_UART2_RXBUFSIZE]; +static char g_uart2txbuffer[CONFIG_UART2_TXBUFSIZE]; +#endif +#ifdef CONFIG_XMC4_USIC3_ISUART +static char g_uart3rxbuffer[CONFIG_UART3_RXBUFSIZE]; +static char g_uart3txbuffer[CONFIG_UART3_TXBUFSIZE]; +#endif +#ifdef CONFIG_XMC4_USIC4_ISUART +static char g_uart4rxbuffer[CONFIG_UART4_RXBUFSIZE]; +static char g_uart4txbuffer[CONFIG_UART4_TXBUFSIZE]; +#endif +#ifdef CONFIG_XMC4_USIC5_ISUART +static char g_uart5rxbuffer[CONFIG_UART5_RXBUFSIZE]; +static char g_uart5txbuffer[CONFIG_UART5_TXBUFSIZE]; +#endif + +/* This describes the state of the Kinetis UART0 port. */ + +#ifdef CONFIG_XMC4_USIC0_ISUART +static struct xmc4_dev_s g_uart0priv = +{ + .uartbase = XMC4_UART0_BASE, + .clock = BOARD_CORECLK_FREQ, + .baud = CONFIG_UART0_BAUD, + .irqs = XMC4_IRQ_USIC0, + .parity = CONFIG_UART0_PARITY, + .bits = CONFIG_UART0_BITS, + .stop2 = CONFIG_UART0_2STOP, +}; + +static uart_dev_t g_uart0port = +{ + .recv = + { + .size = CONFIG_UART0_RXBUFSIZE, + .buffer = g_uart0rxbuffer, + }, + .xmit = + { + .size = CONFIG_UART0_TXBUFSIZE, + .buffer = g_uart0txbuffer, + }, + .ops = &g_uart_ops, + .priv = &g_uart0priv, +}; +#endif + +/* This describes the state of the Kinetis UART1 port. */ + +#ifdef CONFIG_XMC4_USIC1_ISUART +static struct xmc4_dev_s g_uart1priv = +{ + .uartbase = XMC4_UART1_BASE, + .clock = BOARD_CORECLK_FREQ, + .baud = CONFIG_UART1_BAUD, + .irqs = XMC4_IRQ_USIC1, + .parity = CONFIG_UART1_PARITY, + .bits = CONFIG_UART1_BITS, + .stop2 = CONFIG_UART1_2STOP, +}; + +static uart_dev_t g_uart1port = +{ + .recv = + { + .size = CONFIG_UART1_RXBUFSIZE, + .buffer = g_uart1rxbuffer, + }, + .xmit = + { + .size = CONFIG_UART1_TXBUFSIZE, + .buffer = g_uart1txbuffer, + }, + .ops = &g_uart_ops, + .priv = &g_uart1priv, +}; +#endif + +/* This describes the state of the Kinetis UART2 port. */ + +#ifdef CONFIG_XMC4_USIC2_ISUART +static struct xmc4_dev_s g_uart2priv = +{ + .uartbase = XMC4_UART2_BASE, + .clock = BOARD_BUS_FREQ, + .baud = CONFIG_UART2_BAUD, + .irqs = XMC4_IRQ_USIC2, + .parity = CONFIG_UART2_PARITY, + .bits = CONFIG_UART2_BITS, + .stop2 = CONFIG_UART2_2STOP, +}; + +static uart_dev_t g_uart2port = +{ + .recv = + { + .size = CONFIG_UART2_RXBUFSIZE, + .buffer = g_uart2rxbuffer, + }, + .xmit = + { + .size = CONFIG_UART2_TXBUFSIZE, + .buffer = g_uart2txbuffer, + }, + .ops = &g_uart_ops, + .priv = &g_uart2priv, +}; +#endif + +/* This describes the state of the Kinetis UART3 port. */ + +#ifdef CONFIG_XMC4_USIC3_ISUART +static struct xmc4_dev_s g_uart3priv = +{ + .uartbase = XMC4_UART3_BASE, + .clock = BOARD_BUS_FREQ, + .baud = CONFIG_UART3_BAUD, + .irqs = XMC4_IRQ_USIC3, + .parity = CONFIG_UART3_PARITY, + .bits = CONFIG_UART3_BITS, + .stop2 = CONFIG_UART3_2STOP, +}; + +static uart_dev_t g_uart3port = +{ + .recv = + { + .size = CONFIG_UART3_RXBUFSIZE, + .buffer = g_uart3rxbuffer, + }, + .xmit = + { + .size = CONFIG_UART3_TXBUFSIZE, + .buffer = g_uart3txbuffer, + }, + .ops = &g_uart_ops, + .priv = &g_uart3priv, +}; +#endif + +/* This describes the state of the Kinetis UART4 port. */ + +#ifdef CONFIG_XMC4_USIC4_ISUART +static struct xmc4_dev_s g_uart4priv = +{ + .uartbase = XMC4_UART4_BASE, + .clock = BOARD_BUS_FREQ, + .baud = CONFIG_UART4_BAUD, + .irqs = XMC4_IRQ_USIC4, + .parity = CONFIG_UART4_PARITY, + .bits = CONFIG_UART4_BITS, + .stop2 = CONFIG_UART4_2STOP, +}; + +static uart_dev_t g_uart4port = +{ + .recv = + { + .size = CONFIG_UART4_RXBUFSIZE, + .buffer = g_uart4rxbuffer, + }, + .xmit = + { + .size = CONFIG_UART4_TXBUFSIZE, + .buffer = g_uart4txbuffer, + }, + .ops = &g_uart_ops, + .priv = &g_uart4priv, +}; +#endif + +/* This describes the state of the Kinetis UART5 port. */ + +#ifdef CONFIG_XMC4_USIC5_ISUART +static struct xmc4_dev_s g_uart5priv = +{ + .uartbase = XMC4_UART5_BASE, + .clock = BOARD_BUS_FREQ, + .baud = CONFIG_UART5_BAUD, + .irqs = XMC4_IRQ_USIC5, + .parity = CONFIG_UART5_PARITY, + .bits = CONFIG_UART5_BITS, + .stop2 = CONFIG_UART5_2STOP, +}; + +static uart_dev_t g_uart5port = +{ + .recv = + { + .size = CONFIG_UART5_RXBUFSIZE, + .buffer = g_uart5rxbuffer, + }, + .xmit = + { + .size = CONFIG_UART5_TXBUFSIZE, + .buffer = g_uart5txbuffer, + }, + .ops = &g_uart_ops, + .priv = &g_uart5priv, +}; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_serialin + ****************************************************************************/ + +static inline uint8_t up_serialin(struct xmc4_dev_s *priv, int offset) +{ + return getreg8(priv->uartbase + offset); +} + +/**************************************************************************** + * Name: up_serialout + ****************************************************************************/ + +static inline void up_serialout(struct xmc4_dev_s *priv, int offset, uint8_t value) +{ + putreg8(value, priv->uartbase + offset); +} + +/**************************************************************************** + * Name: up_setuartint + ****************************************************************************/ + +static void up_setuartint(struct xmc4_dev_s *priv) +{ + irqstate_t flags; + uint8_t regval; + + /* Re-enable/re-disable interrupts corresponding to the state of bits in ie */ +#warning Missing logic + + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: up_restoreuartint + ****************************************************************************/ + +static void up_restoreuartint(struct xmc4_dev_s *priv, uint8_t ie) +{ + irqstate_t flags; + + /* Re-enable/re-disable interrupts corresponding to the state of bits in ie */ + + flags = enter_critical_section(); +#warning Missing logic + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: up_disableuartint + ****************************************************************************/ + +static void up_disableuartint(struct xmc4_dev_s *priv, uint8_t *ie) +{ + irqstate_t flags; + + flags = enter_critical_section(); + if (ie) + { + *ie = priv->ie; + } + + up_restoreuartint(priv, 0); + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: xmc4_setup + * + * Description: + * Configure the UART baud, bits, parity, etc. This method is called the + * first time that the serial port is opened. + * + ****************************************************************************/ + +static int xmc4_setup(struct uart_dev_s *dev) +{ +#ifndef CONFIG_SUPPRESS_UART_CONFIG + struct xmc4_dev_s *priv = (struct xmc4_dev_s *)dev->priv; + + /* Configure the UART as an RS-232 UART */ + + xmc4_uart_configure(priv->uartbase, priv->baud, priv->clock, + priv->parity, priv->bits, priv->stop2); +#endif + + /* Make sure that all interrupts are disabled */ + + up_restoreuartint(priv, 0); + return OK; +} + +/**************************************************************************** + * Name: xmc4_shutdown + * + * Description: + * Disable the UART. This method is called when the serial + * port is closed + * + ****************************************************************************/ + +static void xmc4_shutdown(struct uart_dev_s *dev) +{ + struct xmc4_dev_s *priv = (struct xmc4_dev_s *)dev->priv; + + /* Disable interrupts */ + + up_restoreuartint(priv, 0); + + /* Reset hardware and disable Rx and Tx */ + + xmc4_uart_reset(priv->uartbase); +} + +/**************************************************************************** + * Name: xmc4_attach + * + * Description: + * Configure the UART to operation in interrupt driven mode. This method is + * called when the serial port is opened. Normally, this is just after the + * the setup() method is called, however, the serial console may operate in + * a non-interrupt driven mode during the boot phase. + * + * RX and TX interrupts are not enabled when by the attach method (unless the + * hardware supports multiple levels of interrupt enabling). The RX and TX + * interrupts are not enabled until the txint() and rxint() methods are called. + * + ****************************************************************************/ + +static int xmc4_attach(struct uart_dev_s *dev) +{ + struct xmc4_dev_s *priv = (struct xmc4_dev_s *)dev->priv; + int ret; + + /* Attach and enable the IRQ(s). The interrupts are (probably) still + * disabled in the C2 register. + */ + + ret = irq_attach(priv->irqs, xmc4_interrupt, dev); + if (ret == OK) + { + up_enable_irq(priv->irqs); + } + + return ret; +} + +/**************************************************************************** + * Name: xmc4_detach + * + * Description: + * Detach UART interrupts. This method is called when the serial port is + * closed normally just before the shutdown method is called. The exception + * is the serial console which is never shutdown. + * + ****************************************************************************/ + +static void xmc4_detach(struct uart_dev_s *dev) +{ + struct xmc4_dev_s *priv = (struct xmc4_dev_s *)dev->priv; + + /* Disable interrupts */ + + up_restoreuartint(priv, 0); + up_disable_irq(priv->irqs); + + /* Detach from the interrupt(s) */ + + irq_detach(priv->irqs); +} + +/**************************************************************************** + * Name: xmc4_interrupt + * + * Description: + * This is the UART status interrupt handler. It will be invoked when an + * interrupt received on the 'irq' It should call uart_transmitchars or + * uart_receivechar to perform the appropriate data transfers. The + * interrupt handling logic must be able to map the 'irq' number into the + * approprite uart_dev_s structure in order to call these functions. + * + ****************************************************************************/ + +static int xmc4_interrupt(int irq, void *context, FAR void *arg) +{ + struct uart_dev_s *dev = (struct uart_dev_s *)arg; + struct xmc4_dev_s *priv; + int passes; + uint8_t s1; + bool handled; + + DEBUGASSERT(dev != NULL && dev->priv != NULL); + priv = (struct xmc4_dev_s *)dev->priv; + + /* Loop until there are no characters to be transferred or, + * until we have been looping for a long time. + */ + + handled = true; + for (passes = 0; passes < 256 && handled; passes++) + { + handled = false; + + /* Read status register 1 */ + + s1 = up_serialin(priv, XMC4_UART_S1_OFFSET); + + /* Handle incoming, receive bytes */ + + /* Check if the receive data register is full (RDRF). NOTE: If + * FIFOS are enabled, this does not mean that the FIFO is full, + * rather, it means that the number of bytes in the RX FIFO has + * exceeded the watermark setting. There may actually be RX data + * available! + * + * The RDRF status indication is cleared when the data is read from + * the RX data register. + */ + +#warning Missing logic + { + /* Process incoming bytes */ + + uart_recvchars(dev); + handled = true; + } + + /* Handle outgoing, transmit bytes */ + + /* Check if the transmit data register is "empty." NOTE: If FIFOS + * are enabled, this does not mean that the FIFO is empty, rather, + * it means that the number of bytes in the TX FIFO is below the + * watermark setting. There could actually be space for additional TX + * data. + * + * The TDRE status indication is cleared when the data is written to + * the TX data register. + */ + +#warning Missing logic + { + /* Process outgoing bytes */ + + uart_xmitchars(dev); + handled = true; + } + } + + return OK; +} + +/**************************************************************************** + * Name: xmc4_ioctl + * + * Description: + * All ioctl calls will be routed through this method + * + ****************************************************************************/ + +static int xmc4_ioctl(struct file *filep, int cmd, unsigned long arg) +{ +#if 0 /* Reserved for future growth */ + struct inode *inode; + struct uart_dev_s *dev; + struct xmc4_dev_s *priv; + int ret = OK; + + DEBUGASSERT(filep, filep->f_inode); + inode = filep->f_inode; + dev = inode->i_private; + + DEBUGASSERT(dev, dev->priv); + priv = (struct xmc4_dev_s *)dev->priv; + + switch (cmd) + { + case xxx: /* Add commands here */ + break; + + default: + ret = -ENOTTY; + break; + } + + return ret; +#else + return -ENOTTY; +#endif +} + +/**************************************************************************** + * Name: xmc4_receive + * + * Description: + * Called (usually) from the interrupt level to receive one + * character from the UART. Error bits associated with the + * receipt are provided in the return 'status'. + * + ****************************************************************************/ + +static int xmc4_receive(struct uart_dev_s *dev, uint32_t *status) +{ + struct xmc4_dev_s *priv = (struct xmc4_dev_s *)dev->priv; + uint8_t s1; + + /* Get error status information: + * + * FE: Framing error. To clear FE, read S1 with FE set and then read + * read UART data register (D). + * NF: Noise flag. To clear NF, read S1 and then read the UART data + * register (D). + * PF: Parity error flag. To clear PF, read S1 and then read the UART + * data register (D). + */ + + s1 = up_serialin(priv, XMC4_UART_S1_OFFSET); + + /* Return status information */ + + if (status) + { + *status = (uint32_t)s1; + } + + /* Then return the actual received byte. Reading S1 then D clears all + * RX errors. + */ + + return (int)up_serialin(priv, XMC4_UART_D_OFFSET); +} + +/**************************************************************************** + * Name: xmc4_rxint + * + * Description: + * Call to enable or disable RX interrupts + * + ****************************************************************************/ + +static void xmc4_rxint(struct uart_dev_s *dev, bool enable) +{ + struct xmc4_dev_s *priv = (struct xmc4_dev_s *)dev->priv; + irqstate_t flags; + + flags = enter_critical_section(); + if (enable) + { + /* Receive an interrupt when their is anything in the Rx data register (or an Rx + * timeout occurs). + */ + +#ifndef CONFIG_SUPPRESS_SERIAL_INTS + priv->ie |= UART_C2_RIE; + up_setuartint(priv); +#endif + } + else + { +#ifdef CONFIG_DEBUG_FEATURES +# warning "Revisit: How are errors enabled?" + priv->ie &= ~UART_C2_RIE; +#else + priv->ie &= ~UART_C2_RIE; +#endif + up_setuartint(priv); + } + + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: xmc4_rxavailable + * + * Description: + * Return true if the receive register is not empty + * + ****************************************************************************/ + +static bool xmc4_rxavailable(struct uart_dev_s *dev) +{ + struct xmc4_dev_s *priv = (struct xmc4_dev_s *)dev->priv; + /* Return true if the receive data register is full (RDRF). NOTE: If + * FIFOS are enabled, this does not mean that the FIFO is full, + * rather, it means that the number of bytes in the RX FIFO has + * exceeded the watermark setting. There may actually be RX data + * available! + */ + + return (up_serialin(priv, XMC4_UART_S1_OFFSET) & UART_S1_RDRF) != 0; +} + +/**************************************************************************** + * Name: xmc4_send + * + * Description: + * This method will send one byte on the UART. + * + ****************************************************************************/ + +static void xmc4_send(struct uart_dev_s *dev, int ch) +{ + struct xmc4_dev_s *priv = (struct xmc4_dev_s *)dev->priv; + up_serialout(priv, XMC4_UART_D_OFFSET, (uint8_t)ch); +} + +/**************************************************************************** + * Name: xmc4_txint + * + * Description: + * Call to enable or disable TX interrupts + * + ****************************************************************************/ + +static void xmc4_txint(struct uart_dev_s *dev, bool enable) +{ + struct xmc4_dev_s *priv = (struct xmc4_dev_s *)dev->priv; + irqstate_t flags; + + flags = enter_critical_section(); + if (enable) + { + /* Enable the TX interrupt */ + +#ifndef CONFIG_SUPPRESS_SERIAL_INTS + priv->ie |= UART_C2_TIE; + up_setuartint(priv); + + /* Fake a TX interrupt here by just calling uart_xmitchars() with + * interrupts disabled (note this may recurse). + */ + + uart_xmitchars(dev); +#endif + } + else + { + /* Disable the TX interrupt */ + + priv->ie &= ~UART_C2_TIE; + up_setuartint(priv); + } + + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: xmc4_txready + * + * Description: + * Return true if the tranmsit data register is empty + * + ****************************************************************************/ + +static bool xmc4_txready(struct uart_dev_s *dev) +{ + struct xmc4_dev_s *priv = (struct xmc4_dev_s *)dev->priv; + + /* Return true if the transmit data register is "empty." NOTE: If + * FIFOS are enabled, this does not mean that the FIFO is empty, + * rather, it means that the number of bytes in the TX FIFO is + * below the watermark setting. There may actually be space for + * additional TX data. + */ + + return (up_serialin(priv, XMC4_UART_S1_OFFSET) & UART_S1_TDRE) != 0; +} + +/**************************************************************************** + * Name: xmc4_txempty + * + * Description: + * Return true if the tranmsit data register is empty + * + ****************************************************************************/ + +static bool xmc4_txempty(struct uart_dev_s *dev) +{ + struct xmc4_dev_s *priv = (struct xmc4_dev_s *)dev->priv; + + /* Return true if the transmit buffer/fifo is "empty." */ + + return (up_serialin(priv, XMC4_UART_SFIFO_OFFSET) & UART_SFIFO_TXEMPT) != 0; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: xmc4_earlyserialinit + * + * Description: + * Performs the low level UART initialization early in debug so that the + * serial console will be available during bootup. This must be called + * before up_serialinit. NOTE: This function depends on GPIO pin + * configuration performed in up_consoleinit() and main clock iniialization + * performed in up_clkinitialize(). + * + ****************************************************************************/ + +#if defined(USE_EARLYSERIALINIT) +void xmc4_earlyserialinit(void) +{ + /* Disable interrupts from all UARTS. The console is enabled in + * pic32mx_consoleinit() + */ + + up_restoreuartint(TTYS0_DEV.priv, 0); +#ifdef TTYS1_DEV + up_restoreuartint(TTYS1_DEV.priv, 0); +#endif +#ifdef TTYS2_DEV + up_restoreuartint(TTYS2_DEV.priv, 0); +#endif +#ifdef TTYS3_DEV + up_restoreuartint(TTYS3_DEV.priv, 0); +#endif +#ifdef TTYS4_DEV + up_restoreuartint(TTYS4_DEV.priv, 0); +#endif +#ifdef TTYS5_DEV + up_restoreuartint(TTYS5_DEV.priv, 0); +#endif + + /* Configuration whichever one is the console */ + +#ifdef HAVE_UART_CONSOLE + CONSOLE_DEV.isconsole = true; + xmc4_setup(&CONSOLE_DEV); +#endif +} +#endif + +/**************************************************************************** + * Name: up_serialinit + * + * Description: + * Register serial console and serial ports. This assumes + * that up_earlyserialinit was called previously. + * + * Input Parameters: + * None + * + * Returns Value: + * None + * + ****************************************************************************/ + +void up_serialinit(void) +{ + char devname[] = "/dev/ttySx"; + + /* Register the console */ + +#ifdef HAVE_UART_CONSOLE + (void)uart_register("/dev/console", &CONSOLE_DEV); +#endif + + /* Register all UARTs */ + + (void)uart_register("/dev/ttyS0", &TTYS0_DEV); +#ifdef TTYS1_DEV + devname[(sizeof(devname)/sizeof(devname[0]))-2] = '0' + first++; + (void)uart_register("/dev/ttyS1", &TTYS1_DEV); +#endif +#ifdef TTYS2_DEV + devname[(sizeof(devname)/sizeof(devname[0]))-2] = '0' + first++; + (void)uart_register("/dev/ttyS2", &TTYS2_DEV); +#endif +#ifdef TTYS3_DEV + devname[(sizeof(devname)/sizeof(devname[0]))-2] = '0' + first++; + (void)uart_register("/dev/ttyS3", &TTYS3_DEV); +#endif +#ifdef TTYS4_DEV + devname[(sizeof(devname)/sizeof(devname[0]))-2] = '0' + first++; + (void)uart_register("/dev/ttyS4", &TTYS4_DEV); +#endif +#ifdef TTYS5_DEV + devname[(sizeof(devname)/sizeof(devname[0]))-2] = '0' + first++; + (void)uart_register("/dev/ttyS5", &TTYS5_DEV); +#endif + return first; +} + +/**************************************************************************** + * Name: up_putc + * + * Description: + * Provide priority, low-level access to support OS debug writes + * + ****************************************************************************/ + +#ifdef HAVE_UART_PUTC +int up_putc(int ch) +{ +#ifdef HAVE_UART_CONSOLE + struct xmc4_dev_s *priv = (struct xmc4_dev_s *)CONSOLE_DEV.priv; + uint8_t ie; + + up_disableuartint(priv, &ie); + + /* Check for LF */ + + if (ch == '\n') + { + /* Add CR */ + + up_lowputc('\r'); + } + + up_lowputc(ch); + up_restoreuartint(priv, ie); +#endif + return ch; +} +#endif + +#else /* USE_SERIALDRIVER */ + +/**************************************************************************** + * Name: up_putc + * + * Description: + * Provide priority, low-level access to support OS debug writes + * + ****************************************************************************/ + +#ifdef HAVE_UART_PUTC +int up_putc(int ch) +{ +#ifdef HAVE_UART_CONSOLE + /* Check for LF */ + + if (ch == '\n') + { + /* Add CR */ + + up_lowputc('\r'); + } + + up_lowputc(ch); +#endif + return ch; +} +#endif + +#endif /* HAVE_UART_DEVICE && USE_SERIALDRIVER */ + diff --git a/arch/arm/src/xmc4/xmc4_spi.h b/arch/arm/src/xmc4/xmc4_spi.h new file mode 100644 index 00000000000..0ac514c5cee --- /dev/null +++ b/arch/arm/src/xmc4/xmc4_spi.h @@ -0,0 +1,165 @@ +/**************************************************************************** + * arch/arm/src/xmc4/xmc4_spi.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_XMC4_XMC4_SPI_H +#define __ARCH_ARM_SRC_XMC4_XMC4_SPI_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "chip/xmc4_spi.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +struct spi_dev_s; +enum spi_dev_e; + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/************************************************************************************ + * Name: xmc4_spibus_initialize + * + * Description: + * Initialize the selected SPI bus + * + * Input Parameter: + * bus number (for hardware that has mutiple SPI interfaces) + * + * Returned Value: + * Valid SPI device structure reference on succcess; a NULL on failure + * + ************************************************************************************/ + +FAR struct spi_dev_s *xmc4_spibus_initialize(int bus); + +/************************************************************************************ + * Name: xmc4_spi[n]select, xmc4_spi[n]status, and xmc4_spi[n]cmddata + * + * Description: + * These external functions must be provided by board-specific logic. They are + * implementations of the select, status, and cmddata methods of the SPI interface + * defined by struct spi_ops_s (see include/nuttx/spi/spi.h). All other methods + * including xmc4_spibus_initialize()) are provided by common Kinetis logic. To use + * this common SPI logic on your board: + * + * 1. Provide logic in xmc4_board_initialize() to configure SPI chip select + * pins. + * 2. Provide xmc4_spi[n]select() and xmc4_spi[n]status() functions + * in your board-specific logic. These functions will perform chip selection + * and status operations using GPIOs in the way your board is configured. + * 2. If CONFIG_SPI_CMDDATA is defined in the NuttX configuration, provide + * xmc4_spi[n]cmddata() functions in your board-specific logic. These + * functions will perform cmd/data selection operations using GPIOs in the way + * your board is configured. + * 3. Add a call to xmc4_spibus_initialize() in your low level application + * initialization logic + * 4. The handle returned by xmc4_spibus_initialize() may then be used to bind the + * SPI driver to higher level logic (e.g., calling + * mmcsd_spislotinitialize(), for example, will bind the SPI driver to + * the SPI MMC/SD driver). + * + ************************************************************************************/ + +#ifdef CONFIG_XMC4_SPI0 +void xmc4_spi0select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected); +uint8_t xmc4_spi0status(FAR struct spi_dev_s *dev, enum spi_dev_e devid); +#ifdef CONFIG_SPI_CMDDATA +int xmc4_spi0cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd); +#endif +#endif +#ifdef CONFIG_XMC4_SPI1 +void xmc4_spi1select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected); +uint8_t xmc4_spi1status(FAR struct spi_dev_s *dev, enum spi_dev_e devid); +#ifdef CONFIG_SPI_CMDDATA +int xmc4_spi1cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd); +#endif +#endif +#ifdef CONFIG_XMC4_SPI2 +void xmc4_spi2select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected); +uint8_t xmc4_spi2status(FAR struct spi_dev_s *dev, enum spi_dev_e devid); +#ifdef CONFIG_SPI_CMDDATA +int xmc4_spi2cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd); +#endif +#endif + +/**************************************************************************** + * Name: ssp_flush + * + * Description: + * Flush and discard any words left in the RX fifo. This can be called + * from spi[n]select after a device is deselected (if you worry about such + * things). + * + * Input Parameters: + * dev - Device-specific state data + * + * Returned Value: + * None + * + ****************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +} +#endif +#if defined(CONFIG_XMC4_SPI0) || defined(CONFIG_XMC4_SPI1) || defined(CONFIG_XMC4_SPI2) +struct spi_dev_s; +void spi_flush(FAR struct spi_dev_s *dev); +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_ARM_SRC_XMC4_XMC4_SPI_H */ diff --git a/arch/arm/src/xmc4/xmc4_start.c b/arch/arm/src/xmc4/xmc4_start.c new file mode 100644 index 00000000000..e71722e4be5 --- /dev/null +++ b/arch/arm/src/xmc4/xmc4_start.c @@ -0,0 +1,355 @@ +/**************************************************************************** + * arch/arm/src/xmc4/xmc4_start.c + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "up_arch.h" +#include "up_internal.h" + +#include "xmc4_userspace.h" + +#ifdef CONFIG_ARCH_FPU +# include "nvic.h" +#endif + +/**************************************************************************** + * Private Function prototypes + ****************************************************************************/ + +#ifdef CONFIG_ARCH_FPU +static inline void xmc4_fpu_config(void); +#endif +#ifdef CONFIG_STACK_COLORATION +static void go_os_start(void *pv, unsigned int nbytes) + __attribute__ ((naked, no_instrument_function, noreturn)); +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ +/* Memory Map ***************************************************************/ +/* + * 0x0000:0000 - Beginning of the internal FLASH. Address of vectors. + * Mapped as boot memory address 0x0000:0000 at reset. + * 0x07ff:ffff - End of flash region (assuming the max of 2MiB of FLASH). + * 0x1fff:0000 - Start of internal SRAM and start of .data (_sdata) + * - End of .data (_edata) and start of .bss (_sbss) + * - End of .bss (_ebss) and bottom of idle stack + * - _ebss + CONFIG_IDLETHREAD_STACKSIZE = end of idle stack, + * start of heap. NOTE that the ARM uses a decrement before + * store stack so that the correct initial value is the end of + * the stack + 4; + * 0x2002:ffff - End of internal SRAM and end of heap (a + */ + +#define IDLE_STACK ((uintptr_t)&_ebss+CONFIG_IDLETHREAD_STACKSIZE-4) +#define HEAP_BASE ((uintptr_t)&_ebss+CONFIG_IDLETHREAD_STACKSIZE) + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* g_idle_topstack: _sbss is the start of the BSS region as defined by the + * linker script. _ebss lies at the end of the BSS region. The idle task + * stack starts at the end of BSS and is of size CONFIG_IDLETHREAD_STACKSIZE. + * The IDLE thread is the thread that the system boots on and, eventually, + * becomes the IDLE, do nothing task that runs only when there is nothing + * else to run. The heap continues from there until the end of memory. + * g_idle_topstack is a read-only variable the provides this computed + * address. + */ +#if defined(CONFIG_ARMV7M_CMNVECTOR) +const uintptr_t g_idle_topstack = HEAP_BASE; +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + + +#ifdef CONFIG_ARMV7M_STACKCHECK +/* we need to get r10 set before we can allow instrumentation calls */ + +void __start(void) __attribute__ ((no_instrument_function)); +#endif + +/**************************************************************************** + * Name: xmc4_fpu_config + * + * Description: + * Configure the FPU. Relative bit settings: + * + * CPACR: Enables access to CP10 and CP11 + * CONTROL.FPCA: Determines whether the FP extension is active in the + * current context: + * FPCCR.ASPEN: Enables automatic FP state preservation, then the + * processor sets this bit to 1 on successful completion of any FP + * instruction. + * FPCCR.LSPEN: Enables lazy context save of FP state. When this is + * done, the processor reserves space on the stack for the FP state, + * but does not save that state information to the stack. + * + * Software must not change the value of the ASPEN bit or LSPEN bit while either: + * - the CPACR permits access to CP10 and CP11, that give access to the FP + * extension, or + * - the CONTROL.FPCA bit is set to 1 + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_FPU +#if defined(CONFIG_ARMV7M_CMNVECTOR) && !defined(CONFIG_ARMV7M_LAZYFPU) + +static inline void xmc4_fpu_config(void) +{ + uint32_t regval; + + /* Set CONTROL.FPCA so that we always get the extended context frame + * with the volatile FP registers stacked above the basic context. + */ + + regval = getcontrol(); + regval |= (1 << 2); + setcontrol(regval); + + /* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend + * with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we + * are going to turn on CONTROL.FPCA for all contexts. + */ + + regval = getreg32(NVIC_FPCCR); + regval &= ~((1 << 31) | (1 << 30)); + putreg32(regval, NVIC_FPCCR); + + /* Enable full access to CP10 and CP11 */ + + regval = getreg32(NVIC_CPACR); + regval |= ((3 << (2*10)) | (3 << (2*11))); + putreg32(regval, NVIC_CPACR); +} + +#else + +static inline void xmc4_fpu_config(void) +{ + uint32_t regval; + + /* Clear CONTROL.FPCA so that we do not get the extended context frame + * with the volatile FP registers stacked in the saved context. + */ + + regval = getcontrol(); + regval &= ~(1 << 2); + setcontrol(regval); + + /* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend + * with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we + * are going to keep CONTROL.FPCA off for all contexts. + */ + + regval = getreg32(NVIC_FPCCR); + regval &= ~((1 << 31) | (1 << 30)); + putreg32(regval, NVIC_FPCCR); + + /* Enable full access to CP10 and CP11 */ + + regval = getreg32(NVIC_CPACR); + regval |= ((3 << (2*10)) | (3 << (2*11))); + putreg32(regval, NVIC_CPACR); +} + +#endif + +#else +# define xmc4_fpu_config() +#endif + +/**************************************************************************** + * Name: go_os_start + * + * Description: + * Set the IDLE stack to the + * + ****************************************************************************/ + +#ifdef CONFIG_STACK_COLORATION +static void go_os_start(void *pv, unsigned int nbytes) +{ + /* Set the IDLE stack to the stack coloration value then jump to + * os_start(). We take extreme care here because were currently + * executing on this stack. + * + * We want to avoid sneak stack access generated by the compiler. + */ + + __asm__ __volatile__ + ( + "\tmovs r1, r1, lsr #2\n" /* R1 = nwords = nbytes >> 2 */ + "\tbeq 2f\n" /* (should not happen) */ + + "\tbic r0, r0, #3\n" /* R0 = Aligned stackptr */ + "\tmovw r2, #0xbeef\n" /* R2 = STACK_COLOR = 0xdeadbeef */ + "\tmovt r2, #0xdead\n" + + "1:\n" /* Top of the loop */ + "\tsub r1, r1, #1\n" /* R1 nwords-- */ + "\tcmp r1, #0\n" /* Check (nwords == 0) */ + "\tstr r2, [r0], #4\n" /* Save stack color word, increment stackptr */ + "\tbne 1b\n" /* Bottom of the loop */ + + "2:\n" + "\tmov r14, #0\n" /* LR = return address (none) */ + "\tb os_start\n" /* Branch to os_start */ + ); +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: _start + * + * Description: + * This is the reset entry point. + * + ****************************************************************************/ + +void __start(void) +{ + const uint32_t *src; + uint32_t *dest; + +#ifdef CONFIG_ARMV7M_STACKCHECK + /* Set the stack limit before we attempt to call any functions */ + + __asm__ volatile ("sub r10, sp, %0" : : "r" (CONFIG_IDLETHREAD_STACKSIZE - 64) : ); +#endif + + /* Disable the watchdog timer */ + + kinetis_wddisable(); + + /* Clear .bss. We'll do this inline (vs. calling memset) just to be + * certain that there are no issues with the state of global variables. + */ + + for (dest = &_sbss; dest < &_ebss; ) + { + *dest++ = 0; + } + + /* Move the initialized data section from his temporary holding spot in + * FLASH into the correct place in SRAM. The correct place in SRAM is + * give by _sdata and _edata. The temporary location is in FLASH at the + * end of all of the other read-only data (.text, .rodata) at _eronly. + */ + + for (src = &_eronly, dest = &_sdata; dest < &_edata; ) + { + *dest++ = *src++; + } + + /* Copy any necessary code sections from FLASH to RAM. The correct + * destination in SRAM is given by _sramfuncs and _eramfuncs. The + * temporary location is in flash after the data initialization code + * at _framfuncs + */ + +#ifdef CONFIG_ARCH_RAMFUNCS + for (src = &_framfuncs, dest = &_sramfuncs; dest < &_eramfuncs; ) + { + *dest++ = *src++; + } +#endif + + /* Perform clock and Kinetis module initialization (This depends on + * RAM functions having been copied to RAM). + */ + + xmc4_clock_config(); + + /* Configure the uart and perform early serial initialization so that we + * can get debug output as soon as possible (This depends on clock + * configuration). + */ + + xmc4_fpu_config(); + xmc4_lowsetup(); +#ifdef USE_EARLYSERIALINIT + xmc4_earlyserialinit(); +#endif + + /* For the case of the separate user-/kernel-space build, perform whatever + * platform specific initialization of the user memory is required. + * Normally this just means initializing the user space .data and .bss + * segments. + */ + +#ifdef CONFIG_BUILD_PROTECTED + xmc4_userspace(); +#endif + + /* Initialize other on-board resources */ + + xmc4_board_initialize(); + + /* Then start NuttX */ + + os_start(); + + /* Shouldn't get here */ + + for (; ; ); +} diff --git a/arch/arm/src/xmc4/xmc4_timerisr.c b/arch/arm/src/xmc4/xmc4_timerisr.c new file mode 100644 index 00000000000..ba9e98596c8 --- /dev/null +++ b/arch/arm/src/xmc4/xmc4_timerisr.c @@ -0,0 +1,152 @@ +/**************************************************************************** + * arch/arm/src/xmc4/xmc4_timerisr.c + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "nvic.h" +#include "clock/clock.h" +#include "up_internal.h" +#include "up_arch.h" + +#include "chip.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* The desired timer interrupt frequency is provided by the definition + * CLK_TCK (see include/time.h). CLK_TCK defines the desired number of + * system clock ticks per second. That value is a user configurable setting + * that defaults to 100 (100 ticks per second = 10 MS interval). + * + * The Clock Source: The System Tick Timer's clock source is always the core + * clock + */ + +#define SYSTICK_RELOAD ((BOARD_CORECLK_FREQ / CLK_TCK) - 1) + +/* The size of the reload field is 24 bits. Verify that the reload value + * will fit in the reload register. + */ + +#if SYSTICK_RELOAD > 0x00ffffff +# error SYSTICK_RELOAD exceeds the range of the RELOAD register +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Function: xmc4_timerisr + * + * Description: + * The timer ISR will perform a variety of services for various portions + * of the systems. + * + ****************************************************************************/ + +static int xmc4_timerisr(int irq, uint32_t *regs, FAR void *arg) +{ + /* Process timer interrupt */ + + sched_process_timer(); + return 0; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Function: arm_timer_initialize + * + * Description: + * This function is called during start-up to initialize + * the timer interrupt. + * + ****************************************************************************/ + +void arm_timer_initialize(void) +{ + uint32_t regval; + + /* Set the SysTick interrupt to the default priority */ + + regval = getreg32(NVIC_SYSH12_15_PRIORITY); + regval &= ~NVIC_SYSH_PRIORITY_PR15_MASK; + regval |= (NVIC_SYSH_PRIORITY_DEFAULT << NVIC_SYSH_PRIORITY_PR15_SHIFT); + putreg32(regval, NVIC_SYSH12_15_PRIORITY); + + /* Note that is should not be neccesary to set the SYSTICK clock source: + * "The CLKSOURCE bit in SysTick Control and Status register is always set + * to select the core clock." + */ + +#if 0 + regval = getreg32(NVIC_SYSTICK_CTRL); + regval |= NVIC_SYSTICK_CTRL_CLKSOURCE; + putreg32(regval, NVIC_SYSTICK_CTRL); +#endif + + /* Configure SysTick to interrupt at the requested rate */ + + putreg32(SYSTICK_RELOAD, NVIC_SYSTICK_RELOAD); + + /* Attach the timer interrupt vector */ + + (void)irq_attach(XMC4_IRQ_SYSTICK, (xcpt_t)xmc4_timerisr, NULL); + + /* Enable SysTick interrupts */ + + putreg32((NVIC_SYSTICK_CTRL_CLKSOURCE | NVIC_SYSTICK_CTRL_TICKINT | + NVIC_SYSTICK_CTRL_ENABLE), + NVIC_SYSTICK_CTRL); + + /* And enable the timer interrupt */ + + up_enable_irq(XMC4_IRQ_SYSTICK); +} diff --git a/arch/arm/src/xmc4/xmc4_userspace.c b/arch/arm/src/xmc4/xmc4_userspace.c new file mode 100644 index 00000000000..02dc2d2303a --- /dev/null +++ b/arch/arm/src/xmc4/xmc4_userspace.c @@ -0,0 +1,107 @@ +/**************************************************************************** + * arch/arm/src/xmc4/xmc4_userspace.c + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include + +#include "xmc4_mpuinit.h" +#include "xmc4_userspace.h" + +#ifdef CONFIG_BUILD_PROTECTED + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: xmc4_userspace + * + * Description: + * For the case of the separate user-/kernel-space build, perform whatever + * platform specific initialization of the user memory is required. + * Normally this just means initializing the user space .data and .bss + * segments. + * + ****************************************************************************/ + +void xmc4_userspace(void) +{ + uint8_t *src; + uint8_t *dest; + uint8_t *end; + + /* Clear all of user-space .bss */ + + DEBUGASSERT(USERSPACE->us_bssstart != 0 && USERSPACE->us_bssend != 0 && + USERSPACE->us_bssstart <= USERSPACE->us_bssend); + + dest = (uint8_t *)USERSPACE->us_bssstart; + end = (uint8_t *)USERSPACE->us_bssend; + + while (dest != end) + { + *dest++ = 0; + } + + /* Initialize all of user-space .data */ + + DEBUGASSERT(USERSPACE->us_datasource != 0 && + USERSPACE->us_datastart != 0 && USERSPACE->us_dataend != 0 && + USERSPACE->us_datastart <= USERSPACE->us_dataend); + + src = (uint8_t *)USERSPACE->us_datasource; + dest = (uint8_t *)USERSPACE->us_datastart; + end = (uint8_t *)USERSPACE->us_dataend; + + while (dest != end) + { + *dest++ = *src++; + } + + /* Configure the MPU to permit user-space access to its FLASH and RAM */ + + xmc4_mpuinitialize(); +} + +#endif /* CONFIG_BUILD_PROTECTED */ + diff --git a/arch/arm/src/xmc4/xmc4_userspace.h b/arch/arm/src/xmc4/xmc4_userspace.h new file mode 100644 index 00000000000..661982c8f90 --- /dev/null +++ b/arch/arm/src/xmc4/xmc4_userspace.h @@ -0,0 +1,64 @@ +/************************************************************************************ + * arch/arm/src/xmc4/xmc4_userspace.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_XMC4_XMC4_USERSPACE_H +#define __ARCH_ARM_SRC_XMC4_XMC4_USERSPACE_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/**************************************************************************** + * Name: xmc4_userspace + * + * Description: + * For the case of the separate user-/kernel-space build, perform whatever + * platform specific initialization of the user memory is required. + * Normally this just means initializing the user space .data and .bss + * segments. + * + ****************************************************************************/ + +#ifdef CONFIG_BUILD_PROTECTED +void xmc4_userspace(void); +#endif + +#endif /* __ARCH_ARM_SRC_XMC4_XMC4_USERSPACE_H */ From 2430049e3b5496c91f70ccfaa306c9b0f5878abe Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Tue, 14 Mar 2017 13:04:09 -0600 Subject: [PATCH 02/21] arch/arm/include/xmc4: More support for Infineon XMC4xxx arch. Still incomplete. --- arch/arm/include/xmc4/chip.h | 130 ++++++++++++++++ arch/arm/include/xmc4/irq.h | 120 +++++++++++++++ arch/arm/include/xmc4/xmc4500_irq.h | 225 ++++++++++++++++++++++++++++ 3 files changed, 475 insertions(+) create mode 100644 arch/arm/include/xmc4/chip.h create mode 100644 arch/arm/include/xmc4/irq.h create mode 100644 arch/arm/include/xmc4/xmc4500_irq.h diff --git a/arch/arm/include/xmc4/chip.h b/arch/arm/include/xmc4/chip.h new file mode 100644 index 00000000000..7ea5157a736 --- /dev/null +++ b/arch/arm/include/xmc4/chip.h @@ -0,0 +1,130 @@ +/************************************************************************************ + * arch/arm/include/xmc4/chip.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_INCLUDE_XM4_CHIP_H +#define __ARCH_ARM_INCLUDE_XM4_CHIP_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Get customizations for each supported chip */ + +#if defined(CONFIG_ARCH_XMC4500) +# define XM4_NUSIC 3 /* Three USIC modules: USCI0-2 */ + +#else +# error "Unsupported XMC4000 chip" +#endif + +/* NVIC priority levels *************************************************************/ +/* Each priority field holds a priority value, 0-15. The lower the value, the greater + * the priority of the corresponding interrupt. The XMC4500 implements only + * bits[7:2] of this field, bits[1:0] read as zero and ignore writes. + */ + +#define NVIC_SYSH_PRIORITY_MIN 0xfc /* All bits[7:2] set is minimum priority */ +#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */ +#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */ +#define NVIC_SYSH_PRIORITY_STEP 0x04 /* Steps between supported priority values */ + +/* If CONFIG_ARMV7M_USEBASEPRI is selected, then interrupts will be disabled + * by setting the BASEPRI register to NVIC_SYSH_DISABLE_PRIORITY so that most + * interrupts will not have execution priority. SVCall must have execution + * priority in all cases. + * + * In the normal cases, interrupts are not nest-able and all interrupts run + * at an execution priority between NVIC_SYSH_PRIORITY_MIN and + * NVIC_SYSH_PRIORITY_MAX (with NVIC_SYSH_PRIORITY_MAX reserved for SVCall). + * + * If, in addition, CONFIG_ARCH_HIPRI_INTERRUPT is defined, then special + * high priority interrupts are supported. These are not "nested" in the + * normal sense of the word. These high priority interrupts can interrupt + * normal processing but execute outside of OS (although they can "get back + * into the game" via a PendSV interrupt). + * + * In the normal course of things, interrupts must occasionally be disabled + * using the up_irq_save() inline function to prevent contention in use of + * resources that may be shared between interrupt level and non-interrupt + * level logic. Now the question arises, if CONFIG_ARCH_HIPRI_INTERRUPT, + * do we disable all interrupts (except SVCall), or do we only disable the + * "normal" interrupts. Since the high priority interrupts cannot interact + * with the OS, you may want to permit the high priority interrupts even if + * interrupts are disabled. The setting CONFIG_ARCH_INT_DISABLEALL can be + * used to select either behavior: + * + * ----------------------------+--------------+---------------------------- + * CONFIG_ARCH_HIPRI_INTERRUPT | NO | YES + * ----------------------------+--------------+--------------+------------- + * CONFIG_ARCH_INT_DISABLEALL | N/A | YES | NO + * ----------------------------+--------------+--------------+------------- + * | | | SVCall + * | SVCall | SVCall | HIGH + * Disable here and below --------> MAXNORMAL ---> HIGH --------> MAXNORMAL + * | | MAXNORMAL | + * ----------------------------+--------------+--------------+------------- + */ + +#if defined(CONFIG_ARCH_HIPRI_INTERRUPT) && defined(CONFIG_ARCH_INT_DISABLEALL) +# define NVIC_SYSH_MAXNORMAL_PRIORITY (NVIC_SYSH_PRIORITY_MAX + 2*NVIC_SYSH_PRIORITY_STEP) +# define NVIC_SYSH_HIGH_PRIORITY (NVIC_SYSH_PRIORITY_MAX + NVIC_SYSH_PRIORITY_STEP) +# define NVIC_SYSH_DISABLE_PRIORITY NVIC_SYSH_HIGH_PRIORITY +# define NVIC_SYSH_SVCALL_PRIORITY NVIC_SYSH_PRIORITY_MAX +#else +# define NVIC_SYSH_MAXNORMAL_PRIORITY (NVIC_SYSH_PRIORITY_MAX + NVIC_SYSH_PRIORITY_STEP) +# define NVIC_SYSH_HIGH_PRIORITY NVIC_SYSH_PRIORITY_MAX +# define NVIC_SYSH_DISABLE_PRIORITY NVIC_SYSH_MAXNORMAL_PRIORITY +# define NVIC_SYSH_SVCALL_PRIORITY NVIC_SYSH_PRIORITY_MAX +#endif + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_INCLUDE_XM4_CHIP_H */ diff --git a/arch/arm/include/xmc4/irq.h b/arch/arm/include/xmc4/irq.h new file mode 100644 index 00000000000..65300dcee3b --- /dev/null +++ b/arch/arm/include/xmc4/irq.h @@ -0,0 +1,120 @@ +/**************************************************************************** + * arch/arm/include/xmc4/irq.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* This file should never be included directed but, rather, only indirectly + * through nuttx/irq.h + */ + +#ifndef __ARCH_ARM_INCLUDE_XM4_IRQ_H +#define __ARCH_ARM_INCLUDE_XM4_IRQ_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include +#include + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* IRQ numbers. The IRQ number corresponds vector number and hence map directly to + * bits in the NVIC. This does, however, waste several words of memory in the IRQ + * to handle mapping tables. + */ + +/* Processor Exceptions (vectors 0-15) */ + +#define XM4_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */ + /* Vector 0: Reset stack pointer value */ + /* Vector 1: Reset (not handler as an IRQ) */ +#define XM4_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */ +#define XM4_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */ +#define XM4_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */ +#define XM4_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */ +#define XM4_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */ + /* Vectors 7-10: Reserved */ +#define XM4_IRQ_SVCALL (11) /* Vector 11: SVC call */ +#define XM4_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */ + /* Vector 13: Reserved */ +#define XM4_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */ +#define XM4_IRQ_SYSTICK (15) /* Vector 15: System tick */ + +/* External interrupts (vectors >= 16). These definitions are chip-specific */ + +#define XM4_IRQ_FIRST (16) /* Vector number of the first external interrupt */ + +#if defined(CONFIG_ARCH_XMC4500) +# include +#else + /* The interrupt vectors for other parts are defined in other documents and may or + * may not be the same as above (the family members are all very similar) This + * error just means that you have to look at the document and determine for yourself + * if the vectors are the same. + */ + +# error "No IRQ numbers for this XMC4xxx part" +#endif + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +#ifndef __ASSEMBLY__ +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#undef EXTERN +#ifdef __cplusplus +} +#endif +#endif + +#endif /* __ARCH_ARM_INCLUDE_XM4_IRQ_H */ + diff --git a/arch/arm/include/xmc4/xmc4500_irq.h b/arch/arm/include/xmc4/xmc4500_irq.h new file mode 100644 index 00000000000..1005adeb495 --- /dev/null +++ b/arch/arm/include/xmc4/xmc4500_irq.h @@ -0,0 +1,225 @@ +/***************************************************************************** + * arch/arm/include/xmc4/xmc4500_.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* This file should never be included directed but, rather, only indirectly + * through nuttx/irq.h + */ + +#ifndef xmc4__ARCH_ARM_INCLUDE_XM4_XM4500_IRQ_H +#define xmc4__ARCH_ARM_INCLUDE_XM4_XM4500_IRQ_H + +/***************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/***************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* IRQ numbers. The IRQ number corresponds vector number and hence map + * directly to bits in the NVIC. This does, however, waste several words of + * memory in the IRQ to handle mapping tables. + * + * Processor Exceptions (vectors 0-15). These common definitions can be found + * in the file nuttx/arch/arm/include/kinets/irq.h which includes this file + * + * External interrupts (vectors >= 16) + * + * Acronyms: + * ADC - Analog to Digital Converter + * CCU - Capture Compare Unit + * DAC - Digital to Analog Converter + * DSD - Delta Sigmoid Demodulator + * ERU - External Request Unit + * FCE - Flexible CRC Engine + * GPDMA - General Purpose DMA + * LEDTS - LED and Touch Sense Control Unit + * PMU - Program Management Unit + * POSIF - Position Interface + * SDMMC - Multi Media Card Interface + * USB - Universal Serial Bus + * USCI - Universal Serial Interface + */ + +#define XM4_IRQ_SCU (XM4_IRQ_FIRST+0) /* 0: System Control */ +#define XM4_IRQ_ERU0_SR0 (XM4_IRQ_FIRST+1) /* 1: ERU0, SR0 */ +#define XM4_IRQ_ERU0_SR1 (XM4_IRQ_FIRST+2) /* 2: ERU0, SR1 */ +#define XM4_IRQ_ERU0_SR2 (XM4_IRQ_FIRST+3) /* 3: ERU0, SR2 */ +#define XM4_IRQ_ERU0_SR3 (XM4_IRQ_FIRST+4) /* 4: ERU0, SR3 */ +#define XM4_IRQ_ERU1_SR0 (XM4_IRQ_FIRST+5) /* 5: ERU1, SR0 */ +#define XM4_IRQ_ERU1_SR1 (XM4_IRQ_FIRST+6) /* 6: ERU1, SR1 */ +#define XM4_IRQ_ERU1_SR2 (XM4_IRQ_FIRST+7) /* 7: ERU1, SR2 */ +#define XM4_IRQ_ERU1_SR3 (XM4_IRQ_FIRST+8) /* 8: ERU1, SR3 */ +#define XM4_IRQ_RESVD009 (XM4_IRQ_FIRST+9) /* 9: Reserved */ +#define XM4_IRQ_RESVD010 (XM4_IRQ_FIRST+10) /* 10: Reserved */ +#define XM4_IRQ_RESVD011 (XM4_IRQ_FIRST+11) /* 11: Reserved */ +#define XM4_IRQ_PMU1_SR0 (XM4_IRQ_FIRST+12) /* 12: PMU, SR0 */ +#define XM4_IRQ_RESVD011 (XM4_IRQ_FIRST+13) /* 13: Reserved */ +#define XM4_IRQ_VADC_COSR0 (XM4_IRQ_FIRST+14) /* 14: ADC Common Block 0 */ +#define XM4_IRQ_VADC_COSR1 (XM4_IRQ_FIRST+15) /* 15: ADC Common Block 1 */ +#define XM4_IRQ_VADC_COSR2 (XM4_IRQ_FIRST+16) /* 16: ADC Common Block 2 */ +#define XM4_IRQ_VADC_COSR3 (XM4_IRQ_FIRST+17) /* 17: ADC Common Block 3 */ +#define XM4_IRQ_VADC_GOSR0 (XM4_IRQ_FIRST+18) /* 18: ADC Group 0, SR0 */ +#define XM4_IRQ_VADC_GOSR1 (XM4_IRQ_FIRST+19) /* 19: ADC Group 0, SR1 */ +#define XM4_IRQ_VADC_GOSR2 (XM4_IRQ_FIRST+20) /* 20: ADC Group 0, SR2 */ +#define XM4_IRQ_VADC_GOSR3 (XM4_IRQ_FIRST+21) /* 21: ADC Group 0, SR3 */ +#define XM4_IRQ_VADC_G1SR0 (XM4_IRQ_FIRST+22) /* 22: ADC Group 1, SR0 */ +#define XM4_IRQ_VADC_G1SR1 (XM4_IRQ_FIRST+23) /* 23: ADC Group 1, SR1 */ +#define XM4_IRQ_VADC_G1SR2 (XM4_IRQ_FIRST+24) /* 24: ADC Group 1, SR2 */ +#define XM4_IRQ_VADC_G1SR3 (XM4_IRQ_FIRST+25) /* 25: ADC Group 1, SR3 */ +#define XM4_IRQ_VADC_G2SR0 (XM4_IRQ_FIRST+26) /* 26: ADC Group 2, SR0 */ +#define XM4_IRQ_VADC_G2SR1 (XM4_IRQ_FIRST+27) /* 27: ADC Group 2, SR1 */ +#define XM4_IRQ_VADC_G2SR2 (XM4_IRQ_FIRST+28) /* 28: ADC Group 2, SR2 */ +#define XM4_IRQ_VADC_G2SR3 (XM4_IRQ_FIRST+29) /* 29: ADC Group 2, SR3 */ +#define XM4_IRQ_VADC_G3SR0 (XM4_IRQ_FIRST+30) /* 30: ADC Group 3, SR0 */ +#define XM4_IRQ_VADC_G3SR1 (XM4_IRQ_FIRST+31) /* 31: ADC Group 3, SR1 */ +#define XM4_IRQ_VADC_G3SR2 (XM4_IRQ_FIRST+32) /* 32: ADC Group 3, SR2 */ +#define XM4_IRQ_VADC_G3SR3 (XM4_IRQ_FIRST+33) /* 33: ADC Group 3, SR3 */ +#define XM4_IRQ_DSD_SRM0 (XM4_IRQ_FIRST+34) /* 34: DSD Main, SRM0 */ +#define XM4_IRQ_DSD_SRM1 (XM4_IRQ_FIRST+35) /* 35: DSD Main, SRM1 */ +#define XM4_IRQ_DSD_SRM2 (XM4_IRQ_FIRST+36) /* 36: DSD Main, SRM2 */ +#define XM4_IRQ_DSD_SRM3 (XM4_IRQ_FIRST+37) /* 37: DSD Main, SRM3 */ +#define XM4_IRQ_DSD_SRA0 (XM4_IRQ_FIRST+38) /* 38: DSD Auxiliary, SRA0 */ +#define XM4_IRQ_DSD_SRA1 (XM4_IRQ_FIRST+39) /* 39: DSD Auxiliary, SRA1 */ +#define XM4_IRQ_DSD_SRA2 (XM4_IRQ_FIRST+40) /* 40: DSD Auxiliary, SRA2 */ +#define XM4_IRQ_DSD_SRA3 (XM4_IRQ_FIRST+41) /* 41: DSD Auxiliary, SRA3 */ +#define XM4_IRQ_DAC_SR0 (XM4_IRQ_FIRST+42) /* 42: DAC, SR0 */ +#define XM4_IRQ_DAC_SR1 (XM4_IRQ_FIRST+43) /* 43: DAC, SR1 */ +#define XM4_IRQ_CCU40_SR0 (XM4_IRQ_FIRST+44) /* 44: CCU4 Module 0, SR0 */ +#define XM4_IRQ_CCU40_SR1 (XM4_IRQ_FIRST+45) /* 45: CCU4 Module 0, SR1 */ +#define XM4_IRQ_CCU40_SR2 (XM4_IRQ_FIRST+46) /* 46: CCU4 Module 0, SR2 */ +#define XM4_IRQ_CCU40_SR3 (XM4_IRQ_FIRST+47) /* 47: CCU4 Module 0, SR3 */ +#define XM4_IRQ_CCU41_SR0 (XM4_IRQ_FIRST+48) /* 48: CCU4 Module 1, SR0 */ +#define XM4_IRQ_CCU41_SR1 (XM4_IRQ_FIRST+49) /* 49: CCU4 Module 1, SR1 */ +#define XM4_IRQ_CCU41_SR2 (XM4_IRQ_FIRST+50) /* 50: CCU4 Module 1, SR2 */ +#define XM4_IRQ_CCU41_SR3 (XM4_IRQ_FIRST+51) /* 51: CCU4 Module 1, SR3 */ +#define XM4_IRQ_CCU42_SR0 (XM4_IRQ_FIRST+52) /* 52: CCU4 Module 2, SR0 */ +#define XM4_IRQ_CCU42_SR1 (XM4_IRQ_FIRST+53) /* 53: CCU4 Module 2, SR1 */ +#define XM4_IRQ_CCU42_SR2 (XM4_IRQ_FIRST+54) /* 54: CCU4 Module 2, SR2 */ +#define XM4_IRQ_CCU42_SR3 (XM4_IRQ_FIRST+55) /* 55: CCU4 Module 2, SR3 */ +#define XM4_IRQ_CCU43_SR0 (XM4_IRQ_FIRST+56) /* 56: CCU4 Module 3, SR0 */ +#define XM4_IRQ_CCU43_SR1 (XM4_IRQ_FIRST+57) /* 57: CCU4 Module 3, SR1 */ +#define XM4_IRQ_CCU43_SR2 (XM4_IRQ_FIRST+58) /* 58: CCU4 Module 3, SR2 */ +#define XM4_IRQ_CCU43_SR3 (XM4_IRQ_FIRST+59) /* 59: CCU4 Module 3, SR3 */ +#define XM4_IRQ_CCU80_SR0 (XM4_IRQ_FIRST+60) /* 60: CCU8 Module 0, SR0 */ +#define XM4_IRQ_CCU80_SR1 (XM4_IRQ_FIRST+61) /* 61: CCU8 Module 0, SR1 */ +#define XM4_IRQ_CCU80_SR2 (XM4_IRQ_FIRST+62) /* 62: CCU8 Module 0, SR2 */ +#define XM4_IRQ_CCU80_SR3 (XM4_IRQ_FIRST+63) /* 63: CCU8 Module 0, SR3 */ +#define XM4_IRQ_CCU81_SR0 (XM4_IRQ_FIRST+64) /* 64: CCU8 Module 1, SR0 */ +#define XM4_IRQ_CCU81_SR1 (XM4_IRQ_FIRST+65) /* 65: CCU8 Module 1, SR1 */ +#define XM4_IRQ_CCU81_SR2 (XM4_IRQ_FIRST+66) /* 66: CCU8 Module 1, SR2 */ +#define XM4_IRQ_CCU81_SR3 (XM4_IRQ_FIRST+67) /* 67: CCU8 Module 1, SR3 */ +#define XM4_IRQ_POSIF0_SR0 (XM4_IRQ_FIRST+68) /* 68: POSIF Module 0, SR0 */ +#define XM4_IRQ_POSIF0_SR1 (XM4_IRQ_FIRST+69) /* 69: POSIF Module 0, SR1 */ +#define XM4_IRQ_POSIF1_SR0 (XM4_IRQ_FIRST+70) /* 70: POSIF Module 1, SR0 */ +#define XM4_IRQ_POSIF1_SR1 (XM4_IRQ_FIRST+71) /* 71: POSIF Module 1, SR1 */ +#define XM4_IRQ_RESVD072 (XM4_IRQ_FIRST+72) /* 72: Reserved */ +#define XM4_IRQ_RESVD073 (XM4_IRQ_FIRST+73) /* 73: Reserved */ +#define XM4_IRQ_RESVD074 (XM4_IRQ_FIRST+74) /* 74: Reserved */ +#define XM4_IRQ_RESVD075 (XM4_IRQ_FIRST+75) /* 75: Reserved */ +#define XM4_IRQ_CAN_SR0 (XM4_IRQ_FIRST+76) /* 76: MultiCAN, SR0 */ +#define XM4_IRQ_CAN_SR1 (XM4_IRQ_FIRST+77) /* 77: MultiCAN, SR1 */ +#define XM4_IRQ_CAN_SR2 (XM4_IRQ_FIRST+78) /* 78: MultiCAN, SR2 */ +#define XM4_IRQ_CAN_SR3 (XM4_IRQ_FIRST+79) /* 79: MultiCAN, SR3 */ +#define XM4_IRQ_CAN_SR4 (XM4_IRQ_FIRST+80) /* 80: MultiCAN, SR4 */ +#define XM4_IRQ_CAN_SR5 (XM4_IRQ_FIRST+81) /* 81: MultiCAN, SR5 */ +#define XM4_IRQ_CAN_SR6 (XM4_IRQ_FIRST+82) /* 82: MultiCAN, SR6 */ +#define XM4_IRQ_CAN_SR7 (XM4_IRQ_FIRST+83) /* 83: MultiCAN, SR7 */ +#define XM4_IRQ_USIC0_SR0 (XM4_IRQ_FIRST+84) /* 84: USIC0 Channel, SR0 */ +#define XM4_IRQ_USIC0_SR1 (XM4_IRQ_FIRST+85) /* 85: USIC0 Channel, SR1 */ +#define XM4_IRQ_USIC0_SR2 (XM4_IRQ_FIRST+86) /* 86: USIC0 Channel, SR2 */ +#define XM4_IRQ_USIC0_SR3 (XM4_IRQ_FIRST+87) /* 87: USIC0 Channel, SR3 */ +#define XM4_IRQ_USIC0_SR4 (XM4_IRQ_FIRST+88) /* 88: USIC0 Channel, SR4 */ +#define XM4_IRQ_USIC0_SR5 (XM4_IRQ_FIRST+89) /* 89: USIC0 Channel, SR5 */ +#define XM4_IRQ_USIC1_SR0 (XM4_IRQ_FIRST+90) /* 90: USIC1 Channel, SR0 */ +#define XM4_IRQ_USIC1_SR1 (XM4_IRQ_FIRST+91) /* 91: USIC1 Channel, SR1 */ +#define XM4_IRQ_USIC1_SR2 (XM4_IRQ_FIRST+92) /* 92: USIC1 Channel, SR2 */ +#define XM4_IRQ_USIC1_SR3 (XM4_IRQ_FIRST+93) /* 93: USIC1 Channel, SR3 */ +#define XM4_IRQ_USIC1_SR4 (XM4_IRQ_FIRST+94) /* 94: USIC1 Channel, SR4 */ +#define XM4_IRQ_USIC1_SR5 (XM4_IRQ_FIRST+95) /* 95: USIC1 Channel, SR5 */ +#define XM4_IRQ_USIC2_SR0 (XM4_IRQ_FIRST+96) /* 96: USIC1 Channel, SR0 */ +#define XM4_IRQ_USIC2_SR1 (XM4_IRQ_FIRST+97) /* 97: USIC1 Channel, SR1 */ +#define XM4_IRQ_USIC2_SR2 (XM4_IRQ_FIRST+98) /* 98: USIC1 Channel, SR2 */ +#define XM4_IRQ_USIC2_SR3 (XM4_IRQ_FIRST+99) /* 99: USIC1 Channel, SR3 */ +#define XM4_IRQ_USIC2_SR4 (XM4_IRQ_FIRST+100) /* 100: USIC1 Channel, SR4 */ +#define XM4_IRQ_USIC2_SR5 (XM4_IRQ_FIRST+101) /* 101: USIC1 Channel, SR5 */ +#define XM4_IRQ_LEDTS0_SR0 (XM4_IRQ_FIRST+102) /* 102: LEDTS0, SR0 */ +#define XM4_IRQ_RESVD103 (XM4_IRQ_FIRST+103) /* 103: Reserved */ +#define XM4_IRQ_FCR_SR0 (XM4_IRQ_FIRST+104) /* 102: FCE, SR0 */ +#define XM4_IRQ_GPCMA0_SR0 (XM4_IRQ_FIRST+105) /* 105: GPDMA0, SR0 */ +#define XM4_IRQ_SDMMC_SR0 (XM4_IRQ_FIRST+106) /* 106: SDMMC, SR0 */ +#define XM4_IRQ_USB0_SR0 (XM4_IRQ_FIRST+107) /* 107: USB, SR0 */ +#define XM4_IRQ_ETH0_SR0 (XM4_IRQ_FIRST+108) /* 108: Ethernet, module 0, SR0 */ +#define XM4_IRQ_RESVD109 (XM4_IRQ_FIRST+109) /* 109: Reserved */ +#define XM4_IRQ_GPCMA1_SR0 (XM4_IRQ_FIRST+110) /* 110: GPDMA1, SR0 */ +#define XM4_IRQ_RESVD111 (XM4_IRQ_FIRST+111) /* 111: Reserved */ + +#define NR_INTERRUPTS 112 /* 112 Non core IRQs*/ +#define NR_VECTORS (XM4_IRQ_FIRST+NR_INTERRUPTS) /* 118 vectors */ + +/* GPIO IRQ interrupts -- To be provided */ + +#define NR_IRQS NR_VECTORS + +/***************************************************************************** + * Public Types + ****************************************************************************/ + +/***************************************************************************** + * Public Data + ****************************************************************************/ + +#ifndef __ASSEMBLY__ +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/***************************************************************************** + * Public Functions + ****************************************************************************/ + +#undef EXTERN +#ifdef __cplusplus +} +#endif +#endif + +#endif /* xmc4__ARCH_ARM_INCLUDE_XM4_XM4500_IRQ_H */ From a635e7df7a94c0ff187921c16c5aec568e86e6fa Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Tue, 14 Mar 2017 16:19:30 -0600 Subject: [PATCH 03/21] XMC4xxx: Add SCU header file. --- arch/arm/src/xmc4/chip/xmc4_scu.h | 453 ++++++++++++++++++++++++++++++ 1 file changed, 453 insertions(+) create mode 100644 arch/arm/src/xmc4/chip/xmc4_scu.h diff --git a/arch/arm/src/xmc4/chip/xmc4_scu.h b/arch/arm/src/xmc4/chip/xmc4_scu.h new file mode 100644 index 00000000000..a3e6d116e73 --- /dev/null +++ b/arch/arm/src/xmc4/chip/xmc4_scu.h @@ -0,0 +1,453 @@ +/************************************************************************************ + * arch/arm/src/xmc4/chip/xmc4_scu.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_XMC4_CHIP_XMC4_SCU_H +#define __ARCH_ARM_SRC_XMC4_CHIP_XMC4_SCU_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include +#include "chip/xmc4_memorymap.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Register Offsets *****************************************************************/ + +#define XMC4_GCU_OFFSET 0x0000 /* Offset address of General Control Unit */ +#define XMC4_PCU_OFFSET 0x0200 /* Offset address of Power Control Unit */ +#define XMC4_HCU_OFFSET 0x0300 /* Offset address of Hibernate Control Unit */ +#define XMC4_RCU_OFFSET 0x0400 /* Offset address of Reset Control Unit */ +#define XMC4_CCU_OFFSET 0x0600 /* Offset address of Clock Control Unit */ + +/* General SCU Registers */ + +#define XMC4_GCU_ID_OFFSET 0x0000 /* Module Identification Register */ +#define XMC4_GCU_IDCHIP_OFFSET 0x0004 /* Chip ID */ +#define XMC4_GCU_IDMANUF_OFFSET 0x0008 /* Manufactory ID */ +#define XMC4_GCU_STCON_OFFSET 0x0010 /* Start-up Control */ +#define XMC4_GCU_GPR0_OFFSET 0x002c /* General Purpose Register 0 */ +#define XMC4_GCU_GPR1_OFFSET 0x0030 /* General Purpose Register 1 */ +#define XMC4_GCU_ETH0CON_OFFSET 0x0040 /* Ethernet 0 Port Control */ +#define XMC4_GCU_CCUCON_OFFSET 0x004c /* CCUx Global Start Control Register */ +#define XMC4_GCU_SRSTAT_OFFSET 0x0074 /* Service Request Status */ +#define XMC4_GCU_SRRAW_OFFSET 0x0078 /* RAW Service Request Status */ +#define XMC4_GCU_SRMSK_OFFSET 0x007c /* Service Request Mask */ +#define XMC4_GCU_SRCLR_OFFSET 0x0080 /* Service Request Clear */ +#define XMC4_GCU_SRSET_OFFSET 0x0084 /* Service Request Set */ +#define XMC4_GCU_NMIREQEN_OFFSET 0x0088 /* Enable Promoting Events to NMI Request */ +#define XMC4_GCU_DTSCON_OFFSET 0x008c /* DTS Control */ +#define XMC4_GCU_DTSSTAT_OFFSET 0x0090 /* DTS Status */ +#define XMC4_GCU_SDMMCDEL_OFFSET 0x009c /* SD-MMC Delay Control Register */ +#define XMC4_GCU_G0ORCEN_OFFSET 0x00a0 /* Out-Of-Range Comparator Enable Register 0 */ +#define XMC4_GCU_G1ORCEN_OFFSET 0x00a4 /* Out-Of-Range Comparator Enable Register 1 */ +#define XMC4_GCU_MIRRSTS_OFFSET 0x00c4 /* Mirror Update Status Register */ +#define XMC4_GCU_RMACR_OFFSET 0x00c8 /* Retention Memory Access Control Register */ +#define XMC4_GCU_RMADATA_OFFSET 0x00cc /* Retention Memory Access Data Register */ +#define XMC4_GCU_PEEN_OFFSET 0x013c /* Parity Error Enable Register */ +#define XMC4_GCU_MCHKCON_OFFSET 0x0140 /* Memory Checking Control Register */ +#define XMC4_GCU_PETE_OFFSET 0x0144 /* Parity Error Trap Enable Register */ +#define XMC4_GCU_PERSTEN_OFFSET 0x0148 /* Reset upon Parity Error Enable Register */ +#define XMC4_GCU_PEFLAG_OFFSET 0x0150 /* Parity Error Control Register */ +#define XMC4_GCU_PMTPR_OFFSET 0x0154 /* Parity Memory Test Pattern Register */ +#define XMC4_GCU_PMTSR_OFFSET 0x0158 /* Parity Memory Test Select Register */ +#define XMC4_GCU_TRAPSTAT_OFFSET 0x0160 /* Trap Status Register */ +#define XMC4_GCU_TRAPRAW_OFFSET 0x0164 /* Trap Raw Status Register */ +#define XMC4_GCU_TRAPDIS_OFFSET 0x0168 /* Trap Mask Register */ +#define XMC4_GCU_TRAPCLR_OFFSET 0x016c /* Trap Clear Register */ +#define XMC4_GCU_TRAPSET_OFFSET 0x0170 /* Trap Set Register */ + +/* PCU Registers */ + +#define XMC4_PCU_PWRSTAT_OFFSET 0x0000 /* Power Status Register */ +#define XMC4_PCU_PWRSET_OFFSET 0x0004 /* Power Set Control Register */ +#define XMC4_PCU_PWRCLR_OFFSET 0x0008 /* Power Clear Control Register */ +#define XMC4_PCU_EVRSTAT_OFFSET 0x0010 /* EVR Status Register */ +#define XMC4_PCU_EVRVADCSTAT_OFFSET 0x0014 /* EVR VADC Status Register */ +#define XMC4_PCU_PWRMON_OFFSET 0x002c /* Power Monitor Value */ + +/* HCU Registers */ + +#define XMC4_HCU_HDSTAT_OFFSET 0x0000 /* Hibernate Domain Status Register */ +#define XMC4_HCU_HDCLR_OFFSET 0x0004 /* Hibernate Domain Status Clear Register */ +#define XMC4_HCU_HDSET_OFFSET 0x0008 /* Hibernate Domain Status Set Register */ +#define XMC4_HCU_HDCR_OFFSET 0x000c /* Hibernate Domain Control Register */ +#define XMC4_HCU_OSCSICTRL_OFFSET 0x0014 /* Internal 32.768 kHz Clock Source Control Register */ +#define XMC4_HCU_OSCULSTAT_OFFSET 0x0018 /* OSC_ULP Status Register */ +#define XMC4_HCU_OSCULCTRL_OFFSET 0x001c /* OSC_ULP Control Register */ + +/* RCU Registers */ + +#define XMC4_RCU_RSTSTAT_OFFSET 0x0000 /* System Reset Status */ +#define XMC4_RCU_RSTSET_OFFSET 0x0004 /* Reset Set Register */ +#define XMC4_RCU_RSTCLR_OFFSET 0x0008 /* Reset Clear Register */ +#define XMC4_RCU_PRSTAT0_OFFSET 0x000c /* Peripheral Reset Status Register 0 */ +#define XMC4_RCU_PRSET0_OFFSET 0x0010 /* Peripheral Reset Set Register 0 */ +#define XMC4_RCU_PRCLR0_OFFSET 0x0014 /* Peripheral Reset Clear Register 0 */ +#define XMC4_RCU_PRSTAT1_OFFSET 0x0018 /* Peripheral Reset Status Register 1 */ +#define XMC4_RCU_PRSET1_OFFSET 0x001c /* Peripheral Reset Set Register 1 */ +#define XMC4_RCU_PRCLR1_OFFSET 0x0020 /* Peripheral Reset Clear Register 1 */ +#define XMC4_RCU_PRSTAT2_OFFSET 0x0024 /* Peripheral Reset Status Register 2 */ +#define XMC4_RCU_PRSET2_OFFSET 0x0028 /* Peripheral Reset Set Register 2 */ +#define XMC4_RCU_PRCLR2_OFFSET 0x002c /* Peripheral Reset Clear Register 2 */ +#define XMC4_RCU_PRSTAT3_OFFSET 0x0030 /* Peripheral Reset Status Register 3 */ +#define XMC4_RCU_PRSET3_OFFSET 0x0034 /* Peripheral Reset Set Register 3 */ +#define XMC4_RCU_PRCLR3_OFFSET 0x0038 /* Peripheral Reset Clear Register 3 */ + +/* CCU Registers */ + +#define XMC4_CCU_CLKSTAT_OFFSET 0x0000 /* Clock Status Register */ +#define XMC4_CCU_CLKSET_OFFSET 0x0004 /* Clock Set Control Register */ +#define XMC4_CCU_CLKCLR_OFFSET 0x0008 /* Clock clear Control Register */ +#define XMC4_CCU_SYSCLKCR_OFFSET 0x000c /* System Clock Control */ +#define XMC4_CCU_CPUCLKCR_OFFSET 0x0010 /* CPU Clock Control */ +#define XMC4_CCU_PBCLKCR_OFFSET 0x0014 /* Peripheral Bus Clock Control */ +#define XMC4_CCU_USBCLKCR_OFFSET 0x0018 /* USB Clock Control */ +#define XMC4_CCU_EBUCLKCR_OFFSET 0x001c /* EBU Clock Control */ +#define XMC4_CCU_CCUCLKCR_OFFSET 0x0020 /* CCU Clock Control */ +#define XMC4_CCU_WDTCLKCR_OFFSET 0x0024 /* WDT Clock Control */ +#define XMC4_CCU_EXTCLKCR_OFFSET 0x0028 /* External clock Control Register */ +#define XMC4_CCU_SLEEPCR_OFFSET 0x0030 /* Sleep Control Register */ +#define XMC4_CCU_DSLEEPCR_OFFSET 0x0034 /* Deep Sleep Control Register */ +#define XMC4_CCU_OSCHPSTAT_OFFSET 0x0100 /* OSC_HP Status Register */ +#define XMC4_CCU_OSCHPCTRL_OFFSET 0x0104 /* OSC_HP Control Register */ +#define XMC4_CCU_CLKCALCONST_OFFSET 0x010c /* Clock Calibration Constant Register */ +#define XMC4_CCU_PLLSTAT_OFFSET 0x0110 /* System PLL Status Register */ +#define XMC4_CCU_PLLCON0_OFFSET 0x0114 /* System PLL Configuration 0 Register */ +#define XMC4_CCU_PLLCON1_OFFSET 0x0118 /* System PLL Configuration 1 Register */ +#define XMC4_CCU_PLLCON2_OFFSET 0x011c /* System PLL Configuration 2 Register */ +#define XMC4_CCU_USBPLLSTAT_OFFSET 0x0120 /* USB PLL Status Register */ +#define XMC4_CCU_USBPLLCON_OFFSET 0x0124 /* USB PLL Control Register */ +#define XMC4_CCU_CLKMXSTAT_OFFSET 0x0138 /* Clock Multiplexing Status Register */ + +/* Register Addresses ***************************************************************/ + +#define XMC4_GCU_BASE (XMC4_SCU_BASE+XMC4_GCU_OFFSET) +#define XMC4_PCU_BASE (XMC4_SCU_BASE+XMC4_PCU_OFFSET) +#define XMC4_HCU_BASE (XMC4_SCU_BASE+XMC4_HCU_OFFSET) +#define XMC4_RCU_BASE (XMC4_SCU_BASE+XMC4_RCU_OFFSET) +#define XMC4_CCU_BASE (XMC4_SCU_BASE+XMC4_CCU_OFFSET) + +/* General SCU Registers */ + +#define XMC4_GCU_ID (XMC4_GCU_BASE+XMC4_GCU_ID_OFFSET) +#define XMC4_GCU_IDCHIP (XMC4_GCU_BASE+XMC4_GCU_IDCHIP_OFFSET) +#define XMC4_GCU_IDMANUF (XMC4_GCU_BASE+XMC4_GCU_IDMANUF_OFFSET) +#define XMC4_GCU_STCON (XMC4_GCU_BASE+XMC4_GCU_STCON_OFFSET) +#define XMC4_GCU_GPR0 (XMC4_GCU_BASE+XMC4_GCU_GPR0_OFFSET) +#define XMC4_GCU_GPR1 (XMC4_GCU_BASE+XMC4_GCU_GPR1_OFFSET) +#define XMC4_GCU_ETH0CON (XMC4_GCU_BASE+XMC4_GCU_ETH0CON_OFFSET) +#define XMC4_GCU_CCUCON (XMC4_GCU_BASE+XMC4_GCU_CCUCON_OFFSET) +#define XMC4_GCU_SRSTAT (XMC4_GCU_BASE+XMC4_GCU_SRSTAT_OFFSET) +#define XMC4_GCU_SRRAW (XMC4_GCU_BASE+XMC4_GCU_SRRAW_OFFSET) +#define XMC4_GCU_SRMSK (XMC4_GCU_BASE+XMC4_GCU_SRMSK_OFFSET) +#define XMC4_GCU_SRCLR (XMC4_GCU_BASE+XMC4_GCU_SRCLR_OFFSET) +#define XMC4_GCU_SRSET (XMC4_GCU_BASE+XMC4_GCU_SRSET_OFFSET) +#define XMC4_GCU_NMIREQEN (XMC4_GCU_BASE+XMC4_GCU_NMIREQEN_OFFSET) +#define XMC4_GCU_DTSCON (XMC4_GCU_BASE+XMC4_GCU_DTSCON_OFFSET) +#define XMC4_GCU_DTSSTAT (XMC4_GCU_BASE+XMC4_GCU_DTSSTAT_OFFSET) +#define XMC4_GCU_SDMMCDEL (XMC4_GCU_BASE+XMC4_GCU_SDMMCDEL_OFFSET) +#define XMC4_GCU_G0ORCEN (XMC4_GCU_BASE+XMC4_GCU_G0ORCEN_OFFSET) +#define XMC4_GCU_G1ORCEN (XMC4_GCU_BASE+XMC4_GCU_G1ORCEN_OFFSET) +#define XMC4_GCU_MIRRSTS (XMC4_GCU_BASE+XMC4_GCU_MIRRSTS_OFFSET) +#define XMC4_GCU_RMACR (XMC4_GCU_BASE+XMC4_GCU_RMACR_OFFSET) +#define XMC4_GCU_RMADATA (XMC4_GCU_BASE+XMC4_GCU_RMADATA_OFFSET) +#define XMC4_GCU_PEEN (XMC4_GCU_BASE+XMC4_GCU_PEEN_OFFSET) +#define XMC4_GCU_MCHKCON (XMC4_GCU_BASE+XMC4_GCU_MCHKCON_OFFSET) +#define XMC4_GCU_PETE (XMC4_GCU_BASE+XMC4_GCU_PETE_OFFSET) +#define XMC4_GCU_PERSTEN (XMC4_GCU_BASE+XMC4_GCU_PERSTEN_OFFSET) +#define XMC4_GCU_PEFLAG (XMC4_GCU_BASE+XMC4_GCU_PEFLAG_OFFSET) +#define XMC4_GCU_PMTPR (XMC4_GCU_BASE+XMC4_GCU_PMTPR_OFFSET) +#define XMC4_GCU_PMTSR (XMC4_GCU_BASE+XMC4_GCU_PMTSR_OFFSET) +#define XMC4_GCU_TRAPSTAT (XMC4_GCU_BASE+XMC4_GCU_TRAPSTAT_OFFSET) +#define XMC4_GCU_TRAPRAW (XMC4_GCU_BASE+XMC4_GCU_TRAPRAW_OFFSET) +#define XMC4_GCU_TRAPDIS (XMC4_GCU_BASE+XMC4_GCU_TRAPDIS_OFFSET) +#define XMC4_GCU_TRAPCLR (XMC4_GCU_BASE+XMC4_GCU_TRAPCLR_OFFSET) +#define XMC4_GCU_TRAPSET (XMC4_GCU_BASE+XMC4_GCU_TRAPSET_OFFSET) + +/* PCU Registers */ + +#define XMC4_PCU_PWRSTAT (XMC4_PCU_BASE+XMC4_PCU_PWRSTAT_OFFSET) +#define XMC4_PCU_PWRSET (XMC4_PCU_BASE+XMC4_PCU_PWRSET_OFFSET) +#define XMC4_PCU_PWRCLR (XMC4_PCU_BASE+XMC4_PCU_PWRCLR_OFFSET) +#define XMC4_PCU_EVRSTAT (XMC4_PCU_BASE+XMC4_PCU_EVRSTAT_OFFSET) +#define XMC4_PCU_EVRVADCSTAT (XMC4_PCU_BASE+XMC4_PCU_EVRVADCSTAT_OFFSET) +#define XMC4_PCU_PWRMON (XMC4_PCU_BASE+XMC4_PCU_PWRMON_OFFSET) + +/* HCU Registers */ + +#define XMC4_HCU_HDSTAT (XMC4_HCU_BASE+XMC4_HCU_HDSTAT_OFFSET) +#define XMC4_HCU_HDCLR (XMC4_HCU_BASE+XMC4_HCU_HDCLR_OFFSET) +#define XMC4_HCU_HDSET (XMC4_HCU_BASE+XMC4_HCU_HDSET_OFFSET) +#define XMC4_HCU_HDCR (XMC4_HCU_BASE+XMC4_HCU_HDCR_OFFSET) +#define XMC4_HCU_OSCSICTRL (XMC4_HCU_BASE+XMC4_HCU_OSCSICTRL_OFFSET) +#define XMC4_HCU_OSCULSTAT (XMC4_HCU_BASE+XMC4_HCU_OSCULSTAT_OFFSET) +#define XMC4_HCU_OSCULCTRL (XMC4_HCU_BASE+XMC4_HCU_OSCULCTRL_OFFSET) + +/* RCU Registers */ + +#define XMC4_RCU_RSTSTAT (XMC4_RCU_BASE+XMC4_RCU_RSTSTAT_OFFSET) +#define XMC4_RCU_RSTSET (XMC4_RCU_BASE+XMC4_RCU_RSTSET_OFFSET) +#define XMC4_RCU_RSTCLR (XMC4_RCU_BASE+XMC4_RCU_RSTCLR_OFFSET) +#define XMC4_RCU_PRSTAT0 (XMC4_RCU_BASE+XMC4_RCU_PRSTAT0_OFFSET) +#define XMC4_RCU_PRSET0 (XMC4_RCU_BASE+XMC4_RCU_PRSET0_OFFSET) +#define XMC4_RCU_PRCLR0 (XMC4_RCU_BASE+XMC4_RCU_PRCLR0_OFFSET) +#define XMC4_RCU_PRSTAT1 (XMC4_RCU_BASE+XMC4_RCU_PRSTAT1_OFFSET) +#define XMC4_RCU_PRSET1 (XMC4_RCU_BASE+XMC4_RCU_PRSET1_OFFSET) +#define XMC4_RCU_PRCLR1 (XMC4_RCU_BASE+XMC4_RCU_PRCLR1_OFFSET) +#define XMC4_RCU_PRSTAT2 (XMC4_RCU_BASE+XMC4_RCU_PRSTAT2_OFFSET) +#define XMC4_RCU_PRSET2 (XMC4_RCU_BASE+XMC4_RCU_PRSET2_OFFSET) +#define XMC4_RCU_PRCLR2 (XMC4_RCU_BASE+XMC4_RCU_PRCLR2_OFFSET) +#define XMC4_RCU_PRSTAT3 (XMC4_RCU_BASE+XMC4_RCU_PRSTAT3_OFFSET) +#define XMC4_RCU_PRSET3 (XMC4_RCU_BASE+XMC4_RCU_PRSET3_OFFSET) +#define XMC4_RCU_PRCLR3 (XMC4_RCU_BASE+XMC4_RCU_PRCLR3_OFFSET) + +/* CCU Registers */ + +#define XMC4_CCU_CLKSTAT (XMC4_CCU_BASE+XMC4_CCU_CLKSTAT_OFFSET) +#define XMC4_CCU_CLKSET (XMC4_CCU_BASE+XMC4_CCU_CLKSET_OFFSET) +#define XMC4_CCU_CLKCLR (XMC4_CCU_BASE+XMC4_CCU_CLKCLR_OFFSET) +#define XMC4_CCU_SYSCLKCR (XMC4_CCU_BASE+XMC4_CCU_SYSCLKCR_OFFSET) +#define XMC4_CCU_CPUCLKCR (XMC4_CCU_BASE+XMC4_CCU_CPUCLKCR_OFFSET) +#define XMC4_CCU_PBCLKCR (XMC4_CCU_BASE+XMC4_CCU_PBCLKCR_OFFSET) +#define XMC4_CCU_USBCLKCR (XMC4_CCU_BASE+XMC4_CCU_USBCLKCR_OFFSET) +#define XMC4_CCU_EBUCLKCR (XMC4_CCU_BASE+XMC4_CCU_EBUCLKCR_OFFSET) +#define XMC4_CCU_CCUCLKCR (XMC4_CCU_BASE+XMC4_CCU_CCUCLKCR_OFFSET) +#define XMC4_CCU_WDTCLKCR (XMC4_CCU_BASE+XMC4_CCU_WDTCLKCR_OFFSET) +#define XMC4_CCU_EXTCLKCR (XMC4_CCU_BASE+XMC4_CCU_EXTCLKCR_OFFSET) +#define XMC4_CCU_SLEEPCR (XMC4_CCU_BASE+XMC4_CCU_SLEEPCR_OFFSET) +#define XMC4_CCU_DSLEEPCR (XMC4_CCU_BASE+XMC4_CCU_DSLEEPCR_OFFSET) +#define XMC4_CCU_OSCHPSTAT (XMC4_CCU_BASE+XMC4_CCU_OSCHPSTAT_OFFSET) +#define XMC4_CCU_OSCHPCTRL (XMC4_CCU_BASE+XMC4_CCU_OSCHPCTRL_OFFSET) +#define XMC4_CCU_CLKCALCONST (XMC4_CCU_BASE+XMC4_CCU_CLKCALCONST_OFFSET) +#define XMC4_CCU_PLLSTAT (XMC4_CCU_BASE+XMC4_CCU_PLLSTAT_OFFSET) +#define XMC4_CCU_PLLCON0 (XMC4_CCU_BASE+XMC4_CCU_PLLCON0_OFFSET) +#define XMC4_CCU_PLLCON1 (XMC4_CCU_BASE+XMC4_CCU_PLLCON1_OFFSET) +#define XMC4_CCU_PLLCON2 (XMC4_CCU_BASE+XMC4_CCU_PLLCON2_OFFSET) +#define XMC4_CCU_USBPLLSTAT (XMC4_CCU_BASE+XMC4_CCU_USBPLLSTAT_OFFSET) +#define XMC4_CCU_USBPLLCON (XMC4_CCU_BASE+XMC4_CCU_USBPLLCON_OFFSET) +#define XMC4_CCU_CLKMXSTAT (XMC4_CCU_BASE+XMC4_CCU_CLKMXSTAT_OFFSET) + +/* Register Bit-Field Definitions ***************************************************/ + +/* General SCU Registers */ + +/* Module Identification Register */ +#define GCU_ID_ +/* Chip ID */ +#define GCU_IDCHIP_ +/* Manufactory ID */ +#define GCU_IDMANUF_ +/* Start-up Control */ +#define GCU_STCON_ +/* General Purpose Register 0 */ +#define GCU_GPR0_ +/* General Purpose Register 1 */ +#define GCU_GPR1_ +/* Ethernet 0 Port Control */ +#define GCU_ETH0CON_ +/* CCUx Global Start Control Register */ +#define GCU_CCUCON_ +/* Service Request Status */ +#define GCU_SRSTAT_ +/* RAW Service Request Status */ +#define GCU_SRRAW_ +/* Service Request Mask */ +#define GCU_SRMSK_ +/* Service Request Clear */ +#define GCU_SRCLR_ +/* Service Request Set */ +#define GCU_SRSET_ +/* Enable Promoting Events to NMI Request */ +#define GCU_NMIREQEN_ +/* DTS Control */ +#define GCU_DTSCON_ +/* DTS Status */ +#define GCU_DTSSTAT_ +/* SD-MMC Delay Control Register */ +#define GCU_SDMMCDEL_ +/* Out-Of-Range Comparator Enable Register 0 */ +#define GCU_G0ORCEN_ +/* Out-Of-Range Comparator Enable Register 1 */ +#define GCU_G1ORCEN_ +/* Mirror Update Status Register */ +#define GCU_MIRRSTS_ +/* Retention Memory Access Control Register */ +#define GCU_RMACR_ +/* Retention Memory Access Data Register */ +#define GCU_RMADATA_ +/* Parity Error Enable Register */ +#define GCU_PEEN_ +/* Memory Checking Control Register */ +#define GCU_MCHKCON_ +/* Parity Error Trap Enable Register */ +#define GCU_PETE_ +/* Reset upon Parity Error Enable Register */ +#define GCU_PERSTEN_ +/* Parity Error Control Register */ +#define GCU_PEFLAG_ +/* Parity Memory Test Pattern Register */ +#define GCU_PMTPR_ +/* Parity Memory Test Select Register */ +#define GCU_PMTSR_ +/* Trap Status Register */ +#define GCU_TRAPSTAT_ +/* Trap Raw Status Register */ +#define GCU_TRAPRAW_ +/* Trap Mask Register */ +#define GCU_TRAPDIS_ +/* Trap Clear Register */ +#define GCU_TRAPCLR_ +/* Trap Set Register */ +#define GCU_TRAPSET_ + +/* PCU Registers */ + +/* Power Status Register */ +#define PCU_PWRSTAT_ +/* Power Set Control Register */ +#define PCU_PWRSET_ +/* Power Clear Control Register */ +#define PCU_PWRCLR_ +/* EVR Status Register */ +#define PCU_EVRSTAT_ +/* EVR VADC Status Register */ +#define PCU_EVRVADCSTAT_ +/* Power Monitor Value */ +#define PCU_PWRMON_ + +/* HCU Registers */ + +/* Hibernate Domain Status Register */ +#define HCU_HDSTAT_ +/* Hibernate Domain Status Clear Register */ +#define HCU_HDCLR_ +/* Hibernate Domain Status Set Register */ +#define HCU_HDSET_ +/* Hibernate Domain Control Register */ +#define HCU_HDCR_ +/* Internal 32.768 kHz Clock Source Control Register */ +#define HCU_OSCSICTRL_ +/* OSC_ULP Status Register */ +#define HCU_OSCULSTAT_ +/* OSC_ULP Control Register */ +#define HCU_OSCULCTRL_ + +/* RCU Registers */ + +/* System Reset Status */ +#define RCU_RSTSTAT_ +/* Reset Set Register */ +#define RCU_RSTSET_ +/* Reset Clear Register */ +#define RCU_RSTCLR_ +/* Peripheral Reset Status Register 0 */ +#define RCU_PRSTAT0_ +/* Peripheral Reset Set Register 0 */ +#define RCU_PRSET0_ +/* Peripheral Reset Clear Register 0 */ +#define RCU_PRCLR0_ +/* Peripheral Reset Status Register 1 */ +#define RCU_PRSTAT1_ +/* Peripheral Reset Set Register 1 */ +#define RCU_PRSET1_ +/* Peripheral Reset Clear Register 1 */ +#define RCU_PRCLR1_ +/* Peripheral Reset Status Register 2 */ +#define RCU_PRSTAT2_ +/* Peripheral Reset Set Register 2 */ +#define RCU_PRSET2_ +/* Peripheral Reset Clear Register 2 */ +#define RCU_PRCLR2_ +/* Peripheral Reset Status Register 3 */ +#define RCU_PRSTAT3_ +/* Peripheral Reset Set Register 3 */ +#define RCU_PRSET3_ +/* Peripheral Reset Clear Register 3 */ +#define RCU_PRCLR3_ + +/* CCU Registers */ + +/* Clock Status Register */ +#define CCU_CLKSTAT_ +/* Clock Set Control Register */ +#define CCU_CLKSET_ +/* Clock clear Control Register */ +#define CCU_CLKCLR_ +/* System Clock Control */ +#define CCU_SYSCLKCR_ +/* CPU Clock Control */ +#define CCU_CPUCLKCR_ +/* Peripheral Bus Clock Control */ +#define CCU_PBCLKCR_ +/* USB Clock Control */ +#define CCU_USBCLKCR_ +/* EBU Clock Control */ +#define CCU_EBUCLKCR_ +/* CCU Clock Control */ +#define CCU_CCUCLKCR_ +/* WDT Clock Control */ +#define CCU_WDTCLKCR_ +/* External clock Control Register */ +#define CCU_EXTCLKCR_ +/* Sleep Control Register */ +#define CCU_SLEEPCR_ +/* Deep Sleep Control Register */ +#define CCU_DSLEEPCR_ +/* OSC_HP Status Register */ +#define CCU_OSCHPSTAT_ +/* OSC_HP Control Register */ +#define CCU_OSCHPCTRL_ +/* Clock Calibration Constant Register */ +#define CCU_CLKCALCONST_ +/* System PLL Status Register */ +#define CCU_PLLSTAT_ +/* System PLL Configuration 0 Register */ +#define CCU_PLLCON0_ +/* System PLL Configuration 1 Register */ +#define CCU_PLLCON1_ +/* System PLL Configuration 2 Register */ +#define CCU_PLLCON2_ +/* USB PLL Status Register */ +#define CCU_USBPLLSTAT_ +/* USB PLL Control Register */ +#define CCU_USBPLLCON_ +/* Clock Multiplexing Status Register */ +#define CCU_CLKMXSTAT_ + +#endif /* __ARCH_ARM_SRC_XMC4_CHIP_XMC4_SCU_H */ From 772b3cf21b66b7649b4b1a8e87d70afc081908e6 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Tue, 14 Mar 2017 19:07:19 -0600 Subject: [PATCH 04/21] XMC4xxx: Add Peripheral Memory Map header file. --- arch/arm/src/xmc4/chip/xmc4_memorymap.h | 227 ++++++++ arch/arm/src/xmc4/chip/xmc4_scu.h | 728 ++++++++++++++---------- 2 files changed, 654 insertions(+), 301 deletions(-) create mode 100644 arch/arm/src/xmc4/chip/xmc4_memorymap.h diff --git a/arch/arm/src/xmc4/chip/xmc4_memorymap.h b/arch/arm/src/xmc4/chip/xmc4_memorymap.h new file mode 100644 index 00000000000..8cf50174b9a --- /dev/null +++ b/arch/arm/src/xmc4/chip/xmc4_memorymap.h @@ -0,0 +1,227 @@ +/************************************************************************************ + * arch/arm/src/xmc4/chip/xmc4_memorymap.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Reference: XMC4500 Reference Manual V1.5 2014-07 Microcontrollers. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * May include some logic from sample code provided by Infineon: + * + * Copyright (C) 2011-2015 Infineon Technologies AG. All rights reserved. + * + * Infineon Technologies AG (Infineon) is supplying this software for use with + * Infineon's microcontrollers. This file can be freely distributed within + * development tools that are supporting such microcontrollers. + * + * THIS SOFTWARE IS PROVIDED AS IS. NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, + * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_XMC4_CHIP_XMC4_MEMORYMAP_H +#define __ARCH_ARM_SRC_XMC4_CHIP_XMC4_MEMORYMAP_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Peripheral Memory Map ************************************************************/ +/* Acronyms: + * ADC - Analog to Digital Converter + * CCU - Capture Compare Unit + * DAC - Digital to Analog Converter + * DSD - Delta Sigmoid Demodulator + * ERU - External Request Unit + * FCE - Flexible CRC Engine + * GPDMA - General Purpose DMA + * LEDTS - LED and Touch Sense Control Unit + * PMU - Program Management Unit + * POSIF - Position Interface + * SDMMC - Multi Media Card Interface + * USB - Universal Serial Bus + * USCI - Universal Serial Interface + */ + +#define XMC4_PBA0_BASE 0x40000000 +#define XMC4_VADC_BASE 0x40004000 +#define XMC4_VADC_G0_BASE 0x40004400 +#define XMC4_VADC_G1_BASE 0x40004800 +#define XMC4_VADC_G2_BASE 0x40004c00 +#define XMC4_VADC_G3_BASE 0x40005000 +#define XMC4_DSD_BASE 0x40008000 +#define XMC4_DSD_CH0_BASE 0x40008100 +#define XMC4_DSD_CH1_BASE 0x40008200 +#define XMC4_DSD_CH2_BASE 0x40008300 +#define XMC4_DSD_CH3_BASE 0x40008400 +#define XMC4_CCU40_BASE 0x4000c000 +#define XMC4_CCU40_CC40_BASE 0x4000c100 +#define XMC4_CCU40_CC41_BASE 0x4000c200 +#define XMC4_CCU40_CC42_BASE 0x4000c300 +#define XMC4_CCU40_CC43_BASE 0x4000c400 +#define XMC4_CCU41_BASE 0x40010000 +#define XMC4_CCU41_CC40_BASE 0x40010100 +#define XMC4_CCU41_CC41_BASE 0x40010200 +#define XMC4_CCU41_CC42_BASE 0x40010300 +#define XMC4_CCU41_CC43_BASE 0x40010400 +#define XMC4_CCU42_BASE 0x40014000 +#define XMC4_CCU42_CC40_BASE 0x40014100 +#define XMC4_CCU42_CC41_BASE 0x40014200 +#define XMC4_CCU42_CC42_BASE 0x40014300 +#define XMC4_CCU42_CC43_BASE 0x40014400 +#define XMC4_CCU80_BASE 0x40020000 +#define XMC4_CCU80_CC80_BASE 0x40020100 +#define XMC4_CCU80_CC81_BASE 0x40020200 +#define XMC4_CCU80_CC82_BASE 0x40020300 +#define XMC4_CCU80_CC83_BASE 0x40020400 +#define XMC4_CCU81_BASE 0x40024000 +#define XMC4_CCU81_CC80_BASE 0x40024100 +#define XMC4_CCU81_CC81_BASE 0x40024200 +#define XMC4_CCU81_CC82_BASE 0x40024300 +#define XMC4_CCU81_CC83_BASE 0x40024400 +#define XMC4_POSIF0_BASE 0x40028000 +#define XMC4_POSIF1_BASE 0x4002c000 +#define XMC4_USIC0_BASE 0x40030008 +#define XMC4_USIC0_CH0_BASE 0x40030000 +#define XMC4_USIC0_CH1_BASE 0x40030200 +#define XMC4_ERU1_BASE 0x40044000 + +#define XMC4_PBA1_BASE 0x48000000 +#define XMC4_CCU43_BASE 0x48004000 +#define XMC4_CCU43_CC40_BASE 0x48004100 +#define XMC4_CCU43_CC41_BASE 0x48004200 +#define XMC4_CCU43_CC42_BASE 0x48004300 +#define XMC4_CCU43_CC43_BASE 0x48004400 +#define XMC4_LEDTS0_BASE 0x48010000 +#define XMC4_CAN_BASE 0x48014000 +#define XMC4_CAN_NODE0_BASE 0x48014200 +#define XMC4_CAN_NODE1_BASE 0x48014300 +#define XMC4_CAN_NODE2_BASE 0x48014400 +#define XMC4_CAN_NODE3_BASE 0x48014500 +#define XMC4_CAN_NODE4_BASE 0x48014600 +#define XMC4_CAN_NODE5_BASE 0x48014700 +#define XMC4_CAN_MO_BASE 0x48015000 +#define XMC4_DAC_BASE 0x48018000 +#define XMC4_SDMMC_BASE 0x4801c000 +#define XMC4_USIC1_CH0_BASE 0x48020000 +#define XMC4_USIC1_BASE 0x48020008 +#define XMC4_USIC1_CH1_BASE 0x48020200 +#define XMC4_USIC2_CH0_BASE 0x48024000 +#define XMC4_USIC2_BASE 0x48024008 +#define XMC4_USIC2_CH1_BASE 0x48024200 +#define XMC4_PORT0_BASE 0x48028000 +#define XMC4_PORT1_BASE 0x48028100 +#define XMC4_PORT2_BASE 0x48028200 +#define XMC4_PORT3_BASE 0x48028300 +#define XMC4_PORT4_BASE 0x48028400 +#define XMC4_PORT5_BASE 0x48028500 +#define XMC4_PORT6_BASE 0x48028600 +#define XMC4_PORT7_BASE 0x48028700 +#define XMC4_PORT8_BASE 0x48028800 +#define XMC4_PORT9_BASE 0x48028900 +#define XMC4_PORT14_BASE 0x48028e00 +#define XMC4_PORT15_BASE 0x48028f00 + +#define XMC4_SCU_GENERAL_BASE 0x50004000 +#define XMC4_ETH0_CON_BASE 0x50004040 +#define XMC4_SCU_INTERRUPT_BASE 0x50004074 +#define XMC4_SDMMC_CON_BASE 0x500040b4 +#define XMC4_SCU_PARITY_BASE 0x5000413c +#define XMC4_SCU_TRAP_BASE 0x50004160 +#define XMC4_SCU_POWER_BASE 0x50004200 +#define XMC4_SCU_HIBERNATE_BASE 0x50004300 +#define XMC4_SCU_RESET_BASE 0x50004400 +#define XMC4_SCU_CLK_BASE 0x50004600 +#define XMC4_SCU_OSC_BASE 0x50004700 +#define XMC4_SCU_PLL_BASE 0x50004710 +#define XMC4_ERU0_BASE 0x50004800 +#define XMC4_DLR_BASE 0x50004900 +#define XMC4_RTC_BASE 0x50004a00 +#define XMC4_WDT_BASE 0x50008000 +#define XMC4_ETH0_BASE 0x5000c000 +#define XMC4_USB0_BASE 0x50040000 +#define XMC4_USB0_CH0_BASE 0x50040500 +#define XMC4_USB0_CH1_BASE 0x50040520 +#define XMC4_USB0_CH2_BASE 0x50040540 +#define XMC4_USB0_CH3_BASE 0x50040560 +#define XMC4_USB0_CH4_BASE 0x50040580 +#define XMC4_USB0_CH5_BASE 0x500405a0 +#define XMC4_USB0_CH6_BASE 0x500405c0 +#define XMC4_USB0_CH7_BASE 0x500405e0 +#define XMC4_USB0_CH8_BASE 0x50040600 +#define XMC4_USB0_CH9_BASE 0x50040620 +#define XMC4_USB0_CH10_BASE 0x50040640 +#define XMC4_USB0_CH11_BASE 0x50040660 +#define XMC4_USB0_CH12_BASE 0x50040680 +#define XMC4_USB0_CH13_BASE 0x500406a0 +#define XMC4_USB_EP_BASE 0x50040900 +#define XMC4_USB0_EP1_BASE 0x50040920 +#define XMC4_USB0_EP2_BASE 0x50040940 +#define XMC4_USB0_EP3_BASE 0x50040960 +#define XMC4_USB0_EP4_BASE 0x50040980 +#define XMC4_USB0_EP5_BASE 0x500409a0 +#define XMC4_USB0_EP6_BASE 0x500409c0 +#define XMC4_GPDMA0_CH0_BASE 0x50014000 +#define XMC4_GPDMA0_CH1_BASE 0x50014058 +#define XMC4_GPDMA0_CH2_BASE 0x500140b0 +#define XMC4_GPDMA0_CH3_BASE 0x50014108 +#define XMC4_GPDMA0_CH4_BASE 0x50014160 +#define XMC4_GPDMA0_CH5_BASE 0x500141b8 +#define XMC4_GPDMA0_CH6_BASE 0x50014210 +#define XMC4_GPDMA0_CH7_BASE 0x50014268 +#define XMC4_GPDMA0_BASE 0x500142c0 +#define XMC4_GPDMA1_CH0_BASE 0x50018000 +#define XMC4_GPDMA1_CH1_BASE 0x50018058 +#define XMC4_GPDMA1_CH2_BASE 0x500180b0 +#define XMC4_GPDMA1_CH3_BASE 0x50018108 +#define XMC4_GPDMA1_BASE 0x500182c0 +#define XMC4_FCE_BASE 0x50020000 +#define XMC4_FCE_KE0_BASE 0x50020020 +#define XMC4_FCE_KE1_BASE 0x50020040 +#define XMC4_FCE_KE2_BASE 0x50020060 +#define XMC4_FCE_KE3_BASE 0x50020080 + +#define XMC4_PMU0_BASE 0x58000508 +#define XMC4_FLASH0_BASE 0x58001000 +#define XMC4_PREF_BASE 0x58004000 +#define XMC4_EBU_BASE 0x58008000 + +#define XMC4_PPB_BASE 0xe000e000 + +#endif /* __ARCH_ARM_SRC_XMC4_CHIP_XMC4_SCU_H */ diff --git a/arch/arm/src/xmc4/chip/xmc4_scu.h b/arch/arm/src/xmc4/chip/xmc4_scu.h index a3e6d116e73..ab5b7719953 100644 --- a/arch/arm/src/xmc4/chip/xmc4_scu.h +++ b/arch/arm/src/xmc4/chip/xmc4_scu.h @@ -4,6 +4,8 @@ * Copyright (C) 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * + * Reference: XMC4500 Reference Manual V1.5 2014-07 Microcontrollers. + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: @@ -31,6 +33,20 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * + * May include some logic from sample code provided by Infineon: + * + * Copyright (C) 2011-2015 Infineon Technologies AG. All rights reserved. + * + * Infineon Technologies AG (Infineon) is supplying this software for use with + * Infineon's microcontrollers. This file can be freely distributed within + * development tools that are supporting such microcontrollers. + * + * THIS SOFTWARE IS PROVIDED AS IS. NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, + * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * ************************************************************************************/ #ifndef __ARCH_ARM_SRC_XMC4_CHIP_XMC4_SCU_H @@ -48,406 +64,516 @@ ************************************************************************************/ /* Register Offsets *****************************************************************/ - -#define XMC4_GCU_OFFSET 0x0000 /* Offset address of General Control Unit */ -#define XMC4_PCU_OFFSET 0x0200 /* Offset address of Power Control Unit */ -#define XMC4_HCU_OFFSET 0x0300 /* Offset address of Hibernate Control Unit */ -#define XMC4_RCU_OFFSET 0x0400 /* Offset address of Reset Control Unit */ -#define XMC4_CCU_OFFSET 0x0600 /* Offset address of Clock Control Unit */ - /* General SCU Registers */ -#define XMC4_GCU_ID_OFFSET 0x0000 /* Module Identification Register */ -#define XMC4_GCU_IDCHIP_OFFSET 0x0004 /* Chip ID */ -#define XMC4_GCU_IDMANUF_OFFSET 0x0008 /* Manufactory ID */ -#define XMC4_GCU_STCON_OFFSET 0x0010 /* Start-up Control */ -#define XMC4_GCU_GPR0_OFFSET 0x002c /* General Purpose Register 0 */ -#define XMC4_GCU_GPR1_OFFSET 0x0030 /* General Purpose Register 1 */ -#define XMC4_GCU_ETH0CON_OFFSET 0x0040 /* Ethernet 0 Port Control */ -#define XMC4_GCU_CCUCON_OFFSET 0x004c /* CCUx Global Start Control Register */ -#define XMC4_GCU_SRSTAT_OFFSET 0x0074 /* Service Request Status */ -#define XMC4_GCU_SRRAW_OFFSET 0x0078 /* RAW Service Request Status */ -#define XMC4_GCU_SRMSK_OFFSET 0x007c /* Service Request Mask */ -#define XMC4_GCU_SRCLR_OFFSET 0x0080 /* Service Request Clear */ -#define XMC4_GCU_SRSET_OFFSET 0x0084 /* Service Request Set */ -#define XMC4_GCU_NMIREQEN_OFFSET 0x0088 /* Enable Promoting Events to NMI Request */ -#define XMC4_GCU_DTSCON_OFFSET 0x008c /* DTS Control */ -#define XMC4_GCU_DTSSTAT_OFFSET 0x0090 /* DTS Status */ -#define XMC4_GCU_SDMMCDEL_OFFSET 0x009c /* SD-MMC Delay Control Register */ -#define XMC4_GCU_G0ORCEN_OFFSET 0x00a0 /* Out-Of-Range Comparator Enable Register 0 */ -#define XMC4_GCU_G1ORCEN_OFFSET 0x00a4 /* Out-Of-Range Comparator Enable Register 1 */ -#define XMC4_GCU_MIRRSTS_OFFSET 0x00c4 /* Mirror Update Status Register */ -#define XMC4_GCU_RMACR_OFFSET 0x00c8 /* Retention Memory Access Control Register */ -#define XMC4_GCU_RMADATA_OFFSET 0x00cc /* Retention Memory Access Data Register */ -#define XMC4_GCU_PEEN_OFFSET 0x013c /* Parity Error Enable Register */ -#define XMC4_GCU_MCHKCON_OFFSET 0x0140 /* Memory Checking Control Register */ -#define XMC4_GCU_PETE_OFFSET 0x0144 /* Parity Error Trap Enable Register */ -#define XMC4_GCU_PERSTEN_OFFSET 0x0148 /* Reset upon Parity Error Enable Register */ -#define XMC4_GCU_PEFLAG_OFFSET 0x0150 /* Parity Error Control Register */ -#define XMC4_GCU_PMTPR_OFFSET 0x0154 /* Parity Memory Test Pattern Register */ -#define XMC4_GCU_PMTSR_OFFSET 0x0158 /* Parity Memory Test Select Register */ -#define XMC4_GCU_TRAPSTAT_OFFSET 0x0160 /* Trap Status Register */ -#define XMC4_GCU_TRAPRAW_OFFSET 0x0164 /* Trap Raw Status Register */ -#define XMC4_GCU_TRAPDIS_OFFSET 0x0168 /* Trap Mask Register */ -#define XMC4_GCU_TRAPCLR_OFFSET 0x016c /* Trap Clear Register */ -#define XMC4_GCU_TRAPSET_OFFSET 0x0170 /* Trap Set Register */ +#define XMC4_SCU_ID_OFFSET 0x0000 /* Module Identification Register */ +#define XMC4_SCU_IDCHIP_OFFSET 0x0004 /* Chip ID */ +#define XMC4_SCU_IDMANUF_OFFSET 0x0008 /* Manufactory ID */ +#define XMC4_SCU_STCON_OFFSET 0x0010 /* Start-up Control */ +#define XMC4_SCU_GPR0_OFFSET 0x002c /* General Purpose Register 0 */ +#define XMC4_SCU_GPR1_OFFSET 0x0030 /* General Purpose Register 1 */ +#define XMC4_SCU_ETH0CON_OFFSET 0x0040 /* Ethernet 0 Port Control */ +#define XMC4_SCU_CCUCON_OFFSET 0x004c /* CCUx Global Start Control Register */ +#define XMC4_SCU_DTSCON_OFFSET 0x008c /* DTS Control */ +#define XMC4_SCU_DTSSTAT_OFFSET 0x0090 /* DTS Status */ +#define XMC4_SCU_SDMMCDEL_OFFSET 0x009c /* SD-MMC Delay Control Register */ +#define XMC4_SCU_G0ORCEN_OFFSET 0x00a0 /* Out-Of-Range Comparator Enable Register 0 */ +#define XMC4_SCU_G1ORCEN_OFFSET 0x00a4 /* Out-Of-Range Comparator Enable Register 1 */ +#define XMC4_SCU_MIRRSTS_OFFSET 0x00c4 /* Mirror Update Status Register */ +#define XMC4_SCU_RMACR_OFFSET 0x00c8 /* Retention Memory Access Control Register */ +#define XMC4_SCU_RMADATA_OFFSET 0x00cc /* Retention Memory Access Data Register */ -/* PCU Registers */ +/* Ethernet Control SCU Resters */ -#define XMC4_PCU_PWRSTAT_OFFSET 0x0000 /* Power Status Register */ -#define XMC4_PCU_PWRSET_OFFSET 0x0004 /* Power Set Control Register */ -#define XMC4_PCU_PWRCLR_OFFSET 0x0008 /* Power Clear Control Register */ -#define XMC4_PCU_EVRSTAT_OFFSET 0x0010 /* EVR Status Register */ -#define XMC4_PCU_EVRVADCSTAT_OFFSET 0x0014 /* EVR VADC Status Register */ -#define XMC4_PCU_PWRMON_OFFSET 0x002c /* Power Monitor Value */ +#define XMC4_SCU_ETHCON_OFFSET 0x0000 /* Ethernet 0 Port Control Register */ -/* HCU Registers */ +/* Interrupt Control SCU Registers */ -#define XMC4_HCU_HDSTAT_OFFSET 0x0000 /* Hibernate Domain Status Register */ -#define XMC4_HCU_HDCLR_OFFSET 0x0004 /* Hibernate Domain Status Clear Register */ -#define XMC4_HCU_HDSET_OFFSET 0x0008 /* Hibernate Domain Status Set Register */ -#define XMC4_HCU_HDCR_OFFSET 0x000c /* Hibernate Domain Control Register */ -#define XMC4_HCU_OSCSICTRL_OFFSET 0x0014 /* Internal 32.768 kHz Clock Source Control Register */ -#define XMC4_HCU_OSCULSTAT_OFFSET 0x0018 /* OSC_ULP Status Register */ -#define XMC4_HCU_OSCULCTRL_OFFSET 0x001c /* OSC_ULP Control Register */ +#define XMC4_SCU_SRSTAT_OFFSET 0x0000 /* Service Request Status */ +#define XMC4_SCU_SRRAW_OFFSET 0x0004 /* RAW Service Request Status */ +#define XMC4_SCU_SRMSK_OFFSET 0x0008 /* Service Request Mask */ +#define XMC4_SCU_SRCLR_OFFSET 0x000c /* Service Request Clear */ +#define XMC4_SCU_SRSET_OFFSET 0x0010 /* Service Request Set */ +#define XMC4_SCU_NMIREQEN_OFFSET 0x0014 /* Enable Promoting Events to NMI Request */ -/* RCU Registers */ +/* SDMMC Control SCU Registers */ -#define XMC4_RCU_RSTSTAT_OFFSET 0x0000 /* System Reset Status */ -#define XMC4_RCU_RSTSET_OFFSET 0x0004 /* Reset Set Register */ -#define XMC4_RCU_RSTCLR_OFFSET 0x0008 /* Reset Clear Register */ -#define XMC4_RCU_PRSTAT0_OFFSET 0x000c /* Peripheral Reset Status Register 0 */ -#define XMC4_RCU_PRSET0_OFFSET 0x0010 /* Peripheral Reset Set Register 0 */ -#define XMC4_RCU_PRCLR0_OFFSET 0x0014 /* Peripheral Reset Clear Register 0 */ -#define XMC4_RCU_PRSTAT1_OFFSET 0x0018 /* Peripheral Reset Status Register 1 */ -#define XMC4_RCU_PRSET1_OFFSET 0x001c /* Peripheral Reset Set Register 1 */ -#define XMC4_RCU_PRCLR1_OFFSET 0x0020 /* Peripheral Reset Clear Register 1 */ -#define XMC4_RCU_PRSTAT2_OFFSET 0x0024 /* Peripheral Reset Status Register 2 */ -#define XMC4_RCU_PRSET2_OFFSET 0x0028 /* Peripheral Reset Set Register 2 */ -#define XMC4_RCU_PRCLR2_OFFSET 0x002c /* Peripheral Reset Clear Register 2 */ -#define XMC4_RCU_PRSTAT3_OFFSET 0x0030 /* Peripheral Reset Status Register 3 */ -#define XMC4_RCU_PRSET3_OFFSET 0x0034 /* Peripheral Reset Set Register 3 */ -#define XMC4_RCU_PRCLR3_OFFSET 0x0038 /* Peripheral Reset Clear Register 3 */ +#define XMC4_SCU_SDMMCCON_OFFSET 0x0000 /* SDMMC Configuration */ -/* CCU Registers */ +/* Parity Control Registers */ -#define XMC4_CCU_CLKSTAT_OFFSET 0x0000 /* Clock Status Register */ -#define XMC4_CCU_CLKSET_OFFSET 0x0004 /* Clock Set Control Register */ -#define XMC4_CCU_CLKCLR_OFFSET 0x0008 /* Clock clear Control Register */ -#define XMC4_CCU_SYSCLKCR_OFFSET 0x000c /* System Clock Control */ -#define XMC4_CCU_CPUCLKCR_OFFSET 0x0010 /* CPU Clock Control */ -#define XMC4_CCU_PBCLKCR_OFFSET 0x0014 /* Peripheral Bus Clock Control */ -#define XMC4_CCU_USBCLKCR_OFFSET 0x0018 /* USB Clock Control */ -#define XMC4_CCU_EBUCLKCR_OFFSET 0x001c /* EBU Clock Control */ -#define XMC4_CCU_CCUCLKCR_OFFSET 0x0020 /* CCU Clock Control */ -#define XMC4_CCU_WDTCLKCR_OFFSET 0x0024 /* WDT Clock Control */ -#define XMC4_CCU_EXTCLKCR_OFFSET 0x0028 /* External clock Control Register */ -#define XMC4_CCU_SLEEPCR_OFFSET 0x0030 /* Sleep Control Register */ -#define XMC4_CCU_DSLEEPCR_OFFSET 0x0034 /* Deep Sleep Control Register */ -#define XMC4_CCU_OSCHPSTAT_OFFSET 0x0100 /* OSC_HP Status Register */ -#define XMC4_CCU_OSCHPCTRL_OFFSET 0x0104 /* OSC_HP Control Register */ -#define XMC4_CCU_CLKCALCONST_OFFSET 0x010c /* Clock Calibration Constant Register */ -#define XMC4_CCU_PLLSTAT_OFFSET 0x0110 /* System PLL Status Register */ -#define XMC4_CCU_PLLCON0_OFFSET 0x0114 /* System PLL Configuration 0 Register */ -#define XMC4_CCU_PLLCON1_OFFSET 0x0118 /* System PLL Configuration 1 Register */ -#define XMC4_CCU_PLLCON2_OFFSET 0x011c /* System PLL Configuration 2 Register */ -#define XMC4_CCU_USBPLLSTAT_OFFSET 0x0120 /* USB PLL Status Register */ -#define XMC4_CCU_USBPLLCON_OFFSET 0x0124 /* USB PLL Control Register */ -#define XMC4_CCU_CLKMXSTAT_OFFSET 0x0138 /* Clock Multiplexing Status Register */ +#define XMC4_SCU_PEEN_OFFSET 0x0000 /* Parity Error Enable Register */ +#define XMC4_SCU_MCHKCON_OFFSET 0x0004 /* Memory Checking Control Register */ +#define XMC4_SCU_PETE_OFFSET 0x0008 /* Parity Error Trap Enable Register */ +#define XMC4_SCU_PERSTEN_OFFSET 0x000c /* Reset upon Parity Error Enable Register */ +#define XMC4_SCU_PEFLAG_OFFSET 0x0014 /* Parity Error Control Register */ +#define XMC4_SCU_PMTPR_OFFSET 0x0018 /* Parity Memory Test Pattern Register */ +#define XMC4_SCU_PMTSR_OFFSET 0x001c /* Parity Memory Test Select Register */ + +/* Trap Control Registers */ + +#define XMC4_SCU_TRAPSTAT_OFFSET 0x0000 /* Trap Status Register */ +#define XMC4_SCU_TRAPRAW_OFFSET 0x0004 /* Trap Raw Status Register */ +#define XMC4_SCU_TRAPDIS_OFFSET 0x0008 /* Trap Mask Register */ +#define XMC4_SCU_TRAPCLR_OFFSET 0x000c /* Trap Clear Register */ +#define XMC4_SCU_TRAPSET_OFFSET 0x0010 /* Trap Set Register */ + +/* Power Control SCU Registers */ + +#define XMC4_SCU_PWRSTAT_OFFSET 0x0000 /* Power Status Register */ +#define XMC4_SCU_PWRSET_OFFSET 0x0004 /* Power Set Control Register */ +#define XMC4_SCU_PWRCLR_OFFSET 0x0008 /* Power Clear Control Register */ +#define XMC4_SCU_EVRSTAT_OFFSET 0x0010 /* EVR Status Register */ +#define XMC4_SCU_EVRVADCSTAT_OFFSET 0x0014 /* EVR VADC Status Register */ +#define XMC4_SCU_PWRMON_OFFSET 0x002c /* Power Monitor Value */ + +/* Hibernation SCU Registers */ + +#define XMC4_SCU_HDSTAT_OFFSET 0x0000 /* Hibernate Domain Status Register */ +#define XMC4_SCU_HDCLR_OFFSET 0x0004 /* Hibernate Domain Status Clear Register */ +#define XMC4_SCU_HDSET_OFFSET 0x0008 /* Hibernate Domain Status Set Register */ +#define XMC4_SCU_HDCR_OFFSET 0x000c /* Hibernate Domain Control Register */ +#define XMC4_SCU_OSCSICTRL_OFFSET 0x0014 /* Internal 32.768 kHz Clock Source Control Register */ +#define XMC4_SCU_OSCULSTAT_OFFSET 0x0018 /* OSC_ULP Status Register */ +#define XMC4_SCU_OSCULCTRL_OFFSET 0x001c /* OSC_ULP Control Register */ + +/* Reset SCU Registers */ + +#define XMC4_SCU_RSTSTAT_OFFSET 0x0000 /* System Reset Status */ +#define XMC4_SCU_RSTSET_OFFSET 0x0004 /* Reset Set Register */ +#define XMC4_SCU_RSTCLR_OFFSET 0x0008 /* Reset Clear Register */ +#define XMC4_SCU_PRSTAT0_OFFSET 0x000c /* Peripheral Reset Status Register 0 */ +#define XMC4_SCU_PRSET0_OFFSET 0x0010 /* Peripheral Reset Set Register 0 */ +#define XMC4_SCU_PRCLR0_OFFSET 0x0014 /* Peripheral Reset Clear Register 0 */ +#define XMC4_SCU_PRSTAT1_OFFSET 0x0018 /* Peripheral Reset Status Register 1 */ +#define XMC4_SCU_PRSET1_OFFSET 0x001c /* Peripheral Reset Set Register 1 */ +#define XMC4_SCU_PRCLR1_OFFSET 0x0020 /* Peripheral Reset Clear Register 1 */ +#define XMC4_SCU_PRSTAT2_OFFSET 0x0024 /* Peripheral Reset Status Register 2 */ +#define XMC4_SCU_PRSET2_OFFSET 0x0028 /* Peripheral Reset Set Register 2 */ +#define XMC4_SCU_PRCLR2_OFFSET 0x002c /* Peripheral Reset Clear Register 2 */ +#define XMC4_SCU_PRSTAT3_OFFSET 0x0030 /* Peripheral Reset Status Register 3 */ +#define XMC4_SCU_PRSET3_OFFSET 0x0034 /* Peripheral Reset Set Register 3 */ +#define XMC4_SCU_PRCLR3_OFFSET 0x0038 /* Peripheral Reset Clear Register 3 */ + +/* Clock Control SCU Registers */ + +#define XMC4_SCU_CLKSTAT_OFFSET 0x0000 /* Clock Status Register */ +#define XMC4_SCU_CLKSET_OFFSET 0x0004 /* Clock Set Control Register */ +#define XMC4_SCU_CLKCLR_OFFSET 0x0008 /* Clock clear Control Register */ +#define XMC4_SCU_SYSCLKCR_OFFSET 0x000c /* System Clock Control */ +#define XMC4_SCU_CPUCLKCR_OFFSET 0x0010 /* CPU Clock Control */ +#define XMC4_SCU_PBCLKCR_OFFSET 0x0014 /* Peripheral Bus Clock Control */ +#define XMC4_SCU_USBCLKCR_OFFSET 0x0018 /* USB Clock Control */ +#define XMC4_SCU_EBUCLKCR_OFFSET 0x001c /* EBU Clock Control */ +#define XMC4_SCU_CCUCLKCR_OFFSET 0x0020 /* CCU Clock Control */ +#define XMC4_SCU_WDTCLKCR_OFFSET 0x0024 /* WDT Clock Control */ +#define XMC4_SCU_EXTCLKCR_OFFSET 0x0028 /* External clock Control Register */ +#define XMC4_SCU_SLEEPCR_OFFSET 0x0030 /* Sleep Control Register */ +#define XMC4_SCU_DSLEEPCR_OFFSET 0x0034 /* Deep Sleep Control Register */ +#define XMC4_SCU_CGATSTAT0_OFFSET 0x0040 /* Peripheral 0 Clock Gating Status */ +#define XMC4_SCU_CGATSET0_OFFSET 0x0044 /* Peripheral 0 Clock Gating Set */ +#define XMC4_SCU_CGATCLR0_OFFSET 0x0048 /* Peripheral 0 Clock Gating Clear */ +#define XMC4_SCU_CGATSTAT1_OFFSET 0x004c /* Peripheral 1 Clock Gating Status */ +#define XMC4_SCU_CGATSET1_OFFSET 0x0050 /* Peripheral 1 Clock Gating Set */ +#define XMC4_SCU_CGATCLR1_OFFSET 0x0054 /* Peripheral 1 Clock Gating Clear */ +#define XMC4_SCU_CGATSTAT2_OFFSET 0x0058 /* Peripheral 2 Clock Gating Status */ +#define XMC4_SCU_CGATSET2_OFFSET 0x005c /* Peripheral 2 Clock Gating Set */ +#define XMC4_SCU_CGATCLR2_OFFSET 0x0060 /* Peripheral 2 Clock Gating Clear */ +#define XMC4_SCU_CGATSTAT3_OFFSET 0x0064 /* Peripheral 3 Clock Gating Status */ +#define XMC4_SCU_CGATSET3_OFFSET 0x0068 /* Peripheral 3 Clock Gating Set */ +#define XMC4_SCU_CGATCLR3_OFFSET 0x006c /* Peripheral 3 Clock Gating Clear */ + +/* Oscillator Control SCU Registers */ + +#define XMC4_OCU_OSCHPSTAT_OFFSET 0x0000 /* OSC_HP Status Register */ +#define XMC4_OCU_OSCHPCTRL_OFFSET 0x0004 /* OSC_HP Control Register */ +#define XMC4_OCU_CLKCALCONST_OFFSET 0x000c /* Clock Calibration Constant Register */ + +/* PLL Control SCU Registers */ + +#define XMC4_SCU_PLLSTAT_OFFSET 0x0000 /* System PLL Status Register */ +#define XMC4_SCU_PLLCON0_OFFSET 0x0004 /* System PLL Configuration 0 Register */ +#define XMC4_SCU_PLLCON1_OFFSET 0x0008 /* System PLL Configuration 1 Register */ +#define XMC4_SCU_PLLCON2_OFFSET 0x000c /* System PLL Configuration 2 Register */ +#define XMC4_SCU_USBPLLSTAT_OFFSET 0x0010 /* USB PLL Status Register */ +#define XMC4_SCU_USBPLLCON_OFFSET 0x0014 /* USB PLL Control Register */ +#define XMC4_SCU_CLKMXSTAT_OFFSET 0x0028 /* Clock Multiplexing Status Register */ /* Register Addresses ***************************************************************/ - -#define XMC4_GCU_BASE (XMC4_SCU_BASE+XMC4_GCU_OFFSET) -#define XMC4_PCU_BASE (XMC4_SCU_BASE+XMC4_PCU_OFFSET) -#define XMC4_HCU_BASE (XMC4_SCU_BASE+XMC4_HCU_OFFSET) -#define XMC4_RCU_BASE (XMC4_SCU_BASE+XMC4_RCU_OFFSET) -#define XMC4_CCU_BASE (XMC4_SCU_BASE+XMC4_CCU_OFFSET) - /* General SCU Registers */ -#define XMC4_GCU_ID (XMC4_GCU_BASE+XMC4_GCU_ID_OFFSET) -#define XMC4_GCU_IDCHIP (XMC4_GCU_BASE+XMC4_GCU_IDCHIP_OFFSET) -#define XMC4_GCU_IDMANUF (XMC4_GCU_BASE+XMC4_GCU_IDMANUF_OFFSET) -#define XMC4_GCU_STCON (XMC4_GCU_BASE+XMC4_GCU_STCON_OFFSET) -#define XMC4_GCU_GPR0 (XMC4_GCU_BASE+XMC4_GCU_GPR0_OFFSET) -#define XMC4_GCU_GPR1 (XMC4_GCU_BASE+XMC4_GCU_GPR1_OFFSET) -#define XMC4_GCU_ETH0CON (XMC4_GCU_BASE+XMC4_GCU_ETH0CON_OFFSET) -#define XMC4_GCU_CCUCON (XMC4_GCU_BASE+XMC4_GCU_CCUCON_OFFSET) -#define XMC4_GCU_SRSTAT (XMC4_GCU_BASE+XMC4_GCU_SRSTAT_OFFSET) -#define XMC4_GCU_SRRAW (XMC4_GCU_BASE+XMC4_GCU_SRRAW_OFFSET) -#define XMC4_GCU_SRMSK (XMC4_GCU_BASE+XMC4_GCU_SRMSK_OFFSET) -#define XMC4_GCU_SRCLR (XMC4_GCU_BASE+XMC4_GCU_SRCLR_OFFSET) -#define XMC4_GCU_SRSET (XMC4_GCU_BASE+XMC4_GCU_SRSET_OFFSET) -#define XMC4_GCU_NMIREQEN (XMC4_GCU_BASE+XMC4_GCU_NMIREQEN_OFFSET) -#define XMC4_GCU_DTSCON (XMC4_GCU_BASE+XMC4_GCU_DTSCON_OFFSET) -#define XMC4_GCU_DTSSTAT (XMC4_GCU_BASE+XMC4_GCU_DTSSTAT_OFFSET) -#define XMC4_GCU_SDMMCDEL (XMC4_GCU_BASE+XMC4_GCU_SDMMCDEL_OFFSET) -#define XMC4_GCU_G0ORCEN (XMC4_GCU_BASE+XMC4_GCU_G0ORCEN_OFFSET) -#define XMC4_GCU_G1ORCEN (XMC4_GCU_BASE+XMC4_GCU_G1ORCEN_OFFSET) -#define XMC4_GCU_MIRRSTS (XMC4_GCU_BASE+XMC4_GCU_MIRRSTS_OFFSET) -#define XMC4_GCU_RMACR (XMC4_GCU_BASE+XMC4_GCU_RMACR_OFFSET) -#define XMC4_GCU_RMADATA (XMC4_GCU_BASE+XMC4_GCU_RMADATA_OFFSET) -#define XMC4_GCU_PEEN (XMC4_GCU_BASE+XMC4_GCU_PEEN_OFFSET) -#define XMC4_GCU_MCHKCON (XMC4_GCU_BASE+XMC4_GCU_MCHKCON_OFFSET) -#define XMC4_GCU_PETE (XMC4_GCU_BASE+XMC4_GCU_PETE_OFFSET) -#define XMC4_GCU_PERSTEN (XMC4_GCU_BASE+XMC4_GCU_PERSTEN_OFFSET) -#define XMC4_GCU_PEFLAG (XMC4_GCU_BASE+XMC4_GCU_PEFLAG_OFFSET) -#define XMC4_GCU_PMTPR (XMC4_GCU_BASE+XMC4_GCU_PMTPR_OFFSET) -#define XMC4_GCU_PMTSR (XMC4_GCU_BASE+XMC4_GCU_PMTSR_OFFSET) -#define XMC4_GCU_TRAPSTAT (XMC4_GCU_BASE+XMC4_GCU_TRAPSTAT_OFFSET) -#define XMC4_GCU_TRAPRAW (XMC4_GCU_BASE+XMC4_GCU_TRAPRAW_OFFSET) -#define XMC4_GCU_TRAPDIS (XMC4_GCU_BASE+XMC4_GCU_TRAPDIS_OFFSET) -#define XMC4_GCU_TRAPCLR (XMC4_GCU_BASE+XMC4_GCU_TRAPCLR_OFFSET) -#define XMC4_GCU_TRAPSET (XMC4_GCU_BASE+XMC4_GCU_TRAPSET_OFFSET) +#define XMC4_SCU_ID (XMC4_SCU_GENERAL_BASE+XMC4_SCU_ID_OFFSET) +#define XMC4_SCU_IDCHIP (XMC4_SCU_GENERAL_BASE+XMC4_SCU_IDCHIP_OFFSET) +#define XMC4_SCU_IDMANUF (XMC4_SCU_GENERAL_BASE+XMC4_SCU_IDMANUF_OFFSET) +#define XMC4_SCU_STCON (XMC4_SCU_GENERAL_BASE+XMC4_SCU_STCON_OFFSET) +#define XMC4_SCU_GPR0 (XMC4_SCU_GENERAL_BASE+XMC4_SCU_GPR0_OFFSET) +#define XMC4_SCU_GPR1 (XMC4_SCU_GENERAL_BASE+XMC4_SCU_GPR1_OFFSET) +#define XMC4_SCU_ETH0CON (XMC4_SCU_GENERAL_BASE+XMC4_SCU_ETH0CON_OFFSET) +#define XMC4_SCU_CCUCON (XMC4_SCU_GENERAL_BASE+XMC4_SCU_CCUCON_OFFSET) +#define XMC4_SCU_DTSCON (XMC4_SCU_GENERAL_BASE+XMC4_SCU_DTSCON_OFFSET) +#define XMC4_SCU_DTSSTAT (XMC4_SCU_GENERAL_BASE+XMC4_SCU_DTSSTAT_OFFSET) +#define XMC4_SCU_SDMMCDEL (XMC4_SCU_GENERAL_BASE+XMC4_SCU_SDMMCDEL_OFFSET) +#define XMC4_SCU_G0ORCEN (XMC4_SCU_GENERAL_BASE+XMC4_SCU_G0ORCEN_OFFSET) +#define XMC4_SCU_G1ORCEN (XMC4_SCU_GENERAL_BASE+XMC4_SCU_G1ORCEN_OFFSET) +#define XMC4_SCU_MIRRSTS (XMC4_SCU_GENERAL_BASE+XMC4_SCU_MIRRSTS_OFFSET) +#define XMC4_SCU_RMACR (XMC4_SCU_GENERAL_BASE+XMC4_SCU_RMACR_OFFSET) +#define XMC4_SCU_RMADATA (XMC4_SCU_GENERAL_BASE+XMC4_SCU_RMADATA_OFFSET) -/* PCU Registers */ +/* Ethernet Control SCU Registers */ -#define XMC4_PCU_PWRSTAT (XMC4_PCU_BASE+XMC4_PCU_PWRSTAT_OFFSET) -#define XMC4_PCU_PWRSET (XMC4_PCU_BASE+XMC4_PCU_PWRSET_OFFSET) -#define XMC4_PCU_PWRCLR (XMC4_PCU_BASE+XMC4_PCU_PWRCLR_OFFSET) -#define XMC4_PCU_EVRSTAT (XMC4_PCU_BASE+XMC4_PCU_EVRSTAT_OFFSET) -#define XMC4_PCU_EVRVADCSTAT (XMC4_PCU_BASE+XMC4_PCU_EVRVADCSTAT_OFFSET) -#define XMC4_PCU_PWRMON (XMC4_PCU_BASE+XMC4_PCU_PWRMON_OFFSET) +#define XMC4_SCU_ETHCON (XMC4_ETH0_CON_BASE+XMC4_SCU_ETHCON_OFFSET) -/* HCU Registers */ +/* Parity Control Registers */ -#define XMC4_HCU_HDSTAT (XMC4_HCU_BASE+XMC4_HCU_HDSTAT_OFFSET) -#define XMC4_HCU_HDCLR (XMC4_HCU_BASE+XMC4_HCU_HDCLR_OFFSET) -#define XMC4_HCU_HDSET (XMC4_HCU_BASE+XMC4_HCU_HDSET_OFFSET) -#define XMC4_HCU_HDCR (XMC4_HCU_BASE+XMC4_HCU_HDCR_OFFSET) -#define XMC4_HCU_OSCSICTRL (XMC4_HCU_BASE+XMC4_HCU_OSCSICTRL_OFFSET) -#define XMC4_HCU_OSCULSTAT (XMC4_HCU_BASE+XMC4_HCU_OSCULSTAT_OFFSET) -#define XMC4_HCU_OSCULCTRL (XMC4_HCU_BASE+XMC4_HCU_OSCULCTRL_OFFSET) +#define XMC4_SCU_PEEN (XMC4_SCU_PARITY_BASE+XMC4_SCU_PEEN_OFFSET) +#define XMC4_SCU_MCHKCON (XMC4_SCU_PARITY_BASE+XMC4_SCU_MCHKCON_OFFSET) +#define XMC4_SCU_PETE (XMC4_SCU_PARITY_BASE+XMC4_SCU_PETE_OFFSET) +#define XMC4_SCU_PERSTEN (XMC4_SCU_PARITY_BASE+XMC4_SCU_PERSTEN_OFFSET) +#define XMC4_SCU_PEFLAG (XMC4_SCU_PARITY_BASE+XMC4_SCU_PEFLAG_OFFSET) +#define XMC4_SCU_PMTPR (XMC4_SCU_PARITY_BASE+XMC4_SCU_PMTPR_OFFSET) +#define XMC4_SCU_PMTSR (XMC4_SCU_PARITY_BASE+XMC4_SCU_PMTSR_OFFSET) -/* RCU Registers */ +/* Trap Control Registers */ -#define XMC4_RCU_RSTSTAT (XMC4_RCU_BASE+XMC4_RCU_RSTSTAT_OFFSET) -#define XMC4_RCU_RSTSET (XMC4_RCU_BASE+XMC4_RCU_RSTSET_OFFSET) -#define XMC4_RCU_RSTCLR (XMC4_RCU_BASE+XMC4_RCU_RSTCLR_OFFSET) -#define XMC4_RCU_PRSTAT0 (XMC4_RCU_BASE+XMC4_RCU_PRSTAT0_OFFSET) -#define XMC4_RCU_PRSET0 (XMC4_RCU_BASE+XMC4_RCU_PRSET0_OFFSET) -#define XMC4_RCU_PRCLR0 (XMC4_RCU_BASE+XMC4_RCU_PRCLR0_OFFSET) -#define XMC4_RCU_PRSTAT1 (XMC4_RCU_BASE+XMC4_RCU_PRSTAT1_OFFSET) -#define XMC4_RCU_PRSET1 (XMC4_RCU_BASE+XMC4_RCU_PRSET1_OFFSET) -#define XMC4_RCU_PRCLR1 (XMC4_RCU_BASE+XMC4_RCU_PRCLR1_OFFSET) -#define XMC4_RCU_PRSTAT2 (XMC4_RCU_BASE+XMC4_RCU_PRSTAT2_OFFSET) -#define XMC4_RCU_PRSET2 (XMC4_RCU_BASE+XMC4_RCU_PRSET2_OFFSET) -#define XMC4_RCU_PRCLR2 (XMC4_RCU_BASE+XMC4_RCU_PRCLR2_OFFSET) -#define XMC4_RCU_PRSTAT3 (XMC4_RCU_BASE+XMC4_RCU_PRSTAT3_OFFSET) -#define XMC4_RCU_PRSET3 (XMC4_RCU_BASE+XMC4_RCU_PRSET3_OFFSET) -#define XMC4_RCU_PRCLR3 (XMC4_RCU_BASE+XMC4_RCU_PRCLR3_OFFSET) +#define XMC4_SCU_TRAPSTAT (XMC4_SCU_TRAP_BASE+XMC4_SCU_TRAPSTAT_OFFSET) +#define XMC4_SCU_TRAPRAW (XMC4_SCU_TRAP_BASE+XMC4_SCU_TRAPRAW_OFFSET) +#define XMC4_SCU_TRAPDIS (XMC4_SCU_TRAP_BASE+XMC4_SCU_TRAPDIS_OFFSET) +#define XMC4_SCU_TRAPCLR (XMC4_SCU_TRAP_BASE+XMC4_SCU_TRAPCLR_OFFSET) +#define XMC4_SCU_TRAPSET (XMC4_SCU_TRAP_BASE+XMC4_SCU_TRAPSET_OFFSET) -/* CCU Registers */ +/* Ethernet Control SCU Resters */ -#define XMC4_CCU_CLKSTAT (XMC4_CCU_BASE+XMC4_CCU_CLKSTAT_OFFSET) -#define XMC4_CCU_CLKSET (XMC4_CCU_BASE+XMC4_CCU_CLKSET_OFFSET) -#define XMC4_CCU_CLKCLR (XMC4_CCU_BASE+XMC4_CCU_CLKCLR_OFFSET) -#define XMC4_CCU_SYSCLKCR (XMC4_CCU_BASE+XMC4_CCU_SYSCLKCR_OFFSET) -#define XMC4_CCU_CPUCLKCR (XMC4_CCU_BASE+XMC4_CCU_CPUCLKCR_OFFSET) -#define XMC4_CCU_PBCLKCR (XMC4_CCU_BASE+XMC4_CCU_PBCLKCR_OFFSET) -#define XMC4_CCU_USBCLKCR (XMC4_CCU_BASE+XMC4_CCU_USBCLKCR_OFFSET) -#define XMC4_CCU_EBUCLKCR (XMC4_CCU_BASE+XMC4_CCU_EBUCLKCR_OFFSET) -#define XMC4_CCU_CCUCLKCR (XMC4_CCU_BASE+XMC4_CCU_CCUCLKCR_OFFSET) -#define XMC4_CCU_WDTCLKCR (XMC4_CCU_BASE+XMC4_CCU_WDTCLKCR_OFFSET) -#define XMC4_CCU_EXTCLKCR (XMC4_CCU_BASE+XMC4_CCU_EXTCLKCR_OFFSET) -#define XMC4_CCU_SLEEPCR (XMC4_CCU_BASE+XMC4_CCU_SLEEPCR_OFFSET) -#define XMC4_CCU_DSLEEPCR (XMC4_CCU_BASE+XMC4_CCU_DSLEEPCR_OFFSET) -#define XMC4_CCU_OSCHPSTAT (XMC4_CCU_BASE+XMC4_CCU_OSCHPSTAT_OFFSET) -#define XMC4_CCU_OSCHPCTRL (XMC4_CCU_BASE+XMC4_CCU_OSCHPCTRL_OFFSET) -#define XMC4_CCU_CLKCALCONST (XMC4_CCU_BASE+XMC4_CCU_CLKCALCONST_OFFSET) -#define XMC4_CCU_PLLSTAT (XMC4_CCU_BASE+XMC4_CCU_PLLSTAT_OFFSET) -#define XMC4_CCU_PLLCON0 (XMC4_CCU_BASE+XMC4_CCU_PLLCON0_OFFSET) -#define XMC4_CCU_PLLCON1 (XMC4_CCU_BASE+XMC4_CCU_PLLCON1_OFFSET) -#define XMC4_CCU_PLLCON2 (XMC4_CCU_BASE+XMC4_CCU_PLLCON2_OFFSET) -#define XMC4_CCU_USBPLLSTAT (XMC4_CCU_BASE+XMC4_CCU_USBPLLSTAT_OFFSET) -#define XMC4_CCU_USBPLLCON (XMC4_CCU_BASE+XMC4_CCU_USBPLLCON_OFFSET) -#define XMC4_CCU_CLKMXSTAT (XMC4_CCU_BASE+XMC4_CCU_CLKMXSTAT_OFFSET) +#define XMC4_SCU_ETHCON_OFFSET 0x0000 /* Ethernet 0 Port Control Register */ +#define XMC4_SCU_ETHCON_OFFSET 0x0000 /* Ethernet 0 Port Control Register */ + +/* Interrupt Control SCU Registers */ + +#define XMC4_SCU_SRSTAT (XMC4_SCU_INTERRUPT_BASE+XMC4_SCU_SRSTAT_OFFSET) +#define XMC4_SCU_SRRAW (XMC4_SCU_INTERRUPT_BASE+XMC4_SCU_SRRAW_OFFSET) +#define XMC4_SCU_SRMSK (XMC4_SCU_INTERRUPT_BASE+XMC4_SCU_SRMSK_OFFSET) +#define XMC4_SCU_SRCLR (XMC4_SCU_INTERRUPT_BASE+XMC4_SCU_SRCLR_OFFSET) +#define XMC4_SCU_SRSET (XMC4_SCU_INTERRUPT_BASE+XMC4_SCU_SRSET_OFFSET) +#define XMC4_SCU_NMIREQEN (XMC4_SCU_INTERRUPT_BASE+XMC4_SCU_NMIREQEN_OFFSET) + +/* SDMMC Control SCU Registers */ + +#define XMC4_SCU_SDMMCCON (XMC4_SDMMC_CON_BASE+XMC4_SCU_SDMMCCON_OFFSET) + +/* Power control SCU Registers */ + +#define XMC4_SCU_PWRSTAT (XMC4_SCU_POWER_BASE+XMC4_SCU_PWRSTAT_OFFSET) +#define XMC4_SCU_PWRSET (XMC4_SCU_POWER_BASE+XMC4_SCU_PWRSET_OFFSET) +#define XMC4_SCU_PWRCLR (XMC4_SCU_POWER_BASE+XMC4_SCU_PWRCLR_OFFSET) +#define XMC4_SCU_EVRSTAT (XMC4_SCU_POWER_BASE+XMC4_SCU_EVRSTAT_OFFSET) +#define XMC4_SCU_EVRVADCSTAT (XMC4_SCU_POWER_BASE+XMC4_SCU_EVRVADCSTAT_OFFSET) +#define XMC4_SCU_PWRMON (XMC4_SCU_POWER_BASE+XMC4_SCU_PWRMON_OFFSET) + +/* Hibernation SCU Registers */ + +#define XMC4_SCU_HDSTAT (XMC4_SCU_HIBERNATE_BASE+XMC4_SCU_HDSTAT_OFFSET) +#define XMC4_SCU_HDCLR (XMC4_SCU_HIBERNATE_BASE+XMC4_SCU_HDCLR_OFFSET) +#define XMC4_SCU_HDSET (XMC4_SCU_HIBERNATE_BASE+XMC4_SCU_HDSET_OFFSET) +#define XMC4_SCU_HDCR (XMC4_SCU_HIBERNATE_BASE+XMC4_SCU_HDCR_OFFSET) +#define XMC4_SCU_OSCSICTRL (XMC4_SCU_HIBERNATE_BASE+XMC4_SCU_OSCSICTRL_OFFSET) +#define XMC4_SCU_OSCULSTAT (XMC4_SCU_HIBERNATE_BASE+XMC4_SCU_OSCULSTAT_OFFSET) +#define XMC4_SCU_OSCULCTRL (XMC4_SCU_HIBERNATE_BASE+XMC4_SCU_OSCULCTRL_OFFSET) + +/* Reset SCU Registers */ + +#define XMC4_SCU_RSTSTAT (XMC4_SCU_RESET_BASE+XMC4_SCU_RSTSTAT_OFFSET) +#define XMC4_SCU_RSTSET (XMC4_SCU_RESET_BASE+XMC4_SCU_RSTSET_OFFSET) +#define XMC4_SCU_RSTCLR (XMC4_SCU_RESET_BASE+XMC4_SCU_RSTCLR_OFFSET) +#define XMC4_SCU_PRSTAT0 (XMC4_SCU_RESET_BASE+XMC4_SCU_PRSTAT0_OFFSET) +#define XMC4_SCU_PRSET0 (XMC4_SCU_RESET_BASE+XMC4_SCU_PRSET0_OFFSET) +#define XMC4_SCU_PRCLR0 (XMC4_SCU_RESET_BASE+XMC4_SCU_PRCLR0_OFFSET) +#define XMC4_SCU_PRSTAT1 (XMC4_SCU_RESET_BASE+XMC4_SCU_PRSTAT1_OFFSET) +#define XMC4_SCU_PRSET1 (XMC4_SCU_RESET_BASE+XMC4_SCU_PRSET1_OFFSET) +#define XMC4_SCU_PRCLR1 (XMC4_SCU_RESET_BASE+XMC4_SCU_PRCLR1_OFFSET) +#define XMC4_SCU_PRSTAT2 (XMC4_SCU_RESET_BASE+XMC4_SCU_PRSTAT2_OFFSET) +#define XMC4_SCU_PRSET2 (XMC4_SCU_RESET_BASE+XMC4_SCU_PRSET2_OFFSET) +#define XMC4_SCU_PRCLR2 (XMC4_SCU_RESET_BASE+XMC4_SCU_PRCLR2_OFFSET) +#define XMC4_SCU_PRSTAT3 (XMC4_SCU_RESET_BASE+XMC4_SCU_PRSTAT3_OFFSET) +#define XMC4_SCU_PRSET3 (XMC4_SCU_RESET_BASE+XMC4_SCU_PRSET3_OFFSET) +#define XMC4_SCU_PRCLR3 (XMC4_SCU_RESET_BASE+XMC4_SCU_PRCLR3_OFFSET) + +/* Clock Control SCU Registers */ + +#define XMC4_SCU_CLKSTAT (XMC4_SCU_CLK_BASE+XMC4_SCU_CLKSTAT_OFFSET) +#define XMC4_SCU_CLKSET (XMC4_SCU_CLK_BASE+XMC4_SCU_CLKSET_OFFSET) +#define XMC4_SCU_CLKCLR (XMC4_SCU_CLK_BASE+XMC4_SCU_CLKCLR_OFFSET) +#define XMC4_SCU_SYSCLKCR (XMC4_SCU_CLK_BASE+XMC4_SCU_SYSCLKCR_OFFSET) +#define XMC4_SCU_CPUCLKCR (XMC4_SCU_CLK_BASE+XMC4_SCU_CPUCLKCR_OFFSET) +#define XMC4_SCU_PBCLKCR (XMC4_SCU_CLK_BASE+XMC4_SCU_PBCLKCR_OFFSET) +#define XMC4_SCU_USBCLKCR (XMC4_SCU_CLK_BASE+XMC4_SCU_USBCLKCR_OFFSET) +#define XMC4_SCU_EBUCLKCR (XMC4_SCU_CLK_BASE+XMC4_SCU_EBUCLKCR_OFFSET) +#define XMC4_SCU_CCUCLKCR (XMC4_SCU_CLK_BASE+XMC4_SCU_CCUCLKCR_OFFSET) +#define XMC4_SCU_WDTCLKCR (XMC4_SCU_CLK_BASE+XMC4_SCU_WDTCLKCR_OFFSET) +#define XMC4_SCU_EXTCLKCR (XMC4_SCU_CLK_BASE+XMC4_SCU_EXTCLKCR_OFFSET) +#define XMC4_SCU_SLEEPCR (XMC4_SCU_CLK_BASE+XMC4_SCU_SLEEPCR_OFFSET) +#define XMC4_SCU_DSLEEPCR (XMC4_SCU_CLK_BASE+XMC4_SCU_DSLEEPCR_OFFSET) +#define XMC4_SCU_CGATSTAT0 (XMC4_SCU_CLK_BASE+XMC4_SCU_CGATSTAT0_OFFSET) +#define XMC4_SCU_CGATSET0 (XMC4_SCU_CLK_BASE+XMC4_SCU_CGATSET0_OFFSET) +#define XMC4_SCU_CGATCLR0 (XMC4_SCU_CLK_BASE+XMC4_SCU_CGATCLR0_OFFSET) +#define XMC4_SCU_CGATSTAT1 (XMC4_SCU_CLK_BASE+XMC4_SCU_CGATSTAT1_OFFSET) +#define XMC4_SCU_CGATSET1 (XMC4_SCU_CLK_BASE+XMC4_SCU_CGATSET1_OFFSET) +#define XMC4_SCU_CGATCLR1 (XMC4_SCU_CLK_BASE+XMC4_SCU_CGATCLR1_OFFSET) +#define XMC4_SCU_CGATSTAT2 (XMC4_SCU_CLK_BASE+XMC4_SCU_CGATSTAT2_OFFSET) +#define XMC4_SCU_CGATSET2 (XMC4_SCU_CLK_BASE+XMC4_SCU_CGATSET2_OFFSET +#define XMC4_SCU_CGATCLR2 (XMC4_SCU_CLK_BASE+XMC4_SCU_CGATCLR2_OFFSET +#define XMC4_SCU_CGATSTAT3 (XMC4_SCU_CLK_BASE+XMC4_SCU_CGATSTAT3_OFFSET +#define XMC4_SCU_CGATSET3 (XMC4_SCU_CLK_BASE+XMC4_SCU_CGATSET3_OFFSET +#define XMC4_SCU_CGATCLR3 (XMC4_SCU_CLK_BASE+XMC4_SCU_CGATCLR3_OFFSET_ + +/* Oscillator Control SCU Registers */ + +#define XMC4_OSCU_OSCHPSTAT (XMC4_SCU_OSC_BASE+XMC4_OSCU_OSCHPSTAT_OFFSET) +#define XMC4_OSCU_OSCHPCTRL (XMC4_SCU_OSC_BASE+XMC4_OSCU_OSCHPCTRL_OFFSET) +#define XMC4_OSCU_CLKCALCONST (XMC4_SCU_OSC_BASE+XMC4_OSCU_CLKCALCONST_OFFSET) + +/* PLL Control SCU Registers */ + +#define XMC4_SCU_PLLSTAT (XMC4_SCU_PLL_BASE+XMC4_SCU_PLLSTAT_OFFSET) +#define XMC4_SCU_PLLCON0 (XMC4_SCU_PLL_BASE+XMC4_SCU_PLLCON0_OFFSET) +#define XMC4_SCU_PLLCON1 (XMC4_SCU_PLL_BASE+XMC4_SCU_PLLCON1_OFFSET) +#define XMC4_SCU_PLLCON2 (XMC4_SCU_PLL_BASE+XMC4_SCU_PLLCON2_OFFSET) +#define XMC4_SCU_USBPLLSTAT (XMC4_SCU_PLL_BASE+XMC4_SCU_USBPLLSTAT_OFFSET) +#define XMC4_SCU_USBPLLCON (XMC4_SCU_PLL_BASE+XMC4_SCU_USBPLLCON_OFFSET) +#define XMC4_SCU_CLKMXSTAT (XMC4_SCU_PLL_BASE+XMC4_SCU_CLKMXSTAT_OFFSET) /* Register Bit-Field Definitions ***************************************************/ /* General SCU Registers */ /* Module Identification Register */ -#define GCU_ID_ +#define SCU_ID_ /* Chip ID */ -#define GCU_IDCHIP_ +#define SCU_IDCHIP_ /* Manufactory ID */ -#define GCU_IDMANUF_ +#define SCU_IDMANUF_ /* Start-up Control */ -#define GCU_STCON_ +#define SCU_STCON_ /* General Purpose Register 0 */ -#define GCU_GPR0_ +#define SCU_GPR0_ /* General Purpose Register 1 */ -#define GCU_GPR1_ +#define SCU_GPR1_ /* Ethernet 0 Port Control */ -#define GCU_ETH0CON_ +#define SCU_ETH0CON_ /* CCUx Global Start Control Register */ -#define GCU_CCUCON_ -/* Service Request Status */ -#define GCU_SRSTAT_ -/* RAW Service Request Status */ -#define GCU_SRRAW_ -/* Service Request Mask */ -#define GCU_SRMSK_ -/* Service Request Clear */ -#define GCU_SRCLR_ -/* Service Request Set */ -#define GCU_SRSET_ -/* Enable Promoting Events to NMI Request */ -#define GCU_NMIREQEN_ +#define SCU_CCUCON_ /* DTS Control */ -#define GCU_DTSCON_ +#define SCU_DTSCON_ /* DTS Status */ -#define GCU_DTSSTAT_ -/* SD-MMC Delay Control Register */ -#define GCU_SDMMCDEL_ +#define SCU_DTSSTAT_ +/* SD-MMC Delay Control Register */ +#define SCU_SDMMCDEL_ /* Out-Of-Range Comparator Enable Register 0 */ -#define GCU_G0ORCEN_ +#define SCU_G0ORCEN_ /* Out-Of-Range Comparator Enable Register 1 */ -#define GCU_G1ORCEN_ +#define SCU_G1ORCEN_ /* Mirror Update Status Register */ -#define GCU_MIRRSTS_ -/* Retention Memory Access Control Register */ -#define GCU_RMACR_ -/* Retention Memory Access Data Register */ -#define GCU_RMADATA_ -/* Parity Error Enable Register */ -#define GCU_PEEN_ -/* Memory Checking Control Register */ -#define GCU_MCHKCON_ -/* Parity Error Trap Enable Register */ -#define GCU_PETE_ -/* Reset upon Parity Error Enable Register */ -#define GCU_PERSTEN_ -/* Parity Error Control Register */ -#define GCU_PEFLAG_ -/* Parity Memory Test Pattern Register */ -#define GCU_PMTPR_ -/* Parity Memory Test Select Register */ -#define GCU_PMTSR_ -/* Trap Status Register */ -#define GCU_TRAPSTAT_ -/* Trap Raw Status Register */ -#define GCU_TRAPRAW_ -/* Trap Mask Register */ -#define GCU_TRAPDIS_ -/* Trap Clear Register */ -#define GCU_TRAPCLR_ -/* Trap Set Register */ -#define GCU_TRAPSET_ +#define SCU_MIRRSTS_ -/* PCU Registers */ +/* Ethernet Control SCU Resters */ + +/* Ethernet 0 Port Control Register */ +#define SCU_ETHCON_ + +/* Interrupt Control SCU Registers */ + +/* Service Request Status */ +#define SCU_SRSTAT_ +/* RAW Service Request Status */ +#define SCU_SRRAW_ +/* Service Request Mask */ +#define SCU_SRMSK_ +/* Service Request Clear */ +#define SCU_SRCLR_ +/* Service Request Set */ +#define SCU_SRSET_ +/* Enable Promoting Events to NMI Request */ +#define SCU_NMIREQEN_ +/* Retention Memory Access Control Register */ +#define SCU_RMACR_ +/* Retention Memory Access Data Register */ +#define SCU_RMADATA_ +/* Parity Error Enable Register */ + +/* SDMMC Control SCU Registers */ + +/* SDMMC Configuration */ +#define SCU_SDMMCCON_ + +/* Parity Control Registers */ + +#define SCU_PEEN_ +/* Memory Checking Control Register */ +#define SCU_MCHKCON_ +/* Parity Error Trap Enable Register */ +#define SCU_PETE_ +/* Reset upon Parity Error Enable Register */ +#define SCU_PERSTEN_ +/* Parity Error Control Register */ +#define SCU_PEFLAG_ +/* Parity Memory Test Pattern Register */ +#define SCU_PMTPR_ +/* Parity Memory Test Select Register */ +#define SCU_PMTSR_ + +/* Trap Control Registers */ + +/* Trap Status Register */ +#define SCU_TRAPSTAT_ +/* Trap Raw Status Register */ +#define SCU_TRAPRAW_ +/* Trap Mask Register */ +#define SCU_TRAPDIS_ +/* Trap Clear Register */ +#define SCU_TRAPCLR_ +/* Trap Set Register */ +#define SCU_TRAPSET_ + +/* Power Control SCU Registers */ /* Power Status Register */ -#define PCU_PWRSTAT_ +#define SCU_PWRSTAT_ /* Power Set Control Register */ -#define PCU_PWRSET_ +#define SCU_PWRSET_ /* Power Clear Control Register */ -#define PCU_PWRCLR_ +#define SCU_PWRCLR_ /* EVR Status Register */ -#define PCU_EVRSTAT_ +#define SCU_EVRSTAT_ /* EVR VADC Status Register */ -#define PCU_EVRVADCSTAT_ +#define SCU_EVRVADCSTAT_ /* Power Monitor Value */ -#define PCU_PWRMON_ +#define SCU_PWRMON_ /* HCU Registers */ /* Hibernate Domain Status Register */ -#define HCU_HDSTAT_ +#define SCU_HDSTAT_ /* Hibernate Domain Status Clear Register */ -#define HCU_HDCLR_ +#define SCU_HDCLR_ /* Hibernate Domain Status Set Register */ -#define HCU_HDSET_ +#define SCU_HDSET_ /* Hibernate Domain Control Register */ -#define HCU_HDCR_ +#define SCU_HDCR_ /* Internal 32.768 kHz Clock Source Control Register */ -#define HCU_OSCSICTRL_ +#define SCU_OSCSICTRL_ /* OSC_ULP Status Register */ -#define HCU_OSCULSTAT_ +#define SCU_OSCULSTAT_ /* OSC_ULP Control Register */ -#define HCU_OSCULCTRL_ +#define SCU_OSCULCTRL_ -/* RCU Registers */ +/* Reset SCU Registers */ /* System Reset Status */ -#define RCU_RSTSTAT_ +#define SCU_RSTSTAT_ /* Reset Set Register */ -#define RCU_RSTSET_ +#define SCU_RSTSET_ /* Reset Clear Register */ -#define RCU_RSTCLR_ +#define SCU_RSTCLR_ /* Peripheral Reset Status Register 0 */ -#define RCU_PRSTAT0_ +#define SCU_PRSTAT0_ /* Peripheral Reset Set Register 0 */ -#define RCU_PRSET0_ +#define SCU_PRSET0_ /* Peripheral Reset Clear Register 0 */ -#define RCU_PRCLR0_ +#define SCU_PRCLR0_ /* Peripheral Reset Status Register 1 */ -#define RCU_PRSTAT1_ +#define SCU_PRSTAT1_ /* Peripheral Reset Set Register 1 */ -#define RCU_PRSET1_ +#define SCU_PRSET1_ /* Peripheral Reset Clear Register 1 */ -#define RCU_PRCLR1_ +#define SCU_PRCLR1_ /* Peripheral Reset Status Register 2 */ -#define RCU_PRSTAT2_ +#define SCU_PRSTAT2_ /* Peripheral Reset Set Register 2 */ -#define RCU_PRSET2_ +#define SCU_PRSET2_ /* Peripheral Reset Clear Register 2 */ -#define RCU_PRCLR2_ +#define SCU_PRCLR2_ /* Peripheral Reset Status Register 3 */ -#define RCU_PRSTAT3_ +#define SCU_PRSTAT3_ /* Peripheral Reset Set Register 3 */ -#define RCU_PRSET3_ +#define SCU_PRSET3_ /* Peripheral Reset Clear Register 3 */ -#define RCU_PRCLR3_ +#define SCU_PRCLR3_ -/* CCU Registers */ +/* Clock Control SCU Registers */ /* Clock Status Register */ -#define CCU_CLKSTAT_ +#define SCU_CLKSTAT_ /* Clock Set Control Register */ -#define CCU_CLKSET_ +#define SCU_CLKSET_ /* Clock clear Control Register */ -#define CCU_CLKCLR_ +#define SCU_CLKCLR_ /* System Clock Control */ -#define CCU_SYSCLKCR_ +#define SCU_SYSCLKCR_ /* CPU Clock Control */ -#define CCU_CPUCLKCR_ +#define SCU_CPUCLKCR_ /* Peripheral Bus Clock Control */ -#define CCU_PBCLKCR_ +#define SCU_PBCLKCR_ /* USB Clock Control */ -#define CCU_USBCLKCR_ +#define SCU_USBCLKCR_ /* EBU Clock Control */ -#define CCU_EBUCLKCR_ +#define SCU_EBUCLKCR_ /* CCU Clock Control */ -#define CCU_CCUCLKCR_ +#define SCU_CCUCLKCR_ /* WDT Clock Control */ -#define CCU_WDTCLKCR_ +#define SCU_WDTCLKCR_ /* External clock Control Register */ -#define CCU_EXTCLKCR_ +#define SCU_EXTCLKCR_ /* Sleep Control Register */ -#define CCU_SLEEPCR_ +#define SCU_SLEEPCR_ /* Deep Sleep Control Register */ -#define CCU_DSLEEPCR_ +#define SCU_DSLEEPCR_ +/* Peripheral 0 Clock Gating Status */ +#define SCU_CGATSTAT0_ +/* Peripheral 0 Clock Gating Set */ +#define SCU_CGATSET0_ +/* Peripheral 0 Clock Gating Clear */ +#define SCU_CGATCLR0_ +/* Peripheral 1 Clock Gating Status */ +#define SCU_CGATSTAT1_ +/* Peripheral 1 Clock Gating Set */ +#define SCU_CGATSET1_ +/* Peripheral 1 Clock Gating Clear */ +#define SCU_CGATCLR1_ +/* Peripheral 2 Clock Gating Status */ +#define SCU_CGATSTAT2_ +/* Peripheral 2 Clock Gating Set */ +#define SCU_CGATSET2_ +/* Peripheral 2 Clock Gating Clear */ +#define SCU_CGATCLR2_ +/* Peripheral 3 Clock Gating Status */ +#define SCU_CGATSTAT3_ +/* Peripheral 3 Clock Gating Set */ +#define SCU_CGATSET3_ +/* Peripheral 3 Clock Gating Clear */ +#define SCU_CGATCLR3_ + +/* Oscillator Control SCU Registers */ + /* OSC_HP Status Register */ -#define CCU_OSCHPSTAT_ +#define OSCU_OSCHPSTAT_ /* OSC_HP Control Register */ -#define CCU_OSCHPCTRL_ +#define OSCU_OSCHPCTRL_ /* Clock Calibration Constant Register */ -#define CCU_CLKCALCONST_ +#define OSCU_CLKCALCONST_ + +/* PLL Control SCU Registers */ + /* System PLL Status Register */ -#define CCU_PLLSTAT_ +#define SCU_PLLSTAT_ /* System PLL Configuration 0 Register */ -#define CCU_PLLCON0_ +#define SCU_PLLCON0_ /* System PLL Configuration 1 Register */ -#define CCU_PLLCON1_ +#define SCU_PLLCON1_ /* System PLL Configuration 2 Register */ -#define CCU_PLLCON2_ +#define SCU_PLLCON2_ /* USB PLL Status Register */ -#define CCU_USBPLLSTAT_ +#define SCU_USBPLLSTAT_ /* USB PLL Control Register */ -#define CCU_USBPLLCON_ +#define SCU_USBPLLCON_ /* Clock Multiplexing Status Register */ -#define CCU_CLKMXSTAT_ +#define SCU_CLKMXSTAT_ #endif /* __ARCH_ARM_SRC_XMC4_CHIP_XMC4_SCU_H */ From 77f244ed7b848195b24556f4cfc070fe42a108e8 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Wed, 15 Mar 2017 10:22:24 -0600 Subject: [PATCH 05/21] XMC4xx: Add logic to get the CPU frequency. --- arch/arm/src/xmc4/chip/xmc4_scu.h | 52 ++++++++- arch/arm/src/xmc4/xmc4_clockconfig.c | 110 +++++++++++++++++-- arch/arm/src/xmc4/xmc4_clockconfig.h | 79 ++++++++++++++ arch/arm/src/xmc4/xmc4_start.c | 4 +- arch/arm/src/xmc4/xmc4_start.h | 61 +++++++++++ configs/xmc4500-relax/include/board.h | 150 ++++++++++++++++++++++++++ 6 files changed, 442 insertions(+), 14 deletions(-) create mode 100644 arch/arm/src/xmc4/xmc4_clockconfig.h create mode 100644 arch/arm/src/xmc4/xmc4_start.h create mode 100644 configs/xmc4500-relax/include/board.h diff --git a/arch/arm/src/xmc4/chip/xmc4_scu.h b/arch/arm/src/xmc4/chip/xmc4_scu.h index ab5b7719953..e9370565ba9 100644 --- a/arch/arm/src/xmc4/chip/xmc4_scu.h +++ b/arch/arm/src/xmc4/chip/xmc4_scu.h @@ -505,10 +505,21 @@ #define SCU_CLKSET_ /* Clock clear Control Register */ #define SCU_CLKCLR_ + /* System Clock Control */ -#define SCU_SYSCLKCR_ + +#define SCU_SYSCLKCR_SYSDIV_SHIFT (0) /* Bits 0-7: System Clock Division Value */ +#define SCU_SYSCLKCR_SYSDIV_MASK (0xff << SCU_CLK_SYSCLKCR_SYSDIV_SHIFT) +# define SCU_SYSCLKCR_SYSDIV(n) ((uint32_t)((n)-1) << SCU_CLK_SYSCLKCR_SYSDIV_SHIFT) + +#define SCU_SYSCLKCR_SYSSEL (1 << 16) /* Bit 16: System Clock Selection Value */ +# define SCU_SYSCLKCR_SYSSEL_OFI (0) /* 0=OFI clock */ +# define SCU_SYSCLKCR_SYSSEL_PLL (1 << 16) /* 1=PLL clock */ + /* CPU Clock Control */ -#define SCU_CPUCLKCR_ + +#define SCU_CPUCLKCR_CPUDIV (1 << 0) /* Bit 0: CPU Clock Divider Enable */ + /* Peripheral Bus Clock Control */ #define SCU_PBCLKCR_ /* USB Clock Control */ @@ -562,13 +573,44 @@ /* PLL Control SCU Registers */ /* System PLL Status Register */ -#define SCU_PLLSTAT_ + +#define SCU_PLLSTAT_VCOBYST (1 << 0) /* Bit 0: VCO Bypass Status */ +#define SCU_PLLSTAT_PWDSTAT (1 << 1) /* Bit 1: PLL Power-saving Mode Status */ +#define SCU_PLLSTAT_VCOLOCK (1 << 2) /* Bit 2: PLL LOCK Status */ +#define SCU_PLLSTAT_K1RDY (1 << 4) /* Bit 4: K1 Divider Ready Status */ +#define SCU_PLLSTAT_K2RDY (1 << 5) /* Bit 5: K2 Divider Ready Status */ +#define SCU_PLLSTAT_BY (1 << 6) /* Bit 6: Bypass Mode Status */ +#define SCU_PLLSTAT_PLLLV (1 << 7) /* Bit 7: Oscillator for PLL Valid Low Status */ +#define SCU_PLLSTAT_PLLHV (1 << 8) /* Bit 8: Oscillator for PLL Valid High Status */ +#define SCU_PLLSTAT_PLLSP (1 << 9) /* Bit 9: Oscillator for PLL Valid Spike Status */ + /* System PLL Configuration 0 Register */ #define SCU_PLLCON0_ + /* System PLL Configuration 1 Register */ -#define SCU_PLLCON1_ + +#define SCU_PLLCON1_K1DIV_SHIFT (0) /* Bits 0-6: K1-Divider Value */ +#define SCU_PLLCON1_K1DIV_MASK (0x7f << SCU_PLLCON1_K1DIV_SHIFT) +# define SCU_PLLCON1_K1DIV(n) ((uint32_t)((n)-1) << SCU_PLLCON1_K1DIV_SHIFT) +#define SCU_PLLCON1_NDIV_SHIFT (8) /* Bits 8-14: N-Divider Value */ +#define SCU_PLLCON1_NDIV_MASK (0x7f << SCU_PLLCON1_NDIV_SHIFT) +# define SCU_PLLCON1_NDIV(n) ((uint32_t)((n)-1) << SCU_PLLCON1_NDIV_SHIFT) +#define SCU_PLLCON1_K2DIV_SHIFT (16) /* Bit 16-22: K2-Divider Value */ +#define SCU_PLLCON1_K2DIV_MASK (0x7f << SCU_PLLCON1_K2DIV_SHIFT) +# define SCU_PLLCON1_K2DIV(n) ((uint32_t)((n)-1) << SCU_PLLCON1_K2DIV_SHIFT) +#define SCU_PLLCON1_PDIV_SHIFT (24) /* Bits 24-27: P-Divider Value */ +#define SCU_PLLCON1_PDIV_MASK (0x7f << SCU_PLLCON1_PDIV_SHIFT) +# define SCU_PLLCON1_PDIV(n) ((uint32_t)((n)-1) << SCU_PLLCON1_PDIV_SHIFT) + /* System PLL Configuration 2 Register */ -#define SCU_PLLCON2_ + +#define SCU_PLLCON2_PINSEL (1 << 0) /* Bit 0: P-Divider Input Selection */ +# define SCU_PLLCON2_PINSEL_PLL (0) /* 0=PLL external oscillator selected */ +# define SCU_PLLCON2_PINSEL_OFI (1 << 0) /* 1=Backup clock source selected */ +#define SCU_PLLCON2_K1INSEL (1 << 8) /* Bit 8: K1-Divider Input */ +# define SCU_PLLCON2_K1INSEL_PLL (0) /* 0=PLL external oscillator selected */ +# define SCU_PLLCON2_K1INSEL_OFI (1 << 8) /* 1=Backup clock source selected */ + /* USB PLL Status Register */ #define SCU_USBPLLSTAT_ /* USB PLL Control Register */ diff --git a/arch/arm/src/xmc4/xmc4_clockconfig.c b/arch/arm/src/xmc4/xmc4_clockconfig.c index 67efe53651d..d7d5a8bc7df 100644 --- a/arch/arm/src/xmc4/xmc4_clockconfig.c +++ b/arch/arm/src/xmc4/xmc4_clockconfig.c @@ -1,9 +1,11 @@ /**************************************************************************** - * arch/arm/src/xmc4/xmc4_clock_config.c + * arch/arm/src/xmc4/xmc4_clockconfig.c * * Copyright (C) 2017 Gregory Nutt. All rights reserved. * Authors: Gregory Nutt * + * Reference: XMC4500 Reference Manual V1.5 2014-07 Microcontrollers. + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: @@ -31,6 +33,20 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * + * May include some logic from sample code provided by Infineon: + * + * Copyright (C) 2011-2015 Infineon Technologies AG. All rights reserved. + * + * Infineon Technologies AG (Infineon) is supplying this software for use with + * Infineon's microcontrollers. This file can be freely distributed within + * development tools that are supporting such microcontrollers. + * + * THIS SOFTWARE IS PROVIDED AS IS. NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, + * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * ****************************************************************************/ /**************************************************************************** @@ -47,10 +63,6 @@ * Pre-processor Definitions ****************************************************************************/ -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - /**************************************************************************** * Private Functions ****************************************************************************/ @@ -60,7 +72,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: xmc4_clock_config + * Name: xmc4_clock_configure * * Description: * Called to initialize the XMC4xxx chip. This does whatever setup is @@ -69,6 +81,90 @@ * ****************************************************************************/ -void xmc4_clock_config(void) +void xmc4_clock_configure(void) { } + +/**************************************************************************** + * Name: xmc4_get_coreclock + * + * Description: + * Return the current core clock frequency (fCPU). + * + ****************************************************************************/ + +uint32_t xmc4_get_coreclock(void) +{ + uint32_t pdiv; + uint32_t ndiv; + uint32_t kdiv; + uint32_t sysdiv; + uint32_t regval; + uint32_t temp; + + if ((getreg32(XMC4_SCU_SYSCLKCR) & SCU_SYSCLKCR_SYSSEL) != 0) + { + /* fPLL is clock source for fSYS */ + + if ((getreg32(XMC4_SCU_PLLCON2) & SCU_PLLCON2_PINSEL) != 0) + { + /* PLL input clock is the backup clock (fOFI) */ + + temp = OFI_FREQUENCY; + } + else + { + /* PLL input clock is the high performance oscillator (fOSCHP); + * Only board specific logic knows this value. + */ + + temp = BOARD_XTAL_FREQUENCY; + } + + /* Check if PLL is locked */ + + regval = getreg32(XMC4_SCU_PLLSTAT); + if ((regval & SCU_PLLSTAT_VCOLOCK) != 0) + { + /* PLL normal mode */ + + regval = getreg32(XMC4_SCU_PLLCON1); + pdiv = ((regval & SCU_PLLCON1_PDIV_MASK) >> SCU_PLLCON1_PDIV_SHIFT) + 1; + ndiv = ((regval & SCU_PLLCON1_NDIV_MASK) >> SCU_PLLCON1_NDIV_SHIFT) + 1; + kdiv = ((regval & SCU_PLLCON1_K2DIV_MASK) >> SCU_PLLCON1_K2DIV_SHIFT) + 1; + + temp = (temp / (pdiv * kdiv)) * ndiv; + } + else + { + /* PLL prescalar mode */ + + regval = getreg32(XMC4_SCU_PLLCON1); + kdiv = ((regval & SCU_PLLCON1_K1DIV_MASK) >> SCU_PLLCON1_K1DIV_SHIFT) + 1; + + temp = (temp / kdiv); + } + } + else + { + /* fOFI is clock source for fSYS */ + + temp = OFI_FREQUENCY; + } + + /* Divide by SYSDIV to get fSYS */ + + regval = getreg32(XMC4_SCU_SYSCLKCR); + sysdiv = ((regval & SCU_SYSCLKCR_SYSDIV_MASK) >> SCU_SYSCLKCR_SYSDIV_SHIFT) + 1; + temp = temp / sysdiv; + + /* Check if the fSYS clock is divided by two to produce fCPU clock. */ + + regval = getreg32(CPUCLKCR); + if ((regval & SCU_CPUCLKCR_CPUDIV) != 0) + { + temp = temp >> 1; + } + + return temp; +} diff --git a/arch/arm/src/xmc4/xmc4_clockconfig.h b/arch/arm/src/xmc4/xmc4_clockconfig.h new file mode 100644 index 00000000000..6e03989cad0 --- /dev/null +++ b/arch/arm/src/xmc4/xmc4_clockconfig.h @@ -0,0 +1,79 @@ +/************************************************************************************ + * arch/arm/src/xmc4/xmc4_clockconfig.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_XMC4_XMC4_CLOCKCONFIG_H +#define __ARCH_ARM_SRC_XMC4_XMC4_CLOCKCONFIG_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include +#include + +/************************************************************************************ + * Preprocessor Definitions + ************************************************************************************/ + +#define OFI_FREQUENCY 24000000 /* Frequency of internal Backup Clock Source */ +#define OSI_FREQUENCY 32768 /* Frequency of internal Slow Clock Source */ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/**************************************************************************** + * Name: xmc4_clock_configure + * + * Description: + * Called to initialize the XMC4xxx chip. This does whatever setup is + * needed to put the MCU in a usable state. This includes the + * initialization of clocking using the settings in board.h. + * + ****************************************************************************/ + +void xmc4_clock_configure(void); + +/**************************************************************************** + * Name: xmc4_get_coreclock + * + * Description: + * Return the current core clock frequency. + * + ****************************************************************************/ + +uint32_t xmc4_get_coreclock(void); + +#endif /* __ARCH_ARM_SRC_XMC4_XMC4_CLOCKCONFIG_H */ diff --git a/arch/arm/src/xmc4/xmc4_start.c b/arch/arm/src/xmc4/xmc4_start.c index e71722e4be5..77e792847e9 100644 --- a/arch/arm/src/xmc4/xmc4_start.c +++ b/arch/arm/src/xmc4/xmc4_start.c @@ -279,7 +279,7 @@ void __start(void) /* Disable the watchdog timer */ - kinetis_wddisable(); + xmc4_wddisable(); /* Clear .bss. We'll do this inline (vs. calling memset) just to be * certain that there are no issues with the state of global variables. @@ -318,7 +318,7 @@ void __start(void) * RAM functions having been copied to RAM). */ - xmc4_clock_config(); + xmc4_clock_configure(); /* Configure the uart and perform early serial initialization so that we * can get debug output as soon as possible (This depends on clock diff --git a/arch/arm/src/xmc4/xmc4_start.h b/arch/arm/src/xmc4/xmc4_start.h new file mode 100644 index 00000000000..2be470640bf --- /dev/null +++ b/arch/arm/src/xmc4/xmc4_start.h @@ -0,0 +1,61 @@ +/************************************************************************************ + * arch/arm/src/xmc4/xmc4_start.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_XMC4_XMC4_CLOCKCONFIG_H +#define __ARCH_ARM_SRC_XMC4_XMC4_CLOCKCONFIG_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: xmc4_board_initialize + * + * Description: + * All XMC4xxx architectures must provide the following entry point. This entry + * point is called early in the initialization -- after all memory has been + * configured and mapped but before any devices have been initialized. + * + ************************************************************************************/ + +void xmc4_board_initialize(void); + +#endif /* __ARCH_ARM_SRC_XMC4_XMC4_CLOCKCONFIG_H */ diff --git a/configs/xmc4500-relax/include/board.h b/configs/xmc4500-relax/include/board.h new file mode 100644 index 00000000000..a448469bca7 --- /dev/null +++ b/configs/xmc4500-relax/include/board.h @@ -0,0 +1,150 @@ +/************************************************************************************ + * configs/xmc4500-relax/include/board.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __CONFIG_XMC4500_RELAX_INCLUDE_BOARD_H +#define __CONFIG_XMC4500_RELAX_INCLUDE_BOARD_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +# include +#endif + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Clocking *************************************************************************/ +/* Default clock initialization + * fPLL = 288MHz => fSYS = 288MHz => fCPU = 144MHz + * => fPB = 144MHz + * => fCCU = 144MHz + * => fETH = 72MHz + * => fUSB = 48MHz + * => fEBU = 72MHz + * + * fUSBPLL Disabled, only enabled if SCU_CLK_USBCLKCR_USBSEL_USBPLL is selected + * + * fOFI = 24MHz => fWDT = 24MHz + */ + +/* On-board crystals + * + * NOTE: Only the XMC4500 Relax Kit-V1 provides the 32.768KHz RTC crystal. It + * is not available on XMC4500 Relax Lite Kit-V1. + */ + +#define BOARD_XTAL_FREQUENCY 12000000 /* 12MHz XTAL */ +#undef BOARD_RTC_XTAL_FRQUENCY /* 32.768KHz RTC XTAL not available */ + +/* Select the external crystal as the PLL clock source */ + +#define BOARD_PLL_CLOCKSRC_XTAL 1 /* PLL Clock source == extnernal crystal */ +#undef BOARD_PLL_CLOCKSRC_OFI /* PLL Clock source != internal fast oscillator */ + +/* PLL Configuration: + * + * fPLL = (fPLLSRC / (pdiv * k2div) * ndiv + * + * fPLL = (12000000 / (2 * 1)) * 48 + * = 288MHz + */ + +#define BOARD_PLL_PDIV 2 +#define BOARD_PLL_NDIV 48 +#define BOARD_PLL_K2DIV 1 +#define BOARD_PLL_FREQUENCY 288000000 + +/* System frequency is divided down from PLL output */ + +#define BOARD_SYSDIV 1 /* PLL Output divider to get fSYS */ +#define BOARD_SYS_FREQUENCY 288000000 + +/* CPU frequency may be divided down from system frequency */ + +#define BOARD_CPUDIV_ENABLE 1 /* Enable PLL dive by 2 for fCPU */ +#define BOARD_CPU_FREQUENCY 144000000 + +/* Standby clock source selection + * + * BOARD_STDBY_CLOCKSRC_OSI - Internal slow oscillator (32768Hz) + * BOARD_STDBY_CLOCKSRC_OSCULP - External 32.768KHz crystal + */ + +#define BOARD_STDBY_CLOCKSRC_OSI 1 +#undef BOARD_STDBY_CLOCKSRC_OSCULP + +/* USB PLL settings. + * + * fUSBPLL = 48MHz and fUSBPLLVCO = 384 MHz + * + * Note: Implicit divider of 2 and fUSBPLLVCO >= 260 MHz and + * fUSBPLLVCO <= 520 MHz + */ + +#define BOARD_USB_PDIV 2 +#define BOARD_USB_NDIV 64 + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/************************************************************************************ + * Public Function Prototypes + ************************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __CONFIG_XMC4500_RELAX_INCLUDE_BOARD_H */ From 519f14fbb5bd981966148623b430144d4ba135c2 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Wed, 15 Mar 2017 11:43:58 -0600 Subject: [PATCH 06/21] XMC4xxx: A few more SCU register bit definitions. --- arch/arm/src/xmc4/chip/xmc4_scu.h | 78 +++++++++++++++++++++++-------- 1 file changed, 58 insertions(+), 20 deletions(-) diff --git a/arch/arm/src/xmc4/chip/xmc4_scu.h b/arch/arm/src/xmc4/chip/xmc4_scu.h index e9370565ba9..87b11f3753e 100644 --- a/arch/arm/src/xmc4/chip/xmc4_scu.h +++ b/arch/arm/src/xmc4/chip/xmc4_scu.h @@ -421,25 +421,30 @@ /* Trap Control Registers */ -/* Trap Status Register */ -#define SCU_TRAPSTAT_ -/* Trap Raw Status Register */ -#define SCU_TRAPRAW_ -/* Trap Mask Register */ -#define SCU_TRAPDIS_ -/* Trap Clear Register */ -#define SCU_TRAPCLR_ -/* Trap Set Register */ -#define SCU_TRAPSET_ +/* Trap Status Register, Trap Raw Status Register, Trap Mask Register, Trap Clear + * Register, and Trap Set Register + */ + +#define SCU_TRAP_SOSCWDGT (1 << 0) /* Bit 0: OSC_HP Oscillator Watchdog Trap */ +#define SCU_TRAP_SVCOLCKT (1 << 2) /* Bit 2: System VCO Lock Trap */ +#define SCU_TRAP_UVCOLCKT (1 << 3) /* Bit 3: USB VCO Lock Trap */ +#define SCU_TRAP_PET (1 << 4) /* Bit 4: Parity Error Trap */ +#define SCU_TRAP_BRWNT (1 << 5) /* Bit 5: Brown Out Trap */ +#define SCU_TRAP_ULPWDGT (1 << 6) /* Bit 6: OSC_ULP Oscillator Watchdog Trap */ +#define SCU_TRAP_BWERR0T (1 << 7) /* Bit 7: Peripheral Bridge 0 Trap */ +#define SCU_TRAP_BWERR1T (1 << 8) /* Bit 8: Peripheral Bridge 1 Trap */ /* Power Control SCU Registers */ -/* Power Status Register */ -#define SCU_PWRSTAT_ -/* Power Set Control Register */ -#define SCU_PWRSET_ -/* Power Clear Control Register */ -#define SCU_PWRCLR_ +/* Power Status Register, Power Set Control Register, and Power Clear + * Control Register + */ + +#define SCU_PWR_HIBEN (1 << 0) /* Bit 0: Hibernate Domain Enable State */ +#define SCU_PWR_USBPHYPDQ (1 << 16) /* Bit 16: USB PHY Transceiver State */ +#define SCU_PWR_USBOTGEN (1 << 17) /* Bit 17: USB On-The-Go Comparators State */ +#define SCU_PWR_USBPUWQ (1 << 18) /* Bit 18: USB Weak Pull-Up at PADN State */ + /* EVR Status Register */ #define SCU_EVRSTAT_ /* EVR VADC Status Register */ @@ -467,11 +472,34 @@ /* Reset SCU Registers */ /* System Reset Status */ -#define SCU_RSTSTAT_ + +#define SCU_RSTSTAT_RSTSTAT_SHIFT (0) /* Bits 0-7: Reset Status Information */ +#define SCU_RSTSTAT_RSTSTAT_MASK (0xff << SCU_RSTSTAT_RSTSTAT_SHIFT) +# define SCU_RSTSTAT_RSTSTAT_PORST (1 << SCU_RSTSTAT_RSTSTAT_SHIFT) /* PORST reset */ +# define SCU_RSTSTAT_RSTSTAT_SWD (2 << SCU_RSTSTAT_RSTSTAT_SHIFT) /* SWD reset */ +# define SCU_RSTSTAT_RSTSTAT_PV (4 << SCU_RSTSTAT_RSTSTAT_SHIFT) /* PV reset */ +# define SCU_RSTSTAT_RSTSTAT_CPUSYS (8 << SCU_RSTSTAT_RSTSTAT_SHIFT) /* CPU system reset */ +# define SCU_RSTSTAT_RSTSTAT_CPULOCK (16 << SCU_RSTSTAT_RSTSTAT_SHIFT) /* CPU lockup reset */ +# define SCU_RSTSTAT_RSTSTAT_WDT (32 << SCU_RSTSTAT_RSTSTAT_SHIFT) /* WDT reset */ +# define SCU_RSTSTAT_RSTSTAT_PERR (128 << SCU_RSTSTAT_RSTSTAT_SHIFT) /* Parity Error reset */ + +#define SCU_RSTSTAT_HIBWK (1 << 8) /* Bit 8: Hibernate Wake-up Status */ +#define SCU_RSTSTAT_HIBRS (1 << 9) /* Bit 9: Hibernate Reset Status */ +#define SCU_RSTSTAT_LCKEN (1 << 10) /* Bit 10: Enable Lockup Status */ + /* Reset Set Register */ -#define SCU_RSTSET_ + +#define SCU_RSTSET_HIBWK (1 << 8) /* Bit 8: Hibernate Wake-up Reset Status */ +#define SCU_RSTSET_HIBRS (1 << 9) /* Bit 9: Hibernate Reset Reset Status */ +#define SCU_RSTSET_LCKEN (1 << 10) /* Bit 10: Enable Lockup Reset Status */ + /* Reset Clear Register */ -#define SCU_RSTCLR_ + +#define SCU_RSTCLR_RSCLR (1 << 0) /* Bit 0: Clear Reset Status */ +#define SCU_RSTCLR_HIBWK (1 << 8) /* Bit 8: Clear Hibernate Wake-up Reset Status */ +#define SCU_RSTCLR_HIBRS (1 << 9) /* Bit 9: Clear Hibernate Reset */ +#define SCU_RSTCLR_LCKEN (1 << 10) /* Bit 10: Clear Hibernate Reset */ + /* Peripheral Reset Status Register 0 */ #define SCU_PRSTAT0_ /* Peripheral Reset Set Register 0 */ @@ -585,7 +613,17 @@ #define SCU_PLLSTAT_PLLSP (1 << 9) /* Bit 9: Oscillator for PLL Valid Spike Status */ /* System PLL Configuration 0 Register */ -#define SCU_PLLCON0_ + +#define SCU_PLLCON0_VCOBYP (1 << 0) /* Bit 0: VCO Bypass */ +#define SCU_PLLCON0_VCOPWD (1 << 1) /* Bit 1: VCO Power Saving Mode */ +#define SCU_PLLCON0_VCOTR (1 << 2) /* Bit 2: VCO Trim Control */ +#define SCU_PLLCON0_FINDIS (1 << 4) /* Bit 4: Disconnect Oscillator from VCO */ +#define SCU_PLLCON0_OSCDISCDIS (1 << 6) /* Bit 6: Oscillator Disconnect Disable */ +#define SCU_PLLCON0_PLLPWD (1 << 16) /* Bit 16: PLL Power Saving Mode */ +#define SCU_PLLCON0_OSCRES (1 << 17) /* Bit 17: Oscillator Watchdog Reset */ +#define SCU_PLLCON0_RESLD (1 << 18) /* Bit 18: Restart VCO Lock Detection */ +#define SCU_PLLCON0_AOTREN (1 << 19) /* Bit 19: Automatic Oscillator Calibration Enable */ +#define SCU_PLLCON0_FOTR (1 << 20) /* Bit 20: Factory Oscillator Calibration */ /* System PLL Configuration 1 Register */ From 059e398185c3861406a9e4350ff719f1fb226e53 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Wed, 15 Mar 2017 18:50:48 -0600 Subject: [PATCH 07/21] XMC4xxx: A few more SCU register bit definitions. --- arch/arm/src/xmc4/chip/xmc4_scu.h | 132 ++++++++++++++++++++++++++---- 1 file changed, 117 insertions(+), 15 deletions(-) diff --git a/arch/arm/src/xmc4/chip/xmc4_scu.h b/arch/arm/src/xmc4/chip/xmc4_scu.h index 87b11f3753e..8f6f89cc4a9 100644 --- a/arch/arm/src/xmc4/chip/xmc4_scu.h +++ b/arch/arm/src/xmc4/chip/xmc4_scu.h @@ -326,9 +326,9 @@ /* Oscillator Control SCU Registers */ -#define XMC4_OSCU_OSCHPSTAT (XMC4_SCU_OSC_BASE+XMC4_OSCU_OSCHPSTAT_OFFSET) -#define XMC4_OSCU_OSCHPCTRL (XMC4_SCU_OSC_BASE+XMC4_OSCU_OSCHPCTRL_OFFSET) -#define XMC4_OSCU_CLKCALCONST (XMC4_SCU_OSC_BASE+XMC4_OSCU_CLKCALCONST_OFFSET) +#define XMC4_SCU_OSCHPSTAT (XMC4_SCU_OSC_BASE+XMC4_SCU_OSCHPSTAT_OFFSET) +#define XMC4_SCU_OSCHPCTRL (XMC4_SCU_OSC_BASE+XMC4_SCU_OSCHPCTRL_OFFSET) +#define XMC4_SCU_CLKCALCONST (XMC4_SCU_OSC_BASE+XMC4_SCU_CLKCALCONST_OFFSET) /* PLL Control SCU Registers */ @@ -370,8 +370,23 @@ #define SCU_G0ORCEN_ /* Out-Of-Range Comparator Enable Register 1 */ #define SCU_G1ORCEN_ + /* Mirror Update Status Register */ -#define SCU_MIRRSTS_ + +#define SCU_MIRRSTS_HDCLR (1 << 1) /* Bit 1: HDCLR Mirror Register Write Status */ +#define SCU_MIRRSTS_HDSET (1 << 2) /* Bit 2: HDSET Mirror Register Write Status */ +#define SCU_MIRRSTS_HDCR (1 << 3) /* Bit 3: HDCR Mirror Register Write Status */ +#define SCU_MIRRSTS_OSCSICTRL (1 << 5) /* Bit 5: OSCSICTRL Mirror Register Write Status */ +#define SCU_MIRRSTS_OSCULSTAT (1 << 6) /* Bit 6: OSCULSTAT Mirror Register Write Status */ +#define SCU_MIRRSTS_OSCULCTRL (1 << 7) /* Bit 7: OSCULCTRL Mirror Register Write Status */ +#define SCU_MIRRSTS_RTC_CTR (1 << 8) /* Bit 8: RTC CTR Mirror Register Write Status */ +#define SCU_MIRRSTS_RTC_ATIM0 (1 << 9) /* Bit 9: RTC ATIM0 Mirror Register Write Status */ +#define SCU_MIRRSTS_RTC_ATIM1 (1 << 10) /* Bit 10: RTC ATIM1 Mirror Register Write Status */ +#define SCU_MIRRSTS_RTC_TIM0 (1 << 11) /* Bit 11: RTC TIM0 Mirror Register Write Status */ +#define SCU_MIRRSTS_RTC_TIM1 (1 << 12) /* Bit 12: RTC TIM1 Mirror Register Write Status */ +#define SCU_MIRRSTS_RMX (1 << 13) /* Bit 13: Retention Memory Access Register Update Status */ +#define SCU_MIRRSTS_RTC_MSKSR (1 << 14) /* Bit 14: RTC MSKSSR Mirror Register Write Status */ +#define SCU_MIRRSTS_RTC_CLRSR (1 << 15) /* Bit 15: RTC CLRSR Mirror Register Write Status */ /* Ethernet Control SCU Resters */ @@ -452,22 +467,93 @@ /* Power Monitor Value */ #define SCU_PWRMON_ -/* HCU Registers */ - +/* Hibernation SCU Registers */ /* Hibernate Domain Status Register */ -#define SCU_HDSTAT_ + +#define SCU_HDSTAT_EPEV (1 << 0) /* Bit 0: Wake-up Pin Event Positive Edge Status */ +#define SCU_HDSTAT_ENEV (1 << 1) /* Bit 1: Wake-up Pin Event Negative Edge Status */ +#define SCU_HDSTAT_RTCEV (1 << 2) /* Bit 2: RTC Event Status */ +#define SCU_HDSTAT_ULPWDG (1 << 3) /* Bit 3: ULP WDG Alarm Status */ +#define SCU_HDSTAT_HIBNOUT (1 << 4) /* Bit 3: Hibernate Control Status */ + /* Hibernate Domain Status Clear Register */ -#define SCU_HDCLR_ + +#define SCU_HDCLR_EPEV (1 << 0) /* Bit 0: Wake-up Pin Event Positive Edge Clear */ +#define SCU_HDCLR_ENEV (1 << 1) /* Bit 1: Wake-up Pin Event Negative Edge Clear */ +#define SCU_HDCLR_RTCEV (1 << 2) /* Bit 2: RTC Event Clear */ +#define SCU_HDCLR_ULPWDG (1 << 3) /* Bit 3: ULP WDG Alarm Clear */ + /* Hibernate Domain Status Set Register */ -#define SCU_HDSET_ + +#define SCU_HDSET_EPEV (1 << 0) /* Bit 0: Wake-up Pin Event Positive Edge Set */ +#define SCU_HDSET_ENEV (1 << 1) /* Bit 1: Wake-up Pin Event Negative Edge Set */ +#define SCU_HDSET_RTCEV (1 << 2) /* Bit 2: RTC Event Set */ +#define SCU_HDSET_ULPWDG (1 << 3) /* Bit 3: ULP WDG Alarm Set */ + /* Hibernate Domain Control Register */ -#define SCU_HDCR_ + +#define SCU_HDCR_WKPEP (1 << 0) /* Bit 0: Wake-Up on Pin Event Positive Edge Enable */ +#define SCU_HDCR_WKPEN (1 << 1) /* Bit 1: Wake-up on Pin Event Negative Edge Enable */ +#define SCU_HDCR_RTCE (1 << 2) /* Bit 2: Wake-up on RTC Event Enable */ +#define SCU_HDCR_ULPWDGEN (1 << 3) /* Bit 3: ULP WDG Alarm Enable */ +#define SCU_HDCR_HIB (1 << 4) /* Bit 4: Hibernate Request Value Set */ +#define SCU_HDCR_RCS (1 << 6) /* Bit 6: fRTC Clock Selection */ +# define SCU_HDCR_RCS_OSI (0) /* 0=fOSI */ +# define SCU_HDCR_RCS_ULP (1 << 6) /* 1=fULP */ +#define SCU_HDCR_STDBYSEL (1 << 7) /* Bit 7: fSTDBY Clock Selection */ +# define SCU_HDCR_STDBYSEL_OSI (0) /* 0=fOSI */ +# define SCU_HDCR_STDBYSEL_ULP (1 << 7) /* 1=fULP */ +#define SCU_HDCR_WKUPSEL (1 << 8) /* Bit 8: Wake-Up from Hibernate Trigger Input Select */ +# define SCU_HDCR_WKUPSEL_HIBIO1 (0) /* 0=HIB_IO_1 pin selected */ +# define SCU_HDCR_WKUPSEL_HIBIO0 (1 << 8) /* 1=HIB_IO_0 pin selected */ +#define SCU_HDCR_GPI0SEL (1 << 10) /* Bit 10: General Purpose Input 0 Selection */ +# define SCU_HDCR_GPIOSEL_HIBIO1 (0) /* 0=HIB_IO_1 pin selected */ +# define SCU_HDCR_GPIOSEL_HIBIO0 (1 << 10) /* 1=HIB_IO_0 pin selected */ +#define SCU_HDCR_HIBIO0POL (1 << 12) /* Bit 12: HIBIO0 Polarity Set */ +# define SCU_HDCR_HIBIO0POL_DIR (0) /* 0=Direct */ +# define SCU_HDCR_HIBIO0POL_INV (1 << 12) /* 1=Inverted */ +#define SCU_HDCR_HIBIO1POL (1 << 13) /* Bit 13: HIBIO1 Polarity Set */ +# define SCU_HDCR_HIBIO1POL_DIR (0) /* 0=Direct */ +# define SCU_HDCR_HIBIO1POL_INV (1 << 13) /* 1=Inverted */ +#define SCU_HDCR_HIBIO0SEL_SHIFT (16) /* Bits 16-19: HIB_IO_0 Pin I/O Control */ +#define SCU_HDCR_HIBIO0SEL_MASK (15 << SCU_HDCR_HIBIO0SEL_SHIFT) +# define SCU_HDCR_HIBIO0SEL_DIR (0 << SCU_HDCR_HIBIO0SEL_SHIFT) /* Direct input */ +# define SCU_HDCR_HIBIO0SEL_DIRPD (1 << SCU_HDCR_HIBIO0SEL_SHIFT) /* Direct input, Input pull-down */ +# define SCU_HDCR_HIBIO0SEL_DIRPU (2 << SCU_HDCR_HIBIO0SEL_SHIFT) /* Direct input, Input pull-up */ +# define SCU_HDCR_HIBIO0SEL_PP (8 << SCU_HDCR_HIBIO0SEL_SHIFT) /* Push-pull HIB Control output */ +# define SCU_HDCR_HIBIO0SEL_PPWDT (9 << SCU_HDCR_HIBIO0SEL_SHIFT) /* Push-pull WDT service output */ +# define SCU_HDCR_HIBIO0SEL_PPGPIO (10 << SCU_HDCR_HIBIO0SEL_SHIFT) /* Push-pull GPIO output */ +# define SCU_HDCR_HIBIO0SEL_OD (12 << SCU_HDCR_HIBIO0SEL_SHIFT) /* Open-drain HIB Control output */ +# define SCU_HDCR_HIBIO0SEL_ODWDT (13 << SCU_HDCR_HIBIO0SEL_SHIFT) /* Open-drain WDT service output */ +# define SCU_HDCR_HIBIO0SEL_ODGPIO (14 << SCU_HDCR_HIBIO0SEL_SHIFT) /* Open-drain GPIO output */ +#define SCU_HDCR_HIBIO1SEL_SHIFT (20) /* Bits 20-23: HIB_IO_1 Pin I/O Control */ +#define SCU_HDCR_HIBIO1SEL_MASK (15 << SCU_HDCR_HIBIO1SEL_SHIFT) +# define SCU_HDCR_HIBIO1SEL_DIR (0 << SCU_HDCR_HIBIO1SEL_SHIFT) /* Direct input */ +# define SCU_HDCR_HIBIO1SEL_DIRPD (1 << SCU_HDCR_HIBIO1SEL_SHIFT) /* Direct input, Input pull-down */ +# define SCU_HDCR_HIBIO1SEL_DIRPU (2 << SCU_HDCR_HIBIO1SEL_SHIFT) /* Direct input, Input pull-up */ +# define SCU_HDCR_HIBIO1SEL_PP (8 << SCU_HDCR_HIBIO1SEL_SHIFT) /* Push-pull HIB Control output */ +# define SCU_HDCR_HIBIO1SEL_PPWDT (9 << SCU_HDCR_HIBIO1SEL_SHIFT) /* Push-pull WDT service output */ +# define SCU_HDCR_HIBIO1SEL_PPGPIO (10 << SCU_HDCR_HIBIO1SEL_SHIFT) /* Push-pull GPIO output */ +# define SCU_HDCR_HIBIO1SEL_OD (12 << SCU_HDCR_HIBIO1SEL_SHIFT) /* Open-drain HIB Control output */ +# define SCU_HDCR_HIBIO1SEL_ODWDT (13 << SCU_HDCR_HIBIO1SEL_SHIFT) /* Open-drain WDT service output */ +# define SCU_HDCR_HIBIO1SEL_ODGPIO (14 << SCU_HDCR_HIBIO1SEL_SHIFT) /* Open-drain GPIO output */ + /* Internal 32.768 kHz Clock Source Control Register */ #define SCU_OSCSICTRL_ + /* OSC_ULP Status Register */ -#define SCU_OSCULSTAT_ + +#define SCU_OSCULSTAT_X1D (1 << 0) /* Bit 0: XTAL1 Data Value */ + /* OSC_ULP Control Register */ -#define SCU_OSCULCTRL_ + +#define SCU_OSCULCTRL_X1DEN (1 << 0) /* Bit 0: XTAL1 Data General Purpose Input Enable */ +#define SCU_OSCULCTRL_MODE_SHIFT (4) /* Bits 4-5: Oscillator Mode */ +#define SCU_OSCULCTRL_MODE_MASK (3 << SCU_OSCULCTRL_MODE_SHIFT) +# define SCU_OSCULCTRL_MODE_OPER (0 << SCU_OSCULCTRL_MODE_SHIFT) /* OSC enabled in operation */ +# define SCU_OSCULCTRL_MODE_BYPASS (1 << SCU_OSCULCTRL_MODE_SHIFT) /* OSC enabled in bypass */ +# define SCU_OSCULCTRL_MODE_PDN (2 << SCU_OSCULCTRL_MODE_SHIFT) /* OSC power down */ +# define SCU_OSCULCTRL_MODE_PDNGPI (3 << SCU_OSCULCTRL_MODE_SHIFT) /* OSC power down, GPI possible */ /* Reset SCU Registers */ @@ -592,11 +678,27 @@ /* Oscillator Control SCU Registers */ /* OSC_HP Status Register */ -#define OSCU_OSCHPSTAT_ +#define SCU_OSCHPSTAT_ + /* OSC_HP Control Register */ -#define OSCU_OSCHPCTRL_ + +#define SCU_OSCHPCTRL_X1DEN (1 << 0) /* Bit 0: XTAL1 Data Enable */ +#define SCU_OSCHPCTRL_SHBY (1 << 1) /* Bit 1: Shaper Bypass */ +#define SCU_OSCHPCTRL_GAINSEL_SHIFT (2) /* Bits 2-3: */ +#define SCU_OSCHPCTRL_GAINSEL_MASK (3 << SCU_OSCHPCTRL_GAINSEL_SHIFT) +# define SCU_OSCHPCTRL_GAINSEL(n) ((uint32_t)(n) << SCU_OSCHPCTRL_GAINSEL_SHIFT) +#define SCU_OSCHPCTRL_MODE_SHIFT (4) +#define SCU_OSCHPCTRL_MODE_MASK (3 << SCU_OSCHPCTRL_MODE_SHIFT) +# define SCU_OSCHPCTRL_MODE_XTAL (0 << SCU_OSCHPCTRL_MODE_SHIFT) /* External Crystal Mode */ +# define SCU_OSCHPCTRL_MODE_DIS (1 << SCU_OSCHPCTRL_MODE_SHIFT) /* OSC is disabled */ +# define SCU_OSCHPCTRL_MODE_EXTIN (2 << SCU_OSCHPCTRL_MODE_SHIFT) /* External Input Clock Mode */ +# define SCU_OSCHPCTRL_MODE_DISPSM (3 << SCU_OSCHPCTRL_MODE_SHIFT) /* OSC is disabled, Power-Saving Mode */ +#define SCU_OSCHPCTRL_OSCVAL_SHIFT (16) +#define SCU_OSCHPCTRL_OSCVAL_MASK (15 << SCU_OSCHPCTRL_OSCVAL_SHIFT) +# define SCU_OSCHPCTRL_OSCVAL(n) ((uint32_t)((n)-1) << SCU_OSCHPCTRL_OSCVAL_SHIFT) + /* Clock Calibration Constant Register */ -#define OSCU_CLKCALCONST_ +#define SCU_CLKCALCONST_ /* PLL Control SCU Registers */ From 66d001d0e1ebb8f19deb393666e596715256ac6a Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 16 Mar 2017 09:48:57 -0600 Subject: [PATCH 08/21] XMC4xxx: Initial clock configuration logic. --- arch/arm/src/xmc4/chip/xmc4_flash.h | 203 +++++++++++ arch/arm/src/xmc4/chip/xmc4_memorymap.h | 454 ++++++++++++------------ arch/arm/src/xmc4/chip/xmc4_scu.h | 48 ++- arch/arm/src/xmc4/xmc4_clockconfig.c | 445 +++++++++++++++++++++++ arch/arm/src/xmc4/xmc4_start.c | 46 +++ configs/xmc4500-relax/include/board.h | 8 + 6 files changed, 969 insertions(+), 235 deletions(-) create mode 100644 arch/arm/src/xmc4/chip/xmc4_flash.h diff --git a/arch/arm/src/xmc4/chip/xmc4_flash.h b/arch/arm/src/xmc4/chip/xmc4_flash.h new file mode 100644 index 00000000000..e68e7078e9c --- /dev/null +++ b/arch/arm/src/xmc4/chip/xmc4_flash.h @@ -0,0 +1,203 @@ +/************************************************************************************ + * arch/arm/src/xmc4/chip/xmc4_flash.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Reference: XMC4500 Reference Manual V1.5 2014-07 Microcontrollers. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * May include some logic from sample code provided by Infineon: + * + * Copyright (C) 2011-2015 Infineon Technologies AG. All rights reserved. + * + * Infineon Technologies AG (Infineon) is supplying this software for use with + * Infineon's microcontrollers. This file can be freely distributed within + * development tools that are supporting such microcontrollers. + * + * THIS SOFTWARE IS PROVIDED AS IS. NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, + * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_XMC4_CHIP_XMC4_FLASH_H +#define __ARCH_ARM_SRC_XMC4_CHIP_XMC4_FLASH_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Register Offsets *****************************************************************/ + +/* PMU Registers -- See ID register */ +/* Prefetch Registers -- See PCON register */ + +/* FLASH Registers */ + +#define XMC4_FLASH_ID_OFFSET 0x1008 /* Flash Module Identification Register */ +#define XMC4_FLASH_FSR_OFFSET 0x1010 /* Flash Status Register */ +#define XMC4_FLASH_FCON_OFFSET 0x1014 /* Flash Configuration Register */ +#define XMC4_FLASH_MARP_OFFSET 0x1018 /* Flash Margin Control Register PFLASH */ +#define XMC4_FLASH_PROCON0_OFFSET 0x1020 /* Flash Protection Configuration User 0 */ +#define XMC4_FLASH_PROCON1_OFFSET 0x1024 /* Flash Protection Configuration User 1 */ +#define XMC4_FLASH_PROCON2_OFFSET 0x1028 /* Flash Protection Configuration User 2 */ + +/* Register Addresses ****************************************************************/ + +/* FLASH Registers */ + +#define XMC4_FLASH_ID (XMC4_FLASH0_BASE+XMC4_FLASH_ID_OFFSET) +#define XMC4_FLASH_FSR (XMC4_FLASH0_BASE+XMC4_FLASH_FSR_OFFSET) +#define XMC4_FLASH_FCON (XMC4_FLASH0_BASE+XMC4_FLASH_FCON_OFFSET) +#define XMC4_FLASH_MARP (XMC4_FLASH0_BASE+XMC4_FLASH_MARP_OFFSET) +#define XMC4_FLASH_PROCON0 (XMC4_FLASH0_BASE+XMC4_FLASH_PROCON0_OFFSET) +#define XMC4_FLASH_PROCON1 (XMC4_FLASH0_BASE+XMC4_FLASH_PROCON1_OFFSET) +#define XMC4_FLASH_PROCON2 (XMC4_FLASH0_BASE+XMC4_FLASH_PROCON2_OFFSET) + +/* Register Bit-Field Definitions **************************************************/ + +/* FLASH Registers */ + +/* Flash Module Identification Register */ + +#define FLASH_ID_MOD_REV_SHIFT (0) /* Bits 0-7: Module Revision Number */ +#define FLASH_ID_MOD_REV_MASK (0xff << FLASH_ID_MOD_REV_SHIFT) +#define FLASH_ID_MOD_TYPE_SHIFT (8) /* Bits 8-15: Module Type */ +#define FLASH_ID_MOD_TYPE_MASK (0xff << FLASH_ID_MOD_REV_SHIFT) +#define FLASH_ID_MOD_NUMBER_SHIFT (16) /* Bits 16-31: Module Number Value */ +#define FLASH_ID_MOD_NUMBER_MASK (0xffff << FLASH_ID_MOD_NUMBER_SHIFT) + +/* Flash Status Register */ + +#define FLASH_FSR_PBUSY (1 << 0) /* Bit 0: Program Flash Busy */ +#define FLASH_FSR_FABUSY (1 << 1) /* Bit 1: Flash Array Busy */ +#define FLASH_FSR_PROG (1 << 4) /* Bit 4: Programming State */ +#define FLASH_FSR_ERASE (1 << 5) /* Bit 5: Erase State */ +#define FLASH_FSR_PFPAGE (1 << 6) /* Bit 6: Program Flash in Page Mode */ +#define FLASH_FSR_PFOPER (1 << 8) /* Bit 8: Program Flash Operation Error */ +#define FLASH_FSR_SQER (1 << 10) /* Bit 10: Command Sequence Error */ +#define FLASH_FSR_PROER (1 << 11) /* Bit 11: Protection Error */ +#define FLASH_FSR_PFSBER (1 << 12) /* Bit 12: PFLASH Single-Bit Error and Correction */ +#define FLASH_FSR_PFDBER (1 << 14) /* Bit 14: PFLASH Double-Bit Error */ +#define FLASH_FSR_PROIN (1 << 16) /* Bit 16: Protection Installed */ +#define FLASH_FSR_RPROIN (1 << 18) /* Bit 18: Read Protection Installed */ +#define FLASH_FSR_RPRODIS (1 << 19) /* Bit 19: Read Protection Disable State */ +#define FLASH_FSR_WPROIN0 (1 << 21) /* Bit 21: Sector Write Protection Installed for User 0 */ +#define FLASH_FSR_WPROIN1 (1 << 22) /* Bit 22: Sector Write Protection Installed for User 1 */ +#define FLASH_FSR_WPROIN2 (1 << 23) /* Bit 23: Sector Write Protection Installed for User 2 */ +#define FLASH_FSR_WPRODIS0 (1 << 25) /* Bit 25: Sector Write Protection Disabled for User 0 */ +#define FLASH_FSR_WPRODIS1 (1 << 26) /* Bit 26: Sector Write Protection Disabled for User 1 */ +#define FLASH_FSR_SLM (1 << 28) /* Bit 28: Flash Sleep Mode */ +#define FLASH_FSR_VER (1 << 31) /* Bit 31: Verify Error */ + +/* Flash Configuration Register */ + +#define FLASH_FCON_WSPFLASH_SHIFT (0) /* Bits 0-3: Wait States for read access to PFLASH */ +#define FLASH_FCON_WSPFLASH_MASK (15 << FLASH_FCON_WSPFLASH_SHIFT) +# define FLASH_FCON_WSPFLASH(n) ((uint32_t)((n)-1) << FLASH_FCON_WSPFLASH_SHIFT) +#define FLASH_FCON_WSECPF (1 << 4) /* Bit 4: Wait State for Error Correction of PFLASH */ +#define FLASH_FCON_IDLE (1 << 13) /* Bit 13: Dynamic Flash Idle */ +#define FLASH_FCON_ESLDIS (1 << 14) /* Bit 14: External Sleep Request Disable */ +#define FLASH_FCON_SLEEP (1 << 15) /* Bit 15: Flash SLEEP */ +#define FLASH_FCON_RPA (1 << 16) /* Bit 16: Read Protection Activated */ +#define FLASH_FCON_DCF (1 << 17) /* Bit 17: Disable Code Fetch from Flash Memory */ +#define FLASH_FCON_DDF (1 << 18) /* Bit 18: Disable Any Data Fetch from Flash */ +#define FLASH_FCON_VOPERM (1 << 24) /* Bit 24: Verify and Operation Error Interrupt Mask */ +#define FLASH_FCON_SQERM (1 << 25) /* Bit 25: Command Sequence Error Interrupt Mask */ +#define FLASH_FCON_PROERM (1 << 26) /* Bit 26: Protection Error Interrupt Mask */ +#define FLASH_FCON_PFSBERM (1 << 27) /* Bit 27: PFLASH Single-Bit Error Interrupt Mask */ +#define FLASH_FCON_PFDBERM (1 << 29) /* Bit 29: PFLASH Double-Bit Error Interrupt Mask */ +#define FLASH_FCON_EOBM (1 << 31) /* Bit 31: End of Busy Interrupt Mask */ + +/* Flash Margin Control Register PFLASH */ + +#define FLASH_MARP_MARGIN_SHIFT (0) /* Bits 0-3: PFLASH Margin Selection */ +#define FLASH_MARP_MARGIN_MASK (15 << FLASH_MARP_MARGIN_SHIFT) +#define FLASH_MARP_TRAPDIS (1 << 15) /* Bit 15: PFLASH Double-Bit Error Trap Disable */ + +/* Flash Protection Configuration User 0 */ + +#define FLASH_PROCON0_S0L (1 << 0) /* Bit 0: Sector 0 Locked for Write Protection by User 0 */ +#define FLASH_PROCON0_S1L (1 << 1) /* Bit 1: Sector 1 Locked for Write Protection by User 0 */ +#define FLASH_PROCON0_S2L (1 << 2) /* Bit 2: Sector 2 Locked for Write Protection by User 0 */ +#define FLASH_PROCON0_S3L (1 << 3) /* Bit 3: Sector 3 Locked for Write Protection by User 0 */ +#define FLASH_PROCON0_S4L (1 << 4) /* Bit 4: Sector 4 Locked for Write Protection by User 0 */ +#define FLASH_PROCON0_S5L (1 << 5) /* Bit 5: Sector 5 Locked for Write Protection by User 0 */ +#define FLASH_PROCON0_S6L (1 << 6) /* Bit 6: Sector 6 Locked for Write Protection by User 0 */ +#define FLASH_PROCON0_S7L (1 << 7) /* Bit 7: Sector 7 Locked for Write Protection by User 0 */ +#define FLASH_PROCON0_S8L (1 << 8) /* Bit 8: Sector 8 Locked for Write Protection by User 0 */ +#define FLASH_PROCON0_S9L (1 << 9) /* Bit 9: Sector 9 Locked for Write Protection by User 0 */ +#define FLASH_PROCON0_S10_S11L (1 << 10) /* Bit 10: Sectors 10 and 11 Locked for Write Protection by User 0 */ +#define FLASH_PROCON0_S12_S13L (1 << 11) /* Bit 11: Sectors 12 and 13 Locked for Write Protection by User 0 */ +#define FLASH_PROCON0_S14_S15L (1 << 12) /* Bit 12: Sectors 14 and 15 Locked for Write Protection by User 0 */ +#define FLASH_PROCON0_RPRO (1 << 15) /* Bit 15: Read Protection Configuration */ + +/* Flash Protection Configuration User 1 */ + +#define FLASH_PROCON1_S0L (1 << 0) /* Bit 0: Sector 0 Locked for Write Protection by User 1 */ +#define FLASH_PROCON1_S1L (1 << 1) /* Bit 1: Sector 1 Locked for Write Protection by User 1 */ +#define FLASH_PROCON1_S2L (1 << 2) /* Bit 2: Sector 2 Locked for Write Protection by User 1 */ +#define FLASH_PROCON1_S3L (1 << 3) /* Bit 3: Sector 3 Locked for Write Protection by User 1 */ +#define FLASH_PROCON1_S4L (1 << 4) /* Bit 4: Sector 4 Locked for Write Protection by User 1 */ +#define FLASH_PROCON1_S5L (1 << 5) /* Bit 5: Sector 5 Locked for Write Protection by User 1 */ +#define FLASH_PROCON1_S6L (1 << 6) /* Bit 6: Sector 6 Locked for Write Protection by User 1 */ +#define FLASH_PROCON1_S7L (1 << 7) /* Bit 7: Sector 7 Locked for Write Protection by User 1 */ +#define FLASH_PROCON1_S8L (1 << 8) /* Bit 8: Sector 8 Locked for Write Protection by User 1 */ +#define FLASH_PROCON1_S9L (1 << 9) /* Bit 9: Sector 9 Locked for Write Protection by User 1 */ +#define FLASH_PROCON1_S10_S11L (1 << 10) /* Bit 10: Sectors 10 and 11 Locked for Write Protection by User 1 */ +#define FLASH_PROCON1_S12_S13L (1 << 11) /* Bit 11: Sectors 12 and 13 Locked for Write Protection by User 1 */ +#define FLASH_PROCON1_S14_S15L (1 << 12) /* Bit 12: Sectors 14 and 15 Locked for Write Protection by User 1 */ +#define FLASH_PROCON1_PSR (1 << 16) /* Bit 16: */ + +/* Flash Protection Configuration User 2 */ + +#define FLASH_PROCON2_S0ROM (1 << 0) /* Bit 0: Sector 0 Locked Forever by User 2 */ +#define FLASH_PROCON2_S1ROM (1 << 1) /* Bit 1: Sector 1 Locked Forever by User 2 */ +#define FLASH_PROCON2_S2ROM (1 << 2) /* Bit 2: Sector 2 Locked Forever by User 2 */ +#define FLASH_PROCON2_S3ROM (1 << 3) /* Bit 3: Sector 3 Locked Forever by User 2 */ +#define FLASH_PROCON2_S4ROM (1 << 4) /* Bit 4: Sector 4 Locked Forever by User 2 */ +#define FLASH_PROCON2_S5ROM (1 << 5) /* Bit 5: Sector 5 Locked Forever by User 2 */ +#define FLASH_PROCON2_S6ROM (1 << 6) /* Bit 6: Sector 6 Locked Forever by User 2 */ +#define FLASH_PROCON2_S7ROM (1 << 7) /* Bit 7: Sector 7 Locked Forever by User 2 */ +#define FLASH_PROCON2_S8ROM (1 << 8) /* Bit 8: Sector 8 Locked Forever by User 2 */ +#define FLASH_PROCON2_S9ROM (1 << 9) /* Bit 9: Sector 9 Locked Forever by User 2 */ +#define FLASH_PROCON2_S10_S11ROM (1 << 10) /* Bit 10: Sectors 10 and 11 Locked Forever by User 2 */ +#define FLASH_PROCON2_S12_S13ROM (1 << 11) /* Bit 11: Sectors 12 and 13 Locked Forever by User 2 */ +#define FLASH_PROCON2_S14_S15ROM (1 << 12) /* Bit 12: Sectors 14 and 15 Locked Forever by User 2 */ + +#endif /* __ARCH_ARM_SRC_XMC4_CHIP_XMC4_SCU_H */ diff --git a/arch/arm/src/xmc4/chip/xmc4_memorymap.h b/arch/arm/src/xmc4/chip/xmc4_memorymap.h index 8cf50174b9a..19dd637ab59 100644 --- a/arch/arm/src/xmc4/chip/xmc4_memorymap.h +++ b/arch/arm/src/xmc4/chip/xmc4_memorymap.h @@ -1,227 +1,227 @@ -/************************************************************************************ - * arch/arm/src/xmc4/chip/xmc4_memorymap.h - * - * Copyright (C) 2017 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Reference: XMC4500 Reference Manual V1.5 2014-07 Microcontrollers. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * May include some logic from sample code provided by Infineon: - * - * Copyright (C) 2011-2015 Infineon Technologies AG. All rights reserved. - * - * Infineon Technologies AG (Infineon) is supplying this software for use with - * Infineon's microcontrollers. This file can be freely distributed within - * development tools that are supporting such microcontrollers. - * - * THIS SOFTWARE IS PROVIDED AS IS. NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, - * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_XMC4_CHIP_XMC4_MEMORYMAP_H -#define __ARCH_ARM_SRC_XMC4_CHIP_XMC4_MEMORYMAP_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* Peripheral Memory Map ************************************************************/ -/* Acronyms: - * ADC - Analog to Digital Converter - * CCU - Capture Compare Unit - * DAC - Digital to Analog Converter - * DSD - Delta Sigmoid Demodulator - * ERU - External Request Unit - * FCE - Flexible CRC Engine - * GPDMA - General Purpose DMA - * LEDTS - LED and Touch Sense Control Unit - * PMU - Program Management Unit - * POSIF - Position Interface - * SDMMC - Multi Media Card Interface - * USB - Universal Serial Bus - * USCI - Universal Serial Interface - */ - -#define XMC4_PBA0_BASE 0x40000000 -#define XMC4_VADC_BASE 0x40004000 -#define XMC4_VADC_G0_BASE 0x40004400 -#define XMC4_VADC_G1_BASE 0x40004800 -#define XMC4_VADC_G2_BASE 0x40004c00 -#define XMC4_VADC_G3_BASE 0x40005000 -#define XMC4_DSD_BASE 0x40008000 -#define XMC4_DSD_CH0_BASE 0x40008100 -#define XMC4_DSD_CH1_BASE 0x40008200 -#define XMC4_DSD_CH2_BASE 0x40008300 -#define XMC4_DSD_CH3_BASE 0x40008400 -#define XMC4_CCU40_BASE 0x4000c000 -#define XMC4_CCU40_CC40_BASE 0x4000c100 -#define XMC4_CCU40_CC41_BASE 0x4000c200 -#define XMC4_CCU40_CC42_BASE 0x4000c300 -#define XMC4_CCU40_CC43_BASE 0x4000c400 -#define XMC4_CCU41_BASE 0x40010000 -#define XMC4_CCU41_CC40_BASE 0x40010100 -#define XMC4_CCU41_CC41_BASE 0x40010200 -#define XMC4_CCU41_CC42_BASE 0x40010300 -#define XMC4_CCU41_CC43_BASE 0x40010400 -#define XMC4_CCU42_BASE 0x40014000 -#define XMC4_CCU42_CC40_BASE 0x40014100 -#define XMC4_CCU42_CC41_BASE 0x40014200 -#define XMC4_CCU42_CC42_BASE 0x40014300 -#define XMC4_CCU42_CC43_BASE 0x40014400 -#define XMC4_CCU80_BASE 0x40020000 -#define XMC4_CCU80_CC80_BASE 0x40020100 -#define XMC4_CCU80_CC81_BASE 0x40020200 -#define XMC4_CCU80_CC82_BASE 0x40020300 -#define XMC4_CCU80_CC83_BASE 0x40020400 -#define XMC4_CCU81_BASE 0x40024000 -#define XMC4_CCU81_CC80_BASE 0x40024100 -#define XMC4_CCU81_CC81_BASE 0x40024200 -#define XMC4_CCU81_CC82_BASE 0x40024300 -#define XMC4_CCU81_CC83_BASE 0x40024400 -#define XMC4_POSIF0_BASE 0x40028000 -#define XMC4_POSIF1_BASE 0x4002c000 -#define XMC4_USIC0_BASE 0x40030008 -#define XMC4_USIC0_CH0_BASE 0x40030000 -#define XMC4_USIC0_CH1_BASE 0x40030200 -#define XMC4_ERU1_BASE 0x40044000 - -#define XMC4_PBA1_BASE 0x48000000 -#define XMC4_CCU43_BASE 0x48004000 -#define XMC4_CCU43_CC40_BASE 0x48004100 -#define XMC4_CCU43_CC41_BASE 0x48004200 -#define XMC4_CCU43_CC42_BASE 0x48004300 -#define XMC4_CCU43_CC43_BASE 0x48004400 -#define XMC4_LEDTS0_BASE 0x48010000 -#define XMC4_CAN_BASE 0x48014000 -#define XMC4_CAN_NODE0_BASE 0x48014200 -#define XMC4_CAN_NODE1_BASE 0x48014300 -#define XMC4_CAN_NODE2_BASE 0x48014400 -#define XMC4_CAN_NODE3_BASE 0x48014500 -#define XMC4_CAN_NODE4_BASE 0x48014600 -#define XMC4_CAN_NODE5_BASE 0x48014700 -#define XMC4_CAN_MO_BASE 0x48015000 -#define XMC4_DAC_BASE 0x48018000 -#define XMC4_SDMMC_BASE 0x4801c000 -#define XMC4_USIC1_CH0_BASE 0x48020000 -#define XMC4_USIC1_BASE 0x48020008 -#define XMC4_USIC1_CH1_BASE 0x48020200 -#define XMC4_USIC2_CH0_BASE 0x48024000 -#define XMC4_USIC2_BASE 0x48024008 -#define XMC4_USIC2_CH1_BASE 0x48024200 -#define XMC4_PORT0_BASE 0x48028000 -#define XMC4_PORT1_BASE 0x48028100 -#define XMC4_PORT2_BASE 0x48028200 -#define XMC4_PORT3_BASE 0x48028300 -#define XMC4_PORT4_BASE 0x48028400 -#define XMC4_PORT5_BASE 0x48028500 -#define XMC4_PORT6_BASE 0x48028600 -#define XMC4_PORT7_BASE 0x48028700 -#define XMC4_PORT8_BASE 0x48028800 -#define XMC4_PORT9_BASE 0x48028900 -#define XMC4_PORT14_BASE 0x48028e00 -#define XMC4_PORT15_BASE 0x48028f00 - -#define XMC4_SCU_GENERAL_BASE 0x50004000 -#define XMC4_ETH0_CON_BASE 0x50004040 -#define XMC4_SCU_INTERRUPT_BASE 0x50004074 -#define XMC4_SDMMC_CON_BASE 0x500040b4 -#define XMC4_SCU_PARITY_BASE 0x5000413c -#define XMC4_SCU_TRAP_BASE 0x50004160 -#define XMC4_SCU_POWER_BASE 0x50004200 -#define XMC4_SCU_HIBERNATE_BASE 0x50004300 -#define XMC4_SCU_RESET_BASE 0x50004400 -#define XMC4_SCU_CLK_BASE 0x50004600 -#define XMC4_SCU_OSC_BASE 0x50004700 -#define XMC4_SCU_PLL_BASE 0x50004710 -#define XMC4_ERU0_BASE 0x50004800 -#define XMC4_DLR_BASE 0x50004900 -#define XMC4_RTC_BASE 0x50004a00 -#define XMC4_WDT_BASE 0x50008000 -#define XMC4_ETH0_BASE 0x5000c000 -#define XMC4_USB0_BASE 0x50040000 -#define XMC4_USB0_CH0_BASE 0x50040500 -#define XMC4_USB0_CH1_BASE 0x50040520 -#define XMC4_USB0_CH2_BASE 0x50040540 -#define XMC4_USB0_CH3_BASE 0x50040560 -#define XMC4_USB0_CH4_BASE 0x50040580 -#define XMC4_USB0_CH5_BASE 0x500405a0 -#define XMC4_USB0_CH6_BASE 0x500405c0 -#define XMC4_USB0_CH7_BASE 0x500405e0 -#define XMC4_USB0_CH8_BASE 0x50040600 -#define XMC4_USB0_CH9_BASE 0x50040620 -#define XMC4_USB0_CH10_BASE 0x50040640 -#define XMC4_USB0_CH11_BASE 0x50040660 -#define XMC4_USB0_CH12_BASE 0x50040680 -#define XMC4_USB0_CH13_BASE 0x500406a0 -#define XMC4_USB_EP_BASE 0x50040900 -#define XMC4_USB0_EP1_BASE 0x50040920 -#define XMC4_USB0_EP2_BASE 0x50040940 -#define XMC4_USB0_EP3_BASE 0x50040960 -#define XMC4_USB0_EP4_BASE 0x50040980 -#define XMC4_USB0_EP5_BASE 0x500409a0 -#define XMC4_USB0_EP6_BASE 0x500409c0 -#define XMC4_GPDMA0_CH0_BASE 0x50014000 -#define XMC4_GPDMA0_CH1_BASE 0x50014058 -#define XMC4_GPDMA0_CH2_BASE 0x500140b0 -#define XMC4_GPDMA0_CH3_BASE 0x50014108 -#define XMC4_GPDMA0_CH4_BASE 0x50014160 -#define XMC4_GPDMA0_CH5_BASE 0x500141b8 -#define XMC4_GPDMA0_CH6_BASE 0x50014210 -#define XMC4_GPDMA0_CH7_BASE 0x50014268 -#define XMC4_GPDMA0_BASE 0x500142c0 -#define XMC4_GPDMA1_CH0_BASE 0x50018000 -#define XMC4_GPDMA1_CH1_BASE 0x50018058 -#define XMC4_GPDMA1_CH2_BASE 0x500180b0 -#define XMC4_GPDMA1_CH3_BASE 0x50018108 -#define XMC4_GPDMA1_BASE 0x500182c0 -#define XMC4_FCE_BASE 0x50020000 -#define XMC4_FCE_KE0_BASE 0x50020020 -#define XMC4_FCE_KE1_BASE 0x50020040 -#define XMC4_FCE_KE2_BASE 0x50020060 -#define XMC4_FCE_KE3_BASE 0x50020080 - -#define XMC4_PMU0_BASE 0x58000508 -#define XMC4_FLASH0_BASE 0x58001000 -#define XMC4_PREF_BASE 0x58004000 -#define XMC4_EBU_BASE 0x58008000 - -#define XMC4_PPB_BASE 0xe000e000 - -#endif /* __ARCH_ARM_SRC_XMC4_CHIP_XMC4_SCU_H */ +/************************************************************************************ + * arch/arm/src/xmc4/chip/xmc4_memorymap.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Reference: XMC4500 Reference Manual V1.5 2014-07 Microcontrollers. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * May include some logic from sample code provided by Infineon: + * + * Copyright (C) 2011-2015 Infineon Technologies AG. All rights reserved. + * + * Infineon Technologies AG (Infineon) is supplying this software for use with + * Infineon's microcontrollers. This file can be freely distributed within + * development tools that are supporting such microcontrollers. + * + * THIS SOFTWARE IS PROVIDED AS IS. NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, + * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_XMC4_CHIP_XMC4_MEMORYMAP_H +#define __ARCH_ARM_SRC_XMC4_CHIP_XMC4_MEMORYMAP_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Peripheral Memory Map ************************************************************/ +/* Acronyms: + * ADC - Analog to Digital Converter + * CCU - Capture Compare Unit + * DAC - Digital to Analog Converter + * DSD - Delta Sigmoid Demodulator + * ERU - External Request Unit + * FCE - Flexible CRC Engine + * GPDMA - General Purpose DMA + * LEDTS - LED and Touch Sense Control Unit + * PMU - Program Management Unit + * POSIF - Position Interface + * SDMMC - Multi Media Card Interface + * USB - Universal Serial Bus + * USCI - Universal Serial Interface + */ + +#define XMC4_PBA0_BASE 0x40000000 +#define XMC4_VADC_BASE 0x40004000 +#define XMC4_VADC_G0_BASE 0x40004400 +#define XMC4_VADC_G1_BASE 0x40004800 +#define XMC4_VADC_G2_BASE 0x40004c00 +#define XMC4_VADC_G3_BASE 0x40005000 +#define XMC4_DSD_BASE 0x40008000 +#define XMC4_DSD_CH0_BASE 0x40008100 +#define XMC4_DSD_CH1_BASE 0x40008200 +#define XMC4_DSD_CH2_BASE 0x40008300 +#define XMC4_DSD_CH3_BASE 0x40008400 +#define XMC4_CCU40_BASE 0x4000c000 +#define XMC4_CCU40_CC40_BASE 0x4000c100 +#define XMC4_CCU40_CC41_BASE 0x4000c200 +#define XMC4_CCU40_CC42_BASE 0x4000c300 +#define XMC4_CCU40_CC43_BASE 0x4000c400 +#define XMC4_CCU41_BASE 0x40010000 +#define XMC4_CCU41_CC40_BASE 0x40010100 +#define XMC4_CCU41_CC41_BASE 0x40010200 +#define XMC4_CCU41_CC42_BASE 0x40010300 +#define XMC4_CCU41_CC43_BASE 0x40010400 +#define XMC4_CCU42_BASE 0x40014000 +#define XMC4_CCU42_CC40_BASE 0x40014100 +#define XMC4_CCU42_CC41_BASE 0x40014200 +#define XMC4_CCU42_CC42_BASE 0x40014300 +#define XMC4_CCU42_CC43_BASE 0x40014400 +#define XMC4_CCU80_BASE 0x40020000 +#define XMC4_CCU80_CC80_BASE 0x40020100 +#define XMC4_CCU80_CC81_BASE 0x40020200 +#define XMC4_CCU80_CC82_BASE 0x40020300 +#define XMC4_CCU80_CC83_BASE 0x40020400 +#define XMC4_CCU81_BASE 0x40024000 +#define XMC4_CCU81_CC80_BASE 0x40024100 +#define XMC4_CCU81_CC81_BASE 0x40024200 +#define XMC4_CCU81_CC82_BASE 0x40024300 +#define XMC4_CCU81_CC83_BASE 0x40024400 +#define XMC4_POSIF0_BASE 0x40028000 +#define XMC4_POSIF1_BASE 0x4002c000 +#define XMC4_USIC0_BASE 0x40030008 +#define XMC4_USIC0_CH0_BASE 0x40030000 +#define XMC4_USIC0_CH1_BASE 0x40030200 +#define XMC4_ERU1_BASE 0x40044000 + +#define XMC4_PBA1_BASE 0x48000000 +#define XMC4_CCU43_BASE 0x48004000 +#define XMC4_CCU43_CC40_BASE 0x48004100 +#define XMC4_CCU43_CC41_BASE 0x48004200 +#define XMC4_CCU43_CC42_BASE 0x48004300 +#define XMC4_CCU43_CC43_BASE 0x48004400 +#define XMC4_LEDTS0_BASE 0x48010000 +#define XMC4_CAN_BASE 0x48014000 +#define XMC4_CAN_NODE0_BASE 0x48014200 +#define XMC4_CAN_NODE1_BASE 0x48014300 +#define XMC4_CAN_NODE2_BASE 0x48014400 +#define XMC4_CAN_NODE3_BASE 0x48014500 +#define XMC4_CAN_NODE4_BASE 0x48014600 +#define XMC4_CAN_NODE5_BASE 0x48014700 +#define XMC4_CAN_MO_BASE 0x48015000 +#define XMC4_DAC_BASE 0x48018000 +#define XMC4_SDMMC_BASE 0x4801c000 +#define XMC4_USIC1_CH0_BASE 0x48020000 +#define XMC4_USIC1_BASE 0x48020008 +#define XMC4_USIC1_CH1_BASE 0x48020200 +#define XMC4_USIC2_CH0_BASE 0x48024000 +#define XMC4_USIC2_BASE 0x48024008 +#define XMC4_USIC2_CH1_BASE 0x48024200 +#define XMC4_PORT0_BASE 0x48028000 +#define XMC4_PORT1_BASE 0x48028100 +#define XMC4_PORT2_BASE 0x48028200 +#define XMC4_PORT3_BASE 0x48028300 +#define XMC4_PORT4_BASE 0x48028400 +#define XMC4_PORT5_BASE 0x48028500 +#define XMC4_PORT6_BASE 0x48028600 +#define XMC4_PORT7_BASE 0x48028700 +#define XMC4_PORT8_BASE 0x48028800 +#define XMC4_PORT9_BASE 0x48028900 +#define XMC4_PORT14_BASE 0x48028e00 +#define XMC4_PORT15_BASE 0x48028f00 + +#define XMC4_SCU_GENERAL_BASE 0x50004000 +#define XMC4_ETH0_CON_BASE 0x50004040 +#define XMC4_SCU_INTERRUPT_BASE 0x50004074 +#define XMC4_SDMMC_CON_BASE 0x500040b4 +#define XMC4_SCU_PARITY_BASE 0x5000413c +#define XMC4_SCU_TRAP_BASE 0x50004160 +#define XMC4_SCU_POWER_BASE 0x50004200 +#define XMC4_SCU_HIBERNATE_BASE 0x50004300 +#define XMC4_SCU_RESET_BASE 0x50004400 +#define XMC4_SCU_CLK_BASE 0x50004600 +#define XMC4_SCU_OSC_BASE 0x50004700 +#define XMC4_SCU_PLL_BASE 0x50004710 +#define XMC4_ERU0_BASE 0x50004800 +#define XMC4_DLR_BASE 0x50004900 +#define XMC4_RTC_BASE 0x50004a00 +#define XMC4_WDT_BASE 0x50008000 +#define XMC4_ETH0_BASE 0x5000c000 +#define XMC4_USB0_BASE 0x50040000 +#define XMC4_USB0_CH0_BASE 0x50040500 +#define XMC4_USB0_CH1_BASE 0x50040520 +#define XMC4_USB0_CH2_BASE 0x50040540 +#define XMC4_USB0_CH3_BASE 0x50040560 +#define XMC4_USB0_CH4_BASE 0x50040580 +#define XMC4_USB0_CH5_BASE 0x500405a0 +#define XMC4_USB0_CH6_BASE 0x500405c0 +#define XMC4_USB0_CH7_BASE 0x500405e0 +#define XMC4_USB0_CH8_BASE 0x50040600 +#define XMC4_USB0_CH9_BASE 0x50040620 +#define XMC4_USB0_CH10_BASE 0x50040640 +#define XMC4_USB0_CH11_BASE 0x50040660 +#define XMC4_USB0_CH12_BASE 0x50040680 +#define XMC4_USB0_CH13_BASE 0x500406a0 +#define XMC4_USB_EP_BASE 0x50040900 +#define XMC4_USB0_EP1_BASE 0x50040920 +#define XMC4_USB0_EP2_BASE 0x50040940 +#define XMC4_USB0_EP3_BASE 0x50040960 +#define XMC4_USB0_EP4_BASE 0x50040980 +#define XMC4_USB0_EP5_BASE 0x500409a0 +#define XMC4_USB0_EP6_BASE 0x500409c0 +#define XMC4_GPDMA0_CH0_BASE 0x50014000 +#define XMC4_GPDMA0_CH1_BASE 0x50014058 +#define XMC4_GPDMA0_CH2_BASE 0x500140b0 +#define XMC4_GPDMA0_CH3_BASE 0x50014108 +#define XMC4_GPDMA0_CH4_BASE 0x50014160 +#define XMC4_GPDMA0_CH5_BASE 0x500141b8 +#define XMC4_GPDMA0_CH6_BASE 0x50014210 +#define XMC4_GPDMA0_CH7_BASE 0x50014268 +#define XMC4_GPDMA0_BASE 0x500142c0 +#define XMC4_GPDMA1_CH0_BASE 0x50018000 +#define XMC4_GPDMA1_CH1_BASE 0x50018058 +#define XMC4_GPDMA1_CH2_BASE 0x500180b0 +#define XMC4_GPDMA1_CH3_BASE 0x50018108 +#define XMC4_GPDMA1_BASE 0x500182c0 +#define XMC4_FCE_BASE 0x50020000 +#define XMC4_FCE_KE0_BASE 0x50020020 +#define XMC4_FCE_KE1_BASE 0x50020040 +#define XMC4_FCE_KE2_BASE 0x50020060 +#define XMC4_FCE_KE3_BASE 0x50020080 + +#define XMC4_PMU0_BASE 0x58000500 +#define XMC4_FLASH0_BASE 0x58001000 +#define XMC4_PREF_BASE 0x58004000 +#define XMC4_EBU_BASE 0x58008000 + +#define XMC4_PPB_BASE 0xe000e000 + +#endif /* __ARCH_ARM_SRC_XMC4_CHIP_XMC4_SCU_H */ diff --git a/arch/arm/src/xmc4/chip/xmc4_scu.h b/arch/arm/src/xmc4/chip/xmc4_scu.h index 8f6f89cc4a9..e08a64a48c0 100644 --- a/arch/arm/src/xmc4/chip/xmc4_scu.h +++ b/arch/arm/src/xmc4/chip/xmc4_scu.h @@ -626,18 +626,26 @@ #define SCU_SYSCLKCR_SYSDIV_MASK (0xff << SCU_CLK_SYSCLKCR_SYSDIV_SHIFT) # define SCU_SYSCLKCR_SYSDIV(n) ((uint32_t)((n)-1) << SCU_CLK_SYSCLKCR_SYSDIV_SHIFT) -#define SCU_SYSCLKCR_SYSSEL (1 << 16) /* Bit 16: System Clock Selection Value */ -# define SCU_SYSCLKCR_SYSSEL_OFI (0) /* 0=OFI clock */ -# define SCU_SYSCLKCR_SYSSEL_PLL (1 << 16) /* 1=PLL clock */ +#define SCU_SYSCLKCR_SYSSEL (1 << 16) /* Bit 16: System Clock Selection Value */ +# define SCU_SYSCLKCR_SYSSEL_OFI (0) /* 0=OFI clock */ +# define SCU_SYSCLKCR_SYSSEL_PLL (1 << 16) /* 1=PLL clock */ /* CPU Clock Control */ -#define SCU_CPUCLKCR_CPUDIV (1 << 0) /* Bit 0: CPU Clock Divider Enable */ +#define SCU_CPUCLKCR_CPUDIV (1 << 0) /* Bit 0: CPU Clock Divider Enable */ /* Peripheral Bus Clock Control */ #define SCU_PBCLKCR_ + /* USB Clock Control */ -#define SCU_USBCLKCR_ + +#define SCU_USBCLKCR_USBDIV_SHIFT (0) /* Bits 0-2: USB Clock Divider Value */ +#define SCU_USBCLKCR_USBDIV_MASK (7 << SCU_CLK_USBCLKCR_USBDIV_SHIFT) +# define SCU_SYSCLKCR_USBDIV(n) ((uint32_t)((n)-1) << SCU_CLK_USBCLKCR_USBDIV_SHIFT) +#define SCU_USBCLKCR_USBSEL (1 << 16) /* Bit 16: USB Clock Selection Value */ +# define SCU_USBCLKCR_USBSEL_USBPLL (0) /* 0=USB PLL Clock */ +# define SCU_USBCLKCR_USBSEL_PLL (1 << 16) /* 1= PLL Clock */ + /* EBU Clock Control */ #define SCU_EBUCLKCR_ /* CCU Clock Control */ @@ -752,10 +760,34 @@ # define SCU_PLLCON2_K1INSEL_OFI (1 << 8) /* 1=Backup clock source selected */ /* USB PLL Status Register */ -#define SCU_USBPLLSTAT_ + +#define SCU_USBPLLSTAT_VCOBYST (1 << 0) /* Bit 0: VCO Bypass Status */ +#define SCU_USBPLLSTAT_PWDSTAT (1 << 1) /* Bit 1: PLL Power-saving Mode Status */ +#define SCU_USBPLLSTAT_VCOLOCK (1 << 2) /* Bit 2: PLL VCO Lock Status */ +#define SCU_USBPLLSTAT_BY (1 << 6) /* Bit 6: Bypass Mode Status */ +#define SCU_USBPLLSTAT_VCOLOCKED (1 << 7) /* Bit 7: PLL LOCK Status */ + /* USB PLL Control Register */ -#define SCU_USBPLLCON_ + +#define SCU_USBPLLCON_VCOBYP (1 << 0) /* Bit 0: VCO Bypass */ +#define SCU_USBPLLCON_VCOPWD (1 << 1) /* Bit 1: VCO Power Saving Mode */ +#define SCU_USBPLLCON_VCOTR (1 << 2) /* Bit 2: VCO Trim Control */ +#define SCU_USBPLLCON_FINDIS (1 << 4) /* Bit 4: Disconnect Oscillator from VCO */ +#define SCU_USBPLLCON_OSCDISCDIS (1 << 6) /* Bit 6: Oscillator Disconnect Disable */ +#define SCU_USBPLLCON_NDIV_SHIFT (8) /* Bits 8-14: N-Divider Val */ +#define SCU_USBPLLCON_NDIV_MASK (0x7f << SCU_USBPLLCON_NDIV_SHIFT) +# define SCU_USBPLLCON_NDIV(n) ((uint32_t)((n)-1) << SCU_USBPLLCON_NDIV_SHIFT) +#define SCU_USBPLLCON_PLLPWD (1 << 16) /* Bit 16: PLL Power Saving Mode */ +#define SCU_USBPLLCON_RESLD (1 << 18) /* Bit 18: Restart VCO Lock Detection */ +#define SCU_USBPLLCON_PDIV_SHIFT (24) /* Bits 24-27: P-Divider Value */ +#define SCU_USBPLLCON_PDIV_MASK (15 << SCU_USBPLLCON_PDIV_SHIFT) +# define SCU_USBPLLCON_PDIV(n) ((uint32_t)((n)-1) << SCU_USBPLLCON_PDIV_SHIFT) + /* Clock Multiplexing Status Register */ -#define SCU_CLKMXSTAT_ + +#define SCU_CLKMXSTAT_SYSCLKMUX_SHIFT (0) /* Bits 0-1: System Clock Multiplexing Status */ +#define SCU_CLKMXSTAT_SYSCLKMUX_MASK (3 << SCU_CLKMXSTAT_SYSCLKMUX_SHIFT) +# define SCU_CLKMXSTAT_SYSCLKMUX_OFI (1 << SCU_CLKMXSTAT_SYSCLKMUX_SHIFT) +# define SCU_CLKMXSTAT_SYSCLKMUX_PLL (2 << SCU_CLKMXSTAT_SYSCLKMUX_SHIFT) #endif /* __ARCH_ARM_SRC_XMC4_CHIP_XMC4_SCU_H */ diff --git a/arch/arm/src/xmc4/xmc4_clockconfig.c b/arch/arm/src/xmc4/xmc4_clockconfig.c index d7d5a8bc7df..6667ceca861 100644 --- a/arch/arm/src/xmc4/xmc4_clockconfig.c +++ b/arch/arm/src/xmc4/xmc4_clockconfig.c @@ -56,6 +56,7 @@ #include #include "up_arch.h" +#include "chip/xmc4_scu.h" #include @@ -63,10 +64,77 @@ * Pre-processor Definitions ****************************************************************************/ +/* Oscilator reference frequency */ + +#define FOSCREF (2500000U) + +/* Loop delays at different CPU frequencies */ + +#define DELAY_CNT_50US_50MHZ (2500) +#define DELAY_CNT_150US_50MHZ (7500) +#define DELAY_CNT_50US_48MHZ (2400) +#define DELAY_CNT_50US_72MHZ (3600) +#define DELAY_CNT_50US_96MHZ (4800) +#define DELAY_CNT_50US_120MHZ (6000) +#define DELAY_CNT_50US_144MHZ (7200) + +/* PLL settings */ + +#define SCU_PLLSTAT_OSC_USABLE \ + (SCU_PLLSTAT_PLLHV | SCU_PLLSTAT_PLLLV | SCU_PLLSTAT_PLLSP) + +#ifndef BOARD_PLL_CLOCKSRC_XTAL +# define VCO ((BOARD_XTAL_FREQUENCY / BOARD_PLL_PDIV) * BOARD_PLL_NDIV) +#else /* BOARD_PLL_CLOCKSRC_XTAL */ + +# define BOARD_PLL_PDIV 2 +# define BOARD_PLL_NDIV 24 +# define BOARD_PLL_K2DIV 1 + +# define VCO ((OFI_FREQUENCY / BOARD_PLL_PDIV) * BOARD_PLL_NDIV) + +#endif /* !BOARD_PLL_CLOCKSRC_XTAL */ + +#define PLL_K2DIV_24MHZ (VCO / OFI_FREQUENCY) +#define PLL_K2DIV_48MHZ (VCO / 48000000) +#define PLL_K2DIV_72MHZ (VCO / 72000000) +#define PLL_K2DIV_96MHZ (VCO / 96000000) +#define PLL_K2DIV_120MHZ (VCO / 120000000) + +#define CLKSET_VALUE (0x00000000) +#define SYSCLKCR_VALUE (0x00010001) +#define CPUCLKCR_VALUE (0x00000000) +#define PBCLKCR_VALUE (0x00000000) +#define CCUCLKCR_VALUE (0x00000000) +#define WDTCLKCR_VALUE (0x00000000) +#define EBUCLKCR_VALUE (0x00000003) +#define USBCLKCR_VALUE (0x00010000) +#define EXTCLKCR_VALUE (0x01200003) + +#if ((USBCLKCR_VALUE & SCU_USBCLKCR_USBSEL) == SCU_USBCLKCR_USBSEL_USBPLL) +# define USB_DIV 3 +#else +# define USB_DIV 5 +#endif + /**************************************************************************** * Private Functions ****************************************************************************/ +/**************************************************************************** + * Name: delay + ****************************************************************************/ + +static void delay(uint32_t cycles) +{ + volatile uint32_t i; + + for (i = 0; i < cycles ;++i) + { + __asm__ __volatile__ ("nop"); + } +} + /**************************************************************************** * Public Functions ****************************************************************************/ @@ -83,6 +151,383 @@ void xmc4_clock_configure(void) { + uint32_t regval; + uint32_t bitset; + + /* Disable and clear OSC_HP Oscillator Watchdog, System VCO Lock, USB VCO + * Lock, and OSC_ULP Oscillator Watchdog traps. + */ + + bitset = SCU_TRAP_SOSCWDGT | SCU_TRAP_SVCOLCKT | SCU_TRAP_UVCOLCKT | + SCU_TRAP_ULPWDGT; + + regval = getreg32(XMC4_SCU_TRAPDIS); + regval |= bitset; + putreg32(regval, XMC4_SCU_TRAPDIS); + putreg32(bitset, XMC4_SCU_TRAPCLR); + +#ifdef BOARD_FOFI_CALIBRATION + /* Enable factory calibration */ + + regval = getreg32(XMC4_SCU_PLLCON0); + regval |= SCU_PLLCON0_FOTR; + putreg(regval, XMC4_SCU_PLLCON0); +#else + /* Automatic calibration uses the fSTDBY */ + + /* Enable HIB domain */ + /* Power up HIB domain if and only if it is currently powered down */ + + regval = getreg32(XMC4_SCU_PWRSTAT); + if ((regval & SCU_PWR_HIBEN) == 0) + { + regval = getreg32(XMC4_SCU_PWRSET); + regval |= SCU_PWR_HIBEN; + putreg32(regval, XMC4_SCU_PWRSTAT); + + /* Wait until HIB domain is enabled */ + + while((getreg32(XMC4_SCU_PWRSTAT) & SCU_PWR_HIBEN) == 0) + { + } + } + + /* Remove the reset only if HIB domain were in a state of reset */ + + regval = getreg32(XMC4_SCU_RSTSTAT); + if ((regval & SCU_RSTSTAT_HIBRS) ! = 0) + { + regval = getreg32(XMC4_SCU_RSTSTAT); + SCU_RESET->RSTCLR |= SCU_RESET_RSTCLR_HIBRS_Msk; + delay(DELAY_CNT_150US_50MHZ); + } + +#ifdef BOARD_STDBY_CLOCKSRC_OSCULP + /* Enable OSC_ULP */ + + regval = getreg32(XMC4_SCU_OSCULCTRL); + if ((regval & SCU_OSCULCTRL_MODE_MASK) != 0) + { + /* Check SCU_MIRRSTS to ensure that no transfer over serial interface + * is pending. + */ + + while ((getreg32(XMC4_SCU_MIRRSTS) & SCU_MIRRSTS_OSCULCTRL) != 0) + { + } + + /* Enable OSC_ULP */ + + regval &= ~SCU_OSCULCTRL_MODE_MASK; + putreg32(regval, XMC4_SCU_OSCULCTRL); + + /* Check if the clock is OK using OSCULP Oscillator Watchdog */ + + while ((getreg32(XMC4_SCU_MIRRSTS) & SCU_MIRRSTS_HDCR) != 0) + { + } + + regval = getreg32(XMC4_SCU_HDCR); + regval |= SCU_HDCR_ULPWDGEN; + putreg32(regval, XMC4_SCU_HDCR) + + /* Wait till clock is stable */ + + do + { + /* Check SCU_MIRRSTS to ensure that no transfer over serial interface + * is pending. + */ + + while ((getreg32(XMC4_SCU_MIRRSTS) & SCU_MIRRSTS_HDCLR) != 0) + { + } + + putreg32(SCU_HDCLR_ULPWDG, XMC4_SCU_HDCLR) + delay(DELAY_CNT_50US_50MHZ); + } + while ((getreg32(XMC4_SCU_HDSTAT) & SCU_HDSTAT_ULPWDG) != 0); + } + + /* Now OSC_ULP is running and can be used */ + + while ((getreg32(XMC4_SCU_MIRRSTS) & SCU_MIRRSTS_HDCR) != 0) + { + } + + /* Select OSC_ULP as the clock source for RTC and STDBY */ + + regval = getreg32(XMC4_SCU_HDCR); + regval |= (SCU_HDCR_RCS_ULP | SCU_HDCR_STDBYSEL_ULP); + putreg32(regval, XMC4_SCU_HDCR) + + regval = getreg32(XMC4_SCU_TRAPDIS); + regval &= ~SCU_TRAP_ULPWDGT; + putreg32(regval, XMC4_SCU_TRAPDIS); + +#endif /* BOARD_STDBY_CLOCKSRC_OSCULP */ + + /* Enable automatic calibration of internal fast oscillator */ + + regval = getreg32(XMC4_SCU_PLLCON0); + regval |= SCU_PLLCON0_AOTREN; + putreg(regval, XMC4_SCU_PLLCON0); + +#endif /* BOARD_FOFI_CALIBRATION */ + + delay(DELAY_CNT_50US_50MHZ); + +#if BOARD_ENABLE_PLL + + /* Enable PLL */ + + regval = getreg32(XMC4_SCU_PLLCON0); + regval &= ~(SCU_PLLCON0_VCOPWD | SCU_PLLCON0_PLLPWD); + putreg(regval, XMC4_SCU_PLLCON0); + +#ifdef BOARD_PLL_CLOCKSRC_XTAL + /* Enable OSC_HP */ + + if ((getreg32(XMC4_SCU_OSCHPCTRL) & SCU_OSCHPCTRL_MODE_MASK) != 0U) + { + regval = getreg32(XMC4_SCU_OSCHPCTRL); + regval &= ~(SCU_OSCHPCTRL_MODE_MASK | SCU_OSCHPCTRL_OSCVAL_MASK); + regval |= ((OSCHP_GetFrequency() / FOSCREF) - 1) << SCU_OSCHPCTRL_OSCVAL_SHIFT; + putreg32(regval, XMC4_SCU_OSCHPCTRL); + + /* Select OSC_HP clock as PLL input */ + + regval = getreg32(XMC4_SCU_PLLCON2); + regval &= ~SCU_PLLCON2_PINSEL; + putreg32(regval, XMC4_SCU_PLLCON2); + + /* Restart OSC Watchdog */ + + regval = getreg32(XMC4_SCU_PLLCON0); + regval &= ~SCU_PLLCON0_OSCRES; + putreg(regval, XMC4_SCU_PLLCON0); + + /* Wait till OSC_HP output frequency is usable */ + + while ((getreg32(XMC4_SCU_PLLSTAT) & SCU_PLLSTAT_OSC_USABLE) != SCU_PLLSTAT_OSC_USABLE) + { + } + + regval = getreg32(SCU_TRAP_SOSCWDGT); + regval &= ~bitset; + putreg32(regval, SCU_TRAP_SOSCWDGT); + } +#else /* BOARD_PLL_CLOCKSRC_XTAL */ + + /* Select backup clock as PLL input */ + + regval = getreg32(XMC4_SCU_PLLCON2); + regval |= SCU_PLLCON2_PINSEL; + putreg32(regval, XMC4_SCU_PLLCON2); +#endif + + /* Go to bypass the Main PLL */ + + regval = getreg32(XMC4_SCU_PLLCON0); + regval |= SCU_PLLCON0_VCOBYP; + putreg(regval, XMC4_SCU_PLLCON0); + + /* Disconnect Oscillator from PLL */ + + regval |= SCU_PLLCON0_FINDIS; + putreg(regval, XMC4_SCU_PLLCON0); + + /* Setup divider settings for main PLL */ + + regval = (SCU_PLLCON1_NDIV(BOARD_PLL_NDIV) | + SCU_PLLCON1_K2DIV(PLL_K2DIV_24MHZ) | + SCU_PLLCON1_PDIV(BOARD_PLL_PDIV); + putreg32(regval, XMC4_SCU_PLLCON1); + + /* Set OSCDISCDIS */ + + regval = getreg32(XMC4_SCU_PLLCON0); + regval |= SCU_PLLCON0_OSCDISCDIS; + putreg(regval, XMC4_SCU_PLLCON0); + + /* Connect Oscillator to PLL */ + + regval = getreg32(XMC4_SCU_PLLCON0); + regval &= ~SCU_PLLCON0_FINDIS; + putreg(regval, XMC4_SCU_PLLCON0); + + /* Restart PLL Lock detection */ + + regval |= SCU_PLLCON0_RESLD; + putreg(regval, XMC4_SCU_PLLCON0); + + /* wait for PLL Lock at 24MHz*/ + + while ((getreg32(XMC4_SCU_PLLSTAT) & SCU_PLLSTAT_VCOLOCK) == 0) + { + } + + /* Disable bypass- put PLL clock back */ + + regval = getreg32(XMC4_SCU_PLLCON0); + regval &= ~SCU_PLLCON0_VCOBYP; + putreg(regval, XMC4_SCU_PLLCON0); + + /* Wait for normal mode */ + + while ((getreg32(XMC4_SCU_PLLSTAT) & SCU_PLLSTAT_VCOBYST) != 0) + { + } + + regval = getreg32(XMC4_SCU_TRAPDIS); + regval &= ~SCU_TRAP_UVCOLCKT; + putreg32(regval, XMC4_SCU_TRAPDIS); +#endif /* BOARD_ENABLE_PLL */ + + /* Before scaling to final frequency we need to setup the clock dividers */ + + putreg32(SYSCLKCR_VALUE, XMC4_SCU_SYSCLKCR); + putreg32(PBCLKCR_VALUE, XMC4_SCU_PBCLKCR); + putreg32(CPUCLKCR_VALUE, XMC4_SCU_CPUCLKCR); + putreg32(CCUCLKCR_VALUE, XMC4_SCU_CCUCLKCR); + putreg32(WDTCLKCR_VALUE, XMC4_SCU_WDTCLKCR); + putreg32(EBUCLKCR_VALUE, XMC4_SCU_EBUCLKCR); + putreg32(USBCLKCR_VALUE | USB_DIV, XMC4_SCU_USBCLKCR); + putreg32(EXTCLKCR_VALUE, EXTCLKCR); + +#if BOARD_ENABLE_PLL + /* PLL frequency stepping...*/ + /* Reset OSCDISCDIS */ + + regval = getreg32(XMC4_SCU_PLLCON0); + regval &= ~SCU_PLLCON0_OSCDISCDIS; + putreg(regval, XMC4_SCU_PLLCON0); + + regval = (SCU_PLLCON1_NDIV(BOARD_PLL_NDIV) | + SCU_PLLCON1_K2DIV(PLL_K2DIV_48MHZ) | + SCU_PLLCON1_PDIV(BOARD_PLL_PDIV)); + putreg32(regval, XMC4_SCU_PLLCON1); + + delay(DELAY_CNT_50US_48MHZ); + + regval = (SCU_PLLCON1_NDIV(BOARD_PLL_NDIV) | + SCU_PLLCON1_K2DIV(PLL_K2DIV_72MHZ) | + SCU_PLLCON1_PDIV(BOARD_PLL_PDIV)); + putreg32(regval, XMC4_SCU_PLLCON1); + + delay(DELAY_CNT_50US_72MHZ); + + regval = (SCU_PLLCON1_NDIV(BOARD_PLL_NDIV) | + SCU_PLLCON1_K2DIV(PLL_K2DIV_96MHZ) | + SCU_PLLCON1_PDIV(BOARD_PLL_PDIV)); + putreg32(regval, XMC4_SCU_PLLCON1); + + delay(DELAY_CNT_50US_96MHZ); + + regval = (SCU_PLLCON1_NDIV(BOARD_PLL_NDIV) | + SCU_PLLCON1_K2DIV(PLL_K2DIV_120MHZ) | + SCU_PLLCON1_PDIV(BOARD_PLL_PDIV)); + putreg32(regval, XMC4_SCU_PLLCON1); + + delay(DELAY_CNT_50US_120MHZ); + + regval = (SCU_PLLCON1_NDIV(BOARD_PLL_NDIV) | + SCU_PLLCON1_K2DIV(BOARD_PLL_K2DIV) | + SCU_PLLCON1_PDIV(BOARD_PLL_PDIV)); + putreg32(regval, XMC4_SCU_PLLCON1); + + delay(DELAY_CNT_50US_144MHZ); + +#endif /* BOARD_ENABLE_PLL */ + +#if BOARD_ENABLE_USBPLL + /* Enable USB PLL first */ + + regval = getreg32(XMC4_SCU_USBPLLCON); + regval &= ~(SCU_USBPLLCON_VCOPWD | SCU_USBPLLCON_PLLPWD); + getreg32(regval, XMC4_SCU_USBPLLCON); + + /* USB PLL uses as clock input the OSC_HP */ + /* check and if not already running enable OSC_HP */ + + if ((getreg32(XMC4_SCU_OSCHPCTRL) & SCU_OSCHPCTRL_MODE_MASK) != 0U) + { + /* Check if Main PLL is switched on for OSC WDG */ + + regval = getreg32(XMC4_SCU_PLLCON0); + if ((regval & (SCU_PLLCON0_VCOPWD | SCU_PLLCON0_PLLPWD)) != 0) + { + /* Enable PLL first */ + + regval = getreg32(XMC4_SCU_PLLCON0); + regval &= ~(SCU_PLLCON0_VCOPWD | SCU_PLLCON0_PLLPWD); + putreg(regval, XMC4_SCU_PLLCON0); + } + + regval = getreg32(XMC4_SCU_OSCHPCTRL); + regval &= ~(SCU_OSCHPCTRL_MODE_MASK | SCU_OSCHPCTRL_OSCVAL_MASK); + regval |= ((OSCHP_GetFrequency() / FOSCREF) - 1) << SCU_OSCHPCTRL_OSCVAL_SHIFT; + putreg32(regval, XMC4_SCU_OSCHPCTRL); + + /* Restart OSC Watchdog */ + + regval = getreg32(XMC4_SCU_PLLCON0); + regval &= ~SCU_PLLCON0_OSCRES; + putreg(regval, XMC4_SCU_PLLCON0); + + /* Wait till OSC_HP output frequency is usable */ + + while ((getreg32(XMC4_SCU_PLLSTAT) & SCU_PLLSTAT_OSC_USABLE) != SCU_PLLSTAT_OSC_USABLE) + { + } + } + + /* Setup USB PLL */ + /* Go to bypass the USB PLL */ + + regval = getreg32(XMC4_SCU_USBPLLCON); + regval |= SCU_USBPLLCON_VCOBYP; + putreg32(regval, XMC4_SCU_USBPLLCON); + + /* Disconnect Oscillator from USB PLL */ + + regval |= SCU_USBPLLCON_FINDIS; + putreg32(regval, XMC4_SCU_USBPLLCON); + + /* Setup Divider settings for USB PLL */ + + regval = (SCU_USBPLLCON_NDIV(BOARD_USB_NDIV) | SCU_USBPLLCON_PDIV(BOARD_USB_PDIV)); + putreg32(regval, XMC4_SCU_USBPLLCON); + + /* Set OSCDISCDIS */ + + regval |= SCU_USBPLLCON_OSCDISCDIS; + putreg32(regval, XMC4_SCU_USBPLLCON); + + /* Connect Oscillator to USB PLL */ + + regval &= ~SCU_USBPLLCON_FINDIS; + putreg32(regval, XMC4_SCU_USBPLLCON); + + /* Restart PLL Lock detection */ + + regval |= SCU_USBPLLCON_RESLD; + putreg32(regval, XMC4_SCU_USBPLLCON); + + /* Wait for PLL Lock */ + + while ((getreg32(XMC4_SCU_USBPLLSTAT) & SCU_USBPLLSTAT_VCOLOCK) == 0) + { + } + + regval = getreg32(XMC4_SCU_TRAPDIS); + regval &= ~SCU_TRAP_UVCOLCKT; + putreg32(regval, XMC4_SCU_TRAPDIS); +#endif + + /* Enable selected clocks */ + + putreg32(CLKSET_VALUE, XMC4_SCU_CLKSET) } /**************************************************************************** diff --git a/arch/arm/src/xmc4/xmc4_start.c b/arch/arm/src/xmc4/xmc4_start.c index 77e792847e9..e712f97dd37 100644 --- a/arch/arm/src/xmc4/xmc4_start.c +++ b/arch/arm/src/xmc4/xmc4_start.c @@ -48,6 +48,7 @@ #include "up_arch.h" #include "up_internal.h" +#include "chip/xmc4_flash.h" #include "xmc4_userspace.h" @@ -62,6 +63,8 @@ #ifdef CONFIG_ARCH_FPU static inline void xmc4_fpu_config(void); #endif +static inline void xmc4_unaligned(void); +static inline void xmc4_flash_waitstates(void); #ifdef CONFIG_STACK_COLORATION static void go_os_start(void *pv, unsigned int nbytes) __attribute__ ((naked, no_instrument_function, noreturn)); @@ -214,6 +217,41 @@ static inline void xmc4_fpu_config(void) # define xmc4_fpu_config() #endif +/**************************************************************************** + * Name: xmc4_unaligned + * + * Description: + * Enable unaligned memory access by setting SCB_CCR.UNALIGN_TRP = 0 + * + ****************************************************************************/ + +static inline void xmc4_unaligned(void) +{ + uint32_t regval; + + regval = getreg32(NVIC_CFGCON); + regval &= ~NVIC_CFGCON_UNALIGNTRP; + putreg32(regval, NVIC_CFGCON); +} + +/**************************************************************************** + * Name: xmc4_flash_waitstates + * + * Description: + * Enable unaligned memory access by setting SCB_CCR.UNALIGN_TRP = 0 + * + ****************************************************************************/ + +static inline void xmc4_flash_waitstates(void) +{ + uint32_t regval; + + regval = getreg32(XMC4_FLASH_FCON); + regval &= ~FLASH_FCON_WSPFLASH_MASK; + regval |= FLASH_FCON_WSPFLASH(BOARD_FLASH_WS); + putreg32(regval, XMC4_FLASH_FCON); +} + /**************************************************************************** * Name: go_os_start * @@ -281,6 +319,10 @@ void __start(void) xmc4_wddisable(); + /* Enable unaligned memory access */ + + xmc4_unaligned(); + /* Clear .bss. We'll do this inline (vs. calling memset) just to be * certain that there are no issues with the state of global variables. */ @@ -314,6 +356,10 @@ void __start(void) } #endif + /* Set FLASH wait states prior to the configuration of clocking */ + + xmc4_flash_waitstates(); + /* Perform clock and Kinetis module initialization (This depends on * RAM functions having been copied to RAM). */ diff --git a/configs/xmc4500-relax/include/board.h b/configs/xmc4500-relax/include/board.h index a448469bca7..f3616a21e2c 100644 --- a/configs/xmc4500-relax/include/board.h +++ b/configs/xmc4500-relax/include/board.h @@ -65,6 +65,8 @@ * fOFI = 24MHz => fWDT = 24MHz */ +#undef BOARD_FOFI_CALIBRATION /* Enable factory calibration */ + /* On-board crystals * * NOTE: Only the XMC4500 Relax Kit-V1 provides the 32.768KHz RTC crystal. It @@ -87,6 +89,7 @@ * = 288MHz */ +#define BOARD_ENABLE_PLL 1 #define BOARD_PLL_PDIV 2 #define BOARD_PLL_NDIV 48 #define BOARD_PLL_K2DIV 1 @@ -119,9 +122,14 @@ * fUSBPLLVCO <= 520 MHz */ +#undef BOARD_ENABLE_USBPLL #define BOARD_USB_PDIV 2 #define BOARD_USB_NDIV 64 +/* FLASH wait states */ + +#define BOARD_FLASH_WS 5 + /************************************************************************************ * Public Data ************************************************************************************/ From fe610e7a1d793919f14aaa7f01b69659c51220ec Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 16 Mar 2017 10:52:01 -0600 Subject: [PATCH 09/21] XMC4500 Relax: Add basic board support infrastructure of Infineon XMC4500 Relax Lite v1 --- arch/arm/Kconfig | 25 +- arch/arm/src/xmc4/Kconfig | 2 +- configs/Kconfig | 13 + configs/README.txt | 3 + configs/xmc4500-relax/Kconfig | 4 + configs/xmc4500-relax/nsh/Make.defs | 128 +++ configs/xmc4500-relax/nsh/defconfig | 1038 +++++++++++++++++++++ configs/xmc4500-relax/nsh/setenv.sh | 77 ++ configs/xmc4500-relax/src/Makefile | 55 ++ configs/xmc4500-relax/src/xmc4500-relax.h | 78 ++ configs/xmc4500-relax/src/xmc4_appinit.c | 80 ++ configs/xmc4500-relax/src/xmc4_autoleds.c | 80 ++ configs/xmc4500-relax/src/xmc4_boot.c | 91 ++ configs/xmc4500-relax/src/xmc4_bringup.c | 65 ++ configs/xmc4500-relax/src/xmc4_buttons.c | 78 ++ configs/xmc4500-relax/src/xmc4_userleds.c | 75 ++ 16 files changed, 1879 insertions(+), 13 deletions(-) create mode 100644 configs/xmc4500-relax/Kconfig create mode 100644 configs/xmc4500-relax/nsh/Make.defs create mode 100644 configs/xmc4500-relax/nsh/defconfig create mode 100644 configs/xmc4500-relax/nsh/setenv.sh create mode 100644 configs/xmc4500-relax/src/Makefile create mode 100644 configs/xmc4500-relax/src/xmc4500-relax.h create mode 100644 configs/xmc4500-relax/src/xmc4_appinit.c create mode 100644 configs/xmc4500-relax/src/xmc4_autoleds.c create mode 100644 configs/xmc4500-relax/src/xmc4_boot.c create mode 100644 configs/xmc4500-relax/src/xmc4_bringup.c create mode 100644 configs/xmc4500-relax/src/xmc4_buttons.c create mode 100644 configs/xmc4500-relax/src/xmc4_userleds.c diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 21334e71178..ce6fc7f2af3 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -151,6 +151,14 @@ config ARCH_CHIP_LPC43XX ---help--- NPX LPC43XX architectures (ARM Cortex-M4). +config ARCH_CHIP_MOXART + bool "MoxART" + select ARCH_ARM7TDMI + select ARCH_HAVE_RESET + select ARCH_HAVE_SERIAL_TERMIOS + ---help--- + MoxART family + config ARCH_CHIP_NUC1XX bool "Nuvoton NUC100/120" select ARCH_CORTEXM0 @@ -283,14 +291,6 @@ config ARCH_CHIP_XMC4 ---help--- Infineon XMC4xxx(ARM Cortex-M4) architectures -config ARCH_CHIP_MOXART - bool "MoxART" - select ARCH_ARM7TDMI - select ARCH_HAVE_RESET - select ARCH_HAVE_SERIAL_TERMIOS - ---help--- - MoxART family - endchoice config ARCH_ARM7TDMI @@ -434,6 +434,7 @@ config ARCH_CHIP default "lpc2378" if ARCH_CHIP_LPC2378 default "lpc31xx" if ARCH_CHIP_LPC31XX default "lpc43xx" if ARCH_CHIP_LPC43XX + default "moxart" if ARCH_CHIP_MOXART default "nuc1xx" if ARCH_CHIP_NUC1XX default "sama5" if ARCH_CHIP_SAMA5 default "samdl" if ARCH_CHIP_SAMD || ARCH_CHIP_SAML @@ -444,7 +445,7 @@ config ARCH_CHIP default "stm32l4" if ARCH_CHIP_STM32L4 default "str71x" if ARCH_CHIP_STR71X default "tms570" if ARCH_CHIP_TMS570 - default "moxart" if ARCH_CHIP_MOXART + default "xmc4" if ARCH_CHIP_XMC4 config ARM_TOOLCHAIN_IAR bool @@ -675,6 +676,9 @@ endif if ARCH_CHIP_LPC43XX source arch/arm/src/lpc43xx/Kconfig endif +if ARCH_CHIP_MOXART +source arch/arm/src/moxart/Kconfig +endif if ARCH_CHIP_NUC1XX source arch/arm/src/nuc1xx/Kconfig endif @@ -708,8 +712,5 @@ endif if ARCH_CHIP_XMC4 source arch/arm/src/xmc4/Kconfig endif -if ARCH_CHIP_MOXART -source arch/arm/src/moxart/Kconfig -endif endif # ARCH_ARM diff --git a/arch/arm/src/xmc4/Kconfig b/arch/arm/src/xmc4/Kconfig index 116d56d14f2..096a65fb858 100644 --- a/arch/arm/src/xmc4/Kconfig +++ b/arch/arm/src/xmc4/Kconfig @@ -50,7 +50,7 @@ config XMC4_USCI_I2S # Chip families -menu "ARCH_CHIP_XMC4 Peripheral Support" +menu "XMC4xxx Peripheral Support" config XMC4_USIC0 bool "USIC0" diff --git a/configs/Kconfig b/configs/Kconfig index d5016d9b7ce..d4bb9fe5bd0 100644 --- a/configs/Kconfig +++ b/configs/Kconfig @@ -1270,6 +1270,15 @@ config ARCH_BOARD_VIEWTOOL_STM32F107 board may be fitted with either: (1) STM32F107VCT6 or (2) STM32F103VCT6. See http://www.viewtool.com/ for further information. +config ARCH_BOARD_XMC4500RELAX + bool "Infineon XMC4500 Relax" + depends on ARCH_CHIP_XMC4500 + select ARCH_HAVE_LEDS + select ARCH_HAVE_BUTTONS + select ARCH_HAVE_IRQBUTTONS + ---help--- + Infineon XMC4000 Relax Lite v1 + config ARCH_BOARD_XTRS bool "XTRS TRS80 Model 3 emulation" depends on ARCH_CHIP_Z80 @@ -1531,6 +1540,7 @@ config ARCH_BOARD default "ubw32" if ARCH_BOARD_UBW32 default "us7032evb1" if ARCH_BOARD_US7032EVB1 default "viewtool-stm32f107" if ARCH_BOARD_VIEWTOOL_STM32F107 + default "xmc4500-relax" if ARCH_BOARD_XMC4500RELAX default "xtrs" if ARCH_BOARD_XTRS default "z16f2800100zcog" if ARCH_BOARD_Z16F2800100ZCOG default "z80sim" if ARCH_BOARD_Z80SIM @@ -1936,6 +1946,9 @@ endif if ARCH_BOARD_VIEWTOOL_STM32F107 source "configs/viewtool-stm32f107/Kconfig" endif +if ARCH_BOARD_XMC4500RELAX +source "configs/xmc4500-relax/Kconfig" +endif if ARCH_BOARD_XTRS source "configs/xtrs/Kconfig" endif diff --git a/configs/README.txt b/configs/README.txt index b883163e718..316108f8774 100644 --- a/configs/README.txt +++ b/configs/README.txt @@ -763,6 +763,9 @@ configs/viewtool-stm32f107 board may be fitted with either: (1) STM32F107VCT6 or (2) STM32F103VCT6. See http://www.viewtool.com/ for further information. +config/xmc4500-relax + Infineon XMC4000 Relax Lite v1 + configs/xtrs TRS80 Model 3. This port uses a vintage computer based on the Z80. An emulator for this computer is available to run TRS80 programs on a diff --git a/configs/xmc4500-relax/Kconfig b/configs/xmc4500-relax/Kconfig new file mode 100644 index 00000000000..f72f3c094ce --- /dev/null +++ b/configs/xmc4500-relax/Kconfig @@ -0,0 +1,4 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# diff --git a/configs/xmc4500-relax/nsh/Make.defs b/configs/xmc4500-relax/nsh/Make.defs new file mode 100644 index 00000000000..2d795a8ee1d --- /dev/null +++ b/configs/xmc4500-relax/nsh/Make.defs @@ -0,0 +1,128 @@ +############################################################################ +# configs/xmc4500-relax/nsh/Make.defs +# +# Copyright (C) 2017 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +include ${TOPDIR}/.config +include ${TOPDIR}/tools/Config.mk +include ${TOPDIR}/arch/arm/src/armv7-m/Toolchain.defs + +ifeq ($(CONFIG_ARMV7M_DTCM),y) + LDSCRIPT = flash-dtcm.ld +else + LDSCRIPT = flash-sram.ld +endif + +ifeq ($(WINTOOL),y) + # Windows-native toolchains + DIRLINK = $(TOPDIR)/tools/copydir.sh + DIRUNLINK = $(TOPDIR)/tools/unlink.sh + MKDEP = $(TOPDIR)/tools/mkwindeps.sh + ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" + ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}" + ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)}" +else + # Linux/Cygwin-native toolchain + MKDEP = $(TOPDIR)/tools/mkdeps$(HOSTEXEEXT) + ARCHINCLUDES = -I. -isystem $(TOPDIR)/include + ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx + ARCHSCRIPT = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT) +endif + +CC = $(CROSSDEV)gcc +CXX = $(CROSSDEV)g++ +CPP = $(CROSSDEV)gcc -E +LD = $(CROSSDEV)ld +AR = $(CROSSDEV)ar rcs +NM = $(CROSSDEV)nm +OBJCOPY = $(CROSSDEV)objcopy +OBJDUMP = $(CROSSDEV)objdump + +ARCHCCVERSION = ${shell $(CC) -v 2>&1 | sed -n '/^gcc version/p' | sed -e 's/^gcc version \([0-9\.]\)/\1/g' -e 's/[-\ ].*//g' -e '1q'} +ARCHCCMAJOR = ${shell echo $(ARCHCCVERSION) | cut -d'.' -f1} + +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + ARCHOPTIMIZATION = -g +endif + +ifneq ($(CONFIG_DEBUG_NOOPT),y) + ARCHOPTIMIZATION += $(MAXOPTIMIZATION) +endif + +ARCHCFLAGS = -fno-builtin +ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fcheck-new -fno-rtti +ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -fno-strict-aliasing +ARCHWARNINGSXX = -Wall -Wshadow -Wundef +ARCHDEFINES = +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) +AFLAGS = $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 + +# Loadable module definitions + +CMODULEFLAGS = $(CFLAGS) -mlong-calls # --target1-abs + +LDMODULEFLAGS = -r -e module_initialize +ifeq ($(WINTOOL),y) + LDMODULEFLAGS += -T "${shell cygpath -w $(TOPDIR)/libc/modlib/gnu-elf.ld}" +else + LDMODULEFLAGS += -T $(TOPDIR)/libc/modlib/gnu-elf.ld +endif + +ASMEXT = .S +OBJEXT = .o +LIBEXT = .a +EXEEXT = + +ifneq ($(CROSSDEV),arm-nuttx-elf-) + LDFLAGS += -nostartfiles -nodefaultlibs +endif +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + LDFLAGS += -g +endif + + +HOSTCC = gcc +HOSTINCLUDES = -I. +HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -g -pipe +HOSTLDFLAGS = + diff --git a/configs/xmc4500-relax/nsh/defconfig b/configs/xmc4500-relax/nsh/defconfig new file mode 100644 index 00000000000..54bd16a3928 --- /dev/null +++ b/configs/xmc4500-relax/nsh/defconfig @@ -0,0 +1,1038 @@ +# +# Automatically generated file; DO NOT EDIT. +# Nuttx/ Configuration +# + +# +# Build Setup +# +# CONFIG_EXPERIMENTAL is not set +# CONFIG_DEFAULT_SMALL is not set +# CONFIG_HOST_LINUX is not set +# CONFIG_HOST_OSX is not set +CONFIG_HOST_WINDOWS=y +# CONFIG_HOST_OTHER is not set +CONFIG_TOOLCHAIN_WINDOWS=y +# CONFIG_WINDOWS_NATIVE is not set +CONFIG_WINDOWS_CYGWIN=y +# CONFIG_WINDOWS_UBUNTU is not set +# CONFIG_WINDOWS_MSYS is not set +# CONFIG_WINDOWS_OTHER is not set + +# +# Build Configuration +# +# CONFIG_APPS_DIR="../apps" +CONFIG_BUILD_FLAT=y +# CONFIG_BUILD_2PASS is not set + +# +# Binary Output Formats +# +# CONFIG_RRLOAD_BINARY is not set +# CONFIG_INTELHEX_BINARY is not set +# CONFIG_MOTOROLA_SREC is not set +CONFIG_RAW_BINARY=y +# CONFIG_UBOOT_UIMAGE is not set + +# +# Customize Header Files +# +# CONFIG_ARCH_STDINT_H is not set +# CONFIG_ARCH_STDBOOL_H is not set +# CONFIG_ARCH_MATH_H is not set +# CONFIG_ARCH_FLOAT_H is not set +# CONFIG_ARCH_STDARG_H is not set +# CONFIG_ARCH_DEBUG_H is not set + +# +# Debug Options +# +CONFIG_DEBUG_ALERT=y +# CONFIG_DEBUG_FEATURES is not set +CONFIG_ARCH_HAVE_STACKCHECK=y +# CONFIG_STACK_COLORATION is not set +# CONFIG_ARCH_HAVE_HEAPCHECK is not set +# CONFIG_DEBUG_SYMBOLS is not set +CONFIG_ARCH_HAVE_CUSTOMOPT=y +# CONFIG_DEBUG_NOOPT is not set +# CONFIG_DEBUG_CUSTOMOPT is not set +CONFIG_DEBUG_FULLOPT=y + +# +# System Type +# +CONFIG_ARCH_ARM=y +# CONFIG_ARCH_AVR is not set +# CONFIG_ARCH_HC is not set +# CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set +# CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set +# CONFIG_ARCH_SIM is not set +# CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set +# CONFIG_ARCH_Z16 is not set +# CONFIG_ARCH_Z80 is not set +CONFIG_ARCH="arm" + +# +# ARM Options +# +# CONFIG_ARCH_CHIP_A1X is not set +# CONFIG_ARCH_CHIP_C5471 is not set +# CONFIG_ARCH_CHIP_DM320 is not set +# CONFIG_ARCH_CHIP_EFM32 is not set +# CONFIG_ARCH_CHIP_IMX1 is not set +# CONFIG_ARCH_CHIP_IMX6 is not set +# CONFIG_ARCH_CHIP_KINETIS is not set +# CONFIG_ARCH_CHIP_KL is not set +# CONFIG_ARCH_CHIP_LM is not set +# CONFIG_ARCH_CHIP_TIVA is not set +# CONFIG_ARCH_CHIP_LPC11XX is not set +# CONFIG_ARCH_CHIP_LPC17XX is not set +# CONFIG_ARCH_CHIP_LPC214X is not set +# CONFIG_ARCH_CHIP_LPC2378 is not set +# CONFIG_ARCH_CHIP_LPC31XX is not set +# CONFIG_ARCH_CHIP_LPC43XX is not set +# CONFIG_ARCH_CHIP_MOXART is not set +# CONFIG_ARCH_CHIP_NUC1XX is not set +# CONFIG_ARCH_CHIP_SAMA5 is not set +# CONFIG_ARCH_CHIP_SAMD is not set +# CONFIG_ARCH_CHIP_SAML is not set +# CONFIG_ARCH_CHIP_SAM34 is not set +# CONFIG_ARCH_CHIP_SAMV7 is not set +# CONFIG_ARCH_CHIP_STM32 is not set +# CONFIG_ARCH_CHIP_STM32F7 is not set +# CONFIG_ARCH_CHIP_STM32L4 is not set +# CONFIG_ARCH_CHIP_STR71X is not set +# CONFIG_ARCH_CHIP_TMS570 is not set +CONFIG_ARCH_CHIP_XMC4=y +# CONFIG_ARCH_ARM7TDMI is not set +# CONFIG_ARCH_ARM926EJS is not set +# CONFIG_ARCH_ARM920T is not set +# CONFIG_ARCH_CORTEXM0 is not set +# CONFIG_ARCH_CORTEXM23 is not set +# CONFIG_ARCH_CORTEXM3 is not set +# CONFIG_ARCH_CORTEXM33 is not set +CONFIG_ARCH_CORTEXM4=y +# CONFIG_ARCH_CORTEXM7 is not set +# CONFIG_ARCH_CORTEXA5 is not set +# CONFIG_ARCH_CORTEXA8 is not set +# CONFIG_ARCH_CORTEXA9 is not set +# CONFIG_ARCH_CORTEXR4 is not set +# CONFIG_ARCH_CORTEXR4F is not set +# CONFIG_ARCH_CORTEXR5 is not set +# CONFIG_ARCH_CORTEX5F is not set +# CONFIG_ARCH_CORTEXR7 is not set +# CONFIG_ARCH_CORTEXR7F is not set +CONFIG_ARCH_FAMILY="armv7-m" +CONFIG_ARCH_CHIP="xmc4" +# CONFIG_ARM_TOOLCHAIN_IAR is not set +CONFIG_ARM_TOOLCHAIN_GNU=y +# CONFIG_ARMV7M_USEBASEPRI is not set +CONFIG_ARCH_HAVE_CMNVECTOR=y +CONFIG_ARMV7M_CMNVECTOR=y +CONFIG_ARMV7M_LAZYFPU=y +# CONFIG_ARCH_HAVE_FPU is not set +# CONFIG_ARCH_HAVE_DPFPU is not set +# CONFIG_ARCH_HAVE_TRUSTZONE is not set +CONFIG_ARM_HAVE_MPU_UNIFIED=y +# CONFIG_ARM_MPU is not set + +# +# ARMV7M Configuration Options +# +# CONFIG_ARMV7M_HAVE_ICACHE is not set +# CONFIG_ARMV7M_HAVE_DCACHE is not set +# CONFIG_ARMV7M_HAVE_ITCM is not set +# CONFIG_ARMV7M_HAVE_DTCM is not set +# CONFIG_ARMV7M_TOOLCHAIN_IARW is not set +# CONFIG_ARMV7M_TOOLCHAIN_ATOLLIC is not set +# CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT is not set +# CONFIG_ARMV7M_TOOLCHAIN_CODEREDW is not set +# CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYW is not set +# CONFIG_ARMV7M_TOOLCHAIN_DEVKITARM is not set +# CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIL is not set +CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIW=y +# CONFIG_ARMV7M_TOOLCHAIN_RAISONANCE is not set +CONFIG_ARMV7M_HAVE_STACKCHECK=y +# CONFIG_ARMV7M_STACKCHECK is not set +# CONFIG_ARMV7M_ITMSYSLOG is not set + +# +# XMC4xxx Configuration Options +# +CONFIG_ARCH_CHIP_XMC4500=y +CONFIG_XMC4_USIC=y +CONFIG_XMC4_USCI_UART=y +# CONFIG_XMC4_USCI_LIN is not set +# CONFIG_XMC4_USCI_SPI is not set +# CONFIG_XMC4_USCI_I2C is not set +# CONFIG_XMC4_USCI_I2S is not set + +# +# XMC4xxx Peripheral Support +# +CONFIG_XMC4_USIC0=y +# CONFIG_XMC4_USIC1 is not set +# CONFIG_XMC4_USIC2 is not set +# CONFIG_XMC4_USIC3 is not set +# CONFIG_XMC4_USIC4 is not set +# CONFIG_XMC4_USIC5 is not set + +# +# XMC4xxx USIC Configuration +# +CONFIG_XMC4_USIC0_ISUART=y +# CONFIG_XMC4_USIC0_ISLIN is not set +# CONFIG_XMC4_USIC0_ISSPI is not set +# CONFIG_XMC4_USIC0_ISI2C is not set +# CONFIG_XMC4_USIC0_ISI2S is not set + +# +# Architecture Options +# +# CONFIG_ARCH_NOINTC is not set +# CONFIG_ARCH_VECNOTIRQ is not set +# CONFIG_ARCH_DMA is not set +CONFIG_ARCH_HAVE_IRQPRIO=y +# CONFIG_ARCH_L2CACHE is not set +# CONFIG_ARCH_HAVE_COHERENT_DCACHE is not set +# CONFIG_ARCH_HAVE_ADDRENV is not set +# CONFIG_ARCH_NEED_ADDRENV_MAPPING is not set +# CONFIG_ARCH_HAVE_MULTICPU is not set +CONFIG_ARCH_HAVE_VFORK=y +# CONFIG_ARCH_HAVE_MMU is not set +CONFIG_ARCH_HAVE_MPU=y +# CONFIG_ARCH_NAND_HWECC is not set +# CONFIG_ARCH_HAVE_EXTCLK is not set +# CONFIG_ARCH_HAVE_POWEROFF is not set +CONFIG_ARCH_HAVE_RESET=y +# CONFIG_ARCH_USE_MPU is not set +# CONFIG_ARCH_IRQPRIO is not set +CONFIG_ARCH_STACKDUMP=y +# CONFIG_ENDIAN_BIG is not set +# CONFIG_ARCH_IDLE_CUSTOM is not set +CONFIG_ARCH_HAVE_RAMFUNCS=y +# CONFIG_ARCH_RAMFUNCS is not set +CONFIG_ARCH_HAVE_RAMVECTORS=y +# CONFIG_ARCH_RAMVECTORS is not set +# CONFIG_ARCH_MINIMAL_VECTORTABLE is not set + +# +# Board Settings +# +CONFIG_BOARD_LOOPSPERMSEC=8000 +# CONFIG_ARCH_CALIBRATION is not set + +# +# Interrupt options +# +CONFIG_ARCH_HAVE_INTERRUPTSTACK=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_HAVE_HIPRI_INTERRUPT=y +# CONFIG_ARCH_HIPRI_INTERRUPT is not set + +# +# Boot options +# +# CONFIG_BOOT_RUNFROMEXTSRAM is not set +CONFIG_BOOT_RUNFROMFLASH=y +# CONFIG_BOOT_RUNFROMISRAM is not set +# CONFIG_BOOT_RUNFROMSDRAM is not set +# CONFIG_BOOT_COPYTORAM is not set + +# +# Boot Memory Configuration +# +CONFIG_RAM_START=0x20400000 +CONFIG_RAM_SIZE=393216 +# CONFIG_ARCH_HAVE_SDRAM is not set + +# +# Board Selection +# +CONFIG_ARCH_BOARD_XMC4500RELAX=y +# CONFIG_ARCH_BOARD_CUSTOM is not set +CONFIG_ARCH_BOARD="xmc4500-relax" + +# +# Common Board Options +# +CONFIG_ARCH_HAVE_LEDS=y +CONFIG_ARCH_LEDS=y +CONFIG_ARCH_HAVE_BUTTONS=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_HAVE_IRQBUTTONS=y +CONFIG_ARCH_IRQBUTTONS=y + +# +# Board-Specific Options +# +# CONFIG_BOARD_CRASHDUMP is not set +CONFIG_LIB_BOARDCTL=y +# CONFIG_BOARDCTL_RESET is not set +# CONFIG_BOARDCTL_UNIQUEID is not set +# CONFIG_BOARDCTL_TSCTEST is not set +# CONFIG_BOARDCTL_GRAPHICS is not set +# CONFIG_BOARDCTL_IOCTL is not set + +# +# RTOS Features +# +CONFIG_DISABLE_OS_API=y +# CONFIG_DISABLE_POSIX_TIMERS is not set +# CONFIG_DISABLE_PTHREAD is not set +# CONFIG_DISABLE_SIGNALS is not set +# CONFIG_DISABLE_MQUEUE is not set +# CONFIG_DISABLE_ENVIRON is not set + +# +# Clocks and Timers +# +CONFIG_USEC_PER_TICK=10000 +# CONFIG_SYSTEM_TIME64 is not set +# CONFIG_CLOCK_MONOTONIC is not set +# CONFIG_ARCH_HAVE_TIMEKEEPING is not set +# CONFIG_JULIAN_TIME is not set +CONFIG_START_YEAR=2014 +CONFIG_START_MONTH=3 +CONFIG_START_DAY=10 +CONFIG_MAX_WDOGPARMS=2 +CONFIG_PREALLOC_WDOGS=32 +CONFIG_WDOG_INTRESERVE=4 +CONFIG_PREALLOC_TIMERS=4 + +# +# Tasks and Scheduling +# +# CONFIG_SPINLOCK is not set +# CONFIG_INIT_NONE is not set +CONFIG_INIT_ENTRYPOINT=y +# CONFIG_INIT_FILEPATH is not set +CONFIG_USER_ENTRYPOINT="nsh_main" +CONFIG_RR_INTERVAL=200 +# CONFIG_SCHED_SPORADIC is not set +CONFIG_TASK_NAME_SIZE=31 +CONFIG_MAX_TASKS=16 +# CONFIG_SCHED_HAVE_PARENT is not set +CONFIG_SCHED_WAITPID=y + +# +# Pthread Options +# +# CONFIG_MUTEX_TYPES is not set +CONFIG_NPTHREAD_KEYS=4 +# CONFIG_PTHREAD_CLEANUP is not set +# CONFIG_CANCELLATION_POINTS is not set + +# +# Performance Monitoring +# +# CONFIG_SCHED_CPULOAD is not set +# CONFIG_SCHED_INSTRUMENTATION is not set + +# +# Files and I/O +# +CONFIG_DEV_CONSOLE=y +# CONFIG_FDCLONE_DISABLE is not set +# CONFIG_FDCLONE_STDIO is not set +CONFIG_SDCLONE_DISABLE=y +CONFIG_NFILE_DESCRIPTORS=8 +CONFIG_NFILE_STREAMS=8 +CONFIG_NAME_MAX=32 +# CONFIG_PRIORITY_INHERITANCE is not set + +# +# RTOS hooks +# +# CONFIG_BOARD_INITIALIZE is not set +# CONFIG_SCHED_STARTHOOK is not set +# CONFIG_SCHED_ATEXIT is not set +# CONFIG_SCHED_ONEXIT is not set +# CONFIG_SIG_EVTHREAD is not set + +# +# Signal Numbers +# +CONFIG_SIG_SIGUSR1=1 +CONFIG_SIG_SIGUSR2=2 +CONFIG_SIG_SIGALARM=3 +CONFIG_SIG_SIGCONDTIMEDOUT=16 +CONFIG_SIG_SIGWORK=17 + +# +# POSIX Message Queue Options +# +CONFIG_PREALLOC_MQ_MSGS=4 +CONFIG_MQ_MAXMSGSIZE=32 +# CONFIG_MODULE is not set + +# +# Work queue support +# +CONFIG_SCHED_WORKQUEUE=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=224 +CONFIG_SCHED_HPWORKPERIOD=50000 +CONFIG_SCHED_HPWORKSTACKSIZE=2048 +# CONFIG_SCHED_LPWORK is not set + +# +# Stack and heap information +# +CONFIG_IDLETHREAD_STACKSIZE=1024 +CONFIG_USERMAIN_STACKSIZE=2048 +CONFIG_PTHREAD_STACK_MIN=256 +CONFIG_PTHREAD_STACK_DEFAULT=2048 +# CONFIG_LIB_SYSCALL is not set + +# +# Device Drivers +# +CONFIG_DISABLE_POLL=y +CONFIG_DEV_NULL=y +# CONFIG_DEV_ZERO is not set +# CONFIG_DEV_URANDOM is not set +# CONFIG_DEV_LOOP is not set + +# +# Buffering +# +# CONFIG_DRVR_WRITEBUFFER is not set +# CONFIG_DRVR_READAHEAD is not set +# CONFIG_RAMDISK is not set +# CONFIG_CAN is not set +# CONFIG_ARCH_HAVE_PWM_PULSECOUNT is not set +# CONFIG_ARCH_HAVE_PWM_MULTICHAN is not set +# CONFIG_PWM is not set +CONFIG_ARCH_HAVE_I2CRESET=y +CONFIG_I2C=y +# CONFIG_I2C_SLAVE is not set +# CONFIG_I2C_POLLED is not set +CONFIG_I2C_RESET=y +# CONFIG_I2C_TRACE is not set +CONFIG_I2C_DRIVER=y +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +# CONFIG_ARCH_HAVE_SPI_BITORDER is not set +CONFIG_SPI=y +# CONFIG_SPI_SLAVE is not set +CONFIG_SPI_EXCHANGE=y +# CONFIG_SPI_CMDDATA is not set +# CONFIG_SPI_CALLBACK is not set +# CONFIG_SPI_HWFEATURES is not set +# CONFIG_SPI_CS_DELAY_CONTROL is not set +# CONFIG_SPI_DRIVER is not set +# CONFIG_SPI_BITBANG is not set +# CONFIG_I2S is not set + +# +# Timer Driver Support +# +# CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set +# CONFIG_RTC is not set +# CONFIG_WATCHDOG is not set +# CONFIG_TIMERS_CS2100CP is not set +# CONFIG_ANALOG is not set +# CONFIG_AUDIO_DEVICES is not set +# CONFIG_VIDEO_DEVICES is not set +# CONFIG_BCH is not set +# CONFIG_INPUT is not set + +# +# IO Expander/GPIO Support +# +# CONFIG_IOEXPANDER is not set +# CONFIG_DEV_GPIO is not set + +# +# LCD Driver Support +# +# CONFIG_LCD is not set +# CONFIG_SLCD is not set + +# +# LED Support +# +# CONFIG_USERLED is not set +# CONFIG_RGBLED is not set +# CONFIG_PCA9635PW is not set +# CONFIG_NCP5623C is not set +CONFIG_MMCSD=y +CONFIG_MMCSD_NSLOTS=1 +# CONFIG_MMCSD_READONLY is not set +CONFIG_MMCSD_MULTIBLOCK_DISABLE=y +# CONFIG_MMCSD_MMCSUPPORT is not set +CONFIG_MMCSD_HAVECARDDETECT=y +# CONFIG_MMCSD_SPI is not set +# CONFIG_ARCH_HAVE_SDIO is not set +# CONFIG_SDIO_DMA is not set +# CONFIG_ARCH_HAVE_SDIOWAIT_WRCOMPLETE is not set +# CONFIG_MODEM is not set +CONFIG_MTD=y + +# +# MTD Configuration +# +# CONFIG_MTD_PARTITION is not set +# CONFIG_MTD_SECT512 is not set +# CONFIG_MTD_BYTE_WRITE is not set +# CONFIG_MTD_PROGMEM is not set +CONFIG_MTD_CONFIG=y +# CONFIG_MTD_CONFIG_RAM_CONSOLIDATE is not set +CONFIG_MTD_CONFIG_ERASEDVALUE=0xff + +# +# MTD Device Drivers +# +# CONFIG_MTD_NAND is not set +# CONFIG_RAMMTD is not set +# CONFIG_FILEMTD is not set +CONFIG_MTD_AT24XX=y +# CONFIG_AT24XX_MULTI is not set +CONFIG_AT24XX_SIZE=2 +CONFIG_AT24XX_ADDR=0x57 +CONFIG_AT24XX_EXTENDED=y +CONFIG_AT24XX_EXTSIZE=160 +CONFIG_AT24XX_FREQUENCY=100000 +CONFIG_MTD_AT25=y +CONFIG_AT25_SPIMODE=0 +CONFIG_AT25_SPIFREQUENCY=20000000 +# CONFIG_MTD_AT45DB is not set +# CONFIG_MTD_IS25XP is not set +# CONFIG_MTD_M25P is not set +# CONFIG_MTD_MX25L is not set +# CONFIG_MTD_S25FL1 is not set +# CONFIG_MTD_N25QXXX is not set +# CONFIG_MTD_SMART is not set +# CONFIG_MTD_RAMTRON is not set +# CONFIG_MTD_SST25 is not set +# CONFIG_MTD_SST25XX is not set +# CONFIG_MTD_SST26 is not set +# CONFIG_MTD_SST39FV is not set +# CONFIG_MTD_W25 is not set +# CONFIG_EEPROM is not set +# CONFIG_PIPES is not set +# CONFIG_PM is not set +# CONFIG_POWER is not set +# CONFIG_SENSORS is not set +CONFIG_SERIAL=y +# CONFIG_DEV_LOWCONSOLE is not set +# CONFIG_SERIAL_REMOVABLE is not set +CONFIG_SERIAL_CONSOLE=y +# CONFIG_16550_UART is not set +# CONFIG_UART_SERIALDRIVER is not set +CONFIG_UART0_SERIALDRIVER=y +# CONFIG_UART1_SERIALDRIVER is not set +# CONFIG_UART2_SERIALDRIVER is not set +# CONFIG_UART3_SERIALDRIVER is not set +# CONFIG_UART4_SERIALDRIVER is not set +# CONFIG_UART5_SERIALDRIVER is not set +# CONFIG_UART6_SERIALDRIVER is not set +# CONFIG_UART7_SERIALDRIVER is not set +# CONFIG_UART8_SERIALDRIVER is not set +# CONFIG_SCI0_SERIALDRIVER is not set +# CONFIG_SCI1_SERIALDRIVER is not set +# CONFIG_USART0_SERIALDRIVER is not set +# CONFIG_USART1_SERIALDRIVER is not set +# CONFIG_USART2_SERIALDRIVER is not set +# CONFIG_USART3_SERIALDRIVER is not set +# CONFIG_USART4_SERIALDRIVER is not set +# CONFIG_USART5_SERIALDRIVER is not set +# CONFIG_USART6_SERIALDRIVER is not set +# CONFIG_USART7_SERIALDRIVER is not set +# CONFIG_USART8_SERIALDRIVER is not set +# CONFIG_OTHER_UART_SERIALDRIVER is not set +CONFIG_MCU_SERIAL=y +CONFIG_STANDARD_SERIAL=y +# CONFIG_SERIAL_IFLOWCONTROL is not set +# CONFIG_SERIAL_OFLOWCONTROL is not set +# CONFIG_SERIAL_DMA is not set +# CONFIG_ARCH_HAVE_SERIAL_TERMIOS is not set +CONFIG_UART0_SERIAL_CONSOLE=y +# CONFIG_OTHER_SERIAL_CONSOLE is not set +# CONFIG_NO_SERIAL_CONSOLE is not set + +# +# UART0 Configuration +# +CONFIG_UART0_RXBUFSIZE=256 +CONFIG_UART0_TXBUFSIZE=256 +CONFIG_UART0_BAUD=115200 +CONFIG_UART0_BITS=8 +CONFIG_UART0_PARITY=0 +CONFIG_UART0_2STOP=0 +# CONFIG_UART0_IFLOWCONTROL is not set +# CONFIG_UART0_OFLOWCONTROL is not set +# CONFIG_UART0_DMA is not set +# CONFIG_PSEUDOTERM is not set +# CONFIG_USBDEV is not set +# CONFIG_USBHOST is not set +# CONFIG_HAVE_USBTRACE is not set +# CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set + +# +# System Logging +# +# CONFIG_ARCH_SYSLOG is not set +# CONFIG_RAMLOG is not set +# CONFIG_SYSLOG_INTBUFFER is not set +# CONFIG_SYSLOG_TIMESTAMP is not set +CONFIG_SYSLOG_SERIAL_CONSOLE=y +# CONFIG_SYSLOG_CHAR is not set +CONFIG_SYSLOG_CONSOLE=y +# CONFIG_SYSLOG_NONE is not set +# CONFIG_SYSLOG_FILE is not set +# CONFIG_SYSLOG_CHARDEV is not set + +# +# Networking Support +# +# CONFIG_ARCH_HAVE_NET is not set +# CONFIG_ARCH_HAVE_PHY is not set +# CONFIG_NET is not set + +# +# Crypto API +# +# CONFIG_CRYPTO is not set + +# +# File Systems +# + +# +# File system configuration +# +# CONFIG_DISABLE_MOUNTPOINT is not set +# CONFIG_FS_AUTOMOUNTER is not set +# CONFIG_DISABLE_PSEUDOFS_OPERATIONS is not set +# CONFIG_PSEUDOFS_SOFTLINKS is not set +CONFIG_FS_READABLE=y +CONFIG_FS_WRITABLE=y +# CONFIG_FS_NAMED_SEMAPHORES is not set +CONFIG_FS_MQUEUE_MPATH="/var/mqueue" +# CONFIG_FS_RAMMAP is not set +CONFIG_FS_FAT=y +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FAT_MAXFNAME=32 +# CONFIG_FS_FATTIME is not set +# CONFIG_FAT_FORCE_INDIRECT is not set +# CONFIG_FAT_DMAMEMORY is not set +# CONFIG_FAT_DIRECT_RETRY is not set +# CONFIG_FS_NXFFS is not set +# CONFIG_FS_ROMFS is not set +# CONFIG_FS_TMPFS is not set +# CONFIG_FS_SMARTFS is not set +# CONFIG_FS_BINFS is not set +CONFIG_FS_PROCFS=y +# CONFIG_FS_PROCFS_REGISTER is not set + +# +# Exclude individual procfs entries +# +# CONFIG_FS_PROCFS_EXCLUDE_PROCESS is not set +# CONFIG_FS_PROCFS_EXCLUDE_UPTIME is not set +# CONFIG_FS_PROCFS_EXCLUDE_MOUNTS is not set +# CONFIG_FS_PROCFS_EXCLUDE_MTD is not set +# CONFIG_FS_UNIONFS is not set + +# +# Graphics Support +# +# CONFIG_NX is not set + +# +# Memory Management +# +# CONFIG_MM_SMALL is not set +CONFIG_MM_REGIONS=1 +# CONFIG_ARCH_HAVE_HEAP2 is not set +# CONFIG_GRAN is not set + +# +# Audio Support +# +# CONFIG_AUDIO is not set + +# +# Wireless Support +# + +# +# Binary Loader +# +# CONFIG_BINFMT_DISABLE is not set +# CONFIG_BINFMT_EXEPATH is not set +# CONFIG_NXFLAT is not set +# CONFIG_ELF is not set +CONFIG_BUILTIN=y +# CONFIG_PIC is not set +# CONFIG_SYMTAB_ORDEREDBYNAME is not set + +# +# Library Routines +# + +# +# Standard C Library Options +# + +# +# Standard C I/O +# +# CONFIG_STDIO_DISABLE_BUFFERING is not set +CONFIG_STDIO_BUFFER_SIZE=64 +CONFIG_STDIO_LINEBUFFER=y +CONFIG_NUNGET_CHARS=2 +# CONFIG_NOPRINTF_FIELDWIDTH is not set +# CONFIG_LIBC_FLOATINGPOINT is not set +CONFIG_LIBC_LONG_LONG=y +# CONFIG_LIBC_SCANSET is not set +# CONFIG_EOL_IS_CR is not set +# CONFIG_EOL_IS_LF is not set +# CONFIG_EOL_IS_BOTH_CRLF is not set +CONFIG_EOL_IS_EITHER_CRLF=y +# CONFIG_MEMCPY_VIK is not set +# CONFIG_LIBM is not set + +# +# Architecture-Specific Support +# +CONFIG_ARCH_LOWPUTC=y +# CONFIG_ARCH_ROMGETC is not set +# CONFIG_LIBC_ARCH_MEMCPY is not set +# CONFIG_LIBC_ARCH_MEMCMP is not set +# CONFIG_LIBC_ARCH_MEMMOVE is not set +# CONFIG_LIBC_ARCH_MEMSET is not set +# CONFIG_LIBC_ARCH_STRCHR is not set +# CONFIG_LIBC_ARCH_STRCMP is not set +# CONFIG_LIBC_ARCH_STRCPY is not set +# CONFIG_LIBC_ARCH_STRNCPY is not set +# CONFIG_LIBC_ARCH_STRLEN is not set +# CONFIG_LIBC_ARCH_STRNLEN is not set +# CONFIG_LIBC_ARCH_ELF is not set +# CONFIG_ARMV7M_MEMCPY is not set + +# +# stdlib Options +# +CONFIG_LIB_RAND_ORDER=1 +CONFIG_LIB_HOMEDIR="/" +CONFIG_LIBC_TMPDIR="/tmp" +CONFIG_LIBC_MAX_TMPFILE=32 + +# +# Program Execution Options +# +# CONFIG_LIBC_EXECFUNCS is not set +CONFIG_POSIX_SPAWN_PROXY_STACKSIZE=1024 +CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=2048 + +# +# errno Decode Support +# +# CONFIG_LIBC_STRERROR is not set +# CONFIG_LIBC_PERROR_STDOUT is not set + +# +# memcpy/memset Options +# +# CONFIG_MEMSET_OPTSPEED is not set +# CONFIG_LIBC_DLLFCN is not set +# CONFIG_LIBC_MODLIB is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set + +# +# Time/Time Zone Support +# +# CONFIG_LIBC_LOCALTIME is not set +# CONFIG_TIME_EXTENDED is not set +CONFIG_ARCH_HAVE_TLS=y + +# +# Thread Local Storage (TLS) +# +# CONFIG_TLS is not set + +# +# Network-Related Options +# +# CONFIG_LIBC_IPv4_ADDRCONV is not set +# CONFIG_LIBC_IPv6_ADDRCONV is not set +# CONFIG_LIBC_NETDB is not set + +# +# NETDB Support +# +# CONFIG_NETDB_HOSTFILE is not set +# CONFIG_LIBC_IOCTL_VARIADIC is not set +CONFIG_LIB_SENDFILE_BUFSIZE=512 + +# +# Non-standard Library Support +# +# CONFIG_LIB_CRC64_FAST is not set +# CONFIG_LIB_KBDCODEC is not set +# CONFIG_LIB_SLCDCODEC is not set +# CONFIG_LIB_HEX2BIN is not set + +# +# Basic CXX Support +# +# CONFIG_C99_BOOL8 is not set +# CONFIG_HAVE_CXX is not set + +# +# Application Configuration +# + +# +# Built-In Applications +# +CONFIG_BUILTIN_PROXY_STACKSIZE=1024 + +# +# CAN Utilities +# + +# +# Examples +# +# CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CCTYPE is not set +# CONFIG_EXAMPLES_CHAT is not set +# CONFIG_EXAMPLES_CONFIGDATA is not set +# CONFIG_EXAMPLES_DHCPD is not set +# CONFIG_EXAMPLES_ELF is not set +# CONFIG_EXAMPLES_FSTEST is not set +# CONFIG_EXAMPLES_FTPC is not set +# CONFIG_EXAMPLES_FTPD is not set +# CONFIG_EXAMPLES_HELLO is not set +# CONFIG_EXAMPLES_HIDKBD is not set +# CONFIG_EXAMPLES_IGMP is not set +# CONFIG_EXAMPLES_JSON is not set +# CONFIG_EXAMPLES_KEYPADTEST is not set +# CONFIG_EXAMPLES_MEDIA is not set +# CONFIG_EXAMPLES_MM is not set +# CONFIG_EXAMPLES_MODBUS is not set +# CONFIG_EXAMPLES_MOUNT is not set +CONFIG_EXAMPLES_NSH=y +# CONFIG_EXAMPLES_NULL is not set +# CONFIG_EXAMPLES_NX is not set +# CONFIG_EXAMPLES_NXFFS is not set +# CONFIG_EXAMPLES_NXHELLO is not set +# CONFIG_EXAMPLES_NXIMAGE is not set +# CONFIG_EXAMPLES_NXLINES is not set +# CONFIG_EXAMPLES_NXTERM is not set +# CONFIG_EXAMPLES_NXTEXT is not set +# CONFIG_EXAMPLES_OSTEST is not set +# CONFIG_EXAMPLES_PCA9635 is not set +# CONFIG_EXAMPLES_POSIXSPAWN is not set +# CONFIG_EXAMPLES_PPPD is not set +# CONFIG_EXAMPLES_RFID_READUID is not set +# CONFIG_EXAMPLES_RGBLED is not set +# CONFIG_EXAMPLES_SENDMAIL is not set +# CONFIG_EXAMPLES_SERIALBLASTER is not set +# CONFIG_EXAMPLES_SERIALRX is not set +# CONFIG_EXAMPLES_SERLOOP is not set +# CONFIG_EXAMPLES_SLCD is not set +# CONFIG_EXAMPLES_SMART is not set +# CONFIG_EXAMPLES_SMART_TEST is not set +# CONFIG_EXAMPLES_SMP is not set +# CONFIG_EXAMPLES_STAT is not set +# CONFIG_EXAMPLES_TCPECHO is not set +# CONFIG_EXAMPLES_TELNETD is not set +# CONFIG_EXAMPLES_TIFF is not set +# CONFIG_EXAMPLES_TOUCHSCREEN is not set +# CONFIG_EXAMPLES_USBSERIAL is not set +# CONFIG_EXAMPLES_WATCHDOG is not set +# CONFIG_EXAMPLES_WEBSERVER is not set + +# +# File System Utilities +# +# CONFIG_FSUTILS_FLASH_ERASEALL is not set +# CONFIG_FSUTILS_INIFILE is not set +# CONFIG_FSUTILS_PASSWD is not set + +# +# GPS Utilities +# +# CONFIG_GPSUTILS_MINMEA_LIB is not set + +# +# Graphics Support +# +# CONFIG_TIFF is not set +# CONFIG_GRAPHICS_TRAVELER is not set + +# +# Interpreters +# +# CONFIG_INTERPRETERS_BAS is not set +# CONFIG_INTERPRETERS_FICL is not set +# CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set +# CONFIG_INTERPRETERS_PCODE is not set + +# +# FreeModBus +# +# CONFIG_MODBUS is not set + +# +# Network Utilities +# +# CONFIG_NETUTILS_CODECS is not set +# CONFIG_NETUTILS_ESP8266 is not set +# CONFIG_NETUTILS_FTPC is not set +# CONFIG_NETUTILS_JSON is not set +# CONFIG_NETUTILS_SMTP is not set + +# +# NSH Library +# +CONFIG_NSH_LIBRARY=y +# CONFIG_NSH_MOTD is not set + +# +# Command Line Configuration +# +CONFIG_NSH_READLINE=y +# CONFIG_NSH_CLE is not set +CONFIG_NSH_LINELEN=64 +# CONFIG_NSH_DISABLE_SEMICOLON is not set +CONFIG_NSH_CMDPARMS=y +CONFIG_NSH_MAXARGUMENTS=6 +CONFIG_NSH_ARGCAT=y +CONFIG_NSH_NESTDEPTH=3 +# CONFIG_NSH_DISABLEBG is not set +CONFIG_NSH_BUILTIN_APPS=y + +# +# Disable Individual commands +# +# CONFIG_NSH_DISABLE_ADDROUTE is not set +# CONFIG_NSH_DISABLE_BASENAME is not set +# CONFIG_NSH_DISABLE_CAT is not set +# CONFIG_NSH_DISABLE_CD is not set +# CONFIG_NSH_DISABLE_CP is not set +# CONFIG_NSH_DISABLE_CMP is not set +CONFIG_NSH_DISABLE_DATE=y +# CONFIG_NSH_DISABLE_DD is not set +# CONFIG_NSH_DISABLE_DF is not set +# CONFIG_NSH_DISABLE_DELROUTE is not set +# CONFIG_NSH_DISABLE_DIRNAME is not set +# CONFIG_NSH_DISABLE_ECHO is not set +# CONFIG_NSH_DISABLE_EXEC is not set +# CONFIG_NSH_DISABLE_EXIT is not set +# CONFIG_NSH_DISABLE_FREE is not set +# CONFIG_NSH_DISABLE_GET is not set +# CONFIG_NSH_DISABLE_HELP is not set +# CONFIG_NSH_DISABLE_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_IFUPDOWN is not set +# CONFIG_NSH_DISABLE_KILL is not set +# CONFIG_NSH_DISABLE_LOSETUP is not set +CONFIG_NSH_DISABLE_LOSMART=y +# CONFIG_NSH_DISABLE_LS is not set +# CONFIG_NSH_DISABLE_MB is not set +# CONFIG_NSH_DISABLE_MKDIR is not set +# CONFIG_NSH_DISABLE_MKFATFS is not set +# CONFIG_NSH_DISABLE_MKRD is not set +# CONFIG_NSH_DISABLE_MH is not set +# CONFIG_NSH_DISABLE_MOUNT is not set +# CONFIG_NSH_DISABLE_MV is not set +# CONFIG_NSH_DISABLE_MW is not set +CONFIG_NSH_DISABLE_PRINTF=y +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NSH_DISABLE_PUT is not set +# CONFIG_NSH_DISABLE_PWD is not set +# CONFIG_NSH_DISABLE_RM is not set +# CONFIG_NSH_DISABLE_RMDIR is not set +# CONFIG_NSH_DISABLE_SET is not set +# CONFIG_NSH_DISABLE_SH is not set +# CONFIG_NSH_DISABLE_SLEEP is not set +# CONFIG_NSH_DISABLE_TIME is not set +# CONFIG_NSH_DISABLE_TEST is not set +# CONFIG_NSH_DISABLE_UMOUNT is not set +# CONFIG_NSH_DISABLE_UNAME is not set +# CONFIG_NSH_DISABLE_UNSET is not set +# CONFIG_NSH_DISABLE_USLEEP is not set +# CONFIG_NSH_DISABLE_WGET is not set +# CONFIG_NSH_DISABLE_XD is not set +CONFIG_NSH_MMCSDMINOR=0 +CONFIG_NSH_MMCSDSLOTNO=0 + +# +# Configure Command Options +# +# CONFIG_NSH_CMDOPT_DF_H is not set +# CONFIG_NSH_CMDOPT_DD_STATS is not set +CONFIG_NSH_CODECS_BUFSIZE=128 +CONFIG_NSH_CMDOPT_HEXDUMP=y +CONFIG_NSH_PROC_MOUNTPOINT="/proc" +CONFIG_NSH_FILEIOSIZE=512 + +# +# Scripting Support +# +# CONFIG_NSH_DISABLESCRIPT is not set +# CONFIG_NSH_DISABLE_ITEF is not set +# CONFIG_NSH_DISABLE_LOOPS is not set + +# +# Console Configuration +# +CONFIG_NSH_CONSOLE=y +# CONFIG_NSH_ALTCONDEV is not set +CONFIG_NSH_ARCHINIT=y +# CONFIG_NSH_LOGIN is not set +# CONFIG_NSH_CONSOLE_LOGIN is not set + +# +# NxWidgets/NxWM +# + +# +# Platform-specific Support +# +# CONFIG_PLATFORM_CONFIGDATA is not set + +# +# System Libraries and NSH Add-Ons +# +# CONFIG_SYSTEM_CLE is not set +# CONFIG_SYSTEM_CUTERM is not set +# CONFIG_SYSTEM_FLASH_ERASEALL is not set +# CONFIG_SYSTEM_FREE is not set +# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_SYSTEM_HEXED is not set +CONFIG_SYSTEM_I2CTOOL=y +CONFIG_I2CTOOL_MINBUS=0 +CONFIG_I2CTOOL_MAXBUS=0 +CONFIG_I2CTOOL_MINADDR=0x03 +CONFIG_I2CTOOL_MAXADDR=0x77 +CONFIG_I2CTOOL_MAXREGADDR=0xff +CONFIG_I2CTOOL_DEFFREQ=400000 +# CONFIG_SYSTEM_INSTALL is not set +CONFIG_SYSTEM_RAMTEST=y +CONFIG_READLINE_HAVE_EXTMATCH=y +CONFIG_SYSTEM_READLINE=y +CONFIG_READLINE_ECHO=y +# CONFIG_READLINE_TABCOMPLETION is not set +# CONFIG_READLINE_CMD_HISTORY is not set +# CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_SYSTEM is not set +# CONFIG_SYSTEM_TEE is not set +# CONFIG_SYSTEM_UBLOXMODEM is not set +# CONFIG_SYSTEM_VI is not set +# CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/xmc4500-relax/nsh/setenv.sh b/configs/xmc4500-relax/nsh/setenv.sh new file mode 100644 index 00000000000..2116ba35be3 --- /dev/null +++ b/configs/xmc4500-relax/nsh/setenv.sh @@ -0,0 +1,77 @@ +#!/bin/bash +# configs/xmc4500-relax/nsh/Make.defs +# +# Copyright (C) 2017 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +if [ "$_" = "$0" ] ; then + echo "You must source this script, not run it!" 1>&2 + exit 1 +fi + +WD=`pwd` +if [ ! -x "setenv.sh" ]; then + echo "This script must be executed from the top-level NuttX build directory" + exit 1 +fi + +if [ -z "${PATH_ORIG}" ]; then + export PATH_ORIG="${PATH}" +fi + +# This is the Cygwin path to the location where I installed the Atmel GCC +# toolchain under Windows. You will also have to edit this if you install +# this toolchain in any other location +#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/Atmel/Atmel Toolchain/ARM GCC/Native/4.7.3.99/arm-gnu-toolchain/bin" + +# This is the Cygwin path to the location where I installed the CodeSourcery +# toolchain under windows. You will also have to edit this if you install +# the CodeSourcery toolchain in any other location +#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/CodeSourcery/Sourcery G++ Lite/bin" +#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/CodeSourcery/Sourcery_CodeBench_Lite_for_ARM_EABI/bin" +# export TOOLCHAIN_BIN="/cygdrive/c/Users/MyName/MentorGraphics/Sourcery_CodeBench_Lite_for_ARM_EABI/bin" + +# This is the location where I installed the ARM "GNU Tools for ARM Embedded Processors" +# You can this free toolchain here https://launchpad.net/gcc-arm-embedded +export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/GNU Tools ARM Embedded/4.9 2015q2/bin" + +# This is the path to the location where I installed the devkitARM toolchain +# You can get this free toolchain from http://devkitpro.org/ or http://sourceforge.net/projects/devkitpro/ +#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/devkitARM/bin" + +# This is the Cygwin path to the location where I build the buildroot +# toolchain. +# export TOOLCHAIN_BIN="${WD}/../buildroot/build_arm_nofpu/staging_dir/bin" + +# Add the path to the toolchain to the PATH varialble +export PATH="${TOOLCHAIN_BIN}:/sbin:/usr/sbin:${PATH_ORIG}" + +echo "PATH : ${PATH}" diff --git a/configs/xmc4500-relax/src/Makefile b/configs/xmc4500-relax/src/Makefile new file mode 100644 index 00000000000..d609e49ac8e --- /dev/null +++ b/configs/xmc4500-relax/src/Makefile @@ -0,0 +1,55 @@ +############################################################################ +# configs/xmc4500-relax/src/Makefile +# +# Copyright (C) 2017 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +-include $(TOPDIR)/Make.defs + +ASRCS = +CSRCS = xmc4_boot.c xmc4_bringup.c + +ifeq ($(CONFIG_BUTTONS),y) +CSRCS += xmc4_buttons.c +endif + +ifeq ($(CONFIG_USERLED),y) +CSRCS += xmc4_autoleds.c +else +CSRCS += xmc4_userleds.c +endif + +ifeq ($(CONFIG_LIB_BOARDCTL),y) +CSRCS += xmc4_appinit.c +endif + +include $(TOPDIR)/configs/Board.mk diff --git a/configs/xmc4500-relax/src/xmc4500-relax.h b/configs/xmc4500-relax/src/xmc4500-relax.h new file mode 100644 index 00000000000..6a004c82448 --- /dev/null +++ b/configs/xmc4500-relax/src/xmc4500-relax.h @@ -0,0 +1,78 @@ +/**************************************************************************** + * configs/xmc4500-relax/src/xmc4500-relax.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __CONFIGS_XMC4500_RELAX_SRC_XMC4500_RELAX_H +#define __CONFIGS_XMC4500_RELAX_SRC_XMC4500_RELAX_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* LEDs */ + +/* BUTTONS */ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public data + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: xmc4_bringup + * + * Description: + * Bring up board features + * + ****************************************************************************/ + +int xmc4_bringup(void); + +#endif /* __ASSEMBLY__ */ +#endif /* __CONFIGS_XMC4500_RELAX_SRC_XMC4500_RELAX_H */ diff --git a/configs/xmc4500-relax/src/xmc4_appinit.c b/configs/xmc4500-relax/src/xmc4_appinit.c new file mode 100644 index 00000000000..8e1fa87efe0 --- /dev/null +++ b/configs/xmc4500-relax/src/xmc4_appinit.c @@ -0,0 +1,80 @@ +/**************************************************************************** + * config/xmc4500-relax/src/xmc4_appinit.c + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_app_initialize + * + * Description: + * Perform application specific initialization. This function is never + * called directly from application code, but only indirectly via the + * (non-standard) boardctl() interface using the command BOARDIOC_INIT. + * + * Input Parameters: + * arg - The boardctl() argument is passed to the board_app_initialize() + * implementation without modification. The argument has no + * meaning to NuttX; the meaning of the argument is a contract + * between the board-specific initalization logic and the the + * matching application logic. The value cold be such things as a + * mode enumeration value, a set of DIP switch switch settings, a + * pointer to configuration data read from a file or serial FLASH, + * or whatever you would like to do with it. Every implementation + * should accept zero/NULL as a default configuration. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned on + * any failure to indicate the nature of the failure. + * + ****************************************************************************/ + +int board_app_initialize(uintptr_t arg) +{ +#ifndef CONFIG_BOARD_INITIALIZE + /* Perform board initialization */ + + return xmc4_bringup(); +#else + return OK; +#endif /* CONFIG_BOARD_INITIALIZE */ +} diff --git a/configs/xmc4500-relax/src/xmc4_autoleds.c b/configs/xmc4500-relax/src/xmc4_autoleds.c new file mode 100644 index 00000000000..7fd88f7866b --- /dev/null +++ b/configs/xmc4500-relax/src/xmc4_autoleds.c @@ -0,0 +1,80 @@ +/**************************************************************************** + * configs/xmc4500-relax/include/xmc4_autoleds.c + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "xmc4500-relax.h" + +#ifdef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +void board_autoled_initialize(void) +{ +#warning Missing logic +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ +#warning Missing logic +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ +#warning Missing logic +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/configs/xmc4500-relax/src/xmc4_boot.c b/configs/xmc4500-relax/src/xmc4_boot.c new file mode 100644 index 00000000000..994cdf86c6a --- /dev/null +++ b/configs/xmc4500-relax/src/xmc4_boot.c @@ -0,0 +1,91 @@ +/************************************************************************************ + * configs/xmc4500-relax/src/xmc4_boot.c + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include +#include + +#include "xmc4500-relax.h" + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: xmc4_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. This entry point + * is called early in the initialization -- after all memory has been configured + * and mapped but before any devices have been initialized. + * + ************************************************************************************/ + +void xmc4_boardinitialize(void) +{ +#ifdef CONFIG_ARCH_LEDS + /* Configure on-board LEDs if LED support has been selected. */ + + board_autoled_initialize(); +#endif +} + +/**************************************************************************** + * Name: board_initialize + * + * Description: + * If CONFIG_BOARD_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_initialize(). board_initialize() will be + * called immediately after up_intitialize() is called and just before the + * initial application is started. This additional initialization phase + * may be used, for example, to initialize board-specific device drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_INITIALIZE +void board_initialize(void) +{ + /* Perform board initialization */ + + (void)xmc4_bringup(); +} +#endif /* CONFIG_BOARD_INITIALIZE */ + diff --git a/configs/xmc4500-relax/src/xmc4_bringup.c b/configs/xmc4500-relax/src/xmc4_bringup.c new file mode 100644 index 00000000000..ae7b5a593eb --- /dev/null +++ b/configs/xmc4500-relax/src/xmc4_bringup.c @@ -0,0 +1,65 @@ +/**************************************************************************** + * config/samv71-xult/src/xmc4_bringup.c + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: xmc4_bringup + * + * Description: + * Bring up board features + * + ****************************************************************************/ + +int xmc4_bringup(void) +{ + return OK; +} diff --git a/configs/xmc4500-relax/src/xmc4_buttons.c b/configs/xmc4500-relax/src/xmc4_buttons.c new file mode 100644 index 00000000000..24f9e05a206 --- /dev/null +++ b/configs/xmc4500-relax/src/xmc4_buttons.c @@ -0,0 +1,78 @@ +/**************************************************************************** + * configs/xmc4500-relax/src/xmc4_buttons.c + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include "xmc4500-relax.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_button_initialize + ****************************************************************************/ + +void board_button_initialize(void) +{ +#warning Missing logic +} + +/**************************************************************************** + * Name: board_buttons + ****************************************************************************/ + +uint8_t board_buttons(void) +{ +#warning Missing logic + return 0; +} + +/**************************************************************************** + * Name: board_button_irq + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQBUTTONS +int board_button_irq(int id, xcpt_t irqhandler, FAR void *arg) +{ +#warning Missing logic + return -ENOSYS; +} +#endif /* CONFIG_ARCH_IRQBUTTONS */ diff --git a/configs/xmc4500-relax/src/xmc4_userleds.c b/configs/xmc4500-relax/src/xmc4_userleds.c new file mode 100644 index 00000000000..8bb69336f7e --- /dev/null +++ b/configs/xmc4500-relax/src/xmc4_userleds.c @@ -0,0 +1,75 @@ +/**************************************************************************** + * configs/xmc4500-relax/src/xmc4_userleds.c + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include +#include "xmc4500-relax.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_userled_initialize + ****************************************************************************/ + +void board_userled_initialize(void) +{ +#warning Missing logic +} + +/**************************************************************************** + * Name: board_userled + ****************************************************************************/ + +void board_userled(int led, bool ledon) +{ +#warning Missing logic +} + +/**************************************************************************** + * Name: board_userled_all + ****************************************************************************/ + +void board_userled_all(uint8_t ledset) +{ +#warning Missing logic +} From 5693f26a5ed42d2120fa2adb222c38696965dc36 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 16 Mar 2017 11:30:02 -0600 Subject: [PATCH 10/21] XMC4xx: Fix several early compilation problems. --- arch/arm/include/xmc4/chip.h | 4 +- arch/arm/include/xmc4/irq.h | 38 ++-- arch/arm/include/xmc4/xmc4500_irq.h | 236 +++++++++++----------- arch/arm/src/xmc4/chip/xmc4_scu.h | 14 +- arch/arm/src/xmc4/xmc4_clockconfig.c | 50 ++--- arch/arm/src/xmc4/xmc4_irq.c | 1 + configs/xmc4500-relax/include/board.h | 62 ++++++ configs/xmc4500-relax/src/xmc4500-relax.h | 16 +- 8 files changed, 248 insertions(+), 173 deletions(-) diff --git a/arch/arm/include/xmc4/chip.h b/arch/arm/include/xmc4/chip.h index 7ea5157a736..019c1078230 100644 --- a/arch/arm/include/xmc4/chip.h +++ b/arch/arm/include/xmc4/chip.h @@ -48,11 +48,11 @@ /* Get customizations for each supported chip */ -#if defined(CONFIG_ARCH_XMC4500) +#if defined(CONFIG_ARCH_CHIP_XMC4500) # define XM4_NUSIC 3 /* Three USIC modules: USCI0-2 */ #else -# error "Unsupported XMC4000 chip" +# error "Unsupported XMC4xxx chip" #endif /* NVIC priority levels *************************************************************/ diff --git a/arch/arm/include/xmc4/irq.h b/arch/arm/include/xmc4/irq.h index 65300dcee3b..10fc176a43c 100644 --- a/arch/arm/include/xmc4/irq.h +++ b/arch/arm/include/xmc4/irq.h @@ -37,8 +37,8 @@ * through nuttx/irq.h */ -#ifndef __ARCH_ARM_INCLUDE_XM4_IRQ_H -#define __ARCH_ARM_INCLUDE_XM4_IRQ_H +#ifndef __ARCH_ARM_INCLUDE_XMC4_IRQ_H +#define __ARCH_ARM_INCLUDE_XMC4_IRQ_H /************************************************************************************ * Included Files @@ -58,26 +58,26 @@ /* Processor Exceptions (vectors 0-15) */ -#define XM4_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */ - /* Vector 0: Reset stack pointer value */ - /* Vector 1: Reset (not handler as an IRQ) */ -#define XM4_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */ -#define XM4_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */ -#define XM4_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */ -#define XM4_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */ -#define XM4_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */ - /* Vectors 7-10: Reserved */ -#define XM4_IRQ_SVCALL (11) /* Vector 11: SVC call */ -#define XM4_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */ - /* Vector 13: Reserved */ -#define XM4_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */ -#define XM4_IRQ_SYSTICK (15) /* Vector 15: System tick */ +#define XMC4_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */ + /* Vector 0: Reset stack pointer value */ + /* Vector 1: Reset (not handler as an IRQ) */ +#define XMC4_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */ +#define XMC4_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */ +#define XMC4_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */ +#define XMC4_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */ +#define XMC4_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */ + /* Vectors 7-10: Reserved */ +#define XMC4_IRQ_SVCALL (11) /* Vector 11: SVC call */ +#define XMC4_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */ + /* Vector 13: Reserved */ +#define XMC4_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */ +#define XMC4_IRQ_SYSTICK (15) /* Vector 15: System tick */ /* External interrupts (vectors >= 16). These definitions are chip-specific */ -#define XM4_IRQ_FIRST (16) /* Vector number of the first external interrupt */ +#define XMC4_IRQ_FIRST (16) /* Vector number of the first external interrupt */ -#if defined(CONFIG_ARCH_XMC4500) +#if defined(CONFIG_ARCH_CHIP_XMC4500) # include #else /* The interrupt vectors for other parts are defined in other documents and may or @@ -116,5 +116,5 @@ extern "C" #endif #endif -#endif /* __ARCH_ARM_INCLUDE_XM4_IRQ_H */ +#endif /* __ARCH_ARM_INCLUDE_XMC4_IRQ_H */ diff --git a/arch/arm/include/xmc4/xmc4500_irq.h b/arch/arm/include/xmc4/xmc4500_irq.h index 1005adeb495..dfd21d6c21d 100644 --- a/arch/arm/include/xmc4/xmc4500_irq.h +++ b/arch/arm/include/xmc4/xmc4500_irq.h @@ -37,8 +37,8 @@ * through nuttx/irq.h */ -#ifndef xmc4__ARCH_ARM_INCLUDE_XM4_XM4500_IRQ_H -#define xmc4__ARCH_ARM_INCLUDE_XM4_XM4500_IRQ_H +#ifndef xmc4__ARCH_ARM_INCLUDE_XMC4_XM4500_IRQ_H +#define xmc4__ARCH_ARM_INCLUDE_XMC4_XM4500_IRQ_H /***************************************************************************** * Included Files @@ -75,125 +75,125 @@ * USCI - Universal Serial Interface */ -#define XM4_IRQ_SCU (XM4_IRQ_FIRST+0) /* 0: System Control */ -#define XM4_IRQ_ERU0_SR0 (XM4_IRQ_FIRST+1) /* 1: ERU0, SR0 */ -#define XM4_IRQ_ERU0_SR1 (XM4_IRQ_FIRST+2) /* 2: ERU0, SR1 */ -#define XM4_IRQ_ERU0_SR2 (XM4_IRQ_FIRST+3) /* 3: ERU0, SR2 */ -#define XM4_IRQ_ERU0_SR3 (XM4_IRQ_FIRST+4) /* 4: ERU0, SR3 */ -#define XM4_IRQ_ERU1_SR0 (XM4_IRQ_FIRST+5) /* 5: ERU1, SR0 */ -#define XM4_IRQ_ERU1_SR1 (XM4_IRQ_FIRST+6) /* 6: ERU1, SR1 */ -#define XM4_IRQ_ERU1_SR2 (XM4_IRQ_FIRST+7) /* 7: ERU1, SR2 */ -#define XM4_IRQ_ERU1_SR3 (XM4_IRQ_FIRST+8) /* 8: ERU1, SR3 */ -#define XM4_IRQ_RESVD009 (XM4_IRQ_FIRST+9) /* 9: Reserved */ -#define XM4_IRQ_RESVD010 (XM4_IRQ_FIRST+10) /* 10: Reserved */ -#define XM4_IRQ_RESVD011 (XM4_IRQ_FIRST+11) /* 11: Reserved */ -#define XM4_IRQ_PMU1_SR0 (XM4_IRQ_FIRST+12) /* 12: PMU, SR0 */ -#define XM4_IRQ_RESVD011 (XM4_IRQ_FIRST+13) /* 13: Reserved */ -#define XM4_IRQ_VADC_COSR0 (XM4_IRQ_FIRST+14) /* 14: ADC Common Block 0 */ -#define XM4_IRQ_VADC_COSR1 (XM4_IRQ_FIRST+15) /* 15: ADC Common Block 1 */ -#define XM4_IRQ_VADC_COSR2 (XM4_IRQ_FIRST+16) /* 16: ADC Common Block 2 */ -#define XM4_IRQ_VADC_COSR3 (XM4_IRQ_FIRST+17) /* 17: ADC Common Block 3 */ -#define XM4_IRQ_VADC_GOSR0 (XM4_IRQ_FIRST+18) /* 18: ADC Group 0, SR0 */ -#define XM4_IRQ_VADC_GOSR1 (XM4_IRQ_FIRST+19) /* 19: ADC Group 0, SR1 */ -#define XM4_IRQ_VADC_GOSR2 (XM4_IRQ_FIRST+20) /* 20: ADC Group 0, SR2 */ -#define XM4_IRQ_VADC_GOSR3 (XM4_IRQ_FIRST+21) /* 21: ADC Group 0, SR3 */ -#define XM4_IRQ_VADC_G1SR0 (XM4_IRQ_FIRST+22) /* 22: ADC Group 1, SR0 */ -#define XM4_IRQ_VADC_G1SR1 (XM4_IRQ_FIRST+23) /* 23: ADC Group 1, SR1 */ -#define XM4_IRQ_VADC_G1SR2 (XM4_IRQ_FIRST+24) /* 24: ADC Group 1, SR2 */ -#define XM4_IRQ_VADC_G1SR3 (XM4_IRQ_FIRST+25) /* 25: ADC Group 1, SR3 */ -#define XM4_IRQ_VADC_G2SR0 (XM4_IRQ_FIRST+26) /* 26: ADC Group 2, SR0 */ -#define XM4_IRQ_VADC_G2SR1 (XM4_IRQ_FIRST+27) /* 27: ADC Group 2, SR1 */ -#define XM4_IRQ_VADC_G2SR2 (XM4_IRQ_FIRST+28) /* 28: ADC Group 2, SR2 */ -#define XM4_IRQ_VADC_G2SR3 (XM4_IRQ_FIRST+29) /* 29: ADC Group 2, SR3 */ -#define XM4_IRQ_VADC_G3SR0 (XM4_IRQ_FIRST+30) /* 30: ADC Group 3, SR0 */ -#define XM4_IRQ_VADC_G3SR1 (XM4_IRQ_FIRST+31) /* 31: ADC Group 3, SR1 */ -#define XM4_IRQ_VADC_G3SR2 (XM4_IRQ_FIRST+32) /* 32: ADC Group 3, SR2 */ -#define XM4_IRQ_VADC_G3SR3 (XM4_IRQ_FIRST+33) /* 33: ADC Group 3, SR3 */ -#define XM4_IRQ_DSD_SRM0 (XM4_IRQ_FIRST+34) /* 34: DSD Main, SRM0 */ -#define XM4_IRQ_DSD_SRM1 (XM4_IRQ_FIRST+35) /* 35: DSD Main, SRM1 */ -#define XM4_IRQ_DSD_SRM2 (XM4_IRQ_FIRST+36) /* 36: DSD Main, SRM2 */ -#define XM4_IRQ_DSD_SRM3 (XM4_IRQ_FIRST+37) /* 37: DSD Main, SRM3 */ -#define XM4_IRQ_DSD_SRA0 (XM4_IRQ_FIRST+38) /* 38: DSD Auxiliary, SRA0 */ -#define XM4_IRQ_DSD_SRA1 (XM4_IRQ_FIRST+39) /* 39: DSD Auxiliary, SRA1 */ -#define XM4_IRQ_DSD_SRA2 (XM4_IRQ_FIRST+40) /* 40: DSD Auxiliary, SRA2 */ -#define XM4_IRQ_DSD_SRA3 (XM4_IRQ_FIRST+41) /* 41: DSD Auxiliary, SRA3 */ -#define XM4_IRQ_DAC_SR0 (XM4_IRQ_FIRST+42) /* 42: DAC, SR0 */ -#define XM4_IRQ_DAC_SR1 (XM4_IRQ_FIRST+43) /* 43: DAC, SR1 */ -#define XM4_IRQ_CCU40_SR0 (XM4_IRQ_FIRST+44) /* 44: CCU4 Module 0, SR0 */ -#define XM4_IRQ_CCU40_SR1 (XM4_IRQ_FIRST+45) /* 45: CCU4 Module 0, SR1 */ -#define XM4_IRQ_CCU40_SR2 (XM4_IRQ_FIRST+46) /* 46: CCU4 Module 0, SR2 */ -#define XM4_IRQ_CCU40_SR3 (XM4_IRQ_FIRST+47) /* 47: CCU4 Module 0, SR3 */ -#define XM4_IRQ_CCU41_SR0 (XM4_IRQ_FIRST+48) /* 48: CCU4 Module 1, SR0 */ -#define XM4_IRQ_CCU41_SR1 (XM4_IRQ_FIRST+49) /* 49: CCU4 Module 1, SR1 */ -#define XM4_IRQ_CCU41_SR2 (XM4_IRQ_FIRST+50) /* 50: CCU4 Module 1, SR2 */ -#define XM4_IRQ_CCU41_SR3 (XM4_IRQ_FIRST+51) /* 51: CCU4 Module 1, SR3 */ -#define XM4_IRQ_CCU42_SR0 (XM4_IRQ_FIRST+52) /* 52: CCU4 Module 2, SR0 */ -#define XM4_IRQ_CCU42_SR1 (XM4_IRQ_FIRST+53) /* 53: CCU4 Module 2, SR1 */ -#define XM4_IRQ_CCU42_SR2 (XM4_IRQ_FIRST+54) /* 54: CCU4 Module 2, SR2 */ -#define XM4_IRQ_CCU42_SR3 (XM4_IRQ_FIRST+55) /* 55: CCU4 Module 2, SR3 */ -#define XM4_IRQ_CCU43_SR0 (XM4_IRQ_FIRST+56) /* 56: CCU4 Module 3, SR0 */ -#define XM4_IRQ_CCU43_SR1 (XM4_IRQ_FIRST+57) /* 57: CCU4 Module 3, SR1 */ -#define XM4_IRQ_CCU43_SR2 (XM4_IRQ_FIRST+58) /* 58: CCU4 Module 3, SR2 */ -#define XM4_IRQ_CCU43_SR3 (XM4_IRQ_FIRST+59) /* 59: CCU4 Module 3, SR3 */ -#define XM4_IRQ_CCU80_SR0 (XM4_IRQ_FIRST+60) /* 60: CCU8 Module 0, SR0 */ -#define XM4_IRQ_CCU80_SR1 (XM4_IRQ_FIRST+61) /* 61: CCU8 Module 0, SR1 */ -#define XM4_IRQ_CCU80_SR2 (XM4_IRQ_FIRST+62) /* 62: CCU8 Module 0, SR2 */ -#define XM4_IRQ_CCU80_SR3 (XM4_IRQ_FIRST+63) /* 63: CCU8 Module 0, SR3 */ -#define XM4_IRQ_CCU81_SR0 (XM4_IRQ_FIRST+64) /* 64: CCU8 Module 1, SR0 */ -#define XM4_IRQ_CCU81_SR1 (XM4_IRQ_FIRST+65) /* 65: CCU8 Module 1, SR1 */ -#define XM4_IRQ_CCU81_SR2 (XM4_IRQ_FIRST+66) /* 66: CCU8 Module 1, SR2 */ -#define XM4_IRQ_CCU81_SR3 (XM4_IRQ_FIRST+67) /* 67: CCU8 Module 1, SR3 */ -#define XM4_IRQ_POSIF0_SR0 (XM4_IRQ_FIRST+68) /* 68: POSIF Module 0, SR0 */ -#define XM4_IRQ_POSIF0_SR1 (XM4_IRQ_FIRST+69) /* 69: POSIF Module 0, SR1 */ -#define XM4_IRQ_POSIF1_SR0 (XM4_IRQ_FIRST+70) /* 70: POSIF Module 1, SR0 */ -#define XM4_IRQ_POSIF1_SR1 (XM4_IRQ_FIRST+71) /* 71: POSIF Module 1, SR1 */ -#define XM4_IRQ_RESVD072 (XM4_IRQ_FIRST+72) /* 72: Reserved */ -#define XM4_IRQ_RESVD073 (XM4_IRQ_FIRST+73) /* 73: Reserved */ -#define XM4_IRQ_RESVD074 (XM4_IRQ_FIRST+74) /* 74: Reserved */ -#define XM4_IRQ_RESVD075 (XM4_IRQ_FIRST+75) /* 75: Reserved */ -#define XM4_IRQ_CAN_SR0 (XM4_IRQ_FIRST+76) /* 76: MultiCAN, SR0 */ -#define XM4_IRQ_CAN_SR1 (XM4_IRQ_FIRST+77) /* 77: MultiCAN, SR1 */ -#define XM4_IRQ_CAN_SR2 (XM4_IRQ_FIRST+78) /* 78: MultiCAN, SR2 */ -#define XM4_IRQ_CAN_SR3 (XM4_IRQ_FIRST+79) /* 79: MultiCAN, SR3 */ -#define XM4_IRQ_CAN_SR4 (XM4_IRQ_FIRST+80) /* 80: MultiCAN, SR4 */ -#define XM4_IRQ_CAN_SR5 (XM4_IRQ_FIRST+81) /* 81: MultiCAN, SR5 */ -#define XM4_IRQ_CAN_SR6 (XM4_IRQ_FIRST+82) /* 82: MultiCAN, SR6 */ -#define XM4_IRQ_CAN_SR7 (XM4_IRQ_FIRST+83) /* 83: MultiCAN, SR7 */ -#define XM4_IRQ_USIC0_SR0 (XM4_IRQ_FIRST+84) /* 84: USIC0 Channel, SR0 */ -#define XM4_IRQ_USIC0_SR1 (XM4_IRQ_FIRST+85) /* 85: USIC0 Channel, SR1 */ -#define XM4_IRQ_USIC0_SR2 (XM4_IRQ_FIRST+86) /* 86: USIC0 Channel, SR2 */ -#define XM4_IRQ_USIC0_SR3 (XM4_IRQ_FIRST+87) /* 87: USIC0 Channel, SR3 */ -#define XM4_IRQ_USIC0_SR4 (XM4_IRQ_FIRST+88) /* 88: USIC0 Channel, SR4 */ -#define XM4_IRQ_USIC0_SR5 (XM4_IRQ_FIRST+89) /* 89: USIC0 Channel, SR5 */ -#define XM4_IRQ_USIC1_SR0 (XM4_IRQ_FIRST+90) /* 90: USIC1 Channel, SR0 */ -#define XM4_IRQ_USIC1_SR1 (XM4_IRQ_FIRST+91) /* 91: USIC1 Channel, SR1 */ -#define XM4_IRQ_USIC1_SR2 (XM4_IRQ_FIRST+92) /* 92: USIC1 Channel, SR2 */ -#define XM4_IRQ_USIC1_SR3 (XM4_IRQ_FIRST+93) /* 93: USIC1 Channel, SR3 */ -#define XM4_IRQ_USIC1_SR4 (XM4_IRQ_FIRST+94) /* 94: USIC1 Channel, SR4 */ -#define XM4_IRQ_USIC1_SR5 (XM4_IRQ_FIRST+95) /* 95: USIC1 Channel, SR5 */ -#define XM4_IRQ_USIC2_SR0 (XM4_IRQ_FIRST+96) /* 96: USIC1 Channel, SR0 */ -#define XM4_IRQ_USIC2_SR1 (XM4_IRQ_FIRST+97) /* 97: USIC1 Channel, SR1 */ -#define XM4_IRQ_USIC2_SR2 (XM4_IRQ_FIRST+98) /* 98: USIC1 Channel, SR2 */ -#define XM4_IRQ_USIC2_SR3 (XM4_IRQ_FIRST+99) /* 99: USIC1 Channel, SR3 */ -#define XM4_IRQ_USIC2_SR4 (XM4_IRQ_FIRST+100) /* 100: USIC1 Channel, SR4 */ -#define XM4_IRQ_USIC2_SR5 (XM4_IRQ_FIRST+101) /* 101: USIC1 Channel, SR5 */ -#define XM4_IRQ_LEDTS0_SR0 (XM4_IRQ_FIRST+102) /* 102: LEDTS0, SR0 */ -#define XM4_IRQ_RESVD103 (XM4_IRQ_FIRST+103) /* 103: Reserved */ -#define XM4_IRQ_FCR_SR0 (XM4_IRQ_FIRST+104) /* 102: FCE, SR0 */ -#define XM4_IRQ_GPCMA0_SR0 (XM4_IRQ_FIRST+105) /* 105: GPDMA0, SR0 */ -#define XM4_IRQ_SDMMC_SR0 (XM4_IRQ_FIRST+106) /* 106: SDMMC, SR0 */ -#define XM4_IRQ_USB0_SR0 (XM4_IRQ_FIRST+107) /* 107: USB, SR0 */ -#define XM4_IRQ_ETH0_SR0 (XM4_IRQ_FIRST+108) /* 108: Ethernet, module 0, SR0 */ -#define XM4_IRQ_RESVD109 (XM4_IRQ_FIRST+109) /* 109: Reserved */ -#define XM4_IRQ_GPCMA1_SR0 (XM4_IRQ_FIRST+110) /* 110: GPDMA1, SR0 */ -#define XM4_IRQ_RESVD111 (XM4_IRQ_FIRST+111) /* 111: Reserved */ +#define XMC4_IRQ_SCU (XMC4_IRQ_FIRST+0) /* 0: System Control */ +#define XMC4_IRQ_ERU0_SR0 (XMC4_IRQ_FIRST+1) /* 1: ERU0, SR0 */ +#define XMC4_IRQ_ERU0_SR1 (XMC4_IRQ_FIRST+2) /* 2: ERU0, SR1 */ +#define XMC4_IRQ_ERU0_SR2 (XMC4_IRQ_FIRST+3) /* 3: ERU0, SR2 */ +#define XMC4_IRQ_ERU0_SR3 (XMC4_IRQ_FIRST+4) /* 4: ERU0, SR3 */ +#define XMC4_IRQ_ERU1_SR0 (XMC4_IRQ_FIRST+5) /* 5: ERU1, SR0 */ +#define XMC4_IRQ_ERU1_SR1 (XMC4_IRQ_FIRST+6) /* 6: ERU1, SR1 */ +#define XMC4_IRQ_ERU1_SR2 (XMC4_IRQ_FIRST+7) /* 7: ERU1, SR2 */ +#define XMC4_IRQ_ERU1_SR3 (XMC4_IRQ_FIRST+8) /* 8: ERU1, SR3 */ +#define XMC4_IRQ_RESVD009 (XMC4_IRQ_FIRST+9) /* 9: Reserved */ +#define XMC4_IRQ_RESVD010 (XMC4_IRQ_FIRST+10) /* 10: Reserved */ +#define XMC4_IRQ_RESVD011 (XMC4_IRQ_FIRST+11) /* 11: Reserved */ +#define XMC4_IRQ_PMU1_SR0 (XMC4_IRQ_FIRST+12) /* 12: PMU, SR0 */ +#define XMC4_IRQ_RESVD011 (XMC4_IRQ_FIRST+13) /* 13: Reserved */ +#define XMC4_IRQ_VADC_COSR0 (XMC4_IRQ_FIRST+14) /* 14: ADC Common Block 0 */ +#define XMC4_IRQ_VADC_COSR1 (XMC4_IRQ_FIRST+15) /* 15: ADC Common Block 1 */ +#define XMC4_IRQ_VADC_COSR2 (XMC4_IRQ_FIRST+16) /* 16: ADC Common Block 2 */ +#define XMC4_IRQ_VADC_COSR3 (XMC4_IRQ_FIRST+17) /* 17: ADC Common Block 3 */ +#define XMC4_IRQ_VADC_GOSR0 (XMC4_IRQ_FIRST+18) /* 18: ADC Group 0, SR0 */ +#define XMC4_IRQ_VADC_GOSR1 (XMC4_IRQ_FIRST+19) /* 19: ADC Group 0, SR1 */ +#define XMC4_IRQ_VADC_GOSR2 (XMC4_IRQ_FIRST+20) /* 20: ADC Group 0, SR2 */ +#define XMC4_IRQ_VADC_GOSR3 (XMC4_IRQ_FIRST+21) /* 21: ADC Group 0, SR3 */ +#define XMC4_IRQ_VADC_G1SR0 (XMC4_IRQ_FIRST+22) /* 22: ADC Group 1, SR0 */ +#define XMC4_IRQ_VADC_G1SR1 (XMC4_IRQ_FIRST+23) /* 23: ADC Group 1, SR1 */ +#define XMC4_IRQ_VADC_G1SR2 (XMC4_IRQ_FIRST+24) /* 24: ADC Group 1, SR2 */ +#define XMC4_IRQ_VADC_G1SR3 (XMC4_IRQ_FIRST+25) /* 25: ADC Group 1, SR3 */ +#define XMC4_IRQ_VADC_G2SR0 (XMC4_IRQ_FIRST+26) /* 26: ADC Group 2, SR0 */ +#define XMC4_IRQ_VADC_G2SR1 (XMC4_IRQ_FIRST+27) /* 27: ADC Group 2, SR1 */ +#define XMC4_IRQ_VADC_G2SR2 (XMC4_IRQ_FIRST+28) /* 28: ADC Group 2, SR2 */ +#define XMC4_IRQ_VADC_G2SR3 (XMC4_IRQ_FIRST+29) /* 29: ADC Group 2, SR3 */ +#define XMC4_IRQ_VADC_G3SR0 (XMC4_IRQ_FIRST+30) /* 30: ADC Group 3, SR0 */ +#define XMC4_IRQ_VADC_G3SR1 (XMC4_IRQ_FIRST+31) /* 31: ADC Group 3, SR1 */ +#define XMC4_IRQ_VADC_G3SR2 (XMC4_IRQ_FIRST+32) /* 32: ADC Group 3, SR2 */ +#define XMC4_IRQ_VADC_G3SR3 (XMC4_IRQ_FIRST+33) /* 33: ADC Group 3, SR3 */ +#define XMC4_IRQ_DSD_SRM0 (XMC4_IRQ_FIRST+34) /* 34: DSD Main, SRM0 */ +#define XMC4_IRQ_DSD_SRM1 (XMC4_IRQ_FIRST+35) /* 35: DSD Main, SRM1 */ +#define XMC4_IRQ_DSD_SRM2 (XMC4_IRQ_FIRST+36) /* 36: DSD Main, SRM2 */ +#define XMC4_IRQ_DSD_SRM3 (XMC4_IRQ_FIRST+37) /* 37: DSD Main, SRM3 */ +#define XMC4_IRQ_DSD_SRA0 (XMC4_IRQ_FIRST+38) /* 38: DSD Auxiliary, SRA0 */ +#define XMC4_IRQ_DSD_SRA1 (XMC4_IRQ_FIRST+39) /* 39: DSD Auxiliary, SRA1 */ +#define XMC4_IRQ_DSD_SRA2 (XMC4_IRQ_FIRST+40) /* 40: DSD Auxiliary, SRA2 */ +#define XMC4_IRQ_DSD_SRA3 (XMC4_IRQ_FIRST+41) /* 41: DSD Auxiliary, SRA3 */ +#define XMC4_IRQ_DAC_SR0 (XMC4_IRQ_FIRST+42) /* 42: DAC, SR0 */ +#define XMC4_IRQ_DAC_SR1 (XMC4_IRQ_FIRST+43) /* 43: DAC, SR1 */ +#define XMC4_IRQ_CCU40_SR0 (XMC4_IRQ_FIRST+44) /* 44: CCU4 Module 0, SR0 */ +#define XMC4_IRQ_CCU40_SR1 (XMC4_IRQ_FIRST+45) /* 45: CCU4 Module 0, SR1 */ +#define XMC4_IRQ_CCU40_SR2 (XMC4_IRQ_FIRST+46) /* 46: CCU4 Module 0, SR2 */ +#define XMC4_IRQ_CCU40_SR3 (XMC4_IRQ_FIRST+47) /* 47: CCU4 Module 0, SR3 */ +#define XMC4_IRQ_CCU41_SR0 (XMC4_IRQ_FIRST+48) /* 48: CCU4 Module 1, SR0 */ +#define XMC4_IRQ_CCU41_SR1 (XMC4_IRQ_FIRST+49) /* 49: CCU4 Module 1, SR1 */ +#define XMC4_IRQ_CCU41_SR2 (XMC4_IRQ_FIRST+50) /* 50: CCU4 Module 1, SR2 */ +#define XMC4_IRQ_CCU41_SR3 (XMC4_IRQ_FIRST+51) /* 51: CCU4 Module 1, SR3 */ +#define XMC4_IRQ_CCU42_SR0 (XMC4_IRQ_FIRST+52) /* 52: CCU4 Module 2, SR0 */ +#define XMC4_IRQ_CCU42_SR1 (XMC4_IRQ_FIRST+53) /* 53: CCU4 Module 2, SR1 */ +#define XMC4_IRQ_CCU42_SR2 (XMC4_IRQ_FIRST+54) /* 54: CCU4 Module 2, SR2 */ +#define XMC4_IRQ_CCU42_SR3 (XMC4_IRQ_FIRST+55) /* 55: CCU4 Module 2, SR3 */ +#define XMC4_IRQ_CCU43_SR0 (XMC4_IRQ_FIRST+56) /* 56: CCU4 Module 3, SR0 */ +#define XMC4_IRQ_CCU43_SR1 (XMC4_IRQ_FIRST+57) /* 57: CCU4 Module 3, SR1 */ +#define XMC4_IRQ_CCU43_SR2 (XMC4_IRQ_FIRST+58) /* 58: CCU4 Module 3, SR2 */ +#define XMC4_IRQ_CCU43_SR3 (XMC4_IRQ_FIRST+59) /* 59: CCU4 Module 3, SR3 */ +#define XMC4_IRQ_CCU80_SR0 (XMC4_IRQ_FIRST+60) /* 60: CCU8 Module 0, SR0 */ +#define XMC4_IRQ_CCU80_SR1 (XMC4_IRQ_FIRST+61) /* 61: CCU8 Module 0, SR1 */ +#define XMC4_IRQ_CCU80_SR2 (XMC4_IRQ_FIRST+62) /* 62: CCU8 Module 0, SR2 */ +#define XMC4_IRQ_CCU80_SR3 (XMC4_IRQ_FIRST+63) /* 63: CCU8 Module 0, SR3 */ +#define XMC4_IRQ_CCU81_SR0 (XMC4_IRQ_FIRST+64) /* 64: CCU8 Module 1, SR0 */ +#define XMC4_IRQ_CCU81_SR1 (XMC4_IRQ_FIRST+65) /* 65: CCU8 Module 1, SR1 */ +#define XMC4_IRQ_CCU81_SR2 (XMC4_IRQ_FIRST+66) /* 66: CCU8 Module 1, SR2 */ +#define XMC4_IRQ_CCU81_SR3 (XMC4_IRQ_FIRST+67) /* 67: CCU8 Module 1, SR3 */ +#define XMC4_IRQ_POSIF0_SR0 (XMC4_IRQ_FIRST+68) /* 68: POSIF Module 0, SR0 */ +#define XMC4_IRQ_POSIF0_SR1 (XMC4_IRQ_FIRST+69) /* 69: POSIF Module 0, SR1 */ +#define XMC4_IRQ_POSIF1_SR0 (XMC4_IRQ_FIRST+70) /* 70: POSIF Module 1, SR0 */ +#define XMC4_IRQ_POSIF1_SR1 (XMC4_IRQ_FIRST+71) /* 71: POSIF Module 1, SR1 */ +#define XMC4_IRQ_RESVD072 (XMC4_IRQ_FIRST+72) /* 72: Reserved */ +#define XMC4_IRQ_RESVD073 (XMC4_IRQ_FIRST+73) /* 73: Reserved */ +#define XMC4_IRQ_RESVD074 (XMC4_IRQ_FIRST+74) /* 74: Reserved */ +#define XMC4_IRQ_RESVD075 (XMC4_IRQ_FIRST+75) /* 75: Reserved */ +#define XMC4_IRQ_CAN_SR0 (XMC4_IRQ_FIRST+76) /* 76: MultiCAN, SR0 */ +#define XMC4_IRQ_CAN_SR1 (XMC4_IRQ_FIRST+77) /* 77: MultiCAN, SR1 */ +#define XMC4_IRQ_CAN_SR2 (XMC4_IRQ_FIRST+78) /* 78: MultiCAN, SR2 */ +#define XMC4_IRQ_CAN_SR3 (XMC4_IRQ_FIRST+79) /* 79: MultiCAN, SR3 */ +#define XMC4_IRQ_CAN_SR4 (XMC4_IRQ_FIRST+80) /* 80: MultiCAN, SR4 */ +#define XMC4_IRQ_CAN_SR5 (XMC4_IRQ_FIRST+81) /* 81: MultiCAN, SR5 */ +#define XMC4_IRQ_CAN_SR6 (XMC4_IRQ_FIRST+82) /* 82: MultiCAN, SR6 */ +#define XMC4_IRQ_CAN_SR7 (XMC4_IRQ_FIRST+83) /* 83: MultiCAN, SR7 */ +#define XMC4_IRQ_USIC0_SR0 (XMC4_IRQ_FIRST+84) /* 84: USIC0 Channel, SR0 */ +#define XMC4_IRQ_USIC0_SR1 (XMC4_IRQ_FIRST+85) /* 85: USIC0 Channel, SR1 */ +#define XMC4_IRQ_USIC0_SR2 (XMC4_IRQ_FIRST+86) /* 86: USIC0 Channel, SR2 */ +#define XMC4_IRQ_USIC0_SR3 (XMC4_IRQ_FIRST+87) /* 87: USIC0 Channel, SR3 */ +#define XMC4_IRQ_USIC0_SR4 (XMC4_IRQ_FIRST+88) /* 88: USIC0 Channel, SR4 */ +#define XMC4_IRQ_USIC0_SR5 (XMC4_IRQ_FIRST+89) /* 89: USIC0 Channel, SR5 */ +#define XMC4_IRQ_USIC1_SR0 (XMC4_IRQ_FIRST+90) /* 90: USIC1 Channel, SR0 */ +#define XMC4_IRQ_USIC1_SR1 (XMC4_IRQ_FIRST+91) /* 91: USIC1 Channel, SR1 */ +#define XMC4_IRQ_USIC1_SR2 (XMC4_IRQ_FIRST+92) /* 92: USIC1 Channel, SR2 */ +#define XMC4_IRQ_USIC1_SR3 (XMC4_IRQ_FIRST+93) /* 93: USIC1 Channel, SR3 */ +#define XMC4_IRQ_USIC1_SR4 (XMC4_IRQ_FIRST+94) /* 94: USIC1 Channel, SR4 */ +#define XMC4_IRQ_USIC1_SR5 (XMC4_IRQ_FIRST+95) /* 95: USIC1 Channel, SR5 */ +#define XMC4_IRQ_USIC2_SR0 (XMC4_IRQ_FIRST+96) /* 96: USIC1 Channel, SR0 */ +#define XMC4_IRQ_USIC2_SR1 (XMC4_IRQ_FIRST+97) /* 97: USIC1 Channel, SR1 */ +#define XMC4_IRQ_USIC2_SR2 (XMC4_IRQ_FIRST+98) /* 98: USIC1 Channel, SR2 */ +#define XMC4_IRQ_USIC2_SR3 (XMC4_IRQ_FIRST+99) /* 99: USIC1 Channel, SR3 */ +#define XMC4_IRQ_USIC2_SR4 (XMC4_IRQ_FIRST+100) /* 100: USIC1 Channel, SR4 */ +#define XMC4_IRQ_USIC2_SR5 (XMC4_IRQ_FIRST+101) /* 101: USIC1 Channel, SR5 */ +#define XMC4_IRQ_LEDTS0_SR0 (XMC4_IRQ_FIRST+102) /* 102: LEDTS0, SR0 */ +#define XMC4_IRQ_RESVD103 (XMC4_IRQ_FIRST+103) /* 103: Reserved */ +#define XMC4_IRQ_FCR_SR0 (XMC4_IRQ_FIRST+104) /* 102: FCE, SR0 */ +#define XMC4_IRQ_GPCMA0_SR0 (XMC4_IRQ_FIRST+105) /* 105: GPDMA0, SR0 */ +#define XMC4_IRQ_SDMMC_SR0 (XMC4_IRQ_FIRST+106) /* 106: SDMMC, SR0 */ +#define XMC4_IRQ_USB0_SR0 (XMC4_IRQ_FIRST+107) /* 107: USB, SR0 */ +#define XMC4_IRQ_ETH0_SR0 (XMC4_IRQ_FIRST+108) /* 108: Ethernet, module 0, SR0 */ +#define XMC4_IRQ_RESVD109 (XMC4_IRQ_FIRST+109) /* 109: Reserved */ +#define XMC4_IRQ_GPCMA1_SR0 (XMC4_IRQ_FIRST+110) /* 110: GPDMA1, SR0 */ +#define XMC4_IRQ_RESVD111 (XMC4_IRQ_FIRST+111) /* 111: Reserved */ -#define NR_INTERRUPTS 112 /* 112 Non core IRQs*/ -#define NR_VECTORS (XM4_IRQ_FIRST+NR_INTERRUPTS) /* 118 vectors */ +#define NR_INTERRUPTS 112 /* 112 Non core IRQs*/ +#define NR_VECTORS (XMC4_IRQ_FIRST+NR_INTERRUPTS) /* 118 vectors */ /* GPIO IRQ interrupts -- To be provided */ -#define NR_IRQS NR_VECTORS +#define NR_IRQS NR_VECTORS /***************************************************************************** * Public Types @@ -222,4 +222,4 @@ extern "C" #endif #endif -#endif /* xmc4__ARCH_ARM_INCLUDE_XM4_XM4500_IRQ_H */ +#endif /* xmc4__ARCH_ARM_INCLUDE_XMC4_XM4500_IRQ_H */ diff --git a/arch/arm/src/xmc4/chip/xmc4_scu.h b/arch/arm/src/xmc4/chip/xmc4_scu.h index e08a64a48c0..7e706f501bd 100644 --- a/arch/arm/src/xmc4/chip/xmc4_scu.h +++ b/arch/arm/src/xmc4/chip/xmc4_scu.h @@ -185,9 +185,9 @@ /* Oscillator Control SCU Registers */ -#define XMC4_OCU_OSCHPSTAT_OFFSET 0x0000 /* OSC_HP Status Register */ -#define XMC4_OCU_OSCHPCTRL_OFFSET 0x0004 /* OSC_HP Control Register */ -#define XMC4_OCU_CLKCALCONST_OFFSET 0x000c /* Clock Calibration Constant Register */ +#define XMC4_SCU_OSCHPSTAT_OFFSET 0x0000 /* OSC_HP Status Register */ +#define XMC4_SCU_OSCHPCTRL_OFFSET 0x0004 /* OSC_HP Control Register */ +#define XMC4_SCU_CLKCALCONST_OFFSET 0x000c /* Clock Calibration Constant Register */ /* PLL Control SCU Registers */ @@ -623,8 +623,8 @@ /* System Clock Control */ #define SCU_SYSCLKCR_SYSDIV_SHIFT (0) /* Bits 0-7: System Clock Division Value */ -#define SCU_SYSCLKCR_SYSDIV_MASK (0xff << SCU_CLK_SYSCLKCR_SYSDIV_SHIFT) -# define SCU_SYSCLKCR_SYSDIV(n) ((uint32_t)((n)-1) << SCU_CLK_SYSCLKCR_SYSDIV_SHIFT) +#define SCU_SYSCLKCR_SYSDIV_MASK (0xff << SCU_SYSCLKCR_SYSDIV_SHIFT) +# define SCU_SYSCLKCR_SYSDIV(n) ((uint32_t)((n)-1) << SCU_SYSCLKCR_SYSDIV_SHIFT) #define SCU_SYSCLKCR_SYSSEL (1 << 16) /* Bit 16: System Clock Selection Value */ # define SCU_SYSCLKCR_SYSSEL_OFI (0) /* 0=OFI clock */ @@ -640,8 +640,8 @@ /* USB Clock Control */ #define SCU_USBCLKCR_USBDIV_SHIFT (0) /* Bits 0-2: USB Clock Divider Value */ -#define SCU_USBCLKCR_USBDIV_MASK (7 << SCU_CLK_USBCLKCR_USBDIV_SHIFT) -# define SCU_SYSCLKCR_USBDIV(n) ((uint32_t)((n)-1) << SCU_CLK_USBCLKCR_USBDIV_SHIFT) +#define SCU_USBCLKCR_USBDIV_MASK (7 << SCU_USBCLKCR_USBDIV_SHIFT) +# define SCU_SYSCLKCR_USBDIV(n) ((uint32_t)((n)-1) << SCU_USBCLKCR_USBDIV_SHIFT) #define SCU_USBCLKCR_USBSEL (1 << 16) /* Bit 16: USB Clock Selection Value */ # define SCU_USBCLKCR_USBSEL_USBPLL (0) /* 0=USB PLL Clock */ # define SCU_USBCLKCR_USBSEL_PLL (1 << 16) /* 1= PLL Clock */ diff --git a/arch/arm/src/xmc4/xmc4_clockconfig.c b/arch/arm/src/xmc4/xmc4_clockconfig.c index 6667ceca861..26608a85b84 100644 --- a/arch/arm/src/xmc4/xmc4_clockconfig.c +++ b/arch/arm/src/xmc4/xmc4_clockconfig.c @@ -57,6 +57,7 @@ #include "up_arch.h" #include "chip/xmc4_scu.h" +#include "xmc4_clockconfig.h" #include @@ -83,7 +84,7 @@ #define SCU_PLLSTAT_OSC_USABLE \ (SCU_PLLSTAT_PLLHV | SCU_PLLSTAT_PLLLV | SCU_PLLSTAT_PLLSP) -#ifndef BOARD_PLL_CLOCKSRC_XTAL +#ifdef BOARD_PLL_CLOCKSRC_XTAL # define VCO ((BOARD_XTAL_FREQUENCY / BOARD_PLL_PDIV) * BOARD_PLL_NDIV) #else /* BOARD_PLL_CLOCKSRC_XTAL */ @@ -171,7 +172,7 @@ void xmc4_clock_configure(void) regval = getreg32(XMC4_SCU_PLLCON0); regval |= SCU_PLLCON0_FOTR; - putreg(regval, XMC4_SCU_PLLCON0); + putreg32(regval, XMC4_SCU_PLLCON0); #else /* Automatic calibration uses the fSTDBY */ @@ -195,10 +196,9 @@ void xmc4_clock_configure(void) /* Remove the reset only if HIB domain were in a state of reset */ regval = getreg32(XMC4_SCU_RSTSTAT); - if ((regval & SCU_RSTSTAT_HIBRS) ! = 0) + if ((regval & SCU_RSTSTAT_HIBRS) != 0) { - regval = getreg32(XMC4_SCU_RSTSTAT); - SCU_RESET->RSTCLR |= SCU_RESET_RSTCLR_HIBRS_Msk; + regval = putreg32(SCU_RSTCLR_HIBRS, XMC4_SCU_RSTCLR); delay(DELAY_CNT_150US_50MHZ); } @@ -271,19 +271,19 @@ void xmc4_clock_configure(void) regval = getreg32(XMC4_SCU_PLLCON0); regval |= SCU_PLLCON0_AOTREN; - putreg(regval, XMC4_SCU_PLLCON0); + putreg32(regval, XMC4_SCU_PLLCON0); #endif /* BOARD_FOFI_CALIBRATION */ delay(DELAY_CNT_50US_50MHZ); -#if BOARD_ENABLE_PLL +#ifdef BOARD_ENABLE_PLL /* Enable PLL */ regval = getreg32(XMC4_SCU_PLLCON0); regval &= ~(SCU_PLLCON0_VCOPWD | SCU_PLLCON0_PLLPWD); - putreg(regval, XMC4_SCU_PLLCON0); + putreg32(regval, XMC4_SCU_PLLCON0); #ifdef BOARD_PLL_CLOCKSRC_XTAL /* Enable OSC_HP */ @@ -292,7 +292,7 @@ void xmc4_clock_configure(void) { regval = getreg32(XMC4_SCU_OSCHPCTRL); regval &= ~(SCU_OSCHPCTRL_MODE_MASK | SCU_OSCHPCTRL_OSCVAL_MASK); - regval |= ((OSCHP_GetFrequency() / FOSCREF) - 1) << SCU_OSCHPCTRL_OSCVAL_SHIFT; + regval |= ((BOARD_XTAL_FREQUENCY / FOSCREF) - 1) << SCU_OSCHPCTRL_OSCVAL_SHIFT; putreg32(regval, XMC4_SCU_OSCHPCTRL); /* Select OSC_HP clock as PLL input */ @@ -305,7 +305,7 @@ void xmc4_clock_configure(void) regval = getreg32(XMC4_SCU_PLLCON0); regval &= ~SCU_PLLCON0_OSCRES; - putreg(regval, XMC4_SCU_PLLCON0); + putreg32(regval, XMC4_SCU_PLLCON0); /* Wait till OSC_HP output frequency is usable */ @@ -330,36 +330,36 @@ void xmc4_clock_configure(void) regval = getreg32(XMC4_SCU_PLLCON0); regval |= SCU_PLLCON0_VCOBYP; - putreg(regval, XMC4_SCU_PLLCON0); + putreg32(regval, XMC4_SCU_PLLCON0); /* Disconnect Oscillator from PLL */ regval |= SCU_PLLCON0_FINDIS; - putreg(regval, XMC4_SCU_PLLCON0); + putreg32(regval, XMC4_SCU_PLLCON0); /* Setup divider settings for main PLL */ regval = (SCU_PLLCON1_NDIV(BOARD_PLL_NDIV) | SCU_PLLCON1_K2DIV(PLL_K2DIV_24MHZ) | - SCU_PLLCON1_PDIV(BOARD_PLL_PDIV); + SCU_PLLCON1_PDIV(BOARD_PLL_PDIV)); putreg32(regval, XMC4_SCU_PLLCON1); /* Set OSCDISCDIS */ regval = getreg32(XMC4_SCU_PLLCON0); regval |= SCU_PLLCON0_OSCDISCDIS; - putreg(regval, XMC4_SCU_PLLCON0); + putreg32(regval, XMC4_SCU_PLLCON0); /* Connect Oscillator to PLL */ regval = getreg32(XMC4_SCU_PLLCON0); regval &= ~SCU_PLLCON0_FINDIS; - putreg(regval, XMC4_SCU_PLLCON0); + putreg32(regval, XMC4_SCU_PLLCON0); /* Restart PLL Lock detection */ regval |= SCU_PLLCON0_RESLD; - putreg(regval, XMC4_SCU_PLLCON0); + putreg32(regval, XMC4_SCU_PLLCON0); /* wait for PLL Lock at 24MHz*/ @@ -371,7 +371,7 @@ void xmc4_clock_configure(void) regval = getreg32(XMC4_SCU_PLLCON0); regval &= ~SCU_PLLCON0_VCOBYP; - putreg(regval, XMC4_SCU_PLLCON0); + putreg32(regval, XMC4_SCU_PLLCON0); /* Wait for normal mode */ @@ -393,7 +393,7 @@ void xmc4_clock_configure(void) putreg32(WDTCLKCR_VALUE, XMC4_SCU_WDTCLKCR); putreg32(EBUCLKCR_VALUE, XMC4_SCU_EBUCLKCR); putreg32(USBCLKCR_VALUE | USB_DIV, XMC4_SCU_USBCLKCR); - putreg32(EXTCLKCR_VALUE, EXTCLKCR); + putreg32(EXTCLKCR_VALUE, XMC4_SCU_EXTCLKCR); #if BOARD_ENABLE_PLL /* PLL frequency stepping...*/ @@ -401,7 +401,7 @@ void xmc4_clock_configure(void) regval = getreg32(XMC4_SCU_PLLCON0); regval &= ~SCU_PLLCON0_OSCDISCDIS; - putreg(regval, XMC4_SCU_PLLCON0); + putreg32(regval, XMC4_SCU_PLLCON0); regval = (SCU_PLLCON1_NDIV(BOARD_PLL_NDIV) | SCU_PLLCON1_K2DIV(PLL_K2DIV_48MHZ) | @@ -440,7 +440,7 @@ void xmc4_clock_configure(void) #endif /* BOARD_ENABLE_PLL */ -#if BOARD_ENABLE_USBPLL +#ifdef BOARD_ENABLE_USBPLL /* Enable USB PLL first */ regval = getreg32(XMC4_SCU_USBPLLCON); @@ -461,19 +461,19 @@ void xmc4_clock_configure(void) regval = getreg32(XMC4_SCU_PLLCON0); regval &= ~(SCU_PLLCON0_VCOPWD | SCU_PLLCON0_PLLPWD); - putreg(regval, XMC4_SCU_PLLCON0); + putreg32(regval, XMC4_SCU_PLLCON0); } regval = getreg32(XMC4_SCU_OSCHPCTRL); regval &= ~(SCU_OSCHPCTRL_MODE_MASK | SCU_OSCHPCTRL_OSCVAL_MASK); - regval |= ((OSCHP_GetFrequency() / FOSCREF) - 1) << SCU_OSCHPCTRL_OSCVAL_SHIFT; + regval |= ((BOARD_XTAL_FREQUENCY / FOSCREF) - 1) << SCU_OSCHPCTRL_OSCVAL_SHIFT; putreg32(regval, XMC4_SCU_OSCHPCTRL); /* Restart OSC Watchdog */ regval = getreg32(XMC4_SCU_PLLCON0); regval &= ~SCU_PLLCON0_OSCRES; - putreg(regval, XMC4_SCU_PLLCON0); + putreg32(regval, XMC4_SCU_PLLCON0); /* Wait till OSC_HP output frequency is usable */ @@ -527,7 +527,7 @@ void xmc4_clock_configure(void) /* Enable selected clocks */ - putreg32(CLKSET_VALUE, XMC4_SCU_CLKSET) + putreg32(CLKSET_VALUE, XMC4_SCU_CLKSET); } /**************************************************************************** @@ -605,7 +605,7 @@ uint32_t xmc4_get_coreclock(void) /* Check if the fSYS clock is divided by two to produce fCPU clock. */ - regval = getreg32(CPUCLKCR); + regval = getreg32(XMC4_SCU_CPUCLKCR); if ((regval & SCU_CPUCLKCR_CPUDIV) != 0) { temp = temp >> 1; diff --git a/arch/arm/src/xmc4/xmc4_irq.c b/arch/arm/src/xmc4/xmc4_irq.c index 17725b8c608..c31482b6385 100644 --- a/arch/arm/src/xmc4/xmc4_irq.c +++ b/arch/arm/src/xmc4/xmc4_irq.c @@ -45,6 +45,7 @@ #include #include #include +#include #include "nvic.h" #include "ram_vectors.h" diff --git a/configs/xmc4500-relax/include/board.h b/configs/xmc4500-relax/include/board.h index f3616a21e2c..dbc2440902d 100644 --- a/configs/xmc4500-relax/include/board.h +++ b/configs/xmc4500-relax/include/board.h @@ -130,6 +130,68 @@ #define BOARD_FLASH_WS 5 +/* LED definitions ******************************************************************/ +/* The XMC4500 Relax Lite v1 board has two LEDs: + * + * LED1 P1.1 High output illuminates + * LED2 P1.0 High output illuminates + * + * If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in any + * way. The following definitions are used to access individual LEDs. + */ + +/* LED index values for use with board_userled() */ + +#define BOARD_LED0 0 +#define BOARD_LED1 1 +#define BOARD_NLEDS 2 + +/* LED bits for use with board_userled_all() */ + +#define BOARD_LED0_BIT (1 << BOARD_LED0) +#define BOARD_LED1_BIT (1 << BOARD_LED1) + +/* These LEDs are not used by the board port unless CONFIG_ARCH_LEDS is + * defined. In that case, the usage by the board port is defined in + * include/board.h and src/sam_autoleds.c. The LEDs are used to encode + * OS-related events as follows: + * + * SYMBOL Meaning LED state + * LED2 LED1 + * --------------------- -------------------------- ------ ------ */ + +#define LED_STARTED 0 /* NuttX has been started OFF OFF */ +#define LED_HEAPALLOCATE 0 /* Heap has been allocated OFF OFF */ +#define LED_IRQSENABLED 0 /* Interrupts enabled OFF OFF */ +#define LED_STACKCREATED 1 /* Idle stack created ON OFF */ +#define LED_INIRQ 2 /* In an interrupt No change */ +#define LED_SIGNAL 2 /* In a signal handler No change */ +#define LED_ASSERTION 2 /* An assertion failed No change */ +#define LED_PANIC 3 /* The system has crashed N/C Blinking */ +#undef LED_IDLE /* MCU is is sleep mode Not used */ + +/* Thus if LED0 is statically on, NuttX has successfully booted and is, + * apparently, running normally. If LED1 is flashing at approximately + * 2Hz, then a fatal error has been detected and the system has halted. + * + * NOTE: That LED0 is not used after completion of booting and may + * be used by other board-specific logic. + */ + +/* Button definitions ***************************************************************/ +/* The XMC4500 Relax Lite v1 board has two buttons: + * + * BUTTON1 P1.14 Low input sensed when button pressed + * BUTTON2 P1.15 Low input sensed when button pressed + */ + +#define BUTTON_0 0 +#define BUTTON_1 1 +#define NUM_BUTTONS 2 + +#define BUTTON_0_BIT (1 << BUTTON_0) +#define BUTTON_1_BIT (1 << BUTTON_1) + /************************************************************************************ * Public Data ************************************************************************************/ diff --git a/configs/xmc4500-relax/src/xmc4500-relax.h b/configs/xmc4500-relax/src/xmc4500-relax.h index 6a004c82448..7934462b70e 100644 --- a/configs/xmc4500-relax/src/xmc4500-relax.h +++ b/configs/xmc4500-relax/src/xmc4500-relax.h @@ -46,9 +46,21 @@ * Pre-processor Definitions ****************************************************************************/ -/* LEDs */ +/* LEDs + * + * The XMC4500 Relax Lite v1 board has two LEDs: + * + * LED1 P1.1 High output illuminates + * LED2 P1.0 High output illuminates + */ -/* BUTTONS */ +/* BUTTONS + * + * The XMC4500 Relax Lite v1 board has two buttons: + * + * BUTTON1 P1.14 Low input sensed when button pressed + * BUTTON2 P1.15 Low input sensed when button pressed + */ /**************************************************************************** * Public Types From e67baffc15109ec38969113524961417a772f830 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 16 Mar 2017 13:04:01 -0600 Subject: [PATCH 11/21] XMC4xxx: Add partial USIC header file. --- arch/arm/src/xmc4/chip/xmc4_memorymap.h | 9 +- arch/arm/src/xmc4/chip/xmc4_usic.h | 475 ++++++++++++++++++++++++ 2 files changed, 481 insertions(+), 3 deletions(-) create mode 100644 arch/arm/src/xmc4/chip/xmc4_usic.h diff --git a/arch/arm/src/xmc4/chip/xmc4_memorymap.h b/arch/arm/src/xmc4/chip/xmc4_memorymap.h index 19dd637ab59..c6d15f234f5 100644 --- a/arch/arm/src/xmc4/chip/xmc4_memorymap.h +++ b/arch/arm/src/xmc4/chip/xmc4_memorymap.h @@ -117,9 +117,10 @@ #define XMC4_CCU81_CC83_BASE 0x40024400 #define XMC4_POSIF0_BASE 0x40028000 #define XMC4_POSIF1_BASE 0x4002c000 -#define XMC4_USIC0_BASE 0x40030008 +#define XMC4_USIC0_BASE 0x40030000 #define XMC4_USIC0_CH0_BASE 0x40030000 #define XMC4_USIC0_CH1_BASE 0x40030200 +#define XMC4_USIC0_RAM_BASE 0x40030400 #define XMC4_ERU1_BASE 0x40044000 #define XMC4_PBA1_BASE 0x48000000 @@ -139,12 +140,14 @@ #define XMC4_CAN_MO_BASE 0x48015000 #define XMC4_DAC_BASE 0x48018000 #define XMC4_SDMMC_BASE 0x4801c000 +#define XMC4_USIC1_BASE 0x48020000 #define XMC4_USIC1_CH0_BASE 0x48020000 -#define XMC4_USIC1_BASE 0x48020008 #define XMC4_USIC1_CH1_BASE 0x48020200 +#define XMC4_USIC1_RAM_BASE 0x48020400 +#define XMC4_USIC2_BASE 0x48024000 #define XMC4_USIC2_CH0_BASE 0x48024000 -#define XMC4_USIC2_BASE 0x48024008 #define XMC4_USIC2_CH1_BASE 0x48024200 +#define XMC4_USIC2_CH1_BASE 0x48024400 #define XMC4_PORT0_BASE 0x48028000 #define XMC4_PORT1_BASE 0x48028100 #define XMC4_PORT2_BASE 0x48028200 diff --git a/arch/arm/src/xmc4/chip/xmc4_usic.h b/arch/arm/src/xmc4/chip/xmc4_usic.h new file mode 100644 index 00000000000..089a14811fc --- /dev/null +++ b/arch/arm/src/xmc4/chip/xmc4_usic.h @@ -0,0 +1,475 @@ +/************************************************************************************ + * arch/arm/src/xmc4/chip/xmc4_usic.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Reference: XMC4500 Reference Manual V1.5 2014-07 Microcontrollers. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * May include some logic from sample code provided by Infineon: + * + * Copyright (C) 2011-2015 Infineon Technologies AG. All rights reserved. + * + * Infineon Technologies AG (Infineon) is supplying this software for use with + * Infineon's microcontrollers. This file can be freely distributed within + * development tools that are supporting such microcontrollers. + * + * THIS SOFTWARE IS PROVIDED AS IS. NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, + * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_XMC4_CHIP_XMC4_USIC_H +#define __ARCH_ARM_SRC_XMC4_CHIP_XMC4_USIC_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Register Offsets *****************************************************************/ + +/* PMU Registers -- See ID register */ +/* Prefetch Registers -- See PCON register */ + +/* Kernal Registers */ + +#define XMC4_USIC_ID_OFFSET 0x0008 /* Kernel State Configuration Register */ + +/* USIC Channel Registers */ + +#define XMC4_USIC_CCFG_OFFSET 0x0004 /* Channel Configuration Register */ +#define XMC4_USIC_KSCFG_OFFSET 0x000c /* Kernel State Configuration Register */ +#define XMC4_USIC_FDR_OFFSET 0x0010 /* Fractional Divider Register */ +#define XMC4_USIC_BRG_OFFSET 0x0014 /* Baud Rate Generator Register */ +#define XMC4_USIC_INPR_OFFSET 0x0018 /* Interrupt Node Pointer Register */ +#define XMC4_USIC_DX0CR_OFFSET 0x001c /* Input Control Register 0 */ +#define XMC4_USIC_DX1CR_OFFSET 0x0020 /* Input Control Register 1 */ +#define XMC4_USIC_DX2CR_OFFSET 0x0024 /* Input Control Register 2 */ +#define XMC4_USIC_DX3CR_OFFSET 0x0028 /* Input Control Register 3 */ +#define XMC4_USIC_DX4CR_OFFSET 0x002c /* Input Control Register 4 */ +#define XMC4_USIC_DX5CR_OFFSET 0x0030 /* Input Control Register 5 */ +#define XMC4_USIC_SCTR_OFFSET 0x0034 /* Shift Control Register */ +#define XMC4_USIC_TCSR_OFFSET 0x0038 /* Transmit Control/Status Register */ +#define XMC4_USIC_PCR_OFFSET 0x003c /* Protocol Control Register */ +#define XMC4_USIC_CCR_OFFSET 0x0040 /* Channel Control Register */ +#define XMC4_USIC_CMTR_OFFSET 0x0044 /* Capture Mode Timer Register */ +#define XMC4_USIC_PSR_OFFSET 0x0048 /* Protocol Status Register */ +#define XMC4_USIC_PSCR_OFFSET 0x004c /* Protocol Status Clear Register */ +#define XMC4_USIC_RBUFSR_OFFSET 0x0050 /* Receiver Buffer Status Register */ +#define XMC4_USIC_RBUF_OFFSET 0x0054 /* Receiver Buffer Register */ +#define XMC4_USIC_RBUFD_OFFSET 0x0058 /* Receiver Buffer Register for Debugger */ +#define XMC4_USIC_RBUF0_OFFSET 0x005c /* Receiver Buffer Register 0 */ +#define XMC4_USIC_RBUF1_OFFSET 0x0060 /* Receiver Buffer Register 1 */ +#define XMC4_USIC_RBUF01SR_OFFSET 0x0064 /* Receiver Buffer 01 Status Register */ +#define XMC4_USIC_FMR_OFFSET 0x0068 /* Flag Modification Register */ +#define XMC4_USIC_TBUF_OFFSET 0x0080 /* Transmit Buffer (32 x 4-bytes) */ + +/* USIC FIFO Registers */ + +#define XMC4_USIC_BYP_OFFSET 0x0100 /* Bypass Data Register */ +#define XMC4_USIC_BYPCR_OFFSET 0x0104 /* Bypass Control Register */ +#define XMC4_USIC_TBCTR_OFFSET 0x0108 /* Transmitter Buffer Control Register */ +#define XMC4_USIC_RBCTR_OFFSET 0x010c /* Receiver Buffer Control Register */ +#define XMC4_USIC_TRBPTR_OFFSET 0x0110 /* Transmit/Receive Buffer Pointer Register */ +#define XMC4_USIC_TRBSR_OFFSET 0x0114 /* Transmit/Receive Buffer Status Register */ +#define XMC4_USIC_TRBSCR_OFFSET 0x0118 /* Transmit/Receive Buffer Status Clear Register */ +#define XMC4_USIC_OUTR_OFFSET 0x011c /* Receiver Buffer Output Register */ +#define XMC4_USIC_OUTDR_OFFSET 0x0120 /* Receiver Buffer Output Register L for Debugger */ +#define XMC4_USIC_IN_OFFSET 0x0180 /* Transmit FIFO Buffer (32 x 4-bytes) */ + +/* Register Addresses ****************************************************************/ + +/* USIC0 Registers */ +/* Kernal Registers */ + +#define XMC4_USIC0_ID (XMC4_USIC0_BASE+XMC4_USIC_ID_OFFSET) + +/* USIC0 Channel 0 Registers */ + +#define XMC4_USIC00_CCFG (XMC4_USIC0_CH0_BASE+XMC4_USIC_CCFG_OFFSET) +#define XMC4_USIC00_KSCFG (XMC4_USIC0_CH0_BASE+XMC4_USIC_KSCFG_OFFSET) +#define XMC4_USIC00_FDR (XMC4_USIC0_CH0_BASE+XMC4_USIC_FDR_OFFSET) +#define XMC4_USIC00_BRG (XMC4_USIC0_CH0_BASE+XMC4_USIC_BRG_OFFSET) +#define XMC4_USIC00_INPR (XMC4_USIC0_CH0_BASE+XMC4_USIC_INPR_OFFSET) +#define XMC4_USIC00_DX0CR (XMC4_USIC0_CH0_BASE+XMC4_USIC_DX0CR_OFFSET) +#define XMC4_USIC00_DX1CR (XMC4_USIC0_CH0_BASE+XMC4_USIC_DX1CR_OFFSET) +#define XMC4_USIC00_DX2CR (XMC4_USIC0_CH0_BASE+XMC4_USIC_DX2CR_OFFSET) +#define XMC4_USIC00_DX3CR (XMC4_USIC0_CH0_BASE+XMC4_USIC_DX3CR_OFFSET) +#define XMC4_USIC00_DX4CR (XMC4_USIC0_CH0_BASE+XMC4_USIC_DX4CR_OFFSET) +#define XMC4_USIC00_DX5CR (XMC4_USIC0_CH0_BASE+XMC4_USIC_DX5CR_OFFSET) +#define XMC4_USIC00_SCTR (XMC4_USIC0_CH0_BASE+XMC4_USIC_SCTR_OFFSET) +#define XMC4_USIC00_TCSR (XMC4_USIC0_CH0_BASE+XMC4_USIC_TCSR_OFFSET) +#define XMC4_USIC00_PCR (XMC4_USIC0_CH0_BASE+XMC4_USIC_PCR_OFFSET) +#define XMC4_USIC00_CCR (XMC4_USIC0_CH0_BASE+XMC4_USIC_CCR_OFFSET) +#define XMC4_USIC00_CMTR (XMC4_USIC0_CH0_BASE+XMC4_USIC_CMTR_OFFSET) +#define XMC4_USIC00_PSR (XMC4_USIC0_CH0_BASE+XMC4_USIC_PSR_OFFSET) +#define XMC4_USIC00_PSCR (XMC4_USIC0_CH0_BASE+XMC4_USIC_PSCR_OFFSET) +#define XMC4_USIC00_RBUFSR (XMC4_USIC0_CH0_BASE+XMC4_USIC_RBUFSR_OFFSET) +#define XMC4_USIC00_RBUF (XMC4_USIC0_CH0_BASE+XMC4_USIC_RBUF_OFFSET) +#define XMC4_USIC00_RBUFD (XMC4_USIC0_CH0_BASE+XMC4_USIC_RBUFD_OFFSET) +#define XMC4_USIC00_RBUF0 (XMC4_USIC0_CH0_BASE+XMC4_USIC_RBUF0_OFFSET) +#define XMC4_USIC00_RBUF1 (XMC4_USIC0_CH0_BASE+XMC4_USIC_RBUF1_OFFSET) +#define XMC4_USIC00_RBUF01SR (XMC4_USIC0_CH0_BASE+XMC4_USIC_RBUF01SR_OFFSET) +#define XMC4_USIC00_FMR (XMC4_USIC0_CH0_BASE+XMC4_USIC_FMR_OFFSET) +#define XMC4_USIC00_TBUF (XMC4_USIC0_CH0_BASE+XMC4_USIC_TBUF_OFFSET) + +/* USIC0 Channel 0 FIFO Registers */ + +#define XMC4_USIC00_BYP (XMC4_USIC0_CH0_BASE+XMC4_USIC_BYP_OFFSET) +#define XMC4_USIC00_BYPCR (XMC4_USIC0_CH0_BASE+XMC4_USIC_BYPCR_OFFSET) +#define XMC4_USIC00_TBCTR (XMC4_USIC0_CH0_BASE+XMC4_USIC_TBCTR_OFFSET) +#define XMC4_USIC00_RBCTR (XMC4_USIC0_CH0_BASE+XMC4_USIC_RBCTR_OFFSET) +#define XMC4_USIC00_TRBPTR (XMC4_USIC0_CH0_BASE+XMC4_USIC_TRBPTR_OFFSET) +#define XMC4_USIC00_TRBSR (XMC4_USIC0_CH0_BASE+XMC4_USIC_TRBSR_OFFSET) +#define XMC4_USIC00_TRBSCR (XMC4_USIC0_CH0_BASE+XMC4_USIC_TRBSCR_OFFSET) +#define XMC4_USIC00_OUTR (XMC4_USIC0_CH0_BASE+XMC4_USIC_OUTR_OFFSET) +#define XMC4_USIC00_OUTDR (XMC4_USIC0_CH0_BASE+XMC4_USIC_OUTDR_OFFSET) +#define XMC4_USIC00_IN (XMC4_USIC0_CH0_BASE+XMC4_USIC_IN_OFFSET) + +/* USIC0 Channel 1 Registers */ + +#define XMC4_USIC01_CCFG (XMC4_USIC0_CH1_BASE+XMC4_USIC_CCFG_OFFSET) +#define XMC4_USIC01_KSCFG (XMC4_USIC0_CH1_BASE+XMC4_USIC_KSCFG_OFFSET) +#define XMC4_USIC01_FDR (XMC4_USIC0_CH1_BASE+XMC4_USIC_FDR_OFFSET) +#define XMC4_USIC01_BRG (XMC4_USIC0_CH1_BASE+XMC4_USIC_BRG_OFFSET) +#define XMC4_USIC01_INPR (XMC4_USIC0_CH1_BASE+XMC4_USIC_INPR_OFFSET) +#define XMC4_USIC01_DX0CR (XMC4_USIC0_CH1_BASE+XMC4_USIC_DX0CR_OFFSET) +#define XMC4_USIC01_DX1CR (XMC4_USIC0_CH1_BASE+XMC4_USIC_DX1CR_OFFSET) +#define XMC4_USIC01_DX2CR (XMC4_USIC0_CH1_BASE+XMC4_USIC_DX2CR_OFFSET) +#define XMC4_USIC01_DX3CR (XMC4_USIC0_CH1_BASE+XMC4_USIC_DX3CR_OFFSET) +#define XMC4_USIC01_DX4CR (XMC4_USIC0_CH1_BASE+XMC4_USIC_DX4CR_OFFSET) +#define XMC4_USIC01_DX5CR (XMC4_USIC0_CH1_BASE+XMC4_USIC_DX5CR_OFFSET) +#define XMC4_USIC01_SCTR (XMC4_USIC0_CH1_BASE+XMC4_USIC_SCTR_OFFSET) +#define XMC4_USIC01_TCSR (XMC4_USIC0_CH1_BASE+XMC4_USIC_TCSR_OFFSET) +#define XMC4_USIC01_PCR (XMC4_USIC0_CH1_BASE+XMC4_USIC_PCR_OFFSET) +#define XMC4_USIC01_CCR (XMC4_USIC0_CH1_BASE+XMC4_USIC_CCR_OFFSET) +#define XMC4_USIC01_CMTR (XMC4_USIC0_CH1_BASE+XMC4_USIC_CMTR_OFFSET) +#define XMC4_USIC01_PSR (XMC4_USIC0_CH1_BASE+XMC4_USIC_PSR_OFFSET) +#define XMC4_USIC01_PSCR (XMC4_USIC0_CH1_BASE+XMC4_USIC_PSCR_OFFSET) +#define XMC4_USIC01_RBUFSR (XMC4_USIC0_CH1_BASE+XMC4_USIC_RBUFSR_OFFSET) +#define XMC4_USIC01_RBUF (XMC4_USIC0_CH1_BASE+XMC4_USIC_RBUF_OFFSET) +#define XMC4_USIC01_RBUFD (XMC4_USIC0_CH1_BASE+XMC4_USIC_RBUFD_OFFSET) +#define XMC4_USIC01_RBUF0 (XMC4_USIC0_CH1_BASE+XMC4_USIC_RBUF0_OFFSET) +#define XMC4_USIC01_RBUF1 (XMC4_USIC0_CH1_BASE+XMC4_USIC_RBUF1_OFFSET) +#define XMC4_USIC01_RBUF01SR (XMC4_USIC0_CH1_BASE+XMC4_USIC_RBUF01SR_OFFSET) +#define XMC4_USIC01_FMR (XMC4_USIC0_CH1_BASE+XMC4_USIC_FMR_OFFSET) +#define XMC4_USIC01_TBUF (XMC4_USIC0_CH1_BASE+XMC4_USIC_TBUF_OFFSET) + +/* USIC0 Channel 1 FIFO Registers */ + +#define XMC4_USIC01_BYP (XMC4_USIC0_CH1_BASE+XMC4_USIC_BYP_OFFSET) +#define XMC4_USIC01_BYPCR (XMC4_USIC0_CH1_BASE+XMC4_USIC_BYPCR_OFFSET) +#define XMC4_USIC01_TBCTR (XMC4_USIC0_CH1_BASE+XMC4_USIC_TBCTR_OFFSET) +#define XMC4_USIC01_RBCTR (XMC4_USIC0_CH1_BASE+XMC4_USIC_RBCTR_OFFSET) +#define XMC4_USIC01_TRBPTR (XMC4_USIC0_CH1_BASE+XMC4_USIC_TRBPTR_OFFSET) +#define XMC4_USIC01_TRBSR (XMC4_USIC0_CH1_BASE+XMC4_USIC_TRBSR_OFFSET) +#define XMC4_USIC01_TRBSCR (XMC4_USIC0_CH1_BASE+XMC4_USIC_TRBSCR_OFFSET) +#define XMC4_USIC01_OUTR (XMC4_USIC0_CH1_BASE+XMC4_USIC_OUTR_OFFSET) +#define XMC4_USIC01_OUTDR (XMC4_USIC0_CH1_BASE+XMC4_USIC_OUTDR_OFFSET) +#define XMC4_USIC01_IN (XMC4_USIC0_CH1_BASE+XMC4_USIC_IN_OFFSET) + +/* USIC1 Registers */ +/* Kernal Registers */ + +#define XMC4_USIC1_ID (XMC4_USIC1_BASE+XMC4_USIC_ID_OFFSET) + +/* USIC1 Channel 0 Registers */ + +#define XMC4_USIC10_CCFG (XMC4_USIC1_CH0_BASE+XMC4_USIC_CCFG_OFFSET) +#define XMC4_USIC10_KSCFG (XMC4_USIC1_CH0_BASE+XMC4_USIC_KSCFG_OFFSET) +#define XMC4_USIC10_FDR (XMC4_USIC1_CH0_BASE+XMC4_USIC_FDR_OFFSET) +#define XMC4_USIC10_BRG (XMC4_USIC1_CH0_BASE+XMC4_USIC_BRG_OFFSET) +#define XMC4_USIC10_INPR (XMC4_USIC1_CH0_BASE+XMC4_USIC_INPR_OFFSET) +#define XMC4_USIC10_DX0CR (XMC4_USIC1_CH0_BASE+XMC4_USIC_DX0CR_OFFSET) +#define XMC4_USIC10_DX1CR (XMC4_USIC1_CH0_BASE+XMC4_USIC_DX1CR_OFFSET) +#define XMC4_USIC10_DX2CR (XMC4_USIC1_CH0_BASE+XMC4_USIC_DX2CR_OFFSET) +#define XMC4_USIC10_DX3CR (XMC4_USIC1_CH0_BASE+XMC4_USIC_DX3CR_OFFSET) +#define XMC4_USIC10_DX4CR (XMC4_USIC1_CH0_BASE+XMC4_USIC_DX4CR_OFFSET) +#define XMC4_USIC10_DX5CR (XMC4_USIC1_CH0_BASE+XMC4_USIC_DX5CR_OFFSET) +#define XMC4_USIC10_SCTR (XMC4_USIC1_CH0_BASE+XMC4_USIC_SCTR_OFFSET) +#define XMC4_USIC10_TCSR (XMC4_USIC1_CH0_BASE+XMC4_USIC_TCSR_OFFSET) +#define XMC4_USIC10_PCR (XMC4_USIC1_CH0_BASE+XMC4_USIC_PCR_OFFSET) +#define XMC4_USIC10_CCR (XMC4_USIC1_CH0_BASE+XMC4_USIC_CCR_OFFSET) +#define XMC4_USIC10_CMTR (XMC4_USIC1_CH0_BASE+XMC4_USIC_CMTR_OFFSET) +#define XMC4_USIC10_PSR (XMC4_USIC1_CH0_BASE+XMC4_USIC_PSR_OFFSET) +#define XMC4_USIC10_PSCR (XMC4_USIC1_CH0_BASE+XMC4_USIC_PSCR_OFFSET) +#define XMC4_USIC10_RBUFSR (XMC4_USIC1_CH0_BASE+XMC4_USIC_RBUFSR_OFFSET) +#define XMC4_USIC10_RBUF (XMC4_USIC1_CH0_BASE+XMC4_USIC_RBUF_OFFSET) +#define XMC4_USIC10_RBUFD (XMC4_USIC1_CH0_BASE+XMC4_USIC_RBUFD_OFFSET) +#define XMC4_USIC10_RBUF0 (XMC4_USIC1_CH0_BASE+XMC4_USIC_RBUF0_OFFSET) +#define XMC4_USIC10_RBUF1 (XMC4_USIC1_CH0_BASE+XMC4_USIC_RBUF1_OFFSET) +#define XMC4_USIC10_RBUF01SR (XMC4_USIC1_CH0_BASE+XMC4_USIC_RBUF01SR_OFFSET) +#define XMC4_USIC10_FMR (XMC4_USIC1_CH0_BASE+XMC4_USIC_FMR_OFFSET) +#define XMC4_USIC10_TBUF (XMC4_USIC1_CH0_BASE+XMC4_USIC_TBUF_OFFSET) + +/* USIC1 Channel 0 FIFO Registers */ + +#define XMC4_USIC10_BYP (XMC4_USIC1_CH0_BASE+XMC4_USIC_BYP_OFFSET) +#define XMC4_USIC10_BYPCR (XMC4_USIC1_CH0_BASE+XMC4_USIC_BYPCR_OFFSET) +#define XMC4_USIC10_TBCTR (XMC4_USIC1_CH0_BASE+XMC4_USIC_TBCTR_OFFSET) +#define XMC4_USIC10_RBCTR (XMC4_USIC1_CH0_BASE+XMC4_USIC_RBCTR_OFFSET) +#define XMC4_USIC10_TRBPTR (XMC4_USIC1_CH0_BASE+XMC4_USIC_TRBPTR_OFFSET) +#define XMC4_USIC10_TRBSR (XMC4_USIC1_CH0_BASE+XMC4_USIC_TRBSR_OFFSET) +#define XMC4_USIC10_TRBSCR (XMC4_USIC1_CH0_BASE+XMC4_USIC_TRBSCR_OFFSET) +#define XMC4_USIC10_OUTR (XMC4_USIC1_CH0_BASE+XMC4_USIC_OUTR_OFFSET) +#define XMC4_USIC10_OUTDR (XMC4_USIC1_CH0_BASE+XMC4_USIC_OUTDR_OFFSET) +#define XMC4_USIC10_IN (XMC4_USIC1_CH0_BASE+XMC4_USIC_IN_OFFSET) + +/* USIC1 Channel 1 Registers */ + +#define XMC4_USCI11_CCFG (XMC4_USIC1_CH1_BASE+XMC4_USIC_CCFG_OFFSET) +#define XMC4_USCI11_KSCFG (XMC4_USIC1_CH1_BASE+XMC4_USIC_KSCFG_OFFSET) +#define XMC4_USCI11_FDR (XMC4_USIC1_CH1_BASE+XMC4_USIC_FDR_OFFSET) +#define XMC4_USCI11_BRG (XMC4_USIC1_CH1_BASE+XMC4_USIC_BRG_OFFSET) +#define XMC4_USCI11_INPR (XMC4_USIC1_CH1_BASE+XMC4_USIC_INPR_OFFSET) +#define XMC4_USCI11_DX0CR (XMC4_USIC1_CH1_BASE+XMC4_USIC_DX0CR_OFFSET) +#define XMC4_USCI11_DX1CR (XMC4_USIC1_CH1_BASE+XMC4_USIC_DX1CR_OFFSET) +#define XMC4_USCI11_DX2CR (XMC4_USIC1_CH1_BASE+XMC4_USIC_DX2CR_OFFSET) +#define XMC4_USCI11_DX3CR (XMC4_USIC1_CH1_BASE+XMC4_USIC_DX3CR_OFFSET) +#define XMC4_USCI11_DX4CR (XMC4_USIC1_CH1_BASE+XMC4_USIC_DX4CR_OFFSET) +#define XMC4_USCI11_DX5CR (XMC4_USIC1_CH1_BASE+XMC4_USIC_DX5CR_OFFSET) +#define XMC4_USCI11_SCTR (XMC4_USIC1_CH1_BASE+XMC4_USIC_SCTR_OFFSET) +#define XMC4_USCI11_TCSR (XMC4_USIC1_CH1_BASE+XMC4_USIC_TCSR_OFFSET) +#define XMC4_USCI11_PCR (XMC4_USIC1_CH1_BASE+XMC4_USIC_PCR_OFFSET) +#define XMC4_USCI11_CCR (XMC4_USIC1_CH1_BASE+XMC4_USIC_CCR_OFFSET) +#define XMC4_USCI11_CMTR (XMC4_USIC1_CH1_BASE+XMC4_USIC_CMTR_OFFSET) +#define XMC4_USCI11_PSR (XMC4_USIC1_CH1_BASE+XMC4_USIC_PSR_OFFSET) +#define XMC4_USCI11_PSCR (XMC4_USIC1_CH1_BASE+XMC4_USIC_PSCR_OFFSET) +#define XMC4_USCI11_RBUFSR (XMC4_USIC1_CH1_BASE+XMC4_USIC_RBUFSR_OFFSET) +#define XMC4_USCI11_RBUF (XMC4_USIC1_CH1_BASE+XMC4_USIC_RBUF_OFFSET) +#define XMC4_USCI11_RBUFD (XMC4_USIC1_CH1_BASE+XMC4_USIC_RBUFD_OFFSET) +#define XMC4_USCI11_RBUF0 (XMC4_USIC1_CH1_BASE+XMC4_USIC_RBUF0_OFFSET) +#define XMC4_USCI11_RBUF1 (XMC4_USIC1_CH1_BASE+XMC4_USIC_RBUF1_OFFSET) +#define XMC4_USCI11_RBUF01SR (XMC4_USIC1_CH1_BASE+XMC4_USIC_RBUF01SR_OFFSET) +#define XMC4_USCI11_FMR (XMC4_USIC1_CH1_BASE+XMC4_USIC_FMR_OFFSET) +#define XMC4_USCI11_TBUF (XMC4_USIC1_CH1_BASE+XMC4_USIC_TBUF_OFFSET) + +/* USIC1 Channel 1 FIFO Registers */ + +#define XMC4_USCI11_BYP (XMC4_USIC1_CH1_BASE+XMC4_USIC_BYP_OFFSET) +#define XMC4_USCI11_BYPCR (XMC4_USIC1_CH1_BASE+XMC4_USIC_BYPCR_OFFSET) +#define XMC4_USCI11_TBCTR (XMC4_USIC1_CH1_BASE+XMC4_USIC_TBCTR_OFFSET) +#define XMC4_USCI11_RBCTR (XMC4_USIC1_CH1_BASE+XMC4_USIC_RBCTR_OFFSET) +#define XMC4_USCI11_TRBPTR (XMC4_USIC1_CH1_BASE+XMC4_USIC_TRBPTR_OFFSET) +#define XMC4_USCI11_TRBSR (XMC4_USIC1_CH1_BASE+XMC4_USIC_TRBSR_OFFSET) +#define XMC4_USCI11_TRBSCR (XMC4_USIC1_CH1_BASE+XMC4_USIC_TRBSCR_OFFSET) +#define XMC4_USCI11_OUTR (XMC4_USIC1_CH1_BASE+XMC4_USIC_OUTR_OFFSET) +#define XMC4_USCI11_OUTDR (XMC4_USIC1_CH1_BASE+XMC4_USIC_OUTDR_OFFSET) +#define XMC4_USCI11_IN (XMC4_USIC1_CH1_BASE+XMC4_USIC_IN_OFFSET) + +/* USCI2 Registers */ +/* Kernal Registers */ + +#define XMC4_USCI2_ID (XMC4_USCI2_BASE+XMC4_USIC_ID_OFFSET) + +/* USCI2 Channel 0 Registers */ + +#define XMC4_USCI20_CCFG (XMC4_USCI2_CH0_BASE+XMC4_USIC_CCFG_OFFSET) +#define XMC4_USCI20_KSCFG (XMC4_USCI2_CH0_BASE+XMC4_USIC_KSCFG_OFFSET) +#define XMC4_USCI20_FDR (XMC4_USCI2_CH0_BASE+XMC4_USIC_FDR_OFFSET) +#define XMC4_USCI20_BRG (XMC4_USCI2_CH0_BASE+XMC4_USIC_BRG_OFFSET) +#define XMC4_USCI20_INPR (XMC4_USCI2_CH0_BASE+XMC4_USIC_INPR_OFFSET) +#define XMC4_USCI20_DX0CR (XMC4_USCI2_CH0_BASE+XMC4_USIC_DX0CR_OFFSET) +#define XMC4_USCI20_DX1CR (XMC4_USCI2_CH0_BASE+XMC4_USIC_DX1CR_OFFSET) +#define XMC4_USCI20_DX2CR (XMC4_USCI2_CH0_BASE+XMC4_USIC_DX2CR_OFFSET) +#define XMC4_USCI20_DX3CR (XMC4_USCI2_CH0_BASE+XMC4_USIC_DX3CR_OFFSET) +#define XMC4_USCI20_DX4CR (XMC4_USCI2_CH0_BASE+XMC4_USIC_DX4CR_OFFSET) +#define XMC4_USCI20_DX5CR (XMC4_USCI2_CH0_BASE+XMC4_USIC_DX5CR_OFFSET) +#define XMC4_USCI20_SCTR (XMC4_USCI2_CH0_BASE+XMC4_USIC_SCTR_OFFSET) +#define XMC4_USCI20_TCSR (XMC4_USCI2_CH0_BASE+XMC4_USIC_TCSR_OFFSET) +#define XMC4_USCI20_PCR (XMC4_USCI2_CH0_BASE+XMC4_USIC_PCR_OFFSET) +#define XMC4_USCI20_CCR (XMC4_USCI2_CH0_BASE+XMC4_USIC_CCR_OFFSET) +#define XMC4_USCI20_CMTR (XMC4_USCI2_CH0_BASE+XMC4_USIC_CMTR_OFFSET) +#define XMC4_USCI20_PSR (XMC4_USCI2_CH0_BASE+XMC4_USIC_PSR_OFFSET) +#define XMC4_USCI20_PSCR (XMC4_USCI2_CH0_BASE+XMC4_USIC_PSCR_OFFSET) +#define XMC4_USCI20_RBUFSR (XMC4_USCI2_CH0_BASE+XMC4_USIC_RBUFSR_OFFSET) +#define XMC4_USCI20_RBUF (XMC4_USCI2_CH0_BASE+XMC4_USIC_RBUF_OFFSET) +#define XMC4_USCI20_RBUFD (XMC4_USCI2_CH0_BASE+XMC4_USIC_RBUFD_OFFSET) +#define XMC4_USCI20_RBUF0 (XMC4_USCI2_CH0_BASE+XMC4_USIC_RBUF0_OFFSET) +#define XMC4_USCI20_RBUF1 (XMC4_USCI2_CH0_BASE+XMC4_USIC_RBUF1_OFFSET) +#define XMC4_USCI20_RBUF01SR (XMC4_USCI2_CH0_BASE+XMC4_USIC_RBUF01SR_OFFSET) +#define XMC4_USCI20_FMR (XMC4_USCI2_CH0_BASE+XMC4_USIC_FMR_OFFSET) +#define XMC4_USCI20_TBUF (XMC4_USCI2_CH0_BASE+XMC4_USIC_TBUF_OFFSET) + +/* USCI2 Channel 0 FIFO Registers */ + +#define XMC4_USCI20_BYP (XMC4_USCI2_CH0_BASE+XMC4_USIC_BYP_OFFSET) +#define XMC4_USCI20_BYPCR (XMC4_USCI2_CH0_BASE+XMC4_USIC_BYPCR_OFFSET) +#define XMC4_USCI20_TBCTR (XMC4_USCI2_CH0_BASE+XMC4_USIC_TBCTR_OFFSET) +#define XMC4_USCI20_RBCTR (XMC4_USCI2_CH0_BASE+XMC4_USIC_RBCTR_OFFSET) +#define XMC4_USCI20_TRBPTR (XMC4_USCI2_CH0_BASE+XMC4_USIC_TRBPTR_OFFSET) +#define XMC4_USCI20_TRBSR (XMC4_USCI2_CH0_BASE+XMC4_USIC_TRBSR_OFFSET) +#define XMC4_USCI20_TRBSCR (XMC4_USCI2_CH0_BASE+XMC4_USIC_TRBSCR_OFFSET) +#define XMC4_USCI20_OUTR (XMC4_USCI2_CH0_BASE+XMC4_USIC_OUTR_OFFSET) +#define XMC4_USCI20_OUTDR (XMC4_USCI2_CH0_BASE+XMC4_USIC_OUTDR_OFFSET) +#define XMC4_USCI20_IN (XMC4_USCI2_CH0_BASE+XMC4_USIC_IN_OFFSET) + +/* USCI2 Channel 1 Registers */ + +#define XMC4_USCI21_CCFG (XMC4_USCI2_CH1_BASE+XMC4_USIC_CCFG_OFFSET) +#define XMC4_USCI21_KSCFG (XMC4_USCI2_CH1_BASE+XMC4_USIC_KSCFG_OFFSET) +#define XMC4_USCI21_FDR (XMC4_USCI2_CH1_BASE+XMC4_USIC_FDR_OFFSET) +#define XMC4_USCI21_BRG (XMC4_USCI2_CH1_BASE+XMC4_USIC_BRG_OFFSET) +#define XMC4_USCI21_INPR (XMC4_USCI2_CH1_BASE+XMC4_USIC_INPR_OFFSET) +#define XMC4_USCI21_DX0CR (XMC4_USCI2_CH1_BASE+XMC4_USIC_DX0CR_OFFSET) +#define XMC4_USCI21_DX1CR (XMC4_USCI2_CH1_BASE+XMC4_USIC_DX1CR_OFFSET) +#define XMC4_USCI21_DX2CR (XMC4_USCI2_CH1_BASE+XMC4_USIC_DX2CR_OFFSET) +#define XMC4_USCI21_DX3CR (XMC4_USCI2_CH1_BASE+XMC4_USIC_DX3CR_OFFSET) +#define XMC4_USCI21_DX4CR (XMC4_USCI2_CH1_BASE+XMC4_USIC_DX4CR_OFFSET) +#define XMC4_USCI21_DX5CR (XMC4_USCI2_CH1_BASE+XMC4_USIC_DX5CR_OFFSET) +#define XMC4_USCI21_SCTR (XMC4_USCI2_CH1_BASE+XMC4_USIC_SCTR_OFFSET) +#define XMC4_USCI21_TCSR (XMC4_USCI2_CH1_BASE+XMC4_USIC_TCSR_OFFSET) +#define XMC4_USCI21_PCR (XMC4_USCI2_CH1_BASE+XMC4_USIC_PCR_OFFSET) +#define XMC4_USCI21_CCR (XMC4_USCI2_CH1_BASE+XMC4_USIC_CCR_OFFSET) +#define XMC4_USCI21_CMTR (XMC4_USCI2_CH1_BASE+XMC4_USIC_CMTR_OFFSET) +#define XMC4_USCI21_PSR (XMC4_USCI2_CH1_BASE+XMC4_USIC_PSR_OFFSET) +#define XMC4_USCI21_PSCR (XMC4_USCI2_CH1_BASE+XMC4_USIC_PSCR_OFFSET) +#define XMC4_USCI21_RBUFSR (XMC4_USCI2_CH1_BASE+XMC4_USIC_RBUFSR_OFFSET) +#define XMC4_USCI21_RBUF (XMC4_USCI2_CH1_BASE+XMC4_USIC_RBUF_OFFSET) +#define XMC4_USCI21_RBUFD (XMC4_USCI2_CH1_BASE+XMC4_USIC_RBUFD_OFFSET) +#define XMC4_USCI21_RBUF0 (XMC4_USCI2_CH1_BASE+XMC4_USIC_RBUF0_OFFSET) +#define XMC4_USCI21_RBUF1 (XMC4_USCI2_CH1_BASE+XMC4_USIC_RBUF1_OFFSET) +#define XMC4_USCI21_RBUF01SR (XMC4_USCI2_CH1_BASE+XMC4_USIC_RBUF01SR_OFFSET) +#define XMC4_USCI21_FMR (XMC4_USCI2_CH1_BASE+XMC4_USIC_FMR_OFFSET) +#define XMC4_USCI21_TBUF (XMC4_USCI2_CH1_BASE+XMC4_USIC_TBUF_OFFSET) + +/* USCI2 Channel 1 FIFO Registers */ + +#define XMC4_USCI21_BYP (XMC4_USCI2_CH1_BASE+XMC4_USIC_BYP_OFFSET) +#define XMC4_USCI21_BYPCR (XMC4_USCI2_CH1_BASE+XMC4_USIC_BYPCR_OFFSET) +#define XMC4_USCI21_TBCTR (XMC4_USCI2_CH1_BASE+XMC4_USIC_TBCTR_OFFSET) +#define XMC4_USCI21_RBCTR (XMC4_USCI2_CH1_BASE+XMC4_USIC_RBCTR_OFFSET) +#define XMC4_USCI21_TRBPTR (XMC4_USCI2_CH1_BASE+XMC4_USIC_TRBPTR_OFFSET) +#define XMC4_USCI21_TRBSR (XMC4_USCI2_CH1_BASE+XMC4_USIC_TRBSR_OFFSET) +#define XMC4_USCI21_TRBSCR (XMC4_USCI2_CH1_BASE+XMC4_USIC_TRBSCR_OFFSET) +#define XMC4_USCI21_OUTR (XMC4_USCI2_CH1_BASE+XMC4_USIC_OUTR_OFFSET) +#define XMC4_USCI21_OUTDR (XMC4_USCI2_CH1_BASE+XMC4_USIC_OUTDR_OFFSET) +#define XMC4_USCI21_IN (XMC4_USCI2_CH1_BASE+XMC4_USIC_IN_OFFSET) + +/* Register Bit-Field Definitions **************************************************/ + +/* Kernal Registers */ +/* Kernel State Configuration Register */ + +#define USIC_ID_MOD_REV_SHIFT (0) /* Bits 0-7: Module Revision Number */ +#define USIC_ID_MOD_REV_MASK (0xff << USIC_ID_MOD_REV_SHIFT) +#define USIC_ID_MOD_TYPE_SHIFT (8) /* Bits 8-15: Module Type */ +#define USIC_ID_MOD_TYPE_MASK (0xff << USIC_ID_MOD_REV_SHIFT) +#define USIC_ID_MOD_NUMBER_SHIFT (16) /* Bits 16-31: Module Number Value */ +#define USIC_ID_MOD_NUMBER_MASK (0xffff << USIC_ID_MOD_NUMBER_SHIFT) + +/* USIC Channel Registers */ + +/* Channel Configuration Register */ +#define USIC_CCFG_ +/* Kernel State Configuration Register */ +#define USIC_KSCFG_ +/* Fractional Divider Register */ +#define USIC_FDR_ +/* Baud Rate Generator Register */ +#define USIC_BRG_ +/* Interrupt Node Pointer Register */ +#define USIC_INPR_ +/* Input Control Register 0 */ +#define USIC_DX0CR_ +/* Input Control Register 1 */ +#define USIC_DX1CR_ +/* Input Control Register 2 */ +#define USIC_DX2CR_ +/* Input Control Register 3 */ +#define USIC_DX3CR_ +/* Input Control Register 4 */ +#define USIC_DX4CR_ +/* Input Control Register 5 */ +#define USIC_DX5CR_ +/* Shift Control Register */ +#define USIC_SCTR_ +/* Transmit Control/Status Register */ +#define USIC_TCSR_ +/* Protocol Control Register */ +#define USIC_PCR_ +/* Channel Control Register */ +#define USIC_CCR_ +/* Capture Mode Timer Register */ +#define USIC_CMTR_ +/* Protocol Status Register */ +#define USIC_PSR_ +/* Protocol Status Clear Register */ +#define USIC_PSCR_ +/* Receiver Buffer Status Register */ +#define USIC_RBUFSR_ +/* Receiver Buffer Register */ +#define USIC_RBUF_ +/* Receiver Buffer Register for Debugger */ +#define USIC_RBUFD_ +/* Receiver Buffer Register 0 */ +#define USIC_RBUF0_ +/* Receiver Buffer Register 1 */ +#define USIC_RBUF1_ +/* Receiver Buffer 01 Status Register */ +#define USIC_RBUF01SR_ +/* Flag Modification Register */ +#define USIC_FMR_ +/* Transmit Buffer (32 x 4-bytes) */ +#define USIC_TBUF_ + +/* USIC FIFO Registers */ + +/* Bypass Data Register */ +#define USIC_BYP_ +/* Bypass Control Register */ +#define USIC_BYPCR_ +/* Transmitter Buffer Control Register */ +#define USIC_TBCTR_ +/* Receiver Buffer Control Register */ +#define USIC_RBCTR_ +/* Transmit/Receive Buffer Pointer Register */ +#define USIC_TRBPTR_ +/* Transmit/Receive Buffer Status Register */ +#define USIC_TRBSR_ +/* Transmit/Receive Buffer Status Clear Register */ +#define USIC_TRBSCR_ +/* Receiver Buffer Output Register */ +#define USIC_OUTR_ +/* Receiver Buffer Output Register L for Debugger */ +#define USIC_OUTDR_ +/* Transmit FIFO Buffer (32 x 4-bytes) */ +#define USIC_IN_ + +#endif /* __ARCH_ARM_SRC_XMC4_CHIP_XMC4_SCU_H */ From e30e47683bb23c45e0b029303bef28eabf895611 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 16 Mar 2017 13:24:32 -0600 Subject: [PATCH 12/21] XMC4xxx: Add partial PORTS header file. --- arch/arm/src/xmc4/chip/xmc4_ports.h | 279 ++++++++++++++++++++++++++++ 1 file changed, 279 insertions(+) create mode 100644 arch/arm/src/xmc4/chip/xmc4_ports.h diff --git a/arch/arm/src/xmc4/chip/xmc4_ports.h b/arch/arm/src/xmc4/chip/xmc4_ports.h new file mode 100644 index 00000000000..9bfa067eca2 --- /dev/null +++ b/arch/arm/src/xmc4/chip/xmc4_ports.h @@ -0,0 +1,279 @@ +/************************************************************************************ + * arch/arm/src/xmc4/chip/xmc4_ports.h + * + * Copyright (C /*2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Reference: XMC4500 Reference Manual V1.5 2014-07 Microcontrollers. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION /*HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE /*ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * May include some logic from sample code provided by Infineon: + * + * Copyright (C /*2011-2015 Infineon Technologies AG. All rights reserved. + * + * Infineon Technologies AG (Infineon /*is supplying this software for use with + * Infineon's microcontrollers. This file can be freely distributed within + * development tools that are supporting such microcontrollers. + * + * THIS SOFTWARE IS PROVIDED AS IS. NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, + * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_XMC4_CHIP_XMC4_PORTS_H +#define __ARCH_ARM_SRC_XMC4_CHIP_XMC4_PORTS_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Register Offsets *****************************************************************/ + +/* PORTS Registers */ + +#define XMC4_PORTS_OUT_OFFSET 0x0000 /* Port Output Register */ +#define XMC4_PORTS_OMR_OFFSET 0x0004 /* Port Output Modification Register */ +#define XMC4_PORTS_IOCR0_OFFSET 0x0010 /* Port Input/Output Control Register 0 */ +#define XMC4_PORTS_IOCR4_OFFSET 0x0014 /* Port Input/Output Control Register 4 */ +#define XMC4_PORTS_IOCR8_OFFSET 0x0018 /* Port Input/Output Control Register 8 */ +#define XMC4_PORTS_IOCR12_OFFSET 0x001c /* Port Input/Output Control Register 12 */ +#define XMC4_PORTS_IN_OFFSET 0x0024 /* Port Input Register */ +#define XMC4_PORTS_PDR0_OFFSET 0x0040 /* Port Pad Driver Mode 0 Register */ +#define XMC4_PORTS_PDR1_OFFSET 0x0044 /* Port Pad Driver Mode 1 Register */ +#define XMC4_PORTS_PDISC_OFFSET 0x0060 /* Port Pin Function Decision Control Register */ +#define XMC4_PORTS_PPS_OFFSET 0x0070 /* Port Pin Power Save Register */ +#define XMC4_PORTS_HWSEL_OFFSET 0x0074 /* Port Pin Hardware Select Register */ + +/* Register Addresses ****************************************************************/ +#define 0x48028000 +#define XMC4_PORT1_BASE 0x48028100 +#define XMC4_PORT2_BASE 0x48028200 +#define XMC4_PORT3_BASE 0x48028300 +#define XMC4_PORT4_BASE 0x48028400 +#define XMC4_PORT5_BASE 0x48028500 +#define XMC4_PORT6_BASE 0x48028600 +#define XMC4_PORT7_BASE 0x48028700 +#define XMC4_PORT8_BASE 0x48028800 +#define XMC4_PORT9_BASE 0x48028900 +#define XMC4_PORT14_BASE 0x48028e00 +#define XMC4_PORT15_BASE 0x48028f00 + +#define XMC4_PORT0_OUT (XMC4_PORT0_BASE+XMC4_PORTS_OUT_OFFSET) +#define XMC4_PORT0_OMR (XMC4_PORT0_BASE+XMC4_PORTS_OMR_OFFSET) +#define XMC4_PORT0_IOCR0 (XMC4_PORT0_BASE+XMC4_PORTS_IOCR0_OFFSET) +#define XMC4_PORT0_IOCR4 (XMC4_PORT0_BASE+XMC4_PORTS_IOCR4_OFFSET) +#define XMC4_PORT0_IOCR8 (XMC4_PORT0_BASE+XMC4_PORTS_IOCR8_OFFSET) +#define XMC4_PORT0_IOCR12 (XMC4_PORT0_BASE+XMC4_PORTS_IOCR12_OFFSET) +#define XMC4_PORT0_IN (XMC4_PORT0_BASE+XMC4_PORTS_IN_OFFSET) +#define XMC4_PORT0_PDR0 (XMC4_PORT0_BASE+XMC4_PORTS_PDR0_OFFSET) +#define XMC4_PORT0_PDR1 (XMC4_PORT0_BASE+XMC4_PORTS_PDR1_OFFSET) +#define XMC4_PORT0_PDISC (XMC4_PORT0_BASE+XMC4_PORTS_PDISC_OFFSET) +#define XMC4_PORT0_PPS (XMC4_PORT0_BASE+XMC4_PORTS_PPS_OFFSET) +#define XMC4_PORT0_HWSEL (XMC4_PORT0_BASE+XMC4_PORTS_HWSEL_OFFSET) + +#define XMC4_PORT1_OUT (XMC4_PORT1_BASE+XMC4_PORTS_OUT_OFFSET) +#define XMC4_PORT1_OMR (XMC4_PORT1_BASE+XMC4_PORTS_OMR_OFFSET) +#define XMC4_PORT1_IOCR0 (XMC4_PORT1_BASE+XMC4_PORTS_IOCR0_OFFSET) +#define XMC4_PORT1_IOCR4 (XMC4_PORT1_BASE+XMC4_PORTS_IOCR4_OFFSET) +#define XMC4_PORT1_IOCR8 (XMC4_PORT1_BASE+XMC4_PORTS_IOCR8_OFFSET) +#define XMC4_PORT1_IOCR12 (XMC4_PORT1_BASE+XMC4_PORTS_IOCR12_OFFSET) +#define XMC4_PORT1_IN (XMC4_PORT1_BASE+XMC4_PORTS_IN_OFFSET) +#define XMC4_PORT1_PDR0 (XMC4_PORT1_BASE+XMC4_PORTS_PDR0_OFFSET) +#define XMC4_PORT1_PDR1 (XMC4_PORT1_BASE+XMC4_PORTS_PDR1_OFFSET) +#define XMC4_PORT1_PDISC (XMC4_PORT1_BASE+XMC4_PORTS_PDISC_OFFSET) +#define XMC4_PORT1_PPS (XMC4_PORT1_BASE+XMC4_PORTS_PPS_OFFSET) +#define XMC4_PORT1_HWSEL (XMC4_PORT1_BASE+XMC4_PORTS_HWSEL_OFFSET) + +#define XMC4_PORT2_OUT (XMC4_PORT2_BASE+XMC4_PORTS_OUT_OFFSET) +#define XMC4_PORT2_OMR (XMC4_PORT2_BASE+XMC4_PORTS_OMR_OFFSET) +#define XMC4_PORT2_IOCR0 (XMC4_PORT2_BASE+XMC4_PORTS_IOCR0_OFFSET) +#define XMC4_PORT2_IOCR4 (XMC4_PORT2_BASE+XMC4_PORTS_IOCR4_OFFSET) +#define XMC4_PORT2_IOCR8 (XMC4_PORT2_BASE+XMC4_PORTS_IOCR8_OFFSET) +#define XMC4_PORT2_IOCR12 (XMC4_PORT2_BASE+XMC4_PORTS_IOCR12_OFFSET) +#define XMC4_PORT2_IN (XMC4_PORT2_BASE+XMC4_PORTS_IN_OFFSET) +#define XMC4_PORT2_PDR0 (XMC4_PORT2_BASE+XMC4_PORTS_PDR0_OFFSET) +#define XMC4_PORT2_PDR1 (XMC4_PORT2_BASE+XMC4_PORTS_PDR1_OFFSET) +#define XMC4_PORT2_PDISC (XMC4_PORT2_BASE+XMC4_PORTS_PDISC_OFFSET) +#define XMC4_PORT2_PPS (XMC4_PORT2_BASE+XMC4_PORTS_PPS_OFFSET) +#define XMC4_PORT2_HWSEL (XMC4_PORT2_BASE+XMC4_PORTS_HWSEL_OFFSET) + +#define XMC4_PORT3_OUT (XMC4_PORT3_BASE+XMC4_PORTS_OUT_OFFSET) +#define XMC4_PORT3_OMR (XMC4_PORT3_BASE+XMC4_PORTS_OMR_OFFSET) +#define XMC4_PORT3_IOCR0 (XMC4_PORT3_BASE+XMC4_PORTS_IOCR0_OFFSET) +#define XMC4_PORT3_IOCR4 (XMC4_PORT3_BASE+XMC4_PORTS_IOCR4_OFFSET) +#define XMC4_PORT3_IOCR8 (XMC4_PORT3_BASE+XMC4_PORTS_IOCR8_OFFSET) +#define XMC4_PORT3_IOCR12 (XMC4_PORT3_BASE+XMC4_PORTS_IOCR12_OFFSET) +#define XMC4_PORT3_IN (XMC4_PORT3_BASE+XMC4_PORTS_IN_OFFSET) +#define XMC4_PORT3_PDR0 (XMC4_PORT3_BASE+XMC4_PORTS_PDR0_OFFSET) +#define XMC4_PORT3_PDR1 (XMC4_PORT3_BASE+XMC4_PORTS_PDR1_OFFSET) +#define XMC4_PORT3_PDISC (XMC4_PORT3_BASE+XMC4_PORTS_PDISC_OFFSET) +#define XMC4_PORT3_PPS (XMC4_PORT3_BASE+XMC4_PORTS_PPS_OFFSET) +#define XMC4_PORT3_HWSEL (XMC4_PORT3_BASE+XMC4_PORTS_HWSEL_OFFSET) + +#define XMC4_PORT4_OUT (XMC4_PORT4_BASE+XMC4_PORTS_OUT_OFFSET) +#define XMC4_PORT4_OMR (XMC4_PORT4_BASE+XMC4_PORTS_OMR_OFFSET) +#define XMC4_PORT4_IOCR0 (XMC4_PORT4_BASE+XMC4_PORTS_IOCR0_OFFSET) +#define XMC4_PORT4_IOCR4 (XMC4_PORT4_BASE+XMC4_PORTS_IOCR4_OFFSET) +#define XMC4_PORT4_IOCR8 (XMC4_PORT4_BASE+XMC4_PORTS_IOCR8_OFFSET) +#define XMC4_PORT4_IOCR12 (XMC4_PORT4_BASE+XMC4_PORTS_IOCR12_OFFSET) +#define XMC4_PORT4_IN (XMC4_PORT4_BASE+XMC4_PORTS_IN_OFFSET) +#define XMC4_PORT4_PDR0 (XMC4_PORT4_BASE+XMC4_PORTS_PDR0_OFFSET) +#define XMC4_PORT4_PDR1 (XMC4_PORT4_BASE+XMC4_PORTS_PDR1_OFFSET) +#define XMC4_PORT4_PDISC (XMC4_PORT4_BASE+XMC4_PORTS_PDISC_OFFSET) +#define XMC4_PORT4_PPS (XMC4_PORT4_BASE+XMC4_PORTS_PPS_OFFSET) +#define XMC4_PORT4_HWSEL (XMC4_PORT4_BASE+XMC4_PORTS_HWSEL_OFFSET) + +#define XMC4_PORT5_OUT (XMC4_PORT5_BASE+XMC4_PORTS_OUT_OFFSET) +#define XMC4_PORT5_OMR (XMC4_PORT5_BASE+XMC4_PORTS_OMR_OFFSET) +#define XMC4_PORT5_IOCR0 (XMC4_PORT5_BASE+XMC4_PORTS_IOCR0_OFFSET) +#define XMC4_PORT5_IOCR4 (XMC4_PORT5_BASE+XMC4_PORTS_IOCR4_OFFSET) +#define XMC4_PORT5_IOCR8 (XMC4_PORT5_BASE+XMC4_PORTS_IOCR8_OFFSET) +#define XMC4_PORT5_IOCR12 (XMC4_PORT5_BASE+XMC4_PORTS_IOCR12_OFFSET) +#define XMC4_PORT5_IN (XMC4_PORT5_BASE+XMC4_PORTS_IN_OFFSET) +#define XMC4_PORT5_PDR0 (XMC4_PORT5_BASE+XMC4_PORTS_PDR0_OFFSET) +#define XMC4_PORT5_PDR1 (XMC4_PORT5_BASE+XMC4_PORTS_PDR1_OFFSET) +#define XMC4_PORT5_PDISC (XMC4_PORT5_BASE+XMC4_PORTS_PDISC_OFFSET) +#define XMC4_PORT5_PPS (XMC4_PORT5_BASE+XMC4_PORTS_PPS_OFFSET) +#define XMC4_PORT5_HWSEL (XMC4_PORT5_BASE+XMC4_PORTS_HWSEL_OFFSET) + +#define XMC4_PORT6_OUT (XMC4_PORT6_BASE+XMC4_PORTS_OUT_OFFSET) +#define XMC4_PORT6_OMR (XMC4_PORT6_BASE+XMC4_PORTS_OMR_OFFSET) +#define XMC4_PORT6_IOCR0 (XMC4_PORT6_BASE+XMC4_PORTS_IOCR0_OFFSET) +#define XMC4_PORT6_IOCR4 (XMC4_PORT6_BASE+XMC4_PORTS_IOCR4_OFFSET) +#define XMC4_PORT6_IOCR8 (XMC4_PORT6_BASE+XMC4_PORTS_IOCR8_OFFSET) +#define XMC4_PORT6_IOCR12 (XMC4_PORT6_BASE+XMC4_PORTS_IOCR12_OFFSET) +#define XMC4_PORT6_IN (XMC4_PORT6_BASE+XMC4_PORTS_IN_OFFSET) +#define XMC4_PORT6_PDR0 (XMC4_PORT6_BASE+XMC4_PORTS_PDR0_OFFSET) +#define XMC4_PORT6_PDR1 (XMC4_PORT6_BASE+XMC4_PORTS_PDR1_OFFSET) +#define XMC4_PORT6_PDISC (XMC4_PORT6_BASE+XMC4_PORTS_PDISC_OFFSET) +#define XMC4_PORT6_PPS (XMC4_PORT6_BASE+XMC4_PORTS_PPS_OFFSET) +#define XMC4_PORT6_HWSEL (XMC4_PORT6_BASE+XMC4_PORTS_HWSEL_OFFSET) + +#define XMC4_PORT7_OUT (XMC4_PORT7_BASE+XMC4_PORTS_OUT_OFFSET) +#define XMC4_PORT7_OMR (XMC4_PORT7_BASE+XMC4_PORTS_OMR_OFFSET) +#define XMC4_PORT7_IOCR0 (XMC4_PORT7_BASE+XMC4_PORTS_IOCR0_OFFSET) +#define XMC4_PORT7_IOCR4 (XMC4_PORT7_BASE+XMC4_PORTS_IOCR4_OFFSET) +#define XMC4_PORT7_IOCR8 (XMC4_PORT7_BASE+XMC4_PORTS_IOCR8_OFFSET) +#define XMC4_PORT7_IOCR12 (XMC4_PORT7_BASE+XMC4_PORTS_IOCR12_OFFSET) +#define XMC4_PORT7_IN (XMC4_PORT7_BASE+XMC4_PORTS_IN_OFFSET) +#define XMC4_PORT7_PDR0 (XMC4_PORT7_BASE+XMC4_PORTS_PDR0_OFFSET) +#define XMC4_PORT7_PDR1 (XMC4_PORT7_BASE+XMC4_PORTS_PDR1_OFFSET) +#define XMC4_PORT7_PDISC (XMC4_PORT7_BASE+XMC4_PORTS_PDISC_OFFSET) +#define XMC4_PORT7_PPS (XMC4_PORT7_BASE+XMC4_PORTS_PPS_OFFSET) +#define XMC4_PORT7_HWSEL (XMC4_PORT7_BASE+XMC4_PORTS_HWSEL_OFFSET) + +#define XMC4_PORT8_OUT (XMC4_PORT8_BASE+XMC4_PORTS_OUT_OFFSET) +#define XMC4_PORT8_OMR (XMC4_PORT8_BASE+XMC4_PORTS_OMR_OFFSET) +#define XMC4_PORT8_IOCR0 (XMC4_PORT8_BASE+XMC4_PORTS_IOCR0_OFFSET) +#define XMC4_PORT8_IOCR4 (XMC4_PORT8_BASE+XMC4_PORTS_IOCR4_OFFSET) +#define XMC4_PORT8_IOCR8 (XMC4_PORT8_BASE+XMC4_PORTS_IOCR8_OFFSET) +#define XMC4_PORT8_IOCR12 (XMC4_PORT8_BASE+XMC4_PORTS_IOCR12_OFFSET) +#define XMC4_PORT8_IN (XMC4_PORT8_BASE+XMC4_PORTS_IN_OFFSET) +#define XMC4_PORT8_PDR0 (XMC4_PORT8_BASE+XMC4_PORTS_PDR0_OFFSET) +#define XMC4_PORT8_PDR1 (XMC4_PORT8_BASE+XMC4_PORTS_PDR1_OFFSET) +#define XMC4_PORT8_PDISC (XMC4_PORT8_BASE+XMC4_PORTS_PDISC_OFFSET) +#define XMC4_PORT8_PPS (XMC4_PORT8_BASE+XMC4_PORTS_PPS_OFFSET) +#define XMC4_PORT8_HWSEL (XMC4_PORT8_BASE+XMC4_PORTS_HWSEL_OFFSET) + +#define XMC4_PORT9_OUT (XMC4_PORT9_BASE+XMC4_PORTS_OUT_OFFSET) +#define XMC4_PORT9_OMR (XMC4_PORT9_BASE+XMC4_PORTS_OMR_OFFSET) +#define XMC4_PORT9_IOCR0 (XMC4_PORT9_BASE+XMC4_PORTS_IOCR0_OFFSET) +#define XMC4_PORT9_IOCR4 (XMC4_PORT9_BASE+XMC4_PORTS_IOCR4_OFFSET) +#define XMC4_PORT9_IOCR8 (XMC4_PORT9_BASE+XMC4_PORTS_IOCR8_OFFSET) +#define XMC4_PORT9_IOCR12 (XMC4_PORT9_BASE+XMC4_PORTS_IOCR12_OFFSET) +#define XMC4_PORT9_IN (XMC4_PORT9_BASE+XMC4_PORTS_IN_OFFSET) +#define XMC4_PORT9_PDR0 (XMC4_PORT9_BASE+XMC4_PORTS_PDR0_OFFSET) +#define XMC4_PORT9_PDR1 (XMC4_PORT9_BASE+XMC4_PORTS_PDR1_OFFSET) +#define XMC4_PORT9_PDISC (XMC4_PORT9_BASE+XMC4_PORTS_PDISC_OFFSET) +#define XMC4_PORT9_PPS (XMC4_PORT9_BASE+XMC4_PORTS_PPS_OFFSET) +#define XMC4_PORT9_HWSEL (XMC4_PORT9_BASE+XMC4_PORTS_HWSEL_OFFSET) + +#define XMC4_PORT14_OUT (XMC4_PORT14_BASE+XMC4_PORTS_OUT_OFFSET) +#define XMC4_PORT14_OMR (XMC4_PORT14_BASE+XMC4_PORTS_OMR_OFFSET) +#define XMC4_PORT14_IOCR0 (XMC4_PORT14_BASE+XMC4_PORTS_IOCR0_OFFSET) +#define XMC4_PORT14_IOCR4 (XMC4_PORT14_BASE+XMC4_PORTS_IOCR4_OFFSET) +#define XMC4_PORT14_IOCR8 (XMC4_PORT14_BASE+XMC4_PORTS_IOCR8_OFFSET) +#define XMC4_PORT14_IOCR12 (XMC4_PORT14_BASE+XMC4_PORTS_IOCR12_OFFSET) +#define XMC4_PORT14_IN (XMC4_PORT14_BASE+XMC4_PORTS_IN_OFFSET) +#define XMC4_PORT14_PDR0 (XMC4_PORT14_BASE+XMC4_PORTS_PDR0_OFFSET) +#define XMC4_PORT14_PDR1 (XMC4_PORT14_BASE+XMC4_PORTS_PDR1_OFFSET) +#define XMC4_PORT14_PDISC (XMC4_PORT14_BASE+XMC4_PORTS_PDISC_OFFSET) +#define XMC4_PORT14_PPS (XMC4_PORT14_BASE+XMC4_PORTS_PPS_OFFSET) +#define XMC4_PORT14_HWSEL (XMC4_PORT14_BASE+XMC4_PORTS_HWSEL_OFFSET) + +#define XMC4_PORT15_OUT (XMC4_PORT15_BASE+XMC4_PORTS_OUT_OFFSET) +#define XMC4_PORT15_OMR (XMC4_PORT15_BASE+XMC4_PORTS_OMR_OFFSET) +#define XMC4_PORT15_IOCR0 (XMC4_PORT15_BASE+XMC4_PORTS_IOCR0_OFFSET) +#define XMC4_PORT15_IOCR4 (XMC4_PORT15_BASE+XMC4_PORTS_IOCR4_OFFSET) +#define XMC4_PORT15_IOCR8 (XMC4_PORT15_BASE+XMC4_PORTS_IOCR8_OFFSET) +#define XMC4_PORT15_IOCR12 (XMC4_PORT15_BASE+XMC4_PORTS_IOCR12_OFFSET) +#define XMC4_PORT15_IN (XMC4_PORT15_BASE+XMC4_PORTS_IN_OFFSET) +#define XMC4_PORT15_PDR0 (XMC4_PORT15_BASE+XMC4_PORTS_PDR0_OFFSET) +#define XMC4_PORT15_PDR1 (XMC4_PORT15_BASE+XMC4_PORTS_PDR1_OFFSET) +#define XMC4_PORT15_PDISC (XMC4_PORT15_BASE+XMC4_PORTS_PDISC_OFFSET) +#define XMC4_PORT15_PPS (XMC4_PORT15_BASE+XMC4_PORTS_PPS_OFFSET) +#define XMC4_PORT15_HWSEL (XMC4_PORT15_BASE+XMC4_PORTS_HWSEL_OFFSET) + +/* Register Bit-Field Definitions **************************************************/ + +/* Port Output Register */ +#define PORTS_OUT_ +/* Port Output Modification Register */ +#define PORTS_OMR_ +/* Port Input/Output Control Register 0 */ +#define PORTS_IOCR0_ +/* Port Input/Output Control Register 4 */ +#define PORTS_IOCR4_ +/* Port Input/Output Control Register 8 */ +#define PORTS_IOCR8_ +/* Port Input/Output Control Register 12 */ +#define PORTS_IOCR12_ +/* Port Input Register */ +#define PORTS_IN_ +/* Port Pad Driver Mode 0 Register */ +#define PORTS_PDR0_ +/* Port Pad Driver Mode 1 Register */ +#define PORTS_PDR1_ +/* Port Pin Function Decision Control Register */ +#define PORTS_PDISC_ +/* Port Pin Power Save Register */ +#define PORTS_PPS_ +/* Port Pin Hardware Select Register */ +#define PORTS_HWSEL_ + +#endif /* __ARCH_ARM_SRC_XMC4_CHIP_XMC4_SCU_H */ From 6b167122c0e82f55f95b1037c1f63eb3fdc99c32 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 16 Mar 2017 14:26:22 -0600 Subject: [PATCH 13/21] XMC4xxx: Move clock utility functions from xmc4_clocconfig.c to new xmc4_clockutils.c --- arch/arm/src/xmc4/Make.defs | 6 +- arch/arm/src/xmc4/chip/xmc4_memorymap.h | 2 +- arch/arm/src/xmc4/xmc4_clockconfig.c | 84 ------------- arch/arm/src/xmc4/xmc4_clockutils.c | 150 ++++++++++++++++++++++++ 4 files changed, 154 insertions(+), 88 deletions(-) create mode 100644 arch/arm/src/xmc4/xmc4_clockutils.c diff --git a/arch/arm/src/xmc4/Make.defs b/arch/arm/src/xmc4/Make.defs index 79497388a49..63998a71336 100644 --- a/arch/arm/src/xmc4/Make.defs +++ b/arch/arm/src/xmc4/Make.defs @@ -110,9 +110,9 @@ endif CHIP_ASRCS = -CHIP_CSRCS = xmc4_allocateheap.c xmc4_clockconfig.c xmc4_clrpend.c -CHIP_CSRCS += xmc4_idle.c xmc4_irq.c xmc4_lowputc.c xmc4_gpio.c -CHIP_CSRCS += xmc4_serialinit.c xmc4_serial.c xmc4_start.c xmc4_uid.c +CHIP_CSRCS = xmc4_allocateheap.c xmc4_clockconfig.c xmc4_clockutils.c +CHIP_CSRCS += xmc4_clrpend.c xmc4_idle.c xmc4_irq.c xmc4_lowputc.c +CHIP_CSRCS += xmc4_gpio.c xmc4_serial.c xmc4_start.c # Configuration-dependent Kinetis files diff --git a/arch/arm/src/xmc4/chip/xmc4_memorymap.h b/arch/arm/src/xmc4/chip/xmc4_memorymap.h index c6d15f234f5..c2b847d4e07 100644 --- a/arch/arm/src/xmc4/chip/xmc4_memorymap.h +++ b/arch/arm/src/xmc4/chip/xmc4_memorymap.h @@ -147,7 +147,7 @@ #define XMC4_USIC2_BASE 0x48024000 #define XMC4_USIC2_CH0_BASE 0x48024000 #define XMC4_USIC2_CH1_BASE 0x48024200 -#define XMC4_USIC2_CH1_BASE 0x48024400 +#define XMC4_USIC2_RAM_BASE 0x48024400 #define XMC4_PORT0_BASE 0x48028000 #define XMC4_PORT1_BASE 0x48028100 #define XMC4_PORT2_BASE 0x48028200 diff --git a/arch/arm/src/xmc4/xmc4_clockconfig.c b/arch/arm/src/xmc4/xmc4_clockconfig.c index 26608a85b84..d663ea9f82d 100644 --- a/arch/arm/src/xmc4/xmc4_clockconfig.c +++ b/arch/arm/src/xmc4/xmc4_clockconfig.c @@ -529,87 +529,3 @@ void xmc4_clock_configure(void) putreg32(CLKSET_VALUE, XMC4_SCU_CLKSET); } - -/**************************************************************************** - * Name: xmc4_get_coreclock - * - * Description: - * Return the current core clock frequency (fCPU). - * - ****************************************************************************/ - -uint32_t xmc4_get_coreclock(void) -{ - uint32_t pdiv; - uint32_t ndiv; - uint32_t kdiv; - uint32_t sysdiv; - uint32_t regval; - uint32_t temp; - - if ((getreg32(XMC4_SCU_SYSCLKCR) & SCU_SYSCLKCR_SYSSEL) != 0) - { - /* fPLL is clock source for fSYS */ - - if ((getreg32(XMC4_SCU_PLLCON2) & SCU_PLLCON2_PINSEL) != 0) - { - /* PLL input clock is the backup clock (fOFI) */ - - temp = OFI_FREQUENCY; - } - else - { - /* PLL input clock is the high performance oscillator (fOSCHP); - * Only board specific logic knows this value. - */ - - temp = BOARD_XTAL_FREQUENCY; - } - - /* Check if PLL is locked */ - - regval = getreg32(XMC4_SCU_PLLSTAT); - if ((regval & SCU_PLLSTAT_VCOLOCK) != 0) - { - /* PLL normal mode */ - - regval = getreg32(XMC4_SCU_PLLCON1); - pdiv = ((regval & SCU_PLLCON1_PDIV_MASK) >> SCU_PLLCON1_PDIV_SHIFT) + 1; - ndiv = ((regval & SCU_PLLCON1_NDIV_MASK) >> SCU_PLLCON1_NDIV_SHIFT) + 1; - kdiv = ((regval & SCU_PLLCON1_K2DIV_MASK) >> SCU_PLLCON1_K2DIV_SHIFT) + 1; - - temp = (temp / (pdiv * kdiv)) * ndiv; - } - else - { - /* PLL prescalar mode */ - - regval = getreg32(XMC4_SCU_PLLCON1); - kdiv = ((regval & SCU_PLLCON1_K1DIV_MASK) >> SCU_PLLCON1_K1DIV_SHIFT) + 1; - - temp = (temp / kdiv); - } - } - else - { - /* fOFI is clock source for fSYS */ - - temp = OFI_FREQUENCY; - } - - /* Divide by SYSDIV to get fSYS */ - - regval = getreg32(XMC4_SCU_SYSCLKCR); - sysdiv = ((regval & SCU_SYSCLKCR_SYSDIV_MASK) >> SCU_SYSCLKCR_SYSDIV_SHIFT) + 1; - temp = temp / sysdiv; - - /* Check if the fSYS clock is divided by two to produce fCPU clock. */ - - regval = getreg32(XMC4_SCU_CPUCLKCR); - if ((regval & SCU_CPUCLKCR_CPUDIV) != 0) - { - temp = temp >> 1; - } - - return temp; -} diff --git a/arch/arm/src/xmc4/xmc4_clockutils.c b/arch/arm/src/xmc4/xmc4_clockutils.c new file mode 100644 index 00000000000..cf9649099ed --- /dev/null +++ b/arch/arm/src/xmc4/xmc4_clockutils.c @@ -0,0 +1,150 @@ +/**************************************************************************** + * arch/arm/src/xmc4/xmc4_clockutils.c + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt + * + * Reference: XMC4500 Reference Manual V1.5 2014-07 Microcontrollers. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * May include some logic from sample code provided by Infineon: + * + * Copyright (C) 2011-2015 Infineon Technologies AG. All rights reserved. + * + * Infineon Technologies AG (Infineon) is supplying this software for use with + * Infineon's microcontrollers. This file can be freely distributed within + * development tools that are supporting such microcontrollers. + * + * THIS SOFTWARE IS PROVIDED AS IS. NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, + * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "up_arch.h" +#include "chip/xmc4_scu.h" +#include "xmc4_clockconfig.h" + +#include + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: xmc4_get_coreclock + * + * Description: + * Return the current core clock frequency (fCPU). + * + ****************************************************************************/ + +uint32_t xmc4_get_coreclock(void) +{ + uint32_t pdiv; + uint32_t ndiv; + uint32_t kdiv; + uint32_t sysdiv; + uint32_t regval; + uint32_t temp; + + if ((getreg32(XMC4_SCU_SYSCLKCR) & SCU_SYSCLKCR_SYSSEL) != 0) + { + /* fPLL is clock source for fSYS */ + + if ((getreg32(XMC4_SCU_PLLCON2) & SCU_PLLCON2_PINSEL) != 0) + { + /* PLL input clock is the backup clock (fOFI) */ + + temp = OFI_FREQUENCY; + } + else + { + /* PLL input clock is the high performance oscillator (fOSCHP); + * Only board specific logic knows this value. + */ + + temp = BOARD_XTAL_FREQUENCY; + } + + /* Check if PLL is locked */ + + regval = getreg32(XMC4_SCU_PLLSTAT); + if ((regval & SCU_PLLSTAT_VCOLOCK) != 0) + { + /* PLL normal mode */ + + regval = getreg32(XMC4_SCU_PLLCON1); + pdiv = ((regval & SCU_PLLCON1_PDIV_MASK) >> SCU_PLLCON1_PDIV_SHIFT) + 1; + ndiv = ((regval & SCU_PLLCON1_NDIV_MASK) >> SCU_PLLCON1_NDIV_SHIFT) + 1; + kdiv = ((regval & SCU_PLLCON1_K2DIV_MASK) >> SCU_PLLCON1_K2DIV_SHIFT) + 1; + + temp = (temp / (pdiv * kdiv)) * ndiv; + } + else + { + /* PLL prescalar mode */ + + regval = getreg32(XMC4_SCU_PLLCON1); + kdiv = ((regval & SCU_PLLCON1_K1DIV_MASK) >> SCU_PLLCON1_K1DIV_SHIFT) + 1; + + temp = (temp / kdiv); + } + } + else + { + /* fOFI is clock source for fSYS */ + + temp = OFI_FREQUENCY; + } + + /* Divide by SYSDIV to get fSYS */ + + regval = getreg32(XMC4_SCU_SYSCLKCR); + sysdiv = ((regval & SCU_SYSCLKCR_SYSDIV_MASK) >> SCU_SYSCLKCR_SYSDIV_SHIFT) + 1; + temp = temp / sysdiv; + + /* Check if the fSYS clock is divided by two to produce fCPU clock. */ + + regval = getreg32(XMC4_SCU_CPUCLKCR); + if ((regval & SCU_CPUCLKCR_CPUDIV) != 0) + { + temp = temp >> 1; + } + + return temp; +} From f672478e7ea1a0248c1a1068d43eba486bed954a Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 17 Mar 2017 08:12:21 -0600 Subject: [PATCH 14/21] XMC4xxx: Completes the PORT register definition header file. --- arch/arm/src/xmc4/chip/xmc4_ports.h | 568 +++++++++++++++++++--------- 1 file changed, 383 insertions(+), 185 deletions(-) diff --git a/arch/arm/src/xmc4/chip/xmc4_ports.h b/arch/arm/src/xmc4/chip/xmc4_ports.h index 9bfa067eca2..1d6cfa6b428 100644 --- a/arch/arm/src/xmc4/chip/xmc4_ports.h +++ b/arch/arm/src/xmc4/chip/xmc4_ports.h @@ -66,214 +66,412 @@ /* PORTS Registers */ -#define XMC4_PORTS_OUT_OFFSET 0x0000 /* Port Output Register */ -#define XMC4_PORTS_OMR_OFFSET 0x0004 /* Port Output Modification Register */ -#define XMC4_PORTS_IOCR0_OFFSET 0x0010 /* Port Input/Output Control Register 0 */ -#define XMC4_PORTS_IOCR4_OFFSET 0x0014 /* Port Input/Output Control Register 4 */ -#define XMC4_PORTS_IOCR8_OFFSET 0x0018 /* Port Input/Output Control Register 8 */ -#define XMC4_PORTS_IOCR12_OFFSET 0x001c /* Port Input/Output Control Register 12 */ -#define XMC4_PORTS_IN_OFFSET 0x0024 /* Port Input Register */ -#define XMC4_PORTS_PDR0_OFFSET 0x0040 /* Port Pad Driver Mode 0 Register */ -#define XMC4_PORTS_PDR1_OFFSET 0x0044 /* Port Pad Driver Mode 1 Register */ -#define XMC4_PORTS_PDISC_OFFSET 0x0060 /* Port Pin Function Decision Control Register */ -#define XMC4_PORTS_PPS_OFFSET 0x0070 /* Port Pin Power Save Register */ -#define XMC4_PORTS_HWSEL_OFFSET 0x0074 /* Port Pin Hardware Select Register */ +#define XMC4_PORT_OUT_OFFSET 0x0000 /* Port Output Register */ +#define XMC4_PORT_OMR_OFFSET 0x0004 /* Port Output Modification Register */ +#define XMC4_PORT_IOCR0_OFFSET 0x0010 /* Port Input/Output Control Register 0 */ +#define XMC4_PORT_IOCR4_OFFSET 0x0014 /* Port Input/Output Control Register 4 */ +#define XMC4_PORT_IOCR8_OFFSET 0x0018 /* Port Input/Output Control Register 8 */ +#define XMC4_PORT_IOCR12_OFFSET 0x001c /* Port Input/Output Control Register 12 */ +#define XMC4_PORT_IN_OFFSET 0x0024 /* Port Input Register */ +#define XMC4_PORT_PDR0_OFFSET 0x0040 /* Port Pad Driver Mode 0 Register */ +#define XMC4_PORT_PDR1_OFFSET 0x0044 /* Port Pad Driver Mode 1 Register */ +#define XMC4_PORT_PDISC_OFFSET 0x0060 /* Port Pin Function Decision Control Register */ +#define XMC4_PORT_PPS_OFFSET 0x0070 /* Port Pin Power Save Register */ +#define XMC4_PORT_HWSEL_OFFSET 0x0074 /* Port Pin Hardware Select Register */ /* Register Addresses ****************************************************************/ -#define 0x48028000 -#define XMC4_PORT1_BASE 0x48028100 -#define XMC4_PORT2_BASE 0x48028200 -#define XMC4_PORT3_BASE 0x48028300 -#define XMC4_PORT4_BASE 0x48028400 -#define XMC4_PORT5_BASE 0x48028500 -#define XMC4_PORT6_BASE 0x48028600 -#define XMC4_PORT7_BASE 0x48028700 -#define XMC4_PORT8_BASE 0x48028800 -#define XMC4_PORT9_BASE 0x48028900 -#define XMC4_PORT14_BASE 0x48028e00 -#define XMC4_PORT15_BASE 0x48028f00 -#define XMC4_PORT0_OUT (XMC4_PORT0_BASE+XMC4_PORTS_OUT_OFFSET) -#define XMC4_PORT0_OMR (XMC4_PORT0_BASE+XMC4_PORTS_OMR_OFFSET) -#define XMC4_PORT0_IOCR0 (XMC4_PORT0_BASE+XMC4_PORTS_IOCR0_OFFSET) -#define XMC4_PORT0_IOCR4 (XMC4_PORT0_BASE+XMC4_PORTS_IOCR4_OFFSET) -#define XMC4_PORT0_IOCR8 (XMC4_PORT0_BASE+XMC4_PORTS_IOCR8_OFFSET) -#define XMC4_PORT0_IOCR12 (XMC4_PORT0_BASE+XMC4_PORTS_IOCR12_OFFSET) -#define XMC4_PORT0_IN (XMC4_PORT0_BASE+XMC4_PORTS_IN_OFFSET) -#define XMC4_PORT0_PDR0 (XMC4_PORT0_BASE+XMC4_PORTS_PDR0_OFFSET) -#define XMC4_PORT0_PDR1 (XMC4_PORT0_BASE+XMC4_PORTS_PDR1_OFFSET) -#define XMC4_PORT0_PDISC (XMC4_PORT0_BASE+XMC4_PORTS_PDISC_OFFSET) -#define XMC4_PORT0_PPS (XMC4_PORT0_BASE+XMC4_PORTS_PPS_OFFSET) -#define XMC4_PORT0_HWSEL (XMC4_PORT0_BASE+XMC4_PORTS_HWSEL_OFFSET) +#define XMC4_PORT0_OUT (XMC4_PORT0_BASE+XMC4_PORT_OUT_OFFSET) +#define XMC4_PORT0_OMR (XMC4_PORT0_BASE+XMC4_PORT_OMR_OFFSET) +#define XMC4_PORT0_IOCR0 (XMC4_PORT0_BASE+XMC4_PORT_IOCR0_OFFSET) +#define XMC4_PORT0_IOCR4 (XMC4_PORT0_BASE+XMC4_PORT_IOCR4_OFFSET) +#define XMC4_PORT0_IOCR8 (XMC4_PORT0_BASE+XMC4_PORT_IOCR8_OFFSET) +#define XMC4_PORT0_IOCR12 (XMC4_PORT0_BASE+XMC4_PORT_IOCR12_OFFSET) +#define XMC4_PORT0_IN (XMC4_PORT0_BASE+XMC4_PORT_IN_OFFSET) +#define XMC4_PORT0_PDR0 (XMC4_PORT0_BASE+XMC4_PORT_PDR0_OFFSET) +#define XMC4_PORT0_PDR1 (XMC4_PORT0_BASE+XMC4_PORT_PDR1_OFFSET) +#define XMC4_PORT0_PDISC (XMC4_PORT0_BASE+XMC4_PORT_PDISC_OFFSET) +#define XMC4_PORT0_PPS (XMC4_PORT0_BASE+XMC4_PORT_PPS_OFFSET) +#define XMC4_PORT0_HWSEL (XMC4_PORT0_BASE+XMC4_PORT_HWSEL_OFFSET) -#define XMC4_PORT1_OUT (XMC4_PORT1_BASE+XMC4_PORTS_OUT_OFFSET) -#define XMC4_PORT1_OMR (XMC4_PORT1_BASE+XMC4_PORTS_OMR_OFFSET) -#define XMC4_PORT1_IOCR0 (XMC4_PORT1_BASE+XMC4_PORTS_IOCR0_OFFSET) -#define XMC4_PORT1_IOCR4 (XMC4_PORT1_BASE+XMC4_PORTS_IOCR4_OFFSET) -#define XMC4_PORT1_IOCR8 (XMC4_PORT1_BASE+XMC4_PORTS_IOCR8_OFFSET) -#define XMC4_PORT1_IOCR12 (XMC4_PORT1_BASE+XMC4_PORTS_IOCR12_OFFSET) -#define XMC4_PORT1_IN (XMC4_PORT1_BASE+XMC4_PORTS_IN_OFFSET) -#define XMC4_PORT1_PDR0 (XMC4_PORT1_BASE+XMC4_PORTS_PDR0_OFFSET) -#define XMC4_PORT1_PDR1 (XMC4_PORT1_BASE+XMC4_PORTS_PDR1_OFFSET) -#define XMC4_PORT1_PDISC (XMC4_PORT1_BASE+XMC4_PORTS_PDISC_OFFSET) -#define XMC4_PORT1_PPS (XMC4_PORT1_BASE+XMC4_PORTS_PPS_OFFSET) -#define XMC4_PORT1_HWSEL (XMC4_PORT1_BASE+XMC4_PORTS_HWSEL_OFFSET) +#define XMC4_PORT1_OUT (XMC4_PORT1_BASE+XMC4_PORT_OUT_OFFSET) +#define XMC4_PORT1_OMR (XMC4_PORT1_BASE+XMC4_PORT_OMR_OFFSET) +#define XMC4_PORT1_IOCR0 (XMC4_PORT1_BASE+XMC4_PORT_IOCR0_OFFSET) +#define XMC4_PORT1_IOCR4 (XMC4_PORT1_BASE+XMC4_PORT_IOCR4_OFFSET) +#define XMC4_PORT1_IOCR8 (XMC4_PORT1_BASE+XMC4_PORT_IOCR8_OFFSET) +#define XMC4_PORT1_IOCR12 (XMC4_PORT1_BASE+XMC4_PORT_IOCR12_OFFSET) +#define XMC4_PORT1_IN (XMC4_PORT1_BASE+XMC4_PORT_IN_OFFSET) +#define XMC4_PORT1_PDR0 (XMC4_PORT1_BASE+XMC4_PORT_PDR0_OFFSET) +#define XMC4_PORT1_PDR1 (XMC4_PORT1_BASE+XMC4_PORT_PDR1_OFFSET) +#define XMC4_PORT1_PDISC (XMC4_PORT1_BASE+XMC4_PORT_PDISC_OFFSET) +#define XMC4_PORT1_PPS (XMC4_PORT1_BASE+XMC4_PORT_PPS_OFFSET) +#define XMC4_PORT1_HWSEL (XMC4_PORT1_BASE+XMC4_PORT_HWSEL_OFFSET) -#define XMC4_PORT2_OUT (XMC4_PORT2_BASE+XMC4_PORTS_OUT_OFFSET) -#define XMC4_PORT2_OMR (XMC4_PORT2_BASE+XMC4_PORTS_OMR_OFFSET) -#define XMC4_PORT2_IOCR0 (XMC4_PORT2_BASE+XMC4_PORTS_IOCR0_OFFSET) -#define XMC4_PORT2_IOCR4 (XMC4_PORT2_BASE+XMC4_PORTS_IOCR4_OFFSET) -#define XMC4_PORT2_IOCR8 (XMC4_PORT2_BASE+XMC4_PORTS_IOCR8_OFFSET) -#define XMC4_PORT2_IOCR12 (XMC4_PORT2_BASE+XMC4_PORTS_IOCR12_OFFSET) -#define XMC4_PORT2_IN (XMC4_PORT2_BASE+XMC4_PORTS_IN_OFFSET) -#define XMC4_PORT2_PDR0 (XMC4_PORT2_BASE+XMC4_PORTS_PDR0_OFFSET) -#define XMC4_PORT2_PDR1 (XMC4_PORT2_BASE+XMC4_PORTS_PDR1_OFFSET) -#define XMC4_PORT2_PDISC (XMC4_PORT2_BASE+XMC4_PORTS_PDISC_OFFSET) -#define XMC4_PORT2_PPS (XMC4_PORT2_BASE+XMC4_PORTS_PPS_OFFSET) -#define XMC4_PORT2_HWSEL (XMC4_PORT2_BASE+XMC4_PORTS_HWSEL_OFFSET) +#define XMC4_PORT2_OUT (XMC4_PORT2_BASE+XMC4_PORT_OUT_OFFSET) +#define XMC4_PORT2_OMR (XMC4_PORT2_BASE+XMC4_PORT_OMR_OFFSET) +#define XMC4_PORT2_IOCR0 (XMC4_PORT2_BASE+XMC4_PORT_IOCR0_OFFSET) +#define XMC4_PORT2_IOCR4 (XMC4_PORT2_BASE+XMC4_PORT_IOCR4_OFFSET) +#define XMC4_PORT2_IOCR8 (XMC4_PORT2_BASE+XMC4_PORT_IOCR8_OFFSET) +#define XMC4_PORT2_IOCR12 (XMC4_PORT2_BASE+XMC4_PORT_IOCR12_OFFSET) +#define XMC4_PORT2_IN (XMC4_PORT2_BASE+XMC4_PORT_IN_OFFSET) +#define XMC4_PORT2_PDR0 (XMC4_PORT2_BASE+XMC4_PORT_PDR0_OFFSET) +#define XMC4_PORT2_PDR1 (XMC4_PORT2_BASE+XMC4_PORT_PDR1_OFFSET) +#define XMC4_PORT2_PDISC (XMC4_PORT2_BASE+XMC4_PORT_PDISC_OFFSET) +#define XMC4_PORT2_PPS (XMC4_PORT2_BASE+XMC4_PORT_PPS_OFFSET) +#define XMC4_PORT2_HWSEL (XMC4_PORT2_BASE+XMC4_PORT_HWSEL_OFFSET) -#define XMC4_PORT3_OUT (XMC4_PORT3_BASE+XMC4_PORTS_OUT_OFFSET) -#define XMC4_PORT3_OMR (XMC4_PORT3_BASE+XMC4_PORTS_OMR_OFFSET) -#define XMC4_PORT3_IOCR0 (XMC4_PORT3_BASE+XMC4_PORTS_IOCR0_OFFSET) -#define XMC4_PORT3_IOCR4 (XMC4_PORT3_BASE+XMC4_PORTS_IOCR4_OFFSET) -#define XMC4_PORT3_IOCR8 (XMC4_PORT3_BASE+XMC4_PORTS_IOCR8_OFFSET) -#define XMC4_PORT3_IOCR12 (XMC4_PORT3_BASE+XMC4_PORTS_IOCR12_OFFSET) -#define XMC4_PORT3_IN (XMC4_PORT3_BASE+XMC4_PORTS_IN_OFFSET) -#define XMC4_PORT3_PDR0 (XMC4_PORT3_BASE+XMC4_PORTS_PDR0_OFFSET) -#define XMC4_PORT3_PDR1 (XMC4_PORT3_BASE+XMC4_PORTS_PDR1_OFFSET) -#define XMC4_PORT3_PDISC (XMC4_PORT3_BASE+XMC4_PORTS_PDISC_OFFSET) -#define XMC4_PORT3_PPS (XMC4_PORT3_BASE+XMC4_PORTS_PPS_OFFSET) -#define XMC4_PORT3_HWSEL (XMC4_PORT3_BASE+XMC4_PORTS_HWSEL_OFFSET) +#define XMC4_PORT3_OUT (XMC4_PORT3_BASE+XMC4_PORT_OUT_OFFSET) +#define XMC4_PORT3_OMR (XMC4_PORT3_BASE+XMC4_PORT_OMR_OFFSET) +#define XMC4_PORT3_IOCR0 (XMC4_PORT3_BASE+XMC4_PORT_IOCR0_OFFSET) +#define XMC4_PORT3_IOCR4 (XMC4_PORT3_BASE+XMC4_PORT_IOCR4_OFFSET) +#define XMC4_PORT3_IOCR8 (XMC4_PORT3_BASE+XMC4_PORT_IOCR8_OFFSET) +#define XMC4_PORT3_IOCR12 (XMC4_PORT3_BASE+XMC4_PORT_IOCR12_OFFSET) +#define XMC4_PORT3_IN (XMC4_PORT3_BASE+XMC4_PORT_IN_OFFSET) +#define XMC4_PORT3_PDR0 (XMC4_PORT3_BASE+XMC4_PORT_PDR0_OFFSET) +#define XMC4_PORT3_PDR1 (XMC4_PORT3_BASE+XMC4_PORT_PDR1_OFFSET) +#define XMC4_PORT3_PDISC (XMC4_PORT3_BASE+XMC4_PORT_PDISC_OFFSET) +#define XMC4_PORT3_PPS (XMC4_PORT3_BASE+XMC4_PORT_PPS_OFFSET) +#define XMC4_PORT3_HWSEL (XMC4_PORT3_BASE+XMC4_PORT_HWSEL_OFFSET) -#define XMC4_PORT4_OUT (XMC4_PORT4_BASE+XMC4_PORTS_OUT_OFFSET) -#define XMC4_PORT4_OMR (XMC4_PORT4_BASE+XMC4_PORTS_OMR_OFFSET) -#define XMC4_PORT4_IOCR0 (XMC4_PORT4_BASE+XMC4_PORTS_IOCR0_OFFSET) -#define XMC4_PORT4_IOCR4 (XMC4_PORT4_BASE+XMC4_PORTS_IOCR4_OFFSET) -#define XMC4_PORT4_IOCR8 (XMC4_PORT4_BASE+XMC4_PORTS_IOCR8_OFFSET) -#define XMC4_PORT4_IOCR12 (XMC4_PORT4_BASE+XMC4_PORTS_IOCR12_OFFSET) -#define XMC4_PORT4_IN (XMC4_PORT4_BASE+XMC4_PORTS_IN_OFFSET) -#define XMC4_PORT4_PDR0 (XMC4_PORT4_BASE+XMC4_PORTS_PDR0_OFFSET) -#define XMC4_PORT4_PDR1 (XMC4_PORT4_BASE+XMC4_PORTS_PDR1_OFFSET) -#define XMC4_PORT4_PDISC (XMC4_PORT4_BASE+XMC4_PORTS_PDISC_OFFSET) -#define XMC4_PORT4_PPS (XMC4_PORT4_BASE+XMC4_PORTS_PPS_OFFSET) -#define XMC4_PORT4_HWSEL (XMC4_PORT4_BASE+XMC4_PORTS_HWSEL_OFFSET) +#define XMC4_PORT4_OUT (XMC4_PORT4_BASE+XMC4_PORT_OUT_OFFSET) +#define XMC4_PORT4_OMR (XMC4_PORT4_BASE+XMC4_PORT_OMR_OFFSET) +#define XMC4_PORT4_IOCR0 (XMC4_PORT4_BASE+XMC4_PORT_IOCR0_OFFSET) +#define XMC4_PORT4_IOCR4 (XMC4_PORT4_BASE+XMC4_PORT_IOCR4_OFFSET) +#define XMC4_PORT4_IOCR8 (XMC4_PORT4_BASE+XMC4_PORT_IOCR8_OFFSET) +#define XMC4_PORT4_IOCR12 (XMC4_PORT4_BASE+XMC4_PORT_IOCR12_OFFSET) +#define XMC4_PORT4_IN (XMC4_PORT4_BASE+XMC4_PORT_IN_OFFSET) +#define XMC4_PORT4_PDR0 (XMC4_PORT4_BASE+XMC4_PORT_PDR0_OFFSET) +#define XMC4_PORT4_PDR1 (XMC4_PORT4_BASE+XMC4_PORT_PDR1_OFFSET) +#define XMC4_PORT4_PDISC (XMC4_PORT4_BASE+XMC4_PORT_PDISC_OFFSET) +#define XMC4_PORT4_PPS (XMC4_PORT4_BASE+XMC4_PORT_PPS_OFFSET) +#define XMC4_PORT4_HWSEL (XMC4_PORT4_BASE+XMC4_PORT_HWSEL_OFFSET) -#define XMC4_PORT5_OUT (XMC4_PORT5_BASE+XMC4_PORTS_OUT_OFFSET) -#define XMC4_PORT5_OMR (XMC4_PORT5_BASE+XMC4_PORTS_OMR_OFFSET) -#define XMC4_PORT5_IOCR0 (XMC4_PORT5_BASE+XMC4_PORTS_IOCR0_OFFSET) -#define XMC4_PORT5_IOCR4 (XMC4_PORT5_BASE+XMC4_PORTS_IOCR4_OFFSET) -#define XMC4_PORT5_IOCR8 (XMC4_PORT5_BASE+XMC4_PORTS_IOCR8_OFFSET) -#define XMC4_PORT5_IOCR12 (XMC4_PORT5_BASE+XMC4_PORTS_IOCR12_OFFSET) -#define XMC4_PORT5_IN (XMC4_PORT5_BASE+XMC4_PORTS_IN_OFFSET) -#define XMC4_PORT5_PDR0 (XMC4_PORT5_BASE+XMC4_PORTS_PDR0_OFFSET) -#define XMC4_PORT5_PDR1 (XMC4_PORT5_BASE+XMC4_PORTS_PDR1_OFFSET) -#define XMC4_PORT5_PDISC (XMC4_PORT5_BASE+XMC4_PORTS_PDISC_OFFSET) -#define XMC4_PORT5_PPS (XMC4_PORT5_BASE+XMC4_PORTS_PPS_OFFSET) -#define XMC4_PORT5_HWSEL (XMC4_PORT5_BASE+XMC4_PORTS_HWSEL_OFFSET) +#define XMC4_PORT5_OUT (XMC4_PORT5_BASE+XMC4_PORT_OUT_OFFSET) +#define XMC4_PORT5_OMR (XMC4_PORT5_BASE+XMC4_PORT_OMR_OFFSET) +#define XMC4_PORT5_IOCR0 (XMC4_PORT5_BASE+XMC4_PORT_IOCR0_OFFSET) +#define XMC4_PORT5_IOCR4 (XMC4_PORT5_BASE+XMC4_PORT_IOCR4_OFFSET) +#define XMC4_PORT5_IOCR8 (XMC4_PORT5_BASE+XMC4_PORT_IOCR8_OFFSET) +#define XMC4_PORT5_IOCR12 (XMC4_PORT5_BASE+XMC4_PORT_IOCR12_OFFSET) +#define XMC4_PORT5_IN (XMC4_PORT5_BASE+XMC4_PORT_IN_OFFSET) +#define XMC4_PORT5_PDR0 (XMC4_PORT5_BASE+XMC4_PORT_PDR0_OFFSET) +#define XMC4_PORT5_PDR1 (XMC4_PORT5_BASE+XMC4_PORT_PDR1_OFFSET) +#define XMC4_PORT5_PDISC (XMC4_PORT5_BASE+XMC4_PORT_PDISC_OFFSET) +#define XMC4_PORT5_PPS (XMC4_PORT5_BASE+XMC4_PORT_PPS_OFFSET) +#define XMC4_PORT5_HWSEL (XMC4_PORT5_BASE+XMC4_PORT_HWSEL_OFFSET) -#define XMC4_PORT6_OUT (XMC4_PORT6_BASE+XMC4_PORTS_OUT_OFFSET) -#define XMC4_PORT6_OMR (XMC4_PORT6_BASE+XMC4_PORTS_OMR_OFFSET) -#define XMC4_PORT6_IOCR0 (XMC4_PORT6_BASE+XMC4_PORTS_IOCR0_OFFSET) -#define XMC4_PORT6_IOCR4 (XMC4_PORT6_BASE+XMC4_PORTS_IOCR4_OFFSET) -#define XMC4_PORT6_IOCR8 (XMC4_PORT6_BASE+XMC4_PORTS_IOCR8_OFFSET) -#define XMC4_PORT6_IOCR12 (XMC4_PORT6_BASE+XMC4_PORTS_IOCR12_OFFSET) -#define XMC4_PORT6_IN (XMC4_PORT6_BASE+XMC4_PORTS_IN_OFFSET) -#define XMC4_PORT6_PDR0 (XMC4_PORT6_BASE+XMC4_PORTS_PDR0_OFFSET) -#define XMC4_PORT6_PDR1 (XMC4_PORT6_BASE+XMC4_PORTS_PDR1_OFFSET) -#define XMC4_PORT6_PDISC (XMC4_PORT6_BASE+XMC4_PORTS_PDISC_OFFSET) -#define XMC4_PORT6_PPS (XMC4_PORT6_BASE+XMC4_PORTS_PPS_OFFSET) -#define XMC4_PORT6_HWSEL (XMC4_PORT6_BASE+XMC4_PORTS_HWSEL_OFFSET) +#define XMC4_PORT6_OUT (XMC4_PORT6_BASE+XMC4_PORT_OUT_OFFSET) +#define XMC4_PORT6_OMR (XMC4_PORT6_BASE+XMC4_PORT_OMR_OFFSET) +#define XMC4_PORT6_IOCR0 (XMC4_PORT6_BASE+XMC4_PORT_IOCR0_OFFSET) +#define XMC4_PORT6_IOCR4 (XMC4_PORT6_BASE+XMC4_PORT_IOCR4_OFFSET) +#define XMC4_PORT6_IOCR8 (XMC4_PORT6_BASE+XMC4_PORT_IOCR8_OFFSET) +#define XMC4_PORT6_IOCR12 (XMC4_PORT6_BASE+XMC4_PORT_IOCR12_OFFSET) +#define XMC4_PORT6_IN (XMC4_PORT6_BASE+XMC4_PORT_IN_OFFSET) +#define XMC4_PORT6_PDR0 (XMC4_PORT6_BASE+XMC4_PORT_PDR0_OFFSET) +#define XMC4_PORT6_PDR1 (XMC4_PORT6_BASE+XMC4_PORT_PDR1_OFFSET) +#define XMC4_PORT6_PDISC (XMC4_PORT6_BASE+XMC4_PORT_PDISC_OFFSET) +#define XMC4_PORT6_PPS (XMC4_PORT6_BASE+XMC4_PORT_PPS_OFFSET) +#define XMC4_PORT6_HWSEL (XMC4_PORT6_BASE+XMC4_PORT_HWSEL_OFFSET) -#define XMC4_PORT7_OUT (XMC4_PORT7_BASE+XMC4_PORTS_OUT_OFFSET) -#define XMC4_PORT7_OMR (XMC4_PORT7_BASE+XMC4_PORTS_OMR_OFFSET) -#define XMC4_PORT7_IOCR0 (XMC4_PORT7_BASE+XMC4_PORTS_IOCR0_OFFSET) -#define XMC4_PORT7_IOCR4 (XMC4_PORT7_BASE+XMC4_PORTS_IOCR4_OFFSET) -#define XMC4_PORT7_IOCR8 (XMC4_PORT7_BASE+XMC4_PORTS_IOCR8_OFFSET) -#define XMC4_PORT7_IOCR12 (XMC4_PORT7_BASE+XMC4_PORTS_IOCR12_OFFSET) -#define XMC4_PORT7_IN (XMC4_PORT7_BASE+XMC4_PORTS_IN_OFFSET) -#define XMC4_PORT7_PDR0 (XMC4_PORT7_BASE+XMC4_PORTS_PDR0_OFFSET) -#define XMC4_PORT7_PDR1 (XMC4_PORT7_BASE+XMC4_PORTS_PDR1_OFFSET) -#define XMC4_PORT7_PDISC (XMC4_PORT7_BASE+XMC4_PORTS_PDISC_OFFSET) -#define XMC4_PORT7_PPS (XMC4_PORT7_BASE+XMC4_PORTS_PPS_OFFSET) -#define XMC4_PORT7_HWSEL (XMC4_PORT7_BASE+XMC4_PORTS_HWSEL_OFFSET) +#define XMC4_PORT7_OUT (XMC4_PORT7_BASE+XMC4_PORT_OUT_OFFSET) +#define XMC4_PORT7_OMR (XMC4_PORT7_BASE+XMC4_PORT_OMR_OFFSET) +#define XMC4_PORT7_IOCR0 (XMC4_PORT7_BASE+XMC4_PORT_IOCR0_OFFSET) +#define XMC4_PORT7_IOCR4 (XMC4_PORT7_BASE+XMC4_PORT_IOCR4_OFFSET) +#define XMC4_PORT7_IOCR8 (XMC4_PORT7_BASE+XMC4_PORT_IOCR8_OFFSET) +#define XMC4_PORT7_IOCR12 (XMC4_PORT7_BASE+XMC4_PORT_IOCR12_OFFSET) +#define XMC4_PORT7_IN (XMC4_PORT7_BASE+XMC4_PORT_IN_OFFSET) +#define XMC4_PORT7_PDR0 (XMC4_PORT7_BASE+XMC4_PORT_PDR0_OFFSET) +#define XMC4_PORT7_PDR1 (XMC4_PORT7_BASE+XMC4_PORT_PDR1_OFFSET) +#define XMC4_PORT7_PDISC (XMC4_PORT7_BASE+XMC4_PORT_PDISC_OFFSET) +#define XMC4_PORT7_PPS (XMC4_PORT7_BASE+XMC4_PORT_PPS_OFFSET) +#define XMC4_PORT7_HWSEL (XMC4_PORT7_BASE+XMC4_PORT_HWSEL_OFFSET) -#define XMC4_PORT8_OUT (XMC4_PORT8_BASE+XMC4_PORTS_OUT_OFFSET) -#define XMC4_PORT8_OMR (XMC4_PORT8_BASE+XMC4_PORTS_OMR_OFFSET) -#define XMC4_PORT8_IOCR0 (XMC4_PORT8_BASE+XMC4_PORTS_IOCR0_OFFSET) -#define XMC4_PORT8_IOCR4 (XMC4_PORT8_BASE+XMC4_PORTS_IOCR4_OFFSET) -#define XMC4_PORT8_IOCR8 (XMC4_PORT8_BASE+XMC4_PORTS_IOCR8_OFFSET) -#define XMC4_PORT8_IOCR12 (XMC4_PORT8_BASE+XMC4_PORTS_IOCR12_OFFSET) -#define XMC4_PORT8_IN (XMC4_PORT8_BASE+XMC4_PORTS_IN_OFFSET) -#define XMC4_PORT8_PDR0 (XMC4_PORT8_BASE+XMC4_PORTS_PDR0_OFFSET) -#define XMC4_PORT8_PDR1 (XMC4_PORT8_BASE+XMC4_PORTS_PDR1_OFFSET) -#define XMC4_PORT8_PDISC (XMC4_PORT8_BASE+XMC4_PORTS_PDISC_OFFSET) -#define XMC4_PORT8_PPS (XMC4_PORT8_BASE+XMC4_PORTS_PPS_OFFSET) -#define XMC4_PORT8_HWSEL (XMC4_PORT8_BASE+XMC4_PORTS_HWSEL_OFFSET) +#define XMC4_PORT8_OUT (XMC4_PORT8_BASE+XMC4_PORT_OUT_OFFSET) +#define XMC4_PORT8_OMR (XMC4_PORT8_BASE+XMC4_PORT_OMR_OFFSET) +#define XMC4_PORT8_IOCR0 (XMC4_PORT8_BASE+XMC4_PORT_IOCR0_OFFSET) +#define XMC4_PORT8_IOCR4 (XMC4_PORT8_BASE+XMC4_PORT_IOCR4_OFFSET) +#define XMC4_PORT8_IOCR8 (XMC4_PORT8_BASE+XMC4_PORT_IOCR8_OFFSET) +#define XMC4_PORT8_IOCR12 (XMC4_PORT8_BASE+XMC4_PORT_IOCR12_OFFSET) +#define XMC4_PORT8_IN (XMC4_PORT8_BASE+XMC4_PORT_IN_OFFSET) +#define XMC4_PORT8_PDR0 (XMC4_PORT8_BASE+XMC4_PORT_PDR0_OFFSET) +#define XMC4_PORT8_PDR1 (XMC4_PORT8_BASE+XMC4_PORT_PDR1_OFFSET) +#define XMC4_PORT8_PDISC (XMC4_PORT8_BASE+XMC4_PORT_PDISC_OFFSET) +#define XMC4_PORT8_PPS (XMC4_PORT8_BASE+XMC4_PORT_PPS_OFFSET) +#define XMC4_PORT8_HWSEL (XMC4_PORT8_BASE+XMC4_PORT_HWSEL_OFFSET) -#define XMC4_PORT9_OUT (XMC4_PORT9_BASE+XMC4_PORTS_OUT_OFFSET) -#define XMC4_PORT9_OMR (XMC4_PORT9_BASE+XMC4_PORTS_OMR_OFFSET) -#define XMC4_PORT9_IOCR0 (XMC4_PORT9_BASE+XMC4_PORTS_IOCR0_OFFSET) -#define XMC4_PORT9_IOCR4 (XMC4_PORT9_BASE+XMC4_PORTS_IOCR4_OFFSET) -#define XMC4_PORT9_IOCR8 (XMC4_PORT9_BASE+XMC4_PORTS_IOCR8_OFFSET) -#define XMC4_PORT9_IOCR12 (XMC4_PORT9_BASE+XMC4_PORTS_IOCR12_OFFSET) -#define XMC4_PORT9_IN (XMC4_PORT9_BASE+XMC4_PORTS_IN_OFFSET) -#define XMC4_PORT9_PDR0 (XMC4_PORT9_BASE+XMC4_PORTS_PDR0_OFFSET) -#define XMC4_PORT9_PDR1 (XMC4_PORT9_BASE+XMC4_PORTS_PDR1_OFFSET) -#define XMC4_PORT9_PDISC (XMC4_PORT9_BASE+XMC4_PORTS_PDISC_OFFSET) -#define XMC4_PORT9_PPS (XMC4_PORT9_BASE+XMC4_PORTS_PPS_OFFSET) -#define XMC4_PORT9_HWSEL (XMC4_PORT9_BASE+XMC4_PORTS_HWSEL_OFFSET) +#define XMC4_PORT9_OUT (XMC4_PORT9_BASE+XMC4_PORT_OUT_OFFSET) +#define XMC4_PORT9_OMR (XMC4_PORT9_BASE+XMC4_PORT_OMR_OFFSET) +#define XMC4_PORT9_IOCR0 (XMC4_PORT9_BASE+XMC4_PORT_IOCR0_OFFSET) +#define XMC4_PORT9_IOCR4 (XMC4_PORT9_BASE+XMC4_PORT_IOCR4_OFFSET) +#define XMC4_PORT9_IOCR8 (XMC4_PORT9_BASE+XMC4_PORT_IOCR8_OFFSET) +#define XMC4_PORT9_IOCR12 (XMC4_PORT9_BASE+XMC4_PORT_IOCR12_OFFSET) +#define XMC4_PORT9_IN (XMC4_PORT9_BASE+XMC4_PORT_IN_OFFSET) +#define XMC4_PORT9_PDR0 (XMC4_PORT9_BASE+XMC4_PORT_PDR0_OFFSET) +#define XMC4_PORT9_PDR1 (XMC4_PORT9_BASE+XMC4_PORT_PDR1_OFFSET) +#define XMC4_PORT9_PDISC (XMC4_PORT9_BASE+XMC4_PORT_PDISC_OFFSET) +#define XMC4_PORT9_PPS (XMC4_PORT9_BASE+XMC4_PORT_PPS_OFFSET) +#define XMC4_PORT9_HWSEL (XMC4_PORT9_BASE+XMC4_PORT_HWSEL_OFFSET) -#define XMC4_PORT14_OUT (XMC4_PORT14_BASE+XMC4_PORTS_OUT_OFFSET) -#define XMC4_PORT14_OMR (XMC4_PORT14_BASE+XMC4_PORTS_OMR_OFFSET) -#define XMC4_PORT14_IOCR0 (XMC4_PORT14_BASE+XMC4_PORTS_IOCR0_OFFSET) -#define XMC4_PORT14_IOCR4 (XMC4_PORT14_BASE+XMC4_PORTS_IOCR4_OFFSET) -#define XMC4_PORT14_IOCR8 (XMC4_PORT14_BASE+XMC4_PORTS_IOCR8_OFFSET) -#define XMC4_PORT14_IOCR12 (XMC4_PORT14_BASE+XMC4_PORTS_IOCR12_OFFSET) -#define XMC4_PORT14_IN (XMC4_PORT14_BASE+XMC4_PORTS_IN_OFFSET) -#define XMC4_PORT14_PDR0 (XMC4_PORT14_BASE+XMC4_PORTS_PDR0_OFFSET) -#define XMC4_PORT14_PDR1 (XMC4_PORT14_BASE+XMC4_PORTS_PDR1_OFFSET) -#define XMC4_PORT14_PDISC (XMC4_PORT14_BASE+XMC4_PORTS_PDISC_OFFSET) -#define XMC4_PORT14_PPS (XMC4_PORT14_BASE+XMC4_PORTS_PPS_OFFSET) -#define XMC4_PORT14_HWSEL (XMC4_PORT14_BASE+XMC4_PORTS_HWSEL_OFFSET) +#define XMC4_PORT14_OUT (XMC4_PORT14_BASE+XMC4_PORT_OUT_OFFSET) +#define XMC4_PORT14_OMR (XMC4_PORT14_BASE+XMC4_PORT_OMR_OFFSET) +#define XMC4_PORT14_IOCR0 (XMC4_PORT14_BASE+XMC4_PORT_IOCR0_OFFSET) +#define XMC4_PORT14_IOCR4 (XMC4_PORT14_BASE+XMC4_PORT_IOCR4_OFFSET) +#define XMC4_PORT14_IOCR8 (XMC4_PORT14_BASE+XMC4_PORT_IOCR8_OFFSET) +#define XMC4_PORT14_IOCR12 (XMC4_PORT14_BASE+XMC4_PORT_IOCR12_OFFSET) +#define XMC4_PORT14_IN (XMC4_PORT14_BASE+XMC4_PORT_IN_OFFSET) +#define XMC4_PORT14_PDR0 (XMC4_PORT14_BASE+XMC4_PORT_PDR0_OFFSET) +#define XMC4_PORT14_PDR1 (XMC4_PORT14_BASE+XMC4_PORT_PDR1_OFFSET) +#define XMC4_PORT14_PDISC (XMC4_PORT14_BASE+XMC4_PORT_PDISC_OFFSET) +#define XMC4_PORT14_PPS (XMC4_PORT14_BASE+XMC4_PORT_PPS_OFFSET) +#define XMC4_PORT14_HWSEL (XMC4_PORT14_BASE+XMC4_PORT_HWSEL_OFFSET) -#define XMC4_PORT15_OUT (XMC4_PORT15_BASE+XMC4_PORTS_OUT_OFFSET) -#define XMC4_PORT15_OMR (XMC4_PORT15_BASE+XMC4_PORTS_OMR_OFFSET) -#define XMC4_PORT15_IOCR0 (XMC4_PORT15_BASE+XMC4_PORTS_IOCR0_OFFSET) -#define XMC4_PORT15_IOCR4 (XMC4_PORT15_BASE+XMC4_PORTS_IOCR4_OFFSET) -#define XMC4_PORT15_IOCR8 (XMC4_PORT15_BASE+XMC4_PORTS_IOCR8_OFFSET) -#define XMC4_PORT15_IOCR12 (XMC4_PORT15_BASE+XMC4_PORTS_IOCR12_OFFSET) -#define XMC4_PORT15_IN (XMC4_PORT15_BASE+XMC4_PORTS_IN_OFFSET) -#define XMC4_PORT15_PDR0 (XMC4_PORT15_BASE+XMC4_PORTS_PDR0_OFFSET) -#define XMC4_PORT15_PDR1 (XMC4_PORT15_BASE+XMC4_PORTS_PDR1_OFFSET) -#define XMC4_PORT15_PDISC (XMC4_PORT15_BASE+XMC4_PORTS_PDISC_OFFSET) -#define XMC4_PORT15_PPS (XMC4_PORT15_BASE+XMC4_PORTS_PPS_OFFSET) -#define XMC4_PORT15_HWSEL (XMC4_PORT15_BASE+XMC4_PORTS_HWSEL_OFFSET) +#define XMC4_PORT15_OUT (XMC4_PORT15_BASE+XMC4_PORT_OUT_OFFSET) +#define XMC4_PORT15_OMR (XMC4_PORT15_BASE+XMC4_PORT_OMR_OFFSET) +#define XMC4_PORT15_IOCR0 (XMC4_PORT15_BASE+XMC4_PORT_IOCR0_OFFSET) +#define XMC4_PORT15_IOCR4 (XMC4_PORT15_BASE+XMC4_PORT_IOCR4_OFFSET) +#define XMC4_PORT15_IOCR8 (XMC4_PORT15_BASE+XMC4_PORT_IOCR8_OFFSET) +#define XMC4_PORT15_IOCR12 (XMC4_PORT15_BASE+XMC4_PORT_IOCR12_OFFSET) +#define XMC4_PORT15_IN (XMC4_PORT15_BASE+XMC4_PORT_IN_OFFSET) +#define XMC4_PORT15_PDR0 (XMC4_PORT15_BASE+XMC4_PORT_PDR0_OFFSET) +#define XMC4_PORT15_PDR1 (XMC4_PORT15_BASE+XMC4_PORT_PDR1_OFFSET) +#define XMC4_PORT15_PDISC (XMC4_PORT15_BASE+XMC4_PORT_PDISC_OFFSET) +#define XMC4_PORT15_PPS (XMC4_PORT15_BASE+XMC4_PORT_PPS_OFFSET) +#define XMC4_PORT15_HWSEL (XMC4_PORT15_BASE+XMC4_PORT_HWSEL_OFFSET) /* Register Bit-Field Definitions **************************************************/ -/* Port Output Register */ -#define PORTS_OUT_ -/* Port Output Modification Register */ -#define PORTS_OMR_ +/* Port Output Register, Port Output Modification Register, Port Input Register, + * Port Pin Function Decision Control Register, Port Pin Power Save Register. + */ + +#define PORT_PIN(n) (1 << (n)) + +/* Basic port input/output field values */ +/* Director Input */ + +#define IOCR_NOPULL 0 /* No internal pull device active */ +#define IOCR_PULLDOWN 1 /* Internal pull-down device active */ +#define IOCR_PULLUP 2 /* Internal pull-down device active */ +#define IOCR_CONT 3 /* No internal pull device active; Pn_OUTx continuously + * samples the input value */ + +/* Any of the above may be OR'ed with */ +/* Inverted Input */ + +#define IOCR_INVERT 4 /* Inverted input */ + /* Port Input/Output Control Register 0 */ -#define PORTS_IOCR0_ + +#define PORT_IOCR0_PC_SHIFT(p) (((p) << 3) + 3) +#define PORT_IOCR0_PC_MASK(p) (31 << PORT_IOCR0_PC_SHIFT(p)) +# define PORT_IOCR0_PC(p,n) ((uint32_t)(n) << PORT_IOCR0_PC_SHIFT(p)) +#define PORT_IOCR0_PC0_SHIFT (3) /* Bit 3-7: Port Control for Port n Pin 0 */ +#define PORT_IOCR0_PC0_MASK (31 << PORT_IOCR0_PC0_SHIFT) +# define PORT_IOCR0_PC0(n) ((uint32_t)(n) << PORT_IOCR0_PC0_SHIFT) +#define PORT_IOCR0_PC1_SHIFT (11) /* Bit 11-15: Port Control for Port n Pin 1 */ +#define PORT_IOCR0_PC1_MASK (31 << PORT_IOCR0_PC1_SHIFT) +# define PORT_IOCR0_PC1(n) ((uint32_t)(n) << PORT_IOCR0_PC1_SHIFT) +#define PORT_IOCR0_PC2_SHIFT (19) /* Bit 19-23: Port Control for Port n Pin 2 */ +#define PORT_IOCR0_PC2_MASK (31 << PORT_IOCR0_PC2_SHIFT) +# define PORT_IOCR0_PC2(n) ((uint32_t)(n) << PORT_IOCR0_PC2_SHIFT) +#define PORT_IOCR0_PC3_SHIFT (27) /* Bit 27-31: Port Control for Port 0 Pin 3 */ +#define PORT_IOCR0_PC3_MASK (31 << PORT_IOCR0_PC3_SHIFT) +# define PORT_IOCR0_PC3(n) ((uint32_t)(n) << PORT_IOCR0_PC3_SHIFT) + /* Port Input/Output Control Register 4 */ -#define PORTS_IOCR4_ + +#define PORT_IOCR4_PC_SHIFT(p) ((((p) - 4) << 3) + 3) +#define PORT_IOCR4_PC_MASK(p) (31 << PORT_IOCR4_PC_SHIFT(p)) +# define PORT_IOCR4_PC(p,n) ((uint32_t)(n) << PORT_IOCR4_PC_SHIFT(p)) +#define PORT_IOCR4_PC4_SHIFT (3) /* Bit 3-7: Port Control for Port n Pin 4 */ +#define PORT_IOCR4_PC4_MASK (31 << PORT_IOCR4_PC4_SHIFT) +# define PORT_IOCR4_PC4(n) ((uint32_t)(n) << PORT_IOCR4_PC4_SHIFT) +#define PORT_IOCR4_PC5_SHIFT (11) /* Bit 11-15: Port Control for Port n Pin 5 */ +#define PORT_IOCR4_PC5_MASK (31 << PORT_IOCR4_PC5_SHIFT) +# define PORT_IOCR4_PC5(n) ((uint32_t)(n) << PORT_IOCR4_PC5_SHIFT) +#define PORT_IOCR4_PC6_SHIFT (19) /* Bit 19-23: Port Control for Port n Pin 6 */ +#define PORT_IOCR4_PC6_MASK (31 << PORT_IOCR4_PC6_SHIFT) +# define PORT_IOCR4_PC6(n) ((uint32_t)(n) << PORT_IOCR4_PC6_SHIFT) +#define PORT_IOCR4_PC7_SHIFT (27) /* Bit 27-31: Port Control for Port 0 Pin 7 */ +#define PORT_IOCR4_PC7_MASK (31 << PORT_IOCR4_PC7_SHIFT) +# define PORT_IOCR4_PC7(n) ((uint32_t)(n) << PORT_IOCR4_PC7_SHIFT) + /* Port Input/Output Control Register 8 */ -#define PORTS_IOCR8_ + +#define PORT_IOCR8_PC_SHIFT(p) ((((p) - 8) << 3) + 3) +#define PORT_IOCR8_PC_MASK(p) (31 << PORT_IOCR8_PC_SHIFT(p)) +# define PORT_IOCR8_PC(p,n) ((uint32_t)(n) << PORT_IOCR8_PC_SHIFT(p)) +#define PORT_IOCR8_PC8_SHIFT (3) /* Bit 3-7: Port Control for Port n Pin 8 */ +#define PORT_IOCR8_PC8_MASK (31 << PORT_IOCR8_PC8_SHIFT) +# define PORT_IOCR8_PC8(n) ((uint32_t)(n) << PORT_IOCR8_PC8_SHIFT) +#define PORT_IOCR8_PC9_SHIFT (11) /* Bit 11-15: Port Control for Port n Pin 9 */ +#define PORT_IOCR8_PC9_MASK (31 << PORT_IOCR8_PC9_SHIFT) +# define PORT_IOCR8_PC9(n) ((uint32_t)(n) << PORT_IOCR8_PC9_SHIFT) +#define PORT_IOCR8_PC10_SHIFT (19) /* Bit 19-23: Port Control for Port n Pin 10 */ +#define PORT_IOCR8_PC10_MASK (31 << PORT_IOCR8_PC10_SHIFT) +# define PORT_IOCR8_PC10(n) ((uint32_t)(n) << PORT_IOCR8_PC10_SHIFT) +#define PORT_IOCR8_PC11_SHIFT (27) /* Bit 17-31: Port Control for Port 0 Pin 11 */ +#define PORT_IOCR8_PC11_MASK (31 << PORT_IOCR8_PC11_SHIFT) +# define PORT_IOCR8_PC11(n) ((uint32_t)(n) << PORT_IOCR8_PC11_SHIFT) + /* Port Input/Output Control Register 12 */ -#define PORTS_IOCR12_ -/* Port Input Register */ -#define PORTS_IN_ + +#define PORT_IOCR12_PC_SHIFT(p) ((((p) - 12) << 3) + 3) +#define PORT_IOCR12_PC_MASK(p) (31 << PORT_IOCR12_PC_SHIFT(p)) +# define PORT_IOCR12_PC(p,n) ((uint32_t)(n) << PORT_IOCR12_PC_SHIFT(p)) +#define PORT_IOCR12_PC12_SHIFT (3) /* Bit 3-7: Port Control for Port n Pin 12 */ +#define PORT_IOCR12_PC12_MASK (31 << PORT_IOCR12_PC12_SHIFT) +# define PORT_IOCR12_PC12(n) ((uint32_t)(n) << PORT_IOCR12_PC12_SHIFT) +#define PORT_IOCR12_PC13_SHIFT (11) /* Bit 3-7: Port Control for Port n Pin 13 */ +#define PORT_IOCR12_PC13_MASK (31 << PORT_IOCR12_PC13_SHIFT) +# define PORT_IOCR12_PC13(n) ((uint32_t)(n) << PORT_IOCR12_PC13_SHIFT) +#define PORT_IOCR12_PC14_SHIFT (19) /* Bit 3-7: Port Control for Port n Pin 14 */ +#define PORT_IOCR12_PC14_MASK (31 << PORT_IOCR12_PC14_SHIFT) +# define PORT_IOCR12_PC14(n) ((uint32_t)(n) << PORT_IOCR12_PC14_SHIFT) +#define PORT_IOCR12_PC15_SHIFT (27) /* Bit 3-7: Port Control for Port 0 Pin 15 */ +#define PORT_IOCR12_PC15_MASK (31 << PORT_IOCR12_PC15_SHIFT) +# define PORT_IOCR12_PC15(n) ((uint32_t)(n) << PORT_IOCR12_PC15_SHIFT) + +/* Pad driver field values */ +/* Pad class A1: */ + +#define PDR_PADA1_MEDIUM 0 /* Medium driver */ +#define PDR_PADA1_WEAK 1 /* Weak driver */ + +/* Pad class A1+: */ + +#define PDR_PADA1P_STRONGSOFT 0 /* Strong driver soft edge */ +#define PDR_PADA1P_STRONGSLOW 1 /* Strong driver slow edge */ +#define PDR_PADA1P_MEDIUM 4 /* Medium driver */ +#define PDR_PADA1P_WEAK 5 /* Weak driver */ + +/* Pad class A2: */ + +#define PDR_PADA2_STRONGSHARP 0 /* Strong driver sharp edge */ +#define PDR_PADA2_STRONGMEDIUM 1 /* Strong driver medium edge */ +#define PDR_PADA2_STRONGSOFT 2 /* Strong driver soft edge */ +#define PDR_PADA2_MEDIUM 4 /* Medium driver */ +#define PDR_PADA2_WEAK 7 /* Weak driver */ + /* Port Pad Driver Mode 0 Register */ -#define PORTS_PDR0_ + +#define PORT_PDR0_PD_SHIFT(p) ((p) << 2) +#define PORT_PDR0_PD_MASK(p) (7 << PORT_PDR0_PD_SHIFT(p)) +# define PORT_PDR0_PD(p,n) ((uint32_t)(n) << PORT_PDR0_PD_SHIFT(p)) +#define PORT_PDR0_PD0_SHIFT (0) /* Bit 0-2: Pad Driver Mode for Port n Pin 0 */ +#define PORT_PDR0_PD0_MASK (7 << PORT_PDR0_PD0_SHIFT) +# define PORT_PDR0_PD0(n) ((uint32_t)(n) << PORT_PDR0_PD0_SHIFT) +#define PORT_PDR0_PD1_SHIFT (4) /* Bit 4-6: Pad Driver Mode for Port n Pin 1 */ +#define PORT_PDR0_PD1_MASK (7 << PORT_PDR0_PD1_SHIFT) +# define PORT_PDR0_PD1(n) ((uint32_t)(n) << PORT_PDR0_PD1_SHIFT) +#define PORT_PDR0_PD2_SHIFT (8) /* Bit 8-10: Pad Driver Mode for Port n Pin 2 */ +#define PORT_PDR0_PD2_MASK (7 << PORT_PDR0_PD2_SHIFT) +# define PORT_PDR0_PD2(n) ((uint32_t)(n) << PORT_PDR0_PD2_SHIFT) +#define PORT_PDR0_PD3_SHIFT (12) /* Bit 12-14: Pad Driver Mode for Port 0 Pin 3 */ +#define PORT_PDR0_PD3_MASK (7 << PORT_PDR0_PD3_SHIFT) +# define PORT_PDR0_PD3(n) ((uint32_t)(n) << PORT_PDR0_PD3_SHIFT) +#define PORT_PDR0_PD4_SHIFT (16) /* Bit 16-18: Pad Driver Mode for Port 0 Pin 4 */ +#define PORT_PDR0_PD4_MASK (7 << PORT_PDR0_PD4_SHIFT) +# define PORT_PDR0_PD4(n) ((uint32_t)(n) << PORT_PDR0_PD4_SHIFT) +#define PORT_PDR0_PD5_SHIFT (20) /* Bit 20-22: Pad Driver Mode for Port 0 Pin 5 */ +#define PORT_PDR0_PD5_MASK (7 << PORT_PDR0_PD5_SHIFT) +# define PORT_PDR0_PD5(n) ((uint32_t)(n) << PORT_PDR0_PD5_SHIFT) +#define PORT_PDR0_PD6_SHIFT (24) /* Bit 24-26: Pad Driver Mode for Port 0 Pin 6 */ +#define PORT_PDR0_PD6_MASK (7 << PORT_PDR0_PD6_SHIFT) +# define PORT_PDR0_PD6(n) ((uint32_t)(n) << PORT_PDR0_PD6_SHIFT) +#define PORT_PDR0_PD7_SHIFT (28) /* Bit 28-30: Pad Driver Mode for Port 0 Pin 7 */ +#define PORT_PDR0_PD7_MASK (7 << PORT_PDR0_PD7_SHIFT) +# define PORT_PDR0_PD7(n) ((uint32_t)(n) << PORT_PDR0_PD7_SHIFT) + /* Port Pad Driver Mode 1 Register */ -#define PORTS_PDR1_ -/* Port Pin Function Decision Control Register */ -#define PORTS_PDISC_ -/* Port Pin Power Save Register */ -#define PORTS_PPS_ + +#define PORT_PDR1_PD_SHIFT(p) (((p) - 8) << 2) +#define PORT_PDR1_PD_MASK(p) (7 << PORT_PDR1_PD_SHIFT(p)) +# define PORT_PDR1_PD(p,n) ((uint32_t)(n) << PORT_PDR1_PD_SHIFT(p)) +#define PORT_PDR1_PD8_SHIFT (0) /* Bit 0-2: Pad Driver Mode for Port n Pin 8 */ +#define PORT_PDR1_PD8_MASK (7 << PORT_PDR1_PD8_SHIFT) +# define PORT_PDR1_PD8(n) ((uint32_t)(n) << PORT_PDR1_PD8_SHIFT) +#define PORT_PDR1_PD9_SHIFT (4) /* Bit 4-6: Pad Driver Mode for Port n Pin 9 */ +#define PORT_PDR1_PD9_MASK (7 << PORT_PDR1_PD9_SHIFT) +# define PORT_PDR1_PD9(n) ((uint32_t)(n) << PORT_PDR1_PD9_SHIFT) +#define PORT_PDR1_PD10_SHIFT (8) /* Bit 8-10: Pad Driver Mode for Port n Pin 10 */ +#define PORT_PDR1_PD10_MASK (7 << PORT_PDR1_PD10_SHIFT) +# define PORT_PDR1_PD10(n) ((uint32_t)(n) << PORT_PDR1_PD10_SHIFT) +#define PORT_PDR1_PD11_SHIFT (12) /* Bit 12-14: Pad Driver Mode for Port 0 Pin 11 */ +#define PORT_PDR1_PD11_MASK (7 << PORT_PDR1_PD11_SHIFT) +# define PORT_PDR1_PD11(n) ((uint32_t)(n) << PORT_PDR1_PD11_SHIFT) +#define PORT_PDR1_PD12_SHIFT (16) /* Bit 16-18: Pad Driver Mode for Port 0 Pin 12 */ +#define PORT_PDR1_PD12_MASK (7 << PORT_PDR1_PD12_SHIFT) +# define PORT_PDR1_PD12(n) ((uint32_t)(n) << PORT_PDR1_PD12_SHIFT) +#define PORT_PDR1_PD13_SHIFT (20) /* Bit 20-22: Pad Driver Mode for Port 0 Pin 13 */ +#define PORT_PDR1_PD13_MASK (7 << PORT_PDR1_PD13_SHIFT) +# define PORT_PDR1_PD13(n) ((uint32_t)(n) << PORT_PDR1_PD13_SHIFT) +#define PORT_PDR1_PD14_SHIFT (24) /* Bit 24-26: Pad Driver Mode for Port 0 Pin 14 */ +#define PORT_PDR1_PD14_MASK (7 << PORT_PDR1_PD14_SHIFT) +# define PORT_PDR1_PD14(n) ((uint32_t)(n) << PORT_PDR1_PD14_SHIFT) +#define PORT_PDR1_PD15_SHIFT (28) /* Bit 28-30: Pad Driver Mode for Port 0 Pin 15 */ +#define PORT_PDR1_PD15_MASK (7 << PORT_PDR1_PD15_SHIFT) +# define PORT_PDR1_PD15(n) ((uint32_t)(n) << PORT_PDR1_PD15_SHIFT) + +/* Hardware select field values */ + +#define HWSEL_SOFTWARE 0 /* Software control only */ +#define HWSEL_OVERRIDE0 1 /* HWI0/HWO0 control path can override the + * software configuration */ +#define HWSEL_OVERRIDE1 2 /* HWI1/HWO1 control path can override the + * software configuration */ + /* Port Pin Hardware Select Register */ -#define PORTS_HWSEL_ + +#define PORT_HWSEL_HW_SHIFT(p) ((p) << 1) +#define PORT_HWSEL_HW_MASK(p) (3 << PORT_HWSEL_HW_SHIFT(p)) +# define PORT_HWSEL_HW(p,n) ((uint32_t)(n) << PORT_HWSEL_HW_SHIFT(p)) +#define PORT_HWSEL_HW0_SHIFT (0) /* Bit 0-1: Port n Pin 0 Hardware Select */ +#define PORT_HWSEL_HW0_MASK (3 << PORT_HWSEL_HW0_SHIFT) +# define PORT_HWSEL_HW0(n) ((uint32_t)(n) << PORT_HWSEL_HW0_SHIFT) +#define PORT_HWSEL_HW1_SHIFT (2) /* Bit 2-3: Port n Pin 1 Hardware Select */ +#define PORT_HWSEL_HW1_MASK (3 << PORT_HWSEL_HW1_SHIFT) +# define PORT_HWSEL_HW1(n) ((uint32_t)(n) << PORT_HWSEL_HW1_SHIFT) +#define PORT_HWSEL_HW2_SHIFT (4) /* Bit 4-5: Port n Pin 2 Hardware Select */ +#define PORT_HWSEL_HW2_MASK (3 << PORT_HWSEL_HW2_SHIFT) +# define PORT_HWSEL_HW2(n) ((uint32_t)(n) << PORT_HWSEL_HW2_SHIFT) +#define PORT_HWSEL_HW3_SHIFT (6) /* Bit 6-7: Port 0 Pin 3 Hardware Select */ +#define PORT_HWSEL_HW3_MASK (3 << PORT_HWSEL_HW3_SHIFT) +# define PORT_HWSEL_HW3(n) ((uint32_t)(n) << PORT_HWSEL_HW3_SHIFT) +#define PORT_HWSEL_HW4_SHIFT (8) /* Bit 8-9: Port 0 Pin 4 Hardware Select */ +#define PORT_HWSEL_HW4_MASK (3 << PORT_HWSEL_HW4_SHIFT) +# define PORT_HWSEL_HW4(n) ((uint32_t)(n) << PORT_HWSEL_HW4_SHIFT) +#define PORT_HWSEL_HW5_SHIFT (10) /* Bit 10-11: Port 0 Pin 5 Hardware Select */ +#define PORT_HWSEL_HW5_MASK (3 << PORT_HWSEL_HW5_SHIFT) +# define PORT_HWSEL_HW5(n) ((uint32_t)(n) << PORT_HWSEL_HW5_SHIFT) +#define PORT_HWSEL_HW6_SHIFT (12) /* Bit 12-13: Port 0 Pin 6 Hardware Select */ +#define PORT_HWSEL_HW6_MASK (3 << PORT_HWSEL_HW6_SHIFT) +# define PORT_HWSEL_HW6(n) 14uint32_t)(n) << PORT_HWSEL_HW6_SHIFT) +#define PORT_HWSEL_HW7_SHIFT (14) /* Bit 14-15: Port 0 Pin 7 Hardware Select */ +#define PORT_HWSEL_HW7_MASK (3 << PORT_HWSEL_HW7_SHIFT) +# define PORT_HWSEL_HW7(n) ((uint32_t)(n) << PORT_HWSEL_HW7_SHIFT) +#define PORT_HWSEL_HW8_SHIFT (16) /* Bit 16-17: Port n Pin 8 Hardware Select */ +#define PORT_HWSEL_HW8_MASK (3 << PORT_HWSEL_HW8_SHIFT) +# define PORT_HWSEL_HW8(n) ((uint32_t)(n) << PORT_HWSEL_HW8_SHIFT) +#define PORT_HWSEL_HW9_SHIFT (18) /* Bit 18-19: Port n Pin 9 Hardware Select */ +#define PORT_HWSEL_HW9_MASK (3 << PORT_HWSEL_HW9_SHIFT) +# define PORT_HWSEL_HW9(n) ((uint32_t)(n) << PORT_HWSEL_HW9_SHIFT) +#define PORT_HWSEL_HW10_SHIFT (20) /* Bit 20-21: Port n Pin 10 Hardware Select */ +#define PORT_HWSEL_HW10_MASK (3 << PORT_HWSEL_HW10_SHIFT) +# define PORT_HWSEL_HW10(n) ((uint32_t)(n) << PORT_HWSEL_HW10_SHIFT) +#define PORT_HWSEL_HW11_SHIFT (22) /* Bit 22-23: Port 0 Pin 11 Hardware Select */ +#define PORT_HWSEL_HW11_MASK (3 << PORT_HWSEL_HW11_SHIFT) +# define PORT_HWSEL_HW11(n) ((uint32_t)(n) << PORT_HWSEL_HW11_SHIFT) +#define PORT_HWSEL_HW12_SHIFT (24) /* Bit 24-25: Port 0 Pin 12 Hardware Select */ +#define PORT_HWSEL_HW12_MASK (3 << PORT_HWSEL_HW12_SHIFT) +# define PORT_HWSEL_HW12(n) ((uint32_t)(n) << PORT_HWSEL_HW12_SHIFT) +#define PORT_HWSEL_HW13_SHIFT (26) /* Bit 26-27: Port 0 Pin 13 Hardware Select */ +#define PORT_HWSEL_HW13_MASK (3 << PORT_HWSEL_HW13_SHIFT) +# define PORT_HWSEL_HW13(n) ((uint32_t)(n) << PORT_HWSEL_HW13_SHIFT) +#define PORT_HWSEL_HW14_SHIFT (28) /* Bit 28-29: Port 0 Pin 14 Hardware Select */ +#define PORT_HWSEL_HW14_MASK (3 << PORT_HWSEL_HW14_SHIFT) +# define PORT_HWSEL_HW14(n) 14uint32_t)(n) << PORT_HWSEL_HW14_SHIFT) +#define PORT_HWSEL_HW15_SHIFT (30) /* Bit 30-31: Port 0 Pin 15 Hardware Select */ +#define PORT_HWSEL_HW15_MASK (3 << PORT_HWSEL_HW15_SHIFT) +# define PORT_HWSEL_HW15(n) ((uint32_t)(n) << PORT_HWSEL_HW15_SHIFT) #endif /* __ARCH_ARM_SRC_XMC4_CHIP_XMC4_SCU_H */ From 042b33414abe8950d7dd7223490846681b46957c Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 17 Mar 2017 08:28:40 -0600 Subject: [PATCH 15/21] XMC4xxx: Missing OMR field in PORT register definition header file. --- arch/arm/src/xmc4/chip/xmc4_ports.h | 28 ++++++++++++++++++++-------- 1 file changed, 20 insertions(+), 8 deletions(-) diff --git a/arch/arm/src/xmc4/chip/xmc4_ports.h b/arch/arm/src/xmc4/chip/xmc4_ports.h index 1d6cfa6b428..1465c41a648 100644 --- a/arch/arm/src/xmc4/chip/xmc4_ports.h +++ b/arch/arm/src/xmc4/chip/xmc4_ports.h @@ -239,25 +239,37 @@ /* Register Bit-Field Definitions **************************************************/ -/* Port Output Register, Port Output Modification Register, Port Input Register, - * Port Pin Function Decision Control Register, Port Pin Power Save Register. +/* Port Output Register, , Port Input Register, Port Pin Function Decision Control + * Register, Port Pin Power Save Register. */ #define PORT_PIN(n) (1 << (n)) +/* Port Output Modification Register: + * + * PRx PSx Function + * 0 0 Bit Pn_OUT.Px is not changed. + * 0 1 Bit Pn_OUT.Px is set. + * 1 0 Bit Pn_OUT.Px is reset. + * 1 1 Bit Pn_OUT.Px is toggled. + */ + +#define OMR_PS(n) (1 << (n)) +#define OMR_PR(n) (1 << ((n) + 16)) + /* Basic port input/output field values */ /* Director Input */ -#define IOCR_NOPULL 0 /* No internal pull device active */ -#define IOCR_PULLDOWN 1 /* Internal pull-down device active */ -#define IOCR_PULLUP 2 /* Internal pull-down device active */ -#define IOCR_CONT 3 /* No internal pull device active; Pn_OUTx continuously - * samples the input value */ +#define IOCR_NOPULL 0 /* No internal pull device active */ +#define IOCR_PULLDOWN 1 /* Internal pull-down device active */ +#define IOCR_PULLUP 2 /* Internal pull-down device active */ +#define IOCR_CONT 3 /* No internal pull device active; Pn_OUTx + * continuously samples the input value */ /* Any of the above may be OR'ed with */ /* Inverted Input */ -#define IOCR_INVERT 4 /* Inverted input */ +#define IOCR_INVERT 4 /* Inverted input */ /* Port Input/Output Control Register 0 */ From d2d54b4ae70f0a85bdad8cb35dc521f524541564 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 17 Mar 2017 11:18:24 -0600 Subject: [PATCH 16/21] XMC4xxx: Add framework and definitions for GPIO support --- arch/arm/src/xmc4/chip/xmc4_ports.h | 37 +++-- arch/arm/src/xmc4/xmc4_gpio.c | 98 ++++++++++++ arch/arm/src/xmc4/xmc4_gpio.h | 222 ++++++++++++++++++++++++++++ arch/arm/src/xmc4/xmc4_lowputc.c | 2 +- arch/arm/src/xmc4/xmc4_serial.c | 2 +- arch/arm/src/xmc4/xmc4_start.c | 2 + 6 files changed, 349 insertions(+), 14 deletions(-) diff --git a/arch/arm/src/xmc4/chip/xmc4_ports.h b/arch/arm/src/xmc4/chip/xmc4_ports.h index 1465c41a648..3478d9dedb2 100644 --- a/arch/arm/src/xmc4/chip/xmc4_ports.h +++ b/arch/arm/src/xmc4/chip/xmc4_ports.h @@ -1,7 +1,7 @@ /************************************************************************************ * arch/arm/src/xmc4/chip/xmc4_ports.h * - * Copyright (C /*2017 Gregory Nutt. All rights reserved. + * Copyright (C) 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Reference: XMC4500 Reference Manual V1.5 2014-07 Microcontrollers. @@ -27,17 +27,17 @@ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION /*HOWEVER CAUSED + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE /*ARISING IN + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * * May include some logic from sample code provided by Infineon: * - * Copyright (C /*2011-2015 Infineon Technologies AG. All rights reserved. + * Copyright (C) 2011-2015 Infineon Technologies AG. All rights reserved. * - * Infineon Technologies AG (Infineon /*is supplying this software for use with + * Infineon Technologies AG (Infineon) is supplying this software for use with * Infineon's microcontrollers. This file can be freely distributed within * development tools that are supporting such microcontrollers. * @@ -258,18 +258,31 @@ #define OMR_PR(n) (1 << ((n) + 16)) /* Basic port input/output field values */ -/* Director Input */ +/* Direct Input */ -#define IOCR_NOPULL 0 /* No internal pull device active */ -#define IOCR_PULLDOWN 1 /* Internal pull-down device active */ -#define IOCR_PULLUP 2 /* Internal pull-down device active */ -#define IOCR_CONT 3 /* No internal pull device active; Pn_OUTx +#define IOCR_INPUT_NOPULL 0 /* No internal pull device active */ +#define IOCR_INPUT_PULLDOWN 1 /* Internal pull-down device active */ +#define IOCR_INPUT_PULLUP 2 /* Internal pull-down device active */ +#define IOCR_INPUT_CONT 3 /* No internal pull device active; Pn_OUTx * continuously samples the input value */ -/* Any of the above may be OR'ed with */ +/* Any of the above input configurations may be OR'ed with */ /* Inverted Input */ -#define IOCR_INVERT 4 /* Inverted input */ +#define IOCR_INPUT_INVERT 4 /* Inverted input modifier */ + +/* Push-pull Output (direct input) */ + +#define IOCR_OUTPUT 16 /* General-purpose output */ +#define IOCR_OUTPUT_ALT1 17 /* Alternate output function 1 */ +#define IOCR_OUTPUT_ALT2 18 /* Alternate output function 2 */ +#define IOCR_OUTPUT_ALT3 19 /* Alternate output function 3 */ +#define IOCR_OUTPUT_ALT4 20 /* Alternate output function 4 */ + +/* Any of the above may be OR'ed with */ +/* Open drain output */ + +#define IOCR_OUTPUT_OPENDRAIN 8 /* Output drain output modifier */ /* Port Input/Output Control Register 0 */ diff --git a/arch/arm/src/xmc4/xmc4_gpio.c b/arch/arm/src/xmc4/xmc4_gpio.c index e69de29bb2d..4080a0be992 100644 --- a/arch/arm/src/xmc4/xmc4_gpio.c +++ b/arch/arm/src/xmc4/xmc4_gpio.c @@ -0,0 +1,98 @@ +/**************************************************************************** + * arch/arm/src/xmc4/xmc4_gpio.c + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include +#include + +#include + +#include "up_arch.h" +#include "up_internal.h" + +#include "chip/xmc4_ports.h" +#include "xmc4_gpio.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: xmc4_gpio_config + * + * Description: + * Configure a PIN based on bit-encoded description of the pin, + * 'pincconfig'. + * + ****************************************************************************/ + +int xmc4_gpio_config(gpioconfig_t pinconfig) +{ +#warning Missing logic + return -EINVAL; +} + +/**************************************************************************** + * Name: xmc4_gpio_write + * + * Description: + * Write one or zero to the PORT pin selected by 'pinconfig' + * + ****************************************************************************/ + +void xmc4_gpio_write(gpioconfig_t pinconfig, bool value) +{ +#warning Missing logic +} + +/**************************************************************************** + * Name: xmc4_gpio_read + * + * Description: + * Read one or zero from the PORT pin selected by 'pinconfig' + * + ****************************************************************************/ + +bool xmc4_gpio_read(gpioconfig_t pinconfig) +{ +#warning Missing logic + return false; +} diff --git a/arch/arm/src/xmc4/xmc4_gpio.h b/arch/arm/src/xmc4/xmc4_gpio.h index e69de29bb2d..44ab0bde538 100644 --- a/arch/arm/src/xmc4/xmc4_gpio.h +++ b/arch/arm/src/xmc4/xmc4_gpio.h @@ -0,0 +1,222 @@ +/**************************************************************************** + * arch/arm/src/xmc4/xmc4_gpio.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "chip/xmc4_ports.h" + +/**************************************************************************** + * Preprocessor Definitions + ****************************************************************************/ + +/* 32-bit GIO encoding: + * + * .... TTTT TMDD DCC. .... .... PPPP BBBB + */ + + +/* This identifies the GPIO pint type: + * + * .... TTTT T... .... .... .... .... .... + */ + +#define GPIO_PINTYPE_SHIFT (23) /* Bits 23-27: Pin type */ +#define GPIO_PINTYPE_MASK (31 << GPIO_PINTYPE_SHIFT) + +/* See chip/xmc4_ports.h for the IOCR definitions */ +/* Direct input */ + +# define GPIO_INPUT_NOPULL (IOCR_INPUT_NOPULL << GPIO_PINTYPE_SHIFT) +# define GPIO_INPUT_PULLDOWN (IOCR_INPUT_PULLDOWN << GPIO_PINTYPE_SHIFT) +# define GPIO_INPUT_PULLUP (IOCR_INPUT_PULLUP << GPIO_PINTYPE_SHIFT) +# define GPIO_INPUT_CONT (IOCR_INPUT_CONT << GPIO_PINTYPE_SHIFT) + +/* Push-pull Output (direct input) */ + +# define GPIO_OUTPUT (IOCR_OUTPUT << GPIO_PINTYPE_SHIFT) +# define GPIO_OUTPUT_ALT1 (IOCR_OUTPUT_ALT1 << GPIO_PINTYPE_SHIFT) +# define GPIO_OUTPUT_ALT2 (IOCR_OUTPUT_ALT2 << GPIO_PINTYPE_SHIFT) +# define GPIO_OUTPUT_ALT3 (IOCR_OUTPUT_ALT3 << GPIO_PINTYPE_SHIFT) +# define GPIO_OUTPUT_ALT4 (IOCR_OUTPUT_ALT4 << GPIO_PINTYPE_SHIFT) + +# define _GPIO_OUTPUT_BIT (16 << GPIO_PINTYPE_SHIFT) +# define GPIO_ISINPUT(p) (((p) & _GPIO_OUTPUT_BIT) != 0) +# define GPIO_ISOUTPUT(p) (((p) & _GPIO_OUTPUT_BIT) == 0) + +/* Pin type modifier: + * + * .... .... .M.. .... .... .... .... .... + */ + +#define GPIO_INPUT_INVERT (1 << 22) /* Inverted input modifier */ +#define GPIOS_OUTPUT_OPENDRAIN (1 << 22) /* Output drain output modifier */ + +/* Pad driver strength: + * + * .... .... ..DD D... .... .... .... .... + */ + +#define GPIO_PADTYPE_SHIFT (19) /* Bits 19-21: Pad driver strength */ +#define GPIO_PADTYPE_MASK (7 << GPIO_PADTYPE_SHIFT) + +/* See chip/xmc4_ports.h for the PDR definitions */ +/* Pad class A1: */ + +# define GPIO_PADA1_MEDIUM (PDR_PADA1_MEDIUM << GPIO_PADTYPE_SHIFT) +# define GPIO_PADA1_WEAK (PDR_PADA1_WEAK << GPIO_PADTYPE_SHIFT) + +/* Pad class A1+: */ + +# define GPIO_PADA1P_STRONGSOFT (PDR_PADA1P_STRONGSOFT << GPIO_PADTYPE_SHIFT) +# define GPIO_PADA1P_STRONGSLOW (PDR_PADA1P_STRONGSLOW << GPIO_PADTYPE_SHIFT) +# define GPIO_PADA1P_MEDIUM (PDR_PADA1P_MEDIUM << GPIO_PADTYPE_SHIFT) +# define GPIO_PADA1P_WEAK (PDR_PADA1P_WEAK << GPIO_PADTYPE_SHIFT) + +/* Pad class A2: */ + +# define GPIO_PADA2_STRONGSHARP (PDR_PADA2_STRONGSHARP << GPIO_PADTYPE_SHIFT) +# define GPIO_PADA2_STRONGMEDIUM (PDR_PADA2_STRONGMEDIUM << GPIO_PADTYPE_SHIFT) +# define GPIO_PADA2_STRONGSOFT (PDR_PADA2_STRONGSOFT << GPIO_PADTYPE_SHIFT) +# define GPIO_PADA2_MEDIUM (PDR_PADA2_MEDIUM << GPIO_PADTYPE_SHIFT) +# define GPIO_PADA2_WEAK (PDR_PADA2_WEAK << GPIO_PADTYPE_SHIFT) + +/* Pin control: + * + * .... .... .... .CC. .... .... .... .... + */ + +#define GPIO_PINCTRL_SHIFT (17) /* Bits 17-18: Pad driver strength */ +#define GPIO_PINCTRL_MASK (3 << GPIO_PINCTRL_SHIFT) + +/* See chip/xmc4_ports.h for the PDR definitions */ + +# define GPIO_PINCTRL_SOFTWARE (HWSEL_SOFTWARE << GPIO_PINCTRL_SHIFT) +# define GPIO_PINCTRL_OVERRIDE0 (HWSEL_OVERRIDE0 << GPIO_PINCTRL_SHIFT) +# define GPIO_PINCTRL_OVERRIDE1 (HWSEL_OVERRIDE1 << GPIO_PINCTRL_SHIFT) + +/* This identifies the GPIO port: + * + * .... ... .... .... .... .... PPPP .... + */ + +#define GPIO_PORT_SHIFT (4) /* Bit 4-7: Port number */ +#define GPIO_PORT_MASK (7 << GPIO_PORT_SHIFT) +# define GPIO_PORT0 (0 << GPIO_PORT_SHIFT) +# define GPIO_PORT1 (1 << GPIO_PORT_SHIFT) +# define GPIO_PORT2 (2 << GPIO_PORT_SHIFT) +# define GPIO_PORT3 (3 << GPIO_PORT_SHIFT) +# define GPIO_PORT4 (4 << GPIO_PORT_SHIFT) +# define GPIO_PORT5 (5 << GPIO_PORT_SHIFT) +# define GPIO_PORT6 (6 << GPIO_PORT_SHIFT) +# define GPIO_PORT7 (7 << GPIO_PORT_SHIFT) +# define GPIO_PORT8 (8 << GPIO_PORT_SHIFT) +# define GPIO_PORT9 (9 << GPIO_PORT_SHIFT) +# define GPIO_PORT14 (14 << GPIO_PORT_SHIFT) +# define GPIO_PORT15 (15 << GPIO_PORT_SHIFT) + +/* This identifies the bit in the port: + * + * ... ..... .... .... .... .... .... BBBB + */ + +#define GPIO_PIN_SHIFT (0) /* Bits 0-3: GPIO pin: 0-15 */ +#define GPIO_PIN_MASK (31 << GPIO_PIN_SHIFT) +#define GPIO_PIN0 (0 << GPIO_PIN_SHIFT) +#define GPIO_PIN1 (1 << GPIO_PIN_SHIFT) +#define GPIO_PIN2 (2 << GPIO_PIN_SHIFT) +#define GPIO_PIN3 (3 << GPIO_PIN_SHIFT) +#define GPIO_PIN4 (4 << GPIO_PIN_SHIFT) +#define GPIO_PIN5 (5 << GPIO_PIN_SHIFT) +#define GPIO_PIN6 (6 << GPIO_PIN_SHIFT) +#define GPIO_PIN7 (7 << GPIO_PIN_SHIFT) +#define GPIO_PIN8 (8 << GPIO_PIN_SHIFT) +#define GPIO_PIN9 (9 << GPIO_PIN_SHIFT) +#define GPIO_PIN10 (10 << GPIO_PIN_SHIFT) +#define GPIO_PIN11 (11 << GPIO_PIN_SHIFT) +#define GPIO_PIN12 (12 << GPIO_PIN_SHIFT) +#define GPIO_PIN13 (13 << GPIO_PIN_SHIFT) +#define GPIO_PIN14 (14 << GPIO_PIN_SHIFT) +#define GPIO_PIN15 (15 << GPIO_PIN_SHIFT) + + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/* This is a type large enought to hold all pin configuration bits. */ + +typedef uint32_t gpioconfig_t; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: xmc4_gpio_config + * + * Description: + * Configure a PIN based on bit-encoded description of the pin, + * 'pincconfig'. + * + ****************************************************************************/ + +int xmc4_gpio_config(gpioconfig_t pinconfig); + +/**************************************************************************** + * Name: xmc4_gpio_write + * + * Description: + * Write one or zero to the PORT pin selected by 'pinconfig' + * + ****************************************************************************/ + +void xmc4_gpio_write(gpioconfig_t pinconfig, bool value); + +/**************************************************************************** + * Name: xmc4_gpio_read + * + * Description: + * Read one or zero from the PORT pin selected by 'pinconfig' + * + ****************************************************************************/ + +bool xmc4_gpio_read(gpioconfig_t pinconfig); diff --git a/arch/arm/src/xmc4/xmc4_lowputc.c b/arch/arm/src/xmc4/xmc4_lowputc.c index 8fe2f4094b8..ec44caba54a 100644 --- a/arch/arm/src/xmc4/xmc4_lowputc.c +++ b/arch/arm/src/xmc4/xmc4_lowputc.c @@ -48,7 +48,7 @@ #include "up_arch.h" #include "xmc4_config.h" -#include "chip/xmc4_uart.h" +#include "chip/xmc4_usic.h" #include "chip/xmc4_pinmux.h" /**************************************************************************** diff --git a/arch/arm/src/xmc4/xmc4_serial.c b/arch/arm/src/xmc4/xmc4_serial.c index b90f1c19ff1..509cca56156 100644 --- a/arch/arm/src/xmc4/xmc4_serial.c +++ b/arch/arm/src/xmc4/xmc4_serial.c @@ -59,7 +59,7 @@ #include "xmc4_config.h" #include "chip.h" -#include "chip/xmc4_uart.h" +#include "chip/xmc4_usic.h" /**************************************************************************** * Pre-processor Definitions diff --git a/arch/arm/src/xmc4/xmc4_start.c b/arch/arm/src/xmc4/xmc4_start.c index e712f97dd37..7bf76f1faef 100644 --- a/arch/arm/src/xmc4/xmc4_start.c +++ b/arch/arm/src/xmc4/xmc4_start.c @@ -46,11 +46,13 @@ #include #include +#include "nvic.h" #include "up_arch.h" #include "up_internal.h" #include "chip/xmc4_flash.h" #include "xmc4_userspace.h" +#include "xmc4_start.h" #ifdef CONFIG_ARCH_FPU # include "nvic.h" From 41758d8e4c274df26b4bc0373c322c6090899aa1 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 17 Mar 2017 11:22:42 -0600 Subject: [PATCH 17/21] XMC4xxx: minor update to GPIO definitions. --- arch/arm/src/xmc4/xmc4_gpio.h | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm/src/xmc4/xmc4_gpio.h b/arch/arm/src/xmc4/xmc4_gpio.h index 44ab0bde538..716d821192e 100644 --- a/arch/arm/src/xmc4/xmc4_gpio.h +++ b/arch/arm/src/xmc4/xmc4_gpio.h @@ -87,8 +87,10 @@ * .... .... .M.. .... .... .... .... .... */ -#define GPIO_INPUT_INVERT (1 << 22) /* Inverted input modifier */ -#define GPIOS_OUTPUT_OPENDRAIN (1 << 22) /* Output drain output modifier */ +#define GPIO_INPUT_INVERT (1 << 22) /* Inverted direct input modifier */ + +#define GPIOS_OUTPUT_PUSHPULL (0) /* Push-ull output is the default */ +#define GPIOS_OUTPUT_OPENDRAIN (1 << 22) /* Output drain output modifier */ /* Pad driver strength: * From 8bfb735351850e374a435a5fb116e8fbe3b5fc37 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 17 Mar 2017 13:02:07 -0600 Subject: [PATCH 18/21] XMC4xxx: Finishes implementation of GPIO support. --- arch/arm/src/xmc4/chip/xmc4_memorymap.h | 1 + arch/arm/src/xmc4/chip/xmc4_ports.h | 8 + arch/arm/src/xmc4/xmc4_gpio.c | 399 +++++++++++++++++++++++- arch/arm/src/xmc4/xmc4_gpio.h | 75 +++-- 4 files changed, 450 insertions(+), 33 deletions(-) diff --git a/arch/arm/src/xmc4/chip/xmc4_memorymap.h b/arch/arm/src/xmc4/chip/xmc4_memorymap.h index c2b847d4e07..ea41ac30b1b 100644 --- a/arch/arm/src/xmc4/chip/xmc4_memorymap.h +++ b/arch/arm/src/xmc4/chip/xmc4_memorymap.h @@ -148,6 +148,7 @@ #define XMC4_USIC2_CH0_BASE 0x48024000 #define XMC4_USIC2_CH1_BASE 0x48024200 #define XMC4_USIC2_RAM_BASE 0x48024400 +#define XMC4_PORT_BASE(n) (0x48028000 + ((n) << 8)) #define XMC4_PORT0_BASE 0x48028000 #define XMC4_PORT1_BASE 0x48028100 #define XMC4_PORT2_BASE 0x48028200 diff --git a/arch/arm/src/xmc4/chip/xmc4_ports.h b/arch/arm/src/xmc4/chip/xmc4_ports.h index 3478d9dedb2..588965c9f0b 100644 --- a/arch/arm/src/xmc4/chip/xmc4_ports.h +++ b/arch/arm/src/xmc4/chip/xmc4_ports.h @@ -58,6 +58,8 @@ #include +#include "chip/xmc4_memorymap.h" + /************************************************************************************ * Pre-processor Definitions ************************************************************************************/ @@ -68,13 +70,19 @@ #define XMC4_PORT_OUT_OFFSET 0x0000 /* Port Output Register */ #define XMC4_PORT_OMR_OFFSET 0x0004 /* Port Output Modification Register */ + +#define XMC4_PORT_IOCR_OFFSET(n) (0x0010 + ((n) & 3)) #define XMC4_PORT_IOCR0_OFFSET 0x0010 /* Port Input/Output Control Register 0 */ #define XMC4_PORT_IOCR4_OFFSET 0x0014 /* Port Input/Output Control Register 4 */ #define XMC4_PORT_IOCR8_OFFSET 0x0018 /* Port Input/Output Control Register 8 */ #define XMC4_PORT_IOCR12_OFFSET 0x001c /* Port Input/Output Control Register 12 */ + #define XMC4_PORT_IN_OFFSET 0x0024 /* Port Input Register */ + +#define XMC4_PORT_PDR_OFFSET(n) (0x0010 + (((n) >> 1) & 3)) #define XMC4_PORT_PDR0_OFFSET 0x0040 /* Port Pad Driver Mode 0 Register */ #define XMC4_PORT_PDR1_OFFSET 0x0044 /* Port Pad Driver Mode 1 Register */ + #define XMC4_PORT_PDISC_OFFSET 0x0060 /* Port Pin Function Decision Control Register */ #define XMC4_PORT_PPS_OFFSET 0x0070 /* Port Pin Power Save Register */ #define XMC4_PORT_HWSEL_OFFSET 0x0074 /* Port Pin Hardware Select Register */ diff --git a/arch/arm/src/xmc4/xmc4_gpio.c b/arch/arm/src/xmc4/xmc4_gpio.c index 4080a0be992..2bc8f108282 100644 --- a/arch/arm/src/xmc4/xmc4_gpio.c +++ b/arch/arm/src/xmc4/xmc4_gpio.c @@ -44,6 +44,7 @@ #include #include +#include #include "up_arch.h" #include "up_internal.h" @@ -51,6 +52,301 @@ #include "chip/xmc4_ports.h" #include "xmc4_gpio.h" +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: xmc4_gpio_getreg + * + * Description: + * Return the pin number for this pin configuration + * + ****************************************************************************/ + +static inline uint32_t xmc4_gpio_getreg(uintptr_t portbase, + unsigned int offset) +{ + return getreg32(portbase + offset); +} + +/**************************************************************************** + * Name: xmc4_gpio_putreg + * + * Description: + * Return the pin number for this pin configuration + * + ****************************************************************************/ + +static inline void xmc4_gpio_putreg(uintptr_t portbase, unsigned int offset, + uint32_t regval) +{ + putreg32(regval, portbase + offset); +} + +/**************************************************************************** + * Name: xmc4_gpio_port + * + * Description: + * Return the port number for this pin configuration + * + ****************************************************************************/ + +static inline int xmc4_gpio_port(gpioconfig_t pinconfig) +{ + return ((pinconfig & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT); +} + +/**************************************************************************** + * Name: xmc4_gpio_portbase + * + * Description: + * Return the base address of the port register for this pin configuration. + * + ****************************************************************************/ + +static uintptr_t xmc4_gpio_portbase(gpioconfig_t pinconfig) +{ + return XMC4_PORT_BASE(xmc4_gpio_port(pinconfig)); +} + +/**************************************************************************** + * Name: xmc4_gpio_pin + * + * Description: + * Return the pin number for this pin configuration + * + ****************************************************************************/ + +static unsigned int xmc4_gpio_pin(gpioconfig_t pinconfig) +{ + return ((pinconfig & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT); +} + +/**************************************************************************** + * Name: xmc4_gpio_pintype + * + * Description: + * Return the pintype for this pin configuration + * + ****************************************************************************/ + +static inline unsigned int xmc4_gpio_pintype(gpioconfig_t pinconfig) +{ + return ((pinconfig & GPIO_PINTYPE_MASK) >> GPIO_PINTYPE_SHIFT); +} + +/**************************************************************************** + * Name: xmc4_gpio_pinctrl + * + * Description: + * Return the pintype for this pin configuration + * + ****************************************************************************/ + +static inline unsigned int xmc4_gpio_pinctrl(gpioconfig_t pinconfig) +{ + return ((pinconfig & GPIO_PINCTRL_MASK) >> GPIO_PINCTRL_SHIFT); +} + +/**************************************************************************** + * Name: xmc4_gpio_padtype + * + * Description: + * Return the padtype for this pin configuration + * + ****************************************************************************/ + +static inline unsigned int xmc4_gpio_padtype(gpioconfig_t pinconfig) +{ + return ((pinconfig & GPIO_PADTYPE_MASK) >> GPIO_PADTYPE_SHIFT); +} + +/**************************************************************************** + * Name: xmc4_gpio_iocr + * + * Description: + * Update the IOCR register + * + ****************************************************************************/ + +static void xmc4_gpio_iocr(uintptr_t portbase, unsigned int pin, + unsigned int value) +{ + uint32_t regval; + uint32_t mask; + unsigned int offset; + unsigned int shift; + + /* Read the IOCR register */ + + offset = XMC4_PORT_IOCR_OFFSET(pin); + regval = xmc4_gpio_getreg(portbase, offset); + + /* Set the new value for this field */ + + pin &= 3; + shift = PORT_IOCR0_PC_SHIFT(pin); + mask = PORT_IOCR0_PC_MASK(pin); + + regval &= ~mask; + regval |= (uint32_t)value << shift; + + xmc4_gpio_putreg(portbase, offset, regval); +} + +/**************************************************************************** + * Name: xmc4_gpio_hwsel + * + * Description: + * Update the HWSEL register + * + ****************************************************************************/ + +static inline void xmc4_gpio_hwsel(uintptr_t portbase, unsigned int pin, + unsigned int value) +{ + uint32_t regval; + uint32_t mask; + unsigned int shift; + + /* Read the HWSEL register */ + + regval = xmc4_gpio_getreg(portbase, XMC4_PORT_HWSEL_OFFSET); + + /* Set the new value for this field */ + + shift = PORT_HWSEL_HW_SHIFT(pin); + mask = PORT_HWSEL_HW_MASK(pin); + + regval &= ~mask; + regval |= (uint32_t)value << shift; + + xmc4_gpio_putreg(portbase, XMC4_PORT_HWSEL_OFFSET, regval); +} + +/**************************************************************************** + * Name: xmc4_gpio_pdisc + * + * Description: + * Update the PDISC register + * + ****************************************************************************/ + +static inline void xmc4_gpio_pdisc(uintptr_t portbase, unsigned int pin, + bool value) +{ + uint32_t regval; + uint32_t mask; + + /* Read the PDISC register */ + + regval = xmc4_gpio_getreg(portbase, XMC4_PORT_PDISC_OFFSET); + + /* Set/clear the enable/disable (or analg) value for this field */ + + mask = PORT_PIN(pin); + if (value) + { + regval |= mask; + } + else + { + regval &= ~mask; + } + + xmc4_gpio_putreg(portbase, XMC4_PORT_PDISC_OFFSET, regval); +} + +/**************************************************************************** + * Name: xmc4_gpio_pps + * + * Description: + * Update the PPS register + * + ****************************************************************************/ + +static inline void xmc4_gpio_pps(uintptr_t portbase, unsigned int pin, + bool value) +{ + uint32_t regval; + uint32_t mask; + + /* Read the PPS register */ + + regval = xmc4_gpio_getreg(portbase, XMC4_PORT_PPS_OFFSET); + + /* Set/clear the enable/disable (or analg) value for this field */ + + mask = PORT_PIN(pin); + if (value) + { + regval |= mask; + } + else + { + regval &= ~mask; + } + + xmc4_gpio_putreg(portbase, XMC4_PORT_PPS_OFFSET, regval); +} + +/**************************************************************************** + * Name: xmc4_gpio_pdr + * + * Description: + * Update the IOCR register + * + ****************************************************************************/ + +static void xmc4_gpio_pdr(uintptr_t portbase, unsigned int pin, + unsigned int value) +{ + uint32_t regval; + uint32_t mask; + unsigned int offset; + unsigned int shift; + + /* Read the PDRregister */ + + offset = XMC4_PORT_PDR_OFFSET(pin); + regval = xmc4_gpio_getreg(portbase, offset); + + /* Set the new value for this field */ + + pin &= 7; + shift = PORT_PDR0_PD_SHIFT(pin); + mask = PORT_PDR0_PD_MASK(pin); + + regval &= ~mask; + regval |= (uint32_t)value << shift; + + xmc4_gpio_putreg(portbase, offset, regval); +} + +/**************************************************************************** + * Name: xmc4_gpio_inverted + * + * Description: + * Check if the input is inverted + * + ****************************************************************************/ + +static inline bool xmc4_gpio_inverted(gpioconfig_t pinconfig) +{ + return ((pinconfig & GPIO_INPUT_INVERT) != 0); +} + +/**************************************************************************** + * Name: xmc4_gpio_opendrain + * + * Description: + * Check if the output is opendram + * + ****************************************************************************/ + +#define xmc4_gpio_opendrain(p) xmc4_gpio_inverted(p) + /**************************************************************************** * Public Functions ****************************************************************************/ @@ -66,8 +362,71 @@ int xmc4_gpio_config(gpioconfig_t pinconfig) { -#warning Missing logic - return -EINVAL; + uintptr_t portbase = xmc4_gpio_portbase(pinconfig); + unsigned int pin = xmc4_gpio_pin(pinconfig); + unsigned int value; + irqstate_t flags; + + flags = enter_critical_section(); + if (GPIO_ISINPUT(pinconfig)) + { + /* Get input pin type (IOCR) */ + + value = xmc4_gpio_pintype(pinconfig); + + /* Check if the input is inverted */ + + if (xmc4_gpio_inverted(pinconfig)) + { + value |= IOCR_INPUT_INVERT; + } + } + else + { + /* Force input while we configure */ + + xmc4_gpio_iocr(portbase, pin, IOCR_INPUT_NOPULL); + + /* Set output value before enabling output */ + + xmc4_gpio_write(pinconfig, ((pinconfig & GPIO_OUTPUT_SET) != 0)); + + /* Get output pin type (IOCR) */ + + value = xmc4_gpio_pintype(pinconfig); + + /* Get if the output is opendrain */ + + if (xmc4_gpio_opendrain(pinconfig)) + { + value |= IOCR_OUTPUT_OPENDRAIN; + } + } + + /* Update the IOCR register to instantiate the pin type */ + + xmc4_gpio_iocr(portbase, pin, value); + + /* Select pin control (HWSEL) */ + + value = xmc4_gpio_pinctrl(pinconfig); + xmc4_gpio_hwsel(portbase, pin, value); + + /* Select drive strength */ + + value = xmc4_gpio_padtype(pinconfig); + xmc4_gpio_pdr(portbase, pin, value); + + /* Enable/enable pad or Analog only (PDISC) */ + + xmc4_gpio_pdisc(portbase, pin, ((pinconfig & GPIO_PAD_DISABLE) != 0)); + + /* Make sure pin is not in power save mode (PDR) */ + + xmc4_gpio_pdisc(portbase, pin, false); + + leave_critical_section(flags); + return OK; } /**************************************************************************** @@ -80,7 +439,28 @@ int xmc4_gpio_config(gpioconfig_t pinconfig) void xmc4_gpio_write(gpioconfig_t pinconfig, bool value) { -#warning Missing logic + uintptr_t portbase = xmc4_gpio_portbase(pinconfig); + unsigned int pin = xmc4_gpio_pin(pinconfig); + uint32_t regval; + uint32_t mask; + + /* Read the OUT register */ + + regval = xmc4_gpio_getreg(portbase, XMC4_PORT_OUT_OFFSET); + + /* Set/clear output value for this pin */ + + mask = PORT_PIN(pin); + if (value) + { + regval |= mask; + } + else + { + regval &= ~mask; + } + + xmc4_gpio_putreg(portbase, XMC4_PORT_OUT_OFFSET, regval); } /**************************************************************************** @@ -93,6 +473,15 @@ void xmc4_gpio_write(gpioconfig_t pinconfig, bool value) bool xmc4_gpio_read(gpioconfig_t pinconfig) { -#warning Missing logic - return false; + uintptr_t portbase = xmc4_gpio_portbase(pinconfig); + unsigned int pin = xmc4_gpio_pin(pinconfig); + uint32_t regval; + + /* Read the OUT register */ + + regval = xmc4_gpio_getreg(portbase, XMC4_PORT_IN_OFFSET); + + /* Return in the input state for this pin */ + + return ((regval & PORT_PIN(pin)) != 0); } diff --git a/arch/arm/src/xmc4/xmc4_gpio.h b/arch/arm/src/xmc4/xmc4_gpio.h index 716d821192e..62b11bf048c 100644 --- a/arch/arm/src/xmc4/xmc4_gpio.h +++ b/arch/arm/src/xmc4/xmc4_gpio.h @@ -50,16 +50,16 @@ /* 32-bit GIO encoding: * - * .... TTTT TMDD DCC. .... .... PPPP BBBB + * TTTT TMPD DDCC V.... .... .... PPPP BBBB */ /* This identifies the GPIO pint type: * - * .... TTTT T... .... .... .... .... .... + * TTTT T... .... .... .... .... .... .... */ -#define GPIO_PINTYPE_SHIFT (23) /* Bits 23-27: Pin type */ +#define GPIO_PINTYPE_SHIFT (27) /* Bits 27-31: Pin type */ #define GPIO_PINTYPE_MASK (31 << GPIO_PINTYPE_SHIFT) /* See chip/xmc4_ports.h for the IOCR definitions */ @@ -84,60 +84,79 @@ /* Pin type modifier: * - * .... .... .M.. .... .... .... .... .... + * .... .M.. .... .... .... .... .... .... */ -#define GPIO_INPUT_INVERT (1 << 22) /* Inverted direct input modifier */ +#define GPIO_INPUT_INVERT (1 << 26) /* Bit 26: Inverted direct input modifier */ -#define GPIOS_OUTPUT_PUSHPULL (0) /* Push-ull output is the default */ -#define GPIOS_OUTPUT_OPENDRAIN (1 << 22) /* Output drain output modifier */ +#define GPIO_OUTPUT_OPENDRAIN (1 << 26) /* Bit 26: Output drain output modifier */ +#define GPIO_OUTPUT_PUSHPULL (0) /* Push-pull output is the default */ + +/* Disable PAD: + * + * .... ..P. .... ..... .... .... .... .... + * + * For P0-P6, the PDISC register is ready only. + * For P14-P15, the bit setting also selects Analog+Digital or Analog only + */ + +#define GPIO_PAD_DISABLE (1 << 25) /* Bit 25: Disable Pad (P7-P9) */ +#define GPIO_PAD_ANALOG (1 << 25) /* Bit 25: Analog only (P14-P15) */ /* Pad driver strength: * - * .... .... ..DD D... .... .... .... .... + * .... ...D DD.. ..... .... ......... .... */ -#define GPIO_PADTYPE_SHIFT (19) /* Bits 19-21: Pad driver strength */ -#define GPIO_PADTYPE_MASK (7 << GPIO_PADTYPE_SHIFT) +#define GPIO_PADTYPE_SHIFT (22) /* Bits 22-24: Pad driver strength */ +#define GPIO_PADTYPE_MASK (7 << GPIO_PADTYPE_SHIFT) /* See chip/xmc4_ports.h for the PDR definitions */ /* Pad class A1: */ -# define GPIO_PADA1_MEDIUM (PDR_PADA1_MEDIUM << GPIO_PADTYPE_SHIFT) -# define GPIO_PADA1_WEAK (PDR_PADA1_WEAK << GPIO_PADTYPE_SHIFT) +# define GPIO_PADA1_MEDIUM (PDR_PADA1_MEDIUM << GPIO_PADTYPE_SHIFT) +# define GPIO_PADA1_WEAK (PDR_PADA1_WEAK << GPIO_PADTYPE_SHIFT) /* Pad class A1+: */ -# define GPIO_PADA1P_STRONGSOFT (PDR_PADA1P_STRONGSOFT << GPIO_PADTYPE_SHIFT) -# define GPIO_PADA1P_STRONGSLOW (PDR_PADA1P_STRONGSLOW << GPIO_PADTYPE_SHIFT) -# define GPIO_PADA1P_MEDIUM (PDR_PADA1P_MEDIUM << GPIO_PADTYPE_SHIFT) -# define GPIO_PADA1P_WEAK (PDR_PADA1P_WEAK << GPIO_PADTYPE_SHIFT) +# define GPIO_PADA1P_STRONGSOFT (PDR_PADA1P_STRONGSOFT << GPIO_PADTYPE_SHIFT) +# define GPIO_PADA1P_STRONGSLOW (PDR_PADA1P_STRONGSLOW << GPIO_PADTYPE_SHIFT) +# define GPIO_PADA1P_MEDIUM (PDR_PADA1P_MEDIUM << GPIO_PADTYPE_SHIFT) +# define GPIO_PADA1P_WEAK (PDR_PADA1P_WEAK << GPIO_PADTYPE_SHIFT) /* Pad class A2: */ -# define GPIO_PADA2_STRONGSHARP (PDR_PADA2_STRONGSHARP << GPIO_PADTYPE_SHIFT) -# define GPIO_PADA2_STRONGMEDIUM (PDR_PADA2_STRONGMEDIUM << GPIO_PADTYPE_SHIFT) -# define GPIO_PADA2_STRONGSOFT (PDR_PADA2_STRONGSOFT << GPIO_PADTYPE_SHIFT) -# define GPIO_PADA2_MEDIUM (PDR_PADA2_MEDIUM << GPIO_PADTYPE_SHIFT) -# define GPIO_PADA2_WEAK (PDR_PADA2_WEAK << GPIO_PADTYPE_SHIFT) +# define GPIO_PADA2_STRONGSHARP (PDR_PADA2_STRONGSHARP << GPIO_PADTYPE_SHIFT) +# define GPIO_PADA2_STRONGMEDIUM (PDR_PADA2_STRONGMEDIUM << GPIO_PADTYPE_SHIFT) +# define GPIO_PADA2_STRONGSOFT (PDR_PADA2_STRONGSOFT << GPIO_PADTYPE_SHIFT) +# define GPIO_PADA2_MEDIUM (PDR_PADA2_MEDIUM << GPIO_PADTYPE_SHIFT) +# define GPIO_PADA2_WEAK (PDR_PADA2_WEAK << GPIO_PADTYPE_SHIFT) /* Pin control: * - * .... .... .... .CC. .... .... .... .... + * .... .... ..CC ..... .... .... .... .... */ -#define GPIO_PINCTRL_SHIFT (17) /* Bits 17-18: Pad driver strength */ -#define GPIO_PINCTRL_MASK (3 << GPIO_PINCTRL_SHIFT) +#define GPIO_PINCTRL_SHIFT (20) /* Bits 20-21: Pad driver strength */ +#define GPIO_PINCTRL_MASK (3 << GPIO_PINCTRL_SHIFT) /* See chip/xmc4_ports.h for the PDR definitions */ -# define GPIO_PINCTRL_SOFTWARE (HWSEL_SOFTWARE << GPIO_PINCTRL_SHIFT) -# define GPIO_PINCTRL_OVERRIDE0 (HWSEL_OVERRIDE0 << GPIO_PINCTRL_SHIFT) -# define GPIO_PINCTRL_OVERRIDE1 (HWSEL_OVERRIDE1 << GPIO_PINCTRL_SHIFT) +# define GPIO_PINCTRL_SOFTWARE (HWSEL_SOFTWARE << GPIO_PINCTRL_SHIFT) +# define GPIO_PINCTRL_OVERRIDE0 (HWSEL_OVERRIDE0 << GPIO_PINCTRL_SHIFT) +# define GPIO_PINCTRL_OVERRIDE1 (HWSEL_OVERRIDE1 << GPIO_PINCTRL_SHIFT) + +/* If the pin is an GPIO output, then this identifies the initial output value: + * + * .... .... .... V.... .... .... PPPP BBBB + */ + +#define GPIO_OUTPUT_SET (1 << 19) /* Bit 19: Initial value of output */ +#define GPIO_OUTPUT_CLEAR (0) /* This identifies the GPIO port: * - * .... ... .... .... .... .... PPPP .... + * .... .... .... .... .... .... PPPP .... */ #define GPIO_PORT_SHIFT (4) /* Bit 4-7: Port number */ From 5ae9564b7d2eab24ff753f7fdd0c5902180d137a Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 17 Mar 2017 16:26:11 -0600 Subject: [PATCH 19/21] XMC4xxx: GPIO write should use OMR, not OUTPUT register. --- arch/arm/src/xmc4/xmc4_gpio.c | 35 +++++++++++++++++++++++------------ 1 file changed, 23 insertions(+), 12 deletions(-) diff --git a/arch/arm/src/xmc4/xmc4_gpio.c b/arch/arm/src/xmc4/xmc4_gpio.c index 2bc8f108282..e26967f06f3 100644 --- a/arch/arm/src/xmc4/xmc4_gpio.c +++ b/arch/arm/src/xmc4/xmc4_gpio.c @@ -442,25 +442,34 @@ void xmc4_gpio_write(gpioconfig_t pinconfig, bool value) uintptr_t portbase = xmc4_gpio_portbase(pinconfig); unsigned int pin = xmc4_gpio_pin(pinconfig); uint32_t regval; - uint32_t mask; - /* Read the OUT register */ + /* Setup OMR value for this pin: + * + * PRx PSx Function + * 0 0 Bit Pn_OUT.Px is not changed. + * 0 1 Bit Pn_OUT.Px is set. + * 1 0 Bit Pn_OUT.Px is reset. + * 1 1 Bit Pn_OUT.Px is toggled. + */ - regval = xmc4_gpio_getreg(portbase, XMC4_PORT_OUT_OFFSET); - - /* Set/clear output value for this pin */ - - mask = PORT_PIN(pin); if (value) { - regval |= mask; + /* PRx==0; PSx==1 -> Set output */ + + regval = OMR_PS(pin); } else { - regval &= ~mask; + /* PRx==1; PSx==0 -> Reset output */ + + regval = OMR_PR(pin); } - xmc4_gpio_putreg(portbase, XMC4_PORT_OUT_OFFSET, regval); + /* Set/clear the OUTPUT. This is an atomoc operation so no critical + * section is needed. + */ + + xmc4_gpio_putreg(portbase, XMC4_PORT_OMR_OFFSET, regval); } /**************************************************************************** @@ -477,11 +486,13 @@ bool xmc4_gpio_read(gpioconfig_t pinconfig) unsigned int pin = xmc4_gpio_pin(pinconfig); uint32_t regval; - /* Read the OUT register */ + /* Read the OUT register. This is an atomoc operation so no critical + * section is needed. + */ regval = xmc4_gpio_getreg(portbase, XMC4_PORT_IN_OFFSET); - /* Return in the input state for this pin */ + /* Return in the input state for this pin at the time is was read */ return ((regval & PORT_PIN(pin)) != 0); } From 7bde01df98890f1b774c27f224a03ebd54995255 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 17 Mar 2017 16:40:29 -0600 Subject: [PATCH 20/21] XMC4C: Clean up some naming, fix some comments, add empty PINMUX header file. --- arch/arm/src/xmc4/chip/xmc4_flash.h | 2 +- arch/arm/src/xmc4/chip/xmc4_memorymap.h | 2 +- arch/arm/src/xmc4/chip/xmc4_pinmux.h | 52 +++++++++++++++++++++++++ arch/arm/src/xmc4/chip/xmc4_ports.h | 12 +++--- arch/arm/src/xmc4/chip/xmc4_usic.h | 2 +- arch/arm/src/xmc4/xmc4_gpio.h | 6 +-- 6 files changed, 64 insertions(+), 12 deletions(-) create mode 100644 arch/arm/src/xmc4/chip/xmc4_pinmux.h diff --git a/arch/arm/src/xmc4/chip/xmc4_flash.h b/arch/arm/src/xmc4/chip/xmc4_flash.h index e68e7078e9c..37afed16a2e 100644 --- a/arch/arm/src/xmc4/chip/xmc4_flash.h +++ b/arch/arm/src/xmc4/chip/xmc4_flash.h @@ -200,4 +200,4 @@ #define FLASH_PROCON2_S12_S13ROM (1 << 11) /* Bit 11: Sectors 12 and 13 Locked Forever by User 2 */ #define FLASH_PROCON2_S14_S15ROM (1 << 12) /* Bit 12: Sectors 14 and 15 Locked Forever by User 2 */ -#endif /* __ARCH_ARM_SRC_XMC4_CHIP_XMC4_SCU_H */ +#endif /* __ARCH_ARM_SRC_XMC4_CHIP_XMC4_FLASH_H */ diff --git a/arch/arm/src/xmc4/chip/xmc4_memorymap.h b/arch/arm/src/xmc4/chip/xmc4_memorymap.h index ea41ac30b1b..fb8dcbf183b 100644 --- a/arch/arm/src/xmc4/chip/xmc4_memorymap.h +++ b/arch/arm/src/xmc4/chip/xmc4_memorymap.h @@ -228,4 +228,4 @@ #define XMC4_PPB_BASE 0xe000e000 -#endif /* __ARCH_ARM_SRC_XMC4_CHIP_XMC4_SCU_H */ +#endif /* __ARCH_ARM_SRC_XMC4_CHIP_XMC4_MEMORYMAP_H */ diff --git a/arch/arm/src/xmc4/chip/xmc4_pinmux.h b/arch/arm/src/xmc4/chip/xmc4_pinmux.h new file mode 100644 index 00000000000..44d43074a83 --- /dev/null +++ b/arch/arm/src/xmc4/chip/xmc4_pinmux.h @@ -0,0 +1,52 @@ +/************************************************************************************ + * arch/arm/src/xmc4/chip/xmc4_pinmux.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Reference: XMC4500 Reference Manual V1.5 2014-07 Microcontrollers. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_XMC4_CHIP_XMC4_PINMUX_H +#define __ARCH_ARM_SRC_XMC4_CHIP_XMC4_PINMUX_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + + +#endif /* __ARCH_ARM_SRC_XMC4_CHIP_XMC4_PINMXU_H */ diff --git a/arch/arm/src/xmc4/chip/xmc4_ports.h b/arch/arm/src/xmc4/chip/xmc4_ports.h index 588965c9f0b..bdd90c2902b 100644 --- a/arch/arm/src/xmc4/chip/xmc4_ports.h +++ b/arch/arm/src/xmc4/chip/xmc4_ports.h @@ -447,11 +447,11 @@ /* Hardware select field values */ -#define HWSEL_SOFTWARE 0 /* Software control only */ -#define HWSEL_OVERRIDE0 1 /* HWI0/HWO0 control path can override the - * software configuration */ -#define HWSEL_OVERRIDE1 2 /* HWI1/HWO1 control path can override the - * software configuration */ +#define HWSEL_SW 0 /* Software control only */ +#define HWSEL_HW0 1 /* HWI0/HWO0 control path can override + * the software configuration */ +#define HWSEL_HW1 2 /* HWI1/HWO1 control path can override + * the software configuration */ /* Port Pin Hardware Select Register */ @@ -507,4 +507,4 @@ #define PORT_HWSEL_HW15_MASK (3 << PORT_HWSEL_HW15_SHIFT) # define PORT_HWSEL_HW15(n) ((uint32_t)(n) << PORT_HWSEL_HW15_SHIFT) -#endif /* __ARCH_ARM_SRC_XMC4_CHIP_XMC4_SCU_H */ +#endif /* __ARCH_ARM_SRC_XMC4_CHIP_XMC4_PORTS_H */ diff --git a/arch/arm/src/xmc4/chip/xmc4_usic.h b/arch/arm/src/xmc4/chip/xmc4_usic.h index 089a14811fc..1b3c4d2bdca 100644 --- a/arch/arm/src/xmc4/chip/xmc4_usic.h +++ b/arch/arm/src/xmc4/chip/xmc4_usic.h @@ -472,4 +472,4 @@ /* Transmit FIFO Buffer (32 x 4-bytes) */ #define USIC_IN_ -#endif /* __ARCH_ARM_SRC_XMC4_CHIP_XMC4_SCU_H */ +#endif /* __ARCH_ARM_SRC_XMC4_CHIP_XMC4_USIC_H */ diff --git a/arch/arm/src/xmc4/xmc4_gpio.h b/arch/arm/src/xmc4/xmc4_gpio.h index 62b11bf048c..c1bf09b87bd 100644 --- a/arch/arm/src/xmc4/xmc4_gpio.h +++ b/arch/arm/src/xmc4/xmc4_gpio.h @@ -142,9 +142,9 @@ /* See chip/xmc4_ports.h for the PDR definitions */ -# define GPIO_PINCTRL_SOFTWARE (HWSEL_SOFTWARE << GPIO_PINCTRL_SHIFT) -# define GPIO_PINCTRL_OVERRIDE0 (HWSEL_OVERRIDE0 << GPIO_PINCTRL_SHIFT) -# define GPIO_PINCTRL_OVERRIDE1 (HWSEL_OVERRIDE1 << GPIO_PINCTRL_SHIFT) +# define GPIO_PINCTRL_SOFTWARE (HWSEL_SW << GPIO_PINCTRL_SHIFT) +# define GPIO_PINCTRL_HW0 (HWSEL_HW0 << GPIO_PINCTRL_SHIFT) +# define GPIO_PINCTRL_HW1 (HWSEL_HW1 << GPIO_PINCTRL_SHIFT) /* If the pin is an GPIO output, then this identifies the initial output value: * From c6d5d3bdedd77e7430b58214fa871cb5e9c1b4e8 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 17 Mar 2017 16:44:26 -0600 Subject: [PATCH 21/21] XMC4xxx: All register definition files need to include memorymap.h --- arch/arm/src/xmc4/chip/xmc4_flash.h | 2 ++ arch/arm/src/xmc4/chip/xmc4_usic.h | 2 ++ arch/arm/src/xmc4/xmc4_gpio.h | 6 +++--- 3 files changed, 7 insertions(+), 3 deletions(-) diff --git a/arch/arm/src/xmc4/chip/xmc4_flash.h b/arch/arm/src/xmc4/chip/xmc4_flash.h index 37afed16a2e..0432e465b0a 100644 --- a/arch/arm/src/xmc4/chip/xmc4_flash.h +++ b/arch/arm/src/xmc4/chip/xmc4_flash.h @@ -58,6 +58,8 @@ #include +#include "chip/xmc4_memorymap.h" + /************************************************************************************ * Pre-processor Definitions ************************************************************************************/ diff --git a/arch/arm/src/xmc4/chip/xmc4_usic.h b/arch/arm/src/xmc4/chip/xmc4_usic.h index 1b3c4d2bdca..8b91e88583a 100644 --- a/arch/arm/src/xmc4/chip/xmc4_usic.h +++ b/arch/arm/src/xmc4/chip/xmc4_usic.h @@ -58,6 +58,8 @@ #include +#include "chip/xmc4_memorymap.h" + /************************************************************************************ * Pre-processor Definitions ************************************************************************************/ diff --git a/arch/arm/src/xmc4/xmc4_gpio.h b/arch/arm/src/xmc4/xmc4_gpio.h index c1bf09b87bd..49b80ba1968 100644 --- a/arch/arm/src/xmc4/xmc4_gpio.h +++ b/arch/arm/src/xmc4/xmc4_gpio.h @@ -142,9 +142,9 @@ /* See chip/xmc4_ports.h for the PDR definitions */ -# define GPIO_PINCTRL_SOFTWARE (HWSEL_SW << GPIO_PINCTRL_SHIFT) -# define GPIO_PINCTRL_HW0 (HWSEL_HW0 << GPIO_PINCTRL_SHIFT) -# define GPIO_PINCTRL_HW1 (HWSEL_HW1 << GPIO_PINCTRL_SHIFT) +# define GPIO_PINCTRL_SOFTWARE (HWSEL_SW << GPIO_PINCTRL_SHIFT) +# define GPIO_PINCTRL_HW0 (HWSEL_HW0 << GPIO_PINCTRL_SHIFT) +# define GPIO_PINCTRL_HW1 (HWSEL_HW1 << GPIO_PINCTRL_SHIFT) /* If the pin is an GPIO output, then this identifies the initial output value: *