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ARMv7-M: Add MPU support

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This commit is contained in:
Gregory Nutt 2015-12-14 15:38:58 -06:00
parent 290e5058ea
commit b3502af042
5 changed files with 1069 additions and 2 deletions
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3
arch/arm/src/armv7-r/arm_head.S
View file

@ -150,6 +150,7 @@ __start:
* example, we get here via a bootloader and the control register is in some
* unknown state.
*
* SCTLR_M Bit 0: MPU enable bit
* SCTLR_A Bit 1: Strict alignment disabled
* SCTLR_C Bit 2: DCache disabled
* SCTLR_CCP15BEN Bit 5: CP15 barrier enable
@ -174,7 +175,7 @@ __start:
/* Clear all configurable bits */
bic r0, r0, #(SCTLR_A | SCTLR_C | SCTLR_CCP15BEN | SCTLR_B)
bic r0, r0, #(SCTLR_M | SCTLR_A | SCTLR_C | SCTLR_CCP15BEN | SCTLR_B)
bic r0, r0, #(SCTLR_SW | SCTLR_I | SCTLR_V | SCTLR_RR)
bic r0, r0, #(SCTLR_BR | SCTLR_DZ | SCTLR_FI | SCTLR_U)
bic r0, r0, #(SCTLR_VE | SCTLR_EE | SCTLR_NMFI | SCTLR_TE | SCLTR_IE)

316
arch/arm/src/armv7-r/arm_mpu.c Normal file
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@ -0,0 +1,316 @@
/****************************************************************************
* arch/arm/src/armv7-r/arm_mpu.c
*
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <assert.h>
#include "mpu.h"
#include "up_internal.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Configuration ************************************************************/
#ifndef CONFIG_ARM_MPU_NREGIONS
# define CONFIG_ARM_MPU_NREGIONS 8
#endif
/****************************************************************************
* Private Data
****************************************************************************/
/* These sets represent the set of disabled memory sub-regions. A bit set
* corresponds to a disabled sub-region; the LS bit corresponds to the first
* region.
*
* The g_ms_regionmask array is indexed by the number of subregions at the
* end of the region: 0 means no sub-regions are available(0xff) and 8 means
* all subregions are available (0x00).
*/
static const uint8_t g_ms_regionmask[9] =
{
0xff, 0xfe, 0xfc, 0xf8, 0xf0, 0xe0, 0xc0, 0x80, 0x00
};
/* The g_ls_regionmask array is indexed by the number of subregions at the
* beginning of the region: 0 means no sub-regions need be disabled (0x00)
* and 8 means all subregions must be disabled (0xff).
*/
static const uint8_t g_ls_regionmask[9] =
{
0x00, 0x01, 0x03, 0x07, 0x0f, 0x1f, 0x3f, 0x7f, 0xff
};
/* The next available region number */
static uint8_t g_region;
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: mpu_subregion_ms
*
* Description:
* Given (1) the size of the memory to be mapped and (2) the log2 size
* of the mapping to use, determine the minimal sub-region set at the
* to be disabled at the higher end of the region.
*
* Assumption:
* l2size has the same properties as the return value from
* mpu_log2regionceil()
*
****************************************************************************/
static inline uint32_t mpu_subregion_ms(size_t size, uint8_t l2size)
{
unsigned int nsrs;
uint32_t asize;
uint32_t mask;
/* Examples with l2size = 12:
*
* Shifted Adjusted Number Sub-Region
* Size Mask Size Shift Sub-Regions Bitset
* 0x1000 0x01ff 0x1000 9 8 0x00
* 0x0c00 0x01ff 0x0c00 9 6 0xc0
* 0x0c40 0x01ff 0x0e00 9 7 0x80
*/
if (l2size < 32)
{
mask = ((1 << l2size)-1) >> 3; /* Shifted mask */
}
/* The 4Gb region size is a special case */
else
{
/* NOTE: There is no way to represent a 4Gb region size in the 32-bit
* input.
*/
mask = 0x1fffffff; /* Shifted mask */
}
asize = (size + mask) & ~mask; /* Adjusted size */
nsrs = asize >> (l2size-3); /* Number of subregions */
return g_ms_regionmask[nsrs];
}
/****************************************************************************
* Name: mpu_subregion_ls
*
* Description:
* Given (1) the offset to the beginning of data in the region and (2) the
* log2 size of the mapping to use, determine the minimal sub-region set
* to span that memory region sub-region set at the to be disabled at the
* higher end of the region
*
* Assumption:
* l2size has the same properties as the return value from
* mpu_log2regionceil()
*
****************************************************************************/
static inline uint32_t mpu_subregion_ls(size_t offset, uint8_t l2size)
{
unsigned int nsrs;
uint32_t aoffset;
uint32_t mask;
/* Examples with l2size = 12:
*
* Shifted Adjusted Number Sub-Region
* Offset Mask Offset Shift Sub-Regions Bitset
* 0x0000 0x01ff 0x0000 9 8 0x00
* 0x0400 0x01ff 0x0400 9 6 0x03
* 0x02c0 0x01ff 0x0200 9 7 0x01
*/
if (l2size < 32)
{
mask = ((1 << l2size)-1) >> 3; /* Shifted mask */
}
/* The 4Gb region size is a special case */
else
{
/* NOTE: There is no way to represent a 4Gb region size in the 32-bit
* input.
*/
mask = 0x1fffffff; /* Shifted mask */
}
aoffset = offset & ~mask; /* Adjusted offset */
nsrs = aoffset >> (l2size-3); /* Number of subregions */
return g_ls_regionmask[nsrs];
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: mpu_allocregion
*
* Description:
* Allocate the next region
*
* Assumptions:
* - Regions are never deallocated
* - Regions are only allocated early in initialization, so no special
* protection against re-entrancy is required;
*
****************************************************************************/
unsigned int mpu_allocregion(void)
{
DEBUGASSERT(g_region < CONFIG_ARM_MPU_NREGIONS);
return (unsigned int)g_region++;
}
/****************************************************************************
* Name: mpu_log2regionceil
*
* Description:
* Determine the smallest value of l2size (log base 2 size) such that the
* following is true:
*
* size <= (1 << l2size)
*
****************************************************************************/
uint8_t mpu_log2regionceil(size_t size)
{
uint8_t l2size;
/* The minimum permitted region size is 32 bytes (log2(32) = 5. */
for (l2size = 5; l2size < 32 && size > (1 << l2size); l2size++);
return l2size;
}
/****************************************************************************
* Name: mpu_log2regionfloor
*
* Description:
* Determine the largest value of l2size (log base 2 size) such that the
* following is true:
*
* size >= (1 << l2size)
*
****************************************************************************/
uint8_t mpu_log2regionfloor(size_t size)
{
uint8_t l2size = mpu_log2regionceil(size);
if (l2size > 4 && size < (1 << l2size))
{
l2size--;
}
return l2size;
}
/****************************************************************************
* Name: mpu_subregion
*
* Description:
* Given the size of the (1) memory to be mapped and (2) the log2 size
* of the mapping to use, determine the minimal sub-region set to span
* that memory region.
*
* Assumption:
* l2size has the same properties as the return value from
* mpu_log2regionceil()
*
****************************************************************************/
uint32_t mpu_subregion(uintptr_t base, size_t size, uint8_t l2size)
{
uint32_t mask;
size_t offset;
uint32_t ret;
/* Eight subregions are supported. The representation is as an 8-bit
* value with the LS bit corresponding to subregion 0. A bit is set
* to disable the sub-region.
*
* l2size: Log2 of the actual region size is <= (1 << l2size);
*/
DEBUGASSERT(l2size > 4 && size <= (1 << l2size));
/* For region sizes of 32, 64, and 128 bytes, the effect of setting
* one or more bits of the SRD field to 1 is UNPREDICTABLE.
*/
if (l2size < 8)
{
return 0;
}
/* Calculate the offset of the base address into the aligned region. */
mask = (1 << l2size) - 1;
offset = base & mask;
/* Calculate the mask need to handle disabled subregions at the end of the
* region
*/
ret = mpu_subregion_ms(size + offset, l2size);
/* Then OR in the mask need to handle disabled subregions at the beginning
* of the region.
*/
ret |= mpu_subregion_ls(offset, l2size);
return ret;
}

11
arch/arm/src/armv7-r/cp15.h
View file

@ -74,7 +74,7 @@
#define CP15_MIDR(r) _CP15(0, r, c0, c0, 0) /* Main ID Register */
#define CP15_CTR(r) _CP15(0, r, c0, c0, 1) /* Cache Type Register */
#define CP15_TCMTR(r) _CP15(0, r, c0, c0, 2) /* TCM Type Register */
#define CP15_MPUIDR(r) _CP15(0, r, c0, c0, 4) /* MPU Type Register */
#define CP15_MPUIR(r) _CP15(0, r, c0, c0, 4) /* MPU Type Register */
#define CP15_MPIDR(r) _CP15(0, r, c0, c0, 5) /* Multiprocessor Affinity Register */
#define CP15_REVIDR(r) _CP15(0, r, c0, c0, 6) /* Revision ID register (Cortex-A9) */
#define CP15_MID_PFR0(r) _CP15(0, r, c0, c1, 0) /* Processor Feature Register 0 */
@ -107,6 +107,15 @@
#define CP15_DFAR(r) _CP15(0, r, c6, c0, 0) /* Data Fault Address Register */
#define CP15_IFAR(r) _CP15(0, r, c6, c0, 2) /* Instruction Fault Address Register */
#define CP15_DRBAR(r) _CP15(0, r, c6, c1, 0) /* Data Region Base Address Register */
#define CP15_DRSR(r) _CP15(0, r, c6, c1, 2) /* Data Region Size and Enable Register */
#define CP15_DRACR(r) _CP15(0, r, c6, c1, 4) /* Data Region Access Control Register */
#ifndef CONFIG_ARM_HAVE_MPU_UNIFIED
# define CP15_IRBAR(r) _CP15(0, r, c6, c1, 1) /* Instruction Region Base Address Register */
# define CP15_IRSR(r) _CP15(0, r, c6, c1, 3) /* Instruction Region Size and Enable Register */
# define CP15_IRACR(r) _CP15(0, r, c6, c1, 5) /* Instruction Region Access Control Register */
#endif
#define CP15_RGNR(r) _CP15(0, r, c6, c2, 0) /* MPU Region Number Register */
#define CP15_ICIALLUIS(r) _CP15(0, r, c7, c1, 0) /* Cache Operations Registers */
#define CP15_BPIALLIS(r) _CP15(0, r, c7, c1, 6)

740
arch/arm/src/armv7-r/mpu.h Normal file
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@ -0,0 +1,740 @@
/************************************************************************************
* arch/arm/src/armv7-r/mpu.h
*
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_ARMV7R_MPU_H
#define __ARCH_ARM_SRC_ARMV7R_MPU_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#ifndef __ASSEMBLY__
# include <sys/types.h>
# include <stdint.h>
# include <stdbool.h>
# include <debug.h>
# include "up_arch.h"
# include "cp15.h"
#endif
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* MPU Type Register Bit Definitions */
#define MPUIR_SEPARATE (1 << 0) /* Bit 0: 0:unified or 1:separate memory maps */
#define MPUIR_DREGION_SHIFT (8) /* Bits 8-15: Number MPU data regions */
#define MPUIR_DREGION_MASK (0xff << MPUIR_DREGION_SHIFT)
#define MPUIR_IREGION_SHIFT (16) /* Bits 16-23: Number MPU instruction regions */
#define MPUIR_IREGION_MASK (0xff << MPUIR_IREGION_SHIFT)
/* Region Base Address Register Definitions */
#define MPU_RBAR_MASK 0xfffffffc
/* Region Size and Enable Register */
#define MPU_RASR_ENABLE (1 << 0) /* Bit 0: Region enable */
#define MPU_RASR_RSIZE_SHIFT (1) /* Bits 1-5: Size of the MPU protection region */
#define MPU_RASR_RSIZE_MASK (31 << MPU_RASR_RSIZE_SHIFT)
# define MPU_RASR_RSIZE_LOG2(n) ((n-1) << MPU_RASR_RSIZE_SHIFT)
#define MPU_RASR_SRD_SHIFT (8) /* Bits 8-15: Subregion disable */
#define MPU_RASR_SRD_MASK (0xff << MPU_RASR_SRD_SHIFT)
# define MPU_RASR_SRD_0 (0x01 << MPU_RASR_SRD_SHIFT)
# define MPU_RASR_SRD_1 (0x02 << MPU_RASR_SRD_SHIFT)
# define MPU_RASR_SRD_2 (0x04 << MPU_RASR_SRD_SHIFT)
# define MPU_RASR_SRD_3 (0x08 << MPU_RASR_SRD_SHIFT)
# define MPU_RASR_SRD_4 (0x10 << MPU_RASR_SRD_SHIFT)
# define MPU_RASR_SRD_5 (0x20 << MPU_RASR_SRD_SHIFT)
# define MPU_RASR_SRD_6 (0x40 << MPU_RASR_SRD_SHIFT)
# define MPU_RASR_SRD_7 (0x80 << MPU_RASR_SRD_SHIFT)
/* Region Access Control Register */
#define MPU_RACR_B (1 << 0) /* Bit 0: Bufferable */
#define MPU_RACR_C (1 << 1) /* Bit 1: Cacheable */
#define MPU_RACR_S (1 << 2) /* Bit 2: Shareable */
#define MPU_RACR_TEX_SHIFT (8) /* Bits 0-2: Memory attributes (with C and B) */
#define MPU_RACR_TEX_MASK (7 << MPU_RACR_TEX_SHIFT)
# define MPU_RACR_TEX(n) ((uint32_t)(n) << MPU_RACR_TEX_SHIFT)
#define MPU_RACR_AP_SHIFT (8) /* Bits 8-10: Access permission */
#define MPU_RACR_AP_MASK (7 << MPU_RACR_AP_SHIFT)
# define MPU_RACR_AP_NONO (0 << MPU_RACR_AP_SHIFT) /* PL0:None PL1:None */
# define MPU_RACR_AP_RWNO (1 << MPU_RACR_AP_SHIFT) /* PL0:RW PL1:None */
# define MPU_RACR_AP_RWRO (2 << MPU_RACR_AP_SHIFT) /* PL0:RW PL1:RO */
# define MPU_RACR_AP_RWRW (3 << MPU_RACR_AP_SHIFT) /* PL0:RW PL1:RW */
# define MPU_RACR_AP_RONO (5 << MPU_RACR_AP_SHIFT) /* PL0:RO PL1:None */
# define MPU_RACR_AP_RORO (6 << MPU_RACR_AP_SHIFT) /* PL0:RO PL1:RO */
#define MPU_RACR_XN (1 << 12) /* Bit 12: Instruction access disable */
/* MPU Region Number Register */
#ifdef CONFIG_ARM_MPU_NREGIONS <= 8
# define MPU_RGNR_MASK (0x00000007)
#elif CONFIG_ARM_MPU_NREGIONS <= 16
# define MPU_RGNR_MASK (0x0000000f)
#elif CONFIG_ARM_MPU_NREGIONS <= 32
# define MPU_RGNR_MASK (0x0000001f)
#else
# error "FIXME: Unsupported number of MPU regions"
#endif
/************************************************************************************
* Public Function Prototypes
************************************************************************************/
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Name: mpu_allocregion
*
* Description:
* Allocate the next region
*
****************************************************************************/
unsigned int mpu_allocregion(void);
/****************************************************************************
* Name: mpu_log2regionceil
*
* Description:
* Determine the smallest value of l2size (log base 2 size) such that the
* following is true:
*
* size <= (1 << l2size)
*
****************************************************************************/
uint8_t mpu_log2regionceil(size_t size);
/****************************************************************************
* Name: mpu_log2regionfloor
*
* Description:
* Determine the largest value of l2size (log base 2 size) such that the
* following is true:
*
* size >= (1 << l2size)
*
****************************************************************************/
uint8_t mpu_log2regionfloor(size_t size);
/****************************************************************************
* Name: mpu_subregion
*
* Description:
* Given (1) the offset to the beginning of valid data, (2) the size of the
* memory to be mapped and (2) the log2 size of the mapping to use, determine
* the minimal sub-region set to span that memory region.
*
* Assumption:
* l2size has the same properties as the return value from
* mpu_log2regionceil()
*
****************************************************************************/
uint32_t mpu_subregion(uintptr_t base, size_t size, uint8_t l2size);
/************************************************************************************
* Inline Functions
************************************************************************************/
/****************************************************************************
* Name: mpu_get_mpuir
*
* Description:
* Read the MPUIR register the characteristics of the MPU
*
****************************************************************************/
static inline unsigned int mpu_get_mpuir(void)
{
unsigned int mpuir;
__asm__ __volatile__
(
"\tmrc " CP15_MPUIR(%0)
: "=r" (mpuir)
:
: "memory"
);
return mpuir;
}
/****************************************************************************
* Name: mpu_set_drbar
*
* Description:
* Wrtie to the DRBAR register
*
****************************************************************************/
static inline void mpu_set_drbar(unsigned int drbar)
{
__asm__ __volatile__
(
"\tmcr " CP15_DRBAR(%0)
:
: "r" (drbar)
: "memory"
);
}
/****************************************************************************
* Name: mpu_set_drsr
*
* Description:
* Wrtie to the DRSR register
*
****************************************************************************/
static inline void mpu_set_drsr(unsigned int drsr)
{
__asm__ __volatile__
(
"\tmcr " CP15_DRSR(%0)
:
: "r" (drsr)
: "memory"
);
}
/****************************************************************************
* Name: mpu_set_dracr
*
* Description:
* Wrtie to the DRACR register
*
****************************************************************************/
static inline void mpu_set_dracr(unsigned int dracr)
{
__asm__ __volatile__
(
"\tmcr " CP15_DRACR(%0)
:
: "r" (dracr)
: "memory"
);
}
/****************************************************************************
* Name: mpu_set_irbar
*
* Description:
* Wrtie to the IRBAR register
*
****************************************************************************/
#ifndef CONFIG_ARM_HAVE_MPU_UNIFIED
static inline void mpu_set_irbar(unsigned int irbar)
{
__asm__ __volatile__
(
"\tmcr " CP15_IRBAR(%0)
:
: "r" (irbar)
: "memory"
);
}
#endif
/****************************************************************************
* Name: mpu_set_irsr
*
* Description:
* Wrtie to the IRSR register
*
****************************************************************************/
#ifndef CONFIG_ARM_HAVE_MPU_UNIFIED
static inline void mpu_set_irsr(unsigned int irsr)
{
__asm__ __volatile__
(
"\tmcr " CP15_IRSR(%0)
:
: "r" (irsr)
: "memory"
);
}
#endif
/****************************************************************************
* Name: mpu_set_iracr
*
* Description:
* Wrtie to the IRCR register
*
****************************************************************************/
#ifndef CONFIG_ARM_HAVE_MPU_UNIFIED
static inline void mpu_set_iracr(unsigned int iracr)
{
__asm__ __volatile__
(
"\tmcr " CP15_IRACR(%0)
:
: "r" (iracr)
: "memory"
);
}
#endif
/****************************************************************************
* Name: mpu_set_rgnr
*
* Description:
* Wrtie to the IRCR register
*
****************************************************************************/
static inline void mpu_set_rgnr(unsigned int rgnr)
{
__asm__ __volatile__
(
"\tmcr " CP15_RGNR(%0)
:
: "r" (rgnr)
: "memory"
);
}
/****************************************************************************
* Name: mpu_showtype
*
* Description:
* Show the characteristics of the MPU
*
****************************************************************************/
static inline void mpu_showtype(void)
{
#ifdef CONFIG_DEBUG
uint32_t regval = mpu_get_mpuir();
dbg("%s MPU Regions: data=%d instr=%d\n",
(regval & MPUIR_SEPARATE) != 0 ? "Separate" : "Unified",
(regval & MPUIR_DREGION_MASK) >> MPUIR_DREGION_SHIFT,
(regval & MPUIR_IREGION_MASK) >> MPUIR_IREGION_SHIFT);
#endif
}
/****************************************************************************
* Name: mpu_control
*
* Description:
* Enable (or disable) the MPU
*
****************************************************************************/
static inline void mpu_control(bool enable)
{
uint32_t regval;
/* Set/clear the following bits in the SCTLR:
*
* SCTLR_M Bit 0: MPU enable bit
* SCTLR_BR Bit 17: Background Region bit (not cleared)
*/
regval = cp15_rdsctlr();
if (enable)
{
regval |= (SCTLR_M | SCTLR_BR);
cp15_wrsctlr(regval);
}
else
{
regval &= ~SCTLR_M;
}
cp15_wrsctlr(regval);
}
/****************************************************************************
* Name: mpu_priv_stronglyordered
*
* Description:
* Configure a region for privileged, strongly ordered memory
*
****************************************************************************/
#if defined(CONFIG_ARMV7M_HAVE_ICACHE) || defined(CONFIG_ARMV7M_DCACHE)
static inline void mpu_priv_stronglyordered(uintptr_t base, size_t size)
{
unsigned int region = mpu_allocregion();
uint32_t regval;
uint8_t l2size;
uint8_t subregions;
/* Select the region */
mpu_set_rgnr(region);
/* Select the region base address */
mpu_set_drbar(base & MPU_RBAR_ADDR_MASK) | region | MPU_RBAR_VALID);
/* Select the region size and the sub-region map */
l2size = mpu_log2regionceil(size);
subregions = mpu_subregion(base, size, l2size);
/* The configure the region */
regval = /* Not Cacheable */
/* Not Bufferable */
MPU_RACR_S | /* Shareable */
MPU_RACR_AP_RWNO; /* P:RW U:None */
mpu_set_dracr(regval);
regval = MPU_RASR_ENABLE | /* Enable region */
MPU_RASR_RSIZE_LOG2((uint32_t)l2size) | /* Region size */
((uint32_t)subregions << MPU_RASR_SRD_SHIFT); /* Sub-regions */
mpu_set_drsr(regval);
}
#endif
/****************************************************************************
* Name: mpu_user_flash
*
* Description:
* Configure a region for user program flash
*
****************************************************************************/
static inline void mpu_user_flash(uintptr_t base, size_t size)
{
unsigned int region = mpu_allocregion();
uint32_t regval;
uint8_t l2size;
uint8_t subregions;
/* Select the region */
mpu_set_rgnr(region);
/* Select the region base address */
mpu_set_drbar((base & MPU_RBAR_ADDR_MASK) | region);
/* Select the region size and the sub-region map */
l2size = mpu_log2regionceil(size);
subregions = mpu_subregion(base, size, l2size);
/* The configure the region */
regval = /* Not Cacheable */
MPU_RACR_C | /* Cacheable */
MPU_RACR_AP_RORO; /* P:RO U:RO */
mpu_set_dracr(regval);
regval = MPU_RASR_ENABLE | /* Enable region */
MPU_RASR_RSIZE_LOG2((uint32_t)l2size) | /* Region size */
((uint32_t)subregions << MPU_RASR_SRD_SHIFT); /* Sub-regions */
mpu_set_drsr(regval);
}
/****************************************************************************
* Name: mpu_priv_flash
*
* Description:
* Configure a region for privileged program flash
*
****************************************************************************/
static inline void mpu_priv_flash(uintptr_t base, size_t size)
{
unsigned int region = mpu_allocregion();
uint32_t regval;
uint8_t l2size;
uint8_t subregions;
/* Select the region */
mpu_set_rgnr(region);
/* Select the region base address */
mpu_set_drbar((base & MPU_RBAR_ADDR_MASK) | region);
/* Select the region size and the sub-region map */
l2size = mpu_log2regionceil(size);
subregions = mpu_subregion(base, size, l2size);
/* The configure the region */
regval = MPU_RACR_C | /* Cacheable */
MPU_RACR_AP_RONO; /* P:RO U:None */
mpu_set_dracr(regval);
regval = MPU_RASR_ENABLE | /* Enable region */
MPU_RASR_RSIZE_LOG2((uint32_t)l2size) | /* Region size */
((uint32_t)subregions << MPU_RASR_SRD_SHIFT); /* Sub-regions */
mpu_set_drsr(regval);
}
/****************************************************************************
* Name: mpu_user_intsram
*
* Description:
* Configure a region as user internal SRAM
*
****************************************************************************/
static inline void mpu_user_intsram(uintptr_t base, size_t size)
{
unsigned int region = mpu_allocregion();
uint32_t regval;
uint8_t l2size;
uint8_t subregions;
/* Select the region */
mpu_set_rgnr(region);
/* Select the region base address */
mpu_set_drbar((base & MPU_RBAR_ADDR_MASK) | region);
/* Select the region size and the sub-region map */
l2size = mpu_log2regionceil(size);
subregions = mpu_subregion(base, size, l2size);
/* The configure the region */
regval = MPU_RACR_S | /* Shareable */
MPU_RACR_C | /* Cacheable */
MPU_RACR_AP_RWRW; /* P:RW U:RW */
mpu_set_dracr(regval);
regval = MPU_RASR_ENABLE | /* Enable region */
MPU_RASR_RSIZE_LOG2((uint32_t)l2size) | /* Region size */
((uint32_t)subregions << MPU_RASR_SRD_SHIFT); /* Sub-regions */
mpu_set_drsr(regval);
}
/****************************************************************************
* Name: mpu_priv_intsram
*
* Description:
* Configure a region as privileged internal SRAM
*
****************************************************************************/
static inline void mpu_priv_intsram(uintptr_t base, size_t size)
{
unsigned int region = mpu_allocregion();
uint32_t regval;
uint8_t l2size;
uint8_t subregions;
/* Select the region */
mpu_set_rgnr(region);
/* Select the region base address */
mpu_set_drbar((base & MPU_RBAR_ADDR_MASK) | region);
/* Select the region size and the sub-region map */
l2size = mpu_log2regionceil(size);
subregions = mpu_subregion(base, size, l2size);
/* The configure the region */
regval = MPU_RACR_S | /* Shareable */
MPU_RACR_C | /* Cacheable */
MPU_RACR_AP_RWNO; /* P:RW U:None */
mpu_set_dracr(regval);
regval = MPU_RASR_ENABLE | /* Enable region */
MPU_RASR_RSIZE_LOG2((uint32_t)l2size) | /* Region size */
((uint32_t)subregions << MPU_RASR_SRD_SHIFT); /* Sub-regions */
mpu_set_drsr(regval);
}
/****************************************************************************
* Name: mpu_user_extsram
*
* Description:
* Configure a region as user external SRAM
*
****************************************************************************/
static inline void mpu_user_extsram(uintptr_t base, size_t size)
{
unsigned int region = mpu_allocregion();
uint32_t regval;
uint8_t l2size;
uint8_t subregions;
/* Select the region */
mpu_set_rgnr(region);
/* Select the region base address */
mpu_set_drbar((base & MPU_RBAR_ADDR_MASK) | region);
/* Select the region size and the sub-region map */
l2size = mpu_log2regionceil(size);
subregions = mpu_subregion(base, size, l2size);
/* The configure the region */
regval = MPU_RACR_S | /* Shareable */
MPU_RACR_C | /* Cacheable */
MPU_RACR_B | /* Bufferable */
MPU_RACR_AP_RWRW; /* P:RW U:RW */
mpu_set_dracr(regval);
regval = MPU_RASR_ENABLE | /* Enable region */
MPU_RASR_RSIZE_LOG2((uint32_t)l2size) | /* Region size */
((uint32_t)subregions << MPU_RASR_SRD_SHIFT); /* Sub-regions */
mpu_set_drsr(regval);
}
/****************************************************************************
* Name: mpu_priv_extsram
*
* Description:
* Configure a region as privileged external SRAM
*
****************************************************************************/
static inline void mpu_priv_extsram(uintptr_t base, size_t size)
{
unsigned int region = mpu_allocregion();
uint32_t regval;
uint8_t l2size;
uint8_t subregions;
/* Select the region */
mpu_set_rgnr(region);
/* Select the region base address */
mpu_set_drbar((base & MPU_RBAR_ADDR_MASK) | region);
/* Select the region size and the sub-region map */
l2size = mpu_log2regionceil(size);
subregions = mpu_subregion(base, size, l2size);
/* The configure the region */
regval = MPU_RACR_S | /* Shareable */
MPU_RACR_C | /* Cacheable */
MPU_RACR_B | /* Bufferable */
MPU_RACR_AP_RWNO; /* P:RW U:None */
mpu_set_dracr(regval);
regval = MPU_RASR_ENABLE | /* Enable region */
MPU_RASR_RSIZE_LOG2((uint32_t)l2size) | /* Region size */
((uint32_t)subregions << MPU_RASR_SRD_SHIFT); /* Sub-regions */
mpu_set_drsr(regval);
}
/****************************************************************************
* Name: mpu_peripheral
*
* Description:
* Configure a region as privileged periperal address space
*
****************************************************************************/
static inline void mpu_peripheral(uintptr_t base, size_t size)
{
unsigned int region = mpu_allocregion();
uint32_t regval;
uint8_t l2size;
uint8_t subregions;
/* Select the region */
mpu_set_rgnr(region);
/* Select the region base address */
mpu_set_drbar((base & MPU_RBAR_ADDR_MASK) | region);
/* Select the region size and the sub-region map */
l2size = mpu_log2regionceil(size);
subregions = mpu_subregion(base, size, l2size);
/* Then configure the region */
regval = MPU_RACR_S | /* Shareable */
MPU_RACR_B | /* Bufferable */
MPU_RACR_AP_RWNO | /* P:RW U:None */
MPU_RACR_XN; /* Instruction access disable */
mpu_set_dracr(regval);
regval = MPU_RASR_ENABLE | /* Enable region */
MPU_RASR_RSIZE_LOG2((uint32_t)l2size) | /* Region size */
((uint32_t)subregions << MPU_RASR_SRD_SHIFT); /* Sub-regions */
mpu_set_drsr(regval);
}
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_ARMV7R_MPU_H */

1
arch/arm/src/armv7-r/sctlr.h
View file

@ -131,6 +131,7 @@
/* System Control Register (SCTLR): CRn=c1, opc1=0, CRm=c0, opc2=0
*/
#define SCTLR_M (1 << 0) /* Bit 0: MPU enable bit */
#define SCTLR_A (1 << 1) /* Bit 1: Enables strict alignment of data */
#define SCTLR_C (1 << 2) /* Bit 2: Determines if data can be cached */
/* Bits 3-4: Reserved */