diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_flash.h b/arch/arm/src/stm32l4/hardware/stm32l4_flash.h
index 7261aeb2596..7a14fe18fb8 100644
--- a/arch/arm/src/stm32l4/hardware/stm32l4_flash.h
+++ b/arch/arm/src/stm32l4/hardware/stm32l4_flash.h
@@ -36,9 +36,9 @@
 /* Flash size is known from the chip selection:
  *
  *  When CONFIG_STM32_FLASH_OVERRIDE_DEFAULT is set the
- *  CONFIG_STM32L4_FLASH_CONFIG_x selects the default FLASH size based
+ *  CONFIG_STM32_FLASH_CONFIG_x selects the default FLASH size based
  *  on the chip part number. This value can be overridden with
- *  CONFIG_STM32L4_FLASH_OVERRIDE_x. For example:
+ *  CONFIG_STM32_FLASH_OVERRIDE_x. For example:
  *
  *  Parts STM32L4xxE have 512Kb of FLASH
  *  Parts STM32L4xxG have 1024Kb of FLASH
diff --git a/arch/arm/src/stm32l4/stm32l4_adc.c b/arch/arm/src/stm32l4/stm32l4_adc.c
index c1e4c5730a2..a83d4638b67 100644
--- a/arch/arm/src/stm32l4/stm32l4_adc.c
+++ b/arch/arm/src/stm32l4/stm32l4_adc.c
@@ -2686,7 +2686,7 @@ static void adc_llops_dumpregs(struct stm32_adc_dev_s *dev)
  *   The logic allow initialize ADC regular and injected channels.
  *
  *   The number of injected channels for given ADC is selected from Kconfig
- *   with CONFIG_STM32L4_ADCx_INJECTED_CHAN definitions
+ *   with CONFIG_STM32_ADCx_INJECTED_CHAN definitions
  *
  *   The number of regular channels is obtained from the equation:
  *
@@ -2710,9 +2710,9 @@ static void adc_llops_dumpregs(struct stm32_adc_dev_s *dev)
  *     chanlist[channels]           -> ADC_JSQR_ISQy
  *
  *   where:
- *      y = CONFIG_STM32L4_ADCx_INJECTED_CHAN, and y > 0
+ *      y = CONFIG_STM32_ADCx_INJECTED_CHAN, and y > 0
  *
- *   If CONFIG_STM32L4_ADCx_INJECTED_CHAN = 0, then all channels from
+ *   If CONFIG_STM32_ADCx_INJECTED_CHAN = 0, then all channels from
  *   chanlist are regular channels.
  *
  * Input Parameters:
diff --git a/arch/arm/src/stm32l4/stm32l4_adc.h b/arch/arm/src/stm32l4/stm32l4_adc.h
index 9b4569cc1be..ea303b2705f 100644
--- a/arch/arm/src/stm32l4/stm32l4_adc.h
+++ b/arch/arm/src/stm32l4/stm32l4_adc.h
@@ -40,8 +40,8 @@
 /* Configuration ************************************************************/
 
 /* Timer devices may be used for different purposes.  One special purpose is
- * to control periodic ADC sampling.  If CONFIG_STM32L4_TIMn is defined then
- * CONFIG_STM32L4_TIMn_ADC must also be defined to indicate that timer "n" is
+ * to control periodic ADC sampling.  If CONFIG_STM32_TIMn is defined then
+ * CONFIG_STM32_TIMn_ADC must also be defined to indicate that timer "n" is
  * intended to be used for that purpose. Timers 1,2,3,6 and 15 may be used on
  * STM32L4X3, while STM32L4X6 adds support for timers 4 and 8 as well.
  */
diff --git a/arch/arm/src/stm32l4/stm32l4_allocateheap.c b/arch/arm/src/stm32l4/stm32l4_allocateheap.c
index 2a459135259..d05e804dff9 100644
--- a/arch/arm/src/stm32l4/stm32l4_allocateheap.c
+++ b/arch/arm/src/stm32l4/stm32l4_allocateheap.c
@@ -61,7 +61,7 @@
  * be present in the NuttX configuration file:
  *
  * CONFIG_STM32_FSMC=y      : Enables the FSMC
- * CONFIG_STM32L4_FSMC_SRAM=y : Indicates that SRAM is available via the
+ * CONFIG_STM32_FSMC_SRAM=y : Indicates that SRAM is available via the
  *                              FSMC (as opposed to an LCD or FLASH).
  * CONFIG_HEAP2_BASE          : The base address of the SRAM in the FSMC
  *                              address space
@@ -72,7 +72,7 @@
  */
 
 #ifndef CONFIG_STM32_FSMC
-#  undef CONFIG_STM32L4_FSMC_SRAM
+#  undef CONFIG_STM32_FSMC_SRAM
 #endif
 
 /* STM32L4[7,8]6xx have 128 Kib in two banks, both accessible to DMA:
@@ -118,13 +118,13 @@
 
 #if CONFIG_MM_REGIONS < defined(CONFIG_STM32_SRAM2_HEAP) + \
                         defined(CONFIG_STM32_SRAM3_HEAP) + \
-                        defined(CONFIG_STM32L4_FSMC_SRAM_HEAP) + 1
+                        defined(CONFIG_STM32_FSMC_SRAM_HEAP) + 1
 #  error "You need more memory manager regions to support selected heap components"
 #endif
 
 #if CONFIG_MM_REGIONS > defined(CONFIG_STM32_SRAM2_HEAP) + \
                         defined(CONFIG_STM32_SRAM3_HEAP) + \
-                        defined(CONFIG_STM32L4_FSMC_SRAM_HEAP) + 1
+                        defined(CONFIG_STM32_FSMC_SRAM_HEAP) + 1
 #  warning "CONFIG_MM_REGIONS large enough but I do not know what some of the region(s) are"
 #endif
 
@@ -133,10 +133,10 @@
  * configuration (as CONFIG_HEAP2_BASE and CONFIG_HEAP2_SIZE).
  */
 
-#ifdef CONFIG_STM32L4_FSMC_SRAM
+#ifdef CONFIG_STM32_FSMC_SRAM
 #  if !defined(CONFIG_HEAP2_BASE) || !defined(CONFIG_HEAP2_SIZE)
 #    error "CONFIG_HEAP2_BASE and CONFIG_HEAP2_SIZE must be provided"
-#    undef CONFIG_STM32L4_FSMC_SRAM
+#    undef CONFIG_STM32_FSMC_SRAM
 #  endif
 #endif
 
@@ -352,7 +352,7 @@ void arm_addregion(void)
 
 #endif /* SRAM3 */
 
-#ifdef CONFIG_STM32L4_FSMC_SRAM_HEAP
+#ifdef CONFIG_STM32_FSMC_SRAM_HEAP
 #if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP)
 
   /* Allow user-mode access to the FSMC SRAM user heap memory */
diff --git a/arch/arm/src/stm32l4/stm32l4_dac.c b/arch/arm/src/stm32l4/stm32l4_dac.c
index f6d25a49c6d..2c40fe1339d 100644
--- a/arch/arm/src/stm32l4/stm32l4_dac.c
+++ b/arch/arm/src/stm32l4/stm32l4_dac.c
@@ -277,7 +277,7 @@
 #endif
 
 /* Calculate timer divider values based upon DACn_TIMER_PCLK_FREQUENCY and
- * CONFIG_STM32L4_DACn_TIMER_FREQUENCY.
+ * CONFIG_STM32_DACn_TIMER_FREQUENCY.
  */
 
 #warning "Missing Logic"
diff --git a/arch/arm/src/stm32l4/stm32l4_dac.h b/arch/arm/src/stm32l4/stm32l4_dac.h
index d6b9b1e704b..28ab3dcc962 100644
--- a/arch/arm/src/stm32l4/stm32l4_dac.h
+++ b/arch/arm/src/stm32l4/stm32l4_dac.h
@@ -41,8 +41,8 @@
 /* Configuration ************************************************************/
 
 /* Timer devices may be used for different purposes.  One special purpose is
- * to control periodic DAC outputs.  If CONFIG_STM32L4_TIMn is defined then
- * CONFIG_STM32L4_TIMn_DAC must also be defined to indicate that timer "n"
+ * to control periodic DAC outputs.  If CONFIG_STM32_TIMn is defined then
+ * CONFIG_STM32_TIMn_DAC must also be defined to indicate that timer "n"
  * is intended to be used for that purpose.
  */
 
@@ -71,13 +71,13 @@
 #  undef CONFIG_STM32_TIM8_DAC
 #endif
 #ifndef CONFIG_STM32_TIM15
-#  undef CONFIG_STM32L4_TIM15_DAC
+#  undef CONFIG_STM32_TIM15_DAC
 #endif
 #ifndef CONFIG_STM32_TIM16
-#  undef CONFIG_STM32L4_TIM16_DAC
+#  undef CONFIG_STM32_TIM16_DAC
 #endif
 #ifndef CONFIG_STM32_TIM17
-#  undef CONFIG_STM32L4_TIM17_DAC
+#  undef CONFIG_STM32_TIM17_DAC
 #endif
 
 /* Low-level ops helpers ****************************************************/
diff --git a/arch/arm/src/stm32l4/stm32l4_dfsdm.c b/arch/arm/src/stm32l4/stm32l4_dfsdm.c
index 82472993748..a60bff7bb14 100644
--- a/arch/arm/src/stm32l4/stm32l4_dfsdm.c
+++ b/arch/arm/src/stm32l4/stm32l4_dfsdm.c
@@ -282,11 +282,11 @@ static struct stm32_dev_s g_dfsdmpriv0 =
   .intf        = 0,
   .base        = STM32_DFSDM_BASE,
 #ifdef DFSDM_HAVE_TIMER
-  .trigger     = CONFIG_STM32L4_DFSDM_TIMTRIG,
+  .trigger     = CONFIG_STM32_DFSDM_TIMTRIG,
   .tbase       = DFSDM_TIMER_BASE,
   .extsel      = DFSDM_JEXTSEL_VALUE,
   .pclck       = DFSDM_TIMER_PCLK_FREQUENCY,
-  .freq        = CONFIG_STM32L4_DFSDM_SAMPLE_FREQUENCY,
+  .freq        = CONFIG_STM32_DFSDM_SAMPLE_FREQUENCY,
 #endif
 #ifdef DFSDM_HAVE_DMA
   .dmachan     = DMACHAN_DFSDM0,
@@ -311,11 +311,11 @@ static struct stm32_dev_s g_dfsdmpriv1 =
   .intf        = 1,
   .base        = STM32_DFSDM_BASE,
 #ifdef DFSDM_HAVE_TIMER
-  .trigger     = CONFIG_STM32L4_DFSDM_TIMTRIG,
+  .trigger     = CONFIG_STM32_DFSDM_TIMTRIG,
   .tbase       = DFSDM_TIMER_BASE,
   .extsel      = DFSDM_JEXTSEL_VALUE,
   .pclck       = DFSDM_TIMER_PCLK_FREQUENCY,
-  .freq        = CONFIG_STM32L4_DFSDM_SAMPLE_FREQUENCY,
+  .freq        = CONFIG_STM32_DFSDM_SAMPLE_FREQUENCY,
 #endif
 #ifdef DFSDM_HAVE_DMA
   .dmachan     = DMACHAN_DFSDM1,
@@ -340,11 +340,11 @@ static struct stm32_dev_s g_dfsdmpriv2 =
   .intf        = 0,
   .base        = STM32_DFSDM_BASE,
 #ifdef DFSDM_HAVE_TIMER
-  .trigger     = CONFIG_STM32L4_DFSDM_TIMTRIG,
+  .trigger     = CONFIG_STM32_DFSDM_TIMTRIG,
   .tbase       = DFSDM_TIMER_BASE,
   .extsel      = DFSDM_JEXTSEL_VALUE,
   .pclck       = DFSDM_TIMER_PCLK_FREQUENCY,
-  .freq        = CONFIG_STM32L4_DFSDM_SAMPLE_FREQUENCY,
+  .freq        = CONFIG_STM32_DFSDM_SAMPLE_FREQUENCY,
 #endif
 #ifdef DFSDM_HAVE_DMA
   .dmachan     = DMACHAN_DFSDM2,
@@ -369,11 +369,11 @@ static struct stm32_dev_s g_dfsdmpriv3 =
   .intf        = 0,
   .base        = STM32_DFSDM_BASE,
 #ifdef DFSDM_HAVE_TIMER
-  .trigger     = CONFIG_STM32L4_DFSDM_TIMTRIG,
+  .trigger     = CONFIG_STM32_DFSDM_TIMTRIG,
   .tbase       = DFSDM_TIMER_BASE,
   .extsel      = DFSDM_JEXTSEL_VALUE,
   .pclck       = DFSDM_TIMER_PCLK_FREQUENCY,
-  .freq        = CONFIG_STM32L4_DFSDM_SAMPLE_FREQUENCY,
+  .freq        = CONFIG_STM32_DFSDM_SAMPLE_FREQUENCY,
 #endif
 #ifdef DFSDM_HAVE_DMA
   .dmachan     = DMACHAN_DFSDM3,
diff --git a/arch/arm/src/stm32l4/stm32l4_dfsdm.h b/arch/arm/src/stm32l4/stm32l4_dfsdm.h
index ae4dbd6729f..c623f9234e2 100644
--- a/arch/arm/src/stm32l4/stm32l4_dfsdm.h
+++ b/arch/arm/src/stm32l4/stm32l4_dfsdm.h
@@ -39,32 +39,32 @@
 /* Configuration ************************************************************/
 
 /* Timer devices may be used for different purposes.  One special purpose is
- * to control periodic ADC sampling.  If CONFIG_STM32L4_TIMn is defined then
- * CONFIG_STM32L4_TIMn_DFSDM must also be defined to indicate that timer "n"
+ * to control periodic ADC sampling.  If CONFIG_STM32_TIMn is defined then
+ * CONFIG_STM32_TIMn_DFSDM must also be defined to indicate that timer "n"
  * is intended to be used for that purpose. Timers 1,3,6 and 16 may be used
  * on STM32L4X3, while STM32L4X6 adds support for timers 4,7 and 8 as well.
  */
 
 #ifndef CONFIG_STM32_TIM1
-#  undef CONFIG_STM32L4_TIM1_DFSDM
+#  undef CONFIG_STM32_TIM1_DFSDM
 #endif
 #ifndef CONFIG_STM32_TIM3
-#  undef CONFIG_STM32L4_TIM3_DFSDM
+#  undef CONFIG_STM32_TIM3_DFSDM
 #endif
 #ifndef CONFIG_STM32_TIM4
-#  undef CONFIG_STM32L4_TIM4_DFSDM
+#  undef CONFIG_STM32_TIM4_DFSDM
 #endif
 #ifndef CONFIG_STM32_TIM6
-#  undef CONFIG_STM32L4_TIM6_DFSDM
+#  undef CONFIG_STM32_TIM6_DFSDM
 #endif
 #ifndef CONFIG_STM32_TIM7
-#  undef CONFIG_STM32L4_TIM7_DFSDM
+#  undef CONFIG_STM32_TIM7_DFSDM
 #endif
 #ifndef CONFIG_STM32_TIM8
-#  undef CONFIG_STM32L4_TIM8_DFSDM
+#  undef CONFIG_STM32_TIM8_DFSDM
 #endif
 #ifndef CONFIG_STM32_TIM16
-#  undef CONFIG_STM32L4_TIM16_DFSDM
+#  undef CONFIG_STM32_TIM16_DFSDM
 #endif
 
 #if defined(CONFIG_STM32_DFSDM)
@@ -89,31 +89,31 @@
  * information about the timer.
  */
 
-#if defined(CONFIG_STM32L4_TIM1_DFSDM)
+#if defined(CONFIG_STM32_TIM1_DFSDM)
 #    define DFSDM_HAVE_TIMER           1
 #    define DFSDM_TIMER_BASE           STM32_TIM1_BASE
 #    define DFSDM_TIMER_PCLK_FREQUENCY STM32_TIM1_CLKIN
-#elif defined(CONFIG_STM32L4_TIM3_DFSDM)
+#elif defined(CONFIG_STM32_TIM3_DFSDM)
 #    define DFSDM_HAVE_TIMER           1
 #    define DFSDM_TIMER_BASE           STM32_TIM3_BASE
 #    define DFSDM_TIMER_PCLK_FREQUENCY STM32_TIM3_CLKIN
-#elif defined(CONFIG_STM32L4_TIM4_DFSDM)
+#elif defined(CONFIG_STM32_TIM4_DFSDM)
 #    define DFSDM_HAVE_TIMER           1
 #    define DFSDM_TIMER_BASE           STM32_TIM4_BASE
 #    define DFSDM_TIMER_PCLK_FREQUENCY STM32_TIM4_CLKIN
-#elif defined(CONFIG_STM32L4_TIM6_DFSDM)
+#elif defined(CONFIG_STM32_TIM6_DFSDM)
 #    define DFSDM_HAVE_TIMER           1
 #    define DFSDM_TIMER_BASE           STM32_TIM6_BASE
 #    define DFSDM_TIMER_PCLK_FREQUENCY STM32_TIM6_CLKIN
-#elif defined(CONFIG_STM32L4_TIM7_DFSDM)
+#elif defined(CONFIG_STM32_TIM7_DFSDM)
 #    define DFSDM_HAVE_TIMER           1
 #    define DFSDM_TIMER_BASE           STM32_TIM7_BASE
 #    define DFSDM_TIMER_PCLK_FREQUENCY STM32_TIM7_CLKIN
-#elif defined(CONFIG_STM32L4_TIM8_DFSDM)
+#elif defined(CONFIG_STM32_TIM8_DFSDM)
 #    define DFSDM_HAVE_TIMER           1
 #    define DFSDM_TIMER_BASE           STM32_TIM8_BASE
 #    define DFSDM_TIMER_PCLK_FREQUENCY STM32_TIM8_CLKIN
-#elif defined(CONFIG_STM32L4_TIM16_DFSDM)
+#elif defined(CONFIG_STM32_TIM16_DFSDM)
 #    define DFSDM_HAVE_TIMER           1
 #    define DFSDM_TIMER_BASE           STM32_TIM16_BASE
 #    define DFSDM_TIMER_PCLK_FREQUENCY STM32_TIM16_CLKIN
@@ -122,11 +122,11 @@
 #endif
 
 #ifdef DFSDM_HAVE_TIMER
-#  ifndef CONFIG_STM32L4_DFSDM_SAMPLE_FREQUENCY
-#    error "CONFIG_STM32L4_DFSDM_SAMPLE_FREQUENCY not defined"
+#  ifndef CONFIG_STM32_DFSDM_SAMPLE_FREQUENCY
+#    error "CONFIG_STM32_DFSDM_SAMPLE_FREQUENCY not defined"
 #  endif
-#  ifndef CONFIG_STM32L4_DFSDM_TIMTRIG
-#    error "CONFIG_STM32L4_DFSDM_TIMTRIG not defined"
+#  ifndef CONFIG_STM32_DFSDM_TIMTRIG
+#    error "CONFIG_STM32_DFSDM_TIMTRIG not defined"
 #    warning "Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO 5:TRGO2"
 #  endif
 #endif
@@ -184,107 +184,107 @@
 #define DFSDM_JEXTSEL_T16CC4     DFSDM_FLTCR1_JEXTSEL_T16CC4
 #define DFSDM_JEXTSEL_T16TRGO    DFSDM_FLTCR1_JEXTSEL_T16TRGO
 
-#if defined(CONFIG_STM32L4_TIM1_DFSDM)
-#  if CONFIG_STM32L4_DFSDM_TIMTRIG == 0
+#if defined(CONFIG_STM32_TIM1_DFSDM)
+#  if CONFIG_STM32_DFSDM_TIMTRIG == 0
 #    define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T1CC1
-#  elif CONFIG_STM32L4_DFSDM_TIMTRIG == 1
+#  elif CONFIG_STM32_DFSDM_TIMTRIG == 1
 #    define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T1CC2
-#  elif CONFIG_STM32L4_DFSDM_TIMTRIG == 2
+#  elif CONFIG_STM32_DFSDM_TIMTRIG == 2
 #    define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T1CC3
-#  elif CONFIG_STM32L4_DFSDM_TIMTRIG == 3
+#  elif CONFIG_STM32_DFSDM_TIMTRIG == 3
 #    define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T1CC4
-#  elif CONFIG_STM32L4_DFSDM_TIMTRIG == 4
+#  elif CONFIG_STM32_DFSDM_TIMTRIG == 4
 #    define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T1TRGO
-#  elif CONFIG_STM32L4_DFSDM_TIMTRIG == 5
+#  elif CONFIG_STM32_DFSDM_TIMTRIG == 5
 #    define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T1TRGO2
 #  else
-#    error "CONFIG_STM32L4_DFSDM_TIMTRIG is out of range"
+#    error "CONFIG_STM32_DFSDM_TIMTRIG is out of range"
 #  endif
-#elif defined(CONFIG_STM32L4_TIM3_DFSDM)
-#  if CONFIG_STM32L4_DFSDM_TIMTRIG == 0
+#elif defined(CONFIG_STM32_TIM3_DFSDM)
+#  if CONFIG_STM32_DFSDM_TIMTRIG == 0
 #    define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T3CC1
-#  elif CONFIG_STM32L4_DFSDM_TIMTRIG == 1
+#  elif CONFIG_STM32_DFSDM_TIMTRIG == 1
 #    define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T3CC2
-#  elif CONFIG_STM32L4_DFSDM_TIMTRIG == 2
+#  elif CONFIG_STM32_DFSDM_TIMTRIG == 2
 #    define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T3CC3
-#  elif CONFIG_STM32L4_DFSDM_TIMTRIG == 3
+#  elif CONFIG_STM32_DFSDM_TIMTRIG == 3
 #    define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T3CC4
-#  elif CONFIG_STM32L4_DFSDM_TIMTRIG == 4
+#  elif CONFIG_STM32_DFSDM_TIMTRIG == 4
 #    define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T3TRGO
 #  else
-#    error "CONFIG_STM32L4_DFSDM_TIMTRIG is out of range"
+#    error "CONFIG_STM32_DFSDM_TIMTRIG is out of range"
 #  endif
-#elif defined(CONFIG_STM32L4_TIM4_DFSDM)
-#  if CONFIG_STM32L4_DFSDM_TIMTRIG == 0
+#elif defined(CONFIG_STM32_TIM4_DFSDM)
+#  if CONFIG_STM32_DFSDM_TIMTRIG == 0
 #    define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T4CC1
-#  elif CONFIG_STM32L4_DFSDM_TIMTRIG == 1
+#  elif CONFIG_STM32_DFSDM_TIMTRIG == 1
 #    define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T4CC2
-#  elif CONFIG_STM32L4_DFSDM_TIMTRIG == 2
+#  elif CONFIG_STM32_DFSDM_TIMTRIG == 2
 #    define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T4CC3
-#  elif CONFIG_STM32L4_DFSDM_TIMTRIG == 3
+#  elif CONFIG_STM32_DFSDM_TIMTRIG == 3
 #    define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T4CC4
-#  elif CONFIG_STM32L4_DFSDM_TIMTRIG == 4
+#  elif CONFIG_STM32_DFSDM_TIMTRIG == 4
 #    define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T4TRGO
 #  else
-#    error "CONFIG_STM32L4_DFSDM_TIMTRIG is out of range"
+#    error "CONFIG_STM32_DFSDM_TIMTRIG is out of range"
 #  endif
-#elif defined(CONFIG_STM32L4_TIM6_DFSDM)
-#  if CONFIG_STM32L4_DFSDM_TIMTRIG == 0
+#elif defined(CONFIG_STM32_TIM6_DFSDM)
+#  if CONFIG_STM32_DFSDM_TIMTRIG == 0
 #    define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T6CC1
-#  elif CONFIG_STM32L4_DFSDM_TIMTRIG == 1
+#  elif CONFIG_STM32_DFSDM_TIMTRIG == 1
 #    define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T6CC2
-#  elif CONFIG_STM32L4_DFSDM_TIMTRIG == 2
+#  elif CONFIG_STM32_DFSDM_TIMTRIG == 2
 #    define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T6CC3
-#  elif CONFIG_STM32L4_DFSDM_TIMTRIG == 3
+#  elif CONFIG_STM32_DFSDM_TIMTRIG == 3
 #    define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T6CC4
-#  elif CONFIG_STM32L4_DFSDM_TIMTRIG == 4
+#  elif CONFIG_STM32_DFSDM_TIMTRIG == 4
 #    define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T6TRGO
 #  else
-#    error "CONFIG_STM32L4_DFSDM_TIMTRIG is out of range"
+#    error "CONFIG_STM32_DFSDM_TIMTRIG is out of range"
 #  endif
-#elif defined(CONFIG_STM32L4_TIM7_DFSDM)
-#  if CONFIG_STM32L4_DFSDM_TIMTRIG == 0
+#elif defined(CONFIG_STM32_TIM7_DFSDM)
+#  if CONFIG_STM32_DFSDM_TIMTRIG == 0
 #    define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T7CC1
-#  elif CONFIG_STM32L4_DFSDM_TIMTRIG == 1
+#  elif CONFIG_STM32_DFSDM_TIMTRIG == 1
 #    define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T7CC2
-#  elif CONFIG_STM32L4_DFSDM_TIMTRIG == 2
+#  elif CONFIG_STM32_DFSDM_TIMTRIG == 2
 #    define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T7CC3
-#  elif CONFIG_STM32L4_DFSDM_TIMTRIG == 3
+#  elif CONFIG_STM32_DFSDM_TIMTRIG == 3
 #    define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T7CC4
-#  elif CONFIG_STM32L4_DFSDM_TIMTRIG == 4
+#  elif CONFIG_STM32_DFSDM_TIMTRIG == 4
 #    define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T7TRGO
 #  else
-#    error "CONFIG_STM32L4_DFSDM_TIMTRIG is out of range"
+#    error "CONFIG_STM32_DFSDM_TIMTRIG is out of range"
 #  endif
-#elif defined(CONFIG_STM32L4_TIM8_DFSDM)
-#  if CONFIG_STM32L4_DFSDM_TIMTRIG == 0
+#elif defined(CONFIG_STM32_TIM8_DFSDM)
+#  if CONFIG_STM32_DFSDM_TIMTRIG == 0
 #    define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T8CC1
-#  elif CONFIG_STM32L4_DFSDM_TIMTRIG == 1
+#  elif CONFIG_STM32_DFSDM_TIMTRIG == 1
 #    define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T8CC2
-#  elif CONFIG_STM32L4_DFSDM_TIMTRIG == 2
+#  elif CONFIG_STM32_DFSDM_TIMTRIG == 2
 #    define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T8CC3
-#  elif CONFIG_STM32L4_DFSDM_TIMTRIG == 3
+#  elif CONFIG_STM32_DFSDM_TIMTRIG == 3
 #    define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T8CC4
-#  elif CONFIG_STM32L4_DFSDM_TIMTRIG == 4
+#  elif CONFIG_STM32_DFSDM_TIMTRIG == 4
 #    define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T8TRGO
-#  elif CONFIG_STM32L4_DFSDM_TIMTRIG == 5
+#  elif CONFIG_STM32_DFSDM_TIMTRIG == 5
 #    define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T8TRGO2
 #  else
-#    error "CONFIG_STM32L4_DFSDM_TIMTRIG is out of range"
+#    error "CONFIG_STM32_DFSDM_TIMTRIG is out of range"
 #  endif
-#elif defined(CONFIG_STM32L4_TIM16_DFSDM)
-#  if CONFIG_STM32L4_DFSDM_TIMTRIG == 0
+#elif defined(CONFIG_STM32_TIM16_DFSDM)
+#  if CONFIG_STM32_DFSDM_TIMTRIG == 0
 #    define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T16CC1
-#  elif CONFIG_STM32L4_DFSDM_TIMTRIG == 1
+#  elif CONFIG_STM32_DFSDM_TIMTRIG == 1
 #    define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T16CC2
-#  elif CONFIG_STM32L4_DFSDM_TIMTRIG == 2
+#  elif CONFIG_STM32_DFSDM_TIMTRIG == 2
 #    define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T16CC3
-#  elif CONFIG_STM32L4_DFSDM_TIMTRIG == 3
+#  elif CONFIG_STM32_DFSDM_TIMTRIG == 3
 #    define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T16CC4
-#  elif CONFIG_STM32L4_DFSDM_TIMTRIG == 4
+#  elif CONFIG_STM32_DFSDM_TIMTRIG == 4
 #    define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T16TRGO
 #  else
-#    error "CONFIG_STM32L4_DFSDM_TIMTRIG is out of range"
+#    error "CONFIG_STM32_DFSDM_TIMTRIG is out of range"
 #  endif
 #endif
 
diff --git a/arch/arm/src/stm32l4/stm32l4_iwdg.c b/arch/arm/src/stm32l4/stm32l4_iwdg.c
index 833283f7810..13df82a38ae 100644
--- a/arch/arm/src/stm32l4/stm32l4_iwdg.c
+++ b/arch/arm/src/stm32l4/stm32l4_iwdg.c
@@ -70,12 +70,12 @@
 
 /* Configuration ************************************************************/
 
-#ifndef CONFIG_STM32L4_IWDG_DEFTIMOUT
-#  define CONFIG_STM32L4_IWDG_DEFTIMOUT IWDG_MAXTIMEOUT
+#ifndef CONFIG_STM32_IWDG_DEFTIMOUT
+#  define CONFIG_STM32_IWDG_DEFTIMOUT IWDG_MAXTIMEOUT
 #endif
 
 #ifndef CONFIG_DEBUG_WATCHDOG_INFO
-#  undef CONFIG_STM32L4_IWDG_REGDEBUG
+#  undef CONFIG_STM32_IWDG_REGDEBUG
 #endif
 
 /****************************************************************************
diff --git a/arch/arm/src/stm32l4/stm32l4_otgfsdev.c b/arch/arm/src/stm32l4/stm32l4_otgfsdev.c
index bf1cbe30796..af2df0c32ad 100644
--- a/arch/arm/src/stm32l4/stm32l4_otgfsdev.c
+++ b/arch/arm/src/stm32l4/stm32l4_otgfsdev.c
@@ -5925,4 +5925,4 @@ int usbdev_unregister(struct usbdevclass_driver_s *driver)
   return OK;
 }
 
-#endif /* CONFIG_USBDEV && CONFIG_STM32L4_OTGFSDEV */
+#endif /* CONFIG_USBDEV && CONFIG_STM32_OTGFSDEV */
diff --git a/arch/arm/src/stm32l4/stm32l4_otgfshost.c b/arch/arm/src/stm32l4/stm32l4_otgfshost.c
index 0d28603efda..af49eeca62f 100644
--- a/arch/arm/src/stm32l4/stm32l4_otgfshost.c
+++ b/arch/arm/src/stm32l4/stm32l4_otgfshost.c
@@ -5352,7 +5352,7 @@ static inline int stm32_hw_initialize(struct stm32_usbhost_s *priv)
 #ifndef CONFIG_USBDEV_VBUSSENSING
   regval |= OTGFS_GCCFG_NOVBUSSENS;
 #endif
-#ifdef CONFIG_STM32L4_OTGFS_SOFOUTPUT
+#ifdef CONFIG_STM32_OTG_SOFOUTPUT
   regval |= OTGFS_GCCFG_SOFOUTEN;
 #endif
   stm32_putreg(STM32_OTGFS_GCCFG, regval);
diff --git a/arch/arm/src/stm32l4/stm32l4_pwm.c b/arch/arm/src/stm32l4/stm32l4_pwm.c
index ca5fa299d97..d561662efaa 100644
--- a/arch/arm/src/stm32l4/stm32l4_pwm.c
+++ b/arch/arm/src/stm32l4/stm32l4_pwm.c
@@ -115,10 +115,10 @@
 
 /* Break support */
 
-#if defined(CONFIG_STM32L4_TIM1_BREAK1) || defined(CONFIG_STM32L4_TIM1_BREAK2) || \
-    defined(CONFIG_STM32L4_TIM8_BREAK1) || defined(CONFIG_STM32L4_TIM8_BREAK2) || \
-    defined(CONFIG_STM32L4_TIM15_BREAK1) || defined(CONFIG_STM32L4_TIM16_BREAK1) || \
-    defined(CONFIG_STM32L4_TIM17_BREAK1)
+#if defined(CONFIG_STM32_TIM1_BREAK1) || defined(CONFIG_STM32_TIM1_BREAK2) || \
+    defined(CONFIG_STM32_TIM8_BREAK1) || defined(CONFIG_STM32_TIM8_BREAK2) || \
+    defined(CONFIG_STM32_TIM15_BREAK1) || defined(CONFIG_STM32_TIM16_BREAK1) || \
+    defined(CONFIG_STM32_TIM17_BREAK1)
 #  defined HAVE_BREAK
 #endif
 
@@ -309,14 +309,14 @@ static struct stm32_pwmchan_s g_pwm1channels[] =
 #ifdef HAVE_BREAK
     .brk =
     {
-#ifdef CONFIG_STM32L4_TIM1_BREAK1
+#ifdef CONFIG_STM32_TIM1_BREAK1
       .en1 = 1,
-      .pol1 = CONFIG_STM32L4_TIM1_BRK1POL,
+      .pol1 = CONFIG_STM32_TIM1_BRK1POL,
 #endif
-#ifdef CONFIG_STM32L4_TIM1_BREAK2
+#ifdef CONFIG_STM32_TIM1_BREAK2
       .en2 = 1,
-      .pol2 = CONFIG_STM32L4_TIM1_BRK2POL,
-      .flt2 = CONFIG_STM32L4_TIM1_BRK2FLT,
+      .pol2 = CONFIG_STM32_TIM1_BRK2POL,
+      .flt2 = CONFIG_STM32_TIM1_BRK2FLT,
 #endif
     },
 #endif
@@ -855,14 +855,14 @@ static struct stm32_pwmchan_s g_pwm8channels[] =
 #ifdef HAVE_BREAK
     .brk =
     {
-#ifdef CONFIG_STM32L4_TIM8_BREAK1
+#ifdef CONFIG_STM32_TIM8_BREAK1
       .en1 = 1,
-      .pol1 = CONFIG_STM32L4_TIM8_BRK1POL,
+      .pol1 = CONFIG_STM32_TIM8_BRK1POL,
 #endif
-#ifdef CONFIG_STM32L4_TIM8_BREAK2
+#ifdef CONFIG_STM32_TIM8_BREAK2
       .en2 = 1,
-      .pol2 = CONFIG_STM32L4_TIM8_BRK2POL,
-      .flt2 = CONFIG_STM32L4_TIM8_BRK2FLT,
+      .pol2 = CONFIG_STM32_TIM8_BRK2POL,
+      .flt2 = CONFIG_STM32_TIM8_BRK2FLT,
 #endif
     },
 #endif
@@ -1018,9 +1018,9 @@ static struct stm32_pwmchan_s g_pwm15channels[] =
 #ifdef HAVE_BREAK
     .brk =
     {
-#ifdef CONFIG_STM32L4_TIM15_BREAK1
+#ifdef CONFIG_STM32_TIM15_BREAK1
       .en1 = 1,
-      .pol1 = CONFIG_STM32L4_TIM15_BRK1POL,
+      .pol1 = CONFIG_STM32_TIM15_BRK1POL,
 #endif
       /* No BREAK2 */
     },
@@ -1100,9 +1100,9 @@ static struct stm32_pwmchan_s g_pwm16channels[] =
 #ifdef HAVE_BREAK
     .brk =
     {
-#ifdef CONFIG_STM32L4_TIM16_BREAK1
+#ifdef CONFIG_STM32_TIM16_BREAK1
       .en1 = 1,
-      .pol1 = CONFIG_STM32L4_TIM16_BRK1POL,
+      .pol1 = CONFIG_STM32_TIM16_BRK1POL,
 #endif
       /* No BREAK2 */
     },
@@ -1120,8 +1120,8 @@ static struct stm32_pwmchan_s g_pwm16channels[] =
     .out2    =
     {
       .in_use  = 1,
-      .pol     = CONFIG_STM32L4_TIM16_CH1NPOL,
-      .idle    = CONFIG_STM32L4_TIM16_CH1NIDLE,
+      .pol     = CONFIG_STM32_TIM16_CH1NPOL,
+      .idle    = CONFIG_STM32_TIM16_CH1NIDLE,
       .pincfg  = PWM_TIM16_CH2CFG,
     }
 #endif
@@ -1166,9 +1166,9 @@ static struct stm32_pwmchan_s g_pwm17channels[] =
 #ifdef HAVE_BREAK
     .brk =
     {
-#ifdef CONFIG_STM32L4_TIM17_BREAK1
+#ifdef CONFIG_STM32_TIM17_BREAK1
       .en1 = 1,
-      .pol1 = CONFIG_STM32L4_TIM17_BRK1POL,
+      .pol1 = CONFIG_STM32_TIM17_BRK1POL,
 #endif
       /* No BREAK2 */
     },
@@ -1186,8 +1186,8 @@ static struct stm32_pwmchan_s g_pwm17channels[] =
     .out2    =
     {
       .in_use  = 1,
-      .pol     = CONFIG_STM32L4_TIM17_CH1NPOL,
-      .idle    = CONFIG_STM32L4_TIM17_CH1NIDLE,
+      .pol     = CONFIG_STM32_TIM17_CH1NPOL,
+      .idle    = CONFIG_STM32_TIM17_CH1NIDLE,
       .pincfg  = PWM_TIM17_CH2CFG,
     }
 #endif
@@ -1233,7 +1233,7 @@ static struct stm32_pwmchan_s g_pwmlp1channels[] =
     .out1    =
     {
       .in_use  = 1,
-      .pol     = 0,             /* REVISIT: Configure using CONFIG_STM32L4_LPTIM1_CH1POL, */
+      .pol     = 0,             /* REVISIT: Configure using CONFIG_STM32_LPTIM1_CH1POL, */
       .idle    = 0,             /* No idle */
       .pincfg  = PWM_LPTIM1_CH1CFG,
     }
@@ -1289,7 +1289,7 @@ static struct stm32_pwmchan_s g_pwmlp2channels[] =
     .out1    =
     {
       .in_use  = 1,
-      .pol     = 0,             /* REVISIT: Configure using CONFIG_STM32L4_LPTIM2_CH1POL, */
+      .pol     = 0,             /* REVISIT: Configure using CONFIG_STM32_LPTIM2_CH1POL, */
       .idle    = 0,             /* No idle */
       .pincfg  = PWM_LPTIM2_CH1CFG,
     }
@@ -3820,4 +3820,4 @@ struct pwm_lowerhalf_s *stm32_lp_pwminitialize(int timer)
 }
 #endif /* HAVE_LPTIM */
 
-#endif /* CONFIG_STM32L4_TIMn_PWM, n = 1,...,17 */
+#endif /* CONFIG_STM32_TIMn_PWM, n = 1,...,17 */
diff --git a/arch/arm/src/stm32l4/stm32l4_pwm.h b/arch/arm/src/stm32l4/stm32l4_pwm.h
index 26e52e0dc61..71fa1ed1468 100644
--- a/arch/arm/src/stm32l4/stm32l4_pwm.h
+++ b/arch/arm/src/stm32l4/stm32l4_pwm.h
@@ -93,8 +93,8 @@
  *  pulses.
  */
 
-#undef CONFIG_STM32L4_TIM6_PWM
-#undef CONFIG_STM32L4_TIM7_PWM
+#undef CONFIG_STM32_TIM6_PWM
+#undef CONFIG_STM32_TIM7_PWM
 
 /* Check if PWM support for any channel is enabled. */
 
diff --git a/arch/arm/src/stm32l4/stm32l4_qencoder.h b/arch/arm/src/stm32l4/stm32l4_qencoder.h
index 4b07b1fd42a..c54e198eb46 100644
--- a/arch/arm/src/stm32l4/stm32l4_qencoder.h
+++ b/arch/arm/src/stm32l4/stm32l4_qencoder.h
@@ -38,8 +38,8 @@
  ****************************************************************************/
 
 /* Timer devices may be used for different purposes.  One special purpose is
- * as a quadrature encoder input device.  If CONFIG_STM32L4_TIMn is defined
- * then the CONFIG_STM32L4_TIMn_QE must also be defined to indicate that
+ * as a quadrature encoder input device.  If CONFIG_STM32_TIMn is defined
+ * then the CONFIG_STM32_TIMn_QE must also be defined to indicate that
  * timer "n" is intended to be used for as a quadrature encoder.
  */
 
@@ -65,14 +65,14 @@
 /* Only timers 2-5, and 1 & 8 can be used as a quadrature encoder
  */
 
-#undef CONFIG_STM32L4_TIM6_QE
-#undef CONFIG_STM32L4_TIM7_QE
-#undef CONFIG_STM32L4_TIM9_QE
-#undef CONFIG_STM32L4_TIM10_QE
-#undef CONFIG_STM32L4_TIM11_QE
-#undef CONFIG_STM32L4_TIM12_QE
-#undef CONFIG_STM32L4_TIM13_QE
-#undef CONFIG_STM32L4_TIM14_QE
+#undef CONFIG_STM32_TIM6_QE
+#undef CONFIG_STM32_TIM7_QE
+#undef CONFIG_STM32_TIM9_QE
+#undef CONFIG_STM32_TIM10_QE
+#undef CONFIG_STM32_TIM11_QE
+#undef CONFIG_STM32_TIM12_QE
+#undef CONFIG_STM32_TIM13_QE
+#undef CONFIG_STM32_TIM14_QE
 
 /****************************************************************************
  * Included Files
diff --git a/arch/arm/src/stm32l4/stm32l4_sai.c b/arch/arm/src/stm32l4/stm32l4_sai.c
index bb68784d21e..04c5f8759ea 100644
--- a/arch/arm/src/stm32l4/stm32l4_sai.c
+++ b/arch/arm/src/stm32l4/stm32l4_sai.c
@@ -89,29 +89,29 @@
 #  error "Interrupt driven SAI not yet supported"
 #endif
 
-#ifndef CONFIG_STM32L4_SAI_DEFAULT_SAMPLERATE
-#  define CONFIG_STM32L4_SAI_DEFAULT_SAMPLERATE  (48000)
+#ifndef CONFIG_STM32_SAI_DEFAULT_SAMPLERATE
+#  define CONFIG_STM32_SAI_DEFAULT_SAMPLERATE  (48000)
 #endif
 
-#ifndef CONFIG_STM32L4_SAI_DEFAULT_DATALEN
-#  define CONFIG_STM32L4_SAI_DEFAULT_DATALEN     (16)
+#ifndef CONFIG_STM32_SAI_DEFAULT_DATALEN
+#  define CONFIG_STM32_SAI_DEFAULT_DATALEN     (16)
 #endif
 
-#ifndef CONFIG_STM32L4_SAI_MAXINFLIGHT
-#  define CONFIG_STM32L4_SAI_MAXINFLIGHT         (16)
+#ifndef CONFIG_STM32_SAI_MAXINFLIGHT
+#  define CONFIG_STM32_SAI_MAXINFLIGHT         (16)
 #endif
 
 #ifdef CONFIG_STM32_SAI_DMA
 /* SAI DMA priority */
 
-#  if defined(CONFIG_STM32L4_SAI_DMAPRIO)
-#    define SAI_DMA_PRIO       CONFIG_STM32L4_SAI_DMAPRIO
+#  if defined(CONFIG_STM32_SAI_DMAPRIO)
+#    define SAI_DMA_PRIO       CONFIG_STM32_SAI_DMAPRIO
 #  else
 #    define SAI_DMA_PRIO       DMA_CCR_PRIMED
 #  endif
 
 #  if (SAI_DMA_PRIO & ~DMA_CCR_PL_MASK) != 0
-#    error "Illegal value for CONFIG_STM32L4_SAI_DMAPRIO"
+#    error "Illegal value for CONFIG_STM32_SAI_DMAPRIO"
 #  endif
 
 /* DMA channel configuration */
@@ -168,7 +168,7 @@ struct stm32_sai_s
 
   sem_t bufsem;                   /* Buffer wait semaphore */
   struct sai_buffer_s *freelist;  /* A list a free buffer containers */
-  struct sai_buffer_s containers[CONFIG_STM32L4_SAI_MAXINFLIGHT];
+  struct sai_buffer_s containers[CONFIG_STM32_SAI_MAXINFLIGHT];
 };
 
 /****************************************************************************
@@ -244,9 +244,9 @@ static struct stm32_sai_s g_sai1a_priv =
 #ifdef CONFIG_STM32_SAI_DMA
   .dma_ch      = DMACHAN_SAI1_A,
 #endif
-  .datalen     = CONFIG_STM32L4_SAI_DEFAULT_DATALEN,
-  .samplerate  = CONFIG_STM32L4_SAI_DEFAULT_SAMPLERATE,
-  .bufsem      = SEM_INITIALIZER(CONFIG_STM32L4_SAI_MAXINFLIGHT),
+  .datalen     = CONFIG_STM32_SAI_DEFAULT_DATALEN,
+  .samplerate  = CONFIG_STM32_SAI_DEFAULT_SAMPLERATE,
+  .bufsem      = SEM_INITIALIZER(CONFIG_STM32_SAI_MAXINFLIGHT),
 };
 #endif
 
@@ -265,9 +265,9 @@ static struct stm32_sai_s g_sai1b_priv =
 #ifdef CONFIG_STM32_SAI_DMA
   .dma_ch      = DMACHAN_SAI1_B,
 #endif
-  .datalen     = CONFIG_STM32L4_SAI_DEFAULT_DATALEN,
-  .samplerate  = CONFIG_STM32L4_SAI_DEFAULT_SAMPLERATE,
-  .bufsem      = SEM_INITIALIZER(CONFIG_STM32L4_SAI_MAXINFLIGHT),
+  .datalen     = CONFIG_STM32_SAI_DEFAULT_DATALEN,
+  .samplerate  = CONFIG_STM32_SAI_DEFAULT_SAMPLERATE,
+  .bufsem      = SEM_INITIALIZER(CONFIG_STM32_SAI_MAXINFLIGHT),
 };
 #endif
 
@@ -288,9 +288,9 @@ static struct stm32_sai_s g_sai2a_priv =
 #ifdef CONFIG_STM32_SAI_DMA
   .dma_ch      = DMACHAN_SAI2_A,
 #endif
-  .datalen     = CONFIG_STM32L4_SAI_DEFAULT_DATALEN,
-  .samplerate  = CONFIG_STM32L4_SAI_DEFAULT_SAMPLERATE,
-  .bufsem      = SEM_INITIALIZER(CONFIG_STM32L4_SAI_MAXINFLIGHT),
+  .datalen     = CONFIG_STM32_SAI_DEFAULT_DATALEN,
+  .samplerate  = CONFIG_STM32_SAI_DEFAULT_SAMPLERATE,
+  .bufsem      = SEM_INITIALIZER(CONFIG_STM32_SAI_MAXINFLIGHT),
 };
 #endif
 
@@ -309,9 +309,9 @@ static struct stm32_sai_s g_sai2b_priv =
 #ifdef CONFIG_STM32_SAI_DMA
   .dma_ch      = DMACHAN_SAI2_B,
 #endif
-  .datalen     = CONFIG_STM32L4_SAI_DEFAULT_DATALEN,
-  .samplerate  = CONFIG_STM32L4_SAI_DEFAULT_SAMPLERATE,
-  .bufsem      = SEM_INITIALIZER(CONFIG_STM32L4_SAI_MAXINFLIGHT),
+  .datalen     = CONFIG_STM32_SAI_DEFAULT_DATALEN,
+  .samplerate  = CONFIG_STM32_SAI_DEFAULT_SAMPLERATE,
+  .bufsem      = SEM_INITIALIZER(CONFIG_STM32_SAI_MAXINFLIGHT),
 };
 #endif
 
@@ -1232,7 +1232,7 @@ static void sai_buf_initialize(struct stm32_sai_s *priv)
   int i;
 
   priv->freelist = NULL;
-  for (i = 0; i < CONFIG_STM32L4_SAI_MAXINFLIGHT; i++)
+  for (i = 0; i < CONFIG_STM32_SAI_MAXINFLIGHT; i++)
     {
       sai_buf_free(priv, &priv->containers[i]);
     }
@@ -1267,7 +1267,7 @@ static void sai_portinitialize(struct stm32_sai_s *priv)
   /* Configure the data width */
 
   sai_datawidth((struct i2s_dev_s *)priv,
-                CONFIG_STM32L4_SAI_DEFAULT_DATALEN);
+                CONFIG_STM32_SAI_DEFAULT_DATALEN);
 
 #ifdef CONFIG_STM32_SAI_DMA
   /* Get DMA channel */
diff --git a/arch/arm/src/stm32l4/stm32l4_tim.c b/arch/arm/src/stm32l4/stm32l4_tim.c
index 9fadfeef707..80698730c1b 100644
--- a/arch/arm/src/stm32l4/stm32l4_tim.c
+++ b/arch/arm/src/stm32l4/stm32l4_tim.c
@@ -53,20 +53,20 @@
  * Such special purposes include:
  *
  * - To generate modulated outputs for such things as motor control.  If
- *   CONFIG_STM32L4_TIMn is defined then the CONFIG_STM32L4_TIMn_PWM may also
+ *   CONFIG_STM32_TIMn is defined then the CONFIG_STM32_TIMn_PWM may also
  *   be defined to indicate that the timer is intended to be used for pulsed
  *   output modulation.
  *
- * - To control periodic ADC input sampling.  If CONFIG_STM32L4_TIMn is
- *   defined then CONFIG_STM32L4_TIMn_ADC may also be defined to indicate
+ * - To control periodic ADC input sampling.  If CONFIG_STM32_TIMn is
+ *   defined then CONFIG_STM32_TIMn_ADC may also be defined to indicate
  *   that timer "n" is intended to be used for that purpose.
  *
- * - To control periodic DAC outputs.  If CONFIG_STM32L4_TIMn is defined then
- *   CONFIG_STM32L4_TIMn_DAC may also be defined to indicate that timer "n"
+ * - To control periodic DAC outputs.  If CONFIG_STM32_TIMn is defined then
+ *   CONFIG_STM32_TIMn_DAC may also be defined to indicate that timer "n"
  *   is intended to be used for that purpose.
  *
- * - To use a Quadrature Encoder.  If CONFIG_STM32L4_TIMn is defined then
- *   CONFIG_STM32L4_TIMn_QE may also be defined to indicate that timer "n"
+ * - To use a Quadrature Encoder.  If CONFIG_STM32_TIMn is defined then
+ *   CONFIG_STM32_TIMn_QE may also be defined to indicate that timer "n"
  *   is intended to be used for that purpose.
  *
  * In any of these cases, the timer will not be used by this timer module.
@@ -97,13 +97,13 @@
 #  undef CONFIG_STM32_TIM5
 #endif
 
-#if defined(CONFIG_STM32L4_TIM6_PWM) || defined (CONFIG_STM32_TIM6_ADC) || \
-    defined(CONFIG_STM32_TIM6_DAC) || defined(CONFIG_STM32L4_TIM6_QE)
+#if defined(CONFIG_STM32_TIM6_PWM) || defined (CONFIG_STM32_TIM6_ADC) || \
+    defined(CONFIG_STM32_TIM6_DAC) || defined(CONFIG_STM32_TIM6_QE)
 #  undef CONFIG_STM32_TIM6
 #endif
 
-#if defined(CONFIG_STM32L4_TIM7_PWM) || defined (CONFIG_STM32L4_TIM7_ADC) || \
-    defined(CONFIG_STM32_TIM7_DAC) || defined(CONFIG_STM32L4_TIM7_QE)
+#if defined(CONFIG_STM32_TIM7_PWM) || defined (CONFIG_STM32_TIM7_ADC) || \
+    defined(CONFIG_STM32_TIM7_DAC) || defined(CONFIG_STM32_TIM7_QE)
 #  undef CONFIG_STM32_TIM7
 #endif
 
@@ -113,17 +113,17 @@
 #endif
 
 #if defined(CONFIG_STM32_TIM15_PWM) || defined (CONFIG_STM32_TIM15_ADC) || \
-    defined(CONFIG_STM32L4_TIM15_DAC) || defined(CONFIG_STM32L4_TIM15_QE)
+    defined(CONFIG_STM32_TIM15_DAC) || defined(CONFIG_STM32_TIM15_QE)
 #  undef CONFIG_STM32_TIM15
 #endif
 
-#if defined(CONFIG_STM32_TIM16_PWM) || defined (CONFIG_STM32L4_TIM16_ADC) || \
-    defined(CONFIG_STM32L4_TIM16_DAC) || defined(CONFIG_STM32L4_TIM16_QE)
+#if defined(CONFIG_STM32_TIM16_PWM) || defined (CONFIG_STM32_TIM16_ADC) || \
+    defined(CONFIG_STM32_TIM16_DAC) || defined(CONFIG_STM32_TIM16_QE)
 #  undef CONFIG_STM32_TIM16
 #endif
 
-#if defined(CONFIG_STM32_TIM17_PWM) || defined (CONFIG_STM32L4_TIM17_ADC) || \
-    defined(CONFIG_STM32L4_TIM17_DAC) || defined(CONFIG_STM32L4_TIM17_QE)
+#if defined(CONFIG_STM32_TIM17_PWM) || defined (CONFIG_STM32_TIM17_ADC) || \
+    defined(CONFIG_STM32_TIM17_DAC) || defined(CONFIG_STM32_TIM17_QE)
 #  undef CONFIG_STM32_TIM17
 #endif
 
diff --git a/boards/arm/stm32l4/nucleo-l496zg/src/stm32_boot.c b/boards/arm/stm32l4/nucleo-l496zg/src/stm32_boot.c
index 3d4eb5a06ff..4e59599a7e0 100644
--- a/boards/arm/stm32l4/nucleo-l496zg/src/stm32_boot.c
+++ b/boards/arm/stm32l4/nucleo-l496zg/src/stm32_boot.c
@@ -64,7 +64,7 @@ void stm32_board_initialize(void)
   board_autoled_initialize();
 #endif
 
-#if defined(CONFIG_STM32_OTGFS) || defined(CONFIG_STM32L4_HOST)
+#if defined(CONFIG_STM32_OTGFS) || defined(CONFIG_STM32_HOST)
   stm32_usbinitialize();
 #endif