diff --git a/arch/risc-v/include/irq.h b/arch/risc-v/include/irq.h
index c869ac90f56..32710c7e292 100644
--- a/arch/risc-v/include/irq.h
+++ b/arch/risc-v/include/irq.h
@@ -695,7 +695,27 @@ irqstate_t up_irq_enable(void);
  * Name: up_cpu_index
  *
  * Description:
- *   Return the real core number regardless CONFIG_SMP setting
+ *   Return the real core number regardless CONFIG_SMP setting,
+ *   context aware way to query hart id (physical core ID)
+ *
+ *   The function up_cpu_index is designed to retrieve the hardware thread
+ *   ID (hartid) in different execution modes of RISC-V. Its behavior depends
+ *   on the configuration and execution mode:
+ *
+ *   - In machine mode, up_cpu_index reads directly from the CSR mhartid.
+ *   - In supervisor mode, the hartid is stored in the percpu structure
+ *     during boot because supervisor mode does not have access to CSR
+ *     `shartid`. The SBI (Supervisor Binary Interface) provides the hartid
+ *     in the a0 register (as per SBI ABI requirements), and it is the
+ *     responsibility of the payload OS to store this value internally.
+ *     We use the percpu scratch register for this purpose, as it is the only
+ *     location that is unique for each CPU and non-volatile.
+ *
+ *   Note: In flat (machine) mode, you could still read the hartid from CSR
+ *   mhartid even if CONFIG_RISCV_PERCPU_SCRATCH is enabled.
+ *
+ * Returned Value:
+ *   Hart id
  *
  ****************************************************************************/
 
diff --git a/arch/risc-v/src/bl808/chip.h b/arch/risc-v/src/bl808/chip.h
index d93c039e043..dde015abba4 100644
--- a/arch/risc-v/src/bl808/chip.h
+++ b/arch/risc-v/src/bl808/chip.h
@@ -56,7 +56,7 @@
 
 #if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 15
 .macro  setintstack tmp0, tmp1
-  riscv_mhartid \tmp0
+  up_cpu_index \tmp0
   li    \tmp1, STACK_ALIGN_DOWN(CONFIG_ARCH_INTERRUPTSTACK)
   mul   \tmp1, \tmp0, \tmp1
   la    \tmp0, g_intstacktop
diff --git a/arch/risc-v/src/common/CMakeLists.txt b/arch/risc-v/src/common/CMakeLists.txt
index 14aa1f726d6..73aefa3c789 100644
--- a/arch/risc-v/src/common/CMakeLists.txt
+++ b/arch/risc-v/src/common/CMakeLists.txt
@@ -22,7 +22,7 @@
 
 set(SRCS)
 
-list(APPEND SRCS riscv_exception_common.S riscv_mhartid.S riscv_vectors.S)
+list(APPEND SRCS riscv_exception_common.S riscv_vectors.S)
 list(APPEND SRCS riscv_saveusercontext.S)
 list(APPEND SRCS riscv_allocateheap.c riscv_cpuidlestack.c)
 list(APPEND SRCS riscv_cpuinfo.c riscv_createstack.c riscv_doirq.c
diff --git a/arch/risc-v/src/common/Make.defs b/arch/risc-v/src/common/Make.defs
index 3446c748e91..25f008df278 100644
--- a/arch/risc-v/src/common/Make.defs
+++ b/arch/risc-v/src/common/Make.defs
@@ -25,7 +25,7 @@ STARTUP_OBJS = crt0$(OBJEXT)
 endif
 
 # Specify our general Assembly files
-CMN_ASRCS += riscv_vectors.S riscv_exception_common.S riscv_mhartid.S
+CMN_ASRCS += riscv_vectors.S riscv_exception_common.S
 CMN_ASRCS += riscv_saveusercontext.S
 
 # Specify C code within the common directory to be included
diff --git a/arch/risc-v/src/common/riscv_cpuidmap.c b/arch/risc-v/src/common/riscv_cpuidmap.c
index e56860c383d..81a6a778410 100644
--- a/arch/risc-v/src/common/riscv_cpuidmap.c
+++ b/arch/risc-v/src/common/riscv_cpuidmap.c
@@ -46,7 +46,7 @@
 
 int up_this_cpu(void)
 {
-  return riscv_hartid_to_cpuid((int)riscv_mhartid());
+  return riscv_hartid_to_cpuid(up_cpu_index());
 }
 
 /****************************************************************************
@@ -81,6 +81,6 @@ int weak_function riscv_cpuid_to_hartid(int cpu)
 #ifdef CONFIG_SMP
   return cpu + CONFIG_ARCH_RV_HARTID_BASE;
 #else
-  return (int)riscv_mhartid();
+  return up_cpu_index();
 #endif
 }
diff --git a/arch/risc-v/src/common/riscv_cpuindex.c b/arch/risc-v/src/common/riscv_cpuindex.c
index 6e35ede46d6..01c3f8d9fe3 100644
--- a/arch/risc-v/src/common/riscv_cpuindex.c
+++ b/arch/risc-v/src/common/riscv_cpuindex.c
@@ -28,8 +28,10 @@
 
 #include <nuttx/arch.h>
 #include <nuttx/irq.h>
+#include <arch/csr.h>
 
 #include "riscv_internal.h"
+#include "riscv_percpu.h"
 
 /****************************************************************************
  * Public Functions
@@ -45,5 +47,5 @@
 
 int up_cpu_index(void)
 {
-  return (int)riscv_mhartid();
+  return riscv_percpu_get_hartid();
 }
diff --git a/arch/risc-v/src/common/riscv_internal.h b/arch/risc-v/src/common/riscv_internal.h
index e1dece58f4a..9e72f5bb8ba 100644
--- a/arch/risc-v/src/common/riscv_internal.h
+++ b/arch/risc-v/src/common/riscv_internal.h
@@ -356,35 +356,6 @@ void riscv_cpu_boot(int cpu);
 int riscv_smp_call_handler(int irq, void *c, void *arg);
 #endif
 
-/****************************************************************************
- * Name: riscv_mhartid
- *
- * Description:
- *   Context aware way to query hart id (physical core ID)
- *
- *   The function riscv_mhartid is designed to retrieve the hardware thread
- *   ID (hartid) in different execution modes of RISC-V. Its behavior depends
- *   on the configuration and execution mode:
- *
- *   - In machine mode, riscv_mhartid reads directly from the CSR mhartid.
- *   - In supervisor mode, the hartid is stored in the percpu structure
- *     during boot because supervisor mode does not have access to CSR
- *     `shartid`. The SBI (Supervisor Binary Interface) provides the hartid
- *     in the a0 register (as per SBI ABI requirements), and it is the
- *     responsibility of the payload OS to store this value internally.
- *     We use the percpu scratch register for this purpose, as it is the only
- *     location that is unique for each CPU and non-volatile.
- *
- *   Note: In flat (machine) mode, you could still read the hartid from CSR
- *   mhartid even if CONFIG_RISCV_PERCPU_SCRATCH is enabled.
- *
- * Returned Value:
- *   Hart id
- *
- ****************************************************************************/
-
-uintptr_t riscv_mhartid(void);
-
 #ifdef CONFIG_ARCH_RV_CPUID_MAP
 /****************************************************************************
  * Name: riscv_hartid_to_cpuid / riscv_cpuid_to_hartid
diff --git a/arch/risc-v/src/common/riscv_macros.S b/arch/risc-v/src/common/riscv_macros.S
index 11c246cef22..ae530fb03de 100644
--- a/arch/risc-v/src/common/riscv_macros.S
+++ b/arch/risc-v/src/common/riscv_macros.S
@@ -348,17 +348,10 @@
 #endif /* CONFIG_ARCH_INTERRUPTSTACK > 15 */
 
 /****************************************************************************
- * Name: riscv_mhartid
- *
- * Description:
- *   Context aware way to query hart id (physical core ID)
- *
- * Returned Value:
- *   Hart id
- *
+ * Name: up_cpu_index
  ****************************************************************************/
 
-.macro  riscv_mhartid out
+.macro  up_cpu_index out
 #ifdef CONFIG_RISCV_PERCPU_SCRATCH
   csrr    \out, CSR_SCRATCH
   REGLOAD \out, RISCV_PERCPU_HARTID(\out)
diff --git a/arch/risc-v/src/common/riscv_mhartid.S b/arch/risc-v/src/common/riscv_mhartid.S
deleted file mode 100644
index 8506685bbf6..00000000000
--- a/arch/risc-v/src/common/riscv_mhartid.S
+++ /dev/null
@@ -1,55 +0,0 @@
-/****************************************************************************
- * arch/risc-v/src/common/riscv_mhartid.S
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed to the Apache Software Foundation (ASF) under one or more
- * contributor license agreements.  See the NOTICE file distributed with
- * this work for additional information regarding copyright ownership.  The
- * ASF licenses this file to you under the Apache License, Version 2.0 (the
- * "License"); you may not use this file except in compliance with the
- * License.  You may obtain a copy of the License at
- *
- *   http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
- * License for the specific language governing permissions and limitations
- * under the License.
- *
- ****************************************************************************/
-
-.file "riscv_mhartid.S"
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-#include <nuttx/config.h>
-
-#include "riscv_macros.S"
-
-/****************************************************************************
- * Public Symbols
- ****************************************************************************/
-
-    .globl  riscv_mhartid
-
-/****************************************************************************
- * Name: riscv_mhartid
- *
- * Description:
- *   Context aware way to query hart id (physical core ID)
- *
- * Returned Value:
- *   Hart id
- *
- ****************************************************************************/
-
-.type riscv_mhartid, function
-
-riscv_mhartid:
-
-  riscv_mhartid a0
-  ret
diff --git a/arch/risc-v/src/jh7110/chip.h b/arch/risc-v/src/jh7110/chip.h
index 60bcee84320..f82e162d54b 100644
--- a/arch/risc-v/src/jh7110/chip.h
+++ b/arch/risc-v/src/jh7110/chip.h
@@ -56,7 +56,7 @@
 
 #if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 15
 .macro  setintstack tmp0, tmp1
-  riscv_mhartid \tmp0
+  up_cpu_index \tmp0
   li    \tmp1, STACK_ALIGN_DOWN(CONFIG_ARCH_INTERRUPTSTACK)
   mul   \tmp1, \tmp0, \tmp1
   la    \tmp0, g_intstacktop
diff --git a/arch/risc-v/src/k230/chip.h b/arch/risc-v/src/k230/chip.h
index 90e595ee9ee..1e1066e67d2 100644
--- a/arch/risc-v/src/k230/chip.h
+++ b/arch/risc-v/src/k230/chip.h
@@ -58,7 +58,7 @@
 
 #if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 15
 .macro  setintstack tmp0, tmp1
-  riscv_mhartid \tmp0
+  up_cpu_index \tmp0
   li    \tmp1, STACK_ALIGN_DOWN(CONFIG_ARCH_INTERRUPTSTACK)
   mul   \tmp1, \tmp0, \tmp1
   la    \tmp0, g_intstacktop
diff --git a/arch/risc-v/src/mpfs/mpfs_ihc.c b/arch/risc-v/src/mpfs/mpfs_ihc.c
index 3661dfdc54f..9284014e2c1 100644
--- a/arch/risc-v/src/mpfs/mpfs_ihc.c
+++ b/arch/risc-v/src/mpfs/mpfs_ihc.c
@@ -376,7 +376,7 @@ static uint32_t mpfs_ihc_context_to_local_hart_id(ihc_channel_t channel)
   uint32_t hart             = UNDEFINED_HART_ID;
   uint32_t hart_idx         = 0;
   uint32_t harts_in_context = LIBERO_SETTING_CONTEXT_B_HART_EN;
-  uint64_t mhartid          = riscv_mhartid();
+  uint64_t mhartid          = up_cpu_index();
 
   /* If we are sending to a Context, assume we are a Context.
    * i.e. HSS bootloader will not send directly to a context.
@@ -589,7 +589,7 @@ static void mpfs_ihc_rx_message(ihc_channel_t channel, uint32_t mhartid,
 
 static void mpfs_ihc_message_present_isr(void)
 {
-  uint64_t mhartid = riscv_mhartid();
+  uint64_t mhartid = up_cpu_index();
   bool is_ack = false;
   bool is_msg = false;
 
@@ -1308,7 +1308,7 @@ static int mpfs_rptun_thread(int argc, char *argv[])
 
 int mpfs_ihc_init(void)
 {
-  uint32_t  mhartid = (uint32_t)riscv_mhartid();
+  uint32_t  mhartid = (uint32_t)up_cpu_index();
 #ifdef MPFS_RPTUN_USE_THREAD
   char     *argv[3];
   char      arg1[19];
diff --git a/arch/risc-v/src/mpfs/mpfs_irq.c b/arch/risc-v/src/mpfs/mpfs_irq.c
index 2bdea76ea12..3ec191856ca 100644
--- a/arch/risc-v/src/mpfs/mpfs_irq.c
+++ b/arch/risc-v/src/mpfs/mpfs_irq.c
@@ -56,7 +56,7 @@ void up_irqinitialize(void)
 
   /* Initialize PLIC for current hart */
 
-  mpfs_plic_init_hart(riscv_mhartid());
+  mpfs_plic_init_hart(up_cpu_index());
 
   /* Colorize the interrupt stack for debug purposes */
 
diff --git a/arch/risc-v/src/mpfs/mpfs_plic.c b/arch/risc-v/src/mpfs/mpfs_plic.c
index 60c27dae182..b297e61c4e5 100644
--- a/arch/risc-v/src/mpfs/mpfs_plic.c
+++ b/arch/risc-v/src/mpfs/mpfs_plic.c
@@ -213,7 +213,7 @@ void mpfs_plic_init_hart(uintptr_t hartid)
 
 uintptr_t mpfs_plic_get_iebase(void)
 {
-  return get_iebase(riscv_mhartid());
+  return get_iebase(up_cpu_index());
 }
 
 /****************************************************************************
@@ -229,7 +229,7 @@ uintptr_t mpfs_plic_get_iebase(void)
 
 uintptr_t mpfs_plic_get_claimbase(void)
 {
-  return get_claimbase(riscv_mhartid());
+  return get_claimbase(up_cpu_index());
 }
 
 /****************************************************************************
@@ -245,5 +245,5 @@ uintptr_t mpfs_plic_get_claimbase(void)
 
 uintptr_t mpfs_plic_get_thresholdbase(void)
 {
-  return get_thresholdbase(riscv_mhartid());
+  return get_thresholdbase(up_cpu_index());
 }
diff --git a/arch/risc-v/src/mpfs/mpfs_timerisr.c b/arch/risc-v/src/mpfs/mpfs_timerisr.c
index bf87d9efbea..ee66cdc9a46 100644
--- a/arch/risc-v/src/mpfs/mpfs_timerisr.c
+++ b/arch/risc-v/src/mpfs/mpfs_timerisr.c
@@ -66,7 +66,7 @@ void up_timer_initialize(void)
 {
   /* what is our timecmp address for this hart */
 
-  uintptr_t hart_id = riscv_mhartid();
+  uintptr_t hart_id = up_cpu_index();
 
   struct oneshot_lowerhalf_s *lower = riscv_mtimer_initialize(
     MPFS_CLINT_MTIME, MPFS_CLINT_MTIMECMP0 + hart_id * sizeof(uintptr_t),
diff --git a/arch/risc-v/src/qemu-rv/chip.h b/arch/risc-v/src/qemu-rv/chip.h
index 498b5f57802..e62c00e8788 100644
--- a/arch/risc-v/src/qemu-rv/chip.h
+++ b/arch/risc-v/src/qemu-rv/chip.h
@@ -58,7 +58,7 @@
 
 #if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 15
 .macro  setintstack tmp0, tmp1
-  riscv_mhartid \tmp0
+  up_cpu_index \tmp0
   li    \tmp1, STACK_ALIGN_DOWN(CONFIG_ARCH_INTERRUPTSTACK)
   mul   \tmp1, \tmp0, \tmp1
   la    \tmp0, g_intstacktop
diff --git a/arch/risc-v/src/qemu-rv/qemu_rv_irq.c b/arch/risc-v/src/qemu-rv/qemu_rv_irq.c
index 24481b9d889..a7df68de928 100644
--- a/arch/risc-v/src/qemu-rv/qemu_rv_irq.c
+++ b/arch/risc-v/src/qemu-rv/qemu_rv_irq.c
@@ -281,7 +281,7 @@ void up_enable_irq(int irq)
 #else
           riscv_aplic_configure_irq(QEMU_RV_APLIC_BASE, extirq,
                                     RISCV_APLIC_SOURCECFG_SM_EDGE_RISE,
-                                    riscv_mhartid());
+                                    up_cpu_index());
 #ifdef CONFIG_ARCH_RV_HAVE_IMSIC
           riscv_imsic_local_eie_enable(extirq);
 #endif
diff --git a/arch/risc-v/src/qemu-rv/qemu_rv_irq_dispatch.c b/arch/risc-v/src/qemu-rv/qemu_rv_irq_dispatch.c
index b322eea7947..5d2a7aa601d 100644
--- a/arch/risc-v/src/qemu-rv/qemu_rv_irq_dispatch.c
+++ b/arch/risc-v/src/qemu-rv/qemu_rv_irq_dispatch.c
@@ -63,7 +63,7 @@ static void *riscv_dispatch_irq_ext(uintreg_t irq, uintreg_t *regs)
 static void *riscv_dispatch_irq_ext(uintreg_t irq, uintreg_t *regs)
 {
   int extirq;
-  int hartid = riscv_mhartid();
+  int hartid = up_cpu_index();
   uintptr_t aplic_base = RISCV_APLIC_IDC(QEMU_RV_APLIC_BASE, hartid) +
                             RISCV_APLIC_IDC_CLAIMI;
 
diff --git a/arch/risc-v/src/sg2000/chip.h b/arch/risc-v/src/sg2000/chip.h
index 19b65790711..1a66eb3ac3b 100644
--- a/arch/risc-v/src/sg2000/chip.h
+++ b/arch/risc-v/src/sg2000/chip.h
@@ -56,7 +56,7 @@
 
 #if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 15
 .macro  setintstack tmp0, tmp1
-  riscv_mhartid \tmp0
+  up_cpu_index \tmp0
   li    \tmp1, STACK_ALIGN_DOWN(CONFIG_ARCH_INTERRUPTSTACK)
   mul   \tmp1, \tmp0, \tmp1
   la    \tmp0, g_intstacktop