From 761059aee2b107f613f02410903d9fb0fa1c0fa5 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Tue, 28 Oct 2014 15:44:47 -0600 Subject: [PATCH 1/5] SAM4: Fix a usbnsh build problem that has crept into all serial drivers --- arch/arm/src/common/up_internal.h | 4 ++-- arch/arm/src/sam34/sam_serial.c | 2 ++ 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm/src/common/up_internal.h b/arch/arm/src/common/up_internal.h index bd60b0fad1b..929353e8c19 100644 --- a/arch/arm/src/common/up_internal.h +++ b/arch/arm/src/common/up_internal.h @@ -422,13 +422,13 @@ void up_lowputc(char ch); void up_puts(const char *str); void up_lowputs(const char *str); -#if USE_SERIALDRIVER +#ifdef USE_SERIALDRIVER void up_serialinit(void); #else # define up_serialinit() #endif -#if USE_EARLYSERIALINIT +#ifdef USE_EARLYSERIALINIT void up_earlyserialinit(void); #else # define up_earlyserialinit() diff --git a/arch/arm/src/sam34/sam_serial.c b/arch/arm/src/sam34/sam_serial.c index 745fada3394..6aec44070ac 100644 --- a/arch/arm/src/sam34/sam_serial.c +++ b/arch/arm/src/sam34/sam_serial.c @@ -1154,6 +1154,7 @@ static bool up_txempty(struct uart_dev_s *dev) * ****************************************************************************/ +#ifdef USE_EARLYSERIALINIT void up_earlyserialinit(void) { /* NOTE: All GPIO configuration for the USARTs was performed in @@ -1186,6 +1187,7 @@ void up_earlyserialinit(void) up_setup(&CONSOLE_DEV); #endif } +#endif /**************************************************************************** * Name: up_serialinit From 8a17a264ff7c20ddf1e1655e9812b60453af96b8 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Tue, 28 Oct 2014 19:02:21 -0600 Subject: [PATCH 2/5] Fix a few more EFM32 integration bugs --- arch/arm/src/efm32/efm32_lowputc.c | 3 +-- arch/arm/src/efm32/efm32_serial.c | 20 ++++++++++---------- configs/efm32-g8xx-stk/README.txt | 10 ++++++++-- 3 files changed, 19 insertions(+), 14 deletions(-) diff --git a/arch/arm/src/efm32/efm32_lowputc.c b/arch/arm/src/efm32/efm32_lowputc.c index 84e7019fcf4..b8b2ecb7b27 100644 --- a/arch/arm/src/efm32/efm32_lowputc.c +++ b/arch/arm/src/efm32/efm32_lowputc.c @@ -161,7 +161,7 @@ static void efm32_uart_setbaud(uintptr_t base, uint32_t baud) * baud = 2400.0 */ - maxover = ((BOARD_HFPERCLK_FREQUENCY << 8) / 280) / baud; + maxover = (((uint64_t)BOARD_HFPERCLK_FREQUENCY << 8) / 280) / baud; if (maxover >= 16) { DEBUGASSERT(baud <= (BOARD_HFPERCLK_FREQUENCY / 16)); @@ -612,7 +612,6 @@ void efm32_uartconfigure(uintptr_t base, uint32_t baud, unsigned int parity, case 2: regval |= USART_FRAME_PARITY_EVEN; break; - } /* Configure stop bits */ diff --git a/arch/arm/src/efm32/efm32_serial.c b/arch/arm/src/efm32/efm32_serial.c index a3dafd3b07b..f7b18c28ae2 100644 --- a/arch/arm/src/efm32/efm32_serial.c +++ b/arch/arm/src/efm32/efm32_serial.c @@ -100,7 +100,7 @@ #elif defined(CONFIG_UART0_SERIAL_CONSOLE) # define CONSOLE_DEV g_uart0port /* UART0 is console */ # define TTYS0_DEV g_uart0port /* UART0 is ttyS0 */ -# define UART1_ASSIGNED 1 +# define UART0_ASSIGNED 1 #elif defined(CONFIG_UART1_SERIAL_CONSOLE) # define CONSOLE_DEV g_uart1port /* UART1 is console */ # define TTYS0_DEV g_uart1port /* UART1 is ttyS0 */ @@ -359,15 +359,15 @@ static struct uart_dev_s g_usart0port = .recv = { .size = CONFIG_USART0_RXBUFSIZE, - .buffer = g_uart0rxbuffer, + .buffer = g_usart0rxbuffer, }, .xmit = { .size = CONFIG_USART0_TXBUFSIZE, - .buffer = g_uart0txbuffer, + .buffer = g_usart0txbuffer, }, .ops = &g_uart_ops, - .priv = &g_uart0priv, + .priv = &g_usart0priv, }; #endif @@ -397,15 +397,15 @@ static struct uart_dev_s g_usart1port = .recv = { .size = CONFIG_USART1_RXBUFSIZE, - .buffer = g_uart1rxbuffer, + .buffer = g_usart1rxbuffer, }, .xmit = { .size = CONFIG_USART1_TXBUFSIZE, - .buffer = g_uart1txbuffer, + .buffer = g_usart1txbuffer, }, .ops = &g_uart_ops, - .priv = &g_uart1priv, + .priv = &g_usart1priv, }; #endif @@ -435,15 +435,15 @@ static struct uart_dev_s g_usart2port = .recv = { .size = CONFIG_USART2_RXBUFSIZE, - .buffer = g_uart2rxbuffer, + .buffer = g_usart2rxbuffer, }, .xmit = { .size = CONFIG_USART2_TXBUFSIZE, - .buffer = g_uart2txbuffer, + .buffer = g_usart2txbuffer, }, .ops = &g_uart_ops, - .priv = &g_uart2priv, + .priv = &g_usart2priv, }; #endif diff --git a/configs/efm32-g8xx-stk/README.txt b/configs/efm32-g8xx-stk/README.txt index ea683846ec4..4459b2e0010 100644 --- a/configs/efm32-g8xx-stk/README.txt +++ b/configs/efm32-g8xx-stk/README.txt @@ -28,8 +28,14 @@ CONTENTS STATUS ====== - Testing has just begun. So the status is code-complete but only - partially tested. + 2014-10-28. Testing is still in progress. At this point all basic boot + operations are successful: The LEDs work and the application tasks appear + to be successfully started. LED2 is on and LED0 is glowing (meaning that + interrupts are being processed). However, I get no output on PE0. Data + appears to be sent (at least by efm32_lowputc()). However, no signal + activity is present on PE0. + + I am, of course, thinking that this is a pin configuration issue. LEDs ==== From 0679d3109f53ad1f1f6267cbb9ba9b80dcc58156 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Tue, 28 Oct 2014 19:46:45 -0600 Subject: [PATCH 3/5] EFM32: Implement HFPERCLK logic --- arch/arm/src/efm32/efm32_clockconfig.c | 20 ++++++++++++++++++-- 1 file changed, 18 insertions(+), 2 deletions(-) diff --git a/arch/arm/src/efm32/efm32_clockconfig.c b/arch/arm/src/efm32/efm32_clockconfig.c index 13428e61910..53b70259285 100644 --- a/arch/arm/src/efm32/efm32_clockconfig.c +++ b/arch/arm/src/efm32/efm32_clockconfig.c @@ -550,8 +550,24 @@ static inline uint32_t efm32_hfcoreclk_config(uint32_t hfcoreclkdiv, static inline uint32_t efm32_hfperclk_config(uint32_t hfperclkdiv, uint32_t hfclk) { - /* REVISIT: Divider not currently used */ - return hfclk; + uint32_t regval; + uint32_t hfperclk; + unsigned int divider; + + DEBUGASSERT(hfperclkdiv <= _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512); + + /* Set the divider and enable the HFPERCLK */ + + regval = (hfperclkdiv << _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT) | + CMU_HFPERCLKDIV_HFPERCLKEN; + putreg32(regval, EFM32_CMU_HFPERCLKDIV); + + /* The value of hfperclkdiv is log2 of the arithmetic divisor: + * 0->1, 1->2, 2->4, 3->8, ... 9->512. + */ + + divider = 1 << hfperclkdiv; + return hfclk / divider; } /**************************************************************************** From 47a8e614e851fce0e534a858ecd24ca9dbb58c56 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Wed, 29 Oct 2014 08:04:29 -0600 Subject: [PATCH 4/5] EFM32: Minor serial interrupt mask change; Add LEUART0 board support --- arch/arm/src/efm32/efm32_serial.c | 3 +-- configs/efm32-g8xx-stk/include/board.h | 10 ++++++++++ 2 files changed, 11 insertions(+), 2 deletions(-) diff --git a/arch/arm/src/efm32/efm32_serial.c b/arch/arm/src/efm32/efm32_serial.c index f7b18c28ae2..c8f4ce0250b 100644 --- a/arch/arm/src/efm32/efm32_serial.c +++ b/arch/arm/src/efm32/efm32_serial.c @@ -198,8 +198,7 @@ #define EFM32_TXERR_INTS (USART_IEN_TXOF) #define EFM32_RXERR_INTS (USART_IEN_RXOF | USART_IEN_RXUF | \ - USART_IEN_TXUF | USART_IEN_PERR | \ - USART_IEN_FERR) + USART_IEN_PERR | USART_IEN_FERR) #ifdef CONFIG_DEBUG # define EFM32_TX_INTS (USART_IEN_TXBL | EFM32_TXERR_INTS) # define EFM32_RX_INTS (USART_IEN_RXDATAV | EFM32_RXERR_INTS) diff --git a/configs/efm32-g8xx-stk/include/board.h b/configs/efm32-g8xx-stk/include/board.h index 9595a8e21c2..ffcd64f2b86 100644 --- a/configs/efm32-g8xx-stk/include/board.h +++ b/configs/efm32-g8xx-stk/include/board.h @@ -210,6 +210,16 @@ #define BOARD_UART0_TX_GPIO (GPIO_PORTE|GPIO_PIN0) #define BOARD_UART0_ROUTE_LOCATION _USART_ROUTE_LOCATION_LOC1 +/* LEUART0: + * + * LEU0_RX #0 PD5 **AVAILABLE at TP123 and EXP port pin 14** + * LEU0_TX #0 PD4 **AVAILABLE at TP122 and EXP port pin 12** + */ + +#define BOARD_LEUART0_RX_GPIO (GPIO_PORTD|GPIO_PIN5) +#define BOARD_LEUART0_TX_GPIO (GPIO_PORTD|GPIO_PIN4) +#define BOARD_LEUART0_ROUTE_LOCATION _LEUART_ROUTE_LOCATION_LOC0 + /**************************************************************************** * Public Function Prototypes ****************************************************************************/ From b3885111373f8e2607504a5db4eed638ab837186 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Wed, 29 Oct 2014 09:37:39 -0600 Subject: [PATCH 5/5] EFM32: Various fixes for LEUART build --- arch/arm/src/efm32/chip/efm32_cmu.h | 48 +++++++++++++++----------- arch/arm/src/efm32/efm32_clockconfig.c | 19 ++++++++-- arch/arm/src/efm32/efm32_leserial.c | 3 +- arch/arm/src/efm32/efm32_lowputc.c | 2 +- 4 files changed, 46 insertions(+), 26 deletions(-) diff --git a/arch/arm/src/efm32/chip/efm32_cmu.h b/arch/arm/src/efm32/chip/efm32_cmu.h index add85443dca..9822b553e33 100644 --- a/arch/arm/src/efm32/chip/efm32_cmu.h +++ b/arch/arm/src/efm32/chip/efm32_cmu.h @@ -611,8 +611,13 @@ /* Bit fields for CMU LFCLKSEL */ -#define _CMU_LFCLKSEL_RESETVALUE 0x00000005UL /* Default value for CMU_LFCLKSEL */ -#define _CMU_LFCLKSEL_MASK 0x0011000FUL /* Mask for CMU_LFCLKSEL */ +#if defined(CONFIG_EFM32_EFM32GG) +# define _CMU_LFCLKSEL_RESETVALUE 0x00000005UL /* Default value for CMU_LFCLKSEL */ +# define _CMU_LFCLKSEL_MASK 0x0011000FUL /* Mask for CMU_LFCLKSEL */ +#elif defined(CONFIG_EFM32_EFM32G) +# define _CMU_LFCLKSEL_RESETVALUE 0x00000005UL /* Default value for CMU_LFCLKSEL */ +# define _CMU_LFCLKSEL_MASK 0x0011000FUL /* Mask for CMU_LFCLKSEL */ +#endif #define _CMU_LFCLKSEL_LFA_SHIFT 0 /* Shift value for CMU_LFA */ #define _CMU_LFCLKSEL_LFA_MASK 0x3UL /* Bit mask for CMU_LFA */ @@ -638,24 +643,27 @@ #define CMU_LFCLKSEL_LFB_LFRCO (_CMU_LFCLKSEL_LFB_LFRCO << 2) /* Shifted mode LFRCO for CMU_LFCLKSEL */ #define CMU_LFCLKSEL_LFB_LFXO (_CMU_LFCLKSEL_LFB_LFXO << 2) /* Shifted mode LFXO for CMU_LFCLKSEL */ #define CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 << 2) /* Shifted mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */ -#define CMU_LFCLKSEL_LFAE (0x1UL << 16) /* Clock Select for LFA Extended */ -#define _CMU_LFCLKSEL_LFAE_SHIFT 16 /* Shift value for CMU_LFAE */ -#define _CMU_LFCLKSEL_LFAE_MASK 0x10000UL /* Bit mask for CMU_LFAE */ -#define _CMU_LFCLKSEL_LFAE_DEFAULT 0x00000000UL /* Mode DEFAULT for CMU_LFCLKSEL */ -#define _CMU_LFCLKSEL_LFAE_DISABLED 0x00000000UL /* Mode DISABLED for CMU_LFCLKSEL */ -#define _CMU_LFCLKSEL_LFAE_ULFRCO 0x00000001UL /* Mode ULFRCO for CMU_LFCLKSEL */ -#define CMU_LFCLKSEL_LFAE_DEFAULT (_CMU_LFCLKSEL_LFAE_DEFAULT << 16) /* Shifted mode DEFAULT for CMU_LFCLKSEL */ -#define CMU_LFCLKSEL_LFAE_DISABLED (_CMU_LFCLKSEL_LFAE_DISABLED << 16) /* Shifted mode DISABLED for CMU_LFCLKSEL */ -#define CMU_LFCLKSEL_LFAE_ULFRCO (_CMU_LFCLKSEL_LFAE_ULFRCO << 16) /* Shifted mode ULFRCO for CMU_LFCLKSEL */ -#define CMU_LFCLKSEL_LFBE (0x1UL << 20) /* Clock Select for LFB Extended */ -#define _CMU_LFCLKSEL_LFBE_SHIFT 20 /* Shift value for CMU_LFBE */ -#define _CMU_LFCLKSEL_LFBE_MASK 0x100000UL /* Bit mask for CMU_LFBE */ -#define _CMU_LFCLKSEL_LFBE_DEFAULT 0x00000000UL /* Mode DEFAULT for CMU_LFCLKSEL */ -#define _CMU_LFCLKSEL_LFBE_DISABLED 0x00000000UL /* Mode DISABLED for CMU_LFCLKSEL */ -#define _CMU_LFCLKSEL_LFBE_ULFRCO 0x00000001UL /* Mode ULFRCO for CMU_LFCLKSEL */ -#define CMU_LFCLKSEL_LFBE_DEFAULT (_CMU_LFCLKSEL_LFBE_DEFAULT << 20) /* Shifted mode DEFAULT for CMU_LFCLKSEL */ -#define CMU_LFCLKSEL_LFBE_DISABLED (_CMU_LFCLKSEL_LFBE_DISABLED << 20) /* Shifted mode DISABLED for CMU_LFCLKSEL */ -#define CMU_LFCLKSEL_LFBE_ULFRCO (_CMU_LFCLKSEL_LFBE_ULFRCO << 20) /* Shifted mode ULFRCO for CMU_LFCLKSEL */ + +#if defined(CONFIG_EFM32_EFM32GG) +# define CMU_LFCLKSEL_LFAE (0x1UL << 16) /* Clock Select for LFA Extended */ +# define _CMU_LFCLKSEL_LFAE_SHIFT 16 /* Shift value for CMU_LFAE */ +# define _CMU_LFCLKSEL_LFAE_MASK 0x10000UL /* Bit mask for CMU_LFAE */ +# define _CMU_LFCLKSEL_LFAE_DEFAULT 0x00000000UL /* Mode DEFAULT for CMU_LFCLKSEL */ +# define _CMU_LFCLKSEL_LFAE_DISABLED 0x00000000UL /* Mode DISABLED for CMU_LFCLKSEL */ +# define _CMU_LFCLKSEL_LFAE_ULFRCO 0x00000001UL /* Mode ULFRCO for CMU_LFCLKSEL */ +# define CMU_LFCLKSEL_LFAE_DEFAULT (_CMU_LFCLKSEL_LFAE_DEFAULT << 16) /* Shifted mode DEFAULT for CMU_LFCLKSEL */ +# define CMU_LFCLKSEL_LFAE_DISABLED (_CMU_LFCLKSEL_LFAE_DISABLED << 16) /* Shifted mode DISABLED for CMU_LFCLKSEL */ +# define CMU_LFCLKSEL_LFAE_ULFRCO (_CMU_LFCLKSEL_LFAE_ULFRCO << 16) /* Shifted mode ULFRCO for CMU_LFCLKSEL */ +# define CMU_LFCLKSEL_LFBE (0x1UL << 20) /* Clock Select for LFB Extended */ +# define _CMU_LFCLKSEL_LFBE_SHIFT 20 /* Shift value for CMU_LFBE */ +# define _CMU_LFCLKSEL_LFBE_MASK 0x100000UL /* Bit mask for CMU_LFBE */ +# define _CMU_LFCLKSEL_LFBE_DEFAULT 0x00000000UL /* Mode DEFAULT for CMU_LFCLKSEL */ +# define _CMU_LFCLKSEL_LFBE_DISABLED 0x00000000UL /* Mode DISABLED for CMU_LFCLKSEL */ +# define _CMU_LFCLKSEL_LFBE_ULFRCO 0x00000001UL /* Mode ULFRCO for CMU_LFCLKSEL */ +# define CMU_LFCLKSEL_LFBE_DEFAULT (_CMU_LFCLKSEL_LFBE_DEFAULT << 20) /* Shifted mode DEFAULT for CMU_LFCLKSEL */ +# define CMU_LFCLKSEL_LFBE_DISABLED (_CMU_LFCLKSEL_LFBE_DISABLED << 20) /* Shifted mode DISABLED for CMU_LFCLKSEL */ +# define CMU_LFCLKSEL_LFBE_ULFRCO (_CMU_LFCLKSEL_LFBE_ULFRCO << 20) /* Shifted mode ULFRCO for CMU_LFCLKSEL */ +#endif /* Bit fields for CMU STATUS */ diff --git a/arch/arm/src/efm32/efm32_clockconfig.c b/arch/arm/src/efm32/efm32_clockconfig.c index 53b70259285..d7f36314078 100644 --- a/arch/arm/src/efm32/efm32_clockconfig.c +++ b/arch/arm/src/efm32/efm32_clockconfig.c @@ -551,7 +551,6 @@ static inline uint32_t efm32_hfperclk_config(uint32_t hfperclkdiv, uint32_t hfclk) { uint32_t regval; - uint32_t hfperclk; unsigned int divider; DEBUGASSERT(hfperclkdiv <= _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512); @@ -659,11 +658,18 @@ static inline uint32_t efm32_lfaclk_config(uint32_t lfaclksel, bool ulfrco, /* Enable the LFA clock in the LFCLKSEL register */ regval = getreg32(EFM32_CMU_LFCLKSEL); - regval &= ~(_CMU_LFCLKSEL_LFA_MASK | _CMU_LFCLKSEL_LFAE_MASK); + +#ifdef CMU_LFCLKSEL_LFAE + regval &= ~_CMU_LFCLKSEL_LFAE_MASK; +#endif + + regval &= ~_CMU_LFCLKSEL_LFA_MASK; regval |= (lfaclksel << _CMU_LFCLKSEL_LFA_SHIFT); + #ifdef CMU_LFCLKSEL_LFAE_ULFRCO regval |= ((uint32_t)ulfrco << _CMU_LFCLKSEL_LFAE_SHIFT); #endif + putreg32(regval, EFM32_CMU_LFCLKSEL); return lfaclk; @@ -753,11 +759,18 @@ static inline uint32_t efm32_lfbclk_config(uint32_t lfbclksel, bool ulfrco, /* Enable the LFB clock in the LFCLKSEL register */ regval = getreg32(EFM32_CMU_LFCLKSEL); - regval &= ~(_CMU_LFCLKSEL_LFB_MASK | _CMU_LFCLKSEL_LFBE_MASK); + +#ifdef CMU_LFCLKSEL_LFBE + regval &= ~_CMU_LFCLKSEL_LFBE_MASK; +#endif + + regval &= ~_CMU_LFCLKSEL_LFB_MASK; regval |= (lfbclksel << _CMU_LFCLKSEL_LFB_SHIFT); + #ifdef CMU_LFCLKSEL_LFBE_ULFRCO regval |= ((uint32_t)ulfrco << _CMU_LFCLKSEL_LFBE_SHIFT); #endif + putreg32(regval, EFM32_CMU_LFCLKSEL); return lfbclk; diff --git a/arch/arm/src/efm32/efm32_leserial.c b/arch/arm/src/efm32/efm32_leserial.c index b40e3d2b004..8284a6410bc 100644 --- a/arch/arm/src/efm32/efm32_leserial.c +++ b/arch/arm/src/efm32/efm32_leserial.c @@ -127,7 +127,6 @@ # define EFM32_RX_INTS LEUART_IEN_RXDATAV #endif - /**************************************************************************** * Private Types ****************************************************************************/ @@ -217,7 +216,7 @@ static char g_leuart1txbuffer[CONFIG_LEUART1_TXBUFSIZE]; /* This describes the state of the EFM32 LEUART0 port. */ #ifdef CONFIG_EFM32_LEUART0 -static const struct efm32_leuart_s g_leuart0config = +static const struct efm32_config_s g_leuart0config = { .uartbase = EFM32_LEUART0_BASE, .handler = efm32_leuart0_interrupt, diff --git a/arch/arm/src/efm32/efm32_lowputc.c b/arch/arm/src/efm32/efm32_lowputc.c index b8b2ecb7b27..4198288f5d9 100644 --- a/arch/arm/src/efm32/efm32_lowputc.c +++ b/arch/arm/src/efm32/efm32_lowputc.c @@ -325,7 +325,7 @@ void efm32_lowsetup(void) #ifdef HAVE_LEUART_DEVICE /* Enable clocking to configured LEUART interfaces */ - regval = getreg32(EFM32_CMU_LFBCLKEN0); + regval = getreg32(EFM32_CMU_LFBCLKEN0); regval &= ~(CMU_LFBCLKEN0_LEUART0 #ifdef CONFIG_EFM32_LEUART1 | CMU_LFBCLKEN0_LEUART1