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arch/arm/src/lpc11xx, arch/arm/include/lpc11xx, configs/lpcxpresso-lpc1115: Support for the LPCXpresso-LPC1115 and for the LPC1115 architecture in general was removed after NuttX-7.30. The LPC11 port was never really used (to my knowledge) and was no longer supported. A snapshot of the port is still available in the Obsoleted repository. It can be brought back into the main repository at any time if anyone is willing to provide support for the architecture.
This commit is contained in:
Gregory Nutt
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70 changed files with 12 additions and 13675 deletions
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/************************************************************************************
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* arch/arm/include/lpc11xx/chip.h
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*
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* Copyright (C) 2015 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_INCLUDE_LPC11XX_CHIP_H
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#define __ARCH_ARM_INCLUDE_LPC11XX_CHIP_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* Get customizations for each supported chip */
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#if defined(CONFIG_ARCH_CHIP_LPC1115)
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# define LPC111x 1 /* LPC111x family */
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# define LPC11_FLASH_SIZE (64*1024) /* 64Kb */
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# define LPC11_SRAM_SIZE (8*1024) /* 8Kb */
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# define LPC11_CPUSRAM_SIZE (8*1024)
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# undef LPC11_HAVE_BANK0 /* No AHB SRAM bank 0 */
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# undef LPC11_HAVE_BANK1 /* No AHB SRAM bank 1 */
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# define LPC11_NETHCONTROLLERS 0 /* No Ethernet controller */
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# define LPC11_NUSBHOST 0 /* No USB host controller */
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# define LPC11_NUSBOTG 0 /* No USB OTG controller */
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# define LPC11_NUSBDEV 1 /* One USB device controller */
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# define LPC11_NCAN 1 /* One CAN controller */
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# define LPC11_NI2S 0 /* No I2S modules */
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# define LPC11_NDAC 0 /* No DAC module */
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#else
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# error "Unsupported LPC11xx chip"
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#endif
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/* NVIC priority levels *************************************************************/
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/* Each priority field holds a priority value, 0-31. The lower the value, the greater
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* the priority of the corresponding interrupt. The processor implements only
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* bits[7:6] of each field, bits[5:0] read as zero and ignore writes.
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*/
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#define NVIC_SYSH_PRIORITY_MIN 0xc0 /* All bits[7:6] set is minimum priority */
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#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
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#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */
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#define NVIC_SYSH_PRIORITY_STEP 0x40 /* Two bits of interrupt priority used */
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/************************************************************************************
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* Public Types
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************************************************************************************/
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/************************************************************************************
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* Public Data
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************************************************************************************/
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/************************************************************************************
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* Public Functions
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************************************************************************************/
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#endif /* __ARCH_ARM_INCLUDE_LPC11XX_CHIP_H */
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@ -1,143 +0,0 @@
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/****************************************************************************
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* arch/arm/include/lpc11xxx/irq.h
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*
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* Copyright (C) 2015 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/* This file should never be included directed but, rather, only indirectly
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* through nuttx/irq.h
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*/
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#ifndef __ARCH_ARM_INCLUDE_LPC11XX_IRQ_H
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#define __ARCH_ARM_INCLUDE_LPC11XX_IRQ_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#ifndef __ASSEMBLY__
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# include <stdint.h>
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#endif
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#include <arch/lpc11xx/chip.h>
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* IRQ numbers. The IRQ number corresponds vector number and hence map
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* directly to bits in the NVIC. This does, however, waste several words of
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* memory in the IRQ to handle mapping tables.
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*/
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/* Common Processor Exceptions (vectors 0-15) */
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#define LPC11_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */
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/* Vector 0: Reset stack pointer value */
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/* Vector 1: Reset (not handler as an IRQ) */
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#define LPC11_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */
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#define LPC11_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */
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/* Vectors 4-10: Reserved */
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#define LPC11_IRQ_SVCALL (11) /* Vector 11: SVC call */
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/* Vector 12-13: Reserved */
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#define LPC11_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */
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#define LPC11_IRQ_SYSTICK (15) /* Vector 15: System tick */
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/* External interrupts (vectors >= 16) */
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#define LPC11_IRQ_EXTINT (16) /* Vector number of the first external interrupt */
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#if defined(CONFIG_ARCH_CHIP_LPC1115)
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#define LPC11_IRQ_PIO0_0 (16) /* Vector 16: PIO0_0 */
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#define LPC11_IRQ_PIO0_1 (17) /* Vector 17: PIO0_1 */
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#define LPC11_IRQ_PIO0_2 (18) /* Vector 18: PIO0_2 */
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#define LPC11_IRQ_PIO0_3 (19) /* Vector 19: PIO0_3 */
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#define LPC11_IRQ_PIO0_4 (20) /* Vector 20: PIO0_4 */
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#define LPC11_IRQ_PIO0_5 (21) /* Vector 21: PIO0_5 */
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#define LPC11_IRQ_PIO0_6 (22) /* Vector 22: PIO0_6 */
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#define LPC11_IRQ_PIO0_7 (23) /* Vector 23: PIO0_7 */
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#define LPC11_IRQ_PIO0_8 (24) /* Vector 24: PIO0_8 */
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#define LPC11_IRQ_PIO0_9 (25) /* Vector 25: PIO0_9 */
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#define LPC11_IRQ_PIO0_10 (26) /* Vector 26: PIO0_10 */
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#define LPC11_IRQ_PIO0_11 (27) /* Vector 27: PIO0_11 */
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#define LPC11_IRQ_PIO1_0 (28) /* Vector 28: PIO1_0 */
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#define LPC11_IRQ_CCAN (29) /* Vector 29: C_CAN controller for LPC11Cxx */
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#define LPC11_IRQ_SSP1 (30) /* Vector 30: SPI1/SSP1 */
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#define LPC11_IRQ_I2C0 (31) /* Vector 31: I2C0 */
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#define LPC11_IRQ_CT16B0 (32) /* Vector 32: Clock/Timer0 16 bits */
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#define LPC11_IRQ_CT16B1 (33) /* Vector 33: Clock/Timer1 16 bits */
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#define LPC11_IRQ_CT32B0 (34) /* Vector 34: Clock/Timer0 32 bits */
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#define LPC11_IRQ_CT32B1 (35) /* Vector 35: Clock/Timer1 32 bits */
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#define LPC11_IRQ_SSP0 (36) /* Vector 36: SPI0/SSP0 */
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#define LPC11_IRQ_UART (37) /* Vector 37: UART */
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/* Vector 38: Reserved */
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/* Vector 39: Reserved */
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#define LPC11_IRQ_ADC (40) /* Vector 40: Analog/Digital Converter */
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#define LPC11_IRQ_WDT (41) /* Vector 41: Watchdog timer */
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#define LPC11_IRQ_BOD (42) /* Vector 42: Brownout Detection */
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/* Vector 43: Reserved */
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#define LPC11_IRQ_PIO3 (44) /* Vector 44: PIO3 */
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#define LPC11_IRQ_PIO2 (45) /* Vector 45: PIO2 */
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#define LPC11_IRQ_PIO1 (46) /* Vector 46: PIO1 */
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#define LPC11_IRQ_PIO0 (47) /* Vector 47: PIO0 */
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#endif
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#define NR_IRQS (48) /* 32 interrupts plus 16 exceptions */
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/****************************************************************************
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* Public Types
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****************************************************************************/
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#ifndef __ASSEMBLY__
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typedef void (*vic_vector_t)(uint32_t *regs);
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/****************************************************************************
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* Inline functions
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****************************************************************************/
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/****************************************************************************
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* Public Data
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****************************************************************************/
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/****************************************************************************
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* Public Function Prototypes
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****************************************************************************/
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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#ifdef __cplusplus
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}
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#endif
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#endif /* __ASSEMBLY__ */
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#endif /* __ARCH_ARM_INCLUDE_LPC11XX_IRQ_H */
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