From ad02edd8d4b5a16c19441bd75c75b524716f58a4 Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Tue, 18 Aug 2026 12:01:32 +0200 Subject: [PATCH] drivers/net/igb: Access registers at the required width. Launder each register value through a register with an empty asm, on loads and stores both, so the access is the width the source specifies. Same fix as usbhost_xhci_pci.c commit 4b702058f6. Signed-off-by: raiden00pl Assisted-by: Claude Code --- drivers/net/igb.c | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/drivers/net/igb.c b/drivers/net/igb.c index 66b12f055f4..0c22215535e 100644 --- a/drivers/net/igb.c +++ b/drivers/net/igb.c @@ -274,6 +274,12 @@ static const struct netdev_ops_s g_igb_ops = * Private Functions *****************************************************************************/ +/* The device requires 32-bit register accesses, but volatile does not pin + * the access width: GCC 16 narrows a 32-bit load feeding a single bit test + * into a byte load. Launder the value through a register with an empty + * asm, on loads and stores both, to force the full-width access. + */ + /***************************************************************************** * Name: igb_getreg_mem *****************************************************************************/ @@ -281,8 +287,11 @@ static const struct netdev_ops_s g_igb_ops = static uint32_t igb_getreg_mem(FAR struct igb_driver_s *priv, unsigned int offset) { - uintptr_t addr = priv->base + offset; - return *((FAR volatile uint32_t *)addr); + uintptr_t addr = priv->base + offset; + uint32_t regval = *((FAR volatile uint32_t *)addr); + + __asm__ __volatile__("" : "+r"(regval)); + return regval; } /***************************************************************************** @@ -294,6 +303,8 @@ static void igb_putreg_mem(FAR struct igb_driver_s *priv, uint32_t value) { uintptr_t addr = priv->base + offset; + + __asm__ __volatile__("" : "+r"(value)); *((FAR volatile uint32_t *)addr) = value; }