From ac583fc585260748da33ea1df8e8a8c2c0c52ede Mon Sep 17 00:00:00 2001 From: Matteo Golin Date: Mon, 28 Apr 2025 19:10:53 -0400 Subject: [PATCH] arch/arm/rp2040/gpio: Allow simultaneous selection of multiple interrupt modes. The RP2040 chip supports 4 different GPIO interrupt modes. They can be configured to be used simultaneously, although previously the NuttX support only allowed one type of interrupt to be enabled per GPIO pin. This allows up to all four to be selected without changing previous behaviour. Signed-off-by: Matteo Golin --- arch/arm/src/rp2040/rp2040_gpio.c | 8 +++++--- arch/arm/src/rp2040/rp2040_gpio.h | 8 ++++---- 2 files changed, 9 insertions(+), 7 deletions(-) diff --git a/arch/arm/src/rp2040/rp2040_gpio.c b/arch/arm/src/rp2040/rp2040_gpio.c index caf705df9ab..c2a20c0713b 100644 --- a/arch/arm/src/rp2040/rp2040_gpio.c +++ b/arch/arm/src/rp2040/rp2040_gpio.c @@ -284,7 +284,8 @@ void rp2040_gpio_init(uint32_t gpio) * Name: r2040_gpio_irq_attach * * Description: - * Configure the interrupt generated by the specified GPIO pin. + * Configure the interrupt generated by the specified GPIO pin. Multiple + * interrupt modes can be set at once by ORing together interrupt modes. * ****************************************************************************/ @@ -332,11 +333,12 @@ void rp2040_gpio_enable_irq(uint32_t gpio) if (g_gpio_irq_handlers[gpio] != NULL) { - /* Set interrupt enable bit */ + /* Set interrupt enable bits based on selected modes */ reg = RP2040_IO_BANK0_PROC_INTE(gpio, 0); clrbits_reg32(0xf << ((gpio % 8) * 4), reg); - setbits_reg32(0x1 << ((gpio % 8) * 4 + g_gpio_irq_modes[gpio]), reg); + setbits_reg32( + ((uint8_t)g_gpio_irq_modes[gpio] & 0xf) << ((gpio % 8) * 4), reg); } } diff --git a/arch/arm/src/rp2040/rp2040_gpio.h b/arch/arm/src/rp2040/rp2040_gpio.h index a36d8b7290c..0ac77962eff 100644 --- a/arch/arm/src/rp2040/rp2040_gpio.h +++ b/arch/arm/src/rp2040/rp2040_gpio.h @@ -66,10 +66,10 @@ /* GPIO interrupt modes *****************************************************/ -#define RP2040_GPIO_INTR_LEVEL_LOW 0 -#define RP2040_GPIO_INTR_LEVEL_HIGH 1 -#define RP2040_GPIO_INTR_EDGE_LOW 2 -#define RP2040_GPIO_INTR_EDGE_HIGH 3 +#define RP2040_GPIO_INTR_LEVEL_LOW (0x1) +#define RP2040_GPIO_INTR_LEVEL_HIGH (0x2) +#define RP2040_GPIO_INTR_EDGE_LOW (0x4) +#define RP2040_GPIO_INTR_EDGE_HIGH (0x8) /**************************************************************************** * Public Types