diff --git a/arch/arm/src/imxrt/Kconfig b/arch/arm/src/imxrt/Kconfig
index ce807e39c75..b89db3dac00 100644
--- a/arch/arm/src/imxrt/Kconfig
+++ b/arch/arm/src/imxrt/Kconfig
@@ -3000,6 +3000,17 @@ config IMXRT_USDHC1_INVERT_CD
 		If the board defines PIN_USDHC1_CD_GPIO it is assumed to be active low.
 		Selecting IMXRT_USDHC1_INVERT_CD will make it active high.
 
+config IMXRT_USDHC1_SD_HS_MODE
+	bool "Support SD card high speed mode on USDHC1"
+	default n
+	depends on IMXRT_USDHC1
+	---help---
+		Report SDIO_CAPS_SD_HS_MODE so that the generic MMC/SD driver
+		switches an inserted SD card into high speed mode (CMD6) and
+		raises the bus clock accordingly, once the card confirms the
+		switch. The board must provide BOARD_USDHC_SD4MODE_HS_PRESCALER/
+		BOARD_USDHC_SD4MODE_HS_DIVISOR in board.h for the higher clock.
+
 choice
 	depends on IMXRT_USDHC2
 	prompt "Bus width for USDHC2"
@@ -3027,6 +3038,17 @@ config IMXRT_USDHC2_INVERT_CD
 		If the board defines PIN_USDHC2_CD_GPIO it is assumed to be active low.
 		Selecting IMXRT_USDHC2_INVERT_CD will make it active high.
 
+config IMXRT_USDHC2_SD_HS_MODE
+	bool "Support SD card high speed mode on USDHC2"
+	default n
+	depends on IMXRT_USDHC2
+	---help---
+		Report SDIO_CAPS_SD_HS_MODE so that the generic MMC/SD driver
+		switches an inserted SD card into high speed mode (CMD6) and
+		raises the bus clock accordingly, once the card confirms the
+		switch. The board must provide BOARD_USDHC_SD4MODE_HS_PRESCALER/
+		BOARD_USDHC_SD4MODE_HS_DIVISOR in board.h for the higher clock.
+
 endmenu # USDHC Configuration
 
 menu "eDMA Configuration"
diff --git a/arch/arm/src/imxrt/imxrt_usdhc.c b/arch/arm/src/imxrt/imxrt_usdhc.c
index 9bce9e756ff..d63253c91ae 100644
--- a/arch/arm/src/imxrt/imxrt_usdhc.c
+++ b/arch/arm/src/imxrt/imxrt_usdhc.c
@@ -1511,6 +1511,9 @@ static sdio_capset_t imxrt_capabilities(struct sdio_dev_s *dev)
 #endif
 #ifdef CONFIG_IMXRT_USDHC1_WIDTH_D1_D4
         caps |= SDIO_CAPS_4BIT;
+#endif
+#ifdef CONFIG_IMXRT_USDHC1_SD_HS_MODE
+        caps |= SDIO_CAPS_SD_HS_MODE;
 #endif
         break;
 
@@ -1523,6 +1526,9 @@ static sdio_capset_t imxrt_capabilities(struct sdio_dev_s *dev)
 #endif
 #ifdef CONFIG_IMXRT_USDHC2_WIDTH_D1_D8
         caps |= SDIO_CAPS_8BIT;
+#endif
+#ifdef CONFIG_IMXRT_USDHC2_SD_HS_MODE
+        caps |= SDIO_CAPS_SD_HS_MODE;
 #endif
         break;
 
@@ -1855,6 +1861,21 @@ static void imxrt_clock(struct sdio_dev_s *dev, enum sdio_clock_e rate)
                     BOARD_USDHC_SD4MODE_DIVISOR);
         }
         break;
+
+#if defined(CONFIG_IMXRT_USDHC1_SD_HS_MODE) || \
+    defined(CONFIG_IMXRT_USDHC2_SD_HS_MODE)
+      case CLOCK_SD_TRANSFER_4BIT_HS:
+        {
+          /* SD high speed clocking (wide 4-bit mode), sent only after the
+           * card has confirmed the CMD6 high speed switch.
+           */
+
+          mcinfo("4BITTRANSFER_HS\n");
+          regval |= (BOARD_USDHC_SD4MODE_HS_PRESCALER |
+                    BOARD_USDHC_SD4MODE_HS_DIVISOR);
+        }
+        break;
+#endif
     }
 
   putreg32(regval, priv->addr + IMXRT_USDHC_SYSCTL_OFFSET);