mirror of
https://github.com/apache/nuttx.git
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arch/risc-v/src: Fix nxstyle warnings
No functional changes
This commit is contained in:
Yoshinori Sugino
Abdelatif Guettouche
parent
20f701f2ec
commit
aae4e15d9b
24 changed files with 332 additions and 277 deletions
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@ -65,7 +65,7 @@ extern "C"
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#endif
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/****************************************************************************
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* Public Functions
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* Public Function Prototypes
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****************************************************************************/
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EXTERN uint32_t fe310_get_hfclk(void);
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@ -45,7 +45,7 @@
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#include "chip.h"
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/****************************************************************************
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* Public Functions
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* Public Function Prototypes
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****************************************************************************/
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#ifndef __ASSEMBLY__
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@ -66,9 +66,9 @@ typedef struct
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volatile uint32_t START_HI; /* Timer start Register for high 32-bits */
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volatile uint32_t RESET_LO; /* Timer reset Register for low 32-bits */
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volatile uint32_t RESET_HI; /* Timer reset Register for high 32-bits */
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} BASIC_TIM_reg_t;
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} basic_tim_reg_t;
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#define BASIC_TIM ((BASIC_TIM_reg_t*)(CORE_PERI_BASE + 0x0400UL))
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#define BASIC_TIM ((basic_tim_reg_t*)(CORE_PERI_BASE + 0x0400UL))
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#define BASIC_TIM_CASC_ENABLE (1L << 31)
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#define BASIC_TIM_CASC_DISABLE (0L << 31)
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@ -91,10 +91,10 @@ typedef struct
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volatile uint32_t ICACHE_LX_SEL_FLUSH; /* Cluster Icache Level-X Flush Register or FC Flush Selected Address Register */
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volatile uint32_t ICACHE_SEL_FLUSH_STATUS; /* Cluster Icache Flush Selected Address Register or FC ICACHE status */
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volatile uint32_t ICACHE_IS_PRI; /* Cluster Icache is private Icache */
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} SCBC_reg_t;
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} scbc_reg_t;
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#define CORE_SCBC_BASE (CORE_PERI_BASE + 0x1400UL) /* RISC Core System Control Block Cache Base Address */
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#define SCBC ((SCBC_reg_t*)CORE_SCBC_BASE) /* Icache SCBC configuration struct */
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#define SCBC ((scbc_reg_t*)CORE_SCBC_BASE) /* Icache SCBC configuration struct */
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/* FLL_CTRL */
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@ -109,23 +109,27 @@ typedef struct
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volatile uint32_t CLUSTER_CONF2; /* Configuration2 register */
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volatile uint32_t CLUSTER_INTEGRATOR; /* INTEGRATOR register */
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volatile uint32_t FLL_CONVERGE; /* Fll Converge register */
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} FLL_CTRL_reg_t;
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} fll_ctrl_reg_t;
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#define FLL_CTRL ((FLL_CTRL_reg_t *)SOC_PERI_BASE)
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#define FLL_CTRL ((fll_ctrl_reg_t *)SOC_PERI_BASE)
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/* FLL_STATUS - FLL_CTRL status register */
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#define FLL_CTRL_STATUS_MULTI_FACTOR_MASK (0xFFFFU)
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#define FLL_CTRL_STATUS_MULTI_FACTOR_SHIFT (0U)
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#define FLL_CTRL_STATUS_MULTI_FACTOR(x) (((uint32_t)(x) /* << FLL_CTRL_STATUS_MULTI_FACTOR_SHIFT */) & FLL_CTRL_STATUS_MULTI_FACTOR_MASK)
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#define READ_FLL_CTRL_STATUS_MULTI_FACTOR(x) (((uint32_t)(x) & FLL_CTRL_STATUS_MULTI_FACTOR_MASK) /*>> FLL_CTRL_STATUS_MULTI_FACTOR_SHIFT*/)
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#define READ_FLL_CTRL_STATUS_MULTI_FACTOR(x) (((uint32_t)(x) & FLL_CTRL_STATUS_MULTI_FACTOR_MASK) /* >> FLL_CTRL_STATUS_MULTI_FACTOR_SHIFT */)
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/* SOC_CONF1 - FLL_CTRL configuration 1 register */
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#define FLL_CTRL_CONF1_MULTI_FACTOR_MASK (0xFFFFU)
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#define FLL_CTRL_CONF1_MULTI_FACTOR_SHIFT (0U)
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#define FLL_CTRL_CONF1_MULTI_FACTOR(x) (((uint32_t)(x) /* << FLL_CTRL_CONF1_MULTI_FACTOR_SHIFT */) & FLL_CTRL_CONF1_MULTI_FACTOR_MASK)
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#define READ_FLL_CTRL_CONF1_MULTI_FACTOR(x) (((uint32_t)(x) & FLL_CTRL_CONF1_MULTI_FACTOR_MASK) /*>> FLL_CTRL_CONF1_MULTI_FACTOR_SHIFT*/)
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#define READ_FLL_CTRL_CONF1_MULTI_FACTOR(x) (((uint32_t)(x) & FLL_CTRL_CONF1_MULTI_FACTOR_MASK) /* >> FLL_CTRL_CONF1_MULTI_FACTOR_SHIFT */)
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#define FLL_CTRL_CONF1_DCO_INPUT_MASK (0x3FF0000U)
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#define FLL_CTRL_CONF1_DCO_INPUT_SHIFT (16U)
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@ -151,8 +155,10 @@ typedef struct
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#define FLL_CTRL_CONF2_LOOPGAIN_MASK (0xFU)
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#define FLL_CTRL_CONF2_LOOPGAIN_SHIF T (0U)
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#define FLL_CTRL_CONF2_LOOPGAIN(x) (((uint32_t)(x) /* << FLL_CTRL_CONF2_LOOPGAIN_SHIFT */) & FLL_CTRL_CONF2_LOOPGAIN_MASK)
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#define READ_FLL_CTRL_CONF2_LOOPGAIN(x) (((uint32_t)(x) & FLL_CTRL_CONF2_LOOPGAIN_MASK)/* >> FLL_CTRL_CONF2_LOOPGAIN_SHIFT*/)
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#define READ_FLL_CTRL_CONF2_LOOPGAIN(x) (((uint32_t)(x) & FLL_CTRL_CONF2_LOOPGAIN_MASK)/* >> FLL_CTRL_CONF2_LOOPGAIN_SHIFT */)
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#define FLL_CTRL_CONF2_DEASSERT_CYCLES_MASK (0x3F0U)
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#define FLL_CTRL_CONF2_DEASSERT_CYCLES_SHIFT (4U)
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@ -200,8 +206,10 @@ typedef struct
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#define FLL_CTRL_SOC_FLL_CONV_MASK (0x1U)
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#define FLL_CTRL_SOC_FLL_CONV_SHIFT (0U)
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#define FLL_CTRL_SOC_FLL_CONV(x) (((uint32_t)(x) /*<< FLL_CTRL_SOC_FLL_CONV_SHIFT */) & FLL_CTRL_SOC_FLL_CONV_MASK)
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#define READ_FLL_CTRL_SOC_FLL_CONV(x) (((uint32_t)(x) & FLL_CTRL_SOC_FLL_CONV_MASK) /*>> FLL_CTRL_SOC_FLL_CONV_SHIFT*/)
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#define FLL_CTRL_SOC_FLL_CONV(x) (((uint32_t)(x) /* << FLL_CTRL_SOC_FLL_CONV_SHIFT */) & FLL_CTRL_SOC_FLL_CONV_MASK)
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#define READ_FLL_CTRL_SOC_FLL_CONV(x) (((uint32_t)(x) & FLL_CTRL_SOC_FLL_CONV_MASK) /* >> FLL_CTRL_SOC_FLL_CONV_SHIFT */)
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#define FLL_CTRL_CLUSTER_FLL_CONV_MASK (0x2U)
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#define FLL_CTRL_CLUSTER_FLL_CONV_SHIFT (1U)
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@ -228,7 +236,7 @@ typedef struct
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volatile uint32_t INTSTATUS; /* gpio int status register */
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volatile uint32_t EN; /* gpio enable register */
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volatile uint32_t PADCFG[8]; /* pad configuration registers */
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} GPIO_reg_t;
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} gpio_reg_t;
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#define GPIO_INTCFG_TYPE_MASK (0x3U)
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#define GPIO_INTCFG_TYPE_SHIFT (0U)
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@ -238,7 +246,7 @@ typedef struct
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/* Peripheral GPIOA base pointer */
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#define GPIOA ((GPIO_reg_t *)(SOC_PERI_BASE + 0x1000u))
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#define GPIOA ((gpio_reg_t *)(SOC_PERI_BASE + 0x1000u))
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/* UDMA - General Register Layout Typedef */
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@ -252,13 +260,13 @@ typedef struct
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volatile uint32_t TX_SIZE; /* TX UDMA buffer transfer size register */
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volatile uint32_t TX_CFG; /* TX UDMA transfer configuration register */
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volatile uint32_t TX_INITCFG; /* Reserved */
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} UDMA_reg_t;
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} udma_reg_t;
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/* RX_SADDR - RX TX UDMA buffer transfer address register */
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#define UDMA_SADDR_ADDR_MASK (0xFFFFU)
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#define UDMA_SADDR_ADDR_SHIFT (0U)
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#define UDMA_SADDR_ADDR(x) (((uint32_t)(x) /*<< UDMA_SADDR_ADDR_SHIFT*/) & UDMA_SADDR_ADDR_MASK)
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#define UDMA_SADDR_ADDR(x) (((uint32_t)(x) /* << UDMA_SADDR_ADDR_SHIFT */) & UDMA_SADDR_ADDR_MASK)
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/* RX_SIZE - RX TX UDMA buffer transfer size register */
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@ -270,7 +278,7 @@ typedef struct
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#define UDMA_CFG_CONTINOUS_MASK (0x1U)
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#define UDMA_CFG_CONTINOUS_SHIFT (0U)
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#define UDMA_CFG_CONTINOUS(x) (((uint32_t)(x) /*<< UDMA_CFG_CONTINOUS_SHIFT*/) & UDMA_CFG_CONTINOUS_MASK)
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#define UDMA_CFG_CONTINOUS(x) (((uint32_t)(x) /* << UDMA_CFG_CONTINOUS_SHIFT */) & UDMA_CFG_CONTINOUS_MASK)
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#define UDMA_CFG_DATA_SIZE_MASK (0x6U)
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#define UDMA_CFG_DATA_SIZE_SHIFT (1U)
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#define UDMA_CFG_DATA_SIZE(x) (((uint32_t)(x) << UDMA_CFG_DATA_SIZE_SHIFT) & UDMA_CFG_DATA_SIZE_MASK)
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@ -291,12 +299,14 @@ typedef struct
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{
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volatile uint32_t CG; /* clock gating register */
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volatile uint32_t EVTIN; /* input event register */
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} UDMA_GC_reg_t;
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} udma_gc_reg_t;
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#define UDMA_GC_BASE (UDMA_BASE + 0x780u)
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#define UDMA_GC ((UDMA_GC_reg_t *)UDMA_GC_BASE)
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#define UDMA_GC ((udma_gc_reg_t *)UDMA_GC_BASE)
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/* UDMA_GC - UDMA event in register, User chooses which events can come to UDMA as reference events, support up to 4 choices */
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/* UDMA_GC - UDMA event in register, User chooses which events can come to
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* UDMA as reference events, support up to 4 choices
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*/
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#define UDMA_GC_EVTIN_CHOICE0_MASK (0xFFU)
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#define UDMA_GC_EVTIN_CHOICE0_SHIFT (0U)
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@ -318,20 +328,20 @@ typedef struct
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typedef struct
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{
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UDMA_reg_t UDMA_LVDS; /* UDMA general register */
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udma_reg_t UDMA_LVDS; /* UDMA general register */
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volatile uint32_t RF_CFG; /* configuration register */
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volatile uint32_t RF_GPIO; /* Reserved */
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volatile uint32_t RF_STATUS; /* Status register */
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} LVDS_reg_t;
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} lvds_reg_t;
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#define LVDS_BASE (UDMA_BASE + 0 * 128U)
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#define LVDS ((LVDS_reg_t *)LVDS_BASE)
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#define LVDS ((lvds_reg_t *)LVDS_BASE)
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/* RF_CFG - LVDS configuration register */
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#define LVDS_RF_CFG_TX_ENB_MASK (0x1U)
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#define LVDS_RF_CFG_TX_ENB_SHIFT (0U)
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#define LVDS_RF_CFG_TX_ENB(x) (((uint32_t)(x) << /*LVDS_RF_CFG_TX_ENB_SHIFT*/) & LVDS_RF_CFG_TX_ENB_MASK)
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#define LVDS_RF_CFG_TX_ENB(x) (((uint32_t)(x) << /* LVDS_RF_CFG_TX_ENB_SHIFT */) & LVDS_RF_CFG_TX_ENB_MASK)
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#define LVDS_RF_CFG_TX_OEB_MASK (0x2U)
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#define LVDS_RF_CFG_TX_OEB_SHIFT (1U)
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@ -385,13 +395,13 @@ typedef struct
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#define LVDS_RF_STATUS_SYNC_FLAG_MASK (0x1U)
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#define LVDS_RF_STATUS_SYNC_FLAG_SHIFT (0U)
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#define LVDS_RF_STATUS_SYNC_FLAG(x) (((uint32_t)(x) /*<< LVDS_RF_STATUS_SYNC_FLAG_SHIFT*/) & LVDS_RF_STATUS_SYNC_FLAG_MASK)
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#define LVDS_RF_STATUS_SYNC_FLAG(x) (((uint32_t)(x) /* << LVDS_RF_STATUS_SYNC_FLAG_SHIFT */) & LVDS_RF_STATUS_SYNC_FLAG_MASK)
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/* ORCA - Register Layout Typedef */
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typedef struct
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{
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UDMA_reg_t UDMA_ORCA; /* ORCA UDMA general register */
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udma_reg_t UDMA_ORCA; /* ORCA UDMA general register */
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volatile uint32_t RF_CFG; /* ORCA configuration register */
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volatile uint32_t RF_GPIO; /* Reserved */
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volatile uint32_t RF_STATUS; /* ORCA Status register */
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@ -401,16 +411,16 @@ typedef struct
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volatile uint32_t CLKDIV_UPD; /* ORCA uDMA clock divider data register */
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volatile uint32_t ORCA_CFG; /* ORCA configuration register */
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volatile uint32_t CNT_EVENT; /* ORCA Status register */
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} ORCA_reg_t;
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} orca_reg_t;
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#define ORCA_BASE (UDMA_BASE + 0 * 128U)
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#define ORCA ((ORCA_reg_t *)ORCA_BASE)
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#define ORCA ((orca_reg_t *)ORCA_BASE)
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/* RF_CFG - ORCA configuration register */
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#define ORCA_RF_CFG_TX_ENB_MASK (0x1U)
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#define ORCA_RF_CFG_TX_ENB_SHIFT (0U)
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#define ORCA_RF_CFG_TX_ENB(x) (((uint32_t)(x) /*<< ORCA_RF_CFG_TX_ENB_SHIFT*/) & ORCA_RF_CFG_TX_ENB_MASK)
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#define ORCA_RF_CFG_TX_ENB(x) (((uint32_t)(x) /* << ORCA_RF_CFG_TX_ENB_SHIFT */) & ORCA_RF_CFG_TX_ENB_MASK)
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#define ORCA_RF_CFG_TX_OEB_MASK (0x2U)
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#define ORCA_RF_CFG_TX_OEB_SHIFT (1U)
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@ -464,31 +474,31 @@ typedef struct
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#define ORCA_RF_STATUS_SYNC_FLAG_MASK (0x1U)
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#define ORCA_RF_STATUS_SYNC_FLAG_SHIFT (0U)
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#define ORCA_RF_STATUS_SYNC_FLAG(x) (((uint32_t)(x) /*<< ORCA_RF_STATUS_SYNC_FLAG_SHIFT*/) & ORCA_RF_STATUS_SYNC_FLAG_MASK)
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#define ORCA_RF_STATUS_SYNC_FLAG(x) (((uint32_t)(x) /* << ORCA_RF_STATUS_SYNC_FLAG_SHIFT */) & ORCA_RF_STATUS_SYNC_FLAG_MASK)
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/* CLKDIV_EN - ORCA uDMA clock divider enable register */
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#define ORCA_CLKDIV_EN_MASK (0x1U)
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#define ORCA_CLKDIV_EN_SHIFT (0U)
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#define ORCA_CLKDIV_EN(x) (((uint32_t)(x) /*<< ORCA_CLKDIV_EN_SHIFT*/) & ORCA_CLKDIV_EN_MASK)
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#define ORCA_CLKDIV_EN(x) (((uint32_t)(x) /* << ORCA_CLKDIV_EN_SHIFT */) & ORCA_CLKDIV_EN_MASK)
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/* CLKDIV_CFG - ORCA uDMA clock divider configuration register */
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#define ORCA_CLKDIV_CFG_MASK (0xFFU)
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#define ORCA_CLKDIV_CFG_SHIFT (0U)
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#define ORCA_CLKDIV_CFG(x) (((uint32_t)(x) /*<< ORCA_CLKDIV_CFG_SHIFT*/) & ORCA_CLKDIV_CFG_MASK)
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#define ORCA_CLKDIV_CFG(x) (((uint32_t)(x) /* << ORCA_CLKDIV_CFG_SHIFT */) & ORCA_CLKDIV_CFG_MASK)
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/* CLKDIV_UDP - ORCA uDMA clock divider enable register */
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#define ORCA_CLKDIV_UDP_MASK (0x1U)
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#define ORCA_CLKDIV_UDP_SHIFT (0U)
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#define ORCA_CLKDIV_UDP(x) (((uint32_t)(x) /*<< ORCA_CLKDIV_UDP_SHIFT*/) & ORCA_CLKDIV_UDP_MASK)
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#define ORCA_CLKDIV_UDP(x) (((uint32_t)(x) /* << ORCA_CLKDIV_UDP_SHIFT */) & ORCA_CLKDIV_UDP_MASK)
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/* ORCA_CFG - ORCA configuration register */
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#define ORCA_CFG_SIZE_MASK (0xFU)
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#define ORCA_CFG_SIZE_SHIFT (0U)
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#define ORCA_CFG_SIZE(x) (((uint32_t)(x) /*<< ORCA_CFG_SIZE_SHIFT*/) & ORCA_CFG_SIZE_MASK)
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#define ORCA_CFG_SIZE(x) (((uint32_t)(x) /* << ORCA_CFG_SIZE_SHIFT */) & ORCA_CFG_SIZE_MASK)
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#define ORCA_CFG_DELAY_MASK (0xF0U)
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#define ORCA_CFG_DELAY_SHIFT (4U)
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@ -502,13 +512,13 @@ typedef struct
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typedef struct
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{
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UDMA_reg_t UDMA_SPIM; /* SPIM UDMA general register */
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} SPIM_reg_t;
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udma_reg_t UDMA_SPIM; /* SPIM UDMA general register */
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} spim_reg_t;
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#define SPIM0_BASE (UDMA_BASE + 1 * 128U)
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#define SPIM0 ((SPIM_reg_t *)SPIM0_BASE)
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#define SPIM0 ((spim_reg_t *)SPIM0_BASE)
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#define SPIM1_BASE (UDMA_BASE + 2 * 128U)
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#define SPIM1 ((SPIM_reg_t *)SPIM1_BASE)
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#define SPIM1 ((spim_reg_t *)SPIM1_BASE)
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/* uDMA - SPIM uDMA control CMD */
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@ -536,7 +546,7 @@ typedef struct
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#define SPIM_CMD_CFG_CLKDIV_MASK (0xFFU)
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#define SPIM_CMD_CFG_CLKDIV_SHIFT (0U)
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#define SPIM_CMD_CFG_CLKDIV(x) (((uint32_t)(x) /*<< SPIM_CMD_CFG_CLKDIV_SHIFT*/) & SPIM_CMD_CFG_CLKDIV_MASK)
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#define SPIM_CMD_CFG_CLKDIV(x) (((uint32_t)(x) /* << SPIM_CMD_CFG_CLKDIV_SHIFT */) & SPIM_CMD_CFG_CLKDIV_MASK)
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#define SPIM_CMD_CFG_CPHA_MASK (0x100U)
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#define SPIM_CMD_CFG_CPHA_SHIFT (8U)
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#define SPIM_CMD_CFG_CPHA(x) (((uint32_t)(x) << SPIM_CMD_CFG_CPHA_SHIFT) & SPIM_CMD_CFG_CPHA_MASK)
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@ -554,7 +564,7 @@ typedef struct
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#define SPIM_CMD_SEND_VALUEL_MASK (0xFFU)
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#define SPIM_CMD_SEND_VALUEL_SHIFT (0U)
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#define SPIM_CMD_SEND_VALUEL(x) (((uint32_t)(x) /*<< SPIM_CMD_SEND_VALUEL_SHIFT*/) & SPIM_CMD_SEND_VALUEL_MASK)
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#define SPIM_CMD_SEND_VALUEL(x) (((uint32_t)(x) /* << SPIM_CMD_SEND_VALUEL_SHIFT */) & SPIM_CMD_SEND_VALUEL_MASK)
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#define SPIM_CMD_SEND_VALUEH_MASK (0xFF00U)
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#define SPIM_CMD_SEND_VALUEH_SHIFT (8U)
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#define SPIM_CMD_SEND_VALUEH(x) (((uint32_t)(x) << SPIM_CMD_SEND_VALUEH_SHIFT) & SPIM_CMD_SEND_VALUEH_MASK)
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@ -569,7 +579,7 @@ typedef struct
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#define SPIM_CMD_SEND_ADDR_VALUE_MASK (0xFFFFU)
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#define SPIM_CMD_SEND_ADDR_VALUE_SHIFT (0U)
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#define SPIM_CMD_SEND_ADDR_VALUE(x) (((uint32_t)(x) /*<< SPIM_CMD_SEND_ADDR_VALUE_SHIFT*/) & SPIM_CMD_SEND_ADDR_VALUE_MASK)
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#define SPIM_CMD_SEND_ADDR_VALUE(x) (((uint32_t)(x) /* << SPIM_CMD_SEND_ADDR_VALUE_SHIFT */) & SPIM_CMD_SEND_ADDR_VALUE_MASK)
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#define SPIM_CMD_SEND_ADDR_CMD_SIZE_MASK (0x1F0000U)
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#define SPIM_CMD_SEND_ADDR_CMD_SIZE_SHIFT (16U)
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#define SPIM_CMD_SEND_ADDR_CMD_SIZE(x) (((uint32_t)(x) << SPIM_CMD_SEND_ADDR_CMD_SIZE_SHIFT) & SPIM_CMD_SEND_ADDR_CMD_SIZE_MASK)
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@ -587,13 +597,13 @@ typedef struct
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#define SPIM_CMD_WAIT_EVENT_ID_MASK (0x3U)
|
||||
#define SPIM_CMD_WAIT_EVENT_ID_SHIFT (0U)
|
||||
#define SPIM_CMD_WAIT_EVENT_ID(x) (((uint32_t)(x) /*<< SPIM_CMD_WAIT_EVENT_ID_SHIFT*/) & SPIM_CMD_WAIT_EVENT_ID_MASK)
|
||||
#define SPIM_CMD_WAIT_EVENT_ID(x) (((uint32_t)(x) /* << SPIM_CMD_WAIT_EVENT_ID_SHIFT */) & SPIM_CMD_WAIT_EVENT_ID_MASK)
|
||||
|
||||
/* CMD_TX_DATA - SPIM send data */
|
||||
|
||||
#define SPIM_CMD_TX_DATA_SIZE_MASK (0xFFFFU)
|
||||
#define SPIM_CMD_TX_DATA_SIZE_SHIFT (0U)
|
||||
#define SPIM_CMD_TX_DATA_SIZE(x) (((uint32_t)(x) /*<< SPIM_CMD_TX_DATA_SIZE_SHIFT*/) & SPIM_CMD_TX_DATA_SIZE_MASK)
|
||||
#define SPIM_CMD_TX_DATA_SIZE(x) (((uint32_t)(x) /* << SPIM_CMD_TX_DATA_SIZE_SHIFT */) & SPIM_CMD_TX_DATA_SIZE_MASK)
|
||||
#define SPIM_CMD_TX_DATA_BYTE_ALIGN_MASK (0x4000000U)
|
||||
#define SPIM_CMD_TX_DATA_BYTE_ALIGN_SHIFT (26U)
|
||||
#define SPIM_CMD_TX_DATA_BYTE_ALIGN(x) (((uint32_t)(x) << SPIM_CMD_TX_DATA_BYTE_ALIGN_SHIFT) & SPIM_CMD_TX_DATA_BYTE_ALIGN_MASK)
|
||||
|
|
@ -605,7 +615,7 @@ typedef struct
|
|||
|
||||
#define SPIM_CMD_RX_DATA_SIZE_MASK (0xFFFFU)
|
||||
#define SPIM_CMD_RX_DATA_SIZE_SHIFT (0U)
|
||||
#define SPIM_CMD_RX_DATA_SIZE(x) (((uint32_t)(x) /*<< SPIM_CMD_RX_DATA_SIZE_SHIFT*/) & SPIM_CMD_RX_DATA_SIZE_MASK)
|
||||
#define SPIM_CMD_RX_DATA_SIZE(x) (((uint32_t)(x) /* << SPIM_CMD_RX_DATA_SIZE_SHIFT */) & SPIM_CMD_RX_DATA_SIZE_MASK)
|
||||
#define SPIM_CMD_RX_DATA_BYTE_ALIGN_MASK (0x4000000U)
|
||||
#define SPIM_CMD_RX_DATA_BYTE_ALIGN_SHIFT (26U)
|
||||
#define SPIM_CMD_RX_DATA_BYTE_ALIGN(x) (((uint32_t)(x) << SPIM_CMD_RX_DATA_BYTE_ALIGN_SHIFT) & SPIM_CMD_RX_DATA_BYTE_ALIGN_MASK)
|
||||
|
|
@ -617,25 +627,25 @@ typedef struct
|
|||
|
||||
#define SPIM_CMD_RPT_CNT_MASK (0xFFFFU)
|
||||
#define SPIM_CMD_RPT_CNT_SHIFT (0U)
|
||||
#define SPIM_CMD_RPT_CNT(x) (((uint32_t)(x) /*<< SPIM_CMD_RPT_CNT_SHIFT*/) & SPIM_CMD_RPT_CNT_MASK)
|
||||
#define SPIM_CMD_RPT_CNT(x) (((uint32_t)(x) /* << SPIM_CMD_RPT_CNT_SHIFT */) & SPIM_CMD_RPT_CNT_MASK)
|
||||
|
||||
/* CMD_EOT - SPIM clears the chip select (CS), and send a end event or not */
|
||||
|
||||
#define SPIM_CMD_EOT_EVENT_GEN_MASK (0x1U)
|
||||
#define SPIM_CMD_EOT_EVENT_GEN_SHIFT (0U)
|
||||
#define SPIM_CMD_EOT_EVENT_GEN(x) (((uint32_t)(x) /*<< SPIM_CMD_EOT_EVENT_GEN_SHIFT*/) & SPIM_CMD_EOT_EVENT_GEN_MASK)
|
||||
#define SPIM_CMD_EOT_EVENT_GEN(x) (((uint32_t)(x) /* << SPIM_CMD_EOT_EVENT_GEN_SHIFT */) & SPIM_CMD_EOT_EVENT_GEN_MASK)
|
||||
|
||||
/* CMD_RPT_END - SPIM End of the repeat loop */
|
||||
|
||||
#define SPIM_CMD_RPT_END_SPI_CMD_MASK (0xFU)
|
||||
#define SPIM_CMD_RPT_END_SPI_CMD_SHIFT (0U)
|
||||
#define SPIM_CMD_RPT_END_SPI_CMD(x) (((uint32_t)(x) /*<< SPIM_CMD_RPT_END_SPI_CMD_SHIFT*/) & SPIM_CMD_RPT_END_SPI_CMD_MASK)
|
||||
#define SPIM_CMD_RPT_END_SPI_CMD(x) (((uint32_t)(x) /* << SPIM_CMD_RPT_END_SPI_CMD_SHIFT */) & SPIM_CMD_RPT_END_SPI_CMD_MASK)
|
||||
|
||||
/* CMD_RX_CHECK - SPIM check up to 16 bits of data against an expected value */
|
||||
|
||||
#define SPIM_CMD_RX_CHECK_COMP_DATA_MASK (0xFFFFU)
|
||||
#define SPIM_CMD_RX_CHECK_COMP_DATA_SHIFT (0U)
|
||||
#define SPIM_CMD_RX_CHECK_COMP_DATA(x) (((uint32_t)(x) /*<< SPIM_CMD_RX_CHECK_COMP_DATA_SHIFT*/) & SPIM_CMD_RX_CHECK_COMP_DATA_MASK)
|
||||
#define SPIM_CMD_RX_CHECK_COMP_DATA(x) (((uint32_t)(x) /* << SPIM_CMD_RX_CHECK_COMP_DATA_SHIFT */) & SPIM_CMD_RX_CHECK_COMP_DATA_MASK)
|
||||
|
||||
/* The number of bits to check, maximum is 16bits */
|
||||
|
||||
|
|
@ -643,7 +653,9 @@ typedef struct
|
|||
#define SPIM_CMD_RX_CHECK_STATUS_SIZE_SHIFT (16U)
|
||||
#define SPIM_CMD_RX_CHECK_STATUS_SIZE(x) (((uint32_t)(x) << SPIM_CMD_RX_CHECK_STATUS_SIZE_SHIFT) & SPIM_CMD_RX_CHECK_STATUS_SIZE_MASK)
|
||||
|
||||
/* The type of checking, 0 - Equal; 1 - check the bits of one; 2 - check the bits of zero */
|
||||
/* The type of checking, 0 - Equal; 1 - check the bits of one;
|
||||
* 2 - check the bits of zero
|
||||
*/
|
||||
|
||||
#define SPIM_CMD_RX_CHECK_CHECK_TYPE_MASK (0x3000000U)
|
||||
#define SPIM_CMD_RX_CHECK_CHECK_TYPE_SHIFT (24U)
|
||||
|
|
@ -662,7 +674,7 @@ typedef struct
|
|||
|
||||
#define SPIM_CMD_FULL_SIZE_CMD_MASK (0xFFFFU)
|
||||
#define SPIM_CMD_FULL_SIZE_CMD_SHIFT (0U)
|
||||
#define SPIM_CMD_FULL_SIZE_CMD(x) (((uint32_t)(x) /*<< SPIM_CMD_FULL_SIZE_CMD_SHIFT*/) & SPIM_CMD_FULL_SIZE_CMD_MASK)
|
||||
#define SPIM_CMD_FULL_SIZE_CMD(x) (((uint32_t)(x) /* << SPIM_CMD_FULL_SIZE_CMD_SHIFT */) & SPIM_CMD_FULL_SIZE_CMD_MASK)
|
||||
#define SPIM_CMD_FULL_BYTE_ALIGN_CMD_MASK (0x4000000U)
|
||||
#define SPIM_CMD_FULL_BYTE_ALIGN_CMD_SHIFT (26U)
|
||||
#define SPIM_CMD_FULL_BYTE_ALIGN_CMD(x) (((uint32_t)(x) << SPIM_CMD_FULL_BYTE_ALIGN_CMD_SHIFT) & SPIM_CMD_FULL_BYTE_ALIGN_CMD_MASK)
|
||||
|
|
@ -731,7 +743,7 @@ typedef struct
|
|||
|
||||
typedef struct
|
||||
{
|
||||
UDMA_reg_t UDMA_HYPERBUS; /* UDMA general register */
|
||||
udma_reg_t UDMA_HYPERBUS; /* UDMA general register */
|
||||
volatile uint32_t EXT_ADDR; /* Memory access address register */
|
||||
volatile uint32_t EXT_CFG; /* Reserved */
|
||||
volatile uint32_t MEM_CFG0; /* Memory control Configuration register0 */
|
||||
|
|
@ -742,10 +754,10 @@ typedef struct
|
|||
volatile uint32_t MEM_CFG5; /* Memory control Configuration register5 */
|
||||
volatile uint32_t MEM_CFG6; /* Memory control Configuration register6 */
|
||||
volatile uint32_t MEM_CFG7; /* Memory control Configuration register7 */
|
||||
} HYPERBUS_reg_t;
|
||||
} hyperbus_reg_t;
|
||||
|
||||
#define HYPERBUS_BASE0 (UDMA_BASE + 3 * 128U)
|
||||
#define HYPERBUS0 ((HYPERBUS_reg_t *)HYPERBUS_BASE0)
|
||||
#define HYPERBUS0 ((hyperbus_reg_t *)HYPERBUS_BASE0)
|
||||
|
||||
/* MEM_CFG0 - HYPERBUS Memory control Configuration register0 */
|
||||
|
||||
|
|
@ -880,13 +892,13 @@ typedef struct
|
|||
|
||||
typedef struct
|
||||
{
|
||||
UDMA_reg_t UDMA_UART; /* UDMA general register */
|
||||
udma_reg_t UDMA_UART; /* UDMA general register */
|
||||
volatile uint32_t STATUS; /* Status register */
|
||||
volatile uint32_t SETUP; /* Configuration register */
|
||||
} UART_reg_t;
|
||||
} uart_reg_t;
|
||||
|
||||
#define UART_BASE (UDMA_BASE + 4 * 128U)
|
||||
#define UART ((UART_reg_t *)UART_BASE)
|
||||
#define UART ((uart_reg_t *)UART_BASE)
|
||||
|
||||
/* STATUS - UART Status register */
|
||||
|
||||
|
|
@ -930,16 +942,15 @@ typedef struct
|
|||
|
||||
typedef struct
|
||||
{
|
||||
UDMA_reg_t UDMA_I2C; /* UDMA general register */
|
||||
udma_reg_t UDMA_I2C; /* UDMA general register */
|
||||
volatile uint32_t STATUS; /* Status register */
|
||||
volatile uint32_t SETUP; /* Configuration register */
|
||||
|
||||
} I2C_reg_t;
|
||||
} i2c_reg_t;
|
||||
|
||||
#define I2C0_BASE (UDMA_BASE + 5 * 128U)
|
||||
#define I2C0 ((I2C_reg_t *)I2C0_BASE)
|
||||
#define I2C0 ((i2c_reg_t *)I2C0_BASE)
|
||||
#define I2C1_BASE (UDMA_BASE + 6 * 128U)
|
||||
#define I2C1 ((I2C_reg_t *)I2C1_BASE)
|
||||
#define I2C1 ((i2c_reg_t *)I2C1_BASE)
|
||||
|
||||
/* STATUS - I2C Status register */
|
||||
|
||||
|
|
@ -975,13 +986,13 @@ typedef struct
|
|||
|
||||
typedef struct
|
||||
{
|
||||
UDMA_reg_t UDMA_TCDM; /* UDMA general register */
|
||||
udma_reg_t UDMA_TCDM; /* UDMA general register */
|
||||
volatile uint32_t DST_ADDR; /* destination address register */
|
||||
volatile uint32_t SRC_ADDR; /* source address register */
|
||||
} TCDM_reg_t;
|
||||
} tcdm_reg_t;
|
||||
|
||||
#define TCDM_BASE (UDMA_BASE + 7 * 128U)
|
||||
#define TCDM ((TCDM_reg_t *)TCDM_BASE)
|
||||
#define TCDM ((tcdm_reg_t *)TCDM_BASE)
|
||||
|
||||
/* DST_ADDR - TCDM destination address register */
|
||||
|
||||
|
|
@ -999,17 +1010,17 @@ typedef struct
|
|||
|
||||
typedef struct
|
||||
{
|
||||
UDMA_reg_t UDMA_I2S; /* UDMA general register */
|
||||
udma_reg_t UDMA_I2S; /* UDMA general register */
|
||||
volatile uint32_t EXT; /* external clock configuration register */
|
||||
volatile uint32_t CFG_CLKGEN0; /* clock/WS generator 0 configuration register */
|
||||
volatile uint32_t CFG_CLKGEN1; /* clock/WS generator 1 configuration register */
|
||||
volatile uint32_t CHMODE; /* channels mode configuration register */
|
||||
volatile uint32_t FILT_CH0; /* channels 0 filtering configuration register */
|
||||
volatile uint32_t FILT_CH1; /* channels 0 filtering configuration register */
|
||||
} I2S_reg_t;
|
||||
} i2s_reg_t;
|
||||
|
||||
#define I2S_BASE (UDMA_BASE + 8 * 128U)
|
||||
#define I2S ((I2S_reg_t *)I2S_BASE)
|
||||
#define I2S ((i2s_reg_t *)I2S_BASE)
|
||||
|
||||
/* EXT - I2S external clock configuration Register */
|
||||
|
||||
|
|
@ -1103,16 +1114,16 @@ typedef struct
|
|||
|
||||
typedef struct
|
||||
{
|
||||
UDMA_reg_t UDMA_CPI; /* UDMA general register */
|
||||
udma_reg_t UDMA_CPI; /* UDMA general register */
|
||||
volatile uint32_t CFG_GLOB; /* global configuration register */
|
||||
volatile uint32_t CFG_LL; /* lower left comer configuration register */
|
||||
volatile uint32_t CFG_UR; /* upper right comer configuration register */
|
||||
volatile uint32_t CFG_SIZE; /* horizontal resolution configuration register */
|
||||
volatile uint32_t CFG_FILTER; /* RGB coefficients configuration register */
|
||||
} CPI_reg_t;
|
||||
} cpi_reg_t;
|
||||
|
||||
#define CPI_BASE (UDMA_BASE + 9 * 128U)
|
||||
#define CPI ((CPI_reg_t *)CPI_BASE)
|
||||
#define CPI ((cpi_reg_t *)CPI_BASE)
|
||||
|
||||
/* CFG_GLOB - CPI global configuration register */
|
||||
|
||||
|
|
@ -1192,11 +1203,10 @@ typedef struct
|
|||
volatile uint32_t _reserved2[3]; /* reserved */
|
||||
volatile uint32_t CORE_STATUS; /* SOC_CTRL Slepp control register */
|
||||
volatile uint32_t CORE_STATUS_EOC; /* SOC_CTRL Slepp control register */
|
||||
|
||||
} SOC_CTRL_reg_t;
|
||||
} soc_strl_reg_t;
|
||||
|
||||
#define SOC_CTRL_BASE (0x1A104000)
|
||||
#define SOC_CTRL ((SOC_CTRL_reg_t *)SOC_CTRL_BASE)
|
||||
#define SOC_CTRL ((soc_strl_reg_t *)SOC_CTRL_BASE)
|
||||
|
||||
/* CLUSTER_BYPASS - SOC_CTRL information register */
|
||||
|
||||
|
|
@ -1263,17 +1273,20 @@ typedef struct
|
|||
volatile uint32_t RAR_DCDC; /* CTRL control register */
|
||||
volatile uint32_t SLEEP_CTRL; /* CTRL sleep control register */
|
||||
volatile uint32_t FORCE; /* CTRL register */
|
||||
} SOC_CTRL_PMU_reg_t;
|
||||
} soc_ctrl_pmu_reg_t;
|
||||
|
||||
#define PMU_CTRL_BASE (SOC_CTRL_BASE + 0x0100u)
|
||||
#define PMU_CTRL ((SOC_CTRL_PMU_reg_t *)PMU_CTRL_BASE)
|
||||
#define PMU_CTRL ((soc_ctrl_pmu_reg_t *)PMU_CTRL_BASE)
|
||||
|
||||
/* RAR_DCDC - PMU control register */
|
||||
|
||||
#define PMU_CTRL_RAR_DCDC_NV_MASK (0x1FU)
|
||||
#define PMU_CTRL_RAR_DCDC_NV_SHIFT (0U)
|
||||
#define PMU_CTRL_RAR_DCDC_NV(x) (((uint32_t)(x) /* << PMU_CTRL_RAR_DCDC_NV_SHIFT*/) & PMU_CTRL_RAR_DCDC_NV_MASK)
|
||||
#define READ_PMU_CTRL_RAR_DCDC_NV(x) (((uint32_t)(x) & PMU_CTRL_RAR_DCDC_NV_MASK) /*>> PMU_CTRL_RAR_DCDC_NV_SHIFT*/)
|
||||
|
||||
#define PMU_CTRL_RAR_DCDC_NV(x) (((uint32_t)(x) /* << PMU_CTRL_RAR_DCDC_NV_SHIFT */) & PMU_CTRL_RAR_DCDC_NV_MASK)
|
||||
|
||||
#define READ_PMU_CTRL_RAR_DCDC_NV(x) (((uint32_t)(x) & PMU_CTRL_RAR_DCDC_NV_MASK) /* >> PMU_CTRL_RAR_DCDC_NV_SHIFT */)
|
||||
|
||||
#define PMU_CTRL_RAR_DCDC_MV_MASK (0x1F00U)
|
||||
#define PMU_CTRL_RAR_DCDC_MV_SHIFT (8U)
|
||||
#define PMU_CTRL_RAR_DCDC_MV(x) (((uint32_t)(x) << PMU_CTRL_RAR_DCDC_MV_SHIFT) & PMU_CTRL_RAR_DCDC_MV_MASK)
|
||||
|
|
@ -1291,8 +1304,10 @@ typedef struct
|
|||
|
||||
#define PMU_CTRL_SLEEP_CTRL_CFG_MEM_RET_MASK (0xFU)
|
||||
#define PMU_CTRL_SLEEP_CTRL_CFG_MEM_RET_SHIFT (0U)
|
||||
#define PMU_CTRL_SLEEP_CTRL_CFG_MEM_RET(x) (((uint32_t)(x) /* << PMU_CTRL_SLEEP_CTRL_CFG_MEM_RET_SHIFT*/) & PMU_CTRL_SLEEP_CTRL_CFG_MEM_RET_MASK)
|
||||
#define READ_PMU_CTRL_SLEEP_CTRL_CFG_MEM_RET(x) (((uint32_t)(x) & PMU_CTRL_SLEEP_CTRL_CFG_MEM_RET_MASK) /*>> PMU_CTRL_SLEEP_CTRL_CFG_MEM_RET_SHIFT*/)
|
||||
|
||||
#define PMU_CTRL_SLEEP_CTRL_CFG_MEM_RET(x) (((uint32_t)(x) /* << PMU_CTRL_SLEEP_CTRL_CFG_MEM_RET_SHIFT */) & PMU_CTRL_SLEEP_CTRL_CFG_MEM_RET_MASK)
|
||||
|
||||
#define READ_PMU_CTRL_SLEEP_CTRL_CFG_MEM_RET(x) (((uint32_t)(x) & PMU_CTRL_SLEEP_CTRL_CFG_MEM_RET_MASK) /* >> PMU_CTRL_SLEEP_CTRL_CFG_MEM_RET_SHIFT */)
|
||||
|
||||
#define PMU_CTRL_SLEEP_CTRL_CFG_FLL_SOC_RET_MASK (0x10U)
|
||||
#define PMU_CTRL_SLEEP_CTRL_CFG_FLL_SOC_RET_SHIFT (4U)
|
||||
|
|
@ -1366,10 +1381,10 @@ typedef struct
|
|||
volatile uint32_t PAD_SLEEP; /* PORT pad sleep register */
|
||||
volatile uint32_t _reserved0[7]; /* reserved */
|
||||
volatile uint32_t PADCFG[16]; /* PORT pad configuration register 0 */
|
||||
} PORT_reg_t;
|
||||
} port_reg_t;
|
||||
|
||||
#define PORTA_BASE (SOC_CTRL_BASE + 0x0140u)
|
||||
#define PORTA ((PORT_reg_t *)PORTA_BASE)
|
||||
#define PORTA ((port_reg_t *)PORTA_BASE)
|
||||
|
||||
#define GPIO_NUM 32
|
||||
|
||||
|
|
@ -1392,10 +1407,10 @@ typedef struct
|
|||
volatile uint32_t GPIO_ISO; /* GPIO power domains isolation */
|
||||
volatile uint32_t CAM_ISO; /* Cemera power domains isolation */
|
||||
volatile uint32_t LVDS_ISO; /* LVDS power domains isolation */
|
||||
} IO_ISO_reg_t;
|
||||
} io_iso_reg_t;
|
||||
|
||||
#define IO_ISO_BASE (SOC_CTRL_BASE + 0x01C0u)
|
||||
#define IO_ISO ((IO_ISO_reg_t *)IO_ISO_BASE)
|
||||
#define IO_ISO ((io_iso_reg_t *)IO_ISO_BASE)
|
||||
|
||||
#define IO_ISO_GPIO_ISO_MASK (0x1U)
|
||||
#define IO_ISO_GPIO_ISO_SHIFT (0U)
|
||||
|
|
@ -1415,10 +1430,10 @@ typedef struct
|
|||
{
|
||||
volatile uint32_t EVENT_CFG; /* event configuration register */
|
||||
volatile uint32_t CH_EN; /* channel enable register */
|
||||
} PWM_CTRL_reg_t;
|
||||
} pwm_ctrl_reg_t;
|
||||
|
||||
#define PWM_CTRL_BASE (SOC_PERI_BASE + 0x05100u)
|
||||
#define PWM_CTRL ((PWM_CTRL_reg_t *)PWM_CTRL_BASE)
|
||||
#define PWM_CTRL ((pwm_ctrl_reg_t *)PWM_CTRL_BASE)
|
||||
|
||||
/* Set Event. */
|
||||
|
||||
|
|
@ -1448,16 +1463,16 @@ typedef struct
|
|||
volatile uint32_t CH_TH[4]; /* Channles' threshold register */
|
||||
volatile uint32_t CH_LUT[4]; /* Channles' LUT register */
|
||||
volatile uint32_t COUNTER; /* Counter register */
|
||||
} PWM_reg_t;
|
||||
} pwm_reg_t;
|
||||
|
||||
#define PWM0_BASE (SOC_PERI_BASE + 0x05000u)
|
||||
#define PWM0 ((PWM_reg_t *)PWM0_BASE)
|
||||
#define PWM0 ((pwm_reg_t *)PWM0_BASE)
|
||||
#define PWM1_BASE (PWM0_BASE + 0x40u)
|
||||
#define PWM1 ((PWM_reg_t *)PWM1_BASE)
|
||||
#define PWM1 ((pwm_reg_t *)PWM1_BASE)
|
||||
#define PWM2_BASE (PWM1_BASE + 0x40u)
|
||||
#define PWM2 ((PWM_reg_t *)PWM2_BASE)
|
||||
#define PWM2 ((pwm_reg_t *)PWM2_BASE)
|
||||
#define PWM3_BASE (PWM2_BASE + 0x40u)
|
||||
#define PWM3 ((PWM_reg_t *)PWM3_BASE)
|
||||
#define PWM3 ((pwm_reg_t *)PWM3_BASE)
|
||||
|
||||
/* Send command. */
|
||||
|
||||
|
|
@ -1522,10 +1537,10 @@ typedef struct
|
|||
volatile uint32_t ERR_MASK_LSB; /* error mask LSB register */
|
||||
volatile uint32_t TIMER_SEL_HI; /* timer high register */
|
||||
volatile uint32_t TIMER_SEL_LO; /* timer low register */
|
||||
} SOCEU_reg_t;
|
||||
} soceu_reg_t;
|
||||
|
||||
#define SOCEU_BASE (SOC_PERI_BASE + 0x06000u)
|
||||
#define SOCEU ((SOCEU_reg_t *)SOCEU_BASE)
|
||||
#define SOCEU ((soceu_reg_t *)SOCEU_BASE)
|
||||
|
||||
/* The SOC events number */
|
||||
|
||||
|
|
@ -1544,10 +1559,10 @@ typedef struct
|
|||
volatile uint32_t DLC_IOIFR; /* PMU DLC register */
|
||||
volatile uint32_t DLC_IDIFR; /* PMU DLC register */
|
||||
volatile uint32_t DLC_IMCIFR; /* PMU DLC register */
|
||||
} PMU_DLC_reg_t;
|
||||
} pmu_dlc_reg_t;
|
||||
|
||||
#define PMU_DLC_BASE (SOC_PERI_BASE + 0x7000u)
|
||||
#define PMU_DLC ((PMU_DLC_reg_t *)PMU_DLC_BASE)
|
||||
#define PMU_DLC ((pmu_dlc_reg_t *)PMU_DLC_BASE)
|
||||
|
||||
/* PCTRL - PMU DLC PICL control register */
|
||||
|
||||
|
|
@ -1633,7 +1648,9 @@ typedef struct
|
|||
#define PMU_DLC_IMCIFR_ICU_MODE_CHANGED_FLAG_SHIFT (1U)
|
||||
#define PMU_DLC_IMCIFR_ICU_MODE_CHANGED_FLAG(x) (((uint32_t)(x) << PMU_DLC_IMCIFR_ICU_MODE_CHANGED_FLAG_SHIFT) & PMU_DLC_IMCIFR_ICU_MODE_CHANGED_FLAG_MASK)
|
||||
|
||||
/* PCTRL_PADDR The address to write in the DLC_PADDR register is CHIP_SEL_ADDR[4:0] concatenated with REG_ADDR[4:0]. */
|
||||
/* PCTRL_PADDR The address to write in the DLC_PADDR register is
|
||||
* CHIP_SEL_ADDR[4:0] concatenated with REG_ADDR[4:0].
|
||||
*/
|
||||
|
||||
#define PMU_DLC_PICL_REG_ADDR_MASK (0x1FU)
|
||||
#define PMU_DLC_PICL_REG_ADDR_SHIFT (0U)
|
||||
|
|
@ -1689,10 +1706,10 @@ typedef struct
|
|||
volatile uint32_t IRQ_CTRL; /* RTC_APB_IRQ_Control register */
|
||||
volatile uint32_t IRQ_MASK; /* RTC_APB_IRQ_Mask register */
|
||||
volatile uint32_t IRQ_FLAG; /* RTC_APB_IRQ_Flag register */
|
||||
} RTC_APB_reg_t;
|
||||
} rtc_apb_reg_t;
|
||||
|
||||
#define RTC_APB_BASE (SOC_PERI_BASE + 0x08000u)
|
||||
#define RTC_APB ((RTC_APB_reg_t *)RTC_APB_BASE)
|
||||
#define RTC_APB ((rtc_apb_reg_t *)RTC_APB_BASE)
|
||||
|
||||
/* STATUS - RTC_APB STATUS register */
|
||||
|
||||
|
|
@ -1850,10 +1867,10 @@ typedef struct
|
|||
{
|
||||
volatile uint32_t CMD; /* EFUSE_Control register */
|
||||
volatile uint32_t CFG; /* EFUSE_Control register */
|
||||
} EFUSE_CTRL_reg_t;
|
||||
} efuse_ctrl_reg_t;
|
||||
|
||||
#define EFUSE_CTRL_BASE (SOC_PERI_BASE + 0x09000u)
|
||||
#define EFUSE_CTRL ((EFUSE_CTRL_reg_t *)EFUSE_CTRL_BASE)
|
||||
#define EFUSE_CTRL ((efuse_ctrl_reg_t *)EFUSE_CTRL_BASE)
|
||||
|
||||
#define EFUSE_CTRL_CMD_READ 0x1
|
||||
#define EFUSE_CTRL_CMD_WRITE 0x2
|
||||
|
|
@ -1871,10 +1888,10 @@ typedef struct
|
|||
volatile uint32_t WAIT_XTAL_DELTA_MSB; /**< EFUSE_WAIT_XTAL_DELTA_MSB register, offset: 0x06C */
|
||||
volatile uint32_t WAIT_XTAL_MIN; /**< EFUSE_WAIT_XTAL_MIN registers, offset: 0x070 */
|
||||
volatile uint32_t WAIT_XTAL_MAX; /**< EFUSE_WAIT_XTAL_MAX registers, offset: 0x074 */
|
||||
} EFUSE_REGS_reg_t;
|
||||
} efuse_regs_reg_t;
|
||||
|
||||
#define EFUSE_REGS_BASE (SOC_PERI_BASE + 0x09200u)
|
||||
#define EFUSE_REGS ((EFUSE_REGS_reg_t *)EFUSE_REGS_BASE)
|
||||
#define EFUSE_REGS ((efuse_regs_reg_t *)EFUSE_REGS_BASE)
|
||||
|
||||
/* INFO - EFUSE information register */
|
||||
|
||||
|
|
@ -1899,10 +1916,10 @@ typedef struct
|
|||
typedef struct
|
||||
{
|
||||
volatile uint32_t PUTC[16]; /* FC_STDOUT INFO register, offset: 0x000 */
|
||||
} FC_STDOUT_reg_t;
|
||||
} fc_stdout_reg_t;
|
||||
|
||||
#define FC_STDOUT_BASE (SOC_PERI_BASE + 0x10000u + (32 << 7))
|
||||
#define FC_STDOUT ((FC_STDOUT_reg_t *)FC_STDOUT_BASE)
|
||||
#define FC_STDOUT ((fc_stdout_reg_t *)FC_STDOUT_BASE)
|
||||
|
||||
#ifdef FEATURE_CLUSTER
|
||||
/* CLUSTER_STDOUT - Registers Layout Typedef */
|
||||
|
|
@ -1910,10 +1927,10 @@ typedef struct
|
|||
typedef struct
|
||||
{
|
||||
volatile uint32_t PUTC[16]; /* CLUSTER_STDOUT INFO register, offset: 0x000 */
|
||||
} CLUSTER_STDOUT_reg_t;
|
||||
} cluster_stdout_reg_t;
|
||||
|
||||
#define CLUSTER_STDOUT_BASE (SOC_PERI_BASE + 0x10000u)
|
||||
#define CLUSTER_STDOUT ((CLUSTER_STDOUT_reg_t *)CLUSTER_STDOUT_BASE)
|
||||
#define CLUSTER_STDOUT ((cluster_stdout_reg_t *)CLUSTER_STDOUT_BASE)
|
||||
|
||||
/* HWCE - Registers Layout Typedef */
|
||||
|
||||
|
|
@ -1947,10 +1964,10 @@ typedef struct
|
|||
volatile uint32_t HWCE_W_REG; /* W register */
|
||||
volatile uint32_t HWCE_JOB_CONFIG0_REG; /* Job_Config0 register */
|
||||
volatile uint32_t HWCE_JOB_CONFIG1_REG; /* Job_Config1 register */
|
||||
} HWCE_reg_t;
|
||||
} hwce_reg_t;
|
||||
|
||||
#define HWCE_BASE (CORE_PERI_BASE + 0x00001000)
|
||||
#define HWCE ((HWCE_reg_t *) HWCE_BASE)
|
||||
#define HWCE ((hwce_reg_t *) HWCE_BASE)
|
||||
|
||||
/* Internal registers */
|
||||
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/************************************************************************************
|
||||
/****************************************************************************
|
||||
* arch/risc-v/src/gap8/gap8_fll.c
|
||||
* GAP8 FLL clock generator
|
||||
*
|
||||
|
|
@ -32,30 +32,30 @@
|
|||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
****************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* FC can run up to 250MHz@1.2V, and 150MHz@1.0V. While the default voltage of PMU
|
||||
* is 1.2V, it's okay to boost up without considering PMU.
|
||||
************************************************************************************/
|
||||
/****************************************************************************
|
||||
* FC can run up to 250MHz@1.2V, and 150MHz@1.0V. While the default voltage
|
||||
* of PMU is 1.2V, it's okay to boost up without considering PMU.
|
||||
****************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
****************************************************************************/
|
||||
|
||||
#include "gap8_fll.h"
|
||||
|
||||
/************************************************************************************
|
||||
/****************************************************************************
|
||||
* Pre-Processor Declarations
|
||||
************************************************************************************/
|
||||
****************************************************************************/
|
||||
|
||||
/* Log2(FLL_REF_CLK=32768) */
|
||||
|
||||
#define LOG2_REFCLK 15
|
||||
|
||||
/************************************************************************************
|
||||
* Public Function
|
||||
************************************************************************************/
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: gap8_setfreq
|
||||
|
|
@ -103,7 +103,7 @@ void gap8_setfreq(uint32_t frequency)
|
|||
}
|
||||
while (mult_factor_diff > 0x10);
|
||||
|
||||
FLL_CTRL->SOC_CONF2 = FLL_CTRL_CONF2_LOOPGAIN(0xB) |
|
||||
FLL_CTRL->SOC_CONF2 = FLL_CTRL_CONF2_LOOPGAIN(0xb) |
|
||||
FLL_CTRL_CONF2_DEASSERT_CYCLES(0x10) |
|
||||
FLL_CTRL_CONF2_ASSERT_CYCLES(0x10) |
|
||||
FLL_CTRL_CONF2_LOCK_TOLERANCE(0x100) |
|
||||
|
|
@ -124,5 +124,5 @@ uint32_t gap8_getfreq(void)
|
|||
{
|
||||
/* FreqOut = Fref * mult/2^(div-1), where div = 1 */
|
||||
|
||||
return FLL_REF_CLK * (FLL_CTRL->SOC_FLL_STATUS & 0xFFFF);
|
||||
return FLL_REF_CLK * (FLL_CTRL->SOC_FLL_STATUS & 0xffff);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/************************************************************************************
|
||||
/****************************************************************************
|
||||
* arch/risc-v/src/gap8/gap8_fll.h
|
||||
* GAP8 FLL clock generator
|
||||
*
|
||||
|
|
@ -32,25 +32,25 @@
|
|||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
****************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* FC can run up to 250MHz@1.2V, and 150MHz@1.0V. While the default voltage of PMU
|
||||
* is 1.2V, it's okay to boost up without considering PMU.
|
||||
************************************************************************************/
|
||||
/****************************************************************************
|
||||
* FC can run up to 250MHz@1.2V, and 150MHz@1.0V. While the default voltage
|
||||
* of PMU is 1.2V, it's okay to boost up without considering PMU.
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_RISC_V_SRC_GAP8_FLL_H
|
||||
#define __ARCH_RISC_V_SRC_GAP8_FLL_H
|
||||
|
||||
/************************************************************************************
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
****************************************************************************/
|
||||
|
||||
#include "gap8.h"
|
||||
|
||||
/************************************************************************************
|
||||
/****************************************************************************
|
||||
* Public Function Prototypes
|
||||
************************************************************************************/
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: gap8_setfreq
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/************************************************************************************
|
||||
/****************************************************************************
|
||||
* arch/risc-v/src/gap8/gap8_gpio.c
|
||||
* GAP8 FLL clock generator
|
||||
*
|
||||
|
|
@ -32,16 +32,24 @@
|
|||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
****************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
/****************************************************************************
|
||||
* GAP8 has only 1 port. Each pin could be configured to GPIO or alternative
|
||||
* functions.
|
||||
************************************************************************************/
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include "gap8_gpio.h"
|
||||
|
||||
/************************************************************************************
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: gap8_configpin
|
||||
*
|
||||
* Description:
|
||||
|
|
@ -57,7 +65,7 @@
|
|||
* OK on success
|
||||
* ERROR on invalid pin.
|
||||
*
|
||||
************************************************************************************/
|
||||
****************************************************************************/
|
||||
|
||||
int gap8_configpin(uint32_t cfgset)
|
||||
{
|
||||
|
|
@ -120,7 +128,7 @@ int gap8_configpin(uint32_t cfgset)
|
|||
return OK;
|
||||
}
|
||||
|
||||
/************************************************************************************
|
||||
/****************************************************************************
|
||||
* Name: gap8_gpiowrite
|
||||
*
|
||||
* Description:
|
||||
|
|
@ -132,7 +140,7 @@ int gap8_configpin(uint32_t cfgset)
|
|||
* | --- | GPIOn | --- |
|
||||
* | --- | 5-bit | --- |
|
||||
*
|
||||
************************************************************************************/
|
||||
****************************************************************************/
|
||||
|
||||
void gap8_gpiowrite(uint32_t pinset, bool value)
|
||||
{
|
||||
|
|
@ -147,7 +155,7 @@ void gap8_gpiowrite(uint32_t pinset, bool value)
|
|||
}
|
||||
}
|
||||
|
||||
/************************************************************************************
|
||||
/****************************************************************************
|
||||
* Name: gap8_gpioread
|
||||
*
|
||||
* Description:
|
||||
|
|
@ -159,7 +167,7 @@ void gap8_gpiowrite(uint32_t pinset, bool value)
|
|||
* | --- | GPIOn | --- |
|
||||
* | --- | 5-bit | --- |
|
||||
*
|
||||
************************************************************************************/
|
||||
****************************************************************************/
|
||||
|
||||
bool gap8_gpioread(uint32_t pinset)
|
||||
{
|
||||
|
|
@ -167,7 +175,7 @@ bool gap8_gpioread(uint32_t pinset)
|
|||
return (GPIOA->IN >> gpio_n) & 0x1;
|
||||
}
|
||||
|
||||
/************************************************************************************
|
||||
/****************************************************************************
|
||||
* Name: gap8_gpioirqset
|
||||
*
|
||||
* Description:
|
||||
|
|
@ -179,13 +187,14 @@ bool gap8_gpioread(uint32_t pinset)
|
|||
* | --- | int-typ | --- | GPIOn | --- |
|
||||
* | --- | 2-bit | --- | 5-bit | --- |
|
||||
*
|
||||
************************************************************************************/
|
||||
****************************************************************************/
|
||||
|
||||
void gap8_gpioirqset(uint32_t pinset, bool enable)
|
||||
{
|
||||
uint32_t gpio_n = (pinset >> 10) & 0x1f;
|
||||
uint32_t int_type = (pinset >> 18) * 0x3;
|
||||
uint32_t tmp, shitfcnt;
|
||||
uint32_t tmp;
|
||||
uint32_t shitfcnt;
|
||||
|
||||
if (enable)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/************************************************************************************
|
||||
/****************************************************************************
|
||||
* arch/risc-v/src/gap8/gap8_interrupt.c
|
||||
* GAP8 event system
|
||||
*
|
||||
|
|
@ -32,18 +32,18 @@
|
|||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
****************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* GAP8 features a FC controller and a 8-core cluster. IRQ from peripherals have
|
||||
* unique ID, which are dispatched to the FC or cluster by the SOC event unit, and
|
||||
* then by the FC event unit or cluster event unit, and finally to FC or cluster.
|
||||
* Peripherals share the same IRQ entry.
|
||||
************************************************************************************/
|
||||
/****************************************************************************
|
||||
* GAP8 features a FC controller and a 8-core cluster. IRQ from peripherals
|
||||
* have unique ID, which are dispatched to the FC or cluster by the SOC
|
||||
* event unit, and then by the FC event unit or cluster event unit, and
|
||||
* finally to FC or cluster. Peripherals share the same IRQ entry.
|
||||
****************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/irq.h>
|
||||
#include <nuttx/arch.h>
|
||||
|
|
@ -58,9 +58,9 @@
|
|||
|
||||
volatile uint32_t *g_current_regs;
|
||||
|
||||
/************************************************************************************
|
||||
* Public Function
|
||||
************************************************************************************/
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/* Function exported to the Nuttx kernel */
|
||||
|
||||
|
|
@ -100,8 +100,8 @@ void up_irqinitialize(void)
|
|||
{
|
||||
/* Deactivate all the soc events */
|
||||
|
||||
SOC_EU->FC_MASK_MSB = 0xFFFFFFFF;
|
||||
SOC_EU->FC_MASK_LSB = 0xFFFFFFFF;
|
||||
SOC_EU->FC_MASK_MSB = 0xffffffff;
|
||||
SOC_EU->FC_MASK_LSB = 0xffffffff;
|
||||
|
||||
/* enable soc peripheral interrupt */
|
||||
|
||||
|
|
|
|||
|
|
@ -34,15 +34,15 @@
|
|||
*
|
||||
****************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* FC core has a 64-bit basic timer, able to split into 2 32-bit timers, with
|
||||
* identicle memory map and 2 IRQ channels, for both FC core and cluster. We would
|
||||
* use it as system timer.
|
||||
************************************************************************************/
|
||||
/****************************************************************************
|
||||
* FC core has a 64-bit basic timer, able to split into 2 32-bit timers,
|
||||
* with identicle memory map and 2 IRQ channels, for both FC core and
|
||||
* cluster. We would use it as system timer.
|
||||
****************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include <nuttx/arch.h>
|
||||
|
|
@ -56,7 +56,7 @@
|
|||
|
||||
struct gap8_tim_instance
|
||||
{
|
||||
BASIC_TIM_reg_t *reg;
|
||||
basic_tim_reg_t *reg;
|
||||
uint32_t core_clock;
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/************************************************************************************
|
||||
/****************************************************************************
|
||||
* arch/risc-v/src/gap8/gap8_tim.h
|
||||
* PIN driver for GAP8
|
||||
*
|
||||
|
|
@ -32,26 +32,26 @@
|
|||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
****************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* GAP8 features a 64-bit basic timer, able to split into 2 32-bit timers, with
|
||||
* identicle memory map and 2 IRQ channels, for both FC core and cluster. We would
|
||||
* use it as system timer.
|
||||
************************************************************************************/
|
||||
/****************************************************************************
|
||||
* GAP8 features a 64-bit basic timer, able to split into 2 32-bit timers,
|
||||
* with identicle memory map and 2 IRQ channels, for both FC core and
|
||||
* cluster. We would use it as system timer.
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_RISC_V_SRC_GAP8_TIM_H
|
||||
#define __ARCH_RISC_V_SRC_GAP8_TIM_H
|
||||
|
||||
/************************************************************************************
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
****************************************************************************/
|
||||
|
||||
#include "gap8.h"
|
||||
|
||||
/************************************************************************************
|
||||
/****************************************************************************
|
||||
* Public Function Prototypes
|
||||
************************************************************************************/
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: gap8_timer_initialize
|
||||
|
|
|
|||
|
|
@ -34,7 +34,7 @@
|
|||
*
|
||||
****************************************************************************/
|
||||
|
||||
/*****************************************************************************
|
||||
/****************************************************************************
|
||||
* This UART IP has no flow control. So ioctl is limited.
|
||||
* Note that here we don't use the uDMA to send multiple bytes, because
|
||||
* Nuttx serial drivers don't have abstraction for puts().
|
||||
|
|
@ -157,7 +157,7 @@ static struct gap8_uart_t gap8_uarts[GAP8_NR_UART] =
|
|||
{
|
||||
.udma =
|
||||
{
|
||||
.regs = (UDMA_reg_t *)UART,
|
||||
.regs = (udma_reg_t *)UART,
|
||||
.id = GAP8_UDMA_ID_UART,
|
||||
.on_tx = uart_tx_isr,
|
||||
.tx_arg = &g_uart0port,
|
||||
|
|
@ -197,7 +197,7 @@ static uart_dev_t g_uart0port =
|
|||
{
|
||||
.size = CONFIG_UART_TXBUFSIZE,
|
||||
.buffer = g_uart1txbuffer,
|
||||
},
|
||||
},
|
||||
.ops = &g_uart_ops,
|
||||
.priv = &gap8_uarts[0],
|
||||
};
|
||||
|
|
@ -246,7 +246,7 @@ static void uart_rx_isr(void *arg)
|
|||
static int up_setup(struct uart_dev_s *dev)
|
||||
{
|
||||
struct gap8_uart_t *the_uart = (struct gap8_uart_t *)dev->priv;
|
||||
UART_reg_t *uartreg = (UART_reg_t *)the_uart->udma.regs;
|
||||
uart_reg_t *uartreg = (uart_reg_t *)the_uart->udma.regs;
|
||||
uint32_t cfgreg = 0;
|
||||
|
||||
if (the_uart->is_initialized == 0)
|
||||
|
|
@ -303,14 +303,15 @@ static void up_shutdown(struct uart_dev_s *dev)
|
|||
* Name: up_attach
|
||||
*
|
||||
* Description:
|
||||
* Configure the UART to operation in interrupt driven mode. This method is
|
||||
* Configure the UART to operation in interrupt driven mode. This method is
|
||||
* called when the serial port is opened. Normally, this is just after the
|
||||
* the setup() method is called, however, the serial console may operate in
|
||||
* a non-interrupt driven mode during the boot phase.
|
||||
*
|
||||
* RX and TX interrupts are not enabled by the attach method (unless the
|
||||
* hardware supports multiple levels of interrupt enabling). The RX and TX
|
||||
* interrupts are not enabled until the txint() and rxint() methods are called.
|
||||
* interrupts are not enabled until the txint() and rxint() methods are
|
||||
* called.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
|
|
@ -331,7 +332,7 @@ static int up_attach(struct uart_dev_s *dev)
|
|||
*
|
||||
* Description:
|
||||
* Detach UART interrupts. This method is called when the serial port is
|
||||
* closed normally just before the shutdown method is called. The exception
|
||||
* closed normally just before the shutdown method is called. The exception
|
||||
* is the serial console which is never shutdown.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
|
|
|||
|
|
@ -75,7 +75,10 @@
|
|||
* The peripheral driver instantiate it and register through _init()
|
||||
*/
|
||||
|
||||
static struct gap8_udma_peripheral *_peripherals[GAP8_UDMA_NR_CHANNELS] = { 0 };
|
||||
static struct gap8_udma_peripheral *_peripherals[GAP8_UDMA_NR_CHANNELS] =
|
||||
{
|
||||
0
|
||||
};
|
||||
|
||||
/****************************************************************************
|
||||
* Private Functions
|
||||
|
|
@ -294,7 +297,7 @@ int gap8_udma_rx_poll(struct gap8_udma_peripheral *instance)
|
|||
* Description:
|
||||
* uDMA ISR
|
||||
*
|
||||
***************************************************************************/
|
||||
****************************************************************************/
|
||||
|
||||
int gap8_udma_doirq(int irq, void *context, FAR void *arg)
|
||||
{
|
||||
|
|
@ -349,7 +352,7 @@ int gap8_udma_doirq(int irq, void *context, FAR void *arg)
|
|||
{
|
||||
/* Rx channel */
|
||||
|
||||
if (the_peripheral->rx.block_count > 1)
|
||||
if (the_peripheral->rx.block_count > 1)
|
||||
{
|
||||
the_peripheral->rx.block_count--;
|
||||
the_peripheral->rx.buff += the_peripheral->rx.block_size;
|
||||
|
|
|
|||
|
|
@ -102,7 +102,7 @@ struct gap8_udma_peripheral
|
|||
{
|
||||
/* Public */
|
||||
|
||||
UDMA_reg_t *regs; /* Hardware config regs */
|
||||
udma_reg_t *regs; /* Hardware config regs */
|
||||
uint32_t id; /* GAP8_UDMA_ID_x */
|
||||
void (*on_tx)(void *arg); /* tx callback */
|
||||
void (*on_rx)(void *arg); /* rx callback */
|
||||
|
|
|
|||
|
|
@ -45,7 +45,7 @@
|
|||
#include "chip.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
* Public Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/************************************************************************************
|
||||
/****************************************************************************
|
||||
* arch/risc-v/src/nr5m100/hardware/nr5_timer.h
|
||||
*
|
||||
* Copyright (C) 2016 Ken Pettit. All rights reserved.
|
||||
|
|
@ -28,11 +28,15 @@
|
|||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef ARCH_RISCV_SRC_NR5M100_CHIP_NR5M1XX_TIMERA_H
|
||||
#define ARCH_RISCV_SRC_NR5M100_CHIP_NR5M1XX_TIMERA_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include "nr5m1xx_memorymap.h"
|
||||
|
||||
/* The timers used in the NR5M100 are functionally equivalent to
|
||||
|
|
@ -122,7 +126,7 @@
|
|||
#define NR5_TIMER5_TAIV_OFFSET (NR5_TIMER5_BASE+NR5_TIMERA_TAIV_OFFSET)
|
||||
#endif
|
||||
|
||||
/* Register Bitfield Definitions ********************************************************/
|
||||
/* Register Bitfield Definitions ********************************************/
|
||||
|
||||
/* Control register TACTL Bit definitions */
|
||||
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/************************************************************************************
|
||||
/****************************************************************************
|
||||
* arch/risc-v/src/nr5m100/nr5_arch.c
|
||||
*
|
||||
* Copyright (C) 2016 Ken Pettit. All rights reserved.
|
||||
|
|
@ -28,15 +28,23 @@
|
|||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <string.h>
|
||||
#include <nuttx/arch.h>
|
||||
#include "nr5.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
void up_puts(const char *p)
|
||||
{
|
||||
while (*p != 0)
|
||||
up_lowputc(*(p++));
|
||||
up_lowputc('\n');
|
||||
while (*p != 0)
|
||||
up_lowputc(*(p++));
|
||||
up_lowputc('\n');
|
||||
}
|
||||
|
|
|
|||
|
|
@ -53,6 +53,7 @@
|
|||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* UARTs ****************************************************************************/
|
||||
|
||||
/* Are any UARTs enabled? */
|
||||
|
|
@ -91,7 +92,7 @@
|
|||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
* Public Function Prototypes
|
||||
************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_RISCV_SRC_NR5M100_NR5_CONFIG_H */
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/************************************************************************************
|
||||
/****************************************************************************
|
||||
* arch/risc-v/src/nr5m100/nr5_custom_ops.h
|
||||
*
|
||||
* Copyright (C) 2016 Ken Pettit. All rights reserved.
|
||||
|
|
@ -28,7 +28,7 @@
|
|||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
|
|
@ -44,17 +44,17 @@
|
|||
****************************************************************************/
|
||||
|
||||
.macro getq rd qs
|
||||
custom0 \rd,\qs,0,0
|
||||
custom0 \rd, \qs, 0, 0
|
||||
.endm
|
||||
|
||||
.macro setq qd rs
|
||||
custom0 \qd,\rs,0,1
|
||||
custom0 \qd, \rs, 0, 1
|
||||
.endm
|
||||
|
||||
.macro lsbenc rd rs
|
||||
custom0 \rd,\rs,0,2
|
||||
custom0 \rd, \rs, 0, 2
|
||||
.endm
|
||||
|
||||
.macro timer rd rs
|
||||
custom0 \rd,\rs,0,5
|
||||
custom0 \rd, \rs, 0, 5
|
||||
.endm
|
||||
|
|
|
|||
|
|
@ -70,5 +70,5 @@ void __nr5_init(void)
|
|||
|
||||
/* Shouldn't get here */
|
||||
|
||||
for (;;);
|
||||
for (; ; );
|
||||
}
|
||||
|
|
|
|||
|
|
@ -76,27 +76,27 @@ volatile uint32_t *g_current_regs;
|
|||
|
||||
void epic_dump(void)
|
||||
{
|
||||
uint32_t reg;
|
||||
char str[40];
|
||||
uint32_t reg;
|
||||
char str[40];
|
||||
|
||||
__asm__ volatile("csrr %0, 0x7e0" : "=r"(reg));
|
||||
sprintf(str, "IRQMASK = 0x%08X\r", (int) reg);
|
||||
up_puts(str);
|
||||
__asm__ volatile("csrr %0, 0x7e4" : "=r"(reg));
|
||||
sprintf(str, "IRQSTACK = 0x%08X\r", (int) reg);
|
||||
up_puts(str);
|
||||
__asm__ volatile("csrr %0, 0x7e1" : "=r"(reg));
|
||||
sprintf(str, "PRI1 = 0x%08X\r", (int) reg);
|
||||
up_puts(str);
|
||||
__asm__ volatile("csrr %0, 0x7e2" : "=r"(reg));
|
||||
sprintf(str, "PRI2 = 0x%08X\r", (int) reg);
|
||||
up_puts(str);
|
||||
__asm__ volatile("csrr %0, 0x7e3" : "=r"(reg));
|
||||
sprintf(str, "PRI3 = 0x%08X\r", (int) reg);
|
||||
up_puts(str);
|
||||
__asm__ volatile("csrr %0, 0x7e5" : "=r"(reg));
|
||||
sprintf(str, "SYSTICK = 0x%08X\r", (int) reg);
|
||||
up_puts(str);
|
||||
__asm__ volatile("csrr %0, 0x7e0" : "=r"(reg));
|
||||
sprintf(str, "IRQMASK = 0x%08X\r", (int) reg);
|
||||
up_puts(str);
|
||||
__asm__ volatile("csrr %0, 0x7e4" : "=r"(reg));
|
||||
sprintf(str, "IRQSTACK = 0x%08X\r", (int) reg);
|
||||
up_puts(str);
|
||||
__asm__ volatile("csrr %0, 0x7e1" : "=r"(reg));
|
||||
sprintf(str, "PRI1 = 0x%08X\r", (int) reg);
|
||||
up_puts(str);
|
||||
__asm__ volatile("csrr %0, 0x7e2" : "=r"(reg));
|
||||
sprintf(str, "PRI2 = 0x%08X\r", (int) reg);
|
||||
up_puts(str);
|
||||
__asm__ volatile("csrr %0, 0x7e3" : "=r"(reg));
|
||||
sprintf(str, "PRI3 = 0x%08X\r", (int) reg);
|
||||
up_puts(str);
|
||||
__asm__ volatile("csrr %0, 0x7e5" : "=r"(reg));
|
||||
sprintf(str, "SYSTICK = 0x%08X\r", (int) reg);
|
||||
up_puts(str);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
|
|
@ -151,11 +151,11 @@ void up_irqinitialize(void)
|
|||
/* Colorize the interrupt stack for debug purposes */
|
||||
|
||||
#if defined(CONFIG_STACK_COLORATION) && CONFIG_ARCH_INTERRUPTSTACK > 3
|
||||
{
|
||||
size_t intstack_size = (CONFIG_ARCH_INTERRUPTSTACK & ~3);
|
||||
up_stack_color((FAR void *)((uintptr_t)&g_intstackbase - intstack_size),
|
||||
intstack_size);
|
||||
}
|
||||
{
|
||||
size_t intstack_size = (CONFIG_ARCH_INTERRUPTSTACK & ~3);
|
||||
up_stack_color((FAR void *)((uintptr_t)&g_intstackbase -
|
||||
intstack_size), intstack_size);
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Set the location of the vector table */
|
||||
|
|
@ -168,7 +168,7 @@ void up_irqinitialize(void)
|
|||
csrw %1, 0(zero) \
|
||||
csrw %2, 0(zero) " ::
|
||||
"i"(NR5_EPIC_PRI1_REG), "i"(NR5_EPIC_PRI2_REG),
|
||||
"i"(NR5_EPIC_PRI3_REG) );
|
||||
"i"(NR5_EPIC_PRI3_REG));
|
||||
#endif
|
||||
|
||||
/* Initialize the IRQ stack to Pri level 5 with interrupts disabled */
|
||||
|
|
|
|||
|
|
@ -53,7 +53,8 @@
|
|||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
#define EXTERN extern "C"
|
||||
extern "C" {
|
||||
extern "C"
|
||||
{
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/************************************************************************************
|
||||
/****************************************************************************
|
||||
* arch/risc-v/src/nr5m100/nr5_memorymap.h
|
||||
*
|
||||
* Copyright (C) 2016 Ken Pettit. All rights reserved.
|
||||
|
|
@ -28,12 +28,16 @@
|
|||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef _ARCH_RISCV_SRC_NR5M100_NR5_MEMORYMAP_H
|
||||
#define _ARCH_RISCV_SRC_NR5M100_NR5_MEMORYMAP_H
|
||||
|
||||
//#include <stdint.h>
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
/* #include <stdint.h> */
|
||||
|
||||
#ifdef CONFIG_NR5_NR5MXXX
|
||||
#include "hardware/nr5m1xx_memorymap.h"
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/************************************************************************************
|
||||
/****************************************************************************
|
||||
* arch/risc-v/src/nr5m100/nr5_timer.h
|
||||
*
|
||||
* Copyright (C) 2011-2012 Gregory Nutt. All rights reserved.
|
||||
|
|
@ -33,24 +33,25 @@
|
|||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_RISCV_SRC_NR5M100_NR5_TIMER_H
|
||||
#define __ARCH_RISCV_SRC_NR5M100_NR5_TIMER_H
|
||||
|
||||
/************************************************************************************
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "chip.h"
|
||||
#include "hardware/nr5m1xx_timer.h"
|
||||
|
||||
/************************************************************************************
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
/* Helpers **************************************************************************/
|
||||
****************************************************************************/
|
||||
|
||||
/* Helpers ******************************************************************/
|
||||
|
||||
#define NR5_TIMER_SETMODE(d,mode) ((d)->ops->setmode(d,mode))
|
||||
#define NR5_TIMER_SETCLOCK(d,freq) ((d)->ops->setclock(d,freq))
|
||||
|
|
@ -61,9 +62,9 @@
|
|||
#define NR5_TIMER_DISABLEINT(d,s) ((d)->ops->disableint(d,s))
|
||||
#define NR5_TIMER_ACKINT(d,s) ((d)->ops->ackint(d,s))
|
||||
|
||||
/************************************************************************************
|
||||
/****************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
|
|
@ -95,7 +96,6 @@ typedef enum
|
|||
NR5_TIM_MODE_CK_MED = 0x0010,
|
||||
NR5_TIM_MODE_CK_SYS = 0x0020,
|
||||
NR5_TIM_MODE_CK_EXT = 0x0030,
|
||||
|
||||
} nr5_timer_mode_t;
|
||||
|
||||
/* Timer Operations */
|
||||
|
|
@ -112,7 +112,8 @@ struct nr5_timer_ops_s
|
|||
|
||||
/* Timer Interrupt Operations */
|
||||
|
||||
int (*setisr)(FAR struct nr5_timer_dev_s *dev, xcpt_t handler, void *arg, int source);
|
||||
int (*setisr)(FAR struct nr5_timer_dev_s *dev, xcpt_t handler, void *arg,
|
||||
int source);
|
||||
void (*enableint)(FAR struct nr5_timer_dev_s *dev, int source);
|
||||
void (*disableint)(FAR struct nr5_timer_dev_s *dev, int source);
|
||||
void (*ackint)(FAR struct nr5_timer_dev_s *dev, int source);
|
||||
|
|
@ -125,9 +126,9 @@ struct nr5_timer_dev_s
|
|||
struct nr5_timer_ops_s *ops;
|
||||
};
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
/****************************************************************************
|
||||
* Public Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
/* Power-up timer and get its structure */
|
||||
|
||||
|
|
@ -145,7 +146,8 @@ int nr5_timer_deinit(FAR struct nr5_timer_dev_s *dev);
|
|||
* register the timer drivers at 'devpath'
|
||||
*
|
||||
* Input Parameters:
|
||||
* devpath - The full path to the timer device. This should be of the form /dev/timer0
|
||||
* devpath - The full path to the timer device. This should be of the form
|
||||
* /dev/timer0
|
||||
* timer - the timer number.
|
||||
*
|
||||
* Returned Value:
|
||||
|
|
|
|||
|
|
@ -62,13 +62,13 @@ struct nr5_uart_buffer_s
|
|||
|
||||
struct nr5_uart_regs_s
|
||||
{
|
||||
uint32_t* pbaud; /* Data status port */
|
||||
uint32_t* pstat; /* Data status port */
|
||||
uint8_t* ptx; /* Data TX port */
|
||||
uint8_t* prx; /* Data RX port */
|
||||
uint32_t* pintctrl; /* Interrupt enable control */
|
||||
int rxirq; /* IRQ number */
|
||||
int txirq; /* IRQ number */
|
||||
uint32_t *pbaud; /* Data status port */
|
||||
uint32_t *pstat; /* Data status port */
|
||||
uint8_t *ptx; /* Data TX port */
|
||||
uint8_t *prx; /* Data RX port */
|
||||
uint32_t *pintctrl; /* Interrupt enable control */
|
||||
int rxirq; /* IRQ number */
|
||||
int txirq; /* IRQ number */
|
||||
};
|
||||
|
||||
struct nr5_uart_s
|
||||
|
|
@ -183,8 +183,9 @@ void nr5_uart_init(int uart)
|
|||
{
|
||||
/* Attach the ISR and enable the IRQ with the EPIC */
|
||||
|
||||
//irq_attach(dev->regs->rxirq, &nr5_uart_rx_isr, NULL);
|
||||
//up_enable_irq(dev->regs->rxirq);
|
||||
/* irq_attach(dev->regs->rxirq, &nr5_uart_rx_isr, NULL); */
|
||||
|
||||
/* up_enable_irq(dev->regs->rxirq); */
|
||||
|
||||
/* Set the baud rate */
|
||||
|
||||
|
|
@ -195,7 +196,7 @@ void nr5_uart_init(int uart)
|
|||
|
||||
/* Now enable the RX IRQ in the UART peripheral */
|
||||
|
||||
//*dev->regs->pintctrl = NR5_UART_CTRL_ENABLE_RX_IRQ;
|
||||
/* *dev->regs->pintctrl = NR5_UART_CTRL_ENABLE_RX_IRQ; */
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -208,11 +209,11 @@ uint8_t nr5_uart_get_rx()
|
|||
up_disableints();
|
||||
if (g_nr5_uart1.rxbuf->head != g_nr5_uart1.rxbuf->tail)
|
||||
{
|
||||
struct nr5_uart_buffer_s *pBuf = g_nr5_uart1.rxbuf;
|
||||
struct nr5_uart_buffer_s *pbuf = g_nr5_uart1.rxbuf;
|
||||
|
||||
rxdata = pBuf->buffer[pBuf->tail++];
|
||||
if (pBuf->tail == pBuf->size)
|
||||
pBuf->tail = 0;
|
||||
rxdata = pbuf->buffer[pbuf->tail++];
|
||||
if (pbuf->tail == pbuf->size)
|
||||
pbuf->tail = 0;
|
||||
}
|
||||
|
||||
up_enableints();
|
||||
|
|
@ -223,11 +224,11 @@ uint8_t nr5_uart_get_rx()
|
|||
|
||||
int nr5_uart_test_rx_avail()
|
||||
{
|
||||
struct nr5_uart_buffer_s *pBuf = g_nr5_uart1.rxbuf;
|
||||
struct nr5_uart_buffer_s *pbuf = g_nr5_uart1.rxbuf;
|
||||
int avail;
|
||||
|
||||
up_disableints();
|
||||
avail= !(pBuf->head == pBuf->tail);
|
||||
avail = !(pbuf->head == pbuf->tail);
|
||||
up_enableints();
|
||||
|
||||
/* If no RX data available then halt the processor until an interrupt */
|
||||
|
|
@ -244,19 +245,19 @@ int nr5_uart_test_rx_avail()
|
|||
|
||||
int nr5_uart_test_tx_empty()
|
||||
{
|
||||
return *g_nr5_uart1.regs->pstat & NR5_UART_STATUS_TX_EMPTY;
|
||||
return *g_nr5_uart1.regs->pstat & NR5_UART_STATUS_TX_EMPTY;
|
||||
}
|
||||
|
||||
/* Routine to send TX byte to console UART. */
|
||||
|
||||
void nr5_uart_put_tx(uint8_t ch)
|
||||
{
|
||||
/* Wait for TX to be empty */
|
||||
/* Wait for TX to be empty */
|
||||
|
||||
while (!(*g_nr5_uart1.regs->pstat & NR5_UART_STATUS_TX_EMPTY))
|
||||
;
|
||||
while (!(*g_nr5_uart1.regs->pstat & NR5_UART_STATUS_TX_EMPTY))
|
||||
;
|
||||
|
||||
/* Write to TX */
|
||||
/* Write to TX */
|
||||
|
||||
*g_nr5_uart1.regs->ptx = ch;
|
||||
*g_nr5_uart1.regs->ptx = ch;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/************************************************************************************
|
||||
/****************************************************************************
|
||||
* arch/riscv/src/nr5/nr5_uart.h
|
||||
*
|
||||
* Copyright (C) 2016 Ken Pettit. All rights reserved.
|
||||
|
|
@ -28,11 +28,15 @@
|
|||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef _ARCH_RISCV_SRC_NR5_NR5_UART_H
|
||||
#define _ARCH_RISCV_SRC_NR5_NR5_UART_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef CONFIG_NR5_NR5M1XX
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue