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drivers/clk: use uintptr_t for register addresses

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Change the 'reg' field type from uint32_t to uintptr_t in all clock
provider structs (clk_gate_s, clk_divider_s, clk_phase_s,
clk_fractional_divider_s, clk_multiplier_s, clk_mux_s) and their
corresponding clk_register_*() function prototypes.

Also update clk_write() and clk_read() inline functions to take
uintptr_t parameter and remove the now-redundant (uintptr_t) cast.

On 32-bit embedded platforms uintptr_t equals uint32_t so there is
no functional change. On 64-bit targets (e.g. sim) this fixes
-Wint-to-pointer-cast warnings that GCC15 promotes to errors.

Fixes: #16896
Signed-off-by: hanzhijian <hanzhijian@zepp.com>
This commit is contained in:
hanzhijian 2026-06-18 01:15:48 +08:00 • committed by Xiang Xiao
parent e17d776357
commit a8f55fbfd8
2 changed files with 16 additions and 16 deletions
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24
include/nuttx/clk/clk_provider.h
View file

@ -134,7 +134,7 @@ struct clk_ops_s
struct clk_gate_s
{
uint32_t reg;
uintptr_t reg;
uint8_t bit_idx;
uint8_t flags;
};
@ -153,7 +153,7 @@ struct clk_fixed_factor_s
struct clk_divider_s
{
uint32_t reg;
uintptr_t reg;
uint8_t shift;
uint8_t width;
uint16_t flags;
@ -161,7 +161,7 @@ struct clk_divider_s
struct clk_phase_s
{
uint32_t reg;
uintptr_t reg;
uint8_t shift;
uint8_t width;
uint8_t flags;
@ -169,7 +169,7 @@ struct clk_phase_s
struct clk_fractional_divider_s
{
uint32_t reg;
uintptr_t reg;
uint8_t mwidth;
uint8_t nwidth;
uint8_t mshift;
@ -179,7 +179,7 @@ struct clk_fractional_divider_s
struct clk_multiplier_s
{
uint32_t reg;
uintptr_t reg;
uint8_t shift;
uint8_t width;
uint8_t flags;
@ -187,7 +187,7 @@ struct clk_multiplier_s
struct clk_mux_s
{
uint32_t reg;
uintptr_t reg;
uint8_t width;
uint8_t shift;
uint8_t flags;
@ -205,7 +205,7 @@ FAR struct clk_s *clk_register(FAR const char *name,
FAR struct clk_s *clk_register_gate(FAR const char *name,
FAR const char *parent_name,
uint8_t flags, uint32_t reg,
uint8_t flags, uintptr_t reg,
uint8_t bit_idx,
uint8_t clk_gate_flags);
@ -221,34 +221,34 @@ FAR struct clk_s *clk_register_fixed_factor(FAR const char *name,
FAR struct clk_s *clk_register_divider(FAR const char *name,
FAR const char *parent_name,
uint8_t flags, uint32_t reg,
uint8_t flags, uintptr_t reg,
uint8_t shift, uint8_t width,
uint16_t clk_divider_flags);
FAR struct clk_s *clk_register_phase(FAR const char *name,
FAR const char *parent_name,
uint8_t flags, uint32_t reg,
uint8_t flags, uintptr_t reg,
uint8_t shift, uint8_t width,
uint8_t clk_phase_flags);
FAR struct clk_s *
clk_register_fractional_divider(FAR const char *name,
FAR const char *parent_name,
uint8_t flags, uint32_t reg,
uint8_t flags, uintptr_t reg,
uint8_t mshift, uint8_t mwidth,
uint8_t nshift, uint8_t nwidth,
uint8_t clk_divider_flags);
FAR struct clk_s *clk_register_multiplier(FAR const char *name,
FAR const char *parent_name,
uint8_t flags, uint32_t reg,
uint8_t flags, uintptr_t reg,
uint8_t shift, uint8_t width,
uint8_t clk_multiplier_flags);
FAR struct clk_s *clk_register_mux(FAR const char *name,
FAR const char * const *parent_names,
uint8_t num_parents, uint8_t flags,
uint32_t reg, uint8_t shift,
uintptr_t reg, uint8_t shift,
uint8_t width, uint8_t clk_mux_flags);
#ifdef CONFIG_CLK_RPMSG