From a8abef39079bf75e4ace5f0ce4d3a9f6401a5bf6 Mon Sep 17 00:00:00 2001 From: patacongo Date: Wed, 13 Feb 2013 15:59:10 +0000 Subject: [PATCH] A few more fixes for LPC1788 compilation (still more needed) git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5650 42af7a65-404d-4744-a932-0658087f49c3 --- configs/open1788/include/board.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/configs/open1788/include/board.h b/configs/open1788/include/board.h index 13d75870a95..258735e3416 100644 --- a/configs/open1788/include/board.h +++ b/configs/open1788/include/board.h @@ -84,7 +84,7 @@ */ #define BOARD_CCLKCFG_DIVIDER 6 -#define BOARD_CCLKCFG_VALUE ((BOARD_CCLKCFG_DIVIDER-1) << SYSCON_CCLKCFG_SHIFT) +#define BOARD_CCLKCFG_VALUE ((BOARD_CCLKCFG_DIVIDER-1) << SYSCON_CCLKCFG_CCLKDIV_SHIFT) /* PLL0. PLL0 is used to generate the CPU clock divider input (PLLCLK). * @@ -100,10 +100,10 @@ #define BOARD_CLKSRCSEL_VALUE SYSCON_CLKSRCSEL_MAIN #define BOARD_PLL0CFG_MSEL 20 -#define BOARD_PLL0CFG_NSEL 1 +#define BOARD_PLL0CFG_PSEL 1 #define BOARD_PLL0CFG_VALUE \ - (((BOARD_PLL0CFG_MSEL-1) << SYSCON_PLL0CFG_MSEL_SHIFT) | \ - ((BOARD_PLL0CFG_NSEL-1) << SYSCON_PLL0CFG_NSEL_SHIFT)) + (((BOARD_PLL0CFG_MSEL-1) << SYSCON_PLLCFG_MSEL_SHIFT) | \ + ((BOARD_PLL0CFG_PSEL-1) << SYSCON_PLLCFG_PSEL_SHIFT)) /* PLL1 -- Not used. */