From a67de9ce242054fd0a85de9ea0fc3b90878fadc2 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Mon, 7 Mar 2016 08:21:03 -0600 Subject: [PATCH] i.MX6: Add imx_lowputc.c; repartition some serial logic --- arch/arm/src/imx6/Make.defs | 2 +- arch/arm/src/imx6/chip/imx_pinmux.h | 105 +++++-- arch/arm/src/imx6/imx_config.h | 14 +- arch/arm/src/imx6/imx_lowputc.c | 441 ++++++++++++++++++++++++++++ arch/arm/src/imx6/imx_lowputc.h | 20 ++ arch/arm/src/imx6/imx_serial.c | 259 ++-------------- 6 files changed, 580 insertions(+), 261 deletions(-) create mode 100644 arch/arm/src/imx6/imx_lowputc.c diff --git a/arch/arm/src/imx6/Make.defs b/arch/arm/src/imx6/Make.defs index bc6502d47a4..a9977227a3e 100644 --- a/arch/arm/src/imx6/Make.defs +++ b/arch/arm/src/imx6/Make.defs @@ -133,4 +133,4 @@ CHIP_ASRCS = # i.MX6-specific C source files CHIP_CSRCS = imx_boot.c imx_memorymap.c imx_irq.c -CHIP_CSRCS = imx_gpio.c imx_iomuxc.c # imx_serial.c +CHIP_CSRCS = imx_gpio.c imx_iomuxc.c imx_serial.c # imx_lowputc.c diff --git a/arch/arm/src/imx6/chip/imx_pinmux.h b/arch/arm/src/imx6/chip/imx_pinmux.h index 70ab1e938f6..1eaab69b8c7 100644 --- a/arch/arm/src/imx6/chip/imx_pinmux.h +++ b/arch/arm/src/imx6/chip/imx_pinmux.h @@ -43,6 +43,23 @@ /***************************************************************************************************** * Pre-processor Definitions *****************************************************************************************************/ +/* Alternate Pin Functions. + * + * Alternative pin selections are provided with a numeric suffix like _1, _2, etc. Drivers, however, + * will use the pin selection without the numeric suffix. Additional definitions are required in the + * board.h file. For example, if UART1 RXD connects via the SD3_DATA6 pin, then the following + * definition should appear in the board.h header file for that board: + * + * #define GPIO_UART1_RX_DATA GPIO_UART1_RX_DATA_1 + * + * The driver will then automatically configere to use the SD3_DATA6 pin for UART RXD. + */ + +/* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! + * Additional effort is required to select specific GPIO options such as frequency, open-drain, + * push-pull, and pull-up/down! Just the basics are defined for most pins in this file. See the + * upper imx_gpio.h and imx_iomuxc.h header files for available definitions. + */ #define GPIO_ARM_EVENTI (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMX_PADMUX_GPIO05_INDEX)) #define GPIO_ARM_EVENTO (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMX_PADMUX_CSI0_PIXCLK_INDEX)) @@ -65,14 +82,17 @@ #define GPIO_ARM_TRACE14 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMX_PADMUX_CSI0_DATA17_INDEX)) #define GPIO_ARM_TRACE15 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMX_PADMUX_CSI0_DATA18_INDEX)) #define GPIO_ASRC_EXT_CLK_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMX_PADMUX_KEY_ROW3_INDEX)) + #define GPIO_ASRC_EXT_CLK_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMX_PADMUX_GPIO00_INDEX)) -#define GPIO_ASRC_EXT_CLK_3 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMX_PADMUX_GPIO18_INDEX)) +#define GPIO_ASRC_EXT_CLK_3 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMX_PADMUX_GPIO18_INDEX)) + #define GPIO_AUD3_RXC (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMX_PADMUX_CSI0_DATA10_INDEX)) #define GPIO_AUD3_RXD (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMX_PADMUX_CSI0_DATA07_INDEX)) #define GPIO_AUD3_RXFS (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMX_PADMUX_CSI0_DATA11_INDEX)) #define GPIO_AUD3_TXC (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMX_PADMUX_CSI0_DATA04_INDEX)) #define GPIO_AUD3_TXD (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMX_PADMUX_CSI0_DATA05_INDEX)) #define GPIO_AUD3_TXFS (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMX_PADMUX_CSI0_DATA06_INDEX)) + #define GPIO_AUD4_RXC_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMX_PADMUX_SD2_CMD_INDEX)) #define GPIO_AUD4_RXC_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMX_PADMUX_DISP0_DATA19_INDEX)) #define GPIO_AUD4_RXD_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMX_PADMUX_DISP0_DATA23_INDEX)) @@ -85,6 +105,7 @@ #define GPIO_AUD4_TXD_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMX_PADMUX_SD2_DATA2_INDEX)) #define GPIO_AUD4_TXFS_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMX_PADMUX_DISP0_DATA22_INDEX)) #define GPIO_AUD4_TXFS_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMX_PADMUX_SD2_DATA1_INDEX)) + #define GPIO_AUD5_RXC_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMX_PADMUX_DISP0_DATA14_INDEX)) #define GPIO_AUD5_RXC_2 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMX_PADMUX_EIM_DATA25_INDEX)) #define GPIO_AUD5_RXD_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMX_PADMUX_KEY_ROW1_INDEX)) @@ -97,12 +118,14 @@ #define GPIO_AUD5_TXD_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMX_PADMUX_DISP0_DATA17_INDEX)) #define GPIO_AUD5_TXFS_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMX_PADMUX_KEY_COL1_INDEX)) #define GPIO_AUD5_TXFS_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMX_PADMUX_DISP0_DATA18_INDEX)) + #define GPIO_AUD6_RXC (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMX_PADMUX_DISP0_DATA06_INDEX)) #define GPIO_AUD6_RXD (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMX_PADMUX_DI0_PIN04_INDEX)) #define GPIO_AUD6_RXFS (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMX_PADMUX_DISP0_DATA05_INDEX)) #define GPIO_AUD6_TXC (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMX_PADMUX_DI0_PIN15_INDEX)) #define GPIO_AUD6_TXD (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMX_PADMUX_DI0_PIN02_INDEX)) #define GPIO_AUD6_TXFS (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMX_PADMUX_DI0_PIN03_INDEX)) + #define GPIO_CCM_CLKO1_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMX_PADMUX_GPIO00_INDEX)) #define GPIO_CCM_CLKO1_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMX_PADMUX_CSI0_HSYNC_INDEX)) #define GPIO_CCM_CLKO1_3 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMX_PADMUX_GPIO05_INDEX)) @@ -112,10 +135,13 @@ #define GPIO_CCM_PMIC_READY_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMX_PADMUX_GPIO17_INDEX)) #define GPIO_CCM_PMIC_READY_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMX_PADMUX_EIM_EB0_INDEX)) #define GPIO_CCM_REF_EN (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMX_PADMUX_GPIO09_INDEX)) + #define GPIO_DCIC1_OUT_1 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMX_PADMUX_EIM_DATA17_INDEX)) #define GPIO_DCIC1_OUT_2 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMX_PADMUX_KEY_COL0_INDEX)) + #define GPIO_DCIC2_OUT_1 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMX_PADMUX_KEY_ROW0_INDEX)) #define GPIO_DCIC2_OUT_2 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMX_PADMUX_SD2_DATA0_INDEX)) + #define GPIO_ECSPI1_MISO_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMX_PADMUX_KEY_COL1_INDEX)) #define GPIO_ECSPI1_MISO_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMX_PADMUX_EIM_DATA17_INDEX)) #define GPIO_ECSPI1_MISO_3 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMX_PADMUX_CSI0_DATA06_INDEX)) @@ -140,6 +166,7 @@ #define GPIO_ECSPI1_SS2_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMX_PADMUX_EIM_DATA24_INDEX)) #define GPIO_ECSPI1_SS3_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMX_PADMUX_KEY_COL3_INDEX)) #define GPIO_ECSPI1_SS3_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMX_PADMUX_EIM_DATA25_INDEX)) + #define GPIO_ECSPI2_MISO_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMX_PADMUX_CSI0_DATA10_INDEX)) #define GPIO_ECSPI2_MISO_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMX_PADMUX_DISP0_DATA17_INDEX)) #define GPIO_ECSPI2_MISO_3 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMX_PADMUX_EIM_OE_INDEX)) @@ -157,6 +184,7 @@ #define GPIO_ECSPI2_SS1_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMX_PADMUX_DISP0_DATA15_INDEX)) #define GPIO_ECSPI2_SS2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMX_PADMUX_EIM_DATA24_INDEX)) #define GPIO_ECSPI2_SS3 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMX_PADMUX_EIM_DATA25_INDEX)) + #define GPIO_ECSPI3_MISO (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMX_PADMUX_DISP0_DATA02_INDEX)) #define GPIO_ECSPI3_MOSI (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMX_PADMUX_DISP0_DATA01_INDEX)) #define GPIO_ECSPI3_RDY (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMX_PADMUX_DISP0_DATA07_INDEX)) @@ -165,6 +193,7 @@ #define GPIO_ECSPI3_SS1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMX_PADMUX_DISP0_DATA04_INDEX)) #define GPIO_ECSPI3_SS2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMX_PADMUX_DISP0_DATA05_INDEX)) #define GPIO_ECSPI3_SS3 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMX_PADMUX_DISP0_DATA06_INDEX)) + #define GPIO_ECSPI4_MISO (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMX_PADMUX_EIM_DATA22_INDEX)) #define GPIO_ECSPI4_MOSI (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMX_PADMUX_EIM_DATA28_INDEX)) #define GPIO_ECSPI4_RDY (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMX_PADMUX_EIM_EB3_INDEX)) @@ -174,6 +203,7 @@ #define GPIO_ECSPI4_SS1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMX_PADMUX_EIM_ADDR25_INDEX)) #define GPIO_ECSPI4_SS2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMX_PADMUX_EIM_DATA24_INDEX)) #define GPIO_ECSPI4_SS3 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMX_PADMUX_EIM_DATA25_INDEX)) + #define GPIO_ECSPI5_MISO_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMX_PADMUX_SD1_DATA0_INDEX)) #define GPIO_ECSPI5_MISO_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMX_PADMUX_SD2_DATA0_INDEX)) #define GPIO_ECSPI5_MOSI_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMX_PADMUX_SD1_CMD_INDEX)) @@ -187,22 +217,23 @@ #define GPIO_ECSPI5_SS1_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMX_PADMUX_SD2_DATA2_INDEX)) #define GPIO_ECSPI5_SS2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMX_PADMUX_SD1_DATA3_INDEX)) #define GPIO_ECSPI5_SS3 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMX_PADMUX_SD2_DATA3_INDEX)) -#define GPIO_EIM_AD00 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMX_PADMUX_EIM_AD00_INDEX)) -#define GPIO_EIM_AD01 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMX_PADMUX_EIM_AD01_INDEX)) -#define GPIO_EIM_AD02 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMX_PADMUX_EIM_AD02_INDEX)) -#define GPIO_EIM_AD03 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMX_PADMUX_EIM_AD03_INDEX)) -#define GPIO_EIM_AD04 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMX_PADMUX_EIM_AD04_INDEX)) -#define GPIO_EIM_AD05 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMX_PADMUX_EIM_AD05_INDEX)) -#define GPIO_EIM_AD06 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMX_PADMUX_EIM_AD06_INDEX)) -#define GPIO_EIM_AD07 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMX_PADMUX_EIM_AD07_INDEX)) -#define GPIO_EIM_AD08 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMX_PADMUX_EIM_AD08_INDEX)) -#define GPIO_EIM_AD09 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMX_PADMUX_EIM_AD09_INDEX)) -#define GPIO_EIM_AD10 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMX_PADMUX_EIM_AD10_INDEX)) -#define GPIO_EIM_AD11 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMX_PADMUX_EIM_AD11_INDEX)) -#define GPIO_EIM_AD12 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMX_PADMUX_EIM_AD12_INDEX)) -#define GPIO_EIM_AD13 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMX_PADMUX_EIM_AD13_INDEX)) -#define GPIO_EIM_AD14 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMX_PADMUX_EIM_AD14_INDEX)) -#define GPIO_EIM_AD15 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMX_PADMUX_EIM_AD15_INDEX)) + +#define GPIO_EIM_ADDR00 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMX_PADMUX_EIM_AD00_INDEX)) +#define GPIO_EIM_ADDR01 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMX_PADMUX_EIM_AD01_INDEX)) +#define GPIO_EIM_ADDR02 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMX_PADMUX_EIM_AD02_INDEX)) +#define GPIO_EIM_ADDR03 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMX_PADMUX_EIM_AD03_INDEX)) +#define GPIO_EIM_ADDR04 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMX_PADMUX_EIM_AD04_INDEX)) +#define GPIO_EIM_ADDR05 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMX_PADMUX_EIM_AD05_INDEX)) +#define GPIO_EIM_ADDR06 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMX_PADMUX_EIM_AD06_INDEX)) +#define GPIO_EIM_ADDR07 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMX_PADMUX_EIM_AD07_INDEX)) +#define GPIO_EIM_ADDR08 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMX_PADMUX_EIM_AD08_INDEX)) +#define GPIO_EIM_ADDR09 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMX_PADMUX_EIM_AD09_INDEX)) +#define GPIO_EIM_ADDR10 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMX_PADMUX_EIM_AD10_INDEX)) +#define GPIO_EIM_ADDR11 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMX_PADMUX_EIM_AD11_INDEX)) +#define GPIO_EIM_ADDR12 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMX_PADMUX_EIM_AD12_INDEX)) +#define GPIO_EIM_ADDR13 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMX_PADMUX_EIM_AD13_INDEX)) +#define GPIO_EIM_ADDR14 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMX_PADMUX_EIM_AD14_INDEX)) +#define GPIO_EIM_ADDR15 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMX_PADMUX_EIM_AD15_INDEX)) #define GPIO_EIM_ADDR16 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMX_PADMUX_EIM_ADDR16_INDEX)) #define GPIO_EIM_ADDR17 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMX_PADMUX_EIM_ADDR17_INDEX)) #define GPIO_EIM_ADDR18 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMX_PADMUX_EIM_ADDR18_INDEX)) @@ -263,6 +294,7 @@ #define GPIO_EIM_OE (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMX_PADMUX_EIM_OE_INDEX)) #define GPIO_EIM_RW (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMX_PADMUX_EIM_RW_INDEX)) #define GPIO_EIM_WAIT (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMX_PADMUX_EIM_WAIT_INDEX)) + #define GPIO_ENET_1588_EVENT0_IN (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMX_PADMUX_ENET_TX_DATA1_INDEX)) #define GPIO_ENET_1588_EVENT0_OUT (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMX_PADMUX_GPIO19_INDEX)) #define GPIO_ENET_1588_EVENT1_IN (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMX_PADMUX_ENET_MDC_INDEX)) @@ -293,11 +325,14 @@ #define GPIO_ENET_TX_DATA3 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMX_PADMUX_KEY_ROW0_INDEX)) #define GPIO_ENET_TX_EN (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMX_PADMUX_ENET_TX_EN_INDEX)) #define GPIO_ENET_TX_ER (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMX_PADMUX_GPIO19_INDEX)) + #define GPIO_EPIT1_OUT_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMX_PADMUX_GPIO07_INDEX)) #define GPIO_EPIT1_OUT_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMX_PADMUX_GPIO00_INDEX)) #define GPIO_EPIT1_OUT_3 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMX_PADMUX_EIM_DATA19_INDEX)) + #define GPIO_EPIT2_OUT_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMX_PADMUX_GPIO08_INDEX)) #define GPIO_EPIT2_OUT_2 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMX_PADMUX_EIM_DATA20_INDEX)) + #define GPIO_ESAI_RX_CLK_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMX_PADMUX_GPIO01_INDEX)) #define GPIO_ESAI_RX_CLK_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMX_PADMUX_ENET_MDIO_INDEX)) #define GPIO_ESAI_RX_FS_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMX_PADMUX_GPIO09_INDEX)) @@ -322,28 +357,33 @@ #define GPIO_ESAI_TX4_RX1_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMX_PADMUX_ENET_TX_DATA0_INDEX)) #define GPIO_ESAI_TX5_RX0_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMX_PADMUX_GPIO08_INDEX)) #define GPIO_ESAI_TX5_RX0_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMX_PADMUX_ENET_MDC_INDEX)) + #define GPIO_FLEXCAN1_RX_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMX_PADMUX_KEY_ROW2_INDEX)) #define GPIO_FLEXCAN1_RX_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMX_PADMUX_SD3_CLK_INDEX)) #define GPIO_FLEXCAN1_RX_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMX_PADMUX_GPIO08_INDEX)) #define GPIO_FLEXCAN1_TX_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMX_PADMUX_KEY_COL2_INDEX)) #define GPIO_FLEXCAN1_TX_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMX_PADMUX_SD3_CMD_INDEX)) #define GPIO_FLEXCAN1_TX_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMX_PADMUX_GPIO07_INDEX)) + #define GPIO_FLEXCAN2_RX_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMX_PADMUX_KEY_ROW4_INDEX)) #define GPIO_FLEXCAN2_RX_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMX_PADMUX_SD3_DATA1_INDEX)) #define GPIO_FLEXCAN2_TX_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMX_PADMUX_KEY_COL4_INDEX)) #define GPIO_FLEXCAN2_TX_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMX_PADMUX_SD3_DATA0_INDEX)) + #define GPIO_GPT_CAPTURE1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMX_PADMUX_SD1_DATA0_INDEX)) #define GPIO_GPT_CAPTURE2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMX_PADMUX_SD1_DATA1_INDEX)) #define GPIO_GPT_CLKIN (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMX_PADMUX_SD1_CLK_INDEX)) #define GPIO_GPT_COMPARE1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMX_PADMUX_SD1_CMD_INDEX)) #define GPIO_GPT_COMPARE2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMX_PADMUX_SD1_DATA2_INDEX)) #define GPIO_GPT_COMPARE3 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMX_PADMUX_SD1_DATA3_INDEX)) + #define GPIO_HDMI_TX_CEC_LINE_1 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMX_PADMUX_EIM_ADDR25_INDEX)) #define GPIO_HDMI_TX_CEC_LINE_2 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMX_PADMUX_KEY_ROW2_INDEX)) #define GPIO_HDMI_TX_DDC_SCL_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMX_PADMUX_KEY_COL3_INDEX)) #define GPIO_HDMI_TX_DDC_SCL_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMX_PADMUX_EIM_EB2_INDEX)) #define GPIO_HDMI_TX_DDC_SDA_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMX_PADMUX_KEY_ROW3_INDEX)) #define GPIO_HDMI_TX_DDC_SDA_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMX_PADMUX_EIM_DATA16_INDEX)) + #define GPIO_HSI_RX_DATA (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMX_PADMUX_RGMII_TD2_INDEX)) #define GPIO_HSI_RX_FLAG (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMX_PADMUX_RGMII_TD1_INDEX)) #define GPIO_HSI_RX_READY (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMX_PADMUX_RGMII_RD0_INDEX)) @@ -352,20 +392,24 @@ #define GPIO_HSI_TX_FLAG (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMX_PADMUX_RGMII_RD1_INDEX)) #define GPIO_HSI_TX_READY (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMX_PADMUX_RGMII_TD0_INDEX)) #define GPIO_HSI_TX_WAKE (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMX_PADMUX_RGMII_RD3_INDEX)) + #define GPIO_I2C1_SCL_1 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMX_PADMUX_CSI0_DATA09_INDEX)) #define GPIO_I2C1_SCL_2 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMX_PADMUX_EIM_DATA21_INDEX)) #define GPIO_I2C1_SDA_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMX_PADMUX_EIM_DATA28_INDEX)) #define GPIO_I2C1_SDA_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMX_PADMUX_CSI0_DATA08_INDEX)) + #define GPIO_I2C2_SCL_1 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMX_PADMUX_KEY_COL3_INDEX)) #define GPIO_I2C2_SCL_2 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMX_PADMUX_EIM_EB2_INDEX)) #define GPIO_I2C2_SDA_1 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMX_PADMUX_KEY_ROW3_INDEX)) #define GPIO_I2C2_SDA_2 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMX_PADMUX_EIM_DATA16_INDEX)) + #define GPIO_I2C3_SCL_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMX_PADMUX_GPIO03_INDEX)) #define GPIO_I2C3_SCL_2 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMX_PADMUX_EIM_DATA17_INDEX)) #define GPIO_I2C3_SCL_3 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMX_PADMUX_GPIO05_INDEX)) #define GPIO_I2C3_SDA_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMX_PADMUX_GPIO06_INDEX)) #define GPIO_I2C3_SDA_2 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMX_PADMUX_EIM_DATA18_INDEX)) #define GPIO_I2C3_SDA_3 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMX_PADMUX_GPIO16_INDEX)) + #define GPIO_IPU1_CSI0_DATA_EN (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMX_PADMUX_CSI0_DATA_EN_INDEX)) #define GPIO_IPU1_CSI0_DATA00 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMX_PADMUX_EIM_DATA27_INDEX)) #define GPIO_IPU1_CSI0_DATA01 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMX_PADMUX_EIM_DATA26_INDEX)) @@ -487,6 +531,7 @@ #define GPIO_IPU1_SISG3_2 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMX_PADMUX_EIM_DATA27_INDEX)) #define GPIO_IPU1_SISG4 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMX_PADMUX_KEY_COL4_INDEX)) #define GPIO_IPU1_SISG5 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMX_PADMUX_KEY_ROW4_INDEX)) + #define GPIO_IPU2_CSI1_DATA_EN_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMX_PADMUX_EIM_AD10_INDEX)) #define GPIO_IPU2_CSI1_DATA_EN_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMX_PADMUX_EIM_DATA23_INDEX)) #define GPIO_IPU2_CSI1_DATA00 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMX_PADMUX_EIM_AD09_INDEX)) @@ -561,7 +606,9 @@ #define GPIO_IPU2_SISG3 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMX_PADMUX_EIM_ADDR23_INDEX)) #define GPIO_IPU2_SISG4 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMX_PADMUX_NAND_CLE_INDEX)) #define GPIO_IPU2_SISG5 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMX_PADMUX_NAND_WP_INDEX)) + #define GPIO_JTAG_DE (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMX_PADMUX_GPIO16_INDEX)) + #define GPIO_KEY_COL0 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMX_PADMUX_KEY_COL0_INDEX)) #define GPIO_KEY_COL1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMX_PADMUX_KEY_COL1_INDEX)) #define GPIO_KEY_COL2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMX_PADMUX_KEY_COL2_INDEX)) @@ -591,12 +638,14 @@ #define GPIO_KEY_ROW7_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMX_PADMUX_GPIO05_INDEX)) #define GPIO_KEY_ROW7_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMX_PADMUX_CSI0_DATA09_INDEX)) #define GPIO_KEY_ROW7_3 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMX_PADMUX_SD2_DATA0_INDEX)) + #define GPIO_MLB_CLK_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMX_PADMUX_ENET_TX_DATA1_INDEX)) #define GPIO_MLB_CLK_2 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMX_PADMUX_GPIO03_INDEX)) #define GPIO_MLB_DATA_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMX_PADMUX_ENET_MDC_INDEX)) #define GPIO_MLB_DATA_2 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMX_PADMUX_GPIO02_INDEX)) #define GPIO_MLB_SIG_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMX_PADMUX_ENET_RX_DATA1_INDEX)) #define GPIO_MLB_SIG_2 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMX_PADMUX_GPIO06_INDEX)) + #define GPIO_NAND_ALE (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMX_PADMUX_NAND_ALE_INDEX)) #define GPIO_NAND_CE0 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMX_PADMUX_NAND_CS0_INDEX)) #define GPIO_NAND_CE1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMX_PADMUX_NAND_CS1_INDEX)) @@ -616,16 +665,21 @@ #define GPIO_NAND_READY (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMX_PADMUX_NAND_READY_INDEX)) #define GPIO_NAND_WE (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMX_PADMUX_SD4_CLK_INDEX)) #define GPIO_NAND_WP (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMX_PADMUX_NAND_WP_INDEX)) + #define GPIO_PWM1_OUT_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMX_PADMUX_DISP0_DATA08_INDEX)) #define GPIO_PWM1_OUT_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMX_PADMUX_SD1_DATA3_INDEX)) #define GPIO_PWM1_OUT_3 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMX_PADMUX_GPIO09_INDEX)) + #define GPIO_PWM2_OUT_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMX_PADMUX_DISP0_DATA09_INDEX)) #define GPIO_PWM2_OUT_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMX_PADMUX_SD1_DATA2_INDEX)) #define GPIO_PWM2_OUT_3 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMX_PADMUX_GPIO01_INDEX)) + #define GPIO_PWM3_OUT_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMX_PADMUX_SD1_DATA1_INDEX)) #define GPIO_PWM3_OUT_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMX_PADMUX_SD4_DATA1_INDEX)) + #define GPIO_PWM4_OUT_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMX_PADMUX_SD1_CMD_INDEX)) #define GPIO_PWM4_OUT_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMX_PADMUX_SD4_DATA2_INDEX)) + #define GPIO_RGMII_RD0 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMX_PADMUX_RGMII_RD0_INDEX)) #define GPIO_RGMII_RD1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMX_PADMUX_RGMII_RD1_INDEX)) #define GPIO_RGMII_RD2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMX_PADMUX_RGMII_RD2_INDEX)) @@ -638,6 +692,7 @@ #define GPIO_RGMII_TD3 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMX_PADMUX_RGMII_TD3_INDEX)) #define GPIO_RGMII_TX_CTL (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMX_PADMUX_RGMII_TX_CTL_INDEX)) #define GPIO_RGMII_TXC (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMX_PADMUX_RGMII_TXC_INDEX)) + #define GPIO_SD1_CD (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMX_PADMUX_GPIO01_INDEX)) #define GPIO_SD1_CLK (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMX_PADMUX_SD1_CLK_INDEX)) #define GPIO_SD1_CMD (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMX_PADMUX_SD1_CMD_INDEX)) @@ -654,6 +709,7 @@ #define GPIO_SD1_VSELECT_2 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMX_PADMUX_KEY_ROW3_INDEX)) #define GPIO_SD1_WP_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMX_PADMUX_DI0_PIN04_INDEX)) #define GPIO_SD1_WP_2 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMX_PADMUX_GPIO09_INDEX)) + #define GPIO_SD2_CD (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMX_PADMUX_GPIO04_INDEX)) #define GPIO_SD2_CLK (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMX_PADMUX_SD2_CLK_INDEX)) #define GPIO_SD2_CMD (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMX_PADMUX_SD2_CMD_INDEX)) @@ -669,6 +725,7 @@ #define GPIO_SD2_VSELECT_1 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMX_PADMUX_KEY_ROW2_INDEX)) #define GPIO_SD2_VSELECT_2 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMX_PADMUX_KEY_ROW1_INDEX)) #define GPIO_SD2_WP (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMX_PADMUX_GPIO02_INDEX)) + #define GPIO_SD3_CLK (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMX_PADMUX_SD3_CLK_INDEX)) #define GPIO_SD3_CMD (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMX_PADMUX_SD3_CMD_INDEX)) #define GPIO_SD3_DATA0 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMX_PADMUX_SD3_DATA0_INDEX)) @@ -682,6 +739,7 @@ #define GPIO_SD3_RESET (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMX_PADMUX_SD3_RESET_INDEX)) #define GPIO_SD3_VSELECT_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMX_PADMUX_GPIO18_INDEX)) #define GPIO_SD3_VSELECT_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMX_PADMUX_NAND_CS1_INDEX)) + #define GPIO_SD4_CLK (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMX_PADMUX_SD4_CLK_INDEX)) #define GPIO_SD4_CMD (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMX_PADMUX_SD4_CMD_INDEX)) #define GPIO_SD4_DATA0 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMX_PADMUX_SD4_DATA0_INDEX)) @@ -694,12 +752,15 @@ #define GPIO_SD4_DATA7 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMX_PADMUX_SD4_DATA7_INDEX)) #define GPIO_SD4_RESET (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMX_PADMUX_NAND_ALE_INDEX)) #define GPIO_SD4_VSELECT (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMX_PADMUX_NAND_CS1_INDEX)) + #define GPIO_SDMA_EXT_EVENT0_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMX_PADMUX_GPIO17_INDEX)) #define GPIO_SDMA_EXT_EVENT0_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMX_PADMUX_DISP0_DATA16_INDEX)) #define GPIO_SDMA_EXT_EVENT1_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMX_PADMUX_GPIO18_INDEX)) #define GPIO_SDMA_EXT_EVENT1_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMX_PADMUX_DISP0_DATA17_INDEX)) + #define GPIO_SNVS_VIO_5 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMX_PADMUX_GPIO00_INDEX)) #define GPIO_SNVS_VIO_5_CTL (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMX_PADMUX_GPIO18_INDEX)) + #define GPIO_SPDIF_EXT_CLK_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMX_PADMUX_RGMII_TXC_INDEX)) #define GPIO_SPDIF_EXT_CLK_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMX_PADMUX_ENET_CRS_DV_INDEX)) #define GPIO_SPDIF_IN_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMX_PADMUX_ENET_RX_ER_INDEX)) @@ -714,6 +775,7 @@ #define GPIO_SPDIF_OUT_4 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMX_PADMUX_EIM_DATA22_INDEX)) #define GPIO_SPDIF_SR_CLK_1 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMX_PADMUX_ENET_REF_CLK_INDEX)) #define GPIO_SPDIF_SR_CLK_2 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMX_PADMUX_GPIO08_INDEX)) + #define GPIO_SRC_BOOT_CFG00 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMX_PADMUX_EIM_AD00_INDEX)) #define GPIO_SRC_BOOT_CFG01 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMX_PADMUX_EIM_AD01_INDEX)) #define GPIO_SRC_BOOT_CFG02 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMX_PADMUX_EIM_AD02_INDEX)) @@ -746,6 +808,7 @@ #define GPIO_SRC_BOOT_CFG29 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMX_PADMUX_EIM_RW_INDEX)) #define GPIO_SRC_BOOT_CFG30 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMX_PADMUX_EIM_EB2_INDEX)) #define GPIO_SRC_BOOT_CFG31 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMX_PADMUX_EIM_EB3_INDEX)) + #define GPIO_UART1_CTS_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMX_PADMUX_SD3_DATA0_INDEX)) #define GPIO_UART1_CTS_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMX_PADMUX_EIM_DATA19_INDEX)) #define GPIO_UART1_DCD (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMX_PADMUX_EIM_DATA23_INDEX)) @@ -758,6 +821,7 @@ #define GPIO_UART1_RX_DATA_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMX_PADMUX_CSI0_DATA11_INDEX)) #define GPIO_UART1_TX_DATA_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMX_PADMUX_SD3_DATA7_INDEX)) #define GPIO_UART1_TX_DATA_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMX_PADMUX_CSI0_DATA10_INDEX)) + #define GPIO_UART2_CTS_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMX_PADMUX_SD3_CMD_INDEX)) #define GPIO_UART2_CTS_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMX_PADMUX_SD4_DATA6_INDEX)) #define GPIO_UART2_CTS_3 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMX_PADMUX_EIM_DATA28_INDEX)) @@ -772,6 +836,7 @@ #define GPIO_UART2_TX_DATA_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMX_PADMUX_SD4_DATA7_INDEX)) #define GPIO_UART2_TX_DATA_3 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMX_PADMUX_EIM_DATA26_INDEX)) #define GPIO_UART2_TX_DATA_4 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMX_PADMUX_GPIO07_INDEX)) + #define GPIO_UART3_CTS_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMX_PADMUX_SD3_DATA3_INDEX)) #define GPIO_UART3_CTS_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMX_PADMUX_EIM_DATA23_INDEX)) #define GPIO_UART3_CTS_3 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMX_PADMUX_EIM_DATA30_INDEX)) @@ -782,12 +847,14 @@ #define GPIO_UART3_RX_DATA_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMX_PADMUX_SD4_CLK_INDEX)) #define GPIO_UART3_TX_DATA_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMX_PADMUX_EIM_DATA24_INDEX)) #define GPIO_UART3_TX_DATA_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMX_PADMUX_SD4_CMD_INDEX)) + #define GPIO_UART4_CTS (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMX_PADMUX_CSI0_DATA17_INDEX)) #define GPIO_UART4_RTS (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMX_PADMUX_CSI0_DATA16_INDEX)) #define GPIO_UART4_RX_DATA_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMX_PADMUX_CSI0_DATA13_INDEX)) #define GPIO_UART4_RX_DATA_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMX_PADMUX_KEY_ROW0_INDEX)) #define GPIO_UART4_TX_DATA_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMX_PADMUX_CSI0_DATA12_INDEX)) #define GPIO_UART4_TX_DATA_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMX_PADMUX_KEY_COL0_INDEX)) + #define GPIO_UART5_CTS_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMX_PADMUX_CSI0_DATA19_INDEX)) #define GPIO_UART5_CTS_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMX_PADMUX_KEY_ROW4_INDEX)) #define GPIO_UART5_RTS_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMX_PADMUX_CSI0_DATA18_INDEX)) @@ -796,6 +863,7 @@ #define GPIO_UART5_RX_DATA_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMX_PADMUX_KEY_ROW1_INDEX)) #define GPIO_UART5_TX_DATA_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMX_PADMUX_CSI0_DATA14_INDEX)) #define GPIO_UART5_TX_DATA_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMX_PADMUX_KEY_COL1_INDEX)) + #define GPIO_USB_H1_OC_1 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMX_PADMUX_EIM_DATA30_INDEX)) #define GPIO_USB_H1_OC_2 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMX_PADMUX_GPIO03_INDEX)) #define GPIO_USB_H1_PWR_1 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMX_PADMUX_EIM_DATA31_INDEX)) @@ -813,14 +881,17 @@ #define GPIO_USB_OTG_PWR_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMX_PADMUX_KEY_ROW4_INDEX)) #define GPIO_USB_OTG_PWR_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMX_PADMUX_EIM_DATA22_INDEX)) #define GPIO_USB_OTG_PWR_CTL_WAKE (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMX_PADMUX_GPIO08_INDEX)) + #define GPIO_WDOG1_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMX_PADMUX_GPIO09_INDEX)) #define GPIO_WDOG1_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMX_PADMUX_DISP0_DATA08_INDEX)) #define GPIO_WDOG1_3 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMX_PADMUX_SD1_DATA2_INDEX)) #define GPIO_WDOG1_RESET_DEB (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMX_PADMUX_SD1_DATA2_INDEX)) + #define GPIO_WDOG2_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMX_PADMUX_GPIO01_INDEX)) #define GPIO_WDOG2_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMX_PADMUX_DISP0_DATA09_INDEX)) #define GPIO_WDOG2_3 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMX_PADMUX_SD1_DATA3_INDEX)) #define GPIO_WDOG2_RESET_DEB (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMX_PADMUX_SD1_DATA3_INDEX)) + #define GPIO_XTALOSC_OSC32K_32K_OUT_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMX_PADMUX_ENET_RX_DATA0_INDEX)) #define GPIO_XTALOSC_OSC32K_32K_OUT_2 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMX_PADMUX_KEY_ROW3_INDEX)) #define GPIO_XTALOSC_OSC32K_32K_OUT_3 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMX_PADMUX_SD1_CLK_INDEX)) diff --git a/arch/arm/src/imx6/imx_config.h b/arch/arm/src/imx6/imx_config.h index 294dd75d6f2..a2214e70038 100644 --- a/arch/arm/src/imx6/imx_config.h +++ b/arch/arm/src/imx6/imx_config.h @@ -53,7 +53,7 @@ #if defined(CONFIG_IMX6_UART1) || defined(CONFIG_IMX6_UART2) || \ defined(CONFIG_IMX6_UART3) || defined(CONFIG_IMX6_UART4) || \ defined(CONFIG_IMX6_UART5) -# define IMX6_HAVE_UART +# define IMX_HAVE_UART #endif #undef SUPPRESS_CONSOLE_CONFIG @@ -68,31 +68,31 @@ # undef CONFIG_UART3_SERIAL_CONSOLE # undef CONFIG_UART4_SERIAL_CONSOLE # undef CONFIG_UART5_SERIAL_CONSOLE -# define IMX6_HAVE_UART_CONSOLE 1 +# define IMX_HAVE_UART_CONSOLE 1 #elif defined(CONFIG_UART2_SERIAL_CONSOLE) && defined(CONFIG_IMX6_UART2) # undef CONFIG_UART1_SERIAL_CONSOLE # undef CONFIG_UART3_SERIAL_CONSOLE # undef CONFIG_UART4_SERIAL_CONSOLE # undef CONFIG_UART5_SERIAL_CONSOLE -# define IMX6_HAVE_UART_CONSOLE 1 +# define IMX_HAVE_UART_CONSOLE 1 #elif defined(CONFIG_UART3_SERIAL_CONSOLE) && defined(CONFIG_IMX6_UART3) # undef CONFIG_UART1_SERIAL_CONSOLE # undef CONFIG_UART2_SERIAL_CONSOLE # undef CONFIG_UART4_SERIAL_CONSOLE # undef CONFIG_UART5_SERIAL_CONSOLE -# define IMX6_HAVE_UART_CONSOLE 1 +# define IMX_HAVE_UART_CONSOLE 1 #elif defined(CONFIG_UART4_SERIAL_CONSOLE) && defined(CONFIG_IMX6_UART4) # undef CONFIG_UART1_SERIAL_CONSOLE # undef CONFIG_UART2_SERIAL_CONSOLE # undef CONFIG_UART3_SERIAL_CONSOLE # undef CONFIG_UART5_SERIAL_CONSOLE -# define IMX6_HAVE_UART_CONSOLE 1 +# define IMX_HAVE_UART_CONSOLE 1 #elif defined(CONFIG_UART5_SERIAL_CONSOLE) && defined(CONFIG_IMX6_UART5) # undef CONFIG_UART1_SERIAL_CONSOLE # undef CONFIG_UART2_SERIAL_CONSOLE # undef CONFIG_UART3_SERIAL_CONSOLE # undef CONFIG_UART4_SERIAL_CONSOLE -# define IMX6_HAVE_UART_CONSOLE 1 +# define IMX_HAVE_UART_CONSOLE 1 #else # warning "No valid CONFIG_UARTn/USARTn_SERIAL_CONSOLE Setting" # undef CONFIG_UART1_SERIAL_CONSOLE @@ -100,7 +100,7 @@ # undef CONFIG_UART3_SERIAL_CONSOLE # undef CONFIG_UART4_SERIAL_CONSOLE # undef CONFIG_UART5_SERIAL_CONSOLE -# undef IMX6_HAVE_UART_CONSOLE +# undef IMX_HAVE_UART_CONSOLE #endif #endif /* __ARCH_ARM_SRC_IMX6_IMX_CONFIG_H */ diff --git a/arch/arm/src/imx6/imx_lowputc.c b/arch/arm/src/imx6/imx_lowputc.c new file mode 100644 index 00000000000..167abc206fc --- /dev/null +++ b/arch/arm/src/imx6/imx_lowputc.c @@ -0,0 +1,441 @@ +/**************************************************************************** + * arch/arm/src/imx6/imx_lowputc.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include + +#include "up_arch.h" +#include "chip/imx_uart.h" +#include "imx_gpio.h" +#include "imx_lowputc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifdef IMX_HAVE_UART_CONSOLE +# if defined(CONFIG_UART1_SERIAL_CONSOLE) +# define IMX_CONSOLE_VBASE IMX_UART1_VBASE +# define IMX_CONSOLE_BAUD CONFIG_UART1_BAUD +# define IMX_CONSOLE_BITS CONFIG_UART1_BITS +# define IMX_CONSOLE_PARITY CONFIG_UART1_PARITY +# define IMX_CONSOLE_2STOP CONFIG_UART1_2STOP +# elif defined(CONFIG_UART2_SERIAL_CONSOLE) +# define IMX_CONSOLE_VBASE IMX_UART2_VBASE +# define IMX_CONSOLE_BAUD CONFIG_UART2_BAUD +# define IMX_CONSOLE_BITS CONFIG_UART2_BITS +# define IMX_CONSOLE_PARITY CONFIG_UART2_PARITY +# define IMX_CONSOLE_2STOP CONFIG_UART2_2STOP +# elif defined(CONFIG_UART3_SERIAL_CONSOLE) +# define IMX_CONSOLE_VBASE IMX_UART3_VBASE +# define IMX_CONSOLE_BAUD CONFIG_UART3_BAUD +# define IMX_CONSOLE_BITS CONFIG_UART3_BITS +# define IMX_CONSOLE_PARITY CONFIG_UART3_PARITY +# define IMX_CONSOLE_2STOP CONFIG_UART3_2STOP +# elif defined(CONFIG_UART4_SERIAL_CONSOLE) +# define IMX_CONSOLE_VBASE IMX_UART4_VBASE +# define IMX_CONSOLE_BAUD CONFIG_UART4_BAUD +# define IMX_CONSOLE_BITS CONFIG_UART4_BITS +# define IMX_CONSOLE_PARITY CONFIG_UART4_PARITY +# define IMX_CONSOLE_2STOP CONFIG_UART4_2STOP +# elif defined(CONFIG_UART5_SERIAL_CONSOLE) +# define IMX_CONSOLE_VBASE IMX_UART5_VBASE +# define IMX_CONSOLE_BAUD CONFIG_UART5_BAUD +# define IMX_CONSOLE_BITS CONFIG_UART5_BITS +# define IMX_CONSOLE_PARITY CONFIG_UART5_PARITY +# define IMX_CONSOLE_2STOP CONFIG_UART5_2STOP +# endif +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef IMX_HAVE_UART_CONSOLE +static const struct uart_config_s g_console_config = +{ + .baud = IMX_CONSOLE_BAUD, /* Configured baud */ + .parity = IMX_CONSOLE_PARITY, /* 0=none, 1=odd, 2=even */ + .bits = IMX_CONSOLE_BITS, /* Number of bits (5-9) */ + .stopbits2 = IMX_CONSOLE_2STOP, /* true: Configure with 2 stop bits instead of 1 */ +}; +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: imx_lowsetup + * + * Description: + * Called at the very beginning of _start. Performs low level + * initialization including setup of the console UART. This UART done + * early so that the serial console is available for debugging very early + * in the boot sequence. + * + ****************************************************************************/ + +void imx_lowsetup(void) +{ +#ifdef CONFIG_IMX6_UART1 + /* Disable and configure UART1 */ + + putreg32(0, IMX_UART1_VBASE + UART_UCR1_OFFSET); + putreg32(0, IMX_UART1_VBASE + UART_UCR2_OFFSET); + putreg32(0, IMX_UART1_VBASE + UART_UCR3_OFFSET); + putreg32(0, IMX_UART1_VBASE + UART_UCR4_OFFSET); + + /* Configure UART1 pins: RXD and TXD. Also configure RTS and CTS if flow + * control is enabled. REVISIT: DTR, DCD, RI, and DSR -- not configured. + */ + + (void)imx_config_gpio(GPIO_UART1_RX_DATA); + (void)imx_config_gpio(GPIO_UART1_TX_DATA); +#ifdef CONFIG_UART1_OFLOWCONTROL + (void)imx_config_gpio(GPIO_UART1_CTS); +#endif +#ifdef CONFIG_UART1_IFLOWCONTROL + (void)imx_config_gpio(GPIO_UART1_RTS); +#endif +#endif + +#ifdef CONFIG_IMX6_UART2 + /* Disable and configure UART2 */ + + putreg32(0, IMX_UART2_VBASE + UART_UCR1_OFFSET); + putreg32(0, IMX_UART2_VBASE + UART_UCR2_OFFSET); + putreg32(0, IMX_UART2_VBASE + UART_UCR3_OFFSET); + putreg32(0, IMX_UART2_VBASE + UART_UCR4_OFFSET); + + /* Configure UART2 pins: RXD and TXD. Also configure RTS and CTS if flow + * control is enabled. + */ + + (void)imx_config_gpio(GPIO_UART2_RX_DATA); + (void)imx_config_gpio(GPIO_UART2_TX_DATA); +#ifdef CONFIG_UART1_OFLOWCONTROL + (void)imx_config_gpio(GPIO_UART2_CTS); +#endif +#ifdef CONFIG_UART1_IFLOWCONTROL + (void)imx_config_gpio(GPIO_UART2_RTS); +#endif +#endif + +#ifdef CONFIG_IMX6_UART3 + /* Disable and configure UART3 */ + + putreg32(0, IMX_UART3_VBASE + UART_UCR1_OFFSET); + putreg32(0, IMX_UART3_VBASE + UART_UCR2_OFFSET); + putreg32(0, IMX_UART3_VBASE + UART_UCR3_OFFSET); + putreg32(0, IMX_UART3_VBASE + UART_UCR4_OFFSET); + + /* Configure UART3 pins: RXD and TXD. Also configure RTS and CTS if flow + * control is enabled. + */ + + (void)imx_config_gpio(GPIO_UART3_RX_DATA); + (void)imx_config_gpio(GPIO_UART3_TX_DATA); +#ifdef CONFIG_UART1_OFLOWCONTROL + (void)imx_config_gpio(GPIO_UART3_CTS); +#endif +#ifdef CONFIG_UART1_IFLOWCONTROL + (void)imx_config_gpio(GPIO_UART3_RTS); +#endif +#endif + +#ifdef CONFIG_IMX6_UART4 + /* Disable and configure UART4 */ + + putreg32(0, IMX_UART4_VBASE + UART_UCR1_OFFSET); + putreg32(0, IMX_UART4_VBASE + UART_UCR2_OFFSET); + putreg32(0, IMX_UART4_VBASE + UART_UCR3_OFFSET); + putreg32(0, IMX_UART4_VBASE + UART_UCR4_OFFSET); + + /* Configure UART4 pins: RXD and TXD. Also configure RTS and CTS if flow + * control is enabled. + */ + + (void)imx_config_gpio(GPIO_UART4_RX_DATA); + (void)imx_config_gpio(GPIO_UART4_TX_DATA); +#ifdef CONFIG_UART1_OFLOWCONTROL + (void)imx_config_gpio(GPIO_UART4_CTS); +#endif +#ifdef CONFIG_UART1_IFLOWCONTROL + (void)imx_config_gpio(GPIO_UART4_RTS); +#endif +#endif + +#ifdef CONFIG_IMX6_UART5 + /* Disable and configure UART5 */ + + putreg32(0, IMX_UART5_VBASE + UART_UCR1_OFFSET); + putreg32(0, IMX_UART5_VBASE + UART_UCR2_OFFSET); + putreg32(0, IMX_UART5_VBASE + UART_UCR3_OFFSET); + putreg32(0, IMX_UART5_VBASE + UART_UCR4_OFFSET); + + /* Configure UART5 pins: RXD and TXD. Also configure RTS and CTS if flow + * control is enabled. + */ + + (void)imx_config_gpio(GPIO_UART5_RX_DATA); + (void)imx_config_gpio(GPIO_UART5_TX_DATA); +#ifdef CONFIG_UART1_OFLOWCONTROL + (void)imx_config_gpio(GPIO_UART5_CTS); +#endif +#ifdef CONFIG_UART1_IFLOWCONTROL + (void)imx_config_gpio(GPIO_UART5_RTS); +#endif +#endif + +#ifdef IMX_HAVE_UART_CONSOLE + /* Configure the serial console for initial, non-interrupt driver mode */ + + (void)imx_uart_configure(IMX_CONSOLE_VBASE, &g_console_config); +#endif +} + +/************************************************************************************ + * Name: imx_uart_configure + * + * Description: + * Configure a UART for non-interrupt driven operation + * + ************************************************************************************/ + +int imx_uart_configure(uint32_t base, FAR const struct uart_config_s *config) +{ +#ifndef CONFIG_SUPPRESS_UART_CONFIG + uint32_t regval; + uint32_t ucr2; + uint32_t div; + uint32_t num; + uint32_t den; + + /* Disable the UART */ + + putreg32(0, base + UART_UCR1_OFFSET); + putreg32(0, base + UART_UCR2_OFFSET); + putreg32(0, base + UART_UCR3_OFFSET); + putreg32(0, base + UART_UCR4_OFFSET); + + /* Set up UCR2 */ + + ucr2 = getreg32(base + UART_UCR2_OFFSET); + ucr2 |= (UART_UCR2_SRST | UART_UCR2_IRTS); + + /* Select the number of data bits */ + + DEBUGASSERT(config->bits == 7 || config->bits == 8); + if (config->bits == 8) + { + ucr2 |= UART_UCR2_WS; + } + + /* Select the number of stop bits */ + + if (config->stopbits2) + { + ucr2 |= UART_UCR2_STPB; + } + + /* Select even/odd parity */ + + if (config->parity) + { + DEBUGASSERT(config->parity == 1 || config->parity == 2); + ucr2 |= UART_UCR2_PREN; + if (config->parity == 1) + { + ucr2 |= UART_UCR2_PROE; + } + } + + /* Select RTS */ + +#if 0 + ucr2 &= ~UCR2_IRTS; + ucr2 |= UCR2_CTSC; +#endif + + /* Setup hardware flow control */ + + regval = 0; +#if 0 + if (config->hwfc) + { + ucr2 |= UART_UCR2_IRTS; + + /* CTS controled by Rx FIFO */ + + ucr2 |= UART_UCR2_CTSC; + + /* Set CTS trigger level */ + + regval |= 30 << UART_UCR4_CTSTL_SHIFT; + } +#endif + + /* i.MX reference clock (PERCLK1) is configured for 16MHz */ + + putreg32(regval | UART_UCR4_REF16, base + UART_UCR4_OFFSET); + + /* Setup the new UART configuration */ + + putreg32(ucr2, base + UART_UCR2_OFFSET); + + /* Set the baud. + * + * baud * 16 / REFFREQ = NUM/DEN + * UBIR = NUM-1; + * UMBR = DEN-1 + * REFFREQ = PERCLK1 / DIV + * DIV = RFDIV[2:0] + * + * First, select a closest value we can for the divider + */ + + div = (BOARD_PERCLK1_FREQUENCY >> 4) / config->baud; + if (div > 7) + { + div = 7; + } + else if (div < 1) + { + div = 1; + } + + /* Now find the numerator and denominator. These must have + * the ratio baud/(PERCLK / div / 16), but the values cannot + * exceed 16 bits + */ + + num = config->baud; + den = (BOARD_PERCLK1_FREQUENCY << 4) / div; + + if (num > den) + { + if (num > 0x00010000) + { + /* b16 is a scale such that b16*num = 0x10000 * 2**16 */ + + uint32_t b16 = 0x100000000LL / num; + num = 0x00010000; + den = (b16 * den) >> 16; + } + } + else + { + if (den > 0x0000ffff) + { + /* b16 is a scale such that b16*den = 0x10000 * 2**16 */ + + uint32_t b16 = 0x100000000LL / den; + num = (b16 * num) >> 16; + den = 0x00010000; + } + } + + /* The actual values are we write to the registers need to be + * decremented by 1. + */ + + if (num > 0) + { + num--; + } + + if (den > 0) + { + den--; + } + + /* The UBIR must be set before the UBMR register */ + + putreg32(num, base + UART_UBIR_OFFSET); + putreg32(den, base + UART_UBMR_OFFSET); + + /* Fixup the divisor, the value in the UFCR regiser is + * + * 000 = Divide input clock by 6 + * 001 = Divide input clock by 5 + * 010 = Divide input clock by 4 + * 011 = Divide input clock by 3 + * 100 = Divide input clock by 2 + * 101 = Divide input clock by 1 + * 110 = Divide input clock by 7 + */ + + if (div == 7) + { + div = 6; + } + else + { + div = 6 - div; + } + + regval = div << UART_UFCR_RFDIV_SHIFT; + + /* Set the TX trigger level to interrupt when the TxFIFO has 2 or fewer + * characters. Set the RX trigger level to interrupt when the RxFIFO has + * 1 character. + */ + + regval |= ((2 << UART_UFCR_TXTL_SHIFT) | (1 << UART_UFCR_RXTL_SHIFT)); + putreg32(regval, base + UART_UFCR_OFFSET); + + /* Enable the TX and RX */ + + ucr2 |= (UART_UCR2_TXEN | UART_UCR2_RXEN); + putreg32(ucr2, base + UART_UCR2_OFFSET); + + /* Enable the UART */ + + regval = getreg32(base + UART_UCR1_OFFSET); + regval |= UART_UCR1_UARTCLEN; + putreg32(regval, base + UART_UCR1_OFFSET); +#endif + + return OK; +} diff --git a/arch/arm/src/imx6/imx_lowputc.h b/arch/arm/src/imx6/imx_lowputc.h index 786b8a68aed..a9ff01ba38d 100644 --- a/arch/arm/src/imx6/imx_lowputc.h +++ b/arch/arm/src/imx6/imx_lowputc.h @@ -54,6 +54,16 @@ * Pre-processor Definitions ****************************************************************************/ +/* This structure describes the configuration of an UART */ + +struct uart_config_s +{ + uint32_t baud; /* Configured baud */ + uint8_t parity; /* 0=none, 1=odd, 2=even */ + uint8_t bits; /* Number of bits (5-9) */ + bool stopbits2; /* true: Configure with 2 stop bits instead of 1 */ +}; + /**************************************************************************** * Public Types ****************************************************************************/ @@ -94,6 +104,16 @@ extern "C" void imx_lowsetup(void); +/************************************************************************************ + * Name: imx_uart_configure + * + * Description: + * Configure a UART for non-interrupt driven operation + * + ************************************************************************************/ + +int imx_uart_configure(uint32_t base, FAR const struct uart_config_s *config); + #undef EXTERN #if defined(__cplusplus) } diff --git a/arch/arm/src/imx6/imx_serial.c b/arch/arm/src/imx6/imx_serial.c index cacf39a8dcd..e0f3d87b1ba 100644 --- a/arch/arm/src/imx6/imx_serial.c +++ b/arch/arm/src/imx6/imx_serial.c @@ -52,14 +52,14 @@ #include #include #include -#include #include "chip.h" #include "up_arch.h" #include "up_internal.h" -#include "imx_config.h" #include "chip/imx_uart.h" +#include "imx_config.h" +#include "imx_lowputc.h" #ifdef USE_SERIALDRIVER @@ -228,7 +228,7 @@ static void imx_shutdown(struct uart_dev_s *dev); static int imx_attach(struct uart_dev_s *dev); static void imx_detach(struct uart_dev_s *dev); -static int imx_interrupt(struct uart_dev_s *priv); +static int imx_interrupt(struct uart_dev_s *dev); #ifdef CONFIG_IMX6_UART1 static int imx_uart1_interrupt(int irq, void *context); #endif @@ -542,202 +542,30 @@ static int imx_setup(struct uart_dev_s *dev) { #ifndef CONFIG_SUPPRESS_UART_CONFIG struct imx_uart_s *priv = (struct imx_uart_s *)dev->priv; - uint32_t regval; - uint32_t ucr2; - uint32_t div; - uint32_t num; - uint32_t den; + struct uart_config_s config; + int ret; - /* Disable the UART */ + /* Configure the UART */ - imx_serialout(priv, UART_UCR1_OFFSET, 0); - imx_serialout(priv, UART_UCR2_OFFSET, 0); - imx_serialout(priv, UART_UCR3_OFFSET, 0); - imx_serialout(priv, UART_UCR4_OFFSET, 0); + config.baud = priv->baud; /* Configured baud */ + config.parity = priv->parity; /* 0=none, 1=odd, 2=even */ + config.bits = priv->bits; /* Number of bits (5-9) */ + config.stopbits2 = priv->stopbits2; /* true: Configure with 2 stop bits instead of 1 */ - /* Set up UCR2 */ - - ucr2 = imx_serialin(priv, UART_UCR2_OFFSET); - ucr2 |= (UART_UCR2_SRST | UART_UCR2_IRTS) - - /* Select the number of data bits */ - - DEBUGASSERT(priv->bits == 7 || priv->bits == 8); - if (priv->bits == 8) - { - ucr2 |= UART_UCR2_WS; - } - - /* Select the number of stop bits */ - - if (priv->stopbits2) - { - ucr2 |= UART_UCR2_STPB; - } - - /* Select even/odd parity */ - - if (priv->parity) - { - DEBUGASSERT(priv->parity == 1 || priv->parity == 2); - ucr2 |= UART_UCR2_PREN; - if (priv->parity == 1) - { - ucr2 |= UART_UCR2_PROE; - } - } - - /* Select RTS */ - -#if 0 - ucr2 &= ~UCR2_IRTS; - ucr2 |= UCR2_CTSC; -#endif - - /* Setup hardware flow control */ - - regval = 0; -#if 0 - if (priv->hwfc) - { - ucr2 |= UART_UCR2_IRTS; - - /* CTS controled by Rx FIFO */ - - ucr2 |= UART_UCR2_CTSC; - - /* Set CTS trigger level */ - - regval |= 30 << UART_UCR4_CTSTL_SHIFT; - } -#endif - - /* i.MX reference clock (PERCLK1) is configured for 16MHz */ - - imx_serialout(priv, UART_UCR4_OFFSET, regval | UART_UCR4_REF16); - - /* Setup the new UART configuration */ - - imx_serialout(priv, UART_UCR2_OFFSET, ucr2); - - /* Set the baud. - * - * baud * 16 / REFFREQ = NUM/DEN - * UBIR = NUM-1; - * UMBR = DEN-1 - * REFFREQ = PERCLK1 / DIV - * DIV = RFDIV[2:0] - * - * First, select a closest value we can for the divider - */ - - div = (BOARD_PERCLK1_FREQUENCY >> 4) / priv->baud; - if (div > 7) - { - div = 7; - } - else if (div < 1) - { - div = 1; - } - - /* Now find the numerator and denominator. These must have - * the ratio baud/(PERCLK / div / 16), but the values cannot - * exceed 16 bits - */ - - num = priv->baud; - den = (BOARD_PERCLK1_FREQUENCY << 4) / div; - - if (num > den) - { - if (num > 0x00010000) - { - /* b16 is a scale such that b16*num = 0x10000 * 2**16 */ - - uint32_t b16 = 0x100000000LL / num; - num = 0x00010000; - den = (b16 * den) >> 16; - } - } - else - { - if (den > 0x0000ffff) - { - /* b16 is a scale such that b16*den = 0x10000 * 2**16 */ - - uint32_t b16 = 0x100000000LL / den; - num = (b16 * num) >> 16; - den = 0x00010000; - } - } - - /* The actual values are we write to the registers need to be - * decremented by 1. - */ - - if (num > 0) - { - num--; - } - - if (den > 0) - { - den--; - } - - /* The UBIR must be set before the UBMR register */ - - imx_serialout(priv, UART_UBIR_OFFSET, num); - imx_serialout(priv, UART_UBMR_OFFSET, den); - - /* Fixup the divisor, the value in the UFCR regiser is - * - * 000 = Divide input clock by 6 - * 001 = Divide input clock by 5 - * 010 = Divide input clock by 4 - * 011 = Divide input clock by 3 - * 100 = Divide input clock by 2 - * 101 = Divide input clock by 1 - * 110 = Divide input clock by 7 - */ - - if (div == 7) - { - div = 6; - } - else - { - div = 6 - div; - } - - regval = div << UART_UFCR_RFDIV_SHIFT; - - /* Set the TX trigger level to interrupt when the TxFIFO has 2 or fewer - * characters. Set the RX trigger level to interrupt when the RxFIFO has - * 1 character. - */ - - regval |= ((2 << UART_UFCR_TXTL_SHIFT) | (1 << UART_UFCR_RXTL_SHIFT)); - imx_serialout(priv, UART_UFCR_OFFSET, regval); + ret = imx_uart_configure(priv->uartbase, &config); /* Initialize the UCR1 shadow register */ priv->ucr1 = imx_serialin(priv, UART_UCR1_OFFSET); - /* Enable the UART - * - * UART_UCR1_UARTCLEN = Enable UART clocking - */ + return ret; - ucr2 |= (UART_UCR2_TXEN | UART_UCR2_RXEN); - imx_serialout(priv, UART_UCR1_OFFSET, ucr2); - - priv->ucr1 |= UART_UCR1_UARTCLEN; - imx_serialout(priv, UART_UCR1_OFFSET, priv->ucr1); -#endif +#else + /* Initialize the UCR1 shadow register */ + priv->ucr1 = imx_serialin(priv, UART_UCR1_OFFSET); return OK; +#endif } /**************************************************************************** @@ -824,9 +652,9 @@ static void imx_detach(struct uart_dev_s *dev) * ****************************************************************************/ -static int imx_interrupt(struct uart_dev_s *priv) +static int imx_interrupt(struct uart_dev_s *dev) { - struct uart_dev_s *dev; + struct imx_uart_s *priv = (struct imx_uart_s *)dev->priv; uint32_t usr1; int passes = 0; @@ -1114,54 +942,13 @@ static bool imx_txempty(struct uart_dev_s *dev) void imx_earlyserialinit(void) { - /* Configure and disable the UART1 */ - -#ifdef CONFIG_IMX6_UART1 - imx_serialout(&g_uart1priv, UART_UCR1_OFFSET, 0); - imx_serialout(&g_uart1priv, UART_UCR2_OFFSET, 0); - - /* Configure UART1 pins: RXD, TXD, RTS, and CTS */ - - imxgpio_configpfoutput(GPIOC, 9); /* Port C, pin 9: CTS */ - imxgpio_configpfinput(GPIOC, 10); /* Port C, pin 10: RTS */ - imxgpio_configpfoutput(GPIOC, 11); /* Port C, pin 11: TXD */ - imxgpio_configpfinput(GPIOC, 12); /* Port C, pin 12: RXD */ -#endif - - /* Configure and disable the UART2 */ - -#ifdef CONFIG_IMX6_UART2 - imx_serialout(&g_uart2priv, UART_UCR1_OFFSET, 0); - imx_serialout(&g_uart2priv, UART_UCR2_OFFSET, 0); - - /* Configure UART2 pins: RXD, TXD, RTS, and CTS (only, also - * supports DTR, DCD, RI, and DSR -- not configured) + /* NOTE: This function assumes that low level hardware configuration + * -- including all clocking and pin configuration -- was perfomed by the + * function imx_lowsetup() earlier in the boot sequence. */ - imxgpio_configpfoutput(GPIOB, 28); /* Port B, pin 28: CTS */ - imxgpio_configpfinput(GPIOB, 29); /* Port B, pin 29: RTS */ - imxgpio_configpfoutput(GPIOB, 30); /* Port B, pin 30: TXD */ - imxgpio_configpfinput(GPIOB, 31); /* Port B, pin 31: RXD */ -#endif - - /* Configure and disable the UART3 */ - -#ifdef CONFIG_IMX6_UART3 - imx_serialout(&g_uart3priv, UART_UCR1_OFFSET, 0); - imx_serialout(&g_uart3priv, UART_UCR2_OFFSET, 0); - - /* Configure UART2 pins: RXD, TXD, RTS, and CTS (only, also - * supports DTR, DCD, RI, and DSR -- not configured) - */ - - imxgpio_configpfoutput(GPIOC, 28); /* Port C, pin 18: CTS */ - imxgpio_configpfinput(GPIOC, 29); /* Port C, pin 29: RTS */ - imxgpio_configpfoutput(GPIOC, 30); /* Port C, pin 30: TXD */ - imxgpio_configpfinput(GPIOC, 31); /* Port C, pin 31: RXD */ -#endif - - /* Then enable the console UART. The others will be initialized - * if and when they are opened. + /* Enable the console UART. The other UARTs will be initialized if and + * when they are first opened. */ #ifdef CONSOLE_DEV