From a5e64a0a5cf744ecaa3176946771e333dd5b3e1f Mon Sep 17 00:00:00 2001 From: ouyangxiangzhen Date: Thu, 20 Nov 2025 10:54:59 +0800 Subject: [PATCH] arch/riscv: Add CONFIG_ONESHOT condition for riscv_mtimer.c. This commit added CONFIG_ONESHOT condition for riscv_mtimer.c Signed-off-by: ouyangxiangzhen --- arch/risc-v/src/common/CMakeLists.txt | 6 +++++- arch/risc-v/src/common/Make.defs | 6 +++++- 2 files changed, 10 insertions(+), 2 deletions(-) diff --git a/arch/risc-v/src/common/CMakeLists.txt b/arch/risc-v/src/common/CMakeLists.txt index c4473a1366a..cb765c81fa8 100644 --- a/arch/risc-v/src/common/CMakeLists.txt +++ b/arch/risc-v/src/common/CMakeLists.txt @@ -29,12 +29,16 @@ list(APPEND SRCS riscv_cpuinfo.c riscv_createstack.c riscv_doirq.c riscv_exception.c) list(APPEND SRCS riscv_exit.c riscv_getintstack.c riscv_getnewintctx.c) list(APPEND SRCS riscv_initialize.c riscv_initialstate.c riscv_modifyreg32.c) -list(APPEND SRCS riscv_mtimer.c riscv_nputs.c riscv_registerdump.c) +list(APPEND SRCS riscv_nputs.c riscv_registerdump.c) list(APPEND SRCS riscv_releasestack.c riscv_schedulesigaction.c riscv_sigdeliver.c) list(APPEND SRCS riscv_stackframe.c riscv_tcbinfo.c riscv_swint.c) list(APPEND SRCS riscv_switchcontext.c riscv_usestack.c) +if(CONFIG_ONESHOT) + list(APPEND SRCS riscv_mtimer.c) +endif() + if(NOT CONFIG_ARCH_IDLE_CUSTOM) list(APPEND SRCS riscv_idle.c) endif() diff --git a/arch/risc-v/src/common/Make.defs b/arch/risc-v/src/common/Make.defs index 0e0ab36b1e9..d39d6a7a3c9 100644 --- a/arch/risc-v/src/common/Make.defs +++ b/arch/risc-v/src/common/Make.defs @@ -27,7 +27,7 @@ CMN_ASRCS += riscv_vectors.S riscv_exception_common.S CMN_ASRCS += riscv_saveusercontext.S # Specify C code within the common directory to be included -CMN_CSRCS += riscv_initialize.c riscv_swint.c riscv_mtimer.c +CMN_CSRCS += riscv_initialize.c riscv_swint.c CMN_CSRCS += riscv_allocateheap.c riscv_createstack.c riscv_cpuinfo.c CMN_CSRCS += riscv_cpuidlestack.c riscv_doirq.c riscv_exit.c riscv_exception.c CMN_CSRCS += riscv_getnewintctx.c riscv_getintstack.c riscv_initialstate.c @@ -36,6 +36,10 @@ CMN_CSRCS += riscv_registerdump.c riscv_stackframe.c riscv_schedulesigaction.c CMN_CSRCS += riscv_sigdeliver.c riscv_switchcontext.c CMN_CSRCS += riscv_usestack.c riscv_tcbinfo.c +ifeq ($(CONFIG_ONESHOT),y) + CMN_CSRCS += riscv_mtimer.c +endif + ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y) CMN_CSRCS += riscv_idle.c endif